JPH01109827A - Transmission data error correcting device - Google Patents

Abstract

PURPOSE:To complete the transmission of an error correction code and error correcting operation within a variable transmission frame period by adding the prescribed number of dummy data apparently, adding a coded bit, sending it, allowing the prescribed number of dummy data apparently to receive and using two sets of decoding sections to correct a variable length transmission data string. CONSTITUTION:A coding section 1 is reset just before the input of an information bit by an output of a coded reset pulse generating section 4 and a head 18 or 17th bit of an information bit receives a dummy bit 0 apparently. A reception section is provided with two sets of decoding sections X200, and Y201 and error correction is applied to each frame alternately. A decoding transmission frame counter 202 represents an address of a transmission data and a decoding control pulse generating section 203 receiving it generates various pulses. X, Y are reset just before the input of information bit to the X, Y an output of a decoding reset pulse generation section 204 to receive apparently the 17 or 18th dummy bit.

Description

[Detailed description of the invention] Industrial applications The present invention relates to an apparatus for correcting errors in transmitted data.

2. Description of the Related Art FIGS. 5 and 6 show a simple example of an error correction device for transmission data. FIG. 5 shows a transmitting section, and FIG. 6 shows a receiving section. The encoding unit l is an error correction encoding circuit using a Hamming (31, 26) code that performs error correction encoding by adding 5 bits to transmission information with a data length of 26 bits, and performs error correction of 1 bit. be. The data address counter 2 in FIG. 5 indicates the address of the transmitted data, and is reset at the beginning position of the transmitted data. Switch 10 in encoder l. The switch 11 is controlled by the control pulse generator 3 which receives the output AD of the counter 2, and the switch 11 is operated during the transmission period of 26 bits of transmission information (AD=0 to 25).
0 → A, switch 11 → ON, the transmission period of 5 error correction encoded bits (AD = 26 to 30) is switch 1.
O-ThB, switch 1l-OFF, respectively. The receiving section in FIG. 6 is an error correction decoding circuit, and when an error occurs in the input data, ER="1" is set.
The error bits in the data are inverted and corrected. Note that the transmission data input manually to the error correction decoding circuit is output with a delay of 32 bits.

The above Hamming (at b) error correction code (a: total transmission bit length, b: information bit length) is
(2n-1, 2n-1-n) (n: integer ≧2
), and therefore, the error correcting code can be applied in just the right amount only when the transmission information length is 2n1-n bits. If the transmission information length is other than the above bit length, n such that b>2n-1-n is selected and partial error correction is performed.

Problems to be Solved by the Invention An error correction device using such a Hammin g (a + b) error correction code is applied to a transmission device that assembles frames with a variable frame length F and sends variable length transmission data f bits. In doing so, the following problems arise. First, the minimum length f man of variable length transmission data f
If b < f sin is set for , error correction can be applied to only a portion of the transmitted data as described above. Second, when setting b>f, , for the maximum length f□8 of transmission data f, the minimum b−f, ,
Bit dummy data must be sent and corrected. However, when an error correction code sequence is selected as much as possible such that b>f08, as mentioned above, Hamming (
at b) The error correction code is 2n-1 (=3.7.
15. ---) To be configured, especially f. The larger X is, the longer Ha is extremely excessive compared to the transmission data length.
There may be times when it is necessary to form an mming code. As a result, if the Hamming code length a exceeds the variable length frame length F, the transmission of the error correction code and the error correction operation cannot be completed within the variable length frame period F, and in effect, b>f□8 Naru Hammi
ng (a, b) Application of error correction code becomes impossible.

In order to solve the above-mentioned problems, the present invention applies a Hamming (a+b) error correction code such that b>f, . The present invention provides a transmission data error correction device that enables transmission of an error correction code and error correction operation to be completed within a variable length transmission frame period F.

Means for Solving the Problems The present invention provides Hammi
ng error correction code, by resetting the encoding unit at a predetermined timing by the encoding reset pulse generating unit, a predetermined number of dummy data is apparently added, and then the encoding unit performs the encoding. The receiving section resets the decoding section at a predetermined timing by generating a decoding reset pulse, thereby apparently receiving a predetermined number of dummy data, and the two sets of decoding sections perform the error correction encoding. Correct the variable length transmission data string. However, variable length frames (frame length F, frame pattern length ρ, transmission data length f: minimum f□. to maximum fmax), and Harnming (2n-1, 2n
-1-n) f, t, +fρ>2n-1-2n for the encoding/decoding unit using an error correction code.

Effect: The above configuration makes it possible to perform error correction on all bits of a variable-length transmission data string, and to complete transmission of an error correction code and error correction operation within a variable transmission frame period.

Embodiment The structure of an embodiment of a transmission data error correction apparatus according to the present invention is shown in conjunction with FIGS. 1 to 3. FIG. FIG. 4 shows a frame structure of transmission data and a timing chart of main pulses of each part.

From now on, each operation of this device will be performed according to each waveform ■~[phase](
Hereinafter, they will be explained in correspondence with ■■～■[phase]).

This frame structure is for a high-efficiency encoding transmission device for NTSC video signals, and has a data rate of 32.064 Mb.
/s, frame period average 15.75kHz (N
TSC horizontal sync frequency). Therefore, the total number of data in one frame is 2037.8 bits. Therefore, the standard frame is set to 2037 bits, and the average of 8 out of 10 frames is 2037 bits.
A 2038-bit frame, which is obtained by adding l-bit stuffing to the frame, is introduced, and a variable length data string (frame) is used to achieve this. The frame structure is as shown in ■■, where the first 8 bits are applied to the frame pattern,
The remaining 2018 or 2019 bits are information bits, and the remaining 11 bits are error correction coded bits. Error correction is performed only on transmission information bits, not on frame patterns. This is to avoid the possibility that if an error of two or more bits occurs in the information bits during transmission, the error correction operation will be performed inaccurately, causing the error to spread to the frame pattern, resulting in loss of synchronization. Furthermore, error correction decoding is not performed on the error correction coded bits in the receiving section since these bits do not have information as transmission data.

The information bits of Hamming's error correction code string are 2
n-1-n (=3. 7.・Fist・・Fist,
1023. 2047.4095. ...
), so when performing error correction on all information bits of 2018 or 2019, (2047, 20
36) It is necessary to use a code. FIG. 1(a) shows the transmitter, and the encoder l basically consists of Hamming (204
7°2036) This is an error correction encoding circuit. The encoded transmission frame counter 2 receives the transmission data address AD (V
[■)]. In response to this output AD, the encoding control pulse generator 3 switches the switch 10.1 of the encoder l.
Generate pulses ■■ and ■■ that control 1. During the frame pattern period (AD=0 to 7), the switch 10 is switched to A, and data is output without being encoded. The encoder 1 is reset by the output CL of the encoder reset pulse generator 4 immediately before the information bit input, thereby resetting the first 18 or 17 bits of the information bit) (
2036-2018 or 2019 bits), it can be assumed that dummy bit O is apparently sent. During the transmission data period (AD=8 to 2025 or 2026), the switch 10→A and the switch 11→ON are switched, and error correction encoding is performed along with data transmission. A.D.
-'' During the period 2026-2036 or 2027-2037, the switch 104B switches from switch 11 to OFF and sends out 11 error correction coded bits.

FIG. 2 is a detailed diagram of the receiving section, and FIG. 3 is a detailed diagram of the decoding section in FIG. (2047, 2036) 20 to perform error correction
48 clock leaps are required, so as in this example, 2 clock leaps are required.
When one frame is made up of 037 or 2038 bits, a normal set of error correction circuits cannot perform the correction operation in real time. Therefore, here, 2M decoding units x200 and Y2O1 are provided, each of which performs an error correction operation alternately every l frame. The decoded transmission frame counter 202 indicates the address of the transmission data,
In response to this, the decoding control pulse generator 203 generates various pulses. The frame pattern of the first 8 bits is
The data is input to RAMll0 by the BF through the AND gate 104, and is output after 2048 clock hours without being subjected to any correction or decoding operations. Transmission data is ■■SR, VI■S
The decoding unit X200 . It will be distributed to Y2O1. Output VIeCL X, VT ([DCL Y Niyotte,
X.

Immediately before manually inputting the information bit to Y, reset X and Y, thereby assuming that the 17 or 18-bit dummy bit is apparently received as the main reception, and ■@ZX, Vl@ZY
1. : AND game) Open 103 and input 2029 or 2030 bits of information bits and error correction coded bits to X and Y. RAMll0 receives the address of the free-running 2048 counter 205 and functions as a 2048 latch. X.

The transmission data each subjected to error correction in Y is 2048
After a clock time delay, the signals are synthesized and output at the OR gate 213 (■o).

Effects of the Invention As described above, according to the present invention, error correction is performed on all bits of a variable length transmission data string having a variable length frame, and error correction code transmission and error correction operations are performed within a frame period. It is possible to complete it.

[Brief explanation of the drawing]

1 and 2 are block diagrams of a transmitting and receiving unit of a transmission data error correction device according to an embodiment of the present invention, FIG. 3 is a block diagram of a decoding unit in the same device, and FIG. 4 is an explanation of the operation of the device. FIGS. 5 and 6 are configuration diagrams of a transmitting and receiving section of a conventional transmission data error correction apparatus. DESCRIPTION OF SYMBOLS 1... Encoding part, 2... Encoding transmission frame counter, 3... Encoding control pulse generation part, 4... Encoding reset pulse generation part, 10... 2 selection switch, II
...Open/close switch, 12,13...EOR gate,
14-25...Latch, 100-102...E
OR gate, 103. 104...AND gate, 105---11 manual NOR gate, 106-
--OR gate, 107...inverter, 108
．． 109 race...I10 bus, 110...RAM,
111-123...Latch, 200,201...
Decoding unit, 202...Decoding transmission frame counter, 20
3...Decoding control pulse generation section, 204...Decoding reset pulse generation section, 205...Φ2048 free-running counter, 206...2047'' decoder, 207...NO
R gate, 208.209,213-...OR gate,
210...Inverter, 211, 212...AND
Gate. Name of agent: Patent attorney Toshio Nakao Haka 1 person 10-2 selection Suitsuna 1st drawing 100-702-E OR Tate 10I3-OR Kate 101-11 Inverda t08.109-r10 Buzz 111~IF!3 =-5 4- Figure 3 Compensation Te Part Figure 4

Claims (2)

[Claims] (1) A code that applies Hamming error correction encoding to a transmission data string sent out in a variable length frame (frame length F), which can correct errors in a data string longer than the transmission data length. a code that generates a pulse that resets the encoding unit at a predetermined timing in order to apparently transmit a number of dummy data necessary for the transmission data length to constitute the Hamming error correction code; a transmitting unit including an encoding reset pulse generating unit, an encoding control pulse generating unit that controls the encoding unit, and an encoded transmission frame counter that counts the transmitted data; and the error correction encoded variable length transmission. two sets of decoding units that receive and correct a data string; a decoding unit reset pulse generating unit that generates a pulse to reset the decoding unit at a predetermined timing in order to apparently receive the dummy data; and the decoding unit 1. A transmission data error correction device comprising: a decoding unit control pulse generating unit for controlling the received data; and a receiving unit comprising a decoding unit transmission frame counter for counting the received data. (2) Variable length frame (frame length F, frame pattern length f_P, transmission data length f; minimum f_m_i_n to maximum f_m_a_x), and Hamming (2^n-1
, 2^n-1-n) f_m_i_n+f_P>2^n-1-2n for the encoding/decoding unit using the error correction code.
A transmission data error correction device according to claim 1, characterized in that: