KR100244897B1 - Run, amp generator - Google Patents

Abstract

The present invention relates to a RUN and AMP generating device, comprising: a RUN counter that counts zeros from an AC coefficient, a first RUN and AMP generator generated by the RUN counter, and a first RUN and AMP generating device; 1 RUN AMP register, a second RUN AMP register, a LOC for checking whether or not a codeword exists through the first RUN, AMP generator, and generating a new RUN, AMP in the LOC (RUN-1, 0) It includes a generator, a controller (0, AMP), and a controller that handles control signals of the RUN counter, the first RUN AMP register, and the second RUN AMP register, thereby simplifying hardware and solving time delays.

Description

RUN, AMP generator

1 is a block diagram showing conventional RUN and AMP processes.

2 is a block diagram showing the RUN, AMP according to the present invention

3 is a waveform diagram showing the RUN, AMP output waveform according to the present invention

Table 1, Codeword length table corresponding to RUN and AMP

Codeword Table corresponding to Table 2, RUN, AMP

* Explanation of symbols for main parts of the drawings

1: Quantizer 2: RUN, AMP Generator

3: buffer 4: variable length coder

5: RUN counter 6: 1st RUN, AMP generator

7: LOC 8: 1st RUN, AMP register

9: 2nd RUN, AMP register 10: (RUN-1, 0) generator

11: (0, AMP) generator 12: controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a run, an amplifier (RUN, AMP) generating apparatus, and more particularly, a run for variable-length encoding for simplifying a hardware configuration by processing RUN and AMP processed by a variable-length encoder in order of output; It relates to an amplifier (RUN, AMP) generator.

In general, ACT values of DCT through quantizer in video signal processing of digital VCR have a value between " 1-255 " and not " 0 " and " 0 " in order of low frequency to high frequency. Dimensions are rearranged. The DC coefficient is fixed to 9 bits, and the AC coefficient is RUN and AMP generated when variable length length coding is performed depending on the number of consecutive RUNs " 0 " followed by the magnitude of the AC coefficient (AMP). Therefore, it may not be able to encode. At this time, the RUN and AMP which cannot be encoded are converted into new RUN and AMP of (RUN-1, 0) and (0, AMP) which can be encoded according to the definition in the recommendation of the digital VCR, and are used for encoding.

1 is a block diagram showing a conventional RUN and AMP process. The RUN and AMP generators 2 and the variable length are passed through a quantizer 1 in which an analog signal is converted into a digital signal by displaying one representative value in an amplitude range. A buffer is provided between these encoders to store RUNs and AMPs generated per segment, and then call them according to the processing conditions of the variable length encoder 4 to process them. The quantizer 1 continuously generates data according to a clock. If the next RUN and AMP come in immediately after the RUN and AMP to be converted are processed in two, the data to be processed is not processed. The data is pushed back and cannot be processed in real time. Here data refers to RUN and AMP.

After it is confirmed that the codeword does not exist, it is necessary to prevent the next RUN and AMP from being input to the variable length coder while generating and processing new (RUN-1, 0) and (0, AMP) again. do. However, since the quantizer cannot know in advance that the result of the quantization is RUN or AMP without a codeword, the quantizer continuously outputs quantized AC coefficients. In order to prevent such continuous processing, it is necessary to memorize RUN and AMP corresponding to one segment and process the first data when RUN and AMP of the next segment come in. For the above process, the buffer needs to use a ping-pong structure, control logic, and hardware burden. In addition, there is a problem in that a delay occurs per segment when using the buffer as a ping-pong structure.

The present invention solves the problem of time delay and hardware by using a register and a control logic to control the data well without using a memory that acts as a buffer to solve the above problems without using time delay. It aims to solve.

The present invention provides a RUN counter that counts 0 from an AC coefficient to achieve the above object, a first RUN and AMP generator generated by the RUN counter, and a first RUN AMP to store the first RUN and AMP generator values. Register, second RUN AMP register, LOC to check whether or not a codeword exists through the first RUN, AMP generator, (RUN-1, 0) generator for generating new RUN, AMP in the LOC, ( 0, AMP) generator, and a controller for handling the control signals of the RUN counter, the first RUN AMP register, the second RUN AMP register.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a block diagram showing RUN and AMP according to the present invention, a RUN counter for counting " 0 ", a first RUN and AMP generator for generating primary RUN and AMP by the RUN counter, There is a LOC (7) for checking whether a codeword exists through RUN and AMP, a first RUN AMP register (8) and a second RUN AMP register (9) for storing the RUN and AMP, and a new RUN and AMP generator. It consists of a (RUN-1, 0) generator 10 and a (0, AMP) generator 11 and a controller 12 which handles control signals.

Variable-length-length coding is an operation of converting AC coefficients through a quantizer into variable length codes as shown in Table 2. The variable-length codewords are determined according to the inputs of RUN and AMP. The quantized AC coefficients are quantized by " 0 " or " Converted to an absolute value other than; 0 ". First, the coefficients are input to the RUN counter to count the number of consecutive AC coefficients quantized by " 0 ". At this time, if an absolute AC coefficient value other than " 0 " is input, the count value of " 0 " so far is output and the count value becomes a RUN value. On the other hand, the output value of the AC coefficient from the quantization is input not only to the RUN counter 5 but also to the first RUN and AMP generators 6 simultaneously. Therefore, when a count value other than " 0 " enters the RUN counter 5, the value of counting " 0 " and the absolute value of the following counting count are added to the output of the first RUN and AMP generator 6. The first RUN and AMP values are input to a variable length coder to output a variable length code. As shown in Table 2, since there are RUN and AMP values without a variable length code, as defined in the DVCR recommendation ( RUN-1, 0) and (0, AMP) are divided into two types of RUN and AMP, which are sequentially used for variable length coders. At this time, if a count value other than " 0 " enters the RUN counter 5, the value of counting " 0 " and the absolute value of the following counting count are added to the output of the first RUN and AMP generator 6. Accordingly, the RUN and AMP generated in the primary RUN and AMP generators are the registers of the first RUN and AMP registers (8) and the second RUN and AMP registers (9) and the secondary RUN and AMP generators (RUN-1 and 0). It is simultaneously input to the generators 10 and (0, AMP) generators. It is also input to the LOC 7 which is a checker of codewords corresponding to RUN and AMP. It is checked whether the primary RUN and the AMP input to the LOC 7 have a codeword or not. If the code word is RUN or AMP, the LOC 7 sends a signal to the control unit to generate an input enable signal of the first RUN, AMP register or the second RUN, AMP register and is inputted to the output. It waits for the signal and when it is output sequence, it is output by the output enable signal. If the codeword does not exist RUN, AMP LOC (7) is converted to (RUN-1, 0) generator and (0, AMP) generator secondary RUN, AMP. The values are output in the order of (RUN-1, 0) and (0, AMP) by the output application signal when the output signal waits for the output signal.

3 is a waveform diagram showing the RUN and AMP output waveforms according to the present invention, wherein the AC coefficient through the quantizer is " 0, 0, 47, 0, 38, 19, 18, 17, 0, 25, 41, 0, When the values are equal to 0, 16, 9, 0, 30 ", the values are input to the RUN counter 5 according to the clock. If the input value is " 0 ", the signal 3 becomes high. The RUN counter 5 has " 0 " when the signal 3 is low. Keep the value and if it is high, count by " 1 " by " 0, 1, 2, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 2, 0, 0, 1, 0 " Output the same value as; The signal 4 is also input to the primary RUN and AMP generators. If the signal is low, the signal 4 outputs the AC coefficient output from the quantizer at that moment and the output of the RUN counter. The output value is " (2, 47), (1, 38), (0, 19), (0, 18), (0, 17), (0, 17), (1, 25), (0, 41), (0, 41), (0, 41), (2, 16), (0, 9), (0, 9), ((1, 30)) " The above values are primary RUN and AMP values The values are inputted to the LOC 7 to output the signal 6 high if there is no codeword and to LOW, and low if the codeword is present, and to output the result of the primary RUN and AMP. &Quot; (2, 47), (1, 38), (1, 25), 2, 16), (1, 30) " These codewords are RUN and AMP which do not exist. This requires a second RUN, AMP, as defined in the DVCR. In the part where the output signal 6 of the LOC 7 is high, the primary RUN and AMP can be input to the (RUN-1, 0) generator and the (0, AMP) generator, and are converted into two new RUN and AMP, respectively. do. (2, 47) is (1, 0) and (0, 47), (1, 38) is (0, 0) and (0, 38), and (1, 25) is (0, 0) and (0, 25), (2, 16) are converted to (1, 0) and (0, 16), and (1, 30) is converted to (0, 0) and (0, 30). The (0, 18), (0, 18), (0, 17), (0, 41), and (0, 9) values generated between them are output in order by the control signal. The signals are secondary RUN and AMP output enable signals. The above (1, 0) is output first, and (0, 47) is output later. Of the above output values, RUN and AMP outputs (1, 38), (0, 19), and (0, 18) are continuously entered every one clock. However, (1, 38) is divided into two RUNs and AMPs (0, 0) and (0, 38) because they are RUNs and AMPs without code words. If you try to process (0, 38) after processing (0, 0), then the inputs (0, 19), which are RUN and AMP, are duplicated. Therefore, immediately following (0, 19) is input to the first RUN, AMP register without processing. The next input (0, 18) then outputs (0, 18) to the second RUN, AMP register. In this way, it can be output without overlapping each other under any remaining input situation. The values may be sequentially input to the variable length coder. The output enable signals 9, 10, 13 and 14 here are generated in sequence by the controller.

The present invention can simplify the hardware and solve the time delay.

Claims (3)

RUN counter that counts 0 from AC coefficient, A first RUN and AMP generator generated by the RUN counter, A first RUN AMP register and a second RUN AMP register for storing the first RUN and AMP generator values; A LOC for checking whether a codeword exists through the first RUN and AMP generators; (RUN-1, 0) generator, (0, AMP) generator to generate new RUN, AMP in the LOC, Run, amplifier (RUN, AMP) generating device comprising a controller for handling the control signals of the RUN counter, the first RUN AMP register, the second RUN AMP register The method of claim 1, The first RUN AMP register and the second RUN AMP register is a run, amplifier (RUN, AMP) generator, characterized in that the code word is present. The method of claim 1, The (RUN-1, 0) generator, the (0, AMP) generator is a run, amplifier (RUN, AMP) generator, characterized in that the code word does not exist. TABLE 1 TABLE 2