JPH01109747A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01109747A JPH01109747A JP26843787A JP26843787A JPH01109747A JP H01109747 A JPH01109747 A JP H01109747A JP 26843787 A JP26843787 A JP 26843787A JP 26843787 A JP26843787 A JP 26843787A JP H01109747 A JPH01109747 A JP H01109747A
- Authority
- JP
- Japan
- Prior art keywords
- wiring metal
- metal pattern
- insulating film
- semiconductor substrate
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims 1
- 238000002161 passivation Methods 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 238000004299 exfoliation Methods 0.000 abstract 2
- 239000010408 film Substances 0.000 description 19
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000010409 thin film Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、半導体装置に係り、特にポンディングパッ
ド部を構成する配線金属パターンの構造に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to the structure of a wiring metal pattern constituting a bonding pad portion.
第２図は従来の半導体装置のポンディングパッド部の断
面図である。なお、この図では、例えばＦＥＴのゲート
やソース部は表示されていない。FIG. 2 is a sectional view of a bonding pad portion of a conventional semiconductor device. Note that, in this figure, for example, the gate and source portion of the FET are not shown.
第２図において、１は半導体基板、２は例えばＦＥＴの
ゲートやソースにつながる第１の配線金属パターン、３
は半導体素子の表面保護を目的としたパシベーション膜
、４は外部リード線に接続するための第２の配線金属パ
ターンである。In FIG. 2, 1 is a semiconductor substrate, 2 is a first wiring metal pattern connected to, for example, the gate or source of an FET, and 3 is a semiconductor substrate.
4 is a passivation film for the purpose of protecting the surface of the semiconductor element, and 4 is a second wiring metal pattern for connection to an external lead wire.
次に、製造方法についてＧａＡｓＭＥＳＦＥＴを想定し
て説明する。Next, a manufacturing method will be described assuming a GaAs MESFET.
まず、能動層を有するＧａＡｓからなる半導体基板１上
にソース、ドレイン、ゲートを形成する。この３つの電
極はいずれも外部接続のために半導体基板１上を延伸し
、第１の配線金属パターン２となる。First, a source, a drain, and a gate are formed on a semiconductor substrate 1 made of GaAs and having an active layer. These three electrodes all extend on the semiconductor substrate 1 for external connection and become the first wiring metal pattern 2.
次に、表面保護のため半導体基板１の表面全体にシリコ
ン酸化膜などによるパシベーション膜３をＣＶＤ法等に
より被着させる。つづいて写真製版技術を用いて第１の
配線金属パターン２の所望の位置に開孔部を形成する。Next, for surface protection, a passivation film 3 made of a silicon oxide film or the like is deposited over the entire surface of the semiconductor substrate 1 by CVD or the like. Subsequently, openings are formed at desired positions in the first wiring metal pattern 2 using photolithography.
この時、第１の配線金属パターン２の材料は、ソース、
ドレインに継がるものならば、Ｔ ｉ ／ Ｎ ｉ ／
Ａ ｕ 、ゲートに継がるものならばＴ ｉ ／ Ｐ
ｔ ／ Ａ ｕまたはＴｉ／Ａｊ２等であり、また、
微細パターンを形成する必要性から金属厚は厚くするこ
とができない。At this time, the material of the first wiring metal pattern 2 is source,
If it is connected to the drain, T i / N i /
A u , if it is connected to the gate, T i / P
t/A u or Ti/Aj2, etc., and
The metal thickness cannot be increased due to the necessity of forming fine patterns.
したがって、この第１の配線金属パターン２に直接金線
等のワイヤボンドは困難であり、その表面にざらにＡｕ
等の厚い第２の配線金属パターン４を重ねる必要がある
。Therefore, it is difficult to bond wires such as gold wires directly to this first wiring metal pattern 2, and it is difficult to bond wires such as gold wires directly to this first wiring metal pattern 2.
It is necessary to overlap a thick second wiring metal pattern 4 such as the above.
すなわち、開孔部を覆うように、第２の配線金属パター
ン４を蒸着、リフトオフまたは蒸着、工゛ ツチング
またはメツキ法によって形成する。That is, the second wiring metal pattern 4 is formed by vapor deposition, lift-off, vapor deposition, etching, or plating so as to cover the opening.
従来の技術によるポンディングパッド部は以上のように
構成されているので、ポンデイ、ングパッド部の周辺で
は、金属／絶縁膜／金属の３層構造となってしまう。こ
のような構造の場合、各層を構成する薄膜自身の内部応
力、互いの付着力の弱さ等により第２図中にＸ印で示し
た位置で剥離が発生しやすいという欠点があった。Since the conventional bonding pad section is constructed as described above, the area around the bonding pad section has a three-layer structure of metal/insulating film/metal. In the case of such a structure, there is a drawback that peeling is likely to occur at the position indicated by the X mark in FIG. 2 due to the internal stress of the thin films constituting each layer and the weak adhesion between them.
この発明は、かかる欠点を除去し、信頼性の高い半導体
装置を得ることを目的としている。The present invention aims to eliminate such drawbacks and obtain a highly reliable semiconductor device.
この発明にかかる半導体装置は、半導体基板の主表面に
第１の配線金属パターンを形成し、この第１の配線金属
パターンの周辺を覆うように絶縁膜を形成し、この絶縁
膜に形成された開孔部の内側の前記第１の配線金属パタ
ーン上に第２の配線金属パターンを形成したものである
。In the semiconductor device according to the present invention, a first wiring metal pattern is formed on the main surface of a semiconductor substrate, an insulating film is formed to cover the periphery of the first wiring metal pattern, and an insulating film formed on the insulating film is provided. A second wiring metal pattern is formed on the first wiring metal pattern inside the opening.
この発明においては、第１の配線金属パターンに上に第
２の配線金属パターンが形成されて構成されたポンディ
ングパッド部には金属／絶縁膜／金属となる層構造は存
在しないので、薄膜自身の内部応力や、薄膜相互の付着
力の弱さ等による剥離の発生は防止される。In this invention, since there is no layer structure of metal/insulating film/metal in the bonding pad portion formed by forming the second wiring metal pattern on the first wiring metal pattern, the thin film itself does not have a metal/insulating film/metal layer structure. The occurrence of peeling due to internal stress or weak adhesion between thin films is prevented.
（実施例〕 以下、この発明の一実施例を第１図に従って説明する。(Example〕 An embodiment of the present invention will be described below with reference to FIG.
第１図において、１〜４は第２図と同じものを示すが、
この実施例における第２の配線金属パターン４は、パシ
ベーション膜３の開孔部の内側に形成されている。In Figure 1, 1 to 4 indicate the same things as in Figure 2, but
The second wiring metal pattern 4 in this embodiment is formed inside the opening of the passivation film 3.
次に、第１図の半導体装置の製造方法について説明する
。Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described.
まず、能動層を有する半導体基板１上にソース、ドレイ
ン、ゲートを形成し、それぞれにつながる第１の配線金
属パターン２を形成する。First, a source, a drain, and a gate are formed on a semiconductor substrate 1 having an active layer, and a first wiring metal pattern 2 connected to each is formed.
次に、表面保護のため、半導体基板１の表面にシリコン
酸化膜等の絶縁膜よるパシベーション膜３をＣＶＤ法等
により被着させる。つづいて写真製版技術を用いて第１
の配線金属パターン２の所望の位置に開孔部を形成する
。最後に、開孔部の内側の第１の配線金属パターン２の
上に蒸着、リストオフまたはメツキ法によって第２の配
線金属パターン４を形成する。Next, for surface protection, a passivation film 3 made of an insulating film such as a silicon oxide film is deposited on the surface of the semiconductor substrate 1 by CVD or the like. Next, using photolithography technology, the first
An opening is formed at a desired position in the wiring metal pattern 2. Finally, a second wiring metal pattern 4 is formed on the first wiring metal pattern 2 inside the opening by vapor deposition, list-off, or plating.
第１図から明らかなように、この発明では、第１の配線
金属パターン２の表面が一部露出する。As is clear from FIG. 1, in the present invention, a portion of the surface of the first wiring metal pattern 2 is exposed.
そのため素子の長期にわたる信頼性の点で問題となる可
能性がある。しかし、この点は半導体基板として化合物
半導体を用い、かつ、金属材料が金を主材としてあれば
問題とならない。シリコン半導体を用いた場合には、Ａ
ｕ２．系の材料が使われるが、この場合は第２の配線金
属パターン４のさらに表面にパシベーション膜３を被着
すれば信頼性は確保される。This may pose a problem in terms of long-term reliability of the device. However, this will not be a problem if a compound semiconductor is used as the semiconductor substrate and the metal material is mainly gold. When using a silicon semiconductor, A
u2. In this case, reliability can be ensured by depositing a passivation film 3 on the surface of the second wiring metal pattern 4.
なお、上記実施例ではＧａＡｓＭＥＳＦＥＴについて説
明したが、これはＧａＡｓ集積回路、シリコン集積回路
であってもよく上記実施例と同様の効果を奏する。In the above embodiment, a GaAs MESFET has been described, but it may be a GaAs integrated circuit or a silicon integrated circuit, and the same effects as in the above embodiment can be obtained.
（発明の効果ン
以上説明したように、この発明は、半導体基板の主表面
に形成された第１の配線金属パターンと、この第１の配
線金属パターンの周辺を覆うように形成された絶縁膜と
、この絶縁膜の開孔部の内側の第１の配線金属パターン
上に形成された第２の配線金属パターンとを備えたので
、金属／絶縁膜／金属となる層構造がなくなり、したが
って、絶縁膜の剥離は発生せず、信頼性の高い半導体装
置が得られる効果がある。(Effects of the Invention) As explained above, the present invention includes a first wiring metal pattern formed on the main surface of a semiconductor substrate, and an insulating film formed to cover the periphery of the first wiring metal pattern. and a second wiring metal pattern formed on the first wiring metal pattern inside the opening of the insulating film, there is no layer structure of metal/insulating film/metal, and therefore, This has the effect that peeling of the insulating film does not occur and a highly reliable semiconductor device can be obtained.
第１図はこの発明の一実施例を示す半導体装置のポンデ
ィングパッド部の断面図、第２図は従来の半導体装置の
ポンディングパッド部の断面図である。
図において、１は半導体基板、２は第１の配線金属パタ
ーン、３はパシベーション膜、４は第２の配線金属パタ
ーンである。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第１図
第２図
手続補正書（自発）
１、事件の表示 特願昭６２−２６８４３７号
／／
２、発明の名称 半導体装置
３、補正をする者
代表者志岐守哉
４、代理人
ｉ、補正の対象
明細書の発明の詳細な説明
ｉ、補正の内容
明細書第３頁７行の「継がるものならば、Ｔ ｉ’Ｎｉ
／Ａｕ、Ｊを、「継がるものならばＡｕＧｅ’Ｎｉ／Ａ
ｕ、Ｊと補正する。
以 上FIG. 1 is a sectional view of a bonding pad portion of a semiconductor device showing an embodiment of the present invention, and FIG. 2 is a sectional view of a bonding pad portion of a conventional semiconductor device. In the figure, 1 is a semiconductor substrate, 2 is a first wiring metal pattern, 3 is a passivation film, and 4 is a second wiring metal pattern. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) Figure 1 Figure 2 Procedural amendment (voluntary) 1. Indication of the case Japanese Patent Application No. 1983-268437
// 2. Title of the invention: Semiconductor device 3, Representative of the person making the amendment: Moriya Shiki 4, Agent i, Detailed explanation of the invention in the specification to be amended, i, Page 3, line 7 of the specification of the contents of the amendment. "If it's something that will be inherited, T i'Ni
/Au, J, ``If it's something that will be inherited, then AuGe'Ni/A
Correct as u and J. that's all
Claims (4)
パターンと、この第１の配線金属パターンの周辺を覆う
ように形成された絶縁膜と、前記第１の配線金属パター
ン上の前記絶縁膜に形成された開孔部の内側に形成され
た第２の配線金属パターンとを備えたことを特徴とする
半導体装置。(1) A first wiring metal pattern formed on the main surface of a semiconductor substrate, an insulating film formed to cover the periphery of the first wiring metal pattern, and the first wiring metal pattern formed on the first wiring metal pattern. A semiconductor device comprising: a second wiring metal pattern formed inside an opening formed in an insulating film.
特徴とする特許請求の範囲第（１）項記載の半導体装置
。(2) The semiconductor device according to claim (1), wherein the semiconductor substrate is made of a compound semiconductor.
単層金属で構成されたことを特徴とする特許請求の範囲
第（１）項記載の半導体装置。(3) The semiconductor device according to claim (1), wherein the first and second wiring metal patterns are made of a single layer metal containing gold.
多層金属で構成されたことを特徴とする特許請求の範囲
第（１）項記載の半導体装置。(4) The semiconductor device according to claim (1), wherein the first and second wiring metal patterns are made of multilayer metal containing gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26843787A JPH01109747A (en) | 1987-10-22 | 1987-10-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26843787A JPH01109747A (en) | 1987-10-22 | 1987-10-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01109747A true JPH01109747A (en) | 1989-04-26 |
Family
ID=17458482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26843787A Pending JPH01109747A (en) | 1987-10-22 | 1987-10-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01109747A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006351767A (en) * | 2005-06-15 | 2006-12-28 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP2014145973A (en) * | 2013-01-30 | 2014-08-14 | Japan Oclaro Inc | Semiconductor optical modulator and optical communication module |
-
1987
- 1987-10-22 JP JP26843787A patent/JPH01109747A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006351767A (en) * | 2005-06-15 | 2006-12-28 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP2014145973A (en) * | 2013-01-30 | 2014-08-14 | Japan Oclaro Inc | Semiconductor optical modulator and optical communication module |
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