JPH01108646A - Template matching circuit - Google Patents

Abstract

PURPOSE:To accelerate template matching by setting the execution time of a pipeline processing at each stage less than a transmission delay time per stage of data transmission path. CONSTITUTION:In a memory access control circuit 7, only one of memory access parts in memory readout parts 2A and 2B and memory write parts 5A and 5B is permitted to make access to a memory by a memory access permission signal. The permission of memory access is issued preferentially to the memory access part 2A, 2B, 5A, or 5B generating the memory access, and when plural number of memory access are superposed, priority is attached on the memory access part 2A, 2B, 5A, or 5B from which the request of the memory access is issued earlier. Thus, by controlling the data transmission path by a memory access permission signal for the request of the memory access in the period of memory access, which makes the memory access by another data wait. In such a way, it is possible to evade the simultaneous memory access by plural data.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a circuit that performs template matching using a memory.

<Conventional Technology> Conventionally, when matching memory is accessed using data continuously input from a single human-powered boat, pipeline processing is performed to access the memory densely and increase the processing capacity of the system.

<Problems to be Solved by the Invention> Even when memory is accessed by pipeline processing, there is a limit to how dense the access can be, and the processing capacity of the matching memory section determines the processing capacity of the entire system. The present invention aims to solve the above-mentioned problems and realize high-speed template matching.

<Means to Solve the Problem> In the present invention, the data transmission path is divided into pipeline stages, and the data transmitted through the data transmission path is read from the matching memory, and the read data and the input data are matched. Comparison of data, processing of each data based on the comparison results, and writing of data to the matching memory are configured to be executed in order at each pipeline stage, and furthermore, the processing required for the processing executed at each pipeline stage is The time is set to be equal to or less than the transmission delay time per stage of the data transmission line, and the input data of the data transmission line is processed through the data transmission line of the number of stages necessary for the processing. A memory access control circuit orders memory access requests for a single matching memory generated from data input in parallel to at least one data transmission line that performs the above-mentioned no-blind processing, and prevents multiple memory accesses from occurring at the same time. control so that it does not occur.

<Function> By keeping the execution time of the pipeline processing at each stage within the transmission delay time per stage of the data transmission path,
As long as memory accesses do not overlap, data transmission will not be disrupted, and data can be input from the input port at time intervals determined by the data transmission path's capacity.Even if memory accesses overlap, the data transmission path is controlled by the memory access control circuit. , the memory access being executed is delayed until the memory access is completed, so that no inconsistency occurs in the processing.

By inputting data requiring memory access in parallel, memory access can be made more dense than in the conventional method of accessing memory using data from a single person.

<Embodiment> FIG. 1 is a block diagram of an embodiment of the present invention in the case of two parallel systems, in which data transmission paths IA and IB, memory reading section 2A,
2B, comparison/judgment section 8A, 3B, data processing section 4A, 4
B1 memory writing section 5A.

5B, matching memory 6, memory access control circuit 7
It consists of - With respect to the data input to the data transmission path IA or IB, the memory reading section 2A or 2B reads data at the address corresponding to the identifier consisting of part or all of the data from the matching memory 6, and the comparison judgment section 3A or 3
In B, the read data is compared with each identifier of the input data to determine the relationship between each data. The data processing section 4A or 4B processes each data based on the judgment result obtained by the comparison judgment section 3A or 3B, and the memory writing section 5A or 5B matches any of the above data based on the judgment result. Write to the address corresponding to the identifier of the data in the memory 6, or erase the data in the matching memory 6.

The above series of pipeline processing occurs sequentially for one piece of input data, and memory access requests do not overlap, but if data is input consecutively to the same data transmission path or to different data transmission paths. When data is input in parallel, memory access requests may overlap.

In the memory access control circuit 7, a memory reading section 2A,
2B.

One of the memory access parts of the memory write parts 5A and 5B
Access to the memory is permitted only to these locations using a memory access permission signal (read permission signal A/B or write permission signal A/B). Permission for memory access is granted by the memory access unit 2 where the memory access request occurred.
Priority is given to A, 2B, 5A, or 5B, and if multiple memory accesses overlap, the memory access unit 2A, 2B, or 5 where the memory access request occurred earlier
Priority is given in order from A or 5B. A memory access unit that is permitted to access the memory generates a memory access execution signal (read execution signal A/B, write execution signal A/B) indicating the period during which the memory is being accessed, and during the memory access period, other memory The access unit is not permitted to access the memory, and as soon as the memory access is completed, the memory access unit 2A, 2B, 5A, or 5B that has received another memory access request is permitted to access the memory. In this manner, the data transmission path is controlled by the memory access permission signal during the memory access period in response to a memory access request, and by making memory access by other data wait, it is possible to avoid multiple memory accesses occurring at the same time.

FIG. 2 shows the comparison/judgment section 3A and data processing section 4A in FIG.
, is a configuration diagram when the comparison/determination unit 3B and the data processing unit 4B are executed in the same pipeline stage. Although the illustration is difficult, it is possible to execute multiple pipeline processes in one pipeline stage within the range of the transmission delay time per stage of the data transmission path, depending on the execution time of the pipeline processing, or to execute multiple pipeline processes in one pipeline stage within the range of the transmission delay time per stage of the data transmission path. It is clear that it is possible to implement a configuration in which processing that does not exist is divided into multiple pipeline stages.

<Effects of the Invention> By using the present invention as described above, template matching can be realized at high speed.

[Brief explanation of the drawing]

FIGS. 1 and 2 are configuration diagrams showing one embodiment of the present invention. In FIGS. 1 and 2, IA. IB is a data transmission path, 2A and 2B are memory reading units,
3A and 3B are comparison and determination sections, 4A and 4B are data processing sections,
5A and 5B are memory write units, 6 is a matching memory, and 7 is a memory access control circuit, which converts read execution signals A/B and write execution signals A/B into memory access execution signals, read permission signals A/B, and write. The permission signals A/B are used as memory access permission signals, and the read request signals A/B and write request signals A/B are used as memory access request signals.

Claims (1)

[Claims] 1. A matching memory having at least one input port and having an address corresponding to an identifier consisting of part or all of the data for data input from these input ports, and a matching memory that has an address corresponding to an identifier consisting of a part or all of the data, and a matching memory that has an address corresponding to an identifier consisting of a part or all of the data input from the input port, and a matching memory that has an address corresponding to an identifier consisting of a part or all of the data input from the input port, a memory reading unit that reads an address corresponding to the data, a comparison judgment unit that makes a comparison judgment between the read data and the data, a data processing unit that processes each data based on the comparison result, and the matching memory. a memory writing unit that writes a processing result of the data processing unit to an address corresponding to the identifier of the data, and one or more corresponding to the input ports capable of data transmission while pipeline processing these processes. a data transmission path, and a memory that arbitrates the transmission of data on the data transmission path so that accesses of the single matching memory do not occur simultaneously for two or more data transmitted on at least one data transmission path. What is claimed is: 1. A template matching circuit, comprising: an access control circuit; the circuit executes pipeline processing of each data in parallel for at least one data input, and performs template matching at high speed.