JPH0253161A - Memory access system - Google Patents

Abstract

PURPOSE:To read and write data with no time delay by identifying a bus master having an access to a memory and varying the output timing of the transfer response signal in accordance with the bus master. CONSTITUTION:When a bus master requests an access to a memory 5, a bus request signal is sent to a bus arbiter 7 to perform the arbitration to the bus request given from another bus master. When the bus request is accepted, the master 1 has an access to the memory 5. Then the transfer of data is continued until a transfer response signal (f) is detected. Then the signal (f) is detected by each bus master at different timing each other. Thus a data selector 20 identifies the bus master having an access to the memory 5 by means of the bus busy signals l1 - l4 and outputs the signal (f) in the timing corresponding to said bus master. As a result, the memory access time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access method for a device having a bus configuration in which a plurality of bus masters access memory via a common bus.

[Conventional technology]

Typical bus configurations of this type include multipath, vME bus, etc. For example, Inkface Feb 1987V
It is shown on page 242 of the ME Bus Memory Board Edition.

FIG. 4 is a block diagram of a general multi-mask device using a common bus. A plurality of bus masters 1.2.3.4 and memory 5 are connected to a common bus 6.

In addition, bus masters 1, 2, 3.4 are each bus arbiter 7.
bus arbiter 7 is connected to bus master 1.2.
, 3.4 access the memory 5 at the same time.

The memory is generally constructed as shown in FIG. An address signal a is given from the common bus 6 to an address decoder 11 and a memory control section 12, and the address decoder 11 sends a board select signal (BDSEL) g indicating that a memory on the board has been selected to the memory control section 12. It is designed to be given to Memory fell again? 11 part 12 receives a memory read signal (MEMR)c and a memory write signal (MEMR) from the common bus 6.
MW) d and a clock signal (CLOCK) e are given. The memory control unit 12 then receives a row address strobe signal (RAS), a column address strobe signal (CAS), an out enable signal (OB),
A write enable signal (WE) and an address signal a are output and applied to a memory section 13 consisting of a DRAM. In addition, the memory control unit 12 sets the ready signal (RDY) h to NO.
It is applied to the R circuit 16. The board select signal (B
DSEL) g is also given to the OR circuit 17, and the memory read signal (MEMR) c and the memory write signal (MEMR)
MW) Both d and 1 are given to the AND circuit 18. The output of this AND circuit 18 is applied to the OR circuit 17, and its output is applied to the NOR circuit 16 and the output control terminal OC of the bus driver 15. The direction control terminal DIR of this bus driver 15 is supplied with the memory read signal (MEMR) c. The shift register 14 is supplied with the clock signal e and the output of the NOR circuit 16, and the outputs of the shift register 14 are Q,, Q□I+Q, 11. Q□, are given to the oven collector 19, respectively, and the open collector 19
outputs a transfer response signal (XACT) which is output when data reading or writing is completed. The data b is input/output to/from the bus driver 15, and the bus driver 15 input/output the data b to/from the memory section 13.

In this memory access method, a memory read signal C, a memory write signal d, a clock signal e, and a board select signal g output from an address decoder 11 from a common bus are given to a memory control unit 12, and the memory control unit 12 loads Address strobe signal (RAS), column address strobe signal (CAS), out enable signal (
0ε), write enable signal (WE), and address signal a to the memory section 13, and refresh the memory section I3. The bus driver 15 is enabled when the memory section 13 is accessed, and the bus driver 15 is enabled when the memory section 13 is accessed.
Data b is controlled to be transferred in the A direction, and in the A-B direction during writing.

The shift register 14 has a clear terminal CL of the shift register 14 when the memory section 13 is being read or written.
When R becomes low level, the serial input signals Gy11G, , +1+(lK+2+Qi) are sequentially outputted by the clock signal e. That is, the outputs Q111Q+1+1I
There is a delay in the output becoming high level in the order of Q11゜2... Here, a ready signal (RD
Y) h is at a low level when the memory section 13 is read or written, and is at a high level during the refresh period. The output of the shift register 4 becomes a transfer response signal f and is applied to the bus master 7, and the applied bus master detects this transfer response signal f and completes one data transfer.

[Problem to be solved by the invention]

As mentioned above, when multiple bus masters 1, 2, 3, 4 access the memory 5, each bus master 1, 2.
Since the timing at which the shift register 4 detects the transfer response signal f differs for each bus master, it is necessary to output the transfer response signal f output by the shift register 4 with reference to the bus master that detects it at the latest timing.

However, if the number of accesses to the memory 5 is small, there is not much of a problem, but since modern OA-related equipment handles image information, for example, an image equivalent to A3.16 dots (
16 to copy 4864 x 6252 dots)
If this is done in bit units and the transfer response signal is output at a timing of 8 MHz, and one memory access takes one clock more time, the time loss is 1
25ns X (4864X 6252) / 16
X 2 L = 475 m5, which is a value that cannot be ignored even if it is one clock. Furthermore, when processing becomes complicated due to processing such as rotation and enlargement, there is a problem that the number of memory accesses increases and time loss becomes larger.

SUMMARY OF THE INVENTION In view of such problems, it is an object of the present invention to provide a memory access method that eliminates the delay in outputting a transfer response signal to a bus master and shortens memory access time.

[Effect]

The bus master provides a bus request signal to the bus arbiter. The bus arbiter performs arbitration based on the applied bus request signal. The bus master whose bus request signal is acknowledged through arbitration accesses the memory and outputs a bus busy signal. The memory identifies the bus master based on the bus busy signal and outputs the transfer response signal at a timing appropriate to the bus master, so that there is no time delay until the bus master detects the transfer response signal.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments thereof.

FIG. 1 is a block diagram of a main part of a memory access circuit to which a memory access method according to the present invention is applied. A clock signal e is applied to the clock terminal of the shift register 14, and an enable signal (E
N) The output of a NOR circuit 16 to which i and a ready signal (RDY) h are given is given. Output port of shift register 14. 1Q++Q2. Qz is given to each data selector 20, and this data selector 20 also receives bus busy signals 1 r (BUSY+), l□ (BUSY2) output from each bus master 1, 2, 3, 4.
.

l z (BUSY+), l a (BIJSYa> are given, and the output of the data selector 20 is given to the open collector 19 .
outputs a transfer response signal f. The circuit configuration of the memory 5 other than this circuit portion is the same as that shown in FIG.

Next, the access operation of the memory access circuit configured as described above will be explained with reference to FIGS. 1 to 5. Figure 2 is 1
3 is a timing chart showing the timing at which one bus master accesses the memory, and this figure shows the timing when the memory is read three times.

First, for example, the bus master 1, which requests access to the memory 5, provides a bus request signal (BRQ+) j to the bus arbiter. As a result, the bus arbiter 7
, 3.4, and if bus master 1 is allowed to use the common bus 6, it sends a bus request acceptance signal (B
ACKI) Bus master 1 requesting access to k
give to Then, the bus master 1 whose bus use request has been acknowledged outputs a bus use signal (BIJSYI) l + and accesses the memory 5. Here, the bus master 1 continues to output commands such as addresses and memory read signals until it detects the transfer response signal (XACK) f.

Now, FIG. 3 is a timing chart showing the operation of the data selector 20 shown in FIG. 1. Clear signal (cLR) m given to shift register 14 in FIG.
becomes high level when the memory 5 is accessed as in the case in FIG. 5, and the outputs Qo, Q+, Qz, fl
l+ is sequentially inverted by the clock signal e and shifts the serial input which is always at a high level.

By the way, in FIG. 3, for example, bus master 1 outputs Q0.
However, considering the case where bus master 2 cannot input data unless it outputs Q, in the conventional memory access method, the transfer response signal f is output at the delayed output timing, so for bus master 1, This resulted in a time loss equivalent to one clock of the clock signal.

However, the present invention has a shift register 1 as shown in FIG.
4 is given to the data selector 20, and a bus busy signal (BUSY+ to BUSY4) is used to indicate which bus master is accessing the memory 5. r ~ l
4, and when the bus busy signal 21 is active, the timing of the output Q0 is selected, and when h is active, the timing of the output Q1 is selected, and the timing of the output of the transfer response signal f is changed. The transfer response signal f is output at a timing corresponding to the bus master that is currently in use. In addition, the bus is in use signal! , ~14 is
Since this signal is activated only by a bus master that is authorized to use the common bus 6, two or more bus masters will not be activated in the same way, and the transfer response signal f can be given to the accessing bus master without time loss. .

In this embodiment, the case where bus master 1 accesses the memory has been described, but other bus masters 2, 3, 4
Of course, the memory can also be accessed in the same way.

〔Effect of the invention〕

As described in detail above, when a bus master is accessing memory, the bus master that is accessing the memory is identified by the bus busy signal of the bus master, and the timing for outputting the transfer response signal is set to the bus master. Since the values are varied accordingly, data reading and data writing can be performed without time delay, and memory access time can be shortened. Therefore, by applying the present invention to an image processing apparatus that needs to access a large capacity memory, excellent effects such as the ability to significantly shorten the memory access time can be achieved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the main parts of a memory access circuit for applying the memory access method according to the present invention, Fig. 2 is a timing chart showing the timing when accessing the memory, and Fig. 3 is a transfer response signal generation. FIG. 4 is a block diagram of a multi-mask device using a common bus, and FIG. 5 is a block diagram of a conventional memory. 1.2, 3.4...Bus master 5...Memory
6...Common bus 7...Bus arbiter 11
...Address decoder 12...Memory control section
13...Memory section 14...Shift register 1
6...NOR circuit 20...Data selector agent Patent attorney Noboru Kono e, fcLOc) Formal notes

Claims (1)

[Claims] 1. When multiple bus masters access memory,
In the memory access method, the bus master issues a request to use the shared bus to a bus arbiter, the bus master that is granted the request accesses the memory, and the memory outputs a transfer response signal to the bus master upon completion of data read and data write. A memory access method characterized in that a bus master accessing a memory is identified, and the timing of outputting the transfer response signal is made different depending on the bus master.