JPH0110653Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a device for preventing processing omissions of periodic processing data in a computer system that time-divisionally processes periodic processing data and non-periodic processing data in accordance with processing requests.

Conventionally, there is a computer system that time-sharingly processes fixed periodic processing data and irregular periodic processing data according to processing requests, but in this computer system, processing requests for fixed periodic processing data and processing requests for irregular periodic processing data are simultaneously processed. In order to prevent a situation where a conflict of processing requests occurs and the fixed periodic processing data is not processed, a priority relationship is set between the fixed periodic processing data and the irregular periodic processing data,
Periodically processed data with high priority is processed preferentially.

Control for such priority processing is executed by a control program called an operating system, but it requires additional memory to store the control program, which increases the scale of the hardware. There are drawbacks. This drawback is fatal in computer systems, such as microcomputer systems, where memory capacity is limited and hardware needs to be downsized.

This invention was made in view of the above-mentioned circumstances, and its purpose is to provide a device for preventing processing omissions in periodic processing data that can prevent processing omissions in periodic processing data with a small-scale configuration. .

Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, the processing omission prevention device is roughly divided into a periodic signal generating section 1, a delay period counter 2, and a delay period monitoring section 3. On the other hand, the computer 4 has a program memory M, processing request command flip-flops _F1 to Fn, and a multiplexer.
MPX, data processing unit PU ₁ ~ PUn, output device Q,
It consists of a buffer memory BM.

The periodic signal generator 1 generates a periodic signal P ₁ with a period τ corresponding to the period at which the fixed periodic processing data is to be processed.
It is a clock pulse generator.
The counter CTR ₀ that counts clock pulses from the CPG is compared with the count value of the counter CTR ₀ and the setting data D (τ) representing the processing cycle τ of the fixed-cycle processing data set in the data setting device DS ₁ , and they match. Equipped with a one-shot pulse generator WPG ₀ that outputs a one-shot pulse when
The one-shot pulse is a periodic signal P ₁ with a period τ
is output as

The delay period count 2 is counted up by the period signal P ₁ and counted down by the data processing completion signal P ₃ from the data processing unit PU ₁ , and the count value is calculated as the number of processing delay periods of the fixed period processing data. It outputs a delay period number signal _DP1 representing .

The delay cycle monitoring circuit 3 detects when the value of the delay cycle number signal is within an allowable value, that is, the time period after which the delay of periodic processing data whose processing should be started at the scheduled time every τ period can be recovered. If so, a processing request command _S1 for periodic processing data is generated, and if the delay from the scheduled time is such that it cannot be recovered after that, an abnormal signal _P2 is output, and the allowable delay period is Data setter DS ₂ for setting value D(Y), unacceptable value D of delay period
(N), the data setter DS ₃ compares the output signal DP ₁ of the delay period counter 2 with the above-mentioned allowable value D(Y), and outputs the processing request command S ₁ when DP ₁ = D(Y). One-shot pulse generator
WPG ₁ , and a one-shot pulse generator WPG ₂ that compares the signal DP ₁ with an unacceptable value D(N) and outputs an abnormal signal P ₂ when DP ₁ =D(N).

_The computer 4 temporarily stores a processing request command S ₁ regarding fixed periodic processing data and a processing request command _{S 2 .}
Through command detection scanning by the multiplexer MPX, processing for each command S ₁ to S _o is sequentially accepted, and the processing stored in the program memory in the data processing units PU ₁ to PU _o corresponding to each command S ₁ to _{S o} is performed. Executes processes according to the program sequentially. The buffer memory is used to temporarily store various data when executing a processing program. The processing results are then output to the outside via the output device Q. Note that when the data processing unit PU ₁ completes the predetermined data processing, it outputs a data processing completion signal P ₃ representing this fact. This data processing completion signal _P3 is used as a signal for the delay period counter 2. Next, the operation will be explained using the time chart shown in FIG. In addition, the allowable value of the delay period D(Y)
and non-acceptable values are D(N) and D(Y)=
1, and D(N)=3.

First, when the periodic signal generator 1 outputs the periodic signal P ₁ for every τ period, the delay period counter CTR ₁ is counted up by this periodic signal P ₁ .
The count value, that is, the delay period number signal DP ₁ becomes DP ₁ =1 as shown in FIG. 2c. As a result, the fixed period processing data J(A) is transmitted from the delay period monitoring unit 3.
A processing request command _S1 regarding (see FIG. 2a) is output. This processing request command _S1 is detected by multiplexer MPX. By this,
Fixed period processing data J(A) in data processing unit PU ₁
The related processing is executed for a period of time as indicated by the dotted line in FIG. 2a. When this processing is completed, the data processing unit PU ₁ outputs a data processing completion signal P ₃ , which causes the delay period counter CTR ₁ to count down, and the signal DP ₁ becomes DP ₁ =0. Then, while the signal DP ₁ is DP ₁ = 0, the processing related to other non-periodic processing data J(B) for which a processing request was made while the processing related to the fixed-period processing data J(A) is being executed is performed as shown in FIG. It is executed for the time shown by the wavy line.
Thereafter, when the periodic signal _P1 is generated again, the process regarding the periodic processing data J(A) is executed again.

By the way, if the processing time of irregular periodic processing data in the interval τ ₂ in Fig. 2 increases by t' time, then τ ₃
The periodic processing data J(A) in the interval does not start its processing at the fixed time _t3 , but because the delay period number signal _DP1 is _DP1 =1, it starts with a delay of time t'.

However, the processing of the periodic processing data J(A) that should start at the scheduled time t ₄ in the section τ ₄ in FIG. 2 is delayed by t'' time, and the processing is longer than usual.
If the process is not completed even after the scheduled time t ₆ , the delay period number signal DP ₁ becomes DP ₁ =3 at the scheduled time t ₆ . signal
When DP ₁ becomes "3", it means that the delay time is one cycle (1τ) or more and two cycles worth of periodic processing data are unprocessed. In such a case, it is considered almost impossible to catch up afterward. Therefore, the one-shot pulse generator WPG ₂ outputs an abnormality signal P ₃ when the signal DP ₁ becomes DP ₁ =3, and generates an alarm externally via the output device Q. at the same time,
Reset the delay period counter CTR ₁ . After this,
A similar operation is performed.

As is clear from the above explanation, the present invention monitors processing delays related to periodic processing data, and if the delay time is within an allowable value, predetermined processing is executed even after the scheduled time has passed. This is how it was done. Therefore, it is possible to prevent processing omissions of periodic processing data with an extremely simple configuration, and it is possible to further improve the reliability of the computer system. In particular, when the computer system is intended to control an external device, there is an advantage that it is possible to prevent adverse effects on the external device due to fluctuations in the amount of data processed inside the computer.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a time chart for explaining the operation. DESCRIPTION OF SYMBOLS 1... Periodic signal generation part, 2... Delayed period counter, 3... Delayed period monitoring part, 4... Calculator.

Claims (1)

[Scope of utility model registration request] Generates a periodic signal corresponding to the period at which the periodic processing data should be processed, in a device for preventing processing omissions of periodic processing data in a computer system that time-sharingly processes fixed periodic processing data and irregular periodic processing data according to a processing request. a periodic signal generating means for counting up by the periodic signal and counting down by a data processing completion signal from a data processing section in the computer system;
A counter outputs the count value as a delay cycle number signal representing the number of processing delay cycles of fixed-cycle processing data, and generates a processing request for fixed-cycle processing data when the value of the delay cycle number signal is within an allowable value. , and a delay cycle monitoring means for generating an abnormal signal when the value is outside the allowable value.