JPH01104741U - - Google Patents
Info
- Publication number
- JPH01104741U JPH01104741U JP40388U JP40388U JPH01104741U JP H01104741 U JPH01104741 U JP H01104741U JP 40388 U JP40388 U JP 40388U JP 40388 U JP40388 U JP 40388U JP H01104741 U JPH01104741 U JP H01104741U
- Authority
- JP
- Japan
- Prior art keywords
- package
- terminals
- vertical
- utility
- straight line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図、第２図、第３図および第４図はそれぞ
れ本考案の実施例を示す底面図である。
１……端子、２……最外周の端子列、３……最
内周の端子列、４……中間の周の端子列。
1, 2, 3 and 4 are bottom views showing embodiments of the present invention, respectively. 1...Terminal, 2...Terminal row on the outermost circumference, 3...Terminal row on the innermost circumference, 4...Terminal column on the middle circumference.
Claims (1)
方向について一直線上に配置されていないことを
特徴とするピングリツドアレイＩＣ。 A pin grid array IC characterized in that terminals on adjacent peripheries are not arranged in a straight line in the vertical and horizontal directions of a package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40388U JPH01104741U (en) | 1988-01-05 | 1988-01-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40388U JPH01104741U (en) | 1988-01-05 | 1988-01-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01104741U true JPH01104741U (en) | 1989-07-14 |
Family
ID=31199397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP40388U Pending JPH01104741U (en) | 1988-01-05 | 1988-01-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01104741U (en) |
-
1988
- 1988-01-05 JP JP40388U patent/JPH01104741U/ja active Pending