JPH01103929U - - Google Patents
Info
- Publication number
- JPH01103929U JPH01103929U JP19792687U JP19792687U JPH01103929U JP H01103929 U JPH01103929 U JP H01103929U JP 19792687 U JP19792687 U JP 19792687U JP 19792687 U JP19792687 U JP 19792687U JP H01103929 U JPH01103929 U JP H01103929U
- Authority
- JP
- Japan
- Prior art keywords
- oscillation
- circuit
- dump
- control circuit
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 14
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
Landscapes
- Superheterodyne Receivers (AREA)
- Noise Elimination (AREA)
Description
第１図はこの考案に係る発振制御回路を、デユ
アルチユーナ方式の受信機の局部発振回路に適用
した場合の一例を示す系統図、第２図は同様にシ
ンセサイザチユーナの局部発振回路に適用した場
合の一例を示す系統図、第３図は従来の発振制御
回路の動作を説明するための系統図である。
３，４……チユーナ、１２……マイクロコンピ
ユータ、２０，３０……局部発振回路、２７……
可変容量素子、４０，５０……Ｑダンプ回路、４
４……Ｑダンプ用コンデンサ。
Figure 1 is a system diagram showing an example of the case where the oscillation control circuit according to this invention is applied to the local oscillation circuit of a dual tuner type receiver, and Figure 2 is a system diagram showing an example of the case where the oscillation control circuit according to this invention is applied to the local oscillation circuit of a synthesizer tuner. FIG. 3 is a system diagram for explaining the operation of a conventional oscillation control circuit. 3, 4... tuner, 12... microcomputer, 20, 30... local oscillation circuit, 27...
Variable capacitance element, 40, 50...Q dump circuit, 4
4...Q dump capacitor.
Claims (1)
用できるようになされると共に、 上記夫々の発振回路に対してＱダンプ回路が接
続され、 発振回路の不使用時には、このＱダンプ回路を
動作させることによつて、上記発振回路の発振を
停止させるようにしたことを特徴とする発振制御
回路。 (2) 上記発振回路として、チユーナの局部発振
回路が使用されてなることを特徴とする実用新案
登録請求の範囲第１項記載の発振制御回路。[Claims for Utility Model Registration] (1) It has a plurality of oscillation circuits, each of which can be used independently, and a Q-dump circuit is connected to each of the oscillation circuits. An oscillation control circuit characterized in that when not in use, the oscillation of the oscillation circuit is stopped by operating the Q-dump circuit. (2) The oscillation control circuit according to claim 1, wherein a tuner local oscillation circuit is used as the oscillation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19792687U JPH01103929U (en) | 1987-12-25 | 1987-12-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19792687U JPH01103929U (en) | 1987-12-25 | 1987-12-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01103929U true JPH01103929U (en) | 1989-07-13 |
Family
ID=31488457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19792687U Pending JPH01103929U (en) | 1987-12-25 | 1987-12-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01103929U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5633838B2 (en) * | 1978-06-28 | 1981-08-06 | ||
| JPS6072306A (en) * | 1983-09-28 | 1985-04-24 | Anritsu Corp | Oscillator |
-
1987
- 1987-12-25 JP JP19792687U patent/JPH01103929U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5633838B2 (en) * | 1978-06-28 | 1981-08-06 | ||
| JPS6072306A (en) * | 1983-09-28 | 1985-04-24 | Anritsu Corp | Oscillator |
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