JPH01102431A - Thin film semiconductor device and its production - Google Patents
Thin film semiconductor device and its productionInfo
- Publication number
- JPH01102431A JPH01102431A JP62258298A JP25829887A JPH01102431A JP H01102431 A JPH01102431 A JP H01102431A JP 62258298 A JP62258298 A JP 62258298A JP 25829887 A JP25829887 A JP 25829887A JP H01102431 A JPH01102431 A JP H01102431A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- film
- signal line
- protective film
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 23
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 70
- 230000001681 protective effect Effects 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000002844 melting Methods 0.000 abstract description 3
- 230000008018 melting Effects 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract 2
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 230000007547 defect Effects 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000011109 contamination Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 230000009993 protective function Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は薄膜半導体装置、特に透過型液晶表示用の薄膜
トランジスタおよびその製造方法に係り、さらに具体的
にいえば、パッシベーション特性の優れた薄膜半導体装
置及びその製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a thin film semiconductor device, particularly a thin film transistor for a transmissive liquid crystal display, and a method for manufacturing the same, and more specifically, a thin film semiconductor with excellent passivation properties. This invention relates to a device and its manufacturing method.
［従来の技術］
従来の透過型液晶表示用パネルとしては、「日経エレク
トロニクスＪ １９８４年９月１０日号第２１１頁以降
の「商品化された液晶ポケット・カラーテレビ」と題す
る論文に記載されているように、絶縁性の透明基板（例
えば石英、パイレックス、ソーダガラス等）上に薄膜ト
ランジスタ（以下、ＴＦＴと略称する）をマトリックス
状に形成し、これを液晶のシャッタとして使用する技術
を用いたものが開発されている。[Prior Art] A conventional transmissive liquid crystal display panel is described in an article titled ``Commercialized LCD Pocket Color Television'' in Nikkei Electronics J, September 10, 1984 issue, pages 211 onwards. This is a technology that uses a technology in which thin film transistors (hereinafter referred to as TFTs) are formed in a matrix on an insulating transparent substrate (e.g. quartz, pyrex, soda glass, etc.) and used as a shutter for liquid crystals. is being developed.
表示パネルの表示部電極としては酸化インジウム、酸化
錫あるいはインジウム錫酸化物等の透明電極を用い、対
向する透明電極間に液晶を封入することにより、透過型
の表示パネル構成が得られる。A transmissive display panel structure can be obtained by using transparent electrodes such as indium oxide, tin oxide, or indium tin oxide as the display part electrodes of the display panel and filling liquid crystal between the opposing transparent electrodes.
上記の透明電極とＴＰＴとを一対にし、これをデイスプ
レィの一つの画素として、マトリックス状に配列したも
のがアクティブマトリックス基板である。An active matrix substrate is a pair of transparent electrodes and TPTs arranged in a matrix as one pixel of a display.
ＴＰＴを動作させるためにはソース、ドレイン及びゲー
トにそれぞれ電極が設けられ、さらにこれらの電極は、
二層配線技術により同一基板平面上のゲートおよび信号
ライン用電極とそれぞれ接続された構造をとっている。In order to operate the TPT, electrodes are provided at the source, drain, and gate, and these electrodes are
It has a structure in which it is connected to the gate and signal line electrodes on the same substrate plane using two-layer wiring technology.
このような構造の液晶表示用パネルにおいては、一画素
毎にスイッチング用のＴＰＴが形成されているため、高
いコントラストが得られる。In a liquid crystal display panel having such a structure, a switching TPT is formed for each pixel, so high contrast can be obtained.
第２図はＴＰＴアクティブマトリックス基板の画像表示
領域の構成単位である一画素の平面図で、第３図は第１
図中のＡ−Ａ線にそう、従来の断面構造を示す。Fig. 2 is a plan view of one pixel, which is a constituent unit of the image display area of the TPT active matrix substrate, and Fig. 3 is a plan view of one pixel, which is a constituent unit of the image display area of the TPT active matrix substrate.
The conventional cross-sectional structure is shown on line A-A in the figure.
これらの図において、１はデータ信号ライン電極、２は
ゲート信号ライン電極、３は液晶用透明電極膜、４はＴ
ＰＴのドレイン領域１１とデータ信号ライン１との接続
部（コンタクトスルーホール；穴）、５はＴＦＴ，６は
ＴＦＴのソース領域１０と透明電極膜３の接続部、１７
はゲート引出電極、８はゲート信号ライン電極２とゲー
ト端子電極７の接続部である。In these figures, 1 is a data signal line electrode, 2 is a gate signal line electrode, 3 is a transparent electrode film for liquid crystal, and 4 is a T
A connection part (contact through hole; hole) between the drain region 11 of the PT and the data signal line 1, 5 a TFT, 6 a connection part between the TFT source region 10 and the transparent electrode film 3, 17
8 is a gate lead electrode, and 8 is a connection portion between the gate signal line electrode 2 and the gate terminal electrode 7.
第３図の従来の構造において、９はＴＰＴのチャンネル
領域で、これはノンドープの非晶質シリコンあるいは多
結晶シリコンで形成されている。In the conventional structure shown in FIG. 3, 9 is a channel region of the TPT, which is made of non-doped amorphous silicon or polycrystalline silicon.
１０はＴＰＴのソース領域、１１はＴＰＴのドレイン領
域であり、通常は非晶質シリコンあるいは多結晶シリコ
ンにリンＣＰ） ′、ボロン（Ｂ）、ヒ素（Ａｓ）等の
不純物を、イオン打ち込みや熱拡散法でドープすること
により、低抵抗化して使用する。10 is the source region of the TPT, and 11 is the drain region of the TPT. Usually, impurities such as phosphorus (CP)', boron (B), and arsenic (As) are added to amorphous silicon or polycrystalline silicon by ion implantation or heat treatment. It is used with low resistance by doping using a diffusion method.
１２はＴＰＴのゲート絶縁膜、１３はゲート電極膜で、
ソース１０及びドレイン領域１１と同様に、低抵抗化し
た非晶質シリコンあるいは多結晶シリコンで形成してい
る。１４は絶縁保護膜で、Ｓ ｉ Ｏ ２やＳｉＮ系の
膜を用いている。12 is a TPT gate insulating film, 13 is a gate electrode film,
Like the source 10 and drain region 11, it is made of low-resistance amorphous silicon or polycrystalline silicon. Reference numeral 14 denotes an insulating protective film, which is made of SiO 2 or SiN.
透明電極膜３はソース電極６１を介してソース領域１０
と接続している。またゲート信号ライン電極２は、ゲー
ト引出電極１７と、絶縁保護膜１４の一部開口部に形成
された接続部８内のゲート端子電極７で接続されると共
に、ゲート電極膜１３にも接続されている。１５は絶縁
性の透明基板で、ガラスや石英板である。The transparent electrode film 3 is connected to the source region 10 via the source electrode 61.
is connected to. Further, the gate signal line electrode 2 is connected to the gate lead electrode 17 by a gate terminal electrode 7 in a connecting portion 8 formed in a partial opening of the insulating protective film 14, and is also connected to the gate electrode film 13. ing. 15 is an insulating transparent substrate, which is a glass or quartz plate.
［発明が解決しようとする問題点］
このような従来の技術においては、ゲート信号ライン電
極２すなわち、絶縁保護Ｍ！１４に埋め込まれる第一層
目の電極形成時に、ＴＰＴのゲート絶縁膜１２とソース
領域１０及びドレイン領域１１とのＴＰＴ接合近傍の清
浄化に配慮がされておらず、このために、ゲート信号ラ
イン電極２の残漬物の汚染によるＴＰＴ特性不良（例え
ば、ゲート絶縁抵抗の劣化やソース・ドレイン間のリー
ク電流増大など）を起す問題があった。[Problems to be Solved by the Invention] In such a conventional technique, the gate signal line electrode 2, that is, the insulation protection M! When forming the first layer of electrodes to be embedded in the TPT gate insulating film 12 and the source region 10 and drain region 11, no consideration was given to cleaning the vicinity of the TPT junction, and for this reason, the gate signal line There is a problem in that the contamination of the electrode 2 with residual material causes poor TPT characteristics (for example, deterioration of gate insulation resistance and increase in leakage current between the source and drain).
本発明の目的は、ゲート絶縁膜、ソース及びドレイン領
域のＴＰＴ接合近傍を第一層目の電極形成時に汚染され
ないような構造とした薄膜トランジスタおよびその製造
方法を提供することにある。An object of the present invention is to provide a thin film transistor having a structure in which the vicinity of the TPT junction of the gate insulating film, source and drain regions is not contaminated during formation of the first layer electrode, and a method for manufacturing the same.
［問題点を解決するための手段］
上記目的は、ゲート信号ライン電極すなわち、第一層目
の電極形成前に、ＴＰＴ接合近傍領域にあらかじめ薄い
絶縁保護層を形成することにより達成される。[Means for Solving the Problems] The above object is achieved by forming a thin insulating protective layer in the region near the TPT junction before forming the gate signal line electrode, that is, the first layer electrode.
［作用］
本発明にしたがって、ＴＰＴ接合近傍領域に予め形成し
た薄い保護膜は以下のように作用する。[Function] According to the present invention, the thin protective film previously formed in the region near the TPT junction functions as follows.
・すなわち、従来構造のＴＰＴで、絶縁耐圧、ＴＰＴ特
性及び負荷（経時）寿命試験などにおいて、耐圧不良、
リークの増大、スイッチング速度の低下及びしきい値電
圧の変動を生ずる原因を究明した結果、これらの不良は
、ＴＰＴのゲート絶縁膜とソース領域及びドレイン領域
との間の絶縁性能の低下及び劣化によるものであり、さ
らにこれらの絶縁不良は、ＴＰＴ接合近傍がゲート信号
ライン電極（第一層目の電極）の残漬物で汚染されたこ
とによるものであることが判明した。・In other words, with a TPT of conventional structure, there were no breakdown voltage defects,
As a result of investigating the causes of increased leakage, decreased switching speed, and fluctuations in threshold voltage, we found that these defects were due to decreased insulation performance and deterioration between the gate insulating film and the source and drain regions of the TPT. Furthermore, it was found that these insulation defects were caused by the vicinity of the TPT junction being contaminated with residue from the gate signal line electrode (first layer electrode).
本発明により、ＴＰＴ接合を覆うように形成される薄い
保護膜は、ゲート信号ライン電極がＴＰＴの接合近傍時
にゲート絶縁膜側面に直接接触することを防止するので
、前記電極形成時の残漬物による汚染と、これに伴なう
ＴＰＴ特性の変動や劣化を完全に防止する作用をする。According to the present invention, the thin protective film formed to cover the TPT junction prevents the gate signal line electrode from coming into direct contact with the side surface of the gate insulating film near the TPT junction. It acts to completely prevent contamination and accompanying fluctuations and deterioration of TPT characteristics.
また、前記の薄い保護膜はＡＩなどの電極形成前に形成
されるので、高温での形成ができ、膜質をち密にできる
ので、薄くても十分な保護機能を呈することができる。Furthermore, since the thin protective film is formed before forming the electrodes such as AI, it can be formed at high temperatures and the film quality can be made dense, so that it can provide a sufficient protective function even if it is thin.
［実施例］
以下、本発明の一実施例を第１図により説明する。第１
図は、第３図と同様に、第２図のＡ−Ａ線にそった断面
構造を示す。[Example] Hereinafter, an example of the present invention will be described with reference to FIG. 1st
The figure shows a cross-sectional structure taken along the line A--A in FIG. 2, similar to FIG. 3.
まず、透明絶縁基板（本実施例では、高品質ガラス基板
を使用）１５上に、非晶質シリコン（α−３ｔ）あるい
は多結晶シリコン（ｐ−５ｉ）膜を形成する（本実施例
ではｐ−８ｔ膜を厚さ１５００人に形成した）。First, an amorphous silicon (α-3t) or polycrystalline silicon (p-5i) film is formed on a transparent insulating substrate (in this example, a high-quality glass substrate is used) 15 (in this example, a high-quality glass substrate is used). -8t film was formed to a thickness of 1500 mm).
そして、ＴＰＴ薄膜領域を通常のホトリソグラフィ技術
によりパターニングする。Then, the TPT thin film region is patterned using normal photolithography technology.
次いで、ゲート絶縁膜用Ｓ Ｉ Ｏ２１％及びゲート電
極用ｐ−８ｉ膜を順次に、それぞれ厚さ約１０００人に
形成した後、上記と同様のホトリソグラフィ技術により
パターニングし、ゲート絶縁膜１２及びゲート電極ｌ１
１３を形成する。Next, an SIO21% film for the gate insulating film and a p-8i film for the gate electrode were sequentially formed to a thickness of about 1000 ml each, and then patterned using the same photolithography technique as described above to form the gate insulating film 12 and the gate electrode. electrode l1
form 13.
次いで、ＴＦＴのソース・ドレイン領域及び、ゲート電
極用ｐ−８ｉ膜面１３にｎ型あるいはｐ型の不純物を、
セルファライン方式でイオン注入あるいは熱拡散してソ
ース領域１０． ドレイン領域１１及びチャネル領域
９を形成する。Next, n-type or p-type impurities are added to the source/drain regions of the TFT and the p-8i film surface 13 for gate electrode.
The source region 10 is ion-implanted or thermally diffused using the self-line method. A drain region 11 and a channel region 9 are formed.
本実施例では、ｎ型不純物としてリンをイオン注入した
。また、この時のリンのドーズ量を約５ＸＩＯａｔｏｍ
ｓ／ｃｍ２とした。In this example, phosphorus was ion-implanted as an n-type impurity. In addition, the dose of phosphorus at this time is approximately 5XIOatom.
It was set as s/cm2.
従来はここで、ゲート信号ライン電極２用の導電膜が基
板全面に形成されるが、前記した従来の問題点や作用の
理由により、この実施例では、ゲート信号ライン電極用
導電膜の形成の前に、ＴＰＴ領域を保護するためにあら
かじめ薄いキャップ絶縁保護膜１４１を形成する。Conventionally, a conductive film for the gate signal line electrode 2 is formed on the entire surface of the substrate, but due to the problems and effects of the conventional method described above, in this embodiment, the conductive film for the gate signal line electrode 2 is formed. First, a thin cap insulating protective film 141 is formed in advance to protect the TPT region.
本実施例では、このキャップ絶縁保護膜１４１として常
圧ＣＶＤ方によるち密なＰＳＧ膜を厚さ約１０００Ａに
堆績させた。なお、ここではキャップ絶縁保護膜１４１
を基板１５の全面に形成しているが、最小限ＴＰＴ領域
を被覆できれば十分であることは、容易に理解されるで
あろう。In this embodiment, as the cap insulating protective film 141, a dense PSG film was deposited to a thickness of about 1000 Å by atmospheric pressure CVD. Note that here, the cap insulating protective film 141
is formed over the entire surface of the substrate 15, but it will be easily understood that it is sufficient to cover at least the TPT region.
また、この場合の膜形成温度は、基板が変形しない範囲
で十分に高くできるので、膜質をち密にし、薄くてより
完全な保護機能をもつものとすることができる。Further, in this case, the film formation temperature can be set to a sufficiently high temperature within a range that does not deform the substrate, so that the film can be made denser, thinner, and have a more complete protective function.
その後、従来の場合と同様に、−層目の電極すなわち、
ゲート信号ライン電極２としてＡ！電極膜を、ゲート電
極膜１３に導電接触するように、厚さ約ａｏｏｏＡに形
成し、次いで、メイン絶縁保護膜１４として、ＡＺの融
点以下の温度での、常圧ＣＶＤ法によるＰＳＧ膜を厚さ
約６００ ＯＡに形成する。After that, as in the conventional case, the -th electrode, that is,
A as gate signal line electrode 2! An electrode film is formed to a thickness of about aoooA so as to be in conductive contact with the gate electrode film 13, and then, as the main insulating protective film 14, a PSG film is formed by atmospheric pressure CVD at a temperature below the melting point of AZ. Form to approximately 600 OA.
つづいて、ＴＦＴのソース領域１０、ドレイン領域１１
及びゲート信号ライン電極領域２に、それぞれコンタク
トスルホール６．４、および８をホトリソグラフィ技術
で開孔したのち、それぞれにソース電極１０１、ドレイ
ン電極１１１及びゲート端子電極７、ならびにデータ信
号ライン電極１を同時に形成する。Next, the source region 10 and drain region 11 of the TFT.
After forming contact through holes 6.4 and 8 in the gate signal line electrode region 2 and gate signal line electrode region 2 using photolithography, a source electrode 101, a drain electrode 111, a gate terminal electrode 7, and a data signal line electrode 1 are formed respectively. form at the same time.
ここで形成する電極は、本実施例ではスパッタリング法
によるＡ！膜で、厚さは約６０００人とした。In this example, the electrodes formed here are A! by sputtering method. The film was approximately 6,000 people thick.
その後、ソース領域１０及びその近傍に、液晶駆動用の
透明電極膜３を、ソース電極１０１に導電接触するよう
に形成する。本実施例では、この膜をスパッタリング法
によるインジューム・酸化錫膜（ＩＴＯ膜）とし、その
厚さを約８００λとした。Thereafter, a transparent electrode film 3 for driving the liquid crystal is formed in the source region 10 and its vicinity so as to be in conductive contact with the source electrode 101. In this example, this film was formed into an indium tin oxide film (ITO film) by sputtering, and its thickness was about 800λ.
以上のような工程をへて、第２図に示すＴＰＴ装置を制
作した。なお、これ以降の液晶ディスプケレイ製作工程
は、従来の通常プロセスと全く同じであるので、ここで
はその説明は省略する。Through the above steps, the TPT device shown in FIG. 2 was manufactured. Note that the subsequent steps for manufacturing the liquid crystal display panel are exactly the same as the conventional normal process, so the explanation thereof will be omitted here.
以上のように、本発明の実施例によれば、ＴＰＴのソー
ス、ドレインおよびゲート領域のそれぞれの接合近傍を
覆うように、第一層目の電極形成以前にキャップ絶縁保
護膜を形成しているので、基板１５が変形、溶融しない
範囲で可及的高温での保護膜形成ができ、膜質をち密に
し、電極残漬物等による汚染および、これに伴なうＴＰ
Ｔの護持性の劣化を防止するのに効果がある。As described above, according to the embodiment of the present invention, the cap insulating protective film is formed before forming the first layer electrode so as to cover the vicinity of each junction of the source, drain, and gate regions of the TPT. Therefore, the protective film can be formed at as high a temperature as possible without deforming or melting the substrate 15, making the film dense and preventing contamination from electrode residue and the accompanying TP.
It is effective in preventing deterioration of the protective properties of T.
［発明の効果］
本発明によれば、ＴＦＴ素子のソース、ドレイン接合及
びゲート絶縁膜の電極形成時の、電極残渣物による汚染
を防止できるので、ゲート絶縁耐電圧不良やリーク電流
などを大幅に低減でき、画素欠陥やスイッチング速度低
下のない液晶表示用薄膜トランジスタを歩留り良く製造
できるという効果がある。[Effects of the Invention] According to the present invention, it is possible to prevent contamination due to electrode residues during the formation of electrodes of source and drain junctions and gate insulating films of TFT devices, thereby significantly reducing defects in gate insulation withstand voltage and leakage current. This has the effect that thin film transistors for liquid crystal display can be manufactured with high yield without pixel defects or reduction in switching speed.
また、負荷経時試験におけるしきい値電圧の変動率も、
従来の±１０％に対して±２％以下にできるので、画面
の欠陥や画質低下を防止でき、パネル製作の歩留りを向
上できる効果がある。In addition, the rate of change in threshold voltage in the load aging test is
Since it can be reduced to ±2% or less compared to the conventional ±10%, screen defects and image quality deterioration can be prevented and the yield of panel production can be improved.
第１図は本発明の一実施例の断面図、第２図は本発明を
デイスプレィパネルに適用した場合の一画素部分の平面
図、第３図は従来の液晶表示用薄膜トランジスタの断面
図である。
１・・・データ信号ライン電極、２・・・ゲート信号ラ
イン電極、３・・・透明電極膜、５・・・ＴＰＴ、？・
・・ゲート端子電極、９・・・チャンネル領域、１０・
・・ソース領域、１１・・・ドレイン領域、１２・・・
ゲート絶縁膜、１３・・・ゲート電極膜、１４・・・絶
縁保護膜、１５・・・（透明）絶縁基板、１４１・・・
キャップ絶縁保護膜Figure 1 is a cross-sectional view of one embodiment of the present invention, Figure 2 is a plan view of one pixel portion when the present invention is applied to a display panel, and Figure 3 is a cross-sectional view of a conventional thin film transistor for liquid crystal display. be. DESCRIPTION OF SYMBOLS 1... Data signal line electrode, 2... Gate signal line electrode, 3... Transparent electrode film, 5... TPT, ?・
...Gate terminal electrode, 9...Channel region, 10.
...Source region, 11...Drain region, 12...
Gate insulating film, 13... Gate electrode film, 14... Insulating protective film, 15... (Transparent) insulating substrate, 141...
Cap insulation protective film
Claims (6)
素子と、少なくとも前記薄膜半導体素子を覆うキャップ
絶縁保護膜と、前記絶縁性基板の上面に形成され、薄膜
半導体素子の第１の領域に接続された第１の信号ライン
電極と、前記キャップ絶縁保護膜および第１の信号ライ
ン電極を覆うように、これらの上面に形成された絶縁保
護膜と、前記薄膜半導体素子の第２および第３の領域に
接続されるように絶縁保護膜およびキャップ絶縁保護膜
を貫通して形成された第２および第３の電極と、前記絶
縁保護膜の上面に形成され、前記第２の電極に接続され
た第２の信号ライン電極とを具備したことをことを特徴
とする薄膜半導体装置。(1) an insulating substrate, a thin film semiconductor element formed on the upper surface thereof, a cap insulating protective film covering at least the thin film semiconductor element, and a first region of the thin film semiconductor element formed on the upper surface of the insulating substrate; a first signal line electrode connected to the thin film semiconductor element; an insulating protective film formed on the upper surface of the cap insulating protective film and the first signal line electrode so as to cover the cap insulating protective film and the first signal line electrode; second and third electrodes formed through the insulating protective film and the cap insulating protective film so as to be connected to the region No. 3; and second and third electrodes formed on the upper surface of the insulating protective film and connected to the second electrode. 1. A thin film semiconductor device comprising a second signal line electrode.
にも形成されたことを特徴とする前記特許請求の範囲第
１項記載の薄膜半導体装置。(2) The thin film semiconductor device according to claim 1, wherein the cap insulating protective film is also formed under the first signal line electrode.
他の部分の絶縁保護膜よりも厚いことを特徴とする前記
特許請求の範囲第１項記載の薄膜半導体装置。(3) The thin film semiconductor device according to claim 1, wherein the insulating protective film on the first signal line electrode is thicker than the insulating protective film in other parts.
保護膜よりもち密であることを特徴とする前記特許請求
の範囲第１項記載の薄膜半導体装置。(4) The thin film semiconductor device according to claim 1, wherein the cap insulating protective film is denser than the insulating protective film formed thereon.
くとも前記薄膜半導体素子を覆うキャップ絶縁保護膜を
形成する工程と、前記絶縁性基板の上面に、薄膜半導体
素子の第１の領域に接続される第１の信号ライン電極を
形成する工程と、前記キャップ絶縁保護膜および第１の
信号ライン電極を覆うように、これらの上面に絶縁保護
膜を形成する工程と、前記薄膜半導体素子の第２および
第３の領域を露出させるように、絶縁保護膜およびキャ
ップ絶縁保護膜を貫通して穴を形成する工程と、前記絶
縁保護膜の上面に電極用導電膜を形成し、前記薄膜半導
体素子の第２および第３の領域に接続される第２および
第３の電極、ならびに前記第２の電極に接続される第２
の信号ライン電極を形成する工程とを具備したことをこ
とを特徴とする薄膜半導体装置の製造方法。(5) forming a thin film semiconductor element on the upper surface of the insulating substrate and a cap insulating protective film covering at least the thin film semiconductor element; a step of forming a first signal line electrode of the thin film semiconductor element; a step of forming an insulating protection film on the upper surface of the cap insulating protection film and the first signal line electrode so as to cover the cap insulating protection film and the first signal line electrode; and forming a hole through the insulating protective film and the cap insulating protective film so as to expose a third region, and forming a conductive film for an electrode on the upper surface of the insulating protective film, and forming a hole in the thin film semiconductor element. second and third electrodes connected to the second and third regions; and a second electrode connected to the second electrode.
1. A method for manufacturing a thin film semiconductor device, comprising the steps of: forming a signal line electrode.
にも形成されたことを特徴とする前記特許請求の範囲第
４項記載の薄膜半導体装置の製造方法。(6) The method for manufacturing a thin film semiconductor device according to claim 4, wherein the cap insulating protective film is also formed under the first signal line electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62258298A JPH01102431A (en) | 1987-10-15 | 1987-10-15 | Thin film semiconductor device and its production |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62258298A JPH01102431A (en) | 1987-10-15 | 1987-10-15 | Thin film semiconductor device and its production |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01102431A true JPH01102431A (en) | 1989-04-20 |
Family
ID=17318315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62258298A Pending JPH01102431A (en) | 1987-10-15 | 1987-10-15 | Thin film semiconductor device and its production |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01102431A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1152415A (en) * | 1997-07-29 | 1999-02-26 | Toshiba Corp | Liquid crystal display element |
| KR100285303B1 (en) * | 1991-09-05 | 2001-04-02 | 이데이 노부유끼 | LCD Display |
| JP2019197232A (en) * | 2000-02-22 | 2019-11-14 | 株式会社半導体エネルギー研究所 | Liquid crystal display device |
-
1987
- 1987-10-15 JP JP62258298A patent/JPH01102431A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100285303B1 (en) * | 1991-09-05 | 2001-04-02 | 이데이 노부유끼 | LCD Display |
| JPH1152415A (en) * | 1997-07-29 | 1999-02-26 | Toshiba Corp | Liquid crystal display element |
| JP2019197232A (en) * | 2000-02-22 | 2019-11-14 | 株式会社半導体エネルギー研究所 | Liquid crystal display device |
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