JPH01101731A - Coincidence detecting circuit - Google Patents

Abstract

PURPOSE:To decrease the number of elements when semiconductor integration is executed and to reduce a chip area by using a logical sum circuit as a comparing circuit in each bit. CONSTITUTION:Plural logical sum circuits 3a-3c to input the respective values to logic-invert the digital values of the respective bits of a prescribed value to be set in advance and the respective values of the respective bits of a binary counter 2 and to output the logical sum of respective inputs, are provided. A logical product circuit 4 to input the respective outputs of the logical sum circuits 3a-3c and to output the logical product of the respective inputs, is provided. Thus, only the bit, which is '1' out of the respective bits of the prescribed value to detect coincidence, is observed with attention and a first timing, in which the bit of the correspondent binary counter 2 wholly goes to be '1', can be regarded as a coincident timing. Accordingly, the coincidence can be detected with using the circuit of simple constitution and the number of the transistor elements can be widely decreased. Then, the chip area when a semiconductor integrated circuit is obtained can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a coincidence detection circuit, and particularly to a coincidence detection circuit that detects coincidence between the value of a binary counter and a predetermined value stored in a register.

[Conventional technology]

When managing control timing on a microcomputer, etc., a register (-
A method is sometimes used in which a counter is provided that is progressive at a predetermined clock, and a control signal is generated at that timing by detecting when the counter value becomes equal to the register value.

A conventional coincidence detection circuit used in such a case, for example, as shown in FIG. The match with the value (a3+a2+a+) is detected using the exclusive OR circuits 6a to 6c, and each output of the exclusive OFF circuits 6a to 6c is input to the NOR circuit 7, and the output Voσ of the NOR circuit 7 is detected.
Coincidence detection is performed based on changes in T.

That is, the value of each bit of the binary counter (b3.b
21b is the value of each bit set in register l (
a3+a2+a+), the outputs of the exclusive OR circuits 6a to 6c all become "O".
”, and only in this case, the output Voyr of the NOR circuit 7 becomes high level and a match is detected.

The exclusive off circuits 6a to 6c described above are the fifth
As shown in the figure, NOR circuit 8. lO and AND circuit 9
It is made up of.

[Problem that the invention seeks to solve]

The conventional coincidence detection circuit described above detects the coincidence between the value of each bit of the binary counter and the value of each bit of the register using an exclusive-off circuit, and this exclusive-off circuit consists of two NOR circuits and It has one AND circuit, has a complex configuration, and requires a large number of circuit elements such as transistors. Therefore, if the coincidence detection circuit is made into a semiconductor integrated circuit, the occupied area will increase, leading to an increase in the chip area. There is a drawback.

Means for Solving Problem C] The coincidence detection circuit of the present invention detects each value obtained by logically inverting the digital value of each bit of a predetermined value, and each value of each bit of the binary counter. a plurality of logical sum circuits that take the outputs of the plurality of logical sum circuits as inputs, and output the logical sum of the logical sum circuits; There is.

[Effect]

Since an OR circuit requires fewer elements such as transistors to construct it than an exclusive-OR circuit, it is possible to integrate the elements into a semiconductor by using an OR circuit as a bit-by-bit comparison circuit. The number of chips can be reduced, and the chip area can be reduced.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the coincidence detection circuit of the present invention.

The coincidence detection circuit of this embodiment has OR circuits 3a to 3c in place of the exclusive OR circuits 6a to 6c in the conventional example shown in FIG. The bits are set to the inverted value ("3+M2+at) of the value (a3+a2+al) of each bit of a predetermined value for which a match is to be detected.

In this case, the binary counter 2 is a so-called up counter, and as shown in Table 1, (b31b21bl) advances by 1 from co, o, 0) to (1, 1, l), and is reset again to perform this operation. shall be repeated.

In addition, the value set in register 1 shall always be a larger value than the value of binary counter 2 at that time.0For example, if the value of binary counter 2 is (b3.bz,b
t ) = (o I I I O), then
Value of each bit Cal&2ea! ) is (0, l.

1), (1,0,0), (1,0,1'), (1゜1
, O), (1, 1, l).

Table 1 Next, the operation of this embodiment will be explained.

Now, the predetermined value for which a match should be detected is (a3°a2.a
t) = (1, 0, 1), and the value of the binary counter is (
0, 0, 0). In this case, the inverted value (0, 1, 0) of the predetermined value (1, 0, 1) is stored in the register l. In the initial state, 3 of the OR circuits 3a to 3c
Only the output of b is “1”°, and the outputs of 3a and 3c are “
Next, the binary counter 2 starts counting. At this time, the outputs of the OR circuits 3a to 3c all become U I II, and the output of the AND circuit 4 is inverted from u On to "1°°". This is when the least significant bit b+ and the most significant bit b3 of the binary counter 2 become "l II - (b3Ibl) = (1.

1), as is clear from Table 1, (b3゜bz
, b+) = (1, 0, 1), or (1, 1,
1), first the output of the AND circuit 4 becomes “l”.
” is (1, 0, 1), and the first time the output of this AND circuit 4 is inverted is considered to be the point in time when the value of the binary counter 2 and the predetermined value (a3°a2.at) match. By doing so, a match can be detected without losing reliability.

In this way, we focus on only the bits that are "l" among the bits of the predetermined value to detect a match, and define the first timing when all the bits of the corresponding binary counter 2 become "l" as the match timing. By considering it as
A match can be detected using a simple circuit that does not use an exclusive off circuit as shown in the figure.

FIG. 2(a) is a circuit diagram of another embodiment of the coincidence detection circuit of the present invention, and FIG. 2(b) and (C) are circuit diagrams of equivalent circuits of the portions surrounded by dotted lines in FIG. 2(a).

In the coincidence detection circuit of this embodiment, the binary counter 2
outputs the inverted value (b3.b2.bl) of the counter value in FIG. 1 as shown in Table 2.

Repeat counting from (1, 1, 1) to (0, 0, 0) t-t'.

Also, as a comparison circuit for each bit, an NMOS transistor M1. M2, M3. M4, M5. A wired AND circuit is constructed by using NAND circuits in which M6 are connected in series, and by connecting these in a wired manner and providing a pull-up resistor R between the common connection end and the power supply vDD. That is, the equivalent circuit diagram of this part is as shown in Fig. 2(b). Fig. 2(b) is further equivalent to Fig. 2(C), and Fig. 2(C) is equivalent to Fig. 2(C). It is equivalent to a diagram. That is, the circuit of FIG. 2(a) is equivalent to the circuit of FIG. 1 in terms of logic, and can be easily integrated into a semiconductor integrated circuit using MOS transistors and wired connections. In addition.

The D-type flip-flop 5 latches the input value at the input terminal at the input/output timing of the clock signal φ to the clock terminal GK and outputs it from the Q terminal, and the output easily fluctuates due to the transient operation of the binary counter 2. It is provided to prevent

FIG. 3 is a circuit diagram of still another embodiment of the coincidence detection circuit of the present invention.

This embodiment uses NOR circuits 11a, N11c, 12, which is equivalent to the logic circuit shown in FIG. Since the bits do not exist, the coincidence detection circuit outputs when a coincidence is detected for the upper bits bt to b3.

In addition, in FIGS. 1 and 3, the inverted signal ('j s+ ''; L 21 M I) is stored in the register 1, but a predetermined value C&3*&2+&s) is stored in the register 1. A function to invert and output the stored value may be added.

Furthermore, in the above embodiment, a 3-bit configuration is used as the register 1 and the binary counter 2, but
The number of bits is not limited to this, and the number of bits is arbitrary.

〔Effect of the invention〕

As explained above, by using an OR circuit as a comparison circuit for each bit, the present invention can significantly reduce the number of required transistor elements, and reduce the chip area when implemented as a semiconductor integrated circuit. It has the effect of

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the coincidence detection circuit of the present invention, FIG. 2(a) is a circuit diagram of another embodiment of the coincidence detection circuit of the present invention, and FIGS. 2(b) and (c) is the equivalent circuit of the part surrounded by the dotted line in FIG. 2(a), FIG. 3 is a circuit diagram of still another embodiment of the coincidence detection circuit of the present invention, FIG. 4 is a circuit diagram of a conventional example, Figure 5 shows the exclusive OR circuit 6 of Figure 4.
FIG. 6 is a circuit diagram showing a specific configuration of components a to 6c. 1...Register, 2...Binary counter, 3a-3C...OR circuit, 4...AND circuit, 5...D-type flip-flop, 11a-H0, 12-NOR circuit, M0-M6 ...NMO5) transistor, R...pull-up resistor, Voa...power supply, φ...clock signal. Patent applicant: NEC Corporation Representative: Susumu Uchihara, patent attorney Figure 1 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] A coincidence detection circuit that detects that the value of a binary counter consisting of a plurality of bits matches a predetermined value consisting of a plurality of bits, the circuit comprising: a logic inversion of the digital value of each bit of the predetermined value; a plurality of OR circuits that take each of the values and each of the values of each bit of the binary counter as inputs, calculate the logical sum of these, and output the result; A coincidence detection circuit that includes an AND circuit that performs AND output, or has a configuration equivalent to this in terms of logic circuitry.