JPH01101027A - Quantizer - Google Patents
QuantizerInfo
- Publication number
- JPH01101027A JPH01101027A JP25729687A JP25729687A JPH01101027A JP H01101027 A JPH01101027 A JP H01101027A JP 25729687 A JP25729687 A JP 25729687A JP 25729687 A JP25729687 A JP 25729687A JP H01101027 A JPH01101027 A JP H01101027A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- signal
- terminal
- quantizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000013139 quantization Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 210000000988 bone and bone Anatomy 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の属する技術分野
本発明はΔ−Σ形Ａ／Ｄ変換器の高精度化に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to increasing the accuracy of a Δ-Σ type A/D converter.
（２）従来技術とその問題点
従来、Δ−Σ形量化器にディザ信号を加算して、低振幅
信号入力時のＳ／Ｎ比を改善することは、Ｊ、Ｅｖｅｒ
ａｒｄの論文ｒＡ Ｓｉｎｇｌｅ−Ｃｈａｎｎｅｌ Ｐ
ＣＭ ＣｏｄｅｃＪＩＥＥＥ、 Ｊｏｕｒｎａｌ ｏｆ
ＳＣ，５Ｃ−１４＋ ＰＰ２５−３７． Ｆｅｂｒｕ
ａｒｙ１９７９、等に示されている。(2) Prior art and its problems Conventionally, adding a dither signal to a Δ-Σ type quantizer to improve the S/N ratio when a low amplitude signal is input is
ard's paper rA Single-Channel P
CM CodecJIEEE, Journal of
SC, 5C-14+ PP25-37. February
ary1979, etc.
図１は従来のディザ信号の加算法を示したものであり、
１１はΔ−Σ！子化器、１２はディジタルフィルタ、１
３は入力信号端子、１５はディザ信号入力端子、１４は
量子化値出力端子、１６は加算器である。Figure 1 shows the conventional dither signal addition method.
11 is Δ-Σ! childizer, 12 is a digital filter, 1
3 is an input signal terminal, 15 is a dither signal input terminal, 14 is a quantized value output terminal, and 16 is an adder.
従来は図１に示すようにシングルの量子化器の入力信号
にディザ信号を加算していた。通常、ディザ信号として
直流信号またはパルス信号を入力するが、従来方法の場
合は出力の量子化値にもディザ信号の量子化値が出てし
まうことになる。このため、従来の量子化器においては
量子化器の出力のあとに、直流オフセットを除去するオ
フセットキャンセル回路あるいはパルス信号を完全に除
去する能力を有するディジタルフィルタが必要であり、
このため大規模なディジタル回路を混載する必要が出て
くるため、ＬＳＩが大規模となり歩留りが劣化し、コス
トが上がり、消費電力が大きくなる。アナログ回路を有
する量子化器の場合ディジタル回路が大規模となるため
、ディジタル部からアナログ部への回り込み雑音が多く
なりＳ／Ｎ比が劣化すると言った欠点を有していた。Conventionally, a dither signal was added to the input signal of a single quantizer as shown in FIG. Normally, a DC signal or a pulse signal is input as a dither signal, but in the case of the conventional method, the quantized value of the dither signal also appears in the output quantized value. For this reason, conventional quantizers require an offset cancellation circuit that removes DC offsets or a digital filter that has the ability to completely remove pulse signals after the output of the quantizer.
For this reason, it becomes necessary to incorporate large-scale digital circuits, resulting in large-scale LSIs, lower yields, higher costs, and increased power consumption. In the case of a quantizer having an analog circuit, since the digital circuit is large-scale, there is a drawback that noise from the digital section to the analog section increases and the S/N ratio deteriorates.
（３）発明の目的
本発明の目的は、直流オフセットキャンセル回路、高性
能ディジタルフィルタ等のディザ信号加算に伴う付属回
路を用いない小規模の回路構成により、量子化出力から
ディザ信号成分を除去することのできる量子化器を提供
するものである。(3) Purpose of the Invention The purpose of the present invention is to remove the dither signal component from the quantized output using a small-scale circuit configuration that does not use ancillary circuits associated with dither signal addition such as a DC offset canceling circuit or a high-performance digital filter. This provides a quantizer that can perform
（４）発明の構成
（４−１）発明の特徴と従来技術との差異本発明は、入
力信号に加えられたディザ信号を量子化器の中で打ち消
し、低振幅入力時にも安定でかつディザ成分の除去され
た量子化出力を得ることを最も主要な特徴とし、前述の
ように入力信号にディザ信号を加えながら量子化出力に
はディザ信号成分が出力されないことが従来技術と大き
く異なる。(4) Structure of the Invention (4-1) Features of the Invention and Differences from the Prior Art The present invention cancels out the dither signal added to the input signal in the quantizer, and provides stable dithering even during low amplitude input. The main feature is to obtain a quantized output with components removed, and it differs greatly from the prior art in that while a dither signal is added to the input signal as described above, no dither signal component is output as a quantized output.
以下図面により本発明の実施例について詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.
（４−２）実施例
図２は本発明の第１の実施例であり、２０は差動入力シ
ングルエンド出力のΔ−Σ量子化器、２５はアナログ加
算器、２１は正相信号入力端子、２２は逆相信号入力端
子、２３はディザ信号入力端子、２４は量子化出力端子
である。(4-2) Embodiment FIG. 2 shows the first embodiment of the present invention, in which 20 is a differential input single-end output Δ-Σ quantizer, 25 is an analog adder, and 21 is a positive phase signal input terminal. , 22 is a negative phase signal input terminal, 23 is a dither signal input terminal, and 24 is a quantization output terminal.
図３は差動量子化器２０の具体的な回路例であり、３１
は差動入力、差動出力の増幅器、３２は比較器、３３は
積分用容量、３４は積分用抵抗、３５は帰還用ＤＡコン
バータ、３６はディジタル減算器、３７は正相信号入力
端子、３８は逆相信号入力端子、３９はシングルエンド
の量子化値出力端子である。ここで、入力信号をＡｉ、
ディザ信号をＡ４．正相の比較器出力をり、とし逆相の
比較器出力をり、とすると、端子３７の入力はＡ ｉ＋
Ａ ａ 、端子３８の入力は−Ａｔ＋Ａａとなる。正
相側と逆相側の量子化雑音をそれぞれＱ、、Ｑ、とする
と、Ｄ、、Ｄ、はＺ関数を用いて（１）、 （２）式で
表わすことができる。FIG. 3 shows a specific circuit example of the differential quantizer 20.
is a differential input and differential output amplifier, 32 is a comparator, 33 is an integrating capacitor, 34 is an integrating resistor, 35 is a feedback DA converter, 36 is a digital subtracter, 37 is a positive phase signal input terminal, 38 39 is a negative phase signal input terminal, and 39 is a single-ended quantized value output terminal. Here, the input signal is Ai,
Dither signal to A4. If the positive phase comparator output is R, and the negative phase comparator output is R, then the input to terminal 37 is A i+
Aa, the input to the terminal 38 becomes -At+Aa. Letting the quantization noise on the positive phase side and negative phase side be Q, , Q, respectively, D, , D can be expressed by equations (1) and (2) using the Z function.
Ｄｐ＝Ａｉ＋Ａｄ＋（１−ｚ−’）Ｑｐ （１
）Ｄ、＝−Ａ、＋Ａ、ｔ＋（１〜Ｚ−’）Ｑｌｌ
（２）ここで、端子３９の出力は、Ｄ、とり、、を減算
したものとなるので、端子３９の出力をＤｏとすると、
（３）式となる。Dp=Ai+Ad+(1-z-')Qp (1
)D, =-A, +A, t+(1~Z-')Qll
(2) Here, the output of the terminal 39 is the result of subtracting D, , , , so if the output of the terminal 39 is Do, then
The equation (3) is obtained.
Ｄ、＝Ｄ、＋Ｄ、＝２Ａ五十（１−Ｚ−つ（Ｑ、−Ｑ、
） （３）（３）式から解るように、本発明の第１の
実施例を用いることにより、ディザ信号骨Ａ４は比較器
出力の減算の際に打ち消され除去される。D, =D, +D, = 2A fifty (1-Z- (Q, -Q,
) (3) As can be seen from equation (3), by using the first embodiment of the present invention, the dither signal bone A4 is canceled out and removed during subtraction of the comparator output.
図４は本発明の第２の実施例であり、１１はシングルの
Δ−Σ量子化器、２５はアナログ加算器、２１は正相の
信号入力端子、２２は逆相の信号入力端子、２３はディ
ザ信号入力端子、２４は量子化値出力端子、４３はディ
ジタル減算器である。FIG. 4 shows a second embodiment of the present invention, in which 11 is a single Δ-Σ quantizer, 25 is an analog adder, 21 is a positive phase signal input terminal, 22 is a negative phase signal input terminal, 23 24 is a dither signal input terminal, 24 is a quantized value output terminal, and 43 is a digital subtracter.
図５は、シングルのΔ−Σ量子化器１１の回路例であり
、５１は通常の増幅器、３２は比較器、３３は積分用容
量、３４は積分用抵抗、３５は帰還ＤＡコンバータであ
り、３７は信号入力端子、３９は量子化値出力端子であ
る。この場合も第１の実施例と同様で、２１人力をＡｉ
、２２人力を−Ａム、２３人力をＡ４とし、Δ−Σ量子
化器１１のそれぞれの量子化雑音をＱｐ。FIG. 5 shows a circuit example of a single Δ-Σ quantizer 11, in which 51 is a normal amplifier, 32 is a comparator, 33 is an integrating capacitor, 34 is an integrating resistor, and 35 is a feedback DA converter. 37 is a signal input terminal, and 39 is a quantized value output terminal. This case is also similar to the first embodiment, and 21 manpower is
, 22 human power is -Am, 23 human power is A4, and each quantization noise of the Δ-Σ quantizer 11 is Qp.
Ｑ７とすると正相側の１１の出力り、と逆相側の出力Ｄ
７は（１）、 （２）式と全く同等となる。端子２４の
出力Ｄ０はり、とＤ７を減算したものであり、（３）式
と同等となる。このように本発明の第２の実施例を用い
れば、従来のΔ−Σ量子化器を２個用いて、第１の実施
例と同等なディザ信号成分の除去された量子化出力が得
られる。If it is Q7, the output of 11 on the positive phase side, and the output D on the negative phase side.
7 is completely equivalent to equations (1) and (2). It is obtained by subtracting the output D0 of the terminal 24 and D7, and is equivalent to equation (3). As described above, by using the second embodiment of the present invention, it is possible to obtain a quantized output with the dither signal component removed, which is equivalent to the first embodiment, by using two conventional Δ-Σ quantizers. .
なお、アナログ加算器２５は図５の点線で示したように
入力の積分用抵抗３４に並列に同様の抵抗を接続するの
みで実現することができる。また、減算部分はディジタ
ル値であるので、ディジタル減算器を用いて簡単に実現
することができる。Note that the analog adder 25 can be realized by simply connecting a similar resistor in parallel to the input integrating resistor 34, as shown by the dotted line in FIG. Furthermore, since the subtraction part is a digital value, it can be easily realized using a digital subtracter.
図６は本発明の第２の実施例の応用例である。FIG. 6 is an application example of the second embodiment of the present invention.
本例は特願昭６０−１８５０７号「オーバーサンプリン
グ形アナログ・ディジタル変換器」に示された多段量子
化ノイズ・シェービング方式に本発明を適用した例であ
る。ここで、６１は量子化雑音のアナログ出力端子付き
１重積分Δ−Σ量子化器であり、ａは量子化雑音のアナ
ログ出力端子、ｂはディジタルの量子化値出力端子であ
る。６３は微分器、６４はディジタルのＸ除算器、６５
はアナログの各除算器、６２はディジタル加算器である
。This example is an example in which the present invention is applied to the multi-stage quantization noise shaving method disclosed in Japanese Patent Application No. 18507/1983 entitled "Oversampling Type Analog-to-Digital Converter". Here, 61 is a single integral Δ-Σ quantizer with an analog output terminal for quantization noise, a is an analog output terminal for quantization noise, and b is a digital quantization value output terminal. 63 is a differentiator, 64 is a digital X divider, 65
are analog dividers, and 62 is a digital adder.
本例は３段の多段化を行い、３次のノイズ・シェービン
グ特性を得る例であり、その初段に本発明を用いている
。本発明を用いた利点は端子２４の出力に端子２３のデ
ィザ信号骨が出ないことである。This example is an example in which three stages are used to obtain third-order noise shaving characteristics, and the present invention is used in the first stage. An advantage of using the present invention is that the dither signal of the terminal 23 is not present in the output of the terminal 24.
初段の雑音の影響の大きな多段量子化ノイズ・シェービ
ング方式に対し、初段を差動化することにより、例えば
、ディジタル部からの回り込み雑音等の外部からの雑音
は差動部に対して同期雑音となるので、これを出力側の
減算部で打ち消し、高精度な出力を得ることを可能とし
ている。In contrast to the multi-stage quantization noise shaving method, where noise in the first stage has a large effect, by making the first stage differential, for example, external noise such as wrap-around noise from the digital section is treated as synchronous noise for the differential section. Therefore, this can be canceled out by the subtraction section on the output side, making it possible to obtain highly accurate output.
（発明の効果）
このように本発明を用いれば、ディザ信号成分は量子化
器内で打ち消され、量子化出力に出でこないため、直流
オフセットキャンセル回路およびディザ除去のための高
性能ディジタルフィルタ等を量子化器出力に付加する必
要がなくなる利点を有する。このため、この量子化器を
用いたＡ／Ｄ変換器の小形化が可能となるといった効果
を有している。また量子化器の差動化により外来雑音を
打ち消すことが可能となり、量子化器の高精度化が可能
となるといった効果も有している。(Effects of the Invention) As described above, when the present invention is used, the dither signal component is canceled within the quantizer and does not appear in the quantized output, so a DC offset cancel circuit and a high-performance digital filter for removing dither can be used. This has the advantage that there is no need to add quantizer output to the quantizer output. Therefore, it is possible to downsize an A/D converter using this quantizer. Further, the differentialization of the quantizer makes it possible to cancel out external noise, and has the effect of making it possible to increase the precision of the quantizer.
以上説明したように、入力にディザ信号を加えても、出
力にはディザ信号が出てこないため、従来必要であった
ディザ信号の除去回路を付加する必要がなく、ＬＳＩ化
する場合、占有面積が小さいという利点を有し、このた
め歩留りも良くなる。As explained above, even if a dither signal is added to the input, the dither signal does not appear at the output, so there is no need to add a dither signal removal circuit, which was required in the past. It has the advantage of being small, and therefore the yield is also improved.
さらに入力を差動化しているため、ディザ信号以外でも
、差動端子に同相で加わる雑音はディザ信号と同様に除
去され、高精度化が可能となる。Furthermore, since the input is made differential, even in addition to the dither signal, noise added to the differential terminals in the same phase is removed in the same way as the dither signal, making it possible to achieve higher precision.
図１はディザ信号の加算する従来の回路例を示すブロッ
ク図、図２は本発明の第１の実施例を示すブロック図、
図３は図２の実施例に用いる差動量子化器の構成例を示
す回路図、図４は本発明の第２の実施例を示すブロック
図、図５は図４の実施例に用いるΔ−Σ量子化器の構成
例を示す回路図、図６は本発明の第２の実施例の応用例
を示すブロック図である。
１１・・・Δ−Σ量子化器、 １２・・・直流オフセッ
トキャンセル回路またはディザを除去する能力を有する
ディジタルフィルタ、 １６・・・アナログ加算器、
１５・・・ディザ信号端子、 １３・・・入力信号端子
、 １４・・・量子化値出力端子、 ２０・・・差動量
子化器、 ２１・・・正相の入力信号端子、 ２２・・
・逆相の入力信号端子、 ２３・・・ディザ信号端子、
２４・・・量子化値出力端子、 ２５・・・アナログ
加算器、３１・・・差動入力差動出力増幅器、 ３２・
・・比較器、３３・・・積分用容量、 ３４・・・積分
用抵抗、 ３５・・・帰還用ＤＡコンバータ、 ３６・
・・ディジタル減算器、３７・・・正相入力端子、 ３
８・・・逆相入力端子、 ３９・・・量子化値出力端子
、 ４３・・・ディジタル減算器、５１・・・通常の増
幅器、 ６１・・・量子化雑音のアナログ出力端子付き
量子化器、 ６２・・・ディジタル加算器、 ６３・・
・ディジタル微分器、 ６４・・・ディジタル％除算器
、 ６５・・・アナログ２除算器。
特許出願人 日本電信電話株式会社FIG. 1 is a block diagram showing an example of a conventional circuit for adding dither signals, FIG. 2 is a block diagram showing a first embodiment of the present invention,
3 is a circuit diagram showing a configuration example of a differential quantizer used in the embodiment of FIG. 2, FIG. 4 is a block diagram showing a second embodiment of the present invention, and FIG. 5 is a Δ FIG. 6 is a block diagram showing an example of application of the second embodiment of the present invention. 11...Δ-Σ quantizer, 12... DC offset cancellation circuit or digital filter having the ability to remove dither, 16... Analog adder,
15... Dither signal terminal, 13... Input signal terminal, 14... Quantized value output terminal, 20... Differential quantizer, 21... Positive phase input signal terminal, 22...
・Reverse phase input signal terminal, 23... dither signal terminal,
24... Quantized value output terminal, 25... Analog adder, 31... Differential input differential output amplifier, 32.
... Comparator, 33... Integrating capacitor, 34... Integrating resistor, 35... Feedback DA converter, 36.
...Digital subtracter, 37... Positive phase input terminal, 3
8... Negative phase input terminal, 39... Quantized value output terminal, 43... Digital subtracter, 51... Ordinary amplifier, 61... Quantizer with analog output terminal for quantization noise , 62... digital adder, 63...
- Digital differentiator, 64... Digital % divider, 65... Analog 2 divider. Patent applicant Nippon Telegraph and Telephone Corporation
Claims (1)
Ｓ／Ｎ比を向上させるディザ信号を前記差動化された信
号入力端子に同相で入力するΔ−Σ量子化器と、該Δ−
Σ量子化器の差動化された量子化出力に対する相互減算
を行ってシングルエンド化出力を取り出す減算器とを備
えて、該減算器における減算により前記ディザ信号が打
ち消されて前記シングルエンド化出力には該ディザ信号
を含まない前記入力信号の量子化値が出力されるように
構成された量子化器。a Δ-Σ quantizer whose signal input terminals are differentiated and which inputs a dither signal in phase to the differential signal input terminals to improve the S/N ratio when the input signal is at a low level; −
a subtracter that performs mutual subtraction on the differential quantized output of the Σ quantizer to take out a single-ended output, and the subtraction in the subtracter cancels the dither signal and produces the single-ended output. A quantizer configured to output a quantized value of the input signal that does not include the dither signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25729687A JPH0710046B2 (en) | 1987-10-14 | 1987-10-14 | Quantizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25729687A JPH0710046B2 (en) | 1987-10-14 | 1987-10-14 | Quantizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01101027A true JPH01101027A (en) | 1989-04-19 |
| JPH0710046B2 JPH0710046B2 (en) | 1995-02-01 |
Family
ID=17304398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25729687A Expired - Lifetime JPH0710046B2 (en) | 1987-10-14 | 1987-10-14 | Quantizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0710046B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0295023A (en) * | 1988-09-30 | 1990-04-05 | Yokogawa Electric Corp | Sigmadelta modulation type a/d converter |
| WO2002078193A1 (en) * | 2001-03-28 | 2002-10-03 | Siemens Aktiengesellschaft | Noise-shaping method |
| CN101820268A (en) * | 2010-04-27 | 2010-09-01 | 广州市广晟微电子有限公司 | Circuit and method for correcting direct current of active RC filter |
-
1987
- 1987-10-14 JP JP25729687A patent/JPH0710046B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0295023A (en) * | 1988-09-30 | 1990-04-05 | Yokogawa Electric Corp | Sigmadelta modulation type a/d converter |
| WO2002078193A1 (en) * | 2001-03-28 | 2002-10-03 | Siemens Aktiengesellschaft | Noise-shaping method |
| CN101820268A (en) * | 2010-04-27 | 2010-09-01 | 广州市广晟微电子有限公司 | Circuit and method for correcting direct current of active RC filter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0710046B2 (en) | 1995-02-01 |
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