KR950002297B1 - Signal-delta analog/digital converter - Google Patents

Abstract

The A/D converter reducing the low frequency noise and the off-set error simultaneously by adding miniature circuit comprises a low pass filter (10) filtering the quantum error; an A/D convertor (20) digitizing the filtered signals from the low pass filter (10); a D/A converter (50) converting the digitized signal to feedback the signal; a correlated double sampling circuit (40) eliminating the device noise of the integrator and the off-set error; a control means (60) generating the timing pulses.

Description

Sigma-Delta Analog / Digital Converters

1 is a schematic diagram of a sigma-delta analogue / digital converter according to the present invention.

2 is a circuit diagram showing one embodiment of an integrator used in the analog / digital converter according to the present invention.

3 is a circuit diagram showing another embodiment of an integrator used in the analog / digital converter according to the present invention.

4 is a circuit diagram showing an example of an integrator used in an analog / digital converter according to a conventional chopper stabilization technique.

The present invention relates to an analog / digital converter, and more particularly, to a sigma-delta analog / digital converter that improves offset voltage and flicker noise by using correlated double sampling technology. (Sigma-Delta A / D converter).

In general, analog / digital converters (hereinafter referred to as A / D converters) for converting analog voltages into digital codes are commonly used in the measurement field, and include high-speed conversion, high resolution, low power consumption, and low quantization error. Required. In particular, high resolution has been rapidly advanced with the needs of users and the development of A / D converter technology.

However, the continuous pursuit of high resolution has emerged as an important factor in determining the characteristics of the A / D converter even the noises of the circuit elements which were not a problem before. For example, offset errors caused by low frequency noise and fluctuations in the characteristics of circuit elements.

Examples of conventional A / D converters proposed as a countermeasure against such low frequency noise and offset errors include US Pat. Nos. 4,939,516 and 4,943,807.

First, US Patent 4,939,516 (Title; CHOPPER STABILIZED DELTA-SIGMA ANALOG-TO-DIGILTAL CONVERTER), which is directly related to this invention, includes an analog modulator and a digital filter composed of two integrators, and the two integrators One integrator consists of a chopper stabilized differential amplifier and a capacitively switched input.

The configuration of the chopper stabilized differential amplifier is shown in FIG. Referring to FIG. 4, the clock frequency is controlled using a balanced mdulator composed of four switches SCA1, SCA2, SCB1, and SCB2 at the front of the op amp A1. It is separated from the input reference noise of the op amp A1 by moving to.

After that, it is amplified by the OP amplifier A1 and then modulated again by a balanced modulator composed of four switches (SCA3, SCA4, SCB3, SCB4) in front of the OP amplifier A2 to restore the input signal to its original band, Noise is pushed back to the clock frequency.

In general, since the low pass filter for passing only the desired baseband signal is connected to the output terminal of the OP amplifier A2, the input Leopard noise shifted to the clock frequency is eliminated. Thus, only pure input signals without input Leopard noise can be obtained.

Since the A / D converter using the conventional chopper stabilized differential amplifier requires at least eight switches, the hardware configuration is complicated, thereby increasing noise, and cannot eliminate offset voltage errors.

Conventional techniques related to the elimination of offset errors include the use of digital calibration circuits such as USP 4,943,807 (title; DIGITALLY CALIBRATED DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER), but this also requires a lot of hardware.

It is an object of the present invention to provide a sigma-delta analogue / digital converter which realizes an efficient circuit by simultaneously removing and distributing offset error and low frequency noise with the addition of simple hardware.

In order to achieve the above object, the present invention includes a low pass filter configured to low pass filter a quantization noise and a signal, and an A / D converter configured to quantize the low pass filtered result by the low pass filter. And a D / A converter that provides negative feedback to the analog input of the result of the analog signal being digitalized in the A / D converter, and removes device noise and offset error of the integrator configured in the low pass filter unit. A sigma delta analogue / digital converter including a correlated double sampling circuit, a digital filter for removing unnecessary portions of the quantized digital signal layer through the A / D converter, and a control unit for controlling timing of each unit. to provide.

In the above configuration, the integrator configured in the low pass filter section includes one or more OP amplifiers and means for distributing and eliminating noise and offset errors of the OP amplifiers.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a sigma-delta analogue / digital converter according to the present invention.

As shown in FIG. 1, the present invention is composed of a plurality of integrators and includes a low pass filter unit 10 for low pass filtering of quantization noise and a signal, and a low pass from the low pass filter unit 10. A / D converter 20 (hereinafter, referred to as ADC) for quantizing the filtered result, and D / A converter 50 for negative feedback of the analog signal from the analog signal to the analog input in the ADC 20 (50). (Hereinafter referred to as a DAC) and a correlated double sampling circuit 40 (hereinafter referred to as a CDS circuit) for removing device noise and offset errors of an op amp constituting an integrator configured in the low pass filter section 10. And a digital filter 30 for removing an unnecessary portion of the digital signal quantized by the ADC 20, and a control unit 60 for controlling the timing of each unit.

Here, the low pass filter unit may be composed of a plurality of integrators, and an example of the CDS circuit 40 applied to the integrator is illustrated in FIG. 2.

2 shows that the CDS circuit applied to the integrator, which is the core technology of the present invention, can be simply realized by adding only one switch S3 and one capacitor C3 in the basic integrator.

The integrator has an OP amplifier A1 having a feedback capacitor C3. The feedback capacitor C3 is connected between the output terminal OUT of the op amp A1 and the inverting input terminal − of which the non-inverting input terminal (+) is grounded through a switch S3. And the integrator has a sample end hold circuit with switched capacitor C1. One terminal of the switched capacitor C1 is connected to the other terminal of the switch S1 to which the analog input IN is applied as the one terminal and the other terminal of the switch S4 grounded, and at the same time the capacitor C1, ( It is connected to the non-inverting input terminal (-) of the OP amplifier A1 through C2). In addition, at one connection point of the switched capacitor C1 and the capacitor C2, one terminal is connected to the other terminal of the grounded switch S5 and at the same time, it is connected to the feedback capacitor C3 through the switch S2.

The switches S1, S3, and S5 are closed in accordance with the sample clock signal? 1, and the switches S2 and S4 are closed in accordance with the sample clock signal? 2. The clock signals are nonoverlapping clock signals generated by the control unit 60 of FIG. In other words, the switches S1, S3, and S5 are closed during Ф1, and the switches S2 and S4 are opened. And while in Ф2 it does the opposite.

Referring to FIGS. 1 and 2, the operation of the A / D converter in relation to the achievement of the object of the present invention will be described.

First, referring to FIG. 1, the analog input V _IN subtracts a value fed back through a previous quantized result, that is, a value fed back through a DAC 50 that converts the output of the ADC 20 back to an analog signal. After subtracting), the difference component is input to the integrator of the low pass filter unit 10 to perform integration. Since the analog signal at the integrator output is then integrated with the difference component (derivative value), the actual signal cancels the derivative and integration so that the normal signal is output, which is then quantized through the ADC 20 to enter the digital filter 30. do. On the other hand, the quantization noise generated in the ADC 20 is fed back through the DAC 50, through an integrator, and forms a loop (closed circuit) that is input to the ADC 20 again.

Therefore, the transfer characteristic between the output of the ADC 20 and the quantization noise is represented by 1 / (1 + G (s)) (where G (s) is a characteristic of the low pass filter unit 10 composed of an integrator). The output of the ADC 20 with respect to quantization noise exhibits a high pass filter characteristic. Therefore, the signal-to-noise ratio S / N in the desired band is improved compared to the case where the input signal V _IN is directly quantized through the ADC 20.

In FIG. 1, the role of the digital filter 30 is a low pass filter that removes noise components outside the desired signal band. The quantization noise generated by the ADC 20 can be reduced by high pass filtering, but since 1 / f noise (flicker noise), which is a device noise generated by the OP amplifier A1 constituting the integrator, is added to the input and outputted, In order to remove this component, the CDS circuit shown in FIG. 2 is used. In addition, there is a control unit 60 composed of control logic for controlling each block. The integrator may be configured in multiple stages according to the characteristics of the high pass filter in the overall configuration, or may be configured by replacing comparators and switches, respectively, when the ADC 20 and the DAC 50 are configured in 1 bit.

Referring to FIG. 2, the non-overlapping clock signals Ф1 and Ф2 are provided by the control unit 60. As already mentioned, the switches S1-S5 open and close by an innon-wrapping clock signal. First, the input voltage IN is charged to the capacitor C1 while the clock signal? 1 is high, that is, when the switches S1, S3, and S5 are closed. At the same time, the offset voltage Vos generated at the non-inverting input terminal (+) of the OP amplifier A1 is charged in the capacitor C2.

Next, while the clock signal Ф2 is high, that is, when the switches S4 and S2 are on, the input voltage IN charged in the capacitor C1 is transferred to the capacitor C3 so that the integral Is done. At this time, since the offset voltage Vos is charged in the capacitor C2, the voltage of the connection node between the capacitor C1 and the capacitor C2 is dissipated so that the offset voltage of the OP amplifier A1 disappears to obtain an accurate ground OV value. . That is, the input voltage IN charged in the capacitor C1 is completely discharged and transferred to the capacitor C3. In the conventional case in which such a circuit is not applied, an error occurs because the input voltage IN charged in the capacitor C1 is not completely discharged and the offset voltage Vos remains.

On the other hand, the non-inverting input (+) of the OP amplifier A1 is set to Vin, and the IN, which is the actual analog input, is set to ground to obtain the transfer characteristic between the 1 / f noise, which is the device noise, and the output. Expressed by the formula

Vo [n] = {C3 / (C1 + C3)} × {(Vi [n] + Vos)-(Vi [n-1] + Vos)} + {C3 / (C2 + C3)} × (Vi [ n-1] + Vos)-(Vi [n-1] + Vos)

Expressed as a function of Z, Vo (z) = ( It is represented by × Vi (z) + β × (z ⁻¹ ) × Vi (z) + K.

Therefore, the transfer characteristic is H (z) = ( It is represented by + β x Z ^-1 x Vi (z) + K.

here, = C3 / (C1 + C3), β =-{(C2 / (C2 + C3) + (C3 / (C1 + C3)}}

K =-{C2 / (C2 + C3) x Vos.

As shown in the above equation, since the transmission noise between the device noise and the output shows the characteristics of the high pass filter, the device noise in the desired baseband can be reduced.

4 illustrates a first differential integrator constituting a subtractor, a 1-bit DAC, a CDS circuit, and a low pass filter in the configuration shown in FIG. 1 to improve power noise characteristics.

4 is the same as that of FIG. 2 in the basic operation and configuration except that the signals are differentially inputted and differentially outputted, and thus detailed circuit configurations are omitted.

However, the operation of the 1-bit DAC and the subtractor will be described as a comparator when the DAC 50 of FIG. 1 is 1 bit. The comparator output is high (Q) or low (Q) depending on the result of the low pass filter. do. Depending on the result of the high (Q) or low (Q), the reference voltage (Vref) may be added to the input or subtracted. C _DAC charged in ^{- -} the comparator output is at a high (Q) when, the non-inverting input terminal (+) C _DAC ^+, which is filled in the C _DAC ⁺ Vref added to the input (IN ^+), C _DAC, Vref is input (iN ^-) it will be subtracted from. This results in addition to the differential input as a whole. When the comparator output is low (Q), the opposite is the case, and the result is that it is subtracted from the differential input.

As described above, the present invention can eliminate the low frequency noise with relatively simple hardware and improve the offset error without the need for the conventional digital calibration logic and the like, and realize the A / D converter having excellent characteristics with small chip size. Can be.

Claims (3)

A low pass filter unit 10 configured to low pass filter the quantization noise and the signal, an A / D converter 20 to quantize the low pass filtered result of the low pass filter unit 10, The integrator configured in the low pass filter unit 10 and the D / A converter 50 for negative feedback of the analog signal from the A / D converter 20 to the analog input. A correlated double sampling circuit 40 for removing device noise and offset errors, a digital filter 30 for removing an unnecessary portion of the quantized digital signal through the A / D converter 20, and the respective parts Sigma delta analogue / digital converter characterized in that it comprises a control unit (60) for controlling the timing of the. The sigma delta analogue of claim 1, wherein the integrator configured in the low pass filter unit 10 includes one or more OP amplifiers and means for distributing and eliminating noise and offset errors of the OP amplifiers. / Digital converter. The integrator configured in the low pass filter unit 10 includes an OP amplifier A1 having a feedback capacitor C3, and the feedback capacitor C3 has a non-inverting input terminal (+). Is connected between the output terminal (OUT) of the OP amplifier (A1) and its inverting input terminal (-) through ground (S3), and one terminal of the switched capacitor (C1) is connected to the analog input (IN). The other terminal and one terminal of the switch S1 applied as one terminal are connected to the other terminal of the grounded switch S4 and simultaneously connected to the non-inverting input terminal (-) of the OP amplifier A1 through the capacitor C2. At one connection terminal of the switched capacitor C1 and the capacitor C2, one terminal is connected to the other terminal of the grounded switch S5 and is connected to the feedback capacitor C3 through the switch S2. Sigma delta analogue / digital converter, characterized in that.