JPH0710046B2 - Quantizer - Google Patents
QuantizerInfo
- Publication number
- JPH0710046B2 JPH0710046B2 JP25729687A JP25729687A JPH0710046B2 JP H0710046 B2 JPH0710046 B2 JP H0710046B2 JP 25729687 A JP25729687 A JP 25729687A JP 25729687 A JP25729687 A JP 25729687A JP H0710046 B2 JPH0710046 B2 JP H0710046B2
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- Japan
- Prior art keywords
- output
- quantizer
- signal
- terminal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【発明の詳細な説明】 （１）発明の属する技術分野 本発明はΔ−Σ形A/D変換器の高精度化に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field to which the Invention belongs The present invention relates to high accuracy of a Δ-Σ type A / D converter.
（２）従来技術とその問題点 従来、Δ−Σ形量化器にディザ信号を加算して、低振幅
信号入力時のS/N比を改善することは、J.Everardの論文
「A Single-Channel PCM Codec」IEEE,Journal of SC,S
C-14,PP25-37,February 1979.等に示されている。(2) Conventional technology and its problems Conventionally, adding a dither signal to a Δ-Σ type quantizer to improve the S / N ratio at the time of inputting a low amplitude signal is described in J. Everard's paper “A Single- Channel PCM Codec "IEEE, Journal of SC, S
C-14, PP25-37, February 1979.
図１は従来のディザ信号の加算法を示したものであり、
11はΔ−Σ量子化器、12はディジタルフィルタ、13は入
力信号端子、15はディザ信号入力端子、14は量子化値出
力端子、16は加算器である。FIG. 1 shows a conventional dither signal addition method.
11 is a Δ-Σ quantizer, 12 is a digital filter, 13 is an input signal terminal, 15 is a dither signal input terminal, 14 is a quantized value output terminal, and 16 is an adder.
従来は図１に示すようにシングルの量子化器の入力信号
にディザ信号を加算していた。通常、ディザ信号として
直流信号またはパルス信号を入力するが、従来方法の場
合は出力の量子化値にもディザ信号の量子化値が出てし
まうことになる。このため、従来の量子化器においては
量子化器の出力のあとに、直流オフセットを除去するオ
フセットキャンセル回路あるいはパルス信号を完全に除
去する能力を有するディジタルフィルタが必要であり、
このため大規模なディジタル回路を混載する必要が出て
くるため、LSIが大規模となり歩留りが劣化し、コスト
が上がり、消費電力が大きくなる。アナログ回路を有す
る量子化器の場合ディジタル回路が大規模となるため、
ディジタル部からアナログ部への回り込み雑音が多くな
りS/N比が劣化すると言った欠点を有していた。Conventionally, a dither signal was added to the input signal of a single quantizer as shown in FIG. Normally, a DC signal or a pulse signal is input as the dither signal, but in the case of the conventional method, the quantized value of the dither signal will also appear in the quantized value of the output. Therefore, in the conventional quantizer, after the output of the quantizer, an offset cancel circuit for removing the DC offset or a digital filter having the ability to completely remove the pulse signal is required,
For this reason, it becomes necessary to embed a large-scale digital circuit, which results in a large-scale LSI, which deteriorates the yield, increases the cost, and increases the power consumption. In the case of a quantizer having an analog circuit, the digital circuit becomes large,
There was a drawback that the sneak noise from the digital section to the analog section increased and the S / N ratio deteriorated.
（３）発明の目的 本発明の目的は、直流オフセットキャンセル回路，高性
能ディジタルフィルタ等のディザ信号加算に伴う付属回
路を用いない小規模の回路構成により、量子化出力から
ディザ信号成分を除去することのきる量子化器を提供す
るものである。(3) Object of the Invention An object of the present invention is to remove a dither signal component from a quantized output by a small-scale circuit configuration that does not use an auxiliary circuit associated with dither signal addition such as a DC offset cancel circuit and a high-performance digital filter. It provides a quantum quantizer.
（４）発明の構成 （４−１）発明の特徴と従来技術との差異 本発明は、入力信号に加えられたディザ信号を量子化器
の中で打ち消し、低振幅入力時にも安定でかつディザ成
分の除去された量子化出力を得ることを最も主要な特徴
とし、前述のように入力信号にディザ信号を加えながら
量子化出力にはディザ信号成分が出力されないことが従
来技術と大きく異なる。(4) Configuration of the Invention (4-1) Difference between Features of Invention and Prior Art The present invention cancels a dither signal added to an input signal in a quantizer, and is stable and dithering even at low amplitude input. The most important feature is to obtain a quantized output from which components have been removed. As described above, the dither signal component is not output to the quantized output while adding the dither signal to the input signal, which is a great difference from the prior art.
以下図面により本発明の実施例について詳細に説明す
る。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
（４−２）実施例 図２は本発明の第１の実施例であり、20は差動入力シン
グルエンド出力のΔ−Σ量子化器、25はアナログ加算
器、21は正相信号入力端子、22は逆相信号入力端子、23
はディザ信号入力端子、24は量子化出力端子である。(4-2) Embodiment FIG. 2 is a first embodiment of the present invention, in which 20 is a differential input single-ended output Δ-Σ quantizer, 25 is an analog adder, and 21 is a positive phase signal input terminal. , 22 are negative phase signal input terminals, 23
Is a dither signal input terminal, and 24 is a quantization output terminal.
図３は差動量子化器20の具体的な回路例であり、31は差
動入力，差動出力の増幅器、32は比較器、33は積分用容
量、34は積分用抵抗、35は帰還用DAコンバータ、36はデ
ィジタル減算器、37は正相信号入力端子、38は逆相信号
入力端子、39はシングルエンドの量子化値出力端子であ
る。ここで、入力信号をAi，ディザ信号をAd、正相の比
較器出力をDpとして逆相の比較器出力をDnとすると、端
子37の入力はAi＋Ad，端子38の入力は−Ai＋Adとなる。
正相側と逆相側の量子化雑音をそれぞれQp，Qnとする
と、Dp，DnはＺ関数を用いて（１），（２）式で表わす
ことができる。FIG. 3 shows a specific circuit example of the differential quantizer 20, 31 is a differential input / output amplifier, 32 is a comparator, 33 is an integrating capacitor, 34 is an integrating resistor, and 35 is a feedback. DA converter, 36 is a digital subtractor, 37 is a positive-phase signal input terminal, 38 is a negative-phase signal input terminal, and 39 is a single-ended quantized value output terminal. Here, if the input signal is A i , the dither signal is A d , the positive-phase comparator output is D p , and the negative-phase comparator output is D n , the input of the terminal 37 is A i + A d and the input of the terminal 38 is A i + A d . The input is −A i + A d .
Assuming that the quantization noise on the positive phase side and the quantization noise on the negative phase side are Q p and Q n , respectively, D p and D n can be expressed by equations (1) and (2) using the Z function.
Dp＝Ai＋Ad＋（１−Z-1）Qp （１） Dn＝−Ai＋Ad＋（１−Z-1）Qn （２） ここで、端子39の出力は、DpとDnを減算したものとなる
ので、端子39の出力をDoとすると、（３）式となる。D p = A i + A d + (1-Z -1 ) Q p (1) D n = -A i + A d + (1-Z -1 ) Q n (2) Here, the output of the terminal 39 is Since D p and D n are subtracted, when the output of the terminal 39 is D o , equation (3) is obtained.
Do＝Dp−Dn＝２Ai＋（１−Z-1）（Qp−Qn） （３） （３）式から解るように、本発明の第１の実施例を用い
ることにより、ディザ信号分Adは比較器出力の減算の際
に打ち消され除去される。D o = D p −D n = 2A i + (1-Z −1 ) (Q p −Q n ) (3) As can be seen from the formula (3), by using the first embodiment of the present invention, , The dither signal component A d is canceled and removed when the comparator output is subtracted.
図４は本発明の第２の実施例であり、11はシングルのΔ
−Σ量子化器、25はアナログ加算器、21は正相の信号入
力端子、22は逆相の信号入力端子、23はディザ信号入力
端子、24は量子化値出力端子、43はディジタル減算器で
ある。FIG. 4 shows a second embodiment of the present invention, in which 11 is a single Δ
-Σ quantizer, 25 analog adder, 21 positive phase signal input terminal, 22 negative phase signal input terminal, 23 dither signal input terminal, 24 quantized value output terminal, 43 digital subtractor Is.
図５は、シングルのΔ−Σ量子化器11の回路例であり、
51は通常の増幅器、32は比較器、33は積分用容量、34は
積分用抵抗、35は帰還DAコンバータであり、37は信号入
力端子、39は量子化値出力端子である。この場合も第１
の実施例と同様で、21入力をAi、22入力を−Ai、23入力
をAdとし、Δ−Σ量子化器11のそれぞれの量子化雑音を
Qp，Qnとすると正相側の11の出力Dpと逆相側の出力Dnは
（１），（２）式と全く同等となる。端子24の出力Doは
DpとDnを減算したものであり、（３）式と同等となる。
このように本発明の第２の実施例を用いれば、従来のΔ
−Σ量子化器を２個用いて、第１の実施例と同等なディ
ザ信号成分の除去された量子化出力が得られる。FIG. 5 is a circuit example of a single Δ-Σ quantizer 11,
Reference numeral 51 is a normal amplifier, 32 is a comparator, 33 is an integrating capacitor, 34 is an integrating resistor, 35 is a feedback DA converter, 37 is a signal input terminal, and 39 is a quantized value output terminal. Also in this case
In the same manner as in the embodiment of (1), 21 inputs are A i , 22 inputs are −A i , and 23 inputs are A d, and the respective quantization noises of the Δ−Σ quantizer 11 are
Assuming Q p and Q n , the 11 outputs D p on the positive phase side and the outputs D n on the negative phase side are exactly the same as in equations (1) and (2). The output D o of terminal 24 is
It is a result of subtracting D p and D n , and is equivalent to the equation (3).
Thus, by using the second embodiment of the present invention, the conventional Δ
-Using two Σ quantizers, a quantized output from which the dither signal component is removed, which is equivalent to that in the first embodiment, is obtained.
なお、アナログ加算器25は図５の点線で示したように入
力の積分用抵抗34に並列に同様の抵抗を接続するのみで
実現することができる。また、減算部分はディジタル値
であるので、ディジタル減算器を用いて簡単に実現する
ことができる。The analog adder 25 can be realized only by connecting a similar resistor in parallel to the input integrating resistor 34 as shown by the dotted line in FIG. Further, since the subtraction part is a digital value, it can be easily realized by using a digital subtractor.
図６は本発明の第２の実施例の応用例である。本例は特
願昭60−18507号「オーバーサンプリング形アナログ・
ディジタル変換器」に示された多段量子化ノイズ・シェ
ーピング方式に本発明を適用した例である。ここで、61
は量子化雑音のアナログ出力端子付き１重積分Δ−Σ量
子化器であり、ａは量子化雑音のアナログ出力端子、ｂ
はディジタルの量子化値出力端子である。63は微分器、
64はディジタルの1/2除算器、65はアナログの1/2除算
器、62はディジタル加算器である。FIG. 6 is an application example of the second embodiment of the present invention. This example is Japanese Patent Application No. 60-18507 "Oversampling type analog
It is an example in which the present invention is applied to the multistage quantization noise shaping system shown in "Digital Converter". Where 61
Is a single integral Δ-Σ quantizer with an analog output terminal of quantization noise, a is an analog output terminal of quantization noise, and b is
Is a digital quantized value output terminal. 63 is the differentiator
64 is a digital 1/2 divider, 65 is an analog 1/2 divider, and 62 is a digital adder.
本例は３段の多段化を行い、３次のノイズ・シェーピン
グ特性を得る例であり、その初段に本発明を用いてい
る。本発明を用いた利点は端子24の出力に端子23のディ
ザ信号分が出ないことである。初段の雑音の影響の大き
な多段量子化ノイズ・シェーピング方式に対し、初段を
差動化することにより、例えば、ディジタル部からの回
り込み雑音等の外部からの雑音は差動部に対して同期雑
音となるので、これを出力側の減算部で打ち消し、高精
度な出力を得るとを可能としている。This example is an example in which multi-stages of three stages are performed to obtain a third-order noise shaping characteristic, and the present invention is used in the first stage. An advantage of using the present invention is that the output of terminal 24 does not output the dither signal of terminal 23. In contrast to the multi-stage quantization noise shaping method, which is greatly affected by noise in the first stage, by differentiating the first stage, external noise such as sneak-in noise from the digital section becomes synchronous noise to the differential section. Therefore, it is possible to cancel this by the subtraction unit on the output side and obtain a highly accurate output.
（発明の効果） このように本発明を用いれば、ディザ信号成分は量子化
器内で打ち消され、量子化出力に出てこないため、直流
オフセットキャンセル回路およびディザ除去のための高
性能ディジタルフィルタ等を量子化器出力に付加する必
要がなくなる利点を有する。このため、この量子化器を
用いたA/D変換器の小形化が可能となるといった効果を
有している。また量子化器の差動化により外来雑音を打
ち消すことが可能となり、量子化器の高精度化が可能と
なるといった効果も有している。(Effect of the Invention) As described above, when the present invention is used, the dither signal component is canceled in the quantizer and does not appear in the quantized output. Therefore, a DC offset cancel circuit and a high-performance digital filter for dither removal, etc. Has the advantage that it does not need to be added to the quantizer output. Therefore, there is an effect that the A / D converter using this quantizer can be miniaturized. In addition, it is possible to cancel the external noise by differentiating the quantizer, and it is possible to improve the accuracy of the quantizer.
以上説明したように、入力にディザ信号を加えても、出
力にはディザ信号が出てこないため、従来必要であった
ディザ信号の除去回路を付加する必要がなく、LSI化す
る場合、占有面積が小さいという利点を有し、このため
歩留りも良くなる。As explained above, even if a dither signal is added to the input, the dither signal does not appear at the output, so there is no need to add a dither signal removal circuit, which was required in the past. Has the advantage that it is small, which also improves the yield.
さらに入力を差動化しているため、ディザ信号以外で
も、差動端子に同相で加わる雑音はディザ信号と同様に
除去され、高精度化が可能となる。Further, since the input is differentiated, noise other than the dither signal, which is added to the differential terminals in the same phase, is removed in the same manner as the dither signal, and high accuracy can be achieved.
図１はディザ信号の加算する従来の回路例を示すブロッ
ク図、図２は本発明の第１の実施例を示すブロック図、
図３は図２の実施例に用いる差動量子化器の構成例を示
す回路図、図４は本発明の第２の実施例を示すブロック
図、図５は図４の実施例に用いるΔ−Σ量子化器の構成
例を示す回路図、図６は本発明の第２の実施例の応用例
を示すブロック図である。 11…Δ−Σ量子化器、12…直流オフセットキャンセル回
路またはディザを除去する能力を有するディジタルフィ
ルタ、16…アナログ加算器、15…ディザ信号端子、13…
入力信号端子、14は量子化値出力端子、20…差動量子化
器、21…正相の入力信号端子、22…逆相の入力信号端
子、23…ディザ信号端子、24…量子化値出力端子、25…
アナログ加算器、31…差動入力差動出力増幅器、32…比
較器、33…積分用容量、34…積分用抵抗、35…帰還用DA
コンバータ、36…ディジタル減算器、37…正相入力端
子、38…逆相入力端子、39…量子化値出力端子、43…デ
ィジタル減算器、51…通常の増幅器、61…量子化雑音の
アナログ出力端子付き量子化器、62…ディジタル加算
器、63…ディジタル微分器、64…ディジタル1/2除算
器、65…アナログ1/2除算器。1 is a block diagram showing an example of a conventional circuit for adding dither signals, FIG. 2 is a block diagram showing a first embodiment of the present invention,
3 is a circuit diagram showing a configuration example of a differential quantizer used in the embodiment of FIG. 2, FIG. 4 is a block diagram showing a second embodiment of the present invention, and FIG. 5 is a Δ used in the embodiment of FIG. FIG. 6 is a circuit diagram showing a configuration example of a −Σ quantizer, and FIG. 6 is a block diagram showing an application example of the second embodiment of the present invention. 11 ... Δ-Σ quantizer, 12 ... DC offset cancel circuit or digital filter having ability to remove dither, 16 ... Analog adder, 15 ... Dither signal terminal, 13 ...
Input signal terminal, 14 is a quantized value output terminal, 20 ... Differential quantizer, 21 ... Positive phase input signal terminal, 22 ... Negative phase input signal terminal, 23 ... Dither signal terminal, 24 ... Quantized value output Terminal, 25 ...
Analog adder, 31 ... Differential input differential output amplifier, 32 ... Comparator, 33 ... Integrating capacitance, 34 ... Integrating resistor, 35 ... Feedback DA
Converter, 36 ... Digital subtractor, 37 ... Positive phase input terminal, 38 ... Negative phase input terminal, 39 ... Quantized value output terminal, 43 ... Digital subtractor, 51 ... Normal amplifier, 61 ... Quantization noise analog output Quantizer with terminal, 62 ... Digital adder, 63 ... Digital differentiator, 64 ... Digital 1/2 divider, 65 ... Analog 1/2 divider.
Claims (1)
ベルのときにS/M比を向上させるディザ信号を前記差動
化された信号入力端子に同相で入力するΔ−Σ量子化器
と、該Δ−Σ量子化器の差動化された量子化出力に対す
る相互減算を行ってシングルエンド化出力を取り出す減
算器とを備えて、該減算器における減算により前記ディ
ザ信号が打ち消されて前記シングルエンド化出力には該
ディザ信号を含まない前記入力信号の量子化値が出力さ
れるように構成された量子化器。1. A Δ-Σ quantization in which a dither signal for improving the S / M ratio when a signal input terminal is differentiated and the input signal is at a low level is input in-phase to the differentiated signal input terminal. And a subtracter that performs mutual subtraction on the differential quantized output of the Δ-Σ quantizer to obtain a single-ended output, and the dither signal is canceled by the subtraction in the subtractor. And a quantizer configured to output a quantized value of the input signal that does not include the dither signal to the single-ended output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25729687A JPH0710046B2 (en) | 1987-10-14 | 1987-10-14 | Quantizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25729687A JPH0710046B2 (en) | 1987-10-14 | 1987-10-14 | Quantizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01101027A JPH01101027A (en) | 1989-04-19 |
| JPH0710046B2 true JPH0710046B2 (en) | 1995-02-01 |
Family
ID=17304398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25729687A Expired - Lifetime JPH0710046B2 (en) | 1987-10-14 | 1987-10-14 | Quantizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0710046B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0295023A (en) * | 1988-09-30 | 1990-04-05 | Yokogawa Electric Corp | Sigmadelta modulation type a/d converter |
| DE10115386A1 (en) * | 2001-03-28 | 2002-10-24 | Siemens Ag | Noise-shaping process |
| CN101820268B (en) * | 2010-04-27 | 2012-07-04 | 广州市广晟微电子有限公司 | Circuit and method for correcting direct current of active RC filter |
-
1987
- 1987-10-14 JP JP25729687A patent/JPH0710046B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01101027A (en) | 1989-04-19 |
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