JPH01100962A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPH01100962A JPH01100962A JP62259011A JP25901187A JPH01100962A JP H01100962 A JPH01100962 A JP H01100962A JP 62259011 A JP62259011 A JP 62259011A JP 25901187 A JP25901187 A JP 25901187A JP H01100962 A JPH01100962 A JP H01100962A
- Authority
- JP
- Japan
- Prior art keywords
- film
- nitride film
- polycrystalline silicon
- etching
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 150000004767 nitrides Chemical class 0.000 claims abstract description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 8
- 238000001259 photo etching Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 claims description 4
- 238000003860 storage Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 11
- 238000009413 insulation Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- XUIMIQQOPSSXEZ-OUBTZVSYSA-N silicon-29 atom Chemical compound [29Si] XUIMIQQOPSSXEZ-OUBTZVSYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置の製造方法に%、り、%に
1)ランジスタ型ダイナミック・メモリセルの製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of manufacturing a transistor type dynamic memory cell.
従来、この種の容量絶縁膜に窒化膜を用いる1トラ/・
ジスタ型ダイナミック・メモリセルの製造方法は、第2
図(a)乃至第2図(d)の様な製造方法に従っていた
。即ち、第2図(a)K示すように、電荷蓄積領域が各
々規定されている半導体基体21の主表面に、酸化膜2
2を被着し、その表面に第1のシリコン窒化膜23を被
着し、次に第2図(b)に示すように、第1の多結晶シ
リコン膜を成長させ、フォトエツチング法にて一部除去
し、容i−(セル)プレート24を形成し、次に第2図
(c)K示すように、熱酸化法により、容量プレート2
4の主表面及び側面に、絶縁用熱酸化膜27を被着し、
第1の多結晶シリコン24の下部以外の箇所の第1の窒
化JG!23、酸化膜22をウェットエツチング法によ
り除去し、熱葭化法により、表面にゲート熱酸化膜28
を被着し、次に第2の多結晶シリコン膜29を成長させ
た後、フォトエツチング法によりゲート電極を形成する
という方法をとっていた。Conventionally, a nitride film was used as this type of capacitive insulating film.
The manufacturing method of the transistor type dynamic memory cell is the second one.
The manufacturing method shown in Figures (a) to 2(d) was followed. That is, as shown in FIG. 2(a)K, an oxide film 2 is formed on the main surface of the semiconductor substrate 21 where each charge storage region is defined.
2, a first silicon nitride film 23 is deposited on its surface, and then, as shown in FIG. 2(b), a first polycrystalline silicon film is grown and then etched using a photoetching method. A portion of the capacitor plate 24 is removed, and then, as shown in FIG. 2(c)K, the capacitor plate 2
An insulating thermal oxide film 27 is deposited on the main surface and side surfaces of 4,
The first nitrided JG at a location other than the lower part of the first polycrystalline silicon 24! 23. The oxide film 22 is removed by a wet etching method, and a gate thermal oxide film 28 is formed on the surface by a thermal etching method.
After depositing a polycrystalline silicon film 29, and then growing a second polycrystalline silicon film 29, a gate electrode is formed by photo-etching.
前述した従来の製造方法は、第1の多結晶シリコン膜2
4に、絶縁用熱酸化g27を被着する際K、第1のシリ
コン窒化膜23が酸化されにくいため、多結晶シリコン
膜24の側面に被着する熱酸化[27が−様な厚さとな
らず、第2の多結晶シリコン膜29を被着した際、第1
の多結晶シリコン膜24との間が、いびつに入シ込んだ
形となり、絶縁用熱酸化膜27が十分な絶縁目的を果さ
ず、最悪の場合には第1の多結晶シリコン24と第2の
多結晶シリコン29とが短絡してしまうという欠点があ
りた。In the conventional manufacturing method described above, the first polycrystalline silicon film 2
4, when depositing the insulating thermal oxidation layer 27, the first silicon nitride film 23 is difficult to oxidize, so if the thermal oxidation layer 27 deposited on the side surface of the polycrystalline silicon film 24 has a --like thickness, First, when the second polycrystalline silicon film 29 is deposited, the first
The gap between the first polycrystalline silicon film 24 and the first polycrystalline silicon film 24 becomes distorted and the insulating thermal oxide film 27 does not serve a sufficient purpose of insulation, and in the worst case, the first polycrystalline silicon film 24 and There was a drawback that the polycrystalline silicon 29 of No. 2 would be short-circuited.
本発明の目的は、前記欠点が解決され、ゲート電極下の
絶縁膜が局部的に薄くなることがなく、絶縁破壊や短絡
事故が発生しないようにする半導体集積回路装置の製造
方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that solves the above-mentioned drawbacks, prevents the insulating film under the gate electrode from becoming locally thin, and prevents dielectric breakdown and short circuit accidents. It is in.
本発明の構成は、容量絶縁膜に窒化膜を用いるlトラン
ジスタ型ダイナミック優メモリセルのを形成する半導体
集積回路装置の製造方法において、半導体基体の主表面
に少なくとも第1の窒化膜を形成する工程と、さらに第
1の多結晶シリコン膜を形成し、この膜をフォトエツチ
ング法によってエツチングし、セルプレートを形成した
後、第2の窒化膜を表面に成長させ、シリカフィルムを
塗布し、熱処理を行った上で部分的にエツチングし、前
記第1の多結晶シリフン上の前記第2の窒化膜を露出さ
せ、この窒化膜のエツチングを行い、前記第1の多結晶
シリコン膜の主表面及び側面に接する前記第2の窒化膜
及び前記第1の窒化膜の一部を除去する工程と、さらに
前記主表面及び側面に酸化膜を形成する工程と、少なく
とも前記シリカフィルム、及びこの下の第2の窒化膜を
除去し、多結晶シリコン膜からなるゲート電極を形成す
る工程とを備えている。The structure of the present invention is a method of manufacturing a semiconductor integrated circuit device for forming a transistor-type dynamic memory cell using a nitride film as a capacitive insulating film, in which at least a first nitride film is formed on the main surface of a semiconductor substrate. Then, a first polycrystalline silicon film is formed, and this film is etched using a photoetching method to form a cell plate, and then a second nitride film is grown on the surface, a silica film is applied, and heat treatment is performed. After etching, the second nitride film on the first polycrystalline silicon film is partially etched, and this nitride film is etched to remove the main surface and side surfaces of the first polycrystalline silicon film. a step of removing a portion of the second nitride film and the first nitride film that are in contact with the silica film; further forming an oxide film on the main surface and side surfaces; The nitride film is removed and a gate electrode made of a polycrystalline silicon film is formed.
次に本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第1図(a)乃至第1図(h)は本発明の一実施例の半
導体集積回路装置の製造方法を工程順に示す断面図であ
る。まず第1図(a)において、半導体基体11の電荷
蓄積領域が各々規定されている主表面に、容量酸化膜1
2を被着し、前記酸化膜12上に第1のシリコン窒化膜
13を被着する。次に第1図(b)に示すように、第1
のシリコン窒化膜13上に、第1の多結晶シリコンを被
着し、フォトエツチング法により、容t(セル)プレー
ト14を形成する。次に第1図(c)において、−面に
第2の窒化膜15を被着した後、第1図(d)に示すよ
うに、シリカフィルム16を塗布し、熱処理をtlどこ
した。FIGS. 1(a) to 1(h) are cross-sectional views showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps. First, in FIG. 1(a), a capacitive oxide film 1 is formed on the main surface of the semiconductor substrate 11 where charge storage regions are respectively defined.
A first silicon nitride film 13 is deposited on the oxide film 12. Next, as shown in FIG. 1(b), the first
A first polycrystalline silicon is deposited on the silicon nitride film 13, and a cell plate 14 is formed by photoetching. Next, in FIG. 1(c), after a second nitride film 15 was deposited on the negative side, a silica film 16 was applied as shown in FIG. 1(d), and heat treatment was performed for a period of time.
次に第1図(e)において、多結晶シリコン14の主表
面に被着している105が露出するようにシリカフィル
ム16を部分的にエツチングした。第1図(f)におい
て、窒化膜エッチングにより、多結晶シリコン14の主
表面及び側面部分に被着している第2のシリコン窒化膜
15、及び第1のシリコン窒化膜13の一部を除去する
。第1図ωにおいて、熱酸化法によって、容量プレート
14の主表上面及び側面に、−様な厚さで形状の良い絶
縁酸化yX17を被着する。次に第1図(h)忙おいて
、容量部以外の部分の窒化膜15及び容量酸化膜12を
エッチングにより除去し、新たにゲート酸化膜18を熱
酸化法により被着した後、第2の多結晶シリコン膜19
を被着しフォトエツチング法により、ゲート電極を形成
する。Next, in FIG. 1(e), the silica film 16 was partially etched so that the portion 105 attached to the main surface of the polycrystalline silicon 14 was exposed. In FIG. 1(f), the second silicon nitride film 15 and a part of the first silicon nitride film 13 adhering to the main surface and side surfaces of the polycrystalline silicon 14 are removed by nitride film etching. do. In FIG. 1 ω, insulating oxide yX17 with a -like thickness and good shape is deposited on the upper and side surfaces of the main surface of the capacitor plate 14 by thermal oxidation. Next, in FIG. 1(h), the nitride film 15 and the capacitive oxide film 12 in the portion other than the capacitive part are removed by etching, and a new gate oxide film 18 is deposited by a thermal oxidation method. Polycrystalline silicon film 19
A gate electrode is formed by depositing and photo-etching.
以上説明したように、本発明は、絶縁酸化する第1の多
結晶シリコンの主表面及び側面の第2の窒化膜と、一部
の第1の窒化膜とを、除去し、この除去されたところに
酸化膜を形成することKよって、第1の多結晶シリコン
の側面に−様な厚さの酸化膜を破着することができ、第
2の多結晶シリコンとの十分な絶縁耐圧を得ることがで
きるという効果がある。As explained above, the present invention removes the second nitride film on the main surface and side surfaces of the first polycrystalline silicon to be insulated and oxidized, and a part of the first nitride film. However, by forming an oxide film thereon, it is possible to break the oxide film with a similar thickness to the side surface of the first polycrystalline silicon, thereby obtaining sufficient dielectric strength with respect to the second polycrystalline silicon. It has the effect of being able to
第1図(a)乃至第1図(h)は本発明の一実施例の半
導体集積回路装置の製造方法を工程順に示す断面図、第
2図(a)乃至第2図(d)は従来の製造方法を工程順
に示す断面図である。
11.21・・・・・・半導体基体、12.22・・・
・・・熱酸化膜、13,23・・・・・・第1のシリコ
ン窒化膜、105・・・・・・第2のシリコン窒化膜、
14.24・・・・・・多結晶シリコン膜(容量プレー
ト)、16・・・・・・シリカフィルム、17,27・
・・・・・絶縁熱酸化膜、18,28・・・・・・ゲー
ト熱酸化膜、19.29・・・・・・多結晶シリコン膜
(ゲート)。
代理人 弁理士 内 原 音
第1 図
第7図
第2図FIGS. 1(a) to 1(h) are cross-sectional views showing the manufacturing method of a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps, and FIGS. 2(a) to 2(d) are sectional views of the conventional FIG. 11.21... Semiconductor substrate, 12.22...
...Thermal oxide film, 13,23...First silicon nitride film, 105...Second silicon nitride film,
14.24...Polycrystalline silicon film (capacitance plate), 16...Silica film, 17,27.
...Insulating thermal oxide film, 18,28...Gate thermal oxide film, 19.29...Polycrystalline silicon film (gate). Agent Patent Attorney Uchihara Oto 1 Figure 7 Figure 2
Claims (1)
ダイナミック・メモリセルを形成する半導体集積回路装
置の製造方法において、電荷蓄積領域が各々規定されて
いる半導体基体の主表面に、酸化膜を被着し、前記酸化
膜上に第1の窒化膜を被着する工程と、前記第1の窒化
膜上に第1の多結晶シリコン膜を成長し、フォトエッチ
ング法にて前記電荷蓄積領域の対極としてのセルプレー
トを形成する工程と、次に第2の窒化膜を表面に被着し
、シリカフィルムを塗布し、熱処理した後にエッチバッ
クし、前記第1の多結晶シリコン膜上の前記第2の窒化
膜を露出させる工程と、第1の多結晶シリコン膜の主表
面及び側面に被着した前記第2の窒化膜をエッチングし
除去する工程と、前記エッチングにより露出した前記第
1の窒化膜をエッチングし除去する工程と、前記シリカ
フィルムをエッチングして除去する工程と、熱酸化法に
より前記第1の多結晶シリコンの主表面及び側面に酸化
膜を被着させる工程と、前記第2の窒化膜をエッチング
により除去する工程とを備えていることを特徴とする半
導体集積回路装置の製造方法。In a method for manufacturing a semiconductor integrated circuit device in which a one-transistor type dynamic memory cell is formed using a nitride film as part of a capacitor insulator, an oxide film is coated on the main surface of a semiconductor substrate in which charge storage regions are respectively defined. a step of depositing a first nitride film on the oxide film, growing a first polycrystalline silicon film on the first nitride film, and forming a counter electrode of the charge storage region by photo-etching. Next, a second nitride film is deposited on the surface, a silica film is applied, a heat treatment is performed, and then an etch back is performed to form a second cell plate on the first polycrystalline silicon film. a step of exposing the nitride film, a step of etching and removing the second nitride film deposited on the main surface and side surfaces of the first polycrystalline silicon film, and a step of etching and removing the first nitride film exposed by the etching. a step of etching and removing the silica film; a step of depositing an oxide film on the main surface and side surfaces of the first polycrystalline silicon by a thermal oxidation method; 1. A method for manufacturing a semiconductor integrated circuit device, comprising the step of removing a nitride film by etching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62259011A JPH01100962A (en) | 1987-10-13 | 1987-10-13 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62259011A JPH01100962A (en) | 1987-10-13 | 1987-10-13 | Manufacture of semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01100962A true JPH01100962A (en) | 1989-04-19 |
Family
ID=17328111
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62259011A Pending JPH01100962A (en) | 1987-10-13 | 1987-10-13 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01100962A (en) |
-
1987
- 1987-10-13 JP JP62259011A patent/JPH01100962A/en active Pending
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