JPH01100238U - - Google Patents
Info
- Publication number
- JPH01100238U JPH01100238U JP19525787U JP19525787U JPH01100238U JP H01100238 U JPH01100238 U JP H01100238U JP 19525787 U JP19525787 U JP 19525787U JP 19525787 U JP19525787 U JP 19525787U JP H01100238 U JPH01100238 U JP H01100238U
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- information
- predetermined time
- entry area
- watchdog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002159 abnormal effect Effects 0.000 claims 1
- 230000005856 abnormality Effects 0.000 claims 1
- 238000012544 monitoring process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 101100087530 Caenorhabditis elegans rom-1 gene Proteins 0.000 description 1
- 101100305983 Mus musculus Rom1 gene Proteins 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
- Multi Processors (AREA)
Description
第１図…本考案の概念を説明する図、第２図…
パラレルインタフエース方式のマルチＣＰＵ制御
装置の概要を示す図、第３図…共用ＲＡＭにおけ
るマツプを示す図、第４図…本考案の動作を説明
するフローチヤート。
図において、２―１はＣＰＵ―０、２―２はＲ
ＯＭ―０、２―３はバスアービトレーシヨン回路
、２―４はＣＰＵ―１、２―５はＲＯＭ―１、２
―６は共用ＲＡＭ、２―７は共用Ｉ／Ｏである。
Figure 1: Diagram explaining the concept of the present invention, Figure 2...
FIG. 3 is a diagram showing an overview of a parallel interface type multi-CPU control device; FIG. 3 is a diagram showing a map in a shared RAM; FIG. 4 is a flowchart explaining the operation of the present invention. In the figure, 2-1 is CPU-0, 2-2 is R
OM-0, 2-3 are bus arbitration circuits, 2-4 are CPU-1, 2-5 are ROM-1, 2
-6 is a shared RAM, and 2-7 is a shared I/O.
Claims (1)
いて、 共用ＲＡＭ内に少なくとも立ち上がり情報記入
エリアと各ＣＰＵ用のウオツチドツグ情報記入エ
リアを設けると共に、 自己ＣＰＵの立ち上がり終了情報を前記立ち上
がり情報記入エリアに記入する手段と、 自己ＣＰＵ以外のＣＰＵの立ち上がり終了情報
を第１の所定時間内に読み取る手段と、 第２の所定時間正常動作を継続した時自己ＣＰ
Ｕ用のウオツチドツグ情報記入エリアに所定情報
を記入する手段と、 前記第２の所定時間より大なる第３の所定時間
正常動作を継続した時自己ＣＰＵ以外のウオツチ
ドツグ情報記入エリアの情報を読み取る手段と、 前記第１の所定時間、第２の所定時間、第３の
所定時間を設定するタイマ手段とを設け、 前記立ち上がり終了情報が読み取れなかつた時
または前記ウオツチドツグ情報記入エリアから所
定情報が読み取れなかつた時、それらの情報に対
応するＣＰＵが異常であると判断する相互異常監
視機能を具備したことを特徴とするマルチＣＰＵ
制御装置。[Scope of Claim for Utility Model Registration] In a multi-CPU control device having a shared RAM, at least a start-up information entry area and a watchdog information entry area for each CPU are provided in the shared RAM, and the start-up completion information of its own CPU is used as the start-up information. means for writing in the entry area; means for reading startup completion information of a CPU other than the own CPU within a first predetermined time; and a means for reading start-up completion information of a CPU other than the own CPU within a first predetermined time;
means for writing predetermined information in the watchdog information entry area for the CPU; and means for reading information in the watchdog information entry area for a CPU other than its own CPU when normal operation continues for a third predetermined time period that is greater than the second predetermined time period. and timer means for setting the first predetermined time, the second predetermined time, and the third predetermined time, and when the start-up end information cannot be read or the predetermined information cannot be read from the watchdog information entry area. A multi-CPU characterized by having a mutual abnormality monitoring function that determines that the CPU corresponding to the information is abnormal when
Control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19525787U JPH01100238U (en) | 1987-12-23 | 1987-12-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19525787U JPH01100238U (en) | 1987-12-23 | 1987-12-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01100238U true JPH01100238U (en) | 1989-07-05 |
Family
ID=31485943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19525787U Pending JPH01100238U (en) | 1987-12-23 | 1987-12-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01100238U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57164345A (en) * | 1981-04-01 | 1982-10-08 | Nec Corp | Failure detecting system for composite microcomputer |
| JPS582047B2 (en) * | 1979-11-15 | 1983-01-13 | 三菱鉱業セメント株式会社 | Method for partially reinforcing cementum tubes |
| JPS6242242A (en) * | 1985-08-20 | 1987-02-24 | Matsushita Electric Ind Co Ltd | Supervisory unit for cpu abnormality |
-
1987
- 1987-12-23 JP JP19525787U patent/JPH01100238U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS582047B2 (en) * | 1979-11-15 | 1983-01-13 | 三菱鉱業セメント株式会社 | Method for partially reinforcing cementum tubes |
| JPS57164345A (en) * | 1981-04-01 | 1982-10-08 | Nec Corp | Failure detecting system for composite microcomputer |
| JPS6242242A (en) * | 1985-08-20 | 1987-02-24 | Matsushita Electric Ind Co Ltd | Supervisory unit for cpu abnormality |
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