JP7651292B2 - オンダイｅｃｃを選択的に無効化するための読み出しリトライ - Google Patents

オンダイｅｃｃを選択的に無効化するための読み出しリトライ Download PDF

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JP7651292B2
JP7651292B2 JP2020194691A JP2020194691A JP7651292B2 JP 7651292 B2 JP7651292 B2 JP 7651292B2 JP 2020194691 A JP2020194691 A JP 2020194691A JP 2020194691 A JP2020194691 A JP 2020194691A JP 7651292 B2 JP7651292 B2 JP 7651292B2
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command
memory
data
ecc
memory device
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JP2021179962A (ja
JP2021179962A5 (https=
Inventor
エス．ベインズ クルジット
アガールウォル ラジャット
リー ジョンウォン
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/1052—Bypassing or disabling error detection or correction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Detection And Correction Of Errors (AREA)
  • Memory System (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
JP2020194691A 2020-05-15 2020-11-24 オンダイｅｃｃを選択的に無効化するための読み出しリトライ Active JP7651292B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/875,642 2020-05-15
US16/875,642 US11314589B2 (en) 2020-05-15 2020-05-15 Read retry to selectively disable on-die ECC

Publications (3)

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JP2021179962A JP2021179962A (ja) 2021-11-18
JP2021179962A5 JP2021179962A5 (https=) 2025-02-06
JP7651292B2 true JP7651292B2 (ja) 2025-03-26

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US (2) US11314589B2 (https=)
EP (1) EP3910475B1 (https=)
JP (1) JP7651292B2 (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11048583B1 (en) * 2015-09-11 2021-06-29 Green Mountain Semiconductor Inc. Flexible, low-latency error correction architecture for semiconductor memory products
US11687407B2 (en) * 2020-08-27 2023-06-27 Micron Technologies, Inc. Shared error correction code (ECC) circuitry
US11907544B2 (en) 2020-08-31 2024-02-20 Micron Technology, Inc. Automated error correction with memory refresh
US11593197B2 (en) 2020-12-23 2023-02-28 Samsung Electronics Co., Ltd. Storage device with data quality metric and selectable data recovery scheme
WO2022139849A1 (en) 2020-12-26 2022-06-30 Intel Corporation Adaptive error correction to improve for system memory reliability, availability, and serviceability (ras)
CN114461440B (zh) * 2021-01-20 2022-11-04 沐曦集成电路(上海)有限公司 隐藏ecc编码延时的存储系统及方法
US12086026B2 (en) 2021-03-17 2024-09-10 Micron Technology, Inc. Multiple error correction code (ECC) engines and ECC schemes
US12210456B2 (en) 2021-03-26 2025-01-28 Intel Corporation Dynamic random access memory (DRAM) with scalable meta data
US12181966B2 (en) * 2021-04-08 2024-12-31 Intel Corporation Reduction of latency impact of on-die error checking and correction (ECC)
US11586502B2 (en) * 2021-05-19 2023-02-21 Micron Technology, Inc. Performance and deadlock mitigation during a memory die fail storm
JP7529628B2 (ja) * 2021-07-26 2024-08-06 株式会社日立製作所 プリント配線板及び情報処理装置
KR20230062172A (ko) * 2021-10-29 2023-05-09 삼성전자주식회사 메모리 장치, 이를 포함하는 메모리 모듈 및 메모리 컨트롤러의 동작 방법
CN116110473A (zh) * 2021-11-10 2023-05-12 三星电子株式会社 存储器装置、存储器系统和操作存储器系统的方法
US12242342B2 (en) * 2021-12-14 2025-03-04 Intel Corporation Fast memory ECC error correction
US11955989B2 (en) 2022-08-21 2024-04-09 Nanya Technology Corporation Memory device and test method thereof
US12411615B2 (en) * 2022-12-22 2025-09-09 SanDisk Technologies, Inc. Error correction methods for computational SSD supporting rapid file semantic search
US20260003727A1 (en) * 2024-06-28 2026-01-01 Qualcomm Incorporated Scalable architecture for configurable dynamic error correction coding (ecc) memory

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006191188A (ja) 2004-12-28 2006-07-20 Sharp Corp 画像転送装置および画像表示装置
JP2006227953A (ja) 2005-02-18 2006-08-31 Fujitsu Ltd ファイル制御システムおよびファイル制御装置
JP2006285976A (ja) 2005-03-10 2006-10-19 Matsushita Electric Ind Co Ltd 不揮発性記憶システム、不揮発性記憶装置、データ読出方法及び読出プログラム
JP2013065347A (ja) 2008-06-18 2013-04-11 Intel Corp 共有されるエラー・ビット・コードをもつ共通フレームにおいてデータおよびデータ・マスク・ビットを転送するためのシステム、方法および装置
US20170060680A1 (en) 2015-08-28 2017-03-02 Intel Corporation Memory device check bit read mode
JP2017529599A (ja) 2014-09-26 2017-10-05 インテル・コーポレーション メモリとホストシステムとの間のｅｃｃメタデータの交換
US20190347158A1 (en) 2018-05-10 2019-11-14 SK Hynix Inc. Memory device, memory system including the same and operation method of the memory system

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01209552A (ja) * 1988-02-17 1989-08-23 Hitachi Maxell Ltd 半導体ファイルメモリ装置
JPH11249821A (ja) * 1998-02-27 1999-09-17 Toshiba Corp データ記憶装置及び同装置に適用されるインタフェース条件設定方法
KR20130034522A (ko) * 2011-09-28 2013-04-05 삼성전자주식회사 비휘발성 메모리 장치의 데이터 리드 방법, 및 이를 수행하는 장치
US9811420B2 (en) 2015-03-27 2017-11-07 Intel Corporation Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)
US20170110178A1 (en) * 2015-09-17 2017-04-20 Intel Corporation Hybrid refresh with hidden refreshes and external refreshes
EP3453022B1 (en) 2016-05-02 2022-07-06 INTEL Corporation Internal error checking and correction (ecc) with extra system bits
KR102670661B1 (ko) * 2019-06-19 2024-05-31 삼성전자주식회사 반도체 메모리 장치 및 이를 포함하는 메모리 시스템
US11210167B2 (en) 2019-10-28 2021-12-28 Intel Corporation Memory wordline isolation for improvement in reliability, availability, and scalability (RAS)
US11599481B2 (en) * 2019-12-12 2023-03-07 Western Digital Technologies, Inc. Error recovery from submission queue fetching errors

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006191188A (ja) 2004-12-28 2006-07-20 Sharp Corp 画像転送装置および画像表示装置
JP2006227953A (ja) 2005-02-18 2006-08-31 Fujitsu Ltd ファイル制御システムおよびファイル制御装置
JP2006285976A (ja) 2005-03-10 2006-10-19 Matsushita Electric Ind Co Ltd 不揮発性記憶システム、不揮発性記憶装置、データ読出方法及び読出プログラム
JP2013065347A (ja) 2008-06-18 2013-04-11 Intel Corp 共有されるエラー・ビット・コードをもつ共通フレームにおいてデータおよびデータ・マスク・ビットを転送するためのシステム、方法および装置
JP2017529599A (ja) 2014-09-26 2017-10-05 インテル・コーポレーション メモリとホストシステムとの間のｅｃｃメタデータの交換
US20170060680A1 (en) 2015-08-28 2017-03-02 Intel Corporation Memory device check bit read mode
US20190347158A1 (en) 2018-05-10 2019-11-14 SK Hynix Inc. Memory device, memory system including the same and operation method of the memory system

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Publication number Publication date
EP3910475A1 (en) 2021-11-17
US11314589B2 (en) 2022-04-26
US20200278906A1 (en) 2020-09-03
US20220229724A1 (en) 2022-07-21
JP2021179962A (ja) 2021-11-18
US11966286B2 (en) 2024-04-23
EP3910475B1 (en) 2023-04-05

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