JP7640472B2 - 半導体装置、および半導体装置の作製方法 - Google Patents

半導体装置、および半導体装置の作製方法 Download PDF

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JP7640472B2
JP7640472B2 JP2021569603A JP2021569603A JP7640472B2 JP 7640472 B2 JP7640472 B2 JP 7640472B2 JP 2021569603 A JP2021569603 A JP 2021569603A JP 2021569603 A JP2021569603 A JP 2021569603A JP 7640472 B2 JP7640472 B2 JP 7640472B2
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insulator
oxide
conductor
region
transistor
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JPWO2021140407A5 (enExample
JPWO2021140407A1 (enExample
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舜平 山崎
慎也 笹川
涼太 方堂
智昭 森若
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Noodles (AREA)
  • Bipolar Transistors (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2021569603A 2020-01-10 2020-12-28 半導体装置、および半導体装置の作製方法 Active JP7640472B2 (ja)

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JP2025025809A JP2025071240A (ja) 2020-01-10 2025-02-20 半導体装置

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JP2020002997 2020-01-10
JP2020002997 2020-01-10
PCT/IB2020/062468 WO2021140407A1 (ja) 2020-01-10 2020-12-28 半導体装置、および半導体装置の作製方法

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JPWO2021140407A1 JPWO2021140407A1 (enExample) 2021-07-15
JPWO2021140407A5 JPWO2021140407A5 (enExample) 2023-12-27
JP7640472B2 true JP7640472B2 (ja) 2025-03-05

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US (1) US20230027402A1 (enExample)
JP (2) JP7640472B2 (enExample)
KR (1) KR20220124700A (enExample)
CN (1) CN114930547A (enExample)
WO (1) WO2021140407A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11929436B2 (en) 2021-02-02 2024-03-12 Taiwan Semiconductor Manufacturing Company Limited Thin transistor including a hydrogen-blocking dielectric barrier and methods for forming the same
US11856751B2 (en) * 2021-03-12 2023-12-26 Taiwan Semiconductor Manufacturing Company Limited Drain sharing for memory cell thin film access transistors and methods for forming the same
US12218252B2 (en) * 2021-08-30 2025-02-04 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure with source and drain electrode embedded within semiconductor layer and manufacturing method thereof
US12133396B2 (en) * 2021-08-30 2024-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device, integrated circuit and method of manufacturing the same
KR20250093510A (ko) * 2022-10-21 2025-06-24 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 기억 장치
CN119159015B (zh) * 2024-11-20 2025-06-27 江苏爱矽半导体科技有限公司 一种半导体封装机

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014195062A (ja) 2013-03-01 2014-10-09 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2015005738A (ja) 2013-05-20 2015-01-08 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
JP2015005733A (ja) 2013-05-20 2015-01-08 株式会社半導体エネルギー研究所 半導体装置
WO2019166914A1 (ja) 2018-02-28 2019-09-06 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

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Publication number Priority date Publication date Assignee Title
JPH09139508A (ja) * 1995-11-10 1997-05-27 Toyota Motor Corp 薄膜トランジスタの製造方法
US7419858B2 (en) * 2006-08-31 2008-09-02 Sharp Laboratories Of America, Inc. Recessed-gate thin-film transistor with self-aligned lightly doped drain
CN102804360B (zh) 2009-12-25 2014-12-17 株式会社半导体能源研究所 半导体装置
DE112011102644B4 (de) 2010-08-06 2019-12-05 Semiconductor Energy Laboratory Co., Ltd. Integrierte Halbleiterschaltung
US9343579B2 (en) * 2013-05-20 2016-05-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9954003B2 (en) * 2016-02-17 2018-04-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014195062A (ja) 2013-03-01 2014-10-09 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2015005738A (ja) 2013-05-20 2015-01-08 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
JP2015005733A (ja) 2013-05-20 2015-01-08 株式会社半導体エネルギー研究所 半導体装置
WO2019166914A1 (ja) 2018-02-28 2019-09-06 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

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JP2025071240A (ja) 2025-05-02
WO2021140407A1 (ja) 2021-07-15
JPWO2021140407A1 (enExample) 2021-07-15
US20230027402A1 (en) 2023-01-26
KR20220124700A (ko) 2022-09-14
CN114930547A (zh) 2022-08-19

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