JP7537559B2 - Gaming Machines - Google Patents

Description

The present invention relates to gaming machines.

Pachinko machines and slot machines are known as gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine that stores gaming balls given to a player, and the gaming balls stored in the tray storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out from, for example, a payout device to the tray storage section. In addition, a configuration in which an upper tray storage section and a lower tray storage section are provided as the tray storage section is also known in pachinko gaming machines, and in this case, the gaming balls stored in the upper tray storage section are guided to the gaming ball launching device, and the gaming balls that are surplus in the upper tray storage section are discharged to the lower tray storage section (for example, see Patent Document 1).

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the reels have stopped rotating corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

JP 2009-261415 A

Here, in gaming machines such as those exemplified above , it is necessary for the game to be played smoothly, and there is still room for improvement in this regard.

The present invention has been made in consideration of the above-mentioned circumstances, and has an object to provide a gaming machine that enables a game to be played in an optimal manner .

In order to solve the above problems, the present invention provides a game machine comprising: a front body of the game machine that can be opened and closed;
a game value providing means electrically connected to a predetermined detection means for detecting a game ball and for executing a process for providing a game value for a game;
A process execution means electrically connected to the game value providing means and executing a predetermined process;
In a gaming machine comprising:
The game value providing means includes:
a first reference information storage means for storing reference information, which is information used in a process for awarding the game value and is information to be referenced in response to detection by the predetermined detection means;
a first transmitting means for transmitting a reference information signal corresponding to the reference information stored in the first reference information storage means to the process executing means after a predetermined supply of power to the gaming machine is started and before execution of a predetermined process for progressing a game is started;
a second transmitting means for transmitting a predetermined information signal based on information acquired based on detection by the predetermined detecting means to the processing executing means;
a third transmitting means for transmitting a predetermined state signal to the process executing means when a front body of the gaming machine is opened and a predetermined state occurs;
a means for executing an erasure process of information in a predetermined storage area after a predetermined supply of power to the gaming machine is started and before the execution of the predetermined process is started based on the occurrence of a predetermined trigger;
Equipped with
The process execution means includes:
a second reference information storage means for storing reference information corresponding to the reference information signal transmitted from the game value providing means;
an execution means for executing the predetermined process based on the predetermined information signal transmitted from the second transmission means and the reference information stored in the second reference information storage means;
a processing result information storage means for storing processing result information which is information regarding a processing result of the predetermined processing by the execution means;
a means for storing information corresponding to the predetermined status signal transmitted from the third transmitting means when the predetermined status signal is received;
a means for erasing the processing result information stored in the processing result information storage means when a predetermined event occurs based on the performance of a predetermined operation;
Equipped with
The execution means executes the predetermined process when a predetermined execution trigger occurs, which is a trigger other than an execution instruction from the game value providing means and is a trigger for executing the predetermined process;
The game value providing means is a main control means for controlling the progress of a game,
The process execution means is a performance control means for controlling the execution of a performance,
the first transmitting means is configured to transmit the reference information signal to the processing executing means after the erasing process is executed when the predetermined trigger occurs;
The present invention is characterized in that, when a specified event occurs in which control of the progress of the game is stopped, the specified control for transmitting the specified information signal by the second transmitting means is not executed.

According to the present invention, it is possible to ensure that games are played in a favorable manner .

1 is a perspective view showing a pachinko machine according to a first embodiment. 1 is an exploded perspective view showing the main components of a pachinko machine. FIG. 2 is a front view showing the configuration of the game board. An explanatory diagram to explain the configuration regarding the discharge of game balls that have flowed down the game area. FIG. FIG. 2 is a block diagram showing the electrical configuration of the pachinko machine. FIG. 13 is an explanatory diagram for explaining the contents of various counters used in lotteries, etc. FIG. 4 is an explanatory diagram for explaining various tables stored in the main ROM. 4 is a flowchart showing a main process executed by a main CPU. 13 is a flowchart showing a setting value update process executed by a main CPU. 11 is a flowchart showing a timer interrupt process executed by a main CPU. 13 is a flowchart showing a special chart special power control process executed by the main CPU. This is a flowchart showing the special chart change start processing executed by the main CPU. This is an explanatory diagram to explain the configuration in which the detection results of the ball entry detection sensor are input to the main CPU. 13 is a flowchart showing the ball scoring detection process executed by the main CPU. A block diagram to explain the electrical configuration of a dispensing control device and various devices that communicate with the dispensing control device. 13 is a flowchart showing a timer interrupt process executed by the dispensing CPU. 4 is a block diagram for explaining an electrical configuration of a management IC. FIG. FIG. 2 is an explanatory diagram for explaining the configuration of an input port of a management side I/F; FIG. 2 is an explanatory diagram for explaining a configuration of a correspondence relationship memory; FIG. 2 is an explanatory diagram for explaining a configuration of a history memory; 13 is a flowchart showing a recognition process executed by a main CPU. 13 is a flowchart showing a management process executed by a management side CPU. 13A to 15D are time charts showing how information on the correspondence between the first to fifteenth buffers and the types of signals is stored in a correspondence memory. 13 is a flowchart showing a management output process executed by a main CPU. 13 is a flowchart showing a history setting process executed by a management CPU. 5A to 5E are time charts showing how history information is stored in a history memory. 10 is a flowchart showing a process of outputting a setting value update signal executed by a main CPU. 13 is a flowchart showing a setting update recognition process executed by a management CPU. 13 is a flowchart showing a display output process executed by a management CPU. 13 is a flowchart showing a display process executed by a management CPU. 13A is a flowchart showing a data output process executed by a main CPU, and FIG. 13B is a flowchart showing an external output process executed by a control CPU. 13 is an explanatory diagram for explaining various tables stored in a main ROM in the second embodiment. FIG. FIG. 13 is an explanatory diagram for explaining the configuration of a separate storage memory in the third embodiment. 13 is a flowchart showing a setting update recognition process executed by a management CPU. 13 is a flowchart showing a process of monitoring a repeated change executed by a management CPU; 13 is a flowchart showing a repeated change monitoring process executed by a main CPU in the fourth embodiment; 13 is a flowchart showing a setting update recognition process executed by a management CPU in the fifth embodiment. FIG. 23 is an explanatory diagram for explaining a configuration of a history memory in the sixth embodiment. 13 is a flowchart showing a history setting process executed by a management CPU. 13 is a flowchart showing a setting update recognition process executed by a management CPU. FIG. 23 is an explanatory diagram for explaining the configuration of a history memory in the seventh embodiment. 13 is a flowchart showing a setting update recognition process executed by a management CPU. FIG. 23 is an explanatory diagram for explaining the configuration of a history memory in the eighth embodiment. 13 is a flowchart showing a setting update recognition process executed by a management CPU. 13 is a flowchart showing a history setting process executed by a management CPU. 13 is a flowchart showing a display output process executed by a management CPU. FIG. 23 is an explanatory diagram for explaining the configuration of an input port of a management side I/F in the ninth embodiment. 13 is a flowchart showing a recognition process executed by a main CPU. 13 is a flowchart showing a management process executed by a management side CPU. 13A to 13H are time charts showing how information on the correspondence between the first to twelfth buffers and the signal types is stored in a correspondence memory. A block diagram to explain the configuration of the signal path that transmits the detection results of each ball entry detection sensor to the main CPU and the management IC in the 10th embodiment. A front view of the main control device in the eleventh embodiment. 10 is a block diagram for explaining the electrical configuration for performing various displays in the first to fourth notification display devices based on the control of an MPU. FIG. 13 is a flowchart showing a display process executed by a management CPU. 13 is a flowchart showing a setting value update process executed by a main CPU. (a) An explanatory diagram for explaining the display mode of the first to fourth notification display devices when the game history management results are displayed, and (b) an explanatory diagram for explaining the display mode of the first to fourth notification display devices when the setting state of the pachinko machine is changed. 6A to 6H are time charts showing how the first to fourth notification display devices are put into display states. 23A is an explanatory diagram for explaining the configuration of a first notification display device in the twelfth embodiment, and FIG. 23B is an explanatory diagram for explaining the configuration of a second notification display device. This is an explanatory diagram for explaining the display contents of the first alert display device and the second alert display device when the first to fourth alert display devices display the results of game history management and when they display that the setting state of the pachinko machine is in a changeable state in which it is possible to change the setting state. 13 is a flowchart showing a setting value update process executed by a main CPU. FIG. 23 is an explanatory diagram for explaining the configuration of an abnormality display area in the thirteenth embodiment. 13 is a flowchart showing an abnormality setting process executed by a main CPU. 13 is a flowchart showing an abnormality display process executed by a main CPU. 23 is a flowchart showing the management output process executed by the main CPU in the fourteenth embodiment. 13 is a flowchart showing a main process executed by a main CPU in another embodiment. FIG. 23 is an explanatory diagram for explaining the setting mode of programs and data in the main ROM in the fifteenth embodiment. FIG. 11 is an explanatory diagram for explaining a setting mode of each area in the main RAM. 11 is a flowchart showing a timer interrupt process executed by a main CPU. 13 is a flowchart showing a management process executed by a main CPU. 13 is a flowchart showing a management execution process executed by a main CPU. 11 is an explanatory diagram for explaining various areas of a work area for non-specific control used for managing game history. FIG. 13 is a flowchart showing a check process executed by a main CPU. 13 is a flowchart showing the normal goal entry management processing executed by the main CPU. 13 is a flowchart showing a result calculation process executed by a main CPU. 13 is a flowchart showing a display process executed by a main CPU. 23 is a flowchart showing a management process executed by a main CPU in the sixteenth embodiment. 23 is a flowchart showing a management execution process executed by a main CPU in the seventeenth embodiment. 23 is a flowchart showing the management execution process executed by the main CPU in the eighteenth embodiment. 23 is a flowchart showing a management execution process executed by a main CPU in the nineteenth embodiment. 13 is a flowchart showing a management process executed by a main CPU in the twentieth embodiment. 13 is a flowchart showing a management execution process executed by a main CPU. FIG. 23 is an explanatory diagram for explaining the electrical configuration in the twenty-first embodiment. 22 is a flowchart showing a main process executed by a main CPU in the twenty-second embodiment. 13 is a flowchart showing a setting value update process executed by a main CPU. 11 is a flowchart showing a timer interrupt process executed by a main CPU. 13 is a flowchart showing a setting confirmation process executed by a main CPU. 13 is a flowchart showing a RAM monitoring process executed by a main CPU. 13 is a flowchart showing a main process executed by a main CPU in another embodiment. 13 is a flowchart showing a setting value update process executed by a main CPU in another embodiment. A flowchart showing main processing executed by a main CPU in the 23rd embodiment. A flowchart showing a RAM monitoring process executed by the main CPU in the 24th embodiment. 25 is a flowchart showing a RAM monitoring process executed by a main CPU in the twenty-fifth embodiment. 13 is a flowchart showing a management execution process executed by a main CPU. 13 is a flowchart showing another monitoring process executed by a main CPU. A flowchart showing the management process executed by the main CPU in the 26th embodiment. 23 is a flowchart showing the management process executed by the main CPU in the twenty-seventh embodiment. A flowchart showing the management processing executed by the main CPU in the 28th embodiment. A flowchart showing the management process executed by the main CPU in the twenty-ninth embodiment. 30 is a flowchart showing a main process executed by a main CPU in the 30th embodiment. 10 is a flowchart showing a power outage information storage process executed by a main CPU. 1A is a block diagram for explaining the configuration of an MPU, and FIG. 1B is a time chart showing the output of a reset signal by a reset signal output unit. 11 is a flowchart showing a timer interrupt process executed by a main CPU. 13 is a flowchart showing a setting monitoring process executed by a main CPU. 13 is a flowchart showing a management process executed by a main CPU. 13 is a flowchart showing a management execution process executed by a main CPU. 13 is a flowchart showing another monitoring process executed by a main CPU. 31 is a flowchart showing a main process executed by a main CPU in the thirty-first embodiment. 13 is a flowchart showing a clearing process executed by a main CPU when an abnormality occurs. 13 is a flowchart showing a clearing process for non-specific control executed by a main CPU. 32 is a flowchart showing a power outage information storage process executed by a main CPU in the 32nd embodiment. 13 is a flowchart showing a checksum monitoring process executed by a main CPU. 13 is a flowchart showing a clearing process for non-specific control executed by a main CPU. A flowchart showing a main process executed by a main CPU in the thirty-third embodiment. 13 is a flowchart showing a setting confirmation process executed by a main CPU. 13 is a flowchart showing a setting value update process executed by a main CPU. 11 is a flowchart showing a first timer interrupt process executed by a main CPU. 13 is a flowchart showing a setting monitoring process executed by a main CPU. FIG. 2 is a block diagram for explaining a configuration for controlling the display of various display circuits by a main CPU. FIG. 1A is an explanatory diagram for explaining various buffers provided in a work area for specific control, and FIG. 1B is an explanatory diagram for explaining various memory areas provided in a work area for non-specific control. FIG. 2 is an explanatory diagram for explaining an electrical configuration of a display IC. (a) to (g) are time charts showing how type data and display data are transmitted from the main CPU to the display IC and how the display data transmitted from the display IC is received by the first display circuit or the second display circuit. 13 is a flowchart showing a second timer interrupt process executed by a main CPU. (a) is an explanatory diagram for explaining the display contents of the first to fourth notification display devices in a situation where the setting value is updated, and (b) is an explanatory diagram for explaining the display contents of the first to fourth notification display devices in a situation where the setting value is confirmed. A flowchart showing a setting value update process executed by the main CPU in the thirty-fourth embodiment.

First Embodiment
A first embodiment of a pachinko gaming machine (hereinafter referred to as a "pachinko machine"), which is a type of gaming machine, will be described in detail below with reference to the drawings. Fig. 1 is a perspective view of a pachinko machine 10, and Fig. 2 is a perspective view showing the main components of the pachinko machine 10 in an exploded form. For convenience, Fig. 2 omits the components within the play area PA of the pachinko machine 10.

As shown in FIG. 1, a pachinko machine 10 has an outer frame 11 that forms the outer shell of the pachinko machine 10, and a gaming machine main body 12 that is attached to the outer frame 11 so that it can rotate forward. The outer frame 11 is made of wooden boards connected at all four sides and has a rectangular frame shape. The pachinko machine 10 is installed in an amusement hall by attaching and fixing the outer frame 11 to an island facility. Note that the outer frame 11 is not a required component of the pachinko machine 10, and the outer frame 11 may be attached to the island facility of the amusement hall.

As shown in FIG. 2, the gaming machine main body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. The inner frame 13 of the gaming machine main body 12 is rotatably supported by the outer frame 11. In detail, the inner frame 13 can be rotated forward with the left side as the base end and the right side as the tip end when viewed from the front.

The front door frame 14 is rotatably supported by the inner frame 13, and can be rotated forward with the left side as the base end and the right side as the tip end when viewed from the front. The back pack unit 15 is rotatably supported by the inner frame 13, and can be rotated backward with the left side as the base end and the right side as the tip end when viewed from the front.

The gaming machine main body 12 is provided with a locking device at its rotating tip, which has the function of locking the gaming machine main body 12 so that it cannot be opened relative to the outer frame 11, and also has the function of locking the front door frame 14 so that it cannot be opened relative to the inner frame 13. Each of these locked states is released by using an unlocking key to unlock the cylinder lock 17 exposed on the front of the pachinko machine 10.

Next, we will explain the configuration of the front side of the gaming machine main body 12.

The inner frame 13 is mainly composed of a resin base 21 whose outer shape is almost the same as that of the outer frame 11. A roughly elliptical window hole 23 is formed in the center of the resin base 21. A game board 24 is removably attached to the resin base 21. The game board 24 is made of plywood, and a game area PA formed on the front side of the game board 24 is exposed to the front side of the inner frame 13 through the window hole 23 of the resin base 21.

Here, the configuration of the game board 24 will be explained based on Figure 3. Figure 3 is a front view of the game board 24.

An inner rail section 25 and an outer rail section 26 are attached to the game board 24 so as to define a part of the outer edge of the game area PA, and the inner rail section 25 and the outer rail section 26 form a guide rail as a guide means. Game balls launched from a game ball launching mechanism 27 (see Figure 2) attached below the window hole 23 in the resin base 21 are guided to the upper part of the game area PA by the guide rail.

The game ball launching mechanism 27 includes a launching rail 27a extending toward the guide rail, a ball feeder 27b that supplies game balls stored in the upper tray 55a (described later) onto the launching rail 27a, and a solenoid 27c, which is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the guide rail. The solenoid 27c is driven and controlled by rotating a launching operation device (or operation handle) 28 provided on the front door frame 14, and the game balls are launched.

The game board 24 has multiple openings of various sizes that penetrate in the front-to-rear direction. Each opening is provided with a general winning port 31, a special electric winning device 32, a first operating port 33, a second operating port 34, a through gate 35, a variable display unit 36, a special chart unit 37, and a general chart unit 38. There are a total of four general winning ports 31, and one of each of the others.

Even if a ball enters the through gate 35, no game balls are paid out. On the other hand, when balls enter the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34, a predetermined number of game balls are paid out. Specifically, when one game ball enters the first operating opening 33 or when one game ball enters the second operating opening 34, one prize ball is paid out, when one game ball enters the general winning opening 31, ten prize balls are paid out, and when one game ball enters the special electric winning device 32, fifteen prize balls are paid out.

The number of prize balls is arbitrary. For example, the second actuation port 34 may be configured to have a smaller number of prize balls than the first actuation port 33, or the second actuation port 34 may be configured to have a larger number of prize balls than the first actuation port 33.

In addition, an outlet 24a is provided at the bottom of the game board 24, and game balls that do not enter the various winning holes are discharged from the game area PA through the outlet 24a. In addition, numerous nails 24b are planted on the game board 24 to appropriately disperse and adjust the falling direction of the game balls, and various components such as windmills are also arranged.

Here, "ball entry" means that the game ball passes through a specified opening, and includes not only the case where the game ball passes through an opening and is discharged from the game area PA, but also the case where the game ball continues to flow down the game area PA without being discharged from the game area PA after passing through an opening. However, in the following explanation, in order to clearly distinguish from the game ball entering the outlet 24a, the game ball entering the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the through gate 35 will also be referred to as "winning."

The first actuation port 33 and the second actuation port 34 are united as an actuation port device and installed on the game board 24. Both the first actuation port 33 and the second actuation port 34 are open upward. In addition, both actuation ports 33, 34 are lined up vertically with the first actuation port 33 facing upward. The second actuation port 34 is provided with a normal power device 34a as a guide piece consisting of a pair of movable pieces on the left and right. When the normal power device 34a is in a closed state, the game ball cannot enter the second actuation port 34, but when the normal power device 34a is in an open state, the game ball can enter the second actuation port 34.

A through gate 35 is provided upstream of the second operating port 34 in the flow direction of the game ball. The through gate 35 has a through hole (not shown) that penetrates vertically, and a game ball that enters the through gate 35 flows down the game area PA after entering. This makes it possible for a game ball that enters the through gate 35 to enter the second operating port 34.

When a ball wins the through gate 35, the normal power role 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is held when a ball wins the through gate 35, and a changing image is displayed on the normal map display section 38a of the normal map unit 38 located in the lower right corner of the play area PA, an area where the game ball does not pass. Then, when the result of the internal lottery is a winning electric role release, the stop result corresponding to that result is displayed, and the changing display on the normal map display section 38a ends, the normal power open state is entered. In the normal power open state, the normal power role 34a is opened in a predetermined manner.

The map display unit 38a is configured with a segment display in which a number of LED display segments are arranged in a predetermined manner, but is not limited to this and may be configured with other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT or a dot matrix display. The pattern displayed on the map display unit 38a may be a number of different characters, a number of symbols, a number of characters, or a number of colors that are switched between.

In the normal map unit 38, a normal map reserve display section 38b is provided adjacent to the normal map display section 38a. A maximum of four game balls that enter the through gate 35 are reserved, and the number of reserved balls is displayed by lighting up the normal map reserve display section 38b.

A winning lottery is triggered by the entry into the first actuation port 33 or the second actuation port 34. The lottery result is then displayed clearly through the display effects on the special symbol unit 37 and the symbol display device 41 of the variable display unit 36.

Regarding the special chart unit 37 in detail, the special chart unit 37 is provided with a special chart display section 37a. The display area of the special chart display section 37a is narrower than the display surface 41a of the pattern display device 41. In the special chart display section 37a, a winning lottery is held by triggering the winning of the first operating port 33 or the winning of the second operating port 34, and a variable display of the pattern or a predetermined display is performed. Then, the result corresponding to the lottery result is displayed. The special chart display section 37a is configured with a segment display in which a plurality of display segments using LEDs are arranged in a predetermined manner, but is not limited to this, and may be configured with other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT or a dot matrix display device. In addition, the pattern displayed on the special chart display section 37a may be configured to display multiple types of letters, multiple types of symbols, multiple types of characters, or multiple types of colors.

In the special chart unit 37, a special chart reserve display section 37b is provided adjacent to the special chart display section 37a. The number of game balls that enter the first operating port 33 or the second operating port 34 is reserved up to a maximum of four, and the number of reserved balls is displayed by lighting up the special chart reserve display section 37b.

Regarding the pattern display device 41 in detail, the pattern display device 41 is configured as a liquid crystal display device equipped with a liquid crystal display, and the display content is controlled by a display control device described later. Note that the pattern display device 41 is not limited to a liquid crystal display device, and may be other display devices having a display screen such as a plasma display device, an organic EL display device, or a CRT, or may be a dot matrix display device.

In the pattern display device 41, when the special pattern display unit 37a displays a variable or predetermined pattern based on the winning of the first operation port 33 or the winning of the second operation port 34, the pattern display device 41 displays a variable or predetermined pattern accordingly. For example, the display surface 41a of the pattern display device 41 has three pattern rows, an upper row, a middle row, and a lower row, set as a plurality of display areas, and in each pattern row, main patterns numbered "1" to "9" are scrolled and displayed in ascending or descending order. In this scroll display, the scroll display of all pattern rows is started first, and the scroll display is switched to standby display in the order of the upper pattern row → the lower pattern row → the middle pattern row, and finally, the scroll display is ended with a predetermined pattern being statically displayed in each pattern row. Then, in a game round in which the game result is a jackpot result, a combination of predetermined patterns is displayed stationary on a valid line set in advance on the display surface 41a of the pattern display device 41. Specifically, in the case of the most favorable jackpot result described below, the same odd number symbol combination is displayed, in the case of a low probability jackpot result described below, the same even number symbol combination is displayed, and in the case of a low prize high probability jackpot result described below, a symbol combination that is not the same but would not be displayed in the case of a low prize high probability jackpot result is displayed.

In addition, the pattern display device 41 not only performs display effects triggered by winning the first actuation port 33 or the second actuation port 34, but also performs display effects during the opening and closing execution mode to which the game is switched after a winning combination is achieved. In addition, based on winning the actuation port 33, 34, display is started on the special pattern display unit 37a and the pattern display device 41, and one game round is played until a predetermined result is displayed and the game ends. In addition, the manner of the variable display of the patterns on the pattern display device 41 is not limited to the above and is arbitrary, and the number of pattern rows, the direction of the variable display of the patterns in the pattern rows, the number of patterns in each pattern row, etc. can be changed as appropriate. In addition, the patterns displayed by the pattern display device 41 are not limited to the above patterns, and for example, a configuration in which only numbers are displayed as patterns may be used.

When a big jackpot is won in a lottery based on winning the first operating port 33 or the second operating port 34, the mode transitions to an open/close execution mode in which winning is possible in the special electric winning device 32. The special electric winning device 32 has a large winning port (not shown) that leads to the back side of the game board 24, and an open/close door 32a that opens and closes the large winning port. The open/close door 32a is arranged in either a closed state or an open state. Specifically, the open/close door 32a is normally in a closed state in which game balls cannot win, and is switched to an open state in which game balls can win if an internal lottery is selected to transition to the open/close execution mode. Incidentally, the open/close execution mode is a mode to which the mode transitions when a winning result is obtained. Note that while winning is not impossible in the closed state, it may be configured to be in a state in which winning is more difficult than in the open state.

Figure 4 is an explanatory diagram to explain the configuration regarding the discharge of game balls that have flowed down the game area PA.

As already explained, a game ball that enters any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is discharged from the game area PA. In other words, a game ball that is launched from the game ball launching mechanism 27 and flows into the game area PA is discharged from the game area PA by entering any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a. A game ball that enters any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is guided to the back side of the game board 24.

On the back of the game board 24, discharge passages 42-48 are formed corresponding to the general winning port 31, the special winning device 32, the first operating port 33, the second operating port 34, and the outlet 24a, respectively. Game balls that flow into the discharge passages 42-48 flow down the discharge passages 42-48 and are guided to the lower end of the game board 24 on the back side of the game board 24, and are collected in a discharge ball collection section (not shown). The game balls collected in the discharge ball collection section are then discharged to a ball circulation device of the island equipment where the pachinko machine 10 is installed in the game hall.

Each discharge passage section 42-48 is provided with various detection sensors 42a-48a for detecting game balls. These discharge passage sections 42-48 and detection sensors 42a-48a will be described below. As already explained, four general winning openings 31 are provided, and therefore discharge passage sections 42-44 exist corresponding to each of the four. In this case, one detection sensor 42a, 43a is provided for each of the first discharge passage section 42 corresponding to the leftmost general winning opening 31 and the second discharge passage section 43 corresponding to the general winning opening 31 adjacent to it on the right. Specifically, the first winning opening detection sensor 42a is provided so that its detection range is located midway through the first discharge passage section 42, and the second winning opening detection sensor 43a is provided so that its detection range is located midway through the second discharge passage section 43. A game ball that enters the leftmost general winning opening 31 is detected by the first winning opening detection sensor 42a while passing through the first discharge passage section 42, and a game ball that enters the general winning opening 31 adjacent to the left is detected by the second winning opening detection sensor 43a while passing through the second discharge passage section 43. In addition, a third discharge passage section 44 is provided for the two general winning openings 31 on the right side, which are formed to merge at an intermediate position. The third discharge passage section 44 has an entrance side area corresponding to each of the two general winning openings 31, and the entrance side areas merge midway to form one exit side area. A third winning opening detection sensor 44a is provided so that a detection range exists at an intermediate position of the exit side area in the third discharge passage section 44. A game ball that enters either of the two general winning openings 31 on the right side is detected by the third winning opening detection sensor 44a while passing through the third discharge passage section 44.

A fourth discharge passage section 45 exists corresponding to the special electric winning device 32. A special electric detection sensor 45a is provided so that a detection range exists at a midpoint of the fourth discharge passage section 45, and a game ball that enters the special electric winning device 32 is detected by the special electric detection sensor 45a while passing through the fourth discharge passage section 45. A fifth discharge passage section 46 exists corresponding to the first operating port 33. A first operating port detection sensor 46a is provided so that a detection range exists at a midpoint of the fifth discharge passage section 46, and a game ball that enters the first operating port 33 is detected by the first operating port detection sensor 46a while passing through the fifth discharge passage section 46. A sixth discharge passage section 47 exists corresponding to the second operating port 34. A second actuation port detection sensor 47a is provided so that a detection range exists at a midpoint of the sixth discharge passage section 47, and a game ball that enters the second actuation port 34 is detected by the second actuation port detection sensor 47a as it passes through the sixth discharge passage section 47. A seventh discharge passage section 48 exists corresponding to the outlet 24a. An outlet detection sensor 48a is provided so that a detection range exists at a midpoint of the seventh discharge passage section 48, and a game ball that enters the outlet 24a is detected by the outlet detection sensor 48a as it passes through the seventh discharge passage section 48.

A gaming ball that is detected by any one of the various detection sensors 42a-48a will not be detected by the other detection sensors 42a-48a. A gate detection sensor 49a is also provided for the through gate 35, and a gaming ball that passes through the through gate 35 on its way down the play area PA is detected by the gate detection sensor 49a.

The various detection sensors 42a-49a are all electromagnetic induction type proximity sensors, but any sensor can be used as long as it can detect game balls individually. The various detection sensors 42a-49a are electrically connected to the main control device 60, which will be described later, and the detection results of the various detection sensors 42a-49a are output to the main control device 60. Specifically, the various detection sensors 42a-49a output a LOW level signal when they are not detecting a game ball, and output a HI level signal when they are detecting a game ball. However, this is not limited to the above, and the relationship between HI and LOW may be reversed.

As shown in FIG. 2, a front door frame 14 is provided so as to cover the entire front side of the inner frame 13 in which the game board 24 of the above configuration is attached to the resin base 21. As shown in FIG. 1, the front door frame 14 is formed with a window portion 51 that allows almost the entire area of the game area PA to be viewed from the front. The window portion 51 has a substantially elliptical shape, and a window panel 52 is fitted into it. The window panel 52 is formed of glass and is colorless and transparent, but is not limited to this and may be formed of synthetic resin and is colorless and transparent, or may be formed of color and transparency as long as the game area PA can be viewed through the window panel 52 from the front of the pachinko machine 10.

A display light-emitting unit 53 is provided above the window 51. A pair of left and right speaker units 54 are also provided to output sound effects according to the game status. An upper bulge 55 and a lower bulge 56, which bulge toward the front, are arranged vertically below the window 51. An upper tray 55a that opens upward is provided inside the upper bulge 55, and a lower tray 56a that also opens upward is provided inside the lower bulge 56. The upper tray 55a has the function of temporarily storing game balls paid out from the payout device described below, and guiding them to the game ball launching mechanism 27 while aligning them in a row. The lower tray 56a also has the function of storing surplus game balls in the upper tray 55a.

Next, we will explain the configuration on the back side of the gaming machine main body 12.

As shown in FIG. 2, the back of the inner frame 13 (specifically, the game board 24) is equipped with a main control device 60 that is responsible for the main control of the game. FIG. 5 is a front view of the main control device 60.

As shown in FIG. 5, the main control device 60 is configured by housing a main control board 61 in a board box 60a. An MPU 62 is mounted on one of the board surfaces of the main control board 61, which is the element mounting surface. The board box 60a is formed transparent so that the MPU 62 housed in the board box 60a can be seen from outside the board box 60a. Although the board box 60a is formed colorless and transparent, it may be formed colored and transparent as long as the MPU 62 housed in the board box 60a can be seen from outside the board box 60a. The main control device 60 is mounted on the back of the resin base 21 so that the opposing wall portion 60b facing the element mounting surface of the main control board 61 in the board box 60a faces the rear of the pachinko machine 10. Therefore, by opening the gaming machine main body 12 toward the front of the pachinko machine 10 relative to the outer frame 11 and exposing the back surface of the resin base 21, it becomes possible to visually observe the opposing wall portion 60b of the base box 60a, and also to visually observe the MPU 62 through the opposing wall portion 60b.

The board box 60a is formed by combining a plurality of case bodies 60c in front and behind, and the plurality of case bodies 60c are provided with joints 60e for preventing separation of the case bodies 60c and for leaving a trace when the case bodies 60c are separated. The joints 60e are arranged in a row on one side of the board box 60a, which is substantially rectangular. As a result, even if some of the joints 60e are used to prevent separation of the case bodies 60c and the case bodies 60c are separated by destroying the part of the joints 60e, it is possible to prevent separation of the case bodies 60c again by connecting another joint 60e thereafter. In addition, since the joints 60e are destroyed when the case bodies 60c are separated and a trace is left, it is possible to visually check the joints 60e to see whether the separation of the case bodies 60c is being carried out illegally. In addition, a seal 60f is attached to the side of the board box 60a opposite to the side on which the joints 60e are arranged, so as to straddle the boundary between the case bodies 60c. When the seal 60f is peeled off, an adhesive layer remains on the case body 60c. This makes it possible to leave a trace when the seal 60f is peeled off when the case body 60c is separated.

In the main control device 60 configured as described above, the main control board 61 is provided with a setting key insertion section 68a into which a setting key owned by the manager of the game hall is inserted and turned on to trigger a change in the setting state of the pachinko machine 10 within the range of "setting 1" to "setting 6", an update button 68b which is operated to sequentially change the setting state of the pachinko machine 10 after the setting key insertion section 68a is turned on, a reset button 68c which is operated to clear data in the main RAM 65 (described later) provided in the MPU 62 of the main control device 60, and first to third notification display devices 69a to 69c for notifying the management results of the game history. In addition, the MPU 62 mounted on the main control board 61 is provided with a read terminal 68d for connecting a connection terminal of an external device to read the management results of the game history or the information (programs and data) stored in the main ROM 64 by the external device. The setting state of the pachinko machine 10 is not limited to six stages from "Setting 1" to "Setting 6" and can be any number of stages.

The setting key insertion section 68a, update button 68b, reset button 68c, reading terminal 68d (i.e. MPU 62), and first to third notification display devices 69a to 69c are all provided on the element mounting surface of the main control board 61. As already explained, the element mounting surface of the main control board 61 faces the opposing wall 60b of the board box 60a, but the setting key insertion section 68a, update button 68b, reset button 68c, and reading terminal 68d are not covered by the opposing wall 60b. In other words, the areas of the opposing wall 60b facing the setting key insertion section 68a, update button 68b, reset button 68c, and reading terminal 68d are each provided as separate openings. This allows the setting key to be inserted into the setting key insertion section 68a, the update button 68b to be pressed, the reset button 68c to be pressed, and the reading terminal 68d to be connected to a connection terminal for an external device, without the need to open the board box 60a.

By inserting a setting key into the setting key insertion section 68a and rotating it in a predetermined direction, the setting key insertion section 68a is turned ON. In this state, the supply of operating power to the pachinko machine 10 is started (i.e., the supply of operating power to the MPU 62 of the main control device 60 is started), and the setting state of the pachinko machine 10 is changed to a changeable state in which it is possible to change the setting state of the pachinko machine 10. In this state, the setting state of the pachinko machine 10 is changed by one step in ascending order in the range of "Setting 1" to "Setting 6" each time the update button 68b is pressed once. Note that if the update button 68b is operated in the "Setting 6" state, the setting state is updated to "Setting 1". In addition, the setting key inserted in the setting key insertion section 68a is rotated from the ON operation position in the opposite direction to the predetermined direction to return it to the initial position, and the setting key insertion section 68a is turned OFF. When the setting key insertion section 68a is turned OFF, the changeable state ends, and the game is able to be played with the setting value at that time. In other words, even if you operate the update button 68b after the changeable state has ended, the setting value cannot be changed.

The ON operation of the setting key insertion section 68a is only valid when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if the ON operation of the setting key insertion section 68a is performed after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 has ended, the setting value cannot be changed.

The setting state of the pachinko machine 10 determines the degree of advantage per unit time in the pachinko machine 10, and the larger the value of "setting n" (n is an integer from "1" to "6") (i.e., the higher the setting value), the higher the degree of advantage. As will be described in more detail later, there are two winning/losing lottery modes that determine the probability of winning a jackpot result: a low probability mode with a relatively low probability of winning and a high probability mode with a relatively high probability of winning, and the higher the setting value, the higher the probability of winning a jackpot result in the low probability mode. On the other hand, regardless of the setting value, the probability of winning a jackpot result in the high probability mode is constant.

As described above, the reset button 68c is operated to clear the data in the main RAM 65, but in order to clear the data, it is necessary to start the supply of operating power to the pachinko machine 10 while the reset button 68c is pressed (i.e., it is necessary to start the supply of operating power to the MPU 62 of the main control device 60). The ON operation of the reset button 68c is only valid when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if the reset button 68c is pressed after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 has finished, the data in the main RAM 65 cannot be cleared.

As already explained, the read terminal 68d is connected to a connection terminal of an external device to read the results of game history management or the information (programs and data) stored in the main ROM 64 by the external device, but in order to output to the external device, it is necessary to start the supply of operating power to the pachinko machine 10 with the connection terminal of the external device connected to the read terminal 68d (i.e., it is necessary to start the supply of operating power to the MPU 62 of the main control device 60). The connection of the external device to the read terminal 68d is only valid when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if an external device is connected to the read terminal 68d after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 is completed, no external output to the external device is performed.

The first to third notification display devices 69a to 69c are all segment displays in which seven LED display segments are arranged, but are not limited to this and may be a single light-emitting body of a multi-color type, a liquid crystal display device, or an organic EL display. The first to third notification display devices 69a to 69c are all installed so that their display surfaces face the direction in which the element mounting surface of the main control board 61 faces, and are covered by the opposing wall portion 60b of the board box 60a. In this case, since the board box 60a is formed transparent, it is possible to visually observe the display surfaces of the first to third notification display devices 69a to 69c housed within the board box 60a from outside the board box 60a. As already explained, the main control device 60 is mounted on the back surface of the resin base 21 with the opposing wall portion 60b, which faces the element mounting surface of the main control board 61 in the board box 60a, facing toward the rear of the pachinko machine 10. Therefore, when the gaming machine main body 12 is opened toward the front of the pachinko machine 10 relative to the outer frame 11 and the back surface of the resin base 21 is exposed toward the front of the pachinko machine 10, it becomes possible to visually observe the display surfaces of the first to third notification display devices 69a to 69c through the opposing wall portion 60b.

The display surface of the first notification display device 69a displays not only the numbers "0" to "9" but also various characters including alphabetical characters. On the other hand, the second notification display device 69b and the third notification display device 69c display the numbers "0" to "9". The results of the game history management are notified using the first to third notification display devices 69a to 69c, and the contents of this notification will be described in detail later. In addition, in a changeable state in which the setting state of the pachinko machine 10 can be changed, a value corresponding to the current setting value is displayed on the third notification display device 69c. Note that the value corresponding to the setting value may be configured to be displayed on the first notification display device 69a or the second notification display device 69b. In addition, a configuration may be adopted in which the setting value before the changeable state is displayed on one of the first to third notification display devices 69a to 69c, and the current setting value is displayed on another of the first to third notification display devices 69a to 69c.

As shown in FIG. 2, the back pack unit 15 is installed so as to cover the back side of the inner frame 13, including the main control device 60. The back pack unit 15 has a back pack 72 formed of a transparent synthetic resin, to which a dispensing mechanism 73 and a control device assembly unit 74 are attached.

The payout mechanism 73 includes a tank 75 to which game balls are successively replenished from the island equipment of the gaming hall, and a payout device 76 for paying out the game balls stored in the tank 75. The game balls paid out from the payout device 76 are discharged into the upper tray 55a or the lower tray 56a through a payout passage provided downstream of the payout device 76. The payout mechanism 73 is supplied with a main power source of, for example, 24 volts AC, and is equipped with a back pack board having a power switch for turning the power source on and off.

The control device assembly unit 74 is equipped with a payout control device 77 that has the function of controlling the payout device 76, and a power supply and launch control device 78 that generates and outputs the predetermined power required by various control devices, etc., and controls the launch of game balls in response to the player's operation of the launch operation device 28. The payout control device 77 and the power supply and launch control device 78 are stacked one behind the other, with the payout control device 77 at the rear of the pachinko machine 10.

<Electrical configuration of the pachinko machine 10>
FIG. 6 is a block diagram showing the electrical configuration of the pachinko machine 10.

The main control device 60 comprises a main control board 61 which is responsible for the main control of the game, and a power failure monitoring board 67 which monitors the power supply. The main control board 61 is equipped with an MPU 62. In addition to a main CPU 63, which is an arithmetic processing device including a control unit and an arithmetic unit, the MPU 62 also contains a main ROM 64, a main RAM 65, and a management IC 66. In addition to the above elements, the MPU 62 also contains an interrupt circuit, a timer circuit, a data input/output circuit, various counter circuits as random number generators, and the like.

The main ROM 64 is a memory (i.e., a non-volatile memory means) that does not require an external power supply to retain memory, such as a NOR flash memory or a NAND flash memory, and is used for read-only purposes. The main ROM 64 stores various control programs and fixed value data executed by the main CPU 63.

The main RAM 65 is a memory (i.e., a volatile memory means) that requires an external power supply to retain memory, such as SRAM and DRAM, and is used for both reading and writing. The main RAM 65 allows random access, and when compared for the same data capacity, requires less time to read data than the main ROM 64. The main RAM 65 temporarily stores various data for the execution of the control programs stored in the main ROM 64.

The management IC 66 is a management device that manages the game history based on information supplied from the main CPU 63. Details will be described later, but the management IC 66 keeps track of the ball entry history of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a, and keeps track of the ball entry frequency of the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 based on the ball entry history that has been kept track of. The management IC 66 also keeps track of the frequency of the opening/closing execution mode and the high frequency support mode, which will be described later.

The MPU 62 has an input port and an output port. The input side of the MPU 62 is connected to a power outage monitoring board 67 and a payout control device 77 provided in the main control device 60. The power outage monitoring board 67 is connected to a power supply and launch control device 78 that has the function of supplying operating power, and the MPU 62 is supplied with operating power via the power outage monitoring board 67.

The input side of the MPU 62 is connected to various sensors such as the ball entry detection sensors 42a to 49a. As already explained, the ball entry detection sensors 42a to 49a include the first winning hole detection sensor 42a, the second winning hole detection sensor 43a, the third winning hole detection sensor 44a, the special electric detection sensor 45a, the first operating hole detection sensor 46a, the second operating hole detection sensor 47a, the out hole detection sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a to 49a, the main CPU 63 judges whether a ball has entered each entry section. In addition, the main CPU 63 executes various lotteries based on the entry into the first operating hole 33, and executes various lotteries based on the entry into the second operating hole 34.

The input side of the MPU 62 is provided with a setting key insertion section 68a, an update button 68b, and a reset button 68c, which are provided on the main control board 61. The setting key insertion section 68a is provided with a sensor (not shown), which detects whether the setting key insertion section 68a is located at the ON operation position or the OFF operation position. The main CPU 63 then identifies whether the setting key insertion section 68a is located at the ON operation position or the OFF operation position based on the detection result from the sensor. The update button 68b is provided with a sensor (not shown), which detects whether the update button 68b is pressed. The main CPU 63 then identifies whether the update button 68b is pressed based on the detection result from the sensor. The reset button 68c is provided with a sensor (not shown), which detects whether the reset button 68c is pressed. The main CPU 63 then identifies whether the reset button 68c is pressed based on the detection result from the sensor.

The output side of the MPU 62 is connected to a power outage monitoring board 67, a payout control device 77, and an audio/light emitting control device 81. A prize ball command is output to the payout control device 77, for example, based on the fact that a game ball has entered a prize ball entry section among the above-mentioned entry sections, where the occurrence of the ball entry corresponds to the payout of the game ball. Various commands such as a variation command, a type command, and an opening command are output to the audio/light emitting control device 81.

The output side of the MPU 62 is connected to the special electric drive unit 32b that opens and closes the opening and closing door 32a of the special electric winning device 32, the normal electric drive unit 34b that opens and closes the normal electric device 34a of the second operating port 34, the special chart unit 37, and the normal chart unit 38. Incidentally, the special chart unit 37 is provided with a special chart display unit 37a and a special chart reserved display unit 37b, all of which are connected to the output side of the MPU 62. Similarly, the normal chart unit 38 is provided with a normal chart display unit 38a and a normal chart reserved display unit 38b, all of which are connected to the output side of the MPU 62. Various driver circuits are provided on the main control board 61, and the MPU 62 controls the drive of the various drive units and various display units through the driver circuits.

That is, in the open/close execution mode, the main CPU 63 controls the drive of the special power drive unit 32b so that the special power winning device 32 is opened and closed. Also, when the open state of the normal power role device 34a is selected, the main CPU 63 controls the drive of the normal power drive unit 34b so that the normal power role device 34a is opened and closed. Also, during each game round, the main CPU 63 controls the display of the special chart display unit 37a. Also, when the lottery result of whether or not the normal power role device 34a is to be opened is to be clearly displayed, the main CPU 63 controls the display of the normal chart display unit 38a. In addition, when a winning entry occurs in the first operating port 33 or the second operating port 34, or when a change display starts in the special chart display unit 37a, the main CPU 63 executes display control of the special chart pending display unit 37b, and when a winning entry occurs in the through gate 35, or when a change display starts in the regular chart display unit 38a, the main CPU 63 executes display control of the regular chart pending display unit 38b.

The first to third notification display devices 69a to 69c are connected to the output side of the MPU 62. The results of the game history management in the management IC 66 are notified through displays on the first to third notification display devices 69a to 69c. When the setting state of the pachinko machine 10 is changed, the current setting value is displayed on the third notification display device 69c. In this case, the display of the first notification display device 69a and the second notification display device 69b is controlled by the management IC 66 and not by the main CPU 63, whereas the display of the third notification display device 69c is controlled by the main CPU 63 and is also controlled by the management IC 66. Display control of the third notification display device 69c by the main CPU 63 takes priority over display control by the management IC 66.

However, this is not limited to the above, and the third notification display device 69c may also be configured so that its display is controlled by the management IC 66 and not by the main CPU 63. In this case, when the current setting value is to be displayed on the third notification display device 69c upon changing the setting state of the pachinko machine 10, it is preferable that the main CPU 63 instructs the management IC 66 to display the setting value.

The MPU 62 is provided with a read terminal 68d. A sensor (not shown) is provided on the read terminal 68d, and this sensor detects whether or not a connection terminal for an external device is connected to the read terminal 68d. Then, based on the detection result from the sensor, the main CPU 63 determines whether or not a connection terminal for an external device is connected to the read terminal 68d. Furthermore, when an external device is connected to the read terminal 68d, the results of the game history management in the management IC 66 or the information (programs and data) stored in the main ROM 64 are output to the external device.

The power failure monitoring board 67 relays between the main control board 61 and the power supply and launch control device 78, and monitors the stable DC voltage of 24 volts, which is the maximum voltage output from the power supply and launch control device 78. The payout control device 77 controls the payout of prize balls and loan balls by the payout device 76 based on the prize ball command received from the main control device 60.

The power supply and launch control device 78 is connected to a commercial power supply (external power supply) in, for example, an amusement hall. Based on the external power supplied from the commercial power supply, the power supply and launch control device 78 generates the necessary operating power for the main control board 61, the payout control device 77, etc., and supplies the generated operating power. Incidentally, the power supply and launch control device 78 is provided with a power supply unit for power outage such as a backup capacitor, and even when the power supply to the pachinko machine 10 is in an OFF state, the power supply unit for power outage supplies memory retention power to the main RAM 65 of the main control device 60 and the payout control device 77. The power supply and launch control device 78 is also responsible for the launch control of the game ball launch mechanism 27, and the game ball launch mechanism 27 is driven when a predetermined launch condition is met. As already explained, the payout mechanism unit 73 is provided with a power switch, and when the power switch is turned ON, the supply of operating power to the pachinko machine 10 is started, and when the power switch is turned OFF, the supply of operating power to the pachinko machine 10 is stopped.

The audio and light emission control device 81 drives and controls the display light emitting unit 53 and the speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and also controls the display control device 82. The display control device 82 executes display control of the pattern display device 41 based on commands received from the audio and light emission control device 81.

<Electrical configuration for performing various lotteries by the main CPU 63>
Next, the electrical configuration for performing various lotteries by the main CPU 63 will be described with reference to FIG.

During play, the master CPU 63 uses various counter information to perform a lottery for determining whether a jackpot occurs, settings for the display of the special symbol display section 37a, settings for the symbol display of the symbol display device 41, settings for the display of the normal symbol display section 38a, etc. Specifically, as shown in FIG. 7, a winning random number counter C1 used for the lottery for determining whether a jackpot occurs, a jackpot type counter C2 used for determining the type of jackpot, a reach random number counter C3 used for the lottery for determining whether a reach occurs when the symbol display device 41 misses and fluctuates, a random number initial value counter CINI used for setting the initial value of the winning random number counter C1, and a fluctuating type counter CS that determines the display duration in the special symbol display section 37a and the symbol display device 41. In addition, a normal electric device release counter C4 used for the lottery for determining whether the normal electric device 34a of the second operating port 34 is in a normal electric open state is used. The counters C1 to C3, CINI, CS, and C4 are located in the various counter areas 65b of the main RAM 65.

Each of the counters C1 to C3, CINI, CS, and C4 is a loop counter that adds 1 to the previous value each time it is updated and returns to "0" after it reaches its maximum value. Each counter is updated at short intervals. Information corresponding to the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 is stored in the reserved storage area 65a provided as acquired information storage means in the main RAM 65 when a winning occurs in the first actuation port 33 or the second actuation port 34.

The reserved storage area 65a comprises a reserved area RE and an execution area AE. The reserved area RE comprises a first reserved area RE1, a second reserved area RE2, a third reserved area RE3 and a fourth reserved area RE4, and a combination of the numerical information of the winning random number counter C1, the big win type counter C2 and the reach random number counter C3 is stored as reserved information in one of the reserved areas RE1 to RE4 according to the winning history of the first actuation port 33 or the second actuation port 34.

In this case, when multiple consecutive wins occur in the first actuation port 33 or the second actuation port 34, the numerical information is stored in the first holding area RE1 to the fourth holding area RE4 in chronological order from the first holding area RE1 to the second holding area RE2 to the third holding area RE3 to the fourth holding area RE4. By providing four holding areas RE1 to RE4 in this way, up to four winning histories of game balls entering the first actuation port 33 or the second actuation port 34 can be reserved and stored.

The number of items that can be stored on hold is not limited to four, but is arbitrary, and may be any other multiple, such as two, three, or five or more, or may be singular.

The execution area AE is an area for moving the various numerical information stored in the first reserve area RE1 of the reserve area RE when the variable display of the special chart display section 37a begins, and when one game round begins, a win/loss determination is made based on the various numerical information stored in the execution area AE.

Each of the above counters will be explained in detail below.

First, the normal power feature opening counter C4 will be described. The normal power feature opening counter C4 is configured to increment by one within a range of, for example, 0 to 250, and return to "0" after it reaches its maximum value. The normal power feature opening counter C4 is updated periodically, and is stored in the normal power reserve area 65c of the main RAM 65 when the game ball enters the through gate 35. Then, at a specified timing, a lottery is held to determine whether or not to control the normal power feature 34a to an open state based on the stored value of the normal power feature opening counter C4.

In this pachinko machine 10, multiple types of support modes are set so that the manner of support provided by the normal power device 34a differs from one another. In detail, the support modes are set to a high-frequency support mode and a low-frequency support mode so that the frequency with which the normal power device 34a of the second operating port 34 opens per unit time is relatively high and low when compared with a situation in which game balls are continuously released in the same manner into the game area PA.

In the high-frequency support mode and the low-frequency support mode, the probability of winning the normal power opening state in the normal power opening lottery using the normal power role opening counter C4 is the same (for example, both are 4/5). However, in the high-frequency support mode, the number of times that the normal power role 34a will be in the open state when the normal power opening state is won is set to be greater than in the low-frequency support mode, and the opening time for each time is set to be longer. In this case, when the normal power opening state is won in the high-frequency support mode and the open state of the normal power role 34a occurs multiple times, the closing time from the end of one opening state to the start of the next opening state is set to be shorter than the opening time for each time. Furthermore, in the high-frequency support mode, the minimum time to be secured between one normal power opening lottery and the next normal power opening lottery (i.e., the duration of one display on the normal power display unit 38a) is set to be shorter than in the low-frequency support mode.

As described above, in the high-frequency support mode, the probability of a winning entry into the second actuation port 34 is higher than in the low-frequency support mode. In other words, in the low-frequency support mode, the probability of a winning entry into the first actuation port 33 is higher than in the second actuation port 34, but in the high-frequency support mode, the probability of a winning entry into the second actuation port 34 is higher than in the first actuation port 33. When a winning entry into the second actuation port 34 occurs, a predetermined number of game balls are paid out, so in the high-frequency support mode, the player can play without losing too many balls.

The configuration for increasing the frequency of the high-frequency support mode becoming in the normal power release state per unit time compared to the low-frequency support mode is not limited to the above, and may be, for example, a configuration for increasing the probability of winning the normal power release state in the normal power release lottery. In addition, in a configuration in which multiple types of reserved time (for example, the time of variable display executed in the normal power display unit 38a based on winning the through gate 35) are prepared for the time reserved between one normal power release lottery and the next normal power release lottery, the high-frequency support mode may be set so that a shorter reserved time is more likely to be selected or the average reserved time is shorter than in the low-frequency support mode. Furthermore, the advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying any one or any combination of conditions from increasing the number of openings, lengthening the opening time, shortening the reserved time reserved between one normal power release lottery and the next normal power release lottery, shortening the average time of the reserved time, and increasing the winning probability.

Here, as already explained, the pachinko machine 10 has the setting states of "Setting 1" to "Setting 6", but the opening frequency and opening mode of the normal power device 34a in the low-frequency support mode are the same regardless of the setting value, and the opening frequency and opening mode of the normal power device 34a in the high-frequency support mode are also the same regardless of the setting value. However, this is not limited to this, and at least one of the opening frequency and opening mode of the normal power device 34a for at least one of the low-frequency support mode and the high-frequency support mode may be configured to vary depending on the setting state of the pachinko machine 10. For example, the higher the setting value, the higher the opening frequency of the normal power device 34a in the low-frequency support mode, and the higher the probability of a game ball entering the second operating port 34 when the normal power device 34a is in a one-time opening state in the low-frequency support mode. In addition, the higher the set value, the higher the frequency of opening the normal power device 34a in the high-frequency support mode, and the higher the probability of a game ball entering the second operating port 34 when the normal power device 34a is opened once in the high-frequency support mode.

Next, the winning random number counter C1 will be described. The winning random number counter C1 is configured to increment by one within the range of, for example, 0 to 599, and return to "0" after reaching a maximum value. In particular, when the winning random number counter C1 goes around once, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. The random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is updated periodically, and is stored in the reserved storage area 65a of the main RAM 65 when a game ball enters the first actuation port 33 or the second actuation port 34.

The random number value that will result in a jackpot win is stored as a win/lose table in the main ROM 64. Figure 8 is an explanatory diagram for explaining the various tables stored in the main ROM 64. As win/lose tables, low probability win/lose tables 64a to 64f for the low probability mode and high probability win/lose table 64g for the high probability mode are stored.

The low-probability hit/miss tables 64a to 64f are provided in one-to-one correspondence with the setting states of "Setting 1" to "Setting 6." In other words, there are a low-probability hit/miss table 64a for Setting 1, which is referenced when the setting state of the pachinko machine 10 is "Setting 1," a low-probability hit/miss table 64b for Setting 2, which is referenced when the setting state of the pachinko machine 10 is "Setting 2," a low-probability hit/miss table 64c for Setting 3, which is referenced when the setting state of the pachinko machine 10 is "Setting 3," a low-probability hit/miss table 64d for Setting 4, which is referenced when the setting state of the pachinko machine 10 is "Setting 4," a low-probability hit/miss table 64e for Setting 5, which is referenced when the setting state of the pachinko machine 10 is "Setting 5," and a low-probability hit/miss table 64f for Setting 6, which is referenced when the setting state of the pachinko machine 10 is "Setting 6."

These low probability tables 64a to 64f are set so that the higher the setting value, the higher the probability of winning the jackpot. Specifically, when the low probability table 64a for setting 1 is referenced, the probability of winning the jackpot is about 1/320, when the low probability table 64b for setting 2 is referenced, the probability of winning the jackpot is about 1/310, when the low probability table 64c for setting 3 is referenced, the probability of winning the jackpot is about 1/300, when the low probability table 64d for setting 4 is referenced, the probability of winning the jackpot is about 1/290, when the low probability table 64e for setting 5 is referenced, the probability of winning the jackpot is about 1/280, and when the low probability table 64f for setting 6 is referenced, the probability of winning the jackpot is about 1/270. As a result, when the setting state of the pachinko machine 10 is a high setting value, the probability of winning the jackpot in the low probability mode is higher, which is advantageous for the player.

On the other hand, only one type of high probability winning/losing table 64g is provided so that it is common to any of the setting states of "Setting 1" to "Setting 6". The high probability winning/losing table 64g is set so that the probability of winning the jackpot result is higher than the low probability winning/losing tables 64a to 64f regardless of the setting state of "Setting 1" to "Setting 6". Specifically, when the high probability winning/losing table 64g is referenced, the jackpot result occurs at about 1/30. This makes it possible to make the high probability mode more advantageous than the low probability mode regardless of the setting state of the pachinko machine 10. In addition, even if the lowest setting state "Setting 1" is set as the high probability mode, it is possible to increase the probability of winning the jackpot result compared to the low probability mode of the highest setting state "Setting 6". In addition, it is possible to prevent the high probability mode from causing an advantage or disadvantage depending on the setting state of the pachinko machine 10, and it is also possible to reduce the storage capacity for storing the high probability winning/losing table 64g in advance in the main ROM 64.

The jackpot type counter C2 is configured to be incremented by one within the range of 0 to 29, and to return to "0" after it reaches its maximum value. The jackpot type counter C2 is updated periodically, and is stored in the reserved storage area 65a when a game ball enters the first actuation port 33 or the second actuation port 34.

In this pachinko machine 10, multiple jackpot results are set. These multiple jackpot results are set by providing differences in three conditions: (1) the manner of opening and closing control of the special electric prize winning device 32 in the opening and closing execution mode, (2) the lottery mode in the winning/losing lottery means after the opening and closing execution mode ends, and (3) the support mode in the regular electric device 34a of the second operating port 34 after the opening and closing execution mode ends.

As the manner of opening and closing control of the special electric winning device 32 in the opening and closing execution mode, a high frequency winning mode and a low frequency winning mode are set so that the frequency of winning in the special electric winning device 32 from the start to the end of the opening and closing execution mode is relatively high and low. Specifically, in either the high frequency winning mode or the low frequency winning mode, a predetermined number of rounds are played up to the upper limit.

A round play is a play that continues until one of the following conditions is met: a predetermined upper limit duration has elapsed, or a predetermined upper limit number of game balls have entered the special electric winning device 32. In addition, the number of round plays in the open/close execution mode triggered by a jackpot result is the same fixed number of rounds regardless of the type of jackpot result that triggered the transition. Specifically, the upper limit number of round plays is set to 15 rounds regardless of the jackpot result.

In addition, in this pachinko machine 10, the special electric winning device 32 is set to have multiple opening modes with different opening durations from when the special electric winning device 32 is opened to when it is closed. In detail, a long-time mode in which the opening duration is set to 29 seconds, which is a long time, and a short-time mode in which the opening duration is set to 0.06 seconds, which is a short time shorter than the long time, are set.

In this pachinko machine 10, when the launch operation device 28 is operated by the player, the game ball launch mechanism 27 is driven and controlled so that one game ball is launched toward the game area PA every 0.6 seconds. In addition, the upper limit number of balls for the end condition of the round game is set to nine. In this case, in the long-time mode among the above-mentioned opening modes, the opening duration is set to a time longer than the product of the game ball launch cycle and one round game. On the other hand, in the short-time mode, the opening duration is set to a time shorter than the product of the game ball launch cycle and one round game, more specifically, shorter than the game ball launch cycle. Therefore, when one opening is performed in the long-time mode, it is expected that the special electric winning device 32 will win the maximum number of balls in one round game, and when one opening is performed in the short-time mode, it is expected that no prize will be won in the special electric winning device 32, or that if a prize is won, it will be about one ball.

In the high frequency winning mode, the special electric winning device 32 is opened once in each round of play in a long time mode. On the other hand, in the low frequency winning mode, the special electric winning device 32 is opened once in each round of play in a short time mode.

The number of times the special electric winning device 32 is opened and closed, the number of rounds of play, the duration of opening for one opening, and the upper limit number of times per round of play in the high frequency winning mode and low frequency winning mode are not limited to the above values and are arbitrary, so long as the frequency of winning in the special electric winning device 32 from the start to the end of the opening and closing execution mode is higher in the high frequency winning mode than in the low frequency winning mode.

As shown in FIG. 8, the allocation destination of the jackpot result for the jackpot type counter C2 is stored in the main ROM 64 as an allocation table 64h. In addition, in the allocation table 64h, a low probability jackpot result, a low prize high probability jackpot result, and a most favorable jackpot result are set as the allocation destination of the jackpot result in the event of a jackpot result.

A low probability jackpot result is one in which the open/close execution mode becomes the high frequency winning mode, and after the open/close execution mode ends, the win/lose selection mode becomes the low probability mode, and the support mode becomes the high frequency support mode. However, this high frequency support mode will transition to the low frequency support mode if the number of plays reaches the end reference number (specifically, 100 plays) after the transition.

A low-winning, high-probability jackpot result is one in which the open/close execution mode becomes a low-frequency winning mode, and after the open/close execution mode ends, the win/lose lottery mode becomes a high-probability mode, and the support mode becomes a high-frequency support mode. These high-probability and high-frequency support modes continue until the lottery result in a win/lose lottery win and the jackpot state is entered.

The most favorable jackpot result is one in which the open/close execution mode becomes the high-frequency winning mode, and after the open/close execution mode ends, the win/lose lottery mode becomes the high probability mode, and the support mode becomes the high-frequency support mode. These high probability and high frequency support modes continue until the lottery result in a win in the jackpot state, which transitions to the jackpot state.

In relation to the above game states, the normal game state refers to a state in which the win/lose selection mode is a low probability mode and the support mode is a low frequency support mode, rather than the open/close execution mode. Also, a configuration may be adopted in which a low prize-winning high probability jackpot result is not set as a game result. Also, in the open/close execution mode in a low prize-winning high probability jackpot result, the number of rounds of play may be fewer than in the case of a low probability jackpot result and a most favorable jackpot result.

In the distribution table 64h, of the jackpot type counter C2 values of "0 to 29", "0 to 9" correspond to a low probability jackpot result, "10 to 14" correspond to a low probability jackpot result with a high probability of winning, and "15 to 29" correspond to the most favorable jackpot result.

Only one type of distribution table 64h is provided so that it is common to all settings from "Setting 1" to "Setting 6." This makes it possible to prevent any advantage or disadvantage in the distribution pattern of the jackpot result from being caused by the setting state of the pachinko machine 10, and also makes it possible to reduce the storage capacity required to previously store the distribution table 64h in the main ROM 64.

The allocation of the jackpot result may be different depending on the setting state of the pachinko machine 10. For example, the higher the setting value, the higher the probability of being allocated to the most favorable jackpot result, or the higher the setting value, the higher the probability of being allocated to the most favorable jackpot result or the low prize-winning high probability jackpot result. In this case, the higher the setting value, the higher the probability of entering the high probability mode after the jackpot result. Also, the higher the setting value, the lower the probability of being allocated to the low prize-winning high probability jackpot result, or the higher the setting value, the higher the probability of being allocated to the low prize-winning high probability jackpot result. In this case, the higher the setting value, the higher the probability of the opening and closing execution mode of the high frequency winning mode occurring.

Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to be incremented by one within a range of, for example, 0 to 238, and to return to "0" after reaching a maximum value. In this pachinko machine 10, an expectation effect is set as a type of display effect in the pattern display device 41. In a gaming machine equipped with a pattern display device 41 capable of performing a variable display of patterns, in which the final stop result in a game round resulting in a predetermined jackpot result is a grant-corresponding result, the expectation effect refers to a display state that makes the player think that the variable display state is likely to result in the grant-corresponding result from the start of the variable display of patterns in the pattern display device 41 until the stop result is derived and displayed, in a gaming machine in which the final stop result is a grant-corresponding result in a game round resulting in a predetermined jackpot result. Specifically, the grant-corresponding result is a combination of patterns with the same number attached to one of the pay lines that is stopped and displayed.

There are two types of expectation effects: reach displays and advance notices that are set to anticipate the occurrence of reach displays or corresponding results before the reach display occurs.

The reach display includes a display state in which the reach pattern combination is displayed by stopping the display of the patterns for some of the multiple pattern rows displayed on the display surface 41a of the pattern display device 41, and in this state, the remaining pattern rows display a changing pattern. In addition, it includes a state in which the reach pattern combination is displayed as described above, the remaining pattern rows display a changing pattern, and a reach performance is performed by displaying a predetermined character or the like as a video on the background screen, and a reach performance is performed by displaying a reduced or hidden display of the reach pattern combination and displaying a predetermined character or the like as a video on almost the entire display surface 41a.

Pre-notification displays include a mode in which characters are displayed separately from the patterns on the pattern rows in a situation in which patterns are displayed in a variable manner in all pattern rows after the display surface 41a of the pattern display device 41 starts displaying the variable patterns, or in a situation in which patterns are displayed in a variable manner in some pattern rows. Pre-notification displays also include a mode in which the background screen is displayed in a predetermined manner different from the previous manner, and a mode in which the patterns on the pattern rows are displayed in a predetermined manner different from the previous manner. Such pre-notification displays can occur in both game rounds when a reach display is made and when a reach display is not made, but are set to occur with a higher probability when a reach display is made than when a reach display is not made.

The reach display is executed regardless of the value of the reach random number counter C3 in a game round in which the same symbol combination is ultimately displayed. Also, in a game round corresponding to a jackpot result in which the same symbol combination is not displayed, the reach display is not executed regardless of the value of the reach random number counter C3. Also, in a game round corresponding to a miss result, the reach display is executed when the reach random number counter C3 obtained at a predetermined timing by referring to the reach table stored in the main ROM 64 corresponds to the occurrence of the reach display.

On the other hand, the decision as to whether or not to display a preview is not made by the main control device 60, but by the audio and light control device 81. In this case, the audio and light control device 81 executes a lottery process for the preview display so that a game round corresponding to any jackpot result satisfies at least one of the conditions that a preview display is more likely to occur and that a preview display with a low occurrence rate is more likely to occur in a game round corresponding to a miss result. Incidentally, this lottery result is reflected when the performance for the game round is executed by the pattern display device 41.

Here, the probability of a reach display occurring in a game that results in a losing result is the same regardless of the setting state of "Setting 1" to "Setting 6." This makes it possible to ensure that the setting state of the pachinko machine 10 does not result in an advantage or disadvantage in terms of the probability of a reach display occurring in a game that results in a losing result. However, this is not limited to this, and a configuration may be adopted in which the higher the setting value, the higher the probability of a reach display occurring in a game that results in a losing result.

Next, the change type counter CS will be explained. The change type counter CS is configured to increment by one within the range of, for example, 0 to 198, and return to "0" after reaching the maximum value. The change type counter CS is used by the main CPU 63 to determine the display duration in the special chart display unit 37a and the display duration of the pattern in the pattern display device 41. The change type counter CS is updated once each time the timer interrupt process described below is executed, and is repeatedly updated within the remaining time until the next timer interrupt process is executed. The buffer value of the change type counter CS is obtained when determining the change pattern at the start of the change display in the special chart display unit 37a and at the start of the pattern change by the pattern display device 41.

<Regarding the processing configuration of the main CPU 63>
Next, we will explain each process executed to progress the game by the master CPU 63. The processes of the master CPU 63 are roughly divided into main processes that are started when the power is turned on, and timer interrupt processes that are started periodically (every 4 millisecond period in this embodiment).

<Main processing>
First, the main processing will be described with reference to the flowchart of FIG.

First, the power-on wait process is executed (step S101). In this power-on wait process, for example, the main process is started and then a predetermined wait time (specifically, one second) elapses before proceeding to the next process. During the execution period of this power-on wait process, the operation start and initial settings of the pattern display device 41 are completed. After that, access to the main RAM 65 is permitted (step S102).

Then, it is determined whether the setting key insertion section 68a is turned on (step S103). If the setting key insertion section 68a is not turned on (step S103: NO), it is determined whether the reset button 68c is pressed (step S104). If the reset button 68c is pressed (step S104: YES), each area of the main RAM 65 is cleared to "0" except for the area in which the setting value information indicating the setting state of the pachinko machine 10 is set in the main RAM 65, and the area cleared to "0" is initialized (step S105). In other words, when the supply of operating power to the pachinko machine 10 is started while the reset button 68c is pressed without turning on the setting key insertion section 68a, the clearing process of the main RAM 65 is executed while the setting value information is maintained in the state before the supply of operating power to the pachinko machine 10 was stopped, and the initial setting is executed for the memory area in which the clearing process was executed. This makes it possible to initialize other areas of the main RAM 65 without changing the setting value. In step S105, various registers in the main CPU 63 are also cleared to "0" and then initialized.

If the reset button 68c is not pressed (step S104: NO), it is determined whether the power outage flag is set to "1" (step S106). The power outage flag is provided in the main RAM 65, and if the supply of operating power to the main CPU 63 is stopped and a predetermined power outage process is normally executed, the power outage flag is set to "1". If the power outage flag is set to "1", it is determined whether the checksum calculation result matches the checksum saved at the time of power outage, that is, the validity of the stored data (step S107). If the process of step S105 is executed, or if a positive determination is made in step S107, it is determined whether the setting value of the pachinko machine 10 is normal by checking the main RAM 65 (step S108). Specifically, if the setting value is any of "Setting 1" to "Setting 6", it is determined to be normal, and if it is "0" or 7 or more, it is determined to be abnormal.

If a negative judgment is made in any of steps S106 to S108, an operation prohibition process is executed. In the operation prohibition process, an error notification process is executed to notify the hall manager or the like of the occurrence of an error (step S109), and then an infinite loop is entered. The operation prohibition process is released by executing an all-clear process (step S117) described below.

If the determination is affirmative in all of steps S106 to S108, a power-on setting process is executed (step S110). In the power-on setting process, a predetermined area of the main RAM 65 is set to an initial value, such as initializing the power outage flag, and a command corresponding to the current game state is sent to the sound and light emission control device 81. After executing the process of step S110, a recognition process (step S111) is executed to cause the management IC 66 to recognize various information, and a data output process is executed to output various data to an external device connected to the read terminal 68d of the MPU 62 (step S112). The details of the recognition process and the data output process will be explained later.

The main CPU 63 is configured to periodically execute timer interrupt processing, but timer interrupt processing is prohibited from occurring when main processing is started. This state in which timer interrupt processing is prohibited is released when the processing of step S112 is completed and before the processing of step S113 is executed, and execution of timer interrupt processing is permitted. As a result, when the supply of operating power to the main CPU 63 is started, the data output processing of step S112 ends, and timer interrupt processing is not executed until the stage before the processing of step S113 is started. Therefore, processing to progress the game in the main CPU 63 is not started until this situation is reached.

Then, proceed to the remaining processing of steps S113 to S116. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but there will be a remaining time between one timer interrupt processing and the next timer interrupt processing. This remaining time will vary depending on the processing completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining processing of steps S113 to S116. In this respect, the remaining processing of steps S113 to S116 can be said to be non-periodic processing that is executed non-periodically.

In the remaining process, first, in step S113, interrupt prohibition is set to prohibit the occurrence of timer interrupt processing. In the following step S114, random number initial value update processing is executed to update the random number initial value counter CINI, and in step S115, fluctuation counter update processing is executed to update the fluctuation type counter CS. In these update processing, the current numerical information is read from the corresponding counter in the main RAM 65, and the read numerical information is incremented by 1, and then the counter from which it was read is overwritten. In this case, when the counter value exceeds the maximum value, each is cleared to "0". After that, in step S116, interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing is prohibited to a state in which it is permitted. If the processing of step S116 is executed, the process returns to step S113, and the processing of steps S113 to S116 is repeated.

On the other hand, if the setting key insertion section 68a is turned ON (step S103: YES), all areas of the main RAM 65, including the areas in which the setting value information indicating the setting state of the pachinko machine 10 is set in the main RAM 65, are cleared to "0" and the areas cleared to "0" are initialized (step S117). In other words, if an operation to change the setting state of the pachinko machine 10 is performed, all areas of the main RAM 65 are cleared to "0" even if the reset button 68c is not pressed, and the memory areas in which the clearing process has been performed are initialized. In addition, in step S117, various registers of the main CPU 63 are also cleared to "0" and then initialized. Note that this is not limited to this, and even if an operation to change the setting state of the pachinko machine 10 is performed, if the reset button 68c is not pressed, the all-clear process of the main RAM 65 is not executed, and the all-clear process may be executed if an operation to change the setting state of the pachinko machine 10 is performed and the reset button 68c is pressed.

Then, in step S118, a setting value update process is executed, and in step S119, a setting value update signal output process is executed, and then the process proceeds to step S110. The setting value update process is described below. The setting value update signal output process will be described in detail later. Figure 10 is a flowchart showing the setting value update process.

First, the setting value counter provided in the main RAM 65 is set to "1" (step S201). The setting value counter is a counter that allows the main CPU 63 to identify which setting value the setting state of the pachinko machine 10 is. By setting the setting value counter to "1", when the setting value update process is executed, the setting value becomes "Setting 1" regardless of the previous setting value.

Then, a process to start displaying the setting value is executed (step S202). In the process to start displaying the setting value, the display of the third notification display device 69c is controlled so that the number "1" corresponding to "Setting 1" is displayed. When changing the setting value, the manager of the gaming hall can grasp the current setting state of the pachinko machine 10 by checking the third notification display device 69c.

After that, on the condition that the setting key insertion section 68a has not been turned OFF (step S203: NO), it is determined whether the update button 68b has been pressed once (step S204). Specifically, it is determined whether the signal from the sensor that detects the pressing of the update button 68b has switched from a LOW level to a HIGH level. If a negative determination is made in step S204, the process returns to step S203, and it is determined whether the setting key insertion section 68a has been turned OFF.

If the update button 68b has been pressed once (step S204: YES), the value of the setting value counter in the main RAM 65 is incremented by 1 (step S205). If the value of the setting value counter after incrementing by 1 exceeds "6" (step S206: YES), the setting value counter is set to "1" (step S207). As a result, the setting value is updated to the next higher setting each time the update button 68b is pressed once, and if the update button 68b is pressed once when the setting is "setting 6", the setting will return to "setting 1".

If a negative judgment is made in step S206, or if the process of step S207 is executed, a display update process of the setting value is executed (step S208). In the display update process of the setting value, the display of the third notification display device 69c is controlled so that a number corresponding to the value of the setting value counter of the main RAM 65 is displayed. By checking the third notification display device 69c, the manager of the gaming hall can grasp the setting state of the pachinko machine 10 after pressing the update button 68b.

After executing the process of step S208, the process returns to step S203, and it is determined whether the setting key insertion unit 68a has been turned OFF. If it has not been turned OFF (step S203: NO), the process of steps S204 and onwards is executed again. If it has been turned OFF (step S203: YES), a process of ending the display of the setting value is executed (step S209). In the process of ending the display of the setting value, the display of the setting value on the third notification display device 69c is ended.

<Timer interrupt processing>
Next, the timer interrupt process will be described with reference to the flowchart of Fig. 11. The timer interrupt process is executed periodically (for example, every 4 milliseconds).

First, the power outage information storage process is executed (step S301). In the power outage information storage process, it is monitored whether a power outage signal corresponding to the occurrence of a power cut is received from the power outage monitoring board 67, and if a power outage is identified, the power outage process is executed and then an infinite loop is entered. In the power outage process, the power outage flag in the main RAM 65 is set to "1", and a checksum is calculated and the calculated checksum is saved.

Then, a random number update process for selection is executed (step S302). In the random number update process for selection, the winning random number counter C1, the big win type counter C2, the reach random number counter C3, and the normal power feature opening counter C4 are updated. Specifically, the current numerical information is read out sequentially from the winning random number counter C1, the big win type counter C2, the reach random number counter C3, and the normal power feature opening counter C4, and the read numerical information is incremented by 1, and then the counter from which it was read is overwritten. In this case, when the counter value exceeds the maximum value, each is cleared to "0". After that, in step S303, a random number initial value update process is executed as in step S114, and in step S304, a variable counter update process is executed as in step S115.

Then, a fraud detection process is executed to monitor whether or not a specific event set as a target for fraudulent activity has occurred (step S305). In this fraud detection process, the occurrence of multiple types of events is monitored, and if a specific event has occurred, a game stop flag provided in the main RAM 65 is set to "1". In the following step S306, it is determined whether or not the game progress has been stopped by determining whether or not the game stop flag has been set to "1". If a negative determination is made in step S306, the process from step S307 onwards is executed.

In step S307, port output processing is executed. In the port output processing, when output information has been set in the previous timer interrupt processing, processing is executed to output corresponding to the output information to the various drive units 32b, 34b. For example, when information is set to switch the special power winning device 32 to an open state, the output of a drive signal to the special power drive unit 32b is started, and when information is set to switch to a closed state, the output of the drive signal is stopped. Also, when information is set to switch the normal power device 34a of the second operating port 34 to an open state, the output of a drive signal to the normal power drive unit 34b is started, and when information is set to switch to a closed state, the output of the drive signal is stopped.

Then, a read process is executed (step S308). In the read process, signals other than the power failure signal and the winning signal are read, and the read information is stored for use in future processes.

Then, the ball entry detection process is executed (step S309). In the ball entry detection process, the signals received from each ball entry detection sensor 42a to 49a are read, and based on the read results, it is determined whether or not a ball has entered the out gate 24a, the general winning gate 31, the special electric winning device 32, the first operating gate 33, the second operating gate 34, and the through gate 35. Details of the ball entry detection process will be explained later.

Then, a timer update process is executed to collectively update the numerical information of the multiple types of timer counters provided in the main RAM 65 (step S310). In this case, the timer counters whose stored numerical information is updated by subtraction are handled in a consolidated manner, but it is also possible to configure the system to collectively update both subtractive timer counters and additive timer counters.

Then, a launch control process is executed to control the launch of the gaming balls (step S311). When the launch operation to the launch operation device 28 is continued, one gaming ball is launched every 0.6 seconds, which is the predetermined launch cycle. In the following step S312, as an input status monitoring process, based on the information read in the reading process of step S308, a disconnection check is performed for each ball entry detection sensor 42a to 49a, and the opening of the gaming machine main body 12 and front door frame 14 is confirmed.

Then, a special chart special electricity control process is executed to control the execution of the game round and the open/close execution mode (step S313). The special chart special electricity control process will be described in detail later.

Then, execute the normal map normal power control process (step S314). In the normal map normal power control process, if a winning entry has occurred in the through gate 35, execute a process to obtain the reserved information on the normal map side, and if reserved information on the normal map side is stored, execute an opening judgment for the reserved information, and execute a process to perform a normal map performance triggered by the opening judgment. Also, execute a process to open and close the normal power role 34a of the second operating port 34 based on the result of the opening judgment. In this case, if the support mode is the low frequency support mode, execute the corresponding process, and if the support mode is the high frequency support mode, execute the corresponding process. Also, if the opening and closing execution mode is selected, the support mode will be the low frequency support mode even if the previous support mode was the high frequency support mode.

In the next step S315, based on the processing results of the immediately preceding steps S313 and S314, output information is set to reflect the increase or decrease in the number of reserved information related to the special drawing display unit 37a in the special drawing reserved display unit 37b, and output information is set to reflect the increase or decrease in the number of reserved information related to the ordinary drawing display unit 38a in the ordinary drawing reserved display unit 38b. Also, in step S315, based on the processing results of the immediately preceding steps S313 and S314, output information is set to update the display contents of the special drawing display unit 37a, and output information is set to update the display contents of the ordinary drawing display unit 38a.

Then, a payout status receiving process is executed to confirm the contents of the command and signal received from the payout control device 77 and perform processing corresponding to the confirmation result (step S316). A payout output process is also executed to set the prize ball command as the output target (step S317). An external information setting process is also executed to control the start and end of the output of an external signal according to the processing results of the various processes executed in this timer interrupt processing (step S318). Then, a management output process is executed to output information corresponding to the ball entry result in the game area PA to the management IC 66 (step S319). Details of the management output process will be explained later.

Next, the special chart special power control process in step S313 will be explained with reference to the flowchart in Figure 12.

First, the process for acquiring reserved information is executed (step S401). In the process for acquiring reserved information, it is determined whether or not a winning has occurred in the first actuation port 33 or the second actuation port 34, and if a winning has occurred, it is determined whether or not the number of reserved balls in the reserved storage area 65a is less than the upper limit ("4" in this embodiment). If the number of reserved balls is less than the upper limit, the number of reserved balls is incremented by 1, and the numerical information of the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 updated in the previous step S302 is stored in the first reserved area among the empty reserved areas RE1 to RE4 of the reserved area RE. If winning balls have been simultaneously won in the first actuation port 33 and the second actuation port 34, the process for acquiring the reserved information is executed multiple times within the range in which the process for acquiring reserved information is executed once. In addition, when new reserved information is acquired, a corresponding acquisition command is sent to the sound and light emission control device 81. When the audio and light emission control device 81 receives this command, it updates the image displayed on the pattern display device 41, which indicates the number of pending information items, to display content that corresponds to the increase in pending information items.

Then, the information of the special picture special charge counter provided in the main RAM 65 is read (step S402), and the special picture special charge address table provided in the main ROM 64 is read (step S403). Then, a start address corresponding to the information of the special picture special charge counter is obtained from the special picture special charge address table (step S404), and a jump is made to the process indicated by the obtained start address among the processes of steps S406 to S412 (step S405). The special picture special charge counter is a counter that allows the main CPU 63 to grasp which of the various processes of steps S406 to S412 should be executed, and the special picture special charge address table is set with the start address of the program for executing the processes of steps S406 to S412 corresponding to the numerical information of the special picture special charge counter.

In step S406, the special chart change start process is executed. Figure 13 is a flowchart showing the special chart change start process.

In the special chart change start process, the number of reserved information stored in the reserved area RE is 1 or more (step S501: YES), and the data setting process is executed (step S502). In the data setting process, the reserved number is first subtracted by 1, and the data stored in the first reserved area RE1 of the reserved area RE is moved to the execution area AE. Then, a process is executed to shift the data stored in each reserved area RE1 to RE4 of the reserved area RE. This data shift process is a process to shift the data stored in the first reserved area RE1 to the fourth reserved area RE4 to the lower area side in order, and in detail, the data in each area is shifted from the second reserved area RE2 to the first reserved area RE1, the third reserved area RE3 to the second reserved area RE2, the fourth reserved area RE4 to the third reserved area RE3, and so on, and then the fourth reserved area RE4 is cleared to "0". At this time, a shift command to recognize that the data in the reserved area has been shifted is sent to the voice light emission control device 81. When the audio and light emission control device 81 receives this command, it updates the image displayed on the pattern display device 41, which indicates the number of pending information items, to a display content that corresponds to a decrease in the number of pending information items.

After executing the data setting process, the win/lose table is read from the main ROM 64 (step S503). Specifically, first, the current win/lose selection mode is identified by reading information indicating the win/lose selection mode from the main RAM 65. If it is the high probability mode, the high probability win/lose table 64g is read from the main ROM 64. On the other hand, if it is the low probability mode, the setting state of the pachinko machine 10 is identified by reading the value of the setting value counter in the main RAM 65. Then, the low probability win/lose tables 64a to 64f corresponding to the identified setting value are read from the main ROM 64.

Then, the hit/miss table 64a-64g read in step S503 is referenced to execute a hit/miss determination process (step S504). In the hit/miss determination process, it is determined whether the hit/miss determination information stored in the execution area AE, i.e., the numerical information related to the hit random number counter C1, matches the jackpot numerical information set in the hit/miss table 64a-64g read in step S503.

If the result of the win/loss determination process is a jackpot winning result (step S505: YES), an allocation determination process is executed (step S506). In the allocation determination process, the information for allocation determination from the information stored in the execution area AE, i.e., the numerical information related to the jackpot type counter C2, is read out. Then, by referring to the allocation table 64h provided in the main ROM 64, it is determined which jackpot result the numerical information related to the jackpot type counter C2 read out above corresponds to. Specifically, it is determined which jackpot result it corresponds to among a low probability jackpot result, a low prize high probability jackpot result, and a most favorable jackpot result.

Then, a stop result setting process for the jackpot result is executed (step S507). Specifically, information on the form of the pattern to be finally stopped and displayed on the special chart display unit 37a in the game round related to the start of the current fluctuation is identified from a stop result table for the jackpot result stored in advance in the main ROM 64, and the identified information is written to the main RAM 65. In this stop result table for the jackpot result, information on the form of the pattern to be stopped and displayed on the special chart display unit 37a is set differently for each type of jackpot result.

Then, a flag set process corresponding to the distribution determination result is executed (step S508). Specifically, flags corresponding to the types of each jackpot result are provided in the main RAM 65, and in step S508, the flag corresponding to the result of the distribution determination process in step S506 is set to "1".

On the other hand, if it is determined in step S505 that the result is not a jackpot win, a stop result setting process for a miss result is executed (step S509). Specifically, information on the pattern form to be finally stopped and displayed on the special chart display unit 37a in the game round related to the start of the current fluctuation is identified from a stop result table for miss results stored in advance in the main ROM 64, and the identified information is written to the main RAM 65. The information on the pattern form selected in this case is different from the information on the pattern form selected in the case of a jackpot result.

After executing either step S508 or step S509, a process for grasping the duration of the game round is executed (step S510). In this process, the numerical information of the fluctuation type counter CS is acquired. Also, it is determined whether or not a reach display will occur on the pattern display device 41 in the current game round. Specifically, if the game round related to the start of the current fluctuation has a low probability jackpot result or a most favorable jackpot result, it is determined that a reach display will occur. Also, if there is no jackpot result and furthermore the numerical information related to the reach random number counter C3 stored in the execution area AE is numerical information corresponding to the occurrence of a reach, it is determined that a reach display will occur.

If it is determined that a reach display will occur, the reach occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of the game corresponding to the current numerical information of the variable type counter CS. On the other hand, if it is determined that a reach display will not occur, the reach non-occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of the game corresponding to the current numerical information of the variable type counter CS. Incidentally, the duration of the game that can be obtained by reference to the reach non-occurrence duration table is different from the duration of the game that can be obtained by reference to the reach occurrence duration table.

The duration of the game when a reach does not occur is set so that the more reserved information stored in the reserved area RE, the shorter the duration of the game. In addition, the non-reach duration table is set so that a shorter duration of the game is selected when the support mode is a high-frequency support mode than when the support mode is a low-frequency support mode, when the number of reserved information is the same. However, this is not limited to this, and the duration of the game may not change depending on the number of reserved information or the support mode, and the above relationship may be reversed. Furthermore, the above configuration may be applied to the duration of the game when a reach occurs. In addition, a duration table may be set separately for each of various jackpot results, a miss reach, and a miss result without a reach. In this case, the duration of the game is allocated according to each game result.

Then, the information on the duration of the game acquired in step S510 is set in the special chart special electricity timer counter provided in the main RAM 65 (step S511). The update of the numerical information set in the special chart special electricity timer counter is executed in the timer update process (step S310). Incidentally, as a performance for a game round, the display of changing patterns in the special chart display section 37a and the display of changing patterns in the pattern display device 41 are performed, and when each of these display of changes is ended, the final stop display is performed for the final stop period (e.g., 0.5 seconds) with the stop result of that game round displayed (a predetermined combination of patterns is waiting on the pay line in the pattern display device 41). In this case, the duration of the game round acquired in step S510 is the total time for one game round.

Then, the variation command and the type command are sent to the sound and light emission control device 81 (step S512). The variation command includes information on the duration of the game round. Here, as described above, the duration of the game round obtained by referring to the non-reach duration table is different from the duration of the game round obtained by referring to the reach duration table. Therefore, even if the variation command does not include information on whether or not a reach has occurred, the sound and light emission control device 81 can determine whether or not a reach has occurred from the information on the duration of the game round. In this respect, it can be said that the variation command includes information indicating whether or not a reach has occurred. Note that the variation command may also include information directly indicating whether or not a reach has occurred. Furthermore, the type command includes information on the game result.

When the sound and light emission control device 81 receives a variation command and a type command from the main CPU 63, it causes the display light emitting unit 53, the speaker unit 54 and the pattern display device 41 to execute the presentation for the game round. In this case, the presentation for that game round is executed in a manner corresponding to the contents of the variation command and the type command. In addition, the pattern display device 41 displays a variation of the patterns as the presentation for the game round, and when the presentation for that game round ends, a combination of patterns corresponding to the results of the win/lose determination process and the allocation determination process is displayed frozen.

Then, the display of the changing pattern on the special chart display section 37a is started (step S513). Then, the special chart special electricity counter is incremented by 1 (step S514). In this case, since the numerical information of the special chart special electricity counter is "0" when the special chart change start process is executed, the numerical information of the special chart special electricity counter becomes "1". Then, the eleventh output flag provided in the main RAM 65 is set to "1" (step S515). The eleventh output flag is a flag for specifying to the main CPU 63 that information output indicating that a game round has started should be executed to the management IC 66.

Returning to the explanation of the special chart special electricity control process (FIG. 52), in step S407, special chart change processing is executed. In the special chart change processing, it is determined whether or not it is during the duration of a game round and before the final stop display, and if it is before the final stop display, processing is executed to regularly change the display mode of the image in the special chart display section 37a. When it is time to display the final stop, the numerical information of the special chart special electricity counter is incremented by 1, thereby updating the numerical information of the counter from that corresponding to the special chart change processing to that corresponding to the special chart determination processing. Note that in this embodiment, a final stop command is not transmitted from the main CPU 63 to the sound and light emission control device 81.

In step S408, a special chart determination process is executed. In the special chart determination process, the display mode of the image on the special chart display unit 37a is changed to a display mode corresponding to the lottery result of the current game round. In addition, in the special chart determination process, it is determined whether the final stop period has elapsed, and if the period has elapsed, it is determined whether a transition to the opening and closing execution mode will occur. If a transition to the opening and closing execution mode does not occur, the numerical information of the special chart special electricity counter is cleared to "0". If a transition to the opening and closing execution mode occurs, the numerical information of the special chart special electricity counter is incremented by 1, thereby updating the numerical information of the counter from that corresponding to the special chart determination process to that corresponding to the special electricity start process.

In step S409, the special power start process is executed. In the special power start process, if the process for starting the opening period in the current opening/closing execution mode has not yet been executed, the process for setting the opening period is executed. In addition, an opening command is sent to the sound and light emission control device 81. By receiving the opening command, the sound and light emission control device 81 causes the display light-emitting unit 53, the speaker unit 54, and the pattern display device 41 to execute the opening performance. If the opening period has elapsed, a start process is executed to start the first round of play. In the start process, the special power winning device 32 is opened and the end condition of the round of play is set. When setting this end condition, the upper limit of the duration for which the special power winning device 32 is to be kept open in the current first round of play is set, and the upper limit of the number of game balls that can be won in the special power winning device 32 in the current first round of play is set in the winning number counter provided in the main RAM 65.

In step S410, the special line open process is executed. In the special line open process, it is determined whether the end condition of the round game is met. If the end condition is met, the special line winning device 32 is closed. If the currently ended round game is not the last round game executed, the numerical information of the special chart special line counter is incremented by 1 to update the numerical information of the counter from that corresponding to the special line open process to that corresponding to the special line closed process, and if the currently ended round game is the last round game executed, the numerical information of the special chart special line counter is incremented by 2 to update the numerical information of the counter from that corresponding to the special line open process to that corresponding to the special line end process.

In step S411, special line closed processing is executed. In the special line closed processing, it is determined whether or not the interval period between rounds of play has elapsed. The interval period is set when the previous round of play ends. When the interval period has elapsed, the special line winning device 32 is opened and the end condition for the round of play is set. Then, the numerical information of the special chart special line counter is subtracted by 1, thereby updating the numerical information of the counter from that corresponding to the special line closed processing to that corresponding to the special line open processing.

In step S412, the special call termination process is executed. In the special call termination process, if the process for starting the ending period in the current opening/closing execution mode has not yet been executed, the ending period (e.g., 5 seconds) is set and an ending command is sent to the sound and light emission control device 81. By receiving the ending command, the sound and light emission control device 81 causes the display light-emitting unit 53, speaker unit 54, and pattern display device 41 to execute an ending performance. When the ending period has elapsed, the win/lose lottery mode and support mode after the end of the opening/closing execution mode are each set to a mode corresponding to the jackpot result that triggered the start of the current opening/closing execution mode.

Next, we will explain the configuration in the main CPU 63 to determine whether or not a game ball has entered the outlet 24a, general winning port 31, special electric winning device 32, first operating port 33, second operating port 34, and through gate 35 based on the detection results of each ball entry detection sensor 42a to 49a. Figure 14 is an explanatory diagram for explaining the configuration in which the detection results of the ball entry detection sensors 42a to 49a are input to the main CPU 63.

The main CPU 63 is provided with an input port 63a. The input port 63a is configured as an 8-bit parallel interface so that it can handle eight types of signals simultaneously. An area in which information "0" or "1" is stored according to the voltage of each signal is provided in one-to-one correspondence with each terminal. In other words, this area includes the 0th bit D0 to the 7th bit D7. Although more than eight types of signals are input to the input port 63a, in order to limit the types of signals that can be input simultaneously to eight types, the group of signals to be input to the input port 63a is switched through switching control by the driver IC.

In the ball entry detection process (step S309) of the timer interrupt process (FIG. 11), the signal group to be input to the input port 63a is set to the signal group from each ball entry detection sensor 42a to 49a. In a situation where such a setting has been made, the 0th bit D0 stores information corresponding to the detection signal from the first winning opening detection sensor 42a, the 1st bit D1 stores information corresponding to the detection signal from the second winning opening detection sensor 43a, the 2nd bit D2 stores information corresponding to the detection signal from the third winning opening detection sensor 44a, the 3rd bit D3 stores information corresponding to the detection signal from the special electric detection sensor 45a, the 4th bit D4 stores information corresponding to the detection signal from the first operation opening detection sensor 46a, the 5th bit D5 stores information corresponding to the detection signal from the second operation opening detection sensor 47a, the 6th bit D6 stores information corresponding to the detection signal from the out opening detection sensor 48a, and the 7th bit D7 stores information corresponding to the detection signal from the gate detection sensor 49a.

Each of the ball entry detection sensors 42a to 49a outputs a LOW level signal indicating that it is not detecting as a detection signal when it does not detect the passage of a game ball, and outputs a HI level signal indicating that it is detecting as a detection signal when it detects the passage of a game ball. When the input port 63a receives a LOW level signal, it stores "0" information in the corresponding bit, and when it receives a HI level signal, it stores "1" information in the corresponding bit. In other words, when the ball entry detection sensors 42a to 49a do not detect the passage of a game ball, the corresponding bit stores "0" information corresponding to the information indicating that it is not detecting, and when the ball passage is detected, the corresponding bit stores "1" information corresponding to the information indicating that it is detecting.

Figure 15 is a flowchart showing the ball entry detection process executed in step S309 of the timer interrupt process (Figure 11).

When it is confirmed that the 0th bit D0 has switched from a state in which "0" information is stored to a state in which "1" information is stored, it is determined that one game ball has been detected by the first winning hole detection sensor 42a (step S601: YES). In this case, the first output flag provided in the main RAM 65 is set to "1" (step S602), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S603). The first output flag is a flag for the main CPU 63 to specify that information output indicating that one game ball has been detected by the first winning hole detection sensor 42a should be executed to the management IC 66. The 10-ball counter is a counter for the main CPU 63 to specify the number of times that the payout of 10 game balls should be executed. If the value of the 10 prize ball counter is 1 or more, a 10 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (Figure 11), and the value of the 10 prize ball counter is decremented by 1 when the 10 prize ball command is output once. When the payout control device 77 receives the 10 prize ball command, it drives and controls the payout device 76 so that 10 game balls are paid out.

When it is confirmed that the first bit D1 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the second winning hole detection sensor 43a (step S604: YES). In this case, the second output flag provided in the main RAM 65 is set to "1" (step S605), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S606). The second output flag is a flag that specifies to the main CPU 63 that information indicating that one game ball has been detected by the second winning hole detection sensor 43a should be output to the management IC 66.

If it is confirmed that the second bit D2 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the third winning hole detection sensor 44a (step S607: YES). In this case, the third output flag provided in the main RAM 65 is set to "1" (step S608), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S609). The third output flag is a flag that specifies to the main CPU 63 that information indicating that one game ball has been detected by the third winning hole detection sensor 44a should be output to the management IC 66.

If it is confirmed that the third bit D3 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the special electric detection sensor 45a (step S610: YES). In this case, the special electric winning flag provided in the main RAM 65 is set to "1" (step S611), the fourth output flag provided in the main RAM 65 is set to "1" (step S612), and the value of the 15-ball counter provided in the main RAM 65 is incremented by 1 (step S613). The special electric winning flag is a flag for the main CPU 63 to identify that one game ball has entered the special electric winning device 32 during round play in the open/close execution mode. In the special chart special electric control process (step S313) of the timer interrupt process (FIG. 11), by confirming that the special electric winning flag is set to "1", it is determined that one game ball has entered the special electric winning device 32, and the number of remaining balls that can enter the special electric winning device 32 in the round game is reduced by one. When the process of reducing the number of balls that can enter by one is executed, the special electric winning flag is cleared to "0". The fourth output flag is a flag for the main CPU 63 to determine that information output indicating that one game ball has been detected by the special electric detection sensor 45a should be executed to the management IC 66. The 15-ball counter is a counter for the main CPU 63 to determine the number of times that 15 game balls should be paid out. If the value of the 15 prize ball counter is 1 or more, a 15 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (FIG. 11), and the value of the 15 prize ball counter is decremented by 1 when the 15 prize ball command is output once. When the payout control device 77 receives the 15 prize ball command, it drives and controls the payout device 76 so that 15 game balls are paid out.

If it is confirmed that the fourth bit D4 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the first actuation port detection sensor 46a (step S614: YES). In this case, the first actuation winning flag provided in the main RAM 65 is set to "1" (step S615), the fifth output flag provided in the main RAM 65 is set to "1" (step S616), and the value of the one-ball counter provided in the main RAM 65 is incremented by one (step S617). The first actuation winning flag is a flag for the main CPU 63 to identify that one game ball has entered the first actuation port 33. In the special chart special power control process (step S313) of the timer interrupt process (FIG. 11), by confirming that the first operation winning flag is set to "1", a process for newly storing the reserved information is executed on the condition that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit of four. In the special power special power control process (step S313), it is confirmed that the first operation winning flag is set to "1", and when the process corresponding to the confirmation is executed, the first operation winning flag is cleared to "0". The fifth output flag is a flag for specifying in the main CPU 63 that the information output indicating that one game ball has been detected by the first operation port detection sensor 46a should be executed to the management IC 66. The one prize ball counter is a counter for specifying in the main CPU 63 the number of times that one game ball should be paid out. If the value of the 1 prize ball counter is 1 or more, a 1 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (FIG. 11), and the value of the 1 prize ball counter is decremented by 1 when the 1 prize ball command is output once. When the payout control device 77 receives the 1 prize ball command, it drives and controls the payout device 76 so that one game ball is paid out.

If it is confirmed that the fifth bit D5 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the second operation port detection sensor 47a (step S618: YES). In this case, the second operation winning flag provided in the main RAM 65 is set to "1" (step S619), the sixth output flag provided in the main RAM 65 is set to "1" (step S620), and the value of the one-ball counter provided in the main RAM 65 is incremented by one (step S621). The second operation winning flag is a flag for the main CPU 63 to identify that one game ball has entered the second operation port 34. In the special chart special electric control process (step S313) of the timer interrupt process (FIG. 11), by confirming that the second activation winning flag is set to "1", a process is executed to store new reserved information, provided that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit of four. In the special electric special electric control process (step S313), it is confirmed that the second activation winning flag is set to "1", and when the process corresponding to that confirmation is executed, the second activation winning flag is cleared to "0". The sixth output flag is a flag for specifying in the main CPU 63 that information output indicating that one game ball has been detected by the second activation port detection sensor 47a should be executed to the management IC 66.

If it is confirmed that the sixth bit D6 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the outlet detection sensor 48a (step S622: YES). In this case, the seventh output flag provided in the main RAM 65 is set to "1" (step S623). The seventh output flag is a flag that specifies to the main CPU 63 that information indicating that one game ball has been detected by the outlet detection sensor 48a should be output to the management IC 66.

If it is confirmed that the seventh bit D7 has switched from a state in which "0" information is stored to a state in which "1" information is stored, it is determined that one game ball has been detected by the gate detection sensor 49a (step S624: YES). In this case, the gate winning flag provided in the main RAM 65 is set to "1" (step S625). The gate winning flag is a flag for the main CPU 63 to identify that one game ball has entered the through gate 35. In the normal map normal power control process (step S314) of the timer interrupt process (FIG. 11), by confirming that the gate winning flag is set to "1", the process is executed to store the current numerical information of the normal power role release counter C4 as the normal map side reserved information in the normal power reserve area 65c, provided that the number of reserved information on the normal map side stored in the normal power reserve area 65c is less than the upper limit of four. In the normal map and normal power control process (step S314), it is confirmed that the gate winning flag is set to "1", and when the process corresponding to that confirmation is executed, the gate winning flag is cleared to "0".

As already explained, the timer interrupt process (Figure 11) is started at a 4 millisecond cycle, so when one of the ball entry detection sensors 42a-49a starts to detect one game ball, the main CPU 63 determines that one game ball has been detected by the ball entry detection sensor 42a-49a while the ball entry detection sensor 42a-49a continues to detect that one game ball. Therefore, it is sufficient to provide one each of the first through seventh output flags.

Next, we will explain the processing executed by the dispensing control device 77. First, we will explain the electrical configuration of the dispensing control device 77 and the various devices that communicate with the dispensing control device 77, with reference to the block diagram in Figure 16.

The payout control device 77 is equipped with an MPU 91. In addition to a payout side CPU 92, which is a calculation processing device including a control unit and a calculation unit, the MPU 91 also includes a payout side ROM 93, a payout side RAM 94, an interrupt circuit, a timer circuit, a data input/output circuit, etc.

The payout side ROM 93 is a memory (i.e., a non-volatile memory means) that does not require an external power supply to retain memory, such as a NOR type flash memory or a NAND type flash memory, and is used for read-only purposes. The payout side ROM 93 stores various control programs and fixed value data executed by the payout side CPU 92.

The payout side RAM 94 is a memory (i.e., a volatile memory means) that requires an external power supply to retain memory, such as SRAM and DRAM, and is used for both reading and writing. The payout side RAM 94 is randomly accessible, and when compared with the payout side ROM 93 for the same data capacity, the payout side RAM 94 requires less time to read. The payout side RAM 94 temporarily stores various data for the execution of the control program stored in the payout side ROM 93.

The payout side CPU 92 is capable of two-way communication with the main CPU 63. By receiving a prize ball command from the main CPU 63, the payout side CPU 92 drives and controls the payout device 76 so that the number of game balls corresponding to the prize ball command is paid out. The payout side CPU 92 also monitors whether or not the game balls can be paid out normally, and when it is determined that the game balls cannot be paid out normally, it stops the payout device 76 even if the payout side RAM 94 stores information on the number of prize balls that have not been paid out. The payout side CPU 92 also transmits a payout limit command to the main CPU 63 indicating that the game balls cannot be paid out normally. When the main CPU 63 receives the payout limit command, it transmits a notification command to the sound and light emission control device 81 so that a notification indicating that the game balls cannot be paid out normally is executed by the pattern display device 41, the display light emission unit 53, and the speaker unit 54. The states in which game balls cannot be dispensed normally include a full state in which the lower tray 56a is full of game balls, a no-ball state in which the tank 75 has not been refilled with game balls, an abnormal dispense state in which the dispenser 76 does not operate normally, a main body open state in which the gaming machine main body 12 is open from the outer frame 11, and a front door open state in which the front door frame 14 is open from the inner frame 13.

A full tank detection sensor (not shown) is provided midway along the game ball passageway leading from the payout device 76 to the lower tray 56a, and the detection result of the full tank detection sensor is input to the payout side CPU 92. The payout side CPU 92 determines that the tank is full when game balls are continuously detected by the full tank detection sensor, and determines that the full tank state has been released when the state in which game balls are continuously detected by the full tank detection sensor is released.

A no-ball detection sensor (not shown) is provided at a midway point in the game ball passageway leading from the tank 75 to the payout device 76, and the detection result of the no-ball detection sensor is input to the payout side CPU 92. The payout side CPU 92 determines that a no-ball state exists when the no-ball detection sensor continues to not detect game balls, and determines that the no-ball state has been released when the state in which the no-ball detection sensor continues to not detect game balls is released.

The payout device 76 is provided with a payout detection sensor (not shown) for detecting game balls paid out from the payout device 76, and the detection result of the payout detection sensor is input to the payout side CPU 92. The payout side CPU 92 determines that one game ball has been paid out from the payout device 76 when a game ball is detected by the payout detection sensor. The payout side CPU 92 also determines that an abnormal payout state exists when a game ball is not continuously detected by the payout detection sensor despite the payout device 76 being driven and controlled so that a game ball is paid out, and determines that the abnormal payout state has been released when the state in which a game ball is not continuously detected by the payout detection sensor is released.

A front door open sensor 95 is provided on the front part of the inner frame 13 (see FIG. 2), and the detection result of the front door open sensor 95 is input to the dispensing side CPU 92. In this case, when the front door frame 14 is in a closed state relative to the inner frame 13, the front door open sensor 95 transmits a closed detection signal to the dispensing side CPU 92, and when the front door frame 14 is in an open state relative to the inner frame 13, the front door open sensor 95 transmits an open detection signal to the dispensing side CPU 92. When the dispensing side CPU 92 receives a closed detection signal from the front door open sensor 95, it determines that the front door frame 14 is in a closed state, and when it receives an open detection signal from the front door open sensor 95, it determines that the front door frame 14 is in an open state. In addition, the dispensing side CPU 92 transmits a front door open command to the main side CPU 63 at the timing when it determines that the front door frame 14 has changed from a closed state to an open state, and transmits a front door close command to the main side CPU 63 at the timing when it determines that the front door frame 14 has changed from an open state to a closed state. The main CPU 63 determines that the front door frame 14 is in an open state when it receives a front door open command, and determines that the front door frame 14 is in a closed state when it receives a front door close command.

A main body open sensor 96 is provided on the front of the back pack unit 15 (see FIG. 2), and the detection result of the main body open sensor 96 is input to the payout side CPU 92. In this case, when the gaming machine main body 12 is in a closed state relative to the outer frame 11, the main body open sensor 96 transmits a closed detection signal to the payout side CPU 92, and when the gaming machine main body 12 is in an open state relative to the outer frame 11, the main body open sensor 96 transmits an open detection signal to the payout side CPU 92. When the payout side CPU 92 receives a closed detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in a closed state, and when it receives an open detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in an open state. In addition, the payout side CPU 92 transmits a main body open command to the main side CPU 63 at the timing when it determines that the gaming machine main body 12 has changed from a closed state to an open state, and transmits a main body close command to the main side CPU 63 at the timing when it determines that the gaming machine main body 12 has changed from an open state to a closed state. The main CPU 63 determines that the gaming machine main body 12 is in an open state when it receives a main body open command, and determines that the gaming machine main body 12 is in a closed state when it receives a main body close command.

The timer interrupt process executed by the payout CPU 92 will be described with reference to the flowchart in Figure 17. The timer interrupt process is repeatedly started at a predetermined cycle (e.g., every 2 milliseconds).

First, the full tank process is executed (step S701). In the full tank process, as already explained, it is determined whether the tank is full or not based on the detection result of the full tank detection sensor, and if the tank is full, a process is executed to stop the payout of game balls and a command indicating that the tank is full is sent to the main CPU 63. Furthermore, if the full tank state is released, a process is executed to enable the payout of game balls and a command is sent to the main CPU 63 indicating that the full tank state has been released.

After that, the no-ball process is executed (step S702). In the no-ball process, as already explained, it is determined whether or not the no-ball state is present based on the detection result of the no-ball detection sensor, and if the no-ball state is present, a process is executed to stop the payout of game balls, and a command indicating the no-ball state is sent to the main CPU 63. In addition, if the no-ball state is released, a process is executed to enable the payout of game balls, and a command indicating that the no-ball state has been released is sent to the main CPU 63.

Then, a payout abnormality monitoring process is executed (step S703). In the payout abnormality monitoring process, as already explained, it is determined whether or not a payout abnormality state exists based on the detection result of the payout detection sensor, and if a payout abnormality state exists, a process is executed to stop the payout of game balls, and a command is sent to the main CPU 63 indicating that a payout abnormality state exists. In addition, if the payout abnormality state is released, a process is executed to enable the payout of game balls, and a command is sent to the main CPU 63 indicating that the payout abnormality state has been released.

Then, a front door open monitoring process is executed (step S704). In the front door open monitoring process, as already explained, it is determined whether the front door frame 14 is open or not based on the detection result of the front door open sensor 95, and if the front door frame 14 is open, a process is executed to stop the payout of game balls and a front door open command is sent to the main CPU 63. In addition, if the front door frame 14 is closed, a process is executed to enable the payout of game balls and a front door close command is sent to the main CPU 63.

Then, the main body open monitoring process is executed (step S705). As already explained, the main body open monitoring process determines whether the gaming machine main body 12 is open or not based on the detection result of the main body open sensor 96, and if the gaming machine main body 12 is open, a process is executed to stop the payout of gaming balls and a main body open command is sent to the main CPU 63. In addition, if the gaming machine main body 12 is closed, a process is executed to enable the payout of gaming balls and a main body close command is sent to the main CPU 63.

Then, a command read process is executed (step S706). In the command read process, a process for reading the prize ball command sent by the main CPU 63 is executed, and the prize ball command is stored in the payout side RAM 94. Then, after executing a prize ball setting process for adding the number corresponding to the received prize ball command to the unpaid prize ball number information in the payout side RAM 94 (step S707), a payout control process for controlling the execution of the payout of game balls by the payout device 76 is executed (step S708). In the payout control process, when the unpaid prize ball number information stored in the payout side RAM 94 is a value of 1 or more, the payout device 76 is driven and controlled, and when the payout detection sensor detects one game ball, the value of the prize ball number information is subtracted by 1. Then, when the value of the prize ball number information becomes "0", the drive control of the payout device 76 is stopped. After that, an external information setting process is executed to control the start and end of the output of an external signal according to the results of the various processes executed in this timer interrupt process (step S709).

Next, we will explain the configuration for externally outputting information from the pachinko machine 10 to the hall computer HC installed in the gaming hall.

As shown in FIG. 2, the back pack unit 15 is provided with an external terminal board 97. The external terminal board 97 is provided with a large number of external terminals, some of which are electrically connected to the main CPU 63, and some of which are electrically connected to the payout CPU 92. In this way, the main CPU 63 and the payout CPU 92 are each electrically connected to the external terminal board 97, so that the main CPU 63 and the payout CPU 92 can externally output information to the hall computer HC, as shown in FIG. 16.

One external terminal of the external terminal board 97 is electrically connected to the front door open sensor 95, and one external terminal of the external terminal board 97 is electrically connected to the main body open sensor 96. Regarding the configuration of this electrical connection in detail, a signal relay board 98 is provided at a midpoint of the signal path from the front door open sensor 95 to the dispensing side CPU 92. The signal relay board 98 is provided with a branch path SL2 that branches from the signal path SL1 from the front door open sensor 95 to the dispensing side CPU 92. The branch path SL2 is connected to the external terminal for opening the front door on the external terminal board 97. Therefore, the electrical signal corresponding to the detection result of the front door open sensor 95 is not only input to the dispensing side CPU 92, but also input to the external terminal for opening the front door on the external terminal board 97. This makes it possible to externally output a signal indicating whether the front door frame 14 is in an open state to the hall computer HC without going through the control of the dispensing side CPU 92.

Regarding the main body open sensor 96 in detail, the signal relay board 98 has a branch path SL4 that branches off from the signal path SL3 that runs from the main body open sensor 96 to the payout side CPU 92. The branch path SL4 is connected to an external terminal for main body opening on the external terminal board 97. Therefore, an electrical signal corresponding to the detection result of the main body open sensor 96 is not only input to the payout side CPU 92, but also input to the external terminal for main body opening on the external terminal board 97. This makes it possible to externally output a signal indicating whether the gaming machine main body 12 is in an open state to the hall computer HC without going through the control of the payout side CPU 92.

Next, we will explain the contents of the information that is externally output from the main CPU 63 and the payout CPU 92 to the hall computer HC. First, we will explain the contents of the information that is externally output from the main CPU 63 to the hall computer HC.

In the external information setting process (step S318) in the timer interrupt process (FIG. 11), the main CPU 63 sets the output of information to each external terminal assigned to the main CPU 63 on the external terminal board 97. The information output from the main CPU 63 to the external terminal board 97 includes information indicating that the opening/closing execution mode is in progress, information indicating that the support mode is in the high frequency support mode, information indicating that one game round has ended, information indicating that a predetermined number (e.g., 100 balls) of game balls have been discharged from the game area PA through the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, or the second operating port 34, information indicating that a game ball has entered the first operating port 33, and information indicating that a game ball has entered the second operating port 34.

In the external information setting process (step S709) of the timer interrupt process (FIG. 17), the payout CPU 92 sets the output of information to each external terminal assigned to the payout CPU 92 on the external terminal board 97. The information output from the payout CPU 92 to the external terminal board 97 includes information indicating that 10 game balls have been paid out.

The hall computer HC can grasp the manner in which the game balls are paid out in the pachinko machine 10 in accordance with various information received from the pachinko machine 10 via the external terminal board 97. For example,
・The ball payout rate, which is the ratio of the number of game balls paid out until 100 game balls are discharged from the game area PA of the pachinko machine 10. ・The ball payout rate in a normal game state other than the open/close execution mode and the high frequency support mode (hereinafter, this ball payout rate will be referred to as "B")
・The ball output rate in the open/close execution mode ・The ball output rate in the high frequency support mode ・The number of times the game is executed until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio is referred to as "S")
B-S x "number of winning balls for winning the first actuation port 33 and the second actuation port 34"
The number of game balls that enter the first operating port 33 until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio is referred to as "S1")
The number of game balls that enter the second operating port 34 until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio is referred to as "S2")
B-(S1 x "number of winning balls for winning through the first actuation port 33" + S2 x "number of winning balls for winning through the second actuation port 34")
The probability of occurrence of the open/close execution mode per unit play time, the probability of occurrence of the high frequency support mode per unit play time, etc. are calculated. This allows the hall computer HC to manage the ball entry patterns of the game balls in the play area PA of the pachinko machine 10. The number of prize balls refers to the number of game balls paid out when one game ball enters the corresponding ball entry section.

<Configuration for managing winning status of gaming balls>
Next, a description will be given of a configuration for managing a game history using the management IC 66. First, the electrical configuration of the management IC 66 will be described with reference to the block diagram of FIG.

As already explained, the MPU 62 of the main control device 60 includes a main CPU 63, a main ROM 64, a main RAM 65, and a management IC 66. In addition to these, the MPU 62 also includes an I/F 101, and the read terminal 68d already explained.

The I/F 101 is an interface for sending and receiving signals between the MPU 62 and devices external to the MPU 62. The I/F 101 is electrically connected to the main CPU 63 via the internal bus 103. Through the input port of the I/F 101, the detection results from the ball entry detection sensors 42a to 49a and commands from the payout CPU 92 are input to the MPU 62, and various processes are executed by the main CPU 63 as described above based on the input detection results and command contents. In addition, when a signal is output to a device such as the special power drive unit 32b as a result of the execution of various processes by the main CPU 63, the signal output is performed through the output port of the I/F 101, and when a command is output to the payout CPU 92 and the sound and light emission control device 81 as a result of the execution of various processes by the main CPU 63, the command output is performed through the output port of the I/F 101.

The management IC 66 includes a management I/F 111, a management CPU 112, a management ROM 113, a management RAM 114, an RTC 115, a correspondence memory 116, a history memory 117, and a calculation result memory 131. These devices are connected to each other via an internal bus 66a provided in the management IC 66 so as to enable two-way communication.

The management side I/F 111 is an interface for receiving various signals from the main CPU 63 via a group of signal paths 118 for one-way communication built into the MPU 62, and for transmitting various signals to the reading terminal 68d via a group of signal paths 119 for one-way communication built into the MPU 62. Various signals from the main CPU 63 are input to an input port of the management side I/F 111, and various signals to the reading terminal 68d are output from an output port of the management side I/F 111. The main CPU 63 is electrically connected to the reading terminal 68d via a group of signal paths 120 for two-way communication built into the MPU 62.

The management CPU 112 is a processing unit including a control unit and a calculation unit. The management ROM 113 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain memory such as a NOR flash memory and a NAND flash memory, and is used for read-only purposes. The management ROM 113 stores various control programs and fixed value data executed by the management CPU 112. The management RAM 114 is a memory (i.e., a volatile storage means) that requires an external power supply to retain memory such as an SRAM and a DRAM, and is used for both reading and writing. The management RAM 114 is randomly accessible, and when compared with the same data capacity, it takes less time to read than the management ROM 113. The management RAM 114 temporarily stores various data and the like for the execution of the control programs stored in the management ROM 113.

The RTC 115 is a real-time clock that constantly measures date and time information and is capable of outputting the measured date and time information (hereinafter also referred to as date and time information) according to instructions from the management CPU 112. The RTC 115 is equipped with a backup power supply, making it possible to measure date and time information even when the power to the pachinko machine 10 is cut off.

The correspondence memory 116 is a memory (i.e., a volatile storage means) that requires an external power supply to retain data, such as SRAM and DRAM, and is used for both reading and writing. The correspondence memory 116 is used to store information on the correspondence between each of the buffers 122a to 122p provided in the input port 121 of the management side I/F 111 and the types of signals input to those buffers 122a to 122p. The contents of the correspondence memory 116 will be described in detail later.

The history memory 117 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for both reading and writing. The history memory 117 is used to store information regarding the game history received from the main CPU 63 via the management I/F 111. The contents of the history memory 117 will be described in detail later.

The calculation result memory 131 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for both reading and writing. The calculation result memory 131 is used to sequentially store various parameters calculated by the management CPU 112 using the history information stored in the history memory 117. The contents of the various parameters stored in the calculation result memory 131 are sequentially displayed on the first to third notification display devices 69a to 69c, and are also output to an external device connected to the read terminal 68d.

Next, the configuration of the input port 121 provided in the management side I/F 111 will be described. Figure 19 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I/F 111.

The input port 121 is provided with a number of buffers 122a-122p. Specifically, first to sixteenth buffers 122a-122p are provided. Each of the first to sixteenth buffers 122a-122p can receive one type of signal via signal paths 118a-118p, and each of the first to sixteenth buffers 122a-122p stores "0" as the first data when the input signal is at a LOW level, and stores "1" as the second data when the input signal is at a HI level. Note that the relationship between LOW and HI and the first and second data may be reversed.

A first signal corresponding to the detection result of the first winning hole detection sensor 42a is input to the first buffer 122a. In this case, the main CPU 63 outputs a LOW level first signal when no new game balls are detected by the first winning hole detection sensor 42a, and outputs a HI level first signal for a specific period of time when one game ball is detected by the first winning hole detection sensor 42a. This specific period is sufficient for the management CPU 112 to determine that a HI level first signal has been input to the first buffer 122a.

A second signal corresponding to the detection result of the second winning hole detection sensor 43a is input to the second buffer 122b. In this case, the main CPU 63 outputs a LOW level second signal when no new game balls are detected by the second winning hole detection sensor 43a, and outputs a HI level second signal for a specific period of time when one game ball is detected by the second winning hole detection sensor 43a. This specific period is sufficient for the management CPU 112 to determine that a HI level second signal has been input to the second buffer 122b.

A third signal corresponding to the detection result of the third winning hole detection sensor 44a is input to the third buffer 122c. In this case, the main CPU 63 outputs a LOW level third signal when no new game balls are detected by the third winning hole detection sensor 44a, and outputs a HI level third signal for a specific period of time when one game ball is detected by the third winning hole detection sensor 44a. This specific period is sufficient for the management CPU 112 to determine that a HI level third signal has been input to the third buffer 122c.

A fourth signal corresponding to the detection result of the special electric detection sensor 45a is input to the fourth buffer 122d. In this case, the master CPU 63 outputs a LOW level fourth signal when no new game balls are detected by the special electric detection sensor 45a, and outputs a HI level fourth signal for a specific period of time when one game ball is detected by the special electric detection sensor 45a. This specific period is sufficient for the management CPU 112 to determine that a HI level fourth signal has been input to the fourth buffer 122d.

A fifth signal corresponding to the detection result of the first actuation port detection sensor 46a is input to the fifth buffer 122e. In this case, the main CPU 63 outputs a LOW level fifth signal when no new game ball is detected by the first actuation port detection sensor 46a, and outputs a HI level fifth signal for a specific period of time when one game ball is detected by the first actuation port detection sensor 46a. This specific period is sufficient for the management CPU 112 to determine that a HI level fifth signal has been input to the fifth buffer 122e.

A sixth signal corresponding to the detection result of the second actuation port detection sensor 47a is input to the sixth buffer 122f. In this case, the main CPU 63 outputs a LOW level sixth signal when no new game ball is detected by the second actuation port detection sensor 47a, and outputs a HI level sixth signal for a specific period of time when one game ball is detected by the second actuation port detection sensor 47a. This specific period is sufficient for the management CPU 112 to determine that a HI level sixth signal has been input to the sixth buffer 122f.

The seventh buffer 122g receives a seventh signal corresponding to the detection result of the outlet detection sensor 48a. In this case, the main CPU 63 outputs a LOW level seventh signal when no new game balls are detected by the outlet detection sensor 48a, and outputs a HI level seventh signal for a specific period of time when one game ball is detected by the outlet detection sensor 48a. This specific period is sufficient for the management CPU 112 to determine that a HI level seventh signal has been input to the seventh buffer 122g.

An eighth signal corresponding to whether or not the open/close execution mode is in progress is input to the eighth buffer 122h. In this case, the main CPU 63 continuously outputs a LOW level eighth signal when the open/close execution mode is not in progress, and continuously outputs a HI level eighth signal when the open/close execution mode is in progress.

The ninth buffer 122i receives a ninth signal corresponding to whether or not the high-frequency support mode is in effect. In this case, the main CPU 63 continuously outputs a LOW-level ninth signal when the high-frequency support mode is not in effect, and continuously outputs a HI-level ninth signal when the high-frequency support mode is in effect.

The tenth buffer 122j receives a tenth signal corresponding to whether the front door frame 14 is open or not. In this case, the main CPU 63 continuously outputs a LOW level tenth signal when the front door frame 14 is closed, and continuously outputs a HI level tenth signal when the front door frame 14 is open.

An 11th signal corresponding to whether or not a game round has started is input to the 11th buffer 122k. In this case, the master CPU 63 continues to output a LOW level 11th signal until a game round starts, and outputs a HIGH level 11th signal for a specific period of time when a game round starts. This specific period is sufficient for the management CPU 112 to determine that a HIGH level 11th signal has been input to the 11th buffer 122k.

A setting value update signal is input to the 15th buffer 122o to make the management CPU 112 recognize that the setting state of the pachinko machine 10 has been newly set by the main CPU 63. In this case, the main CPU 63 outputs a LOW level setting value update signal when the setting state of the pachinko machine 10 has not been newly set, and outputs a HI level setting value update signal, a pulse signal that is maintained for a specific period of time, for the number of times corresponding to the newly set setting value when the setting state of the pachinko machine 10 has been newly set. This specific period is sufficient for the management CPU 112 to determine that a HI level setting value update signal has been input to the 15th buffer 122o.

An output instruction signal is input to the 16th buffer 122p to cause the management CPU 112 to recognize the opportunity to output the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131 to the read terminal 68d. In this case, the main CPU 63 outputs a LOW level output instruction signal when there is no need to output the history information, and outputs a HI level output instruction signal for a specific period of time when there is a need to output the history information. This specific period is sufficient for the management CPU 112 to identify that a HI level output instruction signal has been input to the 16th buffer 122p.

The twelfth buffer 122l, the thirteenth buffer 122m and the fourteenth buffer 122n are capable of receiving signals from the main CPU 63, but are blank in this pachinko machine 10 and do not receive normal signals. In this way, by providing a greater number of buffers 122a-122p as input ports 121 of the management I/F 111 in this pachinko machine 10 than the number of types of signals output from the main CPU 63 to the management IC 66, it becomes possible to use the management IC 66 in models other than this pachinko machine 10. This makes it possible to increase the versatility of the management IC 66. Incidentally, signal paths 118a-118p are formed between the main CPU 63 and the first through sixteenth buffers 122a-122p so as to correspond one-to-one to the first through sixteenth buffers 122a-122p, respectively, but this is not limited to this, and the signal paths 118l-118n may not be formed between the buffers 122l-122n to be blanked.

The input of a set value update signal to the 15th buffer 122o and the input of an output instruction signal to the 16th buffer 122p are determined in the design stage of the management IC 66, and the management CPU 112 can determine that a set value update signal is input to the 15th buffer 122o and that an output instruction signal is input to the 16th buffer 122p without receiving an instruction from the main CPU 63. On the other hand, the type of signals input to the first to fourteenth buffers 122a to 122n is not determined in the design stage of the management IC 66, and the types of these signals are identified by the management CPU 112 upon receiving an instruction from the main CPU 63. The identification of the types of these signals in the management CPU 112 is performed by transmitting a type identification command from the main CPU 63 to the management CPU 112 when control is started in the main CPU 63 and the management CPU 112 as the supply of operating power to the MPU 62 begins, as will be described in detail later. In this case, the information on the types of various signals provided by the type identification command is stored in the correspondence memory 116, and when the management CPU 112 identifies the types of various signals when operating power is being supplied, the information stored in the correspondence memory 116 is referenced.

Figure 20 is an explanatory diagram for explaining the configuration of the correspondence memory 116. The correspondence memory 116 has first to fourteenth correspondence areas 123a to 123n that correspond one-to-one to the first to fourteenth buffers 122a to 122n provided in the input port 121 of the management side I/F 111.

The first correspondence area 123a stores information indicating that the general winning opening 31 is the general winning opening 31, as information for the management CPU 112 to identify the type of signal input to the first buffer 122a. The first correspondence area 123a also stores information indicating that the general winning opening 31 is the general winning opening 31, as well as information on the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31. The second correspondence area 123b stores information indicating that the general winning opening 31 is the general winning opening 31, as information for the management CPU 112 to identify the type of signal input to the second buffer 122b. The second correspondence area 123b also stores information indicating that the general winning opening 31 is the general winning opening 31, as well as information on the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31. The third correspondence area 123c stores information indicating that the input signal to the third buffer 122c is the general winning opening 31, as information for the management CPU 112 to identify the type of signal input to the third buffer 122c. In addition to the information indicating that the input signal is the general winning opening 31, the third correspondence area 123c also stores information on the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31.

The fourth correspondence area 123d stores information indicating that the signal input to the fourth buffer 122d is the special electric winning device 32, as information for the management CPU 112 to identify the type of signal. The fourth correspondence area 123d also stores information indicating that the signal is the special electric winning device 32, as well as information on the number of game balls (15) that will be paid out when one game ball enters the special electric winning device 32. The fifth correspondence area 123e stores information indicating that the signal is the first operating port 33, as information for the management CPU 112 to identify the type of signal input to the fifth buffer 122e. The fifth correspondence area 123e also stores information indicating that the signal is the first operating port 33, as well as information on the number of game balls (1) that will be paid out when one game ball enters the first operating port 33. The sixth correspondence area 123f stores information indicating that the second actuation port 34 is the one that is used by the management CPU 112 to identify the type of signal input to the sixth buffer 122f. The sixth correspondence area 123f also stores information indicating that the second actuation port 34 is the one, as well as information indicating the number of game balls (one) that will be paid out when one game ball enters the second actuation port 34. The seventh correspondence area 123g stores information indicating that the outlet 24a is the one that is used by the management CPU 112 to identify the type of signal input to the seventh buffer 122g.

The eighth correspondence area 123h stores information indicating that the mode is the open/close execution mode, as information for the management CPU 112 to identify the type of signal input to the eighth buffer 122h. The ninth correspondence area 123i stores information indicating that the mode is the high frequency support mode, as information for the management CPU 112 to identify the type of signal input to the ninth buffer 122i. The tenth correspondence area 123j stores information indicating that the front door frame 14 is the information for the management CPU 112 to identify the type of signal input to the tenth buffer 122j. The eleventh correspondence area 123k stores information indicating that a game round has started, as information for the management CPU 112 to identify the type of signal input to the eleventh buffer 122k.

The twelfth correspondence area 123l stores information indicating that it is blank and does not correspond to any of the types of signals input to the twelfth buffer 122l, as information for the management CPU 112 to identify the type of signal input to the twelfth buffer 122l. The thirteenth correspondence area 123m stores information indicating that it is blank and does not correspond to any of the types of signals input to the thirteenth buffer 122m, as information for the management CPU 112 to identify the type of signal input to the fourteenth buffer 122n. The fourteenth correspondence area 123n stores information indicating that it is blank and does not correspond to any of the types of signals input to the fourteenth buffer 122n, as information for the management CPU 112 to identify the type of signal input to the fourteenth buffer 122n.

As described above, the type of signal to be input to the first through fourteenth buffers 122a through 122n is determined by the management CPU 112 upon receiving instructions from the main CPU 63, making it possible for the management IC 66 to be used in models other than this pachinko machine 10. This makes it possible to increase the versatility of the management IC 66.

In addition, instead of outputting information for recognizing the type of signal each time a signal corresponding to the storage of history information is output to the first to fourteenth buffers 122a to 122n, information for recognizing the type of signal is output in advance, and information for identifying the type of signal input to the first to fourteenth buffers 122a to 122n by the management CPU 112 based on the output information is stored in the correspondence memory 116. This makes it possible to reduce the amount of information output from the main CPU 63 to the management CPU 112 each time a signal is output, compared to a configuration in which information for recognizing the type of signal is output each time a signal corresponding to the storage of history information is output to the first to fourteenth buffers 122a to 122n.

In addition, the information for the management CPU 112 to identify the type of signal input to the first through fourteenth buffers 122a through 122n is output when the supply of operating power begins. This allows the management CPU 112 to identify the type of signal input to the first through fourteenth buffers 122a through 122n when play begins on this pachinko machine 10.

In addition, the information that a setting value update signal is input to the 15th buffer 122o and the information that an output instruction signal is input to the 16th buffer 122p are set during the design stage of the management IC 66. This makes it possible to omit the process for identifying the type of signal input to the 15th buffer 122o and the 16th buffer 122p for the setting value update signal and output instruction signal that are reliably used not only in this pachinko machine 10 but also in other models of pachinko machines that use the management IC 66. This makes it possible to reduce the processing load of the process for identifying the type of such signal.

Next, we will explain the history memory 117 of the management IC 66. Figure 21 is an explanatory diagram for explaining the configuration of the history memory 117.

The history memory 117 is provided with a history area 124 for sequentially storing history information. In the history area 124, multiple pieces of pointer information are set in consecutive numbers, and a history information storage area 125 is set in one-to-one correspondence with each piece of pointer information. The history information storage area 125 can store a combination of RTC information and correspondence information. In this case, each history information storage area 125 has a data capacity of 2 bytes, and 1 byte of data capacity is assigned as an area for storing RTC information, and 1 byte of data capacity is assigned as an area for storing correspondence information. When it becomes necessary to store correspondence information according to a signal input to the first to fourteenth buffers 122a to 122n (actually the first to eleventh buffers 122a to 122k in the case of this pachinko machine 10), the date and time information measured in the current RTC 115 is first stored in the area for storing RTC information in the history information storage area 125 corresponding to the pointer information currently being written. After that, the correspondence information corresponding to the buffer 122a-122n that triggered the current information storage is read from the correspondence area 123a-123n corresponding to the buffer 122a-122n in the correspondence memory 116, and the read correspondence information is stored in an area for storing correspondence information in the history information storage area 125 that corresponds to the pointer information currently being written.

Specifically, the correspondence information stored in the history information storage area 125 is stored in the first to seventh buffers 122a to 122g, as already explained, because signals corresponding to the detection results of the ball entry detection sensors 42a to 48a are input to the first to seventh correspondence areas 123a to 123g in the correspondence memory 116. More specifically, information corresponding to the type of ball entry section corresponding to each of the ball entry detection sensors 42a to 48a is stored in the first to seventh correspondence areas 123a to 123g. As already explained, in this pachinko machine 10, the first to third winning hole detection sensors 42a to 44a all detect game balls that have entered the general winning hole 31, so the first to third correspondence areas 123a to 123c corresponding to these first to third winning hole detection sensors 42a to 44a all store information indicating that it is the general winning hole 31. In addition, the fourth correspondence area 123d stores information indicating that it is the special electric winning device 32, the fifth correspondence area 123e stores information indicating that it is the first operating port 33, the sixth correspondence area 123f stores information indicating that it is the second operating port 34, and the seventh correspondence area 123g stores information indicating that it is the outlet 24a. If the buffer 122a-122n that triggered the current information storage is any of the first to seventh buffers 122a-122g, information on the type of ball entry part corresponding to that buffer 122a-122g is read from any of the first to seventh correspondence areas 123a-123g, and the read information on the type of ball entry part is stored as is in the area for storing correspondence information in the history information storage area 125.

Meanwhile, the eighth buffer 122h receives a signal indicating whether or not it is in the open/close execution mode, the ninth buffer 122i receives a signal indicating whether or not it is in the high frequency support mode, the tenth buffer 122j receives a signal indicating whether or not the front door frame 14 is open, and the eleventh buffer 122k receives a signal indicating whether or not a game round has started. Therefore, the eighth correspondence area 123h stores information indicating the open/close execution mode, the ninth correspondence area 123i stores information indicating the high frequency support mode, the tenth correspondence area 123j stores information indicating the front door frame 14, and the eleventh correspondence area 123k stores information indicating a game round.

As already explained, the main CPU 63 continues to output the 8th signal at a LOW level when the open/close execution mode is not in effect, and continues to output the 8th signal at a HI level when the open/close execution mode is in effect. Therefore, the management CPU 112 can determine that the open/close execution mode has started when the 8th signal changes from a LOW level to a HI level, and that the open/close execution mode has ended when the 8th signal changes from a HI level to a LOW level. In addition, in both cases where the 8th signal changes from a LOW level to a HI level, and where the 8th signal changes from a HI level to a LOW level, the management CPU 112 determines that an opportunity to store the correspondence information in the history information storage area 125 has occurred. In other words, when the 8th signal changes from a LOW level to a HI level, not only the information indicating the open/close execution mode read from the 8th correspondence area 123h but also the start information are stored in the area for storing the correspondence information in the history information storage area 125. In addition, when the eighth signal changes from a high level to a low level, not only the information indicating the opening/closing execution mode read from the eighth correspondence area 123h but also the end information are stored in an area for storing correspondence information in the history information storage area 125.

As already explained, the main CPU 63 continues to output the ninth signal at a LOW level when the high-frequency support mode is not in effect, and continues to output the ninth signal at a HI level when the high-frequency support mode is in effect. Therefore, the management CPU 112 can determine that the high-frequency support mode has started when the ninth signal changes from a LOW level to a HI level, and that the high-frequency support mode has ended when the ninth signal changes from a HI level to a LOW level. In either case of the ninth signal changing from a LOW level to a HI level, or the HI level to a LOW level, the management CPU 112 determines that an opportunity to store the correspondence information in the history information storage area 125 has occurred. In other words, when the ninth signal changes from a LOW level to a HI level, not only the information indicating the high-frequency support mode read from the ninth correspondence area 123i but also the start information are stored in the area for storing the correspondence information in the history information storage area 125. In addition, when the ninth signal changes from a high level to a low level, not only the information indicating the high frequency support mode read from the ninth correspondence area 123i but also the end information are stored in an area for storing correspondence information in the history information storage area 125.

As already explained, the main CPU 63 continuously outputs a LOW level tenth signal when the front door frame 14 is closed, and continuously outputs a HIGH level tenth signal when the front door frame 14 is open, so that the management CPU 112 can determine that the front door frame 14 is open when the tenth signal changes from a LOW level to a HIGH level, and can determine that the front door frame 14 is closed when the tenth signal changes from a HIGH level to a LOW level. In either case of a change from a LOW level to a HIGH level or a change from a HIGH level to a LOW level, the management CPU 112 determines that an opportunity to store the correspondence information in the history information storage area 125 has occurred. In other words, when the 10th signal changes from a LOW level to a HI level, not only the information indicating that it is the front door frame 14 read from the 10th correspondence area 123j but also the opening start information are stored in the area for storing correspondence information in the history information storage area 125. Also, when the 10th signal changes from a HI level to a LOW level, not only the information indicating that it is the front door frame 14 read from the 10th correspondence area 123j but also the opening end information are stored in the area for storing correspondence information in the history information storage area 125.

As already explained, the master CPU 63 continues to output a LOW level 11th signal until the timing for starting a game round arrives, and when the timing for starting a game round arrives, outputs a HIGH level 11th signal for a specific period of time. Therefore, the management CPU 112 determines that a game round has started when the 11th signal changes from a LOW level to a HIGH level. In other words, when the 11th signal changes from a LOW level to a HIGH level, information indicating that this is the game round read from the 11th correspondence area 123k is stored in an area for storing correspondence information in the history information storage area 125.

The history information storage area 125 is provided for a sufficient number of times to store all the history information generated during ten consecutive business days during which the pachinko machine 10 continues to fire game balls from opening to closing. For example, if history information is generated 60,000 times a day, more than 600,000 history information storage areas 125 are provided. This makes it possible to store and hold all history information in the history memory 117 for at least ten days.

The history memory 117 is provided with a pointer area 126 in addition to the history area 124. The pointer area 126 stores information for the management CPU 112 to identify the pointer information currently being written in the history memory 117. Specifically, at the time of shipping the pachinko machine 10, information is set in the pointer area 126 specifying pointer information of "0" as the writing target. Then, every time a piece of history information is newly stored in the history information storage area 125, the information in the pointer area 126 is updated so that the value of the pointer information to be written is incremented by 1. When the last pointer information is the writing target and history information is stored in the history information storage area 125 corresponding to the last pointer information, the information in the pointer area 126 is updated so that the pointer information of "0" is the writing target. As a result, when a storage trigger occurs that exceeds the number of history information that can be stored, the history information is overwritten with new history information in order starting from the history information storage area 125 in which the oldest history information is stored.

In addition, when an external device reads history information from the history memory 117, the history information storage area 125 is cleared to all "0"s, and the information in the pointer area 126 is updated so that pointer information of "0" becomes the write target. This makes it possible to prevent history information that has once been read from becoming the target for reading again.

Next, a specific processing configuration for managing game history using the management IC 66 will be described. First, a processing configuration for storing information on the correspondence between the first to fourteenth buffers 122a to 122n provided in the input port 121 of the management side I/F 111 and the signal type in the correspondence memory 116 will be described. Figure 22 is a flowchart showing the recognition processing executed by the main CPU 63. Note that the recognition processing is executed in step S111 in the main processing (Figure 9).

First, the recognition output counter provided in the main RAM 65 is set to "14" (step S801). The recognition output counter is a counter that allows the main CPU 63 to determine the remaining number of times information output is required to make the management CPU 112 recognize which type of signal the first to fourteenth buffers 122a to 122n of the input port 121 in the management I/F 111 correspond to. As already explained, the first to fourteenth buffers 122a to 122n are the 14 buffers that are the targets for signal type recognition, so the recognition output counter is set to "14".

Then, the output process of the identification start command is executed (step S802). The main CPU 63 outputs various commands to the management CPU 112 to make the management CPU 112 recognize which type of signal the first to fourteenth buffers 122a to 122n correspond to. When outputting this command, the first to eighth signals input to the first to eighth buffers 122a to 122h are used. In other words, the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h) used to instruct the management CPU 112 to store history information are used to output a command to make the management CPU 112 recognize which type of signal the first to fourteenth buffers 122a to 122n correspond to. This makes it possible to reduce the number of signal paths and simplify the configuration compared to a configuration in which the signal path for outputting the command is provided separately from the signal paths 118a to 118p for outputting signals to the first to sixteenth buffers 122a to 122p. The identification start command has a data capacity of 8 bits, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. In addition, in the output process of the identification start command, the output state of the ninth signal is switched to HI level at the timing when the output of the identification start command is started so that the management CPU 112 recognizes that a new command has been sent. In addition, the output period of the identification start command and the period during which the output state of the ninth signal is maintained at HI level are set to a period sufficient for the management CPU 112 to recognize the identification start command and the output state of the ninth signal. By receiving the identification start command, the management CPU 112 specifies that a process should be started to store information on the correspondence between the first to fourteenth buffers 122a to 122n and the signal types in the correspondence memory 116.

Then, a type identification command corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64 (step S803). In this case, the first buffer 122a is the first to be set as the signal type, and then the n+1 buffer is set as the signal type after the n buffer, so that the signal type recognition setting corresponding to the first to fourteenth buffers 122a to 122n is performed. Therefore, if the recognition output counter is "14" to "12", a type identification command indicating that it is the general winning port 31 and the number of prize balls is read, if the recognition output counter is "11", a type identification command indicating that it is the special winning device 32 and the number of prize balls is read, if the recognition output counter is "10", a type identification command indicating that it is the first operating port 33 and the number of prize balls is read, if the recognition output counter is "9", a type identification command indicating that it is the second operating port 34 and the number of prize balls is read, if the recognition output counter is "8", an out port 2 is set as the signal type recognition setting. If the recognition output counter is "7", it reads a type identification command indicating that it is in the open/close execution mode; if the recognition output counter is "6", it reads a type identification command indicating that it is in the high frequency support mode; if the recognition output counter is "5", it reads a type identification command indicating that it is the front door frame 14; if the recognition output counter is "4", it reads a type identification command indicating that it is a play count; if the recognition output counter is "3" to "1", it reads a type identification command indicating that it is blank.

Then, the output process of the read type identification command is executed (step S804). The type identification command has a data capacity of 8 bits, like the identification start command, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. In addition, in the output process of the identification type command, the output state of the ninth signal is switched to HI level at the timing when the output of the identification type command is started so that the management CPU 112 recognizes that a new command has been sent. In addition, the output period of the identification type command and the period during which the output state of the ninth signal is maintained at HI level are set to a period sufficient for the management CPU 112 to recognize the output state of these identification type command and the ninth signal. By receiving the identification type command, the management CPU 112 stores information corresponding to the identification type command in the correspondence area 123a to 123n corresponding to the buffer that is the current setting target among the first to fourteenth buffers 122a to 122n.

Then, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S805), and it is determined whether the value of the recognition output counter after the decrement is "0" (step S806). If the value of the recognition output counter is 1 or more (step S806: NO), processing is executed to output a type identification command corresponding to the value of the recognition output counter after the decrement (steps S803 and S804).

On the other hand, if the value of the recognition output counter is "0" (step S806: YES), output processing of the recognition end command is executed (step S807). The recognition end command has a data capacity of 8 bits, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. In addition, in the recognition end command output processing, the output state of the ninth signal is switched to HI level at the timing when the recognition end command output is started in order to make the management side CPU 112 recognize that a new command has been sent. In addition, the output period of the recognition end command and the period during which the output state of the ninth signal is maintained at HI level are set to a period sufficient for the management side CPU 112 to recognize the recognition end command and the output state of the ninth signal. By receiving the recognition end command, the management side CPU 112 determines that the process for storing the information on the correspondence between the first to fourteenth buffers 122a to 122n and the signal type in the correspondence memory 116 has been completed.

Next, the management process executed by the management CPU 112 will be described with reference to the flowchart in FIG. 23. The management process is started when the supply of operating power to the management CPU 112 is started. The processing speed of the management CPU 112 is configured to be faster than the processing speed of the main CPU 63, and the combination of processes from step S908 onwards in the management process is executed 16 or more times from the start of one timer interrupt process (FIG. 11) in the main CPU 63 until the start of the next timer interrupt process (FIG. 11).

First, it is determined whether or not an identification start command has been received from the main CPU 63 (step S901). If an identification start command has not been received (step S901: NO), a setting update recognition process is executed (step S902), and then the process returns to step S901. In the setting update recognition process, which will be described in detail later, when a new setting is made to the setting status of the pachinko machine 10 by the main CPU 63, a process corresponding to the new setting is executed.

When an identification start command is received from the main CPU 63 (step S901: YES), the value of the setting target counter provided in the management RAM 114 is cleared to "0" (step S903). The setting target counter is a counter that allows the management CPU 112 to identify the type of buffer 122a to 122n for which the signal type is to be set. The first buffer 122a is the first to be set as the signal type, and thereafter the nth buffer and then the n+1th buffer are set as the signal type.

After that, on the condition that a type identification command has been received from the main CPU 63 (step S904: YES), a correspondence setting process is executed (step S905). In the correspondence setting process, information on the signal type set in the currently received type identification command is stored in the correspondence area corresponding to the current value of the setting target counter in the management RAM 114, among the first to fourteenth correspondence areas 123a to 123n of the correspondence memory 116. Then, the value of the setting target counter in the management RAM 114 is incremented by 1 (step S906).

If a negative judgment is made in step S904, or if the processing of step S906 is executed, it is judged whether or not an identification end command has been received from the main CPU 63 (step S907). If an identification end command has not been received (step S907: NO), the process returns to step S904, and the processing of steps S905 and S906 is executed again on the condition that a new type identification command is received from the main CPU 63 (step S904: YES).

If an identification end command has been received from the main CPU 63 (step S907: YES), the processes of steps S908 to S910 are repeatedly executed. In step S908, details will be described later, a history setting process is executed to store history information corresponding to the type of signal received from the main CPU 63 in the history memory 117. In step S909, details will be described later, various parameters are calculated using the history information stored in the history memory 117, and a display output process is executed to notify the first to third notification display devices 69a to 69c of the calculation results. In step S910, details will be described later, an external output process is executed to output the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131 to the reading terminal 68d.

Figure 24 is a time chart showing how information on the correspondence between the first to fourteenth buffers 122a to 122n and the types of signals input to these buffers 122a to 122n is stored in the correspondence memory 116. Figure 24(a) shows the period during which commands are output from the main CPU 63 to the management CPU 112 using the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h), Figure 24(b) shows the period during which the output state of the ninth signal is at HI level, Figure 24(c) shows the execution period of the identification state during which processing is executed to identify the correspondence between the first to fourteenth buffers 122a to 122n and the types of signals input to these buffers 122a to 122n, and Figure 24(d) shows the timing at which the correspondence setting process (step S905) is executed by the management CPU 112.

When the supply of operating power to the main CPU 63 and the management CPU 112 is started, the output of the identification start command using the first to eighth signals is started at the timing of t1 as shown in FIG. 24(a). Also, at the timing of t1, the output state of the ninth signal is changed from LOW level to HI level as shown in FIG. 24(b). Then, at the timing of t2, when the output of the identification start command is continuing, the output state of the ninth signal is changed from HI level to LOW level as shown in FIG. 24(b). The management CPU 112 identifies that a command has been sent from the main CPU 63 by confirming that the output state of the ninth signal has been changed from HI level to LOW level, and grasps the contents of the command received from the main CPU 63 by confirming the information of the first to eighth buffers 122a to 122h. In this case, since the identification start command has been received, the management CPU 112 enters the identification state by making a positive determination at step S901 of the management process (FIG. 23). After that, at timing t3, the output of the identification start command is stopped as shown in FIG. 24(a).

After that, at the timing of t4, the output of the first type identification command using the first to eighth signals is started as shown in FIG. 24(a). Also, at the timing of t4, the output state of the ninth signal is changed from LOW level to HI level as shown in FIG. 24(b). After that, at the timing of t5, when the output of the type identification command is continuing, the output state of the ninth signal is changed from HI level to LOW level as shown in FIG. 24(b). The control side CPU 112 identifies that a command has been sent from the main side CPU 63 by confirming that the output state of the ninth signal has been changed from HI level to LOW level, and grasps the contents of the command received from the main side CPU 63 by confirming the information of the first to eighth buffers 122a to 122h. In this case, since the first type identification command has been received, the control side CPU 112 executes the correspondence setting process as shown in FIG. 24(d) at the timing of t5. In this correspondence setting process, information indicating that it is a general winning port 31 and information on the number of winning balls are stored in the first correspondence area 123a of the correspondence memory 116. After that, at timing t6, the output of the type identification command is stopped as shown in FIG. 24(a).

After that, from t7 to t9, from t10 to t12, from t13 to t15, and from t16 to t18, the management CPU 112 executes the correspondence setting process corresponding to the type identification command output from the master CPU 63, similar to the process from t4 to t6. In this case, the correspondence setting process corresponding to the 14th type identification command is completed from t16 to t18.

After that, at the timing of t19, the output of the identification end command using the first to eighth signals is started as shown in FIG. 24(a). Also, at the timing of t19, the output state of the ninth signal is changed from LOW level to HI level as shown in FIG. 24(b). After that, at the timing of t20, when the output of the identification end command is continuing, the output state of the ninth signal is changed from HI level to LOW level as shown in FIG. 24(b). The management side CPU 112 identifies that a command has been sent from the main side CPU 63 by confirming that the output state of the ninth signal has been changed from HI level to LOW level, and grasps the contents of the command received from the main side CPU 63 by confirming the information of the first to eighth buffers 122a to 122h. In this case, since the identification end command has been received, the identification state of the management side CPU 112 ends at the timing of t20 as shown in FIG. 24(c). After that, the output of the identification end command is stopped at the timing of t21 as shown in FIG. 24(a).

As described above, the configuration allows the management CPU 112 to recognize whether or not a command is being output using the 9th signal, so that the management CPU 112 can clearly recognize that a command is being output even in a configuration in which the command is output using the 1st to 8th signals (i.e., the 1st to 8th signal paths) that are used to instruct the management CPU 112 on the timing to store history information.

Next, the process configuration for storing history information in the history memory 117 will be described. Figure 25 is a flowchart showing the management output process executed by the main CPU 63. Note that the management output process is executed in step S319 in the timer interrupt process (Figure 11).

First, the managed object counter provided in the main RAM 65 is set to "11" (step S1001). The managed object counter is a counter for the main CPU 63 to determine whether there is a managed object that has not been specified as a target for whether or not the signal output state to the management CPU 112 should be changed in the current management output process, and for which managed object the signal output state to the management CPU 112 should be changed. In one management output process, the managed objects for which the main CPU 63 specifies whether or not the signal output state to the management CPU 112 should be changed are the seven ball entry detection sensors 42a to 48a, whether or not the opening and closing execution mode is being executed, whether or not the high frequency support mode is being executed, whether or not the front door frame 14 is being opened and closed, and whether or not a game round has started, for a total of 11 objects. Therefore, the managed object counter is initially set to "11".

Then, it is determined whether the signal output state to the management CPU 112 for the managed object corresponding to the current value of the managed object counter is at HI level (step S1002). If it is not at HI level (step S1002: NO), it is determined whether the value of the managed object counter is 5 or more, thereby identifying which of the seven ball entry detection sensors 42a to 48a is the managed object corresponding to the value of the managed object counter (step S1003).

If a positive judgment is made in step S1003, it is judged whether or not the output flag of the main RAM 65 corresponding to the value of the managed counter is set to "1" (step S1004). Specifically, if the value of the managed counter is "11" and corresponds to the first winning port detection sensor 42a, it is judged whether or not the first output flag is set to "1", if the value of the managed counter is "10" and corresponds to the second winning port detection sensor 43a, it is judged whether or not the second output flag is set to "1", if the value of the managed counter is "9" and corresponds to the third winning port detection sensor 44a, it is judged whether or not the third output flag is set to "1", if the value of the managed counter is "8" and corresponds to the special power detection sensor 45a, it is judged whether or not the third ... special power detection sensor 45a, it is judged whether or not the third output flag is set to "1", if the value of the managed counter is "9" and corresponds to the special power detection sensor 45a, it is judged whether or not the third output flag is set to "1", if the value of the managed counter is "9" and corresponds to the special power detection sensor 45a, it is judged whether or not the third output flag is set to "1", if the value of the managed counter is "9" and corresponds to the special power detection sensor 45a, it is judged whether or not the third output flag is set to "1", if the value of the managed counter is "9" and corresponds to the special power detection sensor 45a, it is judged whether or not the third output flag is set to "1 a, it determines whether the fourth output flag is set to "1"; if the value of the managed counter is "7" and corresponds to the first actuation port detection sensor 46a, it determines whether the fifth output flag is set to "1"; if the value of the managed counter is "6" and corresponds to the second actuation port detection sensor 47a, it determines whether the sixth output flag is set to "1"; if the value of the managed counter is "5" and corresponds to the out port 24a, it determines whether the seventh output flag is set to "1". As already explained, these first to seventh output flags are set to "1" in the ball entry detection process (Figure 15).

If the output flag corresponding to the value of the managed counter is set to "1" (step S1004: YES), the output state of the signal corresponding to the value of the managed counter among the first to seventh signals is set to HI level (step S1005). After that, the output flag corresponding to the value of the managed counter is cleared to "0" (step S1006).

If a negative judgment is made in step S1003, it is determined whether or not an opportunity to switch the output state of the signal corresponding to the value of the managed counter to a HI level has occurred (step S1007). Specifically, if the value of the managed counter is "4", it is determined whether or not a transition to the open/close execution mode has occurred; if the value of the managed counter is "3", it is determined whether or not a transition to the high frequency support mode has occurred; if the value of the managed counter is "2", it is determined whether or not the front door frame 14 has been opened; if the value of the managed counter is "1", it is determined whether or not the eleventh output flag is set to "1" to determine whether or not a game round has started. If a positive judgment is made in step S1007, the output state of the signal corresponding to the value of the managed counter is set to a HI level (step S1008). Note that, if the processing of step S1008 is executed when the value of the managed counter is "1", the eleventh output flag is cleared to "0".

If a positive judgment is made in step S1002, it is judged whether or not an opportunity to switch the output state of the signal corresponding to the value of the managed counter to a LOW level has occurred (step S1009). Specifically, if the value of the managed counter is 5 or more or "1" and the current managed object is any of the ball entry detection sensors 42a-48a or the start of a game round, it is judged whether or not a HI output duration (specifically, 10 milliseconds) has elapsed since the output state of the signal corresponding to the value of the managed counter among the first to seventh signals and the eleventh signal was switched from a LOW level to a HI level. This HI output duration is set in the management side CPU 112 to a period longer than the longest processing interval of the history setting process (step S908) of the management process (FIG. 23), and is a period during which the management side CPU 112 can reliably identify the output state of the signal that has switched from a LOW level to a HI level. In addition, if the value of the managed counter is "4" and the current managed object is in the open/close execution mode, it is determined whether the open/close execution mode has ended; if the value of the managed counter is "3" and the current managed object is in the high frequency support mode, it is determined whether the high frequency support mode has ended; and if the value of the managed counter is "2" and the current managed object is the front door frame 14, it is determined whether the front door frame 14 is in the closed state. If an opportunity to switch the output state of the signal corresponding to the value of the managed counter to a LOW level has occurred (step S1009: YES), the output state of the signal corresponding to the value of the managed counter is set to a LOW level (step S1010).

If a negative judgment is made in step S1004, if the processing of step S1006 is executed, if a negative judgment is made in step S1007, if the processing of step S1008 is executed, if a negative judgment is made in step S1009, or if the processing of step S1010 is executed, the value of the managed object counter in the main RAM 65 is decremented by 1 (step S1011). Then, it is determined whether the value of the managed object counter after the decrement is "0" (step S1012). If the value of the managed object counter is 1 or greater (step S1012: NO), the processing from step S1002 onwards is executed for the managed object corresponding to the new managed object counter value.

Next, the history setting process executed by the management CPU 112 will be described with reference to the flowchart in FIG. 26. The history setting process is executed in step S908 of the management process (FIG. 23).

First, the number of buffers to be checked by the management CPU 112 among the first to fourteenth buffers 122a to 122n is set in a check target counter provided in the management RAM 114 (step S1101). Specifically, the number of correspondence areas in the correspondence memory 116 among the first to fourteenth correspondence areas 123a to 123n that store information other than information indicating that they are blank is identified, and the information of the identified number is set in the check target counter. As already explained, in this pachinko machine 10, information other than information indicating that they are blank is stored in the first to eleventh correspondence areas 123a to 123k, so in step S1101 the check target counter is set to "11".

Then, by checking whether the numerical information stored in the buffer corresponding to the current value of the counter to be checked among the first to fourteenth buffers 122a to 122n has changed from "0" to "1", it is determined whether the output state of the input signal from the main CPU 63 to that buffer has been switched from LOW level to HIGH level (step S1102). Note that when the value of the counter to be checked is "n", the nth buffers 122a to 122n are the targets for checking the numerical information. For example, if the value of the counter to be checked is "11", the eleventh buffer 122k is the target for checking the numerical information, and if the value of the counter to be checked is "5", the fifth buffer 122e is the target for checking the numerical information.

If the determination in step S1102 is affirmative, RTC information, which is date information and time information, is read from the RTC 115 (step S1103). Then, a write process to the history memory 117 is executed (step S1104). In the write process, the pointer information in the history area 124 that is the current write target is identified by referring to the pointer area 126 of the history memory 117, and the RTC information read in step S1103 is written to the history information storage area 125 of the history area 124 that corresponds to the pointer information that is the write target. In addition, correspondence information is read from the correspondence areas 123a to 123n that correspond to the current value of the counter to be confirmed, and the correspondence information is written to the history information storage area 125 that corresponds to the pointer information that is the write target. Furthermore, if the correspondence information is any of information indicating an open/close execution mode, information indicating a high frequency support mode, and information indicating a front door frame 14, not only the correspondence information but also start information is written to the history information storage area 125 corresponding to the pointer information to be written. Note that if the value of the counter to be checked is "n", the nth correspondence area 123a to 123n is the object to read the correspondence information. For example, if the value of the counter to be checked is "11", the eleventh correspondence area 123k is the object to read the correspondence information, and if the value of the counter to be checked is "5", the fifth correspondence area 123e is the object to read the correspondence information.

By executing the writing process as described above, when the value of the counter to be checked is any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the number of times played, the combination of the RTC information and the correspondence relationship information indicating that it is any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the number of times played is stored as history information in the history information storage area 125 corresponding to the pointer information to be written. Also, when the value of the counter to be checked is any of the opening and closing execution mode, the high frequency support mode, and the front door frame 14, the combination of the RTC information, the correspondence relationship information indicating that it is any of the opening and closing execution mode, the high frequency support mode, and the front door frame 14, and the start information is stored as history information in the history information storage area 125 corresponding to the pointer information to be written.

After that, the target pointer is updated (step S1105). In this update, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by one. It is determined whether the pointer information after the increment of one has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after the increment of one is overwritten in the pointer area 126 as the new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

If a negative judgment is made in step S1102, or if the processing of step S1105 is executed, it is judged whether or not the correspondence information for checking whether the signal output has been switched to a LOW level is stored in the correspondence area 123a to 123n corresponding to the current value of the counter to be checked (step S1106). Specifically, if the current value of the counter to be checked is "8" to "10", the corresponding correspondence area 123h to 123j stores any one of information indicating the opening/closing execution mode, information indicating the high frequency support mode, and information indicating the front door frame 14, so a positive judgment is made in step S1106.

If the determination in step S1106 is affirmative, it is determined whether the output state of the input signal from the main CPU 63 to the buffer corresponding to the current counter value among the first to fourteenth buffers 122a to 122n has been changed from "1" to "0" (step S1107). If the determination in step S1107 is affirmative, the RTC information is read as in step S1103 (step S1108), and a write process to the history memory 117 is executed (step S1109). In the write process, the RTC information read in step S1108 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information to be written. In addition, the correspondence information is read from the correspondence areas 123a to 123n corresponding to the current counter value to be checked, and the correspondence information is written to the history information storage area 125 corresponding to the pointer information to be written. In addition, not only the correspondence information but also the end information is written to the history information storage area 125 corresponding to the pointer information to be written. By executing the writing process in this manner, when the value of the counter to be checked is either the open/close execution mode, the high frequency support mode, or the front door frame 14, a combination of the RTC information, the correspondence information indicating either the open/close execution mode, the high frequency support mode, or the front door frame 14, and the end information is stored as history information in the history information storage area 125 corresponding to the pointer information to be written. Thereafter, the target pointer update process is executed in the same manner as in step S1105 (step S1110).

If a negative judgment is made in step S1106, if a negative judgment is made in step S1107, or if the processing of step S1110 is executed, the value of the confirmation target counter in the management RAM 114 is decremented by 1 (step S1111). Then, it is determined whether the value of the confirmation target counter after the decrement is "0" (step S1112). If the value of the confirmation target counter is 1 or greater (step S1112: NO), the processing from step S1102 onwards is executed for the confirmation target corresponding to the new confirmation target counter value.

Next, the manner in which history information is stored in the history memory 117 will be described with reference to the time chart in Figure 27. Figure 27(a) shows the period during which a HIGH level signal is input to any of the first to seventh and eleventh buffers 122a to 122g, 122k, Figure 27(b) shows the period during which a HIGH level signal is input to the eighth buffer 122h, Figure 27(c) shows the period during which a HIGH level signal is input to the ninth buffer 122i, Figure 27(d) shows the period during which a HIGH level signal is input to the tenth buffer 122j, and Figure 27(e) shows the timing of writing history information to the history memory 117.

At the timing of t1, the output state of the signal input to any one of the first to seventh and eleventh buffers 122a to 122g, 122k is switched from LOW to HIGH as shown in FIG. 27(a). Therefore, at the timing of t1, history information is written to the history memory 117 as shown in FIG. 27(e). After that, at the timing of t2, the signal that was switched to HIGH at the timing of t1 is switched to LOW as shown in FIG. 27(a). However, since the signal is input to any one of the first to seventh and eleventh buffers 122a to 122g, 122k and the switching to LOW is not a target for storing history information, writing of history information is not executed at the timing of t2 as shown in FIG. 27(e).

After that, at times t3, t5, t6, t9, t10, t13, and t14, the output state of the signal input to any of the first to seventh and eleventh buffers 122a to 122g, 122k is switched from LOW level to HIGH level, as shown in FIG. 27(a). Therefore, at each of these times, history information is written, as shown in FIG. 27(e).

As shown in FIG. 27(b), the output state of the signal input to the eighth buffer 122h is at HI level from t4 to t7. This eighth buffer 122h corresponds to the occurrence or non-occurrence of the open/close execution mode. Therefore, as shown in FIG. 27(e), history information is written at t4, when the output state of the signal input to the eighth buffer 122h switches to HI level, and at t7, when the output state of the signal switches to LOW level. In this case, the history information written at t4 includes start information, and the history information written at t7 includes end information. This makes it possible to ascertain the execution period of the open/close execution mode by checking the history information in the history memory 117.

In addition, the history information is written in chronological order to the history memory 117. Therefore, it is possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the opening and closing execution mode. In addition, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the opening and closing execution mode by comparing the RTC information.

As shown in FIG. 27(c), the output state of the signal input to the ninth buffer 122i is at HI level from t8 to t11. This ninth buffer 122i corresponds to the occurrence or nonoccurrence of the high-frequency support mode. Therefore, as shown in FIG. 27(e), history information is written at t8, when the output state of the signal input to the ninth buffer 122i switches to HI level, and at t11, when the output state of the signal switches to LOW level. In this case, the history information written at t8 includes start information, and the history information written at t11 includes end information. This makes it possible to ascertain the execution period of the high-frequency support mode by checking the history information in the history memory 117.

In addition, the history information is written in chronological order to the history memory 117. Therefore, it is possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is from the high-frequency support mode. In addition, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is from the high-frequency support mode by comparing the RTC information.

As shown in FIG. 27(d), the output state of the signal input to the tenth buffer 122j is at HI level from t12 to t15. This tenth buffer 122j corresponds to whether the front door frame 14 is open or not. Therefore, as shown in FIG. 27(e), history information is written at t12, when the output state of the signal input to the tenth buffer 122j switches to HI level, and at t15, when the output state of the signal switches to LOW level. In this case, the history information written at t12 includes start information, and the history information written at t15 includes end information. This makes it possible to know the period during which the front door frame 14 is open by checking the history information in the history memory 117.

In addition, the history information is written in chronological order to the history memory 117. Therefore, it is possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 was recorded while the front door frame 14 was open. In addition, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 was recorded while the front door frame 14 was open by comparing the RTC information.

Next, we will explain the output process of the setting value update signal that is executed when the setting state of the pachinko machine 10 is set by the main CPU 63. Figure 28 is a flowchart showing the output process of the setting value update signal that is executed by the main CPU 63. Note that the output process of the setting value update signal is executed in step S119 in the main processing (Figure 9).

A value corresponding to the currently set value of the pachinko machine 10 is set in the pulse number counter provided in the main RAM 65 (step S1201). Specifically, the value of the setting value counter in the main RAM 65 is set in the pulse number counter. Then, it is determined whether the setting value update signal directed to the management CPU 112 is at HI level (step S1202). As already explained, the setting value update signal is input to the 15th buffer 122o of the input port 121 in the management IC 66. Here, the output process of the setting value update signal is executed at a timing prior to the recognition process, which is a process for making the management CPU 112 identify the type of signal input to the 1st to 14th buffers 122a to 122n of the input port 121 in the main process (FIG. 9). In contrast, since the setting value update signal is set in the management IC 66 during the design stage of the pachinko machine 10 to be input to the 15th buffer 122o, even if the setting value update signal output process is executed before the recognition process, it is possible for the management CPU 112 to identify that the signal input to the 15th buffer 122o is a setting value update signal.

If the result of step S1202 is negative, the value of the LOW level counter provided in the main RAM 65 is decremented by 1 (step S1203), and it is determined whether the value of the LOW level counter after decrement is "0" (step S1204). The LOW level counter is a counter that allows the main CPU 63 to determine whether the set value update signal has been maintained at a LOW level for a predetermined period while multiple pulses that make the set value update signal a HI level are output. If the value of the LOW level counter is "0" (step S1204: YES), this means that it is time to set the set value update signal to a HI level, so the set value update signal is set to a HI level (step S1205).

Then, the HI level counter provided in the main RAM 65 is set to "20" (step S1206). The HI level counter is a counter for the main CPU 63 to determine the period during which the set value update signal is maintained at a HI level. The value set in the HI level counter is decremented by 1 at approximately 10 microsecond intervals, so that the set value update signal is maintained at a HI level for 200 microseconds when one pulse is output. This period during which the HI level is maintained is sufficient for the management CPU 112 to determine that the set value update signal has changed from a LOW level to a HI level.

If the set value update signal is at HI level (step S1202: YES), the value of the HI level counter in the main RAM 65 is decremented by 1 (step S1207), and it is determined whether the value of the HI level counter after decrement is "0" (step S1208). If the value of the HI level counter is "0" (step S1208: YES), this means that it is time to set the set value update signal to LOW level, so the set value update signal is set to LOW level (step S1209).

Then, the value of the pulse number counter in the main RAM 65 is decremented by 1 (step S1210), and it is determined whether the value of the pulse number counter after decrement is "0" (step S1211). If the value of the pulse number counter is not "0" (step S1211: NO), this means that the output of the pulse signal by the setting value update signal for the number of times corresponding to the currently set setting value of the pachinko machine 10 has not been completed, so the LOW level counter in the main RAM 65 is set to "20" (step S1212). The value set in the LOW level counter is decremented by 1 at approximately 10 microsecond intervals, so that the LOW level is maintained for 200 microseconds between multiple pulse outputs by the setting value update signal. This period of time during which the LOW level is maintained is sufficient for the management CPU 112 to determine that the setting value update signal has been changed from HI level to LOW level.

If the value of the pulse number counter is "0" (step S1211: YES), this means that the output of the pulse signal by the setting value update signal for the number of times corresponding to the currently set setting value of the pachinko machine 10 has been completed, so the output process of the setting value identification end command is executed (step S1213). The setting value identification end command is a command for making the management CPU 112 recognize that the output of the setting value update signal for making the management CPU 112 recognize the currently set setting value of the pachinko machine 10 has been completed. When outputting the setting value identification end command, the first to eighth signals input to the first to eighth buffers 122a to 122h are used in the same way as the identification start command, type identification command, and identification end command. However, the signal pattern of the setting value identification end command is different from that of the identification start command, type identification command, and identification end command.

As described above, in the output process of the setting value update signal, a number of pulse signals due to the setting value update signal corresponding to the value of the setting value of the pachinko machine 10 that was set when the current supply of operating power began are output to the management IC 66. The management side CPU 112 executes the setting update recognition process to determine the number of pulse signals due to the setting value update signal, and based on that, determines the setting value of the pachinko machine 10 that was set this time.

Figure 29 is a flowchart showing the setting update recognition process executed by the management CPU 112. Note that the setting update recognition process is executed in step S902 of the management process (Figure 23).

It is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from a LOW level to a HIGH level (step S1301). If a positive determination is made in step S1301, the value of the setting value grasp counter provided in the management RAM 114 is set to "1" (step S1302). The setting value grasp counter is a counter for identifying the setting value of the pachinko machine 10 by the management CPU 112; for example, a setting value grasp counter value of "1" means "setting 1," and a setting value grasp counter value of "6" means "setting 6."

Then, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HIGH level again (step S1303). If a positive determination is made in step S1303, the value of the setting value grasp counter in the management RAM 114 is incremented by 1 (step S1304). This causes the setting value of the pachinko machine 10 identified by the management CPU 112 to increase by one level.

If a negative determination is made in step S1303, or if the processing of step S1304 is executed, it is determined whether or not a set value identification end command has been received from the main CPU 63 based on the input state of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S1305). If a negative determination is made in step S1305, the processing returns to step S1303.

If the determination in step S1305 is affirmative, RTC information, which is date information and time information, is read from the RTC 115 (step S1306). Then, a write process to the history memory 117 is executed (step S1307). In the write process, the pointer information in the history area 124 that is currently being written is identified by referring to the pointer area 126 of the history memory 117, and the RTC information read in step S1306 is written to the history information storage area 125 of the history area 124 that corresponds to the pointer information that is being written. In addition, both information for identifying that it is a setting value and information on the value of the setting value grasp counter are written to the history information storage area 125 that corresponds to the pointer information that is being written. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time when the setting was made, and information on the setting value when the setting was made is stored as history information.

After that, the target pointer is updated (step S1308). In this update, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by one. It is determined whether the pointer information after the increment of one has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after the increment of one is overwritten in the pointer area 126 as the new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

By executing the setting update recognition process as described above, when the setting state of the pachinko machine 10 is newly set, the fact that the setting was made, the date and time when the setting was made, and the combination of setting values when the setting was made are stored as history information in the history area 124. As a result, by reading and analyzing the information stored in the history memory 117 using an external device connected to the reading terminal 68d, it is possible to know the date and time when the setting state of the pachinko machine 10 was newly set and the contents of the setting values when the setting was made.

Here, even if the setting state of the pachinko machine 10 is newly set, the information stored in the history memory 117 is maintained as is. This makes it possible to prevent the history information in the history memory 117 from being erased even if the setting state of the pachinko machine 10 is newly set, and various parameters described below are calculated using history information that exists across the timing of the change in the setting state of the pachinko machine 10. In this case, since the date and time when the setting state of the pachinko machine 10 is newly set as described above is stored in the history memory 117, by connecting an external device to the reading terminal 68d and reading the information stored in the history memory 117, it becomes possible to calculate various parameters for the period after the timing when the setting state of the pachinko machine 10 is newly set and during which the setting state is maintained.

Next, the display output process executed by the management CPU 112 will be described with reference to the flowchart in FIG. 30. Note that the display output process is executed in step S909 of the management process (FIG. 23).

First, it is determined whether it is the timing for calculation (step S1401). If 51 seconds have passed since the supply of operating power to the management CPU 112 started, or if 51 seconds have passed since the previous positive judgment in step S1401, a positive judgment is made in step S1401. If a positive judgment is made in step S1401, the number of balls entering during normal times is calculated (step S1402). Specifically, the number of balls entering the out hole 24a is calculated by first counting the number of history information storage areas 125 in which correspondence information indicating that the ball is the out hole 24a is stored in the history area 124 of the history memory 117. In addition, the number of balls entering the general winning hole 31 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the ball is the general winning hole 31 is stored in the history area 124 of the history memory 117. In addition, the number of balls that enter the special electric winning device 32 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the special electric winning device 32 is stored in the history area 124 of the history memory 117. In addition, the number of balls that enter the first operating port 33 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the special electric winning device 32 is stored in the history area 124 of the history memory 117. In addition, the number of balls that enter the second operating port 34 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the special electric winning device 32 is stored in the history area 124 of the history memory 117.

Then, by referring to the history information storage area 125 existing in the period between the history information storage area 125 in which the correspondence relationship information and start information indicating that it is the front door frame 14 are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence relationship information and end information indicating that it is the front door frame 14 are stored, the number of balls that entered each of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 that occurred when the front door frame 14 was in an open state is calculated (step S1403). The period between the history information storage area 125 in which the correspondence relationship information and start information indicating that it is the front door frame 14 are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence relationship information and end information indicating that it is the front door frame 14 are stored is calculated from the RTC information stored in these history information storage areas 125. In addition, in the entire pointer information with consecutive numbers, if there are multiple sections between the history information storage area 125 in which the correspondence information and start information indicating the front door frame 14 are stored and the history information storage area 125 in which the correspondence information and end information indicating the front door frame 14 are stored, the total number of balls entered for each section is calculated. In addition, if there is a history information storage area 125 in which the correspondence information and start information indicating the front door frame 14 are stored, but the correspondence information and end information indicating the front door frame 14 are not stored in the history information storage area 125 in which the RTC information corresponding to a time later than the history information storage area 125 in which the correspondence information and start information indicating the front door frame 14 are stored, all the history information in the history information storage area 125 in which the RTC information corresponding to a time later than the history information storage area 125 in which the correspondence information and start information indicating the front door frame 14 are stored is treated as if the front door frame 14 is in an open state.

After that, various parameters are calculated using the calculation results of steps S1402 and S1403 (step S1404). Specifically, first, the number of balls that entered the front door frame 14 while it was open, calculated in step S1403, is subtracted from the number of balls that entered the front door frame 14, calculated in step S1402. Then, the following first to eighth parameters are calculated using the number of balls entered after the subtraction. The difference between the number of balls entered the out-door 24a calculated in step S1402 and the number of balls entered the out-door 24a calculated in step S1403 is set as the number of balls entered K1, the difference between the number of balls entered the general winning port 31 calculated in step S1402 and the number of balls entered the general winning port 31 calculated in step S1403 is set as the number of balls entered K2, and the difference between the number of balls entered the special winning device 32 calculated in step S1402 and the number of balls entered the special winning device 32 calculated in step S1402 is set as the number of balls entered K3. The difference in the number of balls that enter the special electric winning device 32 calculated in step S1403 is designated as the number of entering balls K3, the difference in the number of balls that enter the first operating port 33 calculated in step S1402 and the number of balls that enter the first operating port 33 calculated in step S1403 is designated as the number of entering balls K4, and the difference in the number of balls that enter the second operating port 34 calculated in step S1402 and the number of balls that enter the second operating port 34 calculated in step S1403 is designated as the number of entering balls K5.
First parameter: total number of game balls paid out (K2 x "number of prize balls for winning the general winning port 31" + K3 x "number of prize balls for winning the special winning device 32" + K4 x "number of prize balls for winning the first operating port 33" + K5 x "number of prize balls for winning the second operating port 34") / total number of game balls discharged from the skill area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D1")
Second parameter: the ratio of the total number of game balls entering the general winning port 31 K2 to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5); Third parameter: the ratio of the total number of game balls entering the special electric winning device 32 K3 to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5); Fourth parameter: the ratio of the total number of game balls entering the first operating port 33 K4 to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio is referred to as "D2")
Fifth parameter: the ratio of the total number of game balls entering the second operating port 34 (K5) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio is referred to as "D3")
Sixth parameter: D1-(D2 x "number of winning balls for winning through the first actuation port 33" + D3 x "number of winning balls for winning through the second actuation port 34")
Seventh parameter: (K3 x "number of prize balls for winning the special electric winning device 32" + K5 x "number of prize balls for winning the second operating port 34") / total number of game balls paid out (K2 x "number of prize balls for winning the general winning port 31" + K3 x "number of prize balls for winning the special electric winning device 32" + K4 x "number of prize balls for winning the first operating port 33" + K5 x "number of prize balls for winning the second operating port 34") 8th parameter: K3 x "number of prize balls for winning at special electric winning device 32" / total number of game balls paid out (K2 x "number of prize balls for winning at general winning port 31" + K3 x "number of prize balls for winning at special electric winning device 32" + K4 x "number of prize balls for winning at first operating port 33" + K5 x "number of prize balls for winning at second operating port 34") ratio. In step S1404, the first to eighth parameters, which are the results of the calculation, are stored in a normal time memory area in calculation result memory 131. The first to eighth parameters stored in the normal time memory area are retained until the next time step S1404 is executed. In other words, when step S1404 is executed next time and the first to eighth parameters are calculated, the newly calculated first to eighth parameters are stored in the normal time memory area, overwriting the previous calculation results of the first to eighth parameters that had been stored in the normal time memory area up until that point.

Then, by referring to the history information storage area 125 existing in the period between the history information storage area 125 in which the correspondence relationship information and start information indicating the open/close execution mode are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence relationship information and end information indicating the open/close execution mode are stored, the number of balls entering each of the out hole 24a, the general winning hole 31, the special electric winning device 32, the first operating hole 33, and the second operating hole 34 that occurred in the open/close execution mode is calculated (step S1405). The period between the history information storage area 125 in which the correspondence relationship information and start information indicating the open/close execution mode are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence relationship information and end information indicating the open/close execution mode are stored is calculated from the RTC information stored in these history information storage areas 125. In addition, in the entire pointer information with consecutive numbers, if there are multiple sections between the history information storage area 125 in which the correspondence relationship information and start information indicating the opening and closing execution mode are stored and the history information storage area 125 in which the correspondence relationship information and end information indicating the opening and closing execution mode are stored, the total number of balls entered for each section is calculated. In addition, if there is a history information storage area 125 in which the correspondence relationship information and start information indicating the opening and closing execution mode are stored, but the history information storage area 125 in which the RTC information corresponding to a time later than the history information storage area 125 is stored does not store the correspondence relationship information and end information indicating the opening and closing execution mode, all the history information in the history information storage area 125 in which the RTC information corresponding to a time later than the history information storage area 125 in which the correspondence relationship information and start information indicating the opening and closing execution mode are stored is treated as being in the opening and closing execution mode.

Then, the number of balls that entered each of the outlet 24a, the general winning port 31, the special winning device 32, the first operating port 33, and the second operating port 34 while the front door frame 14 was in the open state during the period in the opening and closing execution mode identified in step S1405 is calculated (step S1406). The method for calculating the number of balls is the same as in step S1403, except that it is based on the period in the opening and closing execution mode identified in step S1405.

After that, various parameters are calculated using the results of the calculations in steps S1405 and S1406 (step S1407). Specifically, first, the number of balls that entered the front door frame 14 while it was open, calculated in step S1406, is subtracted from the number of balls that entered the front door frame 14 calculated in step S1405. Then, the following eleventh to eighteenth parameters are calculated using the number of balls entered after the subtraction. The difference between the number of balls entered the out-port 24a calculated in step S1405 and the number of balls entered the out-port 24a calculated in step S1406 is set as the number of balls entered K11, the difference between the number of balls entered the general winning port 31 calculated in step S1405 and the number of balls entered the general winning port 31 calculated in step S1406 is set as the number of balls entered K12, and the difference between the number of balls entered the special winning device 32 calculated in step S1405 and the number of balls entered K13 is set as the number of balls entered K14. The difference in the number of balls that enter the special electric winning device 32 calculated in step S1406 is designated as the number of entering balls K13, the difference in the number of balls that enter the first operating port 33 calculated in step S1406 relative to the number of balls that enter the first operating port 33 calculated in step S1405 is designated as the number of entering balls K14, and the difference in the number of balls that enter the second operating port 34 calculated in step S1405 relative to the number of balls that enter the second operating port 34 calculated in step S1406 is designated as the number of entering balls K15.
11th parameter: total number of game balls paid out (K12 x "number of prize balls for winning the general winning port 31" + K13 x "number of prize balls for winning the special winning device 32" + K14 x "number of prize balls for winning the first operating port 33" + K15 x "number of prize balls for winning the second operating port 34") / total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) ratio (hereinafter, this ratio will be referred to as "D11")
・12th parameter: Ratio of total number of game balls entering the general winning port 31 K12/total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) ・13th parameter: Ratio of total number of game balls entering the special winning device 32 K13/total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) ・14th parameter: Ratio of total number of game balls entering the first operating port 33 K14/total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) (hereinafter, this ratio is referred to as "D12")
15th parameter: the ratio of the total number of game balls entering the second operating port 34 (K15) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D13")
16th parameter: D11-(D12 x "number of winning balls for winning the first actuation port 33" + D13 x "number of winning balls for winning the second actuation port 34")
17th parameter: (K13 x "number of prize balls for winning the special electric winning device 32" + K15 x "number of prize balls for winning the second operating port 34") / total number of game balls paid out (K12 x "number of prize balls for winning the general winning port 31" + K13 x "number of prize balls for winning the special electric winning device 32" + K14 x "number of prize balls for winning the first operating port 33" + K15 x "number of prize balls for winning the second operating port 34") 18th parameter: K13 x "number of prize balls for winning at the special electric winning device 32" / total number of game balls paid out (K12 x "number of prize balls for winning at the general winning port 31" + K13 x "number of prize balls for winning at the special electric winning device 32" + K14 x "number of prize balls for winning at the first operating port 33" + K15 x "number of prize balls for winning at the second operating port 34") ratio. In step S1407, the 11th to 18th parameters, which are the results of the calculation, are stored in a memory area for the opening and closing execution mode in the calculation result memory 131. The 11th to 18th parameters stored in the memory area for the opening and closing execution mode are retained until the next time step S1407 is executed. In other words, when step S1407 is executed next time and the 11th to 18th parameters are calculated, the newly calculated 11th to 18th parameters are stored in the memory area for the opening/closing execution mode, overwriting the previous calculation results of the 11th to 18th parameters that had been stored in the memory area for the opening/closing execution mode.

Then, by referring to the history information storage area 125 existing in the period between the history information storage area 125 in which the correspondence relationship information and start information indicating the high-frequency support mode are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence relationship information and end information indicating the high-frequency support mode are stored, the number of balls entering each of the out hole 24a, the general winning hole 31, the special electric winning device 32, the first operating hole 33, and the second operating hole 34 that occurred in the high-frequency support mode situation is calculated (step S1408). The period between the history information storage area 125 in which the correspondence relationship information and start information indicating the high-frequency support mode are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence relationship information and end information indicating the high-frequency support mode are stored is calculated from the RTC information stored in these history information storage areas 125. In addition, in the entire pointer information with consecutive numbers, if there are multiple sections between the history information storage area 125 in which the correspondence relationship information and start information indicating the high-frequency support mode are stored and the history information storage area 125 in which the correspondence relationship information and end information indicating the high-frequency support mode are stored, the total number of balls entered for each section is calculated. In addition, if there is a history information storage area 125 in which the correspondence relationship information and start information indicating the high-frequency support mode are stored, but the history information storage area 125 in which the RTC information corresponding to a time later than the history information storage area 125 is stored does not store the correspondence relationship information and end information indicating the high-frequency support mode, all the history information in the history information storage area 125 in which the RTC information corresponding to a time later than the history information storage area 125 in which the correspondence relationship information and start information indicating the high-frequency support mode are stored is treated as being in the high-frequency support mode.

Then, during the period of the high-frequency support mode identified in step S1408, the number of balls that entered each of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 while the front door frame 14 was in the open state is calculated (step S1409). The method of calculating these numbers of balls is the same as in step S1403, except that it is based on the period of the high-frequency support mode identified in step S1408.

After that, various parameters are calculated using the calculation results of steps S1408 and S1409 (step S1410). Specifically, first, the number of balls that entered the front door frame 14 while it was open, calculated in step S1409, is subtracted from the number of balls that entered the front door frame 14 calculated in step S1408. Then, the following 21st to 26th parameters are calculated using the number of balls entered after the subtraction. The difference between the number of balls entered the out port 24a calculated in step S1408 and the number of balls entered the out port 24a calculated in step S1409 is set as the number of balls entered K21, the difference between the number of balls entered the general winning port 31 calculated in step S1408 and the number of balls entered the general winning port 31 calculated in step S1409 is set as the number of balls entered K22, and the difference between the number of balls entered the special winning device 32 calculated in step S1408 and the number of balls entered K23 is set as the number of balls entered K24. The difference in the number of balls that enter the special electric winning device 32 calculated in step S1409 is designated as the number of entering balls K23, the difference in the number of balls that enter the first operating port 33 calculated in step S1409 relative to the number of balls that enter the first operating port 33 calculated in step S1408 is designated as the number of entering balls K24, and the difference in the number of balls that enter the second operating port 34 calculated in step S1409 relative to the number of balls that enter the second operating port 34 calculated in step S1408 is designated as the number of entering balls K25.
21st parameter: total number of game balls paid out (K22 x "number of prize balls for winning the general winning port 31" + K23 x "number of prize balls for winning the special winning device 32" + K24 x "number of prize balls for winning the first operating port 33" + K25 x "number of prize balls for winning the second operating port 34") / total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) ratio (hereinafter, this ratio will be referred to as "D11")
22nd parameter: Ratio of total number of game balls entering the general winning port 31 K22/total number of game balls discharged from the game area PA (K21+K22+K23+K24+K25) 23rd parameter: Ratio of total number of game balls entering the special winning device 32 K23/total number of game balls discharged from the game area PA (K21+K22+K23+K24+K25) 24th parameter: Ratio of total number of game balls entering the first operating port 33 K24/total number of game balls discharged from the game area PA (K21+K22+K23+K24+K25) (hereinafter, this ratio is referred to as "D22")
25th parameter: the ratio of the total number of game balls entering the second operating port 34 (K25) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D23")
26th parameter: D21-(D22 x "number of winning balls for winning the first actuation port 33" + D23 x "number of winning balls for winning the second actuation port 34")
In step S1410, the 21st to 26th parameters, which are the calculation results, are stored in a storage area for high frequency support mode in the calculation result memory 131. The 21st to 26th parameters stored in the storage area for high frequency support mode are stored and held until the next execution of step S1410. In other words, when the next step S1410 is executed and the 21st to 26th parameters are calculated, the newly calculated 21st to 26th parameters are stored in the storage area for high frequency support mode, overwriting the previous calculation results of the 21st to 26th parameters that were stored in the storage area for high frequency support mode.

Then, the frequency of occurrence of the opening and closing execution mode is calculated and stored (step S1411). Specifically, the number of occurrences of the opening and closing execution mode is calculated by counting the number of history information storage areas 125 in which the correspondence relationship information and start information indicating the opening and closing execution mode are stored in the history area 124 of the history memory 117. Also, the number of occurrences of game times is calculated by counting the number of history information storage areas 125 in which the correspondence relationship information indicating the start of a game time is stored in the history area 124 of the history memory 117. Then, the number of occurrences of the opening and closing execution mode per unit game time is calculated. The number of occurrences of the opening and closing execution mode is set as the number of occurrences K31, and the number of occurrences of a game time is set as the number of occurrences K32.
・31st parameter: K31/K32
In step S1411, the 31st parameter, which is the calculation result, is stored in an opening/closing execution mode frequency storage area in the calculation result memory 131. The 31st parameter stored in the opening/closing execution mode frequency storage area is stored and held until the next execution of step S1411. In other words, when the next step S1411 is executed to calculate the 31st parameter, the newly calculated 31st parameter is stored in the opening/closing execution mode frequency storage area, overwriting the previous calculation result of the 31st parameter that was stored in the opening/closing execution mode frequency storage area.

Then, the occurrence frequency of the high-frequency support mode is calculated and stored (step S1412). Specifically, the number of occurrences of the high-frequency support mode is calculated by counting the number of history information storage areas 125 in which the correspondence relationship information and start information indicating the high-frequency support mode are stored in the history area 124 of the history memory 117. Also, the number of occurrences of the game times is calculated by counting the number of history information storage areas 125 in which the correspondence relationship information indicating the start of the game times is stored in the history area 124 of the history memory 117. Then, the number of occurrences of the high-frequency support mode per unit game time and the ratio of the number of occurrences of the high-frequency support mode to the number of occurrences of the opening and closing execution mode are calculated. Note that the number of occurrences of the high-frequency support mode is the number of occurrences K41, the number of occurrences of the game times is the number of occurrences K42, and the number of occurrences of the opening and closing execution mode calculated in step S1411 is the number of occurrences K43.
41st parameter: K41/K42
42nd parameter: K41/K43
In step S1412, the 41st to 42nd parameters, which are the calculation results, are stored in a high support mode frequency storage area in the calculation result memory 131. The 41st to 42nd parameters stored in the high support mode frequency storage area are stored and held until the next execution of step S1412. In other words, when the next step S1412 is executed and the 41st to 42nd parameters are calculated, the newly calculated 41st to 42nd parameters are stored in the high support mode frequency storage area, overwriting the previous calculation results of the 41st to 42nd parameters that were stored in the high support mode frequency storage area up to that point.

If a negative determination is made in step S1401, or if the processing of step S1412 is executed, display processing is executed (step S1413). FIG. 31 is a flowchart showing the display processing.

First, the value of the update timing counter provided in the management RAM 114 is decremented by 1 (step S1501). The update timing counter is a counter for the management CPU 112 to identify that it is time to update the display contents of the management results of the game history in the first to third notification display devices 69a to 69c. The management CPU 112 notifies the calculation results of the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters by controlling the display of the first to third notification display devices 69a to 69c. In this case, the first notification display device 69a displays information corresponding to the type of the parameter to be notified. In addition, the number corresponding to the tens digit of the value obtained by multiplying the parameter to be notified by 100 is displayed on the second notification display device 69b, and the number corresponding to the ones digit is displayed on the third notification display device 69c. In the first to third notification display devices 69a to 69c, the displays corresponding to the calculation results of the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters are switched in sequence in a predetermined order, and after the calculation result of the forty-second parameter, which is the last parameter to be displayed, is displayed, the calculation result of the first parameter, which is the first parameter to be displayed, is displayed. In this case, the period during which the calculation result of one parameter is continuously displayed is two seconds.

The calculation period for the various parameters in the management CPU 112 is 51 seconds. In contrast, the number of various parameters is 25, and the period during which the calculation result for one parameter is continuously displayed is 2 seconds. Therefore, the various parameters calculated by the management CPU 112 are displayed at least once on the first to third notification display devices 69a to 69c.

When the process of step S1501 is executed, it is determined whether the value of the update timing counter after subtracting 1 is "0" to determine whether it is time to update the display contents of the first to third alarm display devices 69a to 69c (step S1502). If a positive determination is made in step S1502, the value of the display target counter provided in the management RAM 114 is incremented by 1 (step S1503). Then, if the value of the display target counter after incrementing 1 exceeds the maximum value of "24" (step S1504: YES), the value of the display target counter is cleared to "0" (step S1505).

The display object counter is a counter that allows the management CPU 112 to identify the type of parameter that is the display object on the first to third notification display devices 69a to 69c. There is a one-to-one correspondence between the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters and the possible values of the display object counter, "0" to "24." For example, when the value of the display object counter is "0," the first parameter, which is the first display object, becomes the display object on the first to third notification display devices 69a to 69c, and when the value of the display object counter is "24," the forty-second parameter, which is the last display object, becomes the display object on the first to third notification display devices 69a to 69c.

When a negative judgment is made in step S1504, or when the process of step S1505 is executed, the display of the first notification display device 69a is controlled so that information corresponding to the type of parameter corresponding to the value of the counter to be displayed is displayed (step S1506). In addition, the parameter corresponding to the value of the counter to be displayed is read from the calculation result memory 131, and the read parameter is multiplied by 100 so that the number corresponding to the tens digit is displayed on the second notification display device 69b and the number corresponding to the ones digit is displayed on the third notification display device 69c (step S1507). The contents displayed on the first to third notification display devices 69a to 69c in steps S1506 and S1507 continue until the next update timing occurs or until the supply of operating power to the management side CPU 112 is stopped. After that, a value corresponding to 2 seconds is set to the update timing counter of the management side RAM 114 as the value corresponding to the next update timing (step S1508).

By executing the display process as described above, when the supply of operating power to the management CPU 112 has begun, the game history management results are displayed on the first to third notification display devices 69a to 69c. The game history management results are displayed regardless of whether or not play is continuing, and regardless of whether or not the gaming machine main body 12 has been opened relative to the outer frame 11 and the main control device 60 is visible from the front of the pachinko machine 10. By executing display control of the first to third notification display devices 69a to 69c in this way regardless of the game situation or the state of the pachinko machine 10, it is possible to simplify the processing configuration for display control of the first to third notification display devices 69a to 69c.

The display of the game history management results on the first to third notification display devices 69a to 69c begins after the supply of operating power to the management CPU 112 has started and after the identification end command has been received from the main CPU 63. In this case, the information stored in the calculation result memory 131, like the information stored in the history memory 117, is stored and retained even when the supply of operating power to the pachinko machine 10 has been stopped, so that when the supply of operating power to the management CPU 112 has started, the game history management results calculated before the supply of operating power to the management CPU 112 was stopped are displayed.

When the setting state of the pachinko machine 10 is changed after the supply of operating power to the main CPU 63 has started, information corresponding to the setting value being changed is displayed on the third notification display device 69c, but the display of the information corresponding to the setting value is performed before the identification end command is sent from the main CPU 63, whereas the display of the game history management results on the first to third notification display devices 69a to 69c begins after the identification end command is sent from the main CPU 63. This makes it possible to prevent the display periods of these displays from overlapping, even if the third notification display device 69c is configured to be used as a display device for both displaying the information corresponding to the setting value and displaying the game history management results.

In addition, when information corresponding to the set value is displayed, the first notification display device 69a and the second notification display device 69b are hidden. In contrast, when the game history management results are displayed, the first notification display device 69a and the second notification display device 69b are not hidden. This makes it possible to distinguish whether the third notification display device 69c is displaying information corresponding to the set value or displaying the game history management results.

Next, a process configuration for outputting the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131 to an external device electrically connected to the read terminal 68d of the MPU 62 will be described. FIG. 32(a) is a flowchart showing the data output process executed by the main CPU 63. The data output process is executed in step S112 in the main process (FIG. 9).

In the data output process, first, it is determined whether or not a connection signal indicating that an external device is electrically connected to the read terminal 68d is received from the read terminal 68d (step S1601). If a negative determination is made in step S1601, the data output process is terminated as is. In this case, in order to execute the data output process, it is necessary to restart the supply of operating power to the main CPU 63. In order to perform the external output of the history information and various parameters, it is necessary to start the supply of operating power to the main CPU 63 with the external device electrically connected to the read terminal 68d. The power switch for stopping and starting the supply of operating power to the main CPU 63 is provided in the payout mechanism 73 mounted on the back of the back pack unit 15, so that in order to perform these stopping and starting operations, it is necessary to open the gaming machine main body 12 relative to the outer frame 11 to expose the back of the back pack unit 15. Under these circumstances, in order to output the history information and various parameters to the outside, it is necessary to electrically connect an external device to the reading terminal 68d and start supplying operating power to the main CPU 63. This makes it difficult for anyone other than the manager of the amusement hall to read the history information and various parameters.

If the positive determination is made in step S1601, it is determined whether or not a signal for confirming control information is received from the read terminal 68d, and whether or not the current connection of the external device to the read terminal 68d corresponds to confirmation of the control information (programs and data) of the main ROM 64 (step S1602). The external device is configured to be able to perform both confirmation of control information and confirmation of history information and various parameters, and when confirmation of control information is selected by manual operation of the external device, a signal for confirming control information is transmitted from the external device, and when confirmation of history information and various parameters is selected by manual operation of the external device, a signal for confirming history is transmitted from the external device. Note that this is not limited to this, and a configuration in which the external device for confirming control information and the external device for confirming history may be separate. In this case, when an external device for confirming control information is electrically connected to the read terminal 68d, a signal for confirming control information is transmitted from the external device, and when an external device for confirming history is electrically connected to the read terminal 68d, a signal for confirming history is transmitted from the external device.

If a positive determination is made in step S1602, an output process for confirming the control information is executed (step S1603). In this output process, the program and data are read from the main ROM 64 as control information, and the read control information is output to the read terminal 68d. This makes it possible to read the control information in an external device electrically connected to the read terminal 68d, and to confirm whether the control information is authentic or normal.

If a negative judgment is made in step S1602, an output instruction signal is sent to the management CPU 112 (step S1604). Specifically, the output state of the output instruction signal is switched from a LOW level to a HIGH level. This HIGH level output state continues for a specific period of time. This specific period is sufficient for the management CPU 112 to determine that a HIGH level output instruction signal has been input to the 16th buffer 122p. As a result of the output state of the output instruction signal being switched to a HIGH level, a process is executed in the management CPU 112 to output history information.

Specifically, as shown in the flowchart of FIG. 32(b), when the output state of the output instruction signal input to the 16th buffer 122p of the input port 121 switches from LOW level to HIGH level (step S1701: YES), the management CPU 112 reads out the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131, and outputs the read history information and various parameters to the read terminal 68d (step S1702). This makes it possible to read the history information and various parameters in an external device electrically connected to the read terminal 68d, and to analyze the information on the management results of the game history. In addition, when the management CPU 112 outputs the history information to the read terminal 68d, it clears the history memory 117 to "0" (step S1703). The history information in the history memory 117 is erased only when the history information is read by an external device.

Returning to the explanation of the data output process (FIG. 32(a)), when the process of step S1603 is executed or when the process of step S1604 is executed, it is determined whether or not the electrical connection of the external device to the read terminal 68d is still ongoing (step S1605). If it is still ongoing (step S1605: YES), the process waits in step S1605. This makes it possible to prevent a process set in the execution order after the data output process from being executed until the external device is disconnected from the read terminal 68d. When the external device is disconnected from the read terminal 68d (step S1605: NO), the data output process is terminated.

The present embodiment described above provides the following excellent advantages:

When a game ball enters any of the general winning opening 31, the special winning device 32, the first operating opening 33, and the second operating opening 34, the game ball is paid out, so the player plays the game while hoping that the game ball will enter any of these ball entry sections. In this configuration, when a game ball enters any of the out opening 24a, the general winning opening 31, the special winning device 32, the first operating opening 33, and the second operating opening 34 (hereinafter also referred to as the history target ball entry section), the corresponding history information is stored in the history memory 117 of the management IC 66. This makes it possible to store and hold information for managing the number of game balls entering each history target ball entry section or the ball entry frequency in the pachinko machine 10, and by using this managed information, it becomes possible to appropriately manage the ball entry mode of each history target ball entry section. In addition, since the history information is stored and held in the pachinko machine 10 itself, it becomes possible to prevent unauthorized access to or unauthorized modification of the history information.

All ball entry sections that eject game balls from the game area PA are subject to the execution of the history information storage process and are also subject to management using the history information. This makes it possible to manage the frequency of ball entry at any history target ball entry section using the history information. It also makes it possible to manage the ratio of the number of balls that enter each history target ball entry section to the number of balls that are ejected from the game area PA using the history information.

The history information includes RTC information, which is information corresponding to the timing at which the game ball entered the history target entry part that triggered the storage of the history information. This makes it possible to use the history information to obtain a detailed understanding of the game ball entry history at the history target entry part.

The history memory 117 stores not only history information corresponding to game balls entering the history target ball entry section, but also history information indicating whether the opening/closing execution mode is in effect, history information indicating whether the high frequency support mode is in effect, and history information indicating whether the front door frame 14 is open or not. This makes it possible to distinguish between these situations and manage the manner in which game balls enter the history target ball entry section.

The history information stored in the history memory 117 can be output to an external device that is a device outside the pachinko machine 10. This makes it possible to read the history information in the external device and use the read history information to analyze the manner in which game balls enter the history target entry portion.

The MPU 62 is provided with a read terminal 68d, and an external device electrically connected to the read terminal 68d can read the program from the main ROM 64. This makes it possible to check whether the program is normal or not. In this configuration, the read terminal 68d for externally outputting the program is used to externally output the history information stored in the history memory 117. This makes it possible to externally output the history information while preventing the configuration from becoming too complicated.

It is determined whether the information to be output from the read terminal 68d is a program or history information, and the information corresponding to the determination result is output to the outside through the read terminal 68d. As a result, in a configuration in which history information is output to the outside using the read terminal 68d for external output of a program, the pachinko machine 10 determines whether the information to be output to the outside is a program or history information, and outputs the determined information to the outside. Therefore, even in a configuration in which the read terminal 68d is used for both purposes, it is possible to read out only the necessary information.

Based on information received from an external device electrically connected to the read terminal 68d, it is determined whether the information to be output from the read terminal 68d is program information or history information. This makes it possible to prevent the configuration for selecting the information to be output to the outside from becoming complicated.

The MPU 62, which has a main ROM 64 that stores programs in advance, has a management IC 66 and a read terminal 68d. This makes it possible to consolidate the signal path to the read terminal 68d within the MPU 62. This makes it possible to achieve the excellent effects already described while making it difficult to gain unauthorized access to the signal path to the read terminal 68d.

A management CPU 112 is provided in addition to the main CPU 63, which executes the process to have game balls paid out based on the game balls entering either the general winning port 31, the special winning device 32, the first operating port 33, or the second operating port 34, and the management CPU 112 executes the process to have history information stored in the history memory 117. This makes it possible to manage the game ball entry patterns into each history target ball entry section while preventing the processing load on the main CPU 63 from increasing excessively.

The main CPU 63 and the management CPU 112 are provided on the same chip as the MPU 62. This makes it possible to prevent unauthorized access to the communication path between the main CPU 63 and the management CPU 112.

The main CPU 63 transmits information corresponding to the detection results of each of the ball entry detection sensors 42a-48a to each of the buffers 122a-122g of the input port 121 of the management IC 66, using the signal paths corresponding to each of the ball entry detection sensors 42a-48a. This allows the type of information transmitted from the main CPU 63 to correspond to each of the buffers 122a-122g (i.e., each signal path), simplifying the configuration for distinguishing each type of information in the management CPU 112.

The main CPU 63 transmits information corresponding to whether the opening/closing execution mode is in progress, information corresponding to whether the high frequency support mode is in progress, information corresponding to whether the front door frame 14 is open, and information corresponding to the start of a game round to each of the buffers 122h-122k of the input port 121 of the management IC 66 using the signal paths corresponding to each of these situations. This allows the type of information corresponding to each of these situations to correspond to each of the buffers 122h-122k (i.e., each signal path), making it possible to simplify the configuration for distinguishing between each type of information in the management CPU 112.

The main CPU 63 transmits to the management CPU 112 correspondence information indicating which type of information each of the buffers 122a-122k (i.e., each of the signal paths 118a-118k) corresponds to. This eliminates the need to store the correspondence information in advance in the management IC 66. This makes it possible to increase the versatility of the management IC 66.

When the supply of operating power to the main CPU 63 is started, the main CPU 63 transmits correspondence information to the management IC 66. This makes it possible for the management IC 66 to identify the correspondence between the information transmitted from the main CPU 63 and the history target ball entry area in a situation where a game ball may enter the history target ball entry area.

The correspondence information is sent from the main CPU 63 to the management IC 66 using signal paths 118a to 118g for transmitting information indicating whether or not a game ball has entered the history target entry portion. This makes it possible to simplify the communication configuration compared to a configuration in which a dedicated signal path is provided for transmitting the correspondence information.

The management IC 66 is provided with a correspondence memory 116, and the correspondence information transmitted from the main CPU 63 to the management IC 66 is stored in the correspondence memory 116. This eliminates the need to provide information that enables the management IC 66 to identify the historical target goal location that corresponds to the information to be transmitted each time the main CPU 63 transmits information on the detection results of each goal detection sensor 42a to 48a. This makes it possible to reduce the amount of information transmitted from the main CPU 63 regarding the detection results of each goal detection sensor 42a to 48a.

When the output state of the output instruction signal output from the main CPU 63 to the management IC 66 switches from LOW level to HIGH level, information is output from the management IC 66 to the read terminal 68d. In this case, the management CPU 112 can identify that the signal path corresponding to the 16th buffer 122p corresponds to the output instruction signal without receiving the correspondence information from the main CPU 63. This makes it possible to prevent the configuration for transmitting the correspondence information from becoming extremely complicated.

The management IC 66 is provided with buffers 122a-122p capable of receiving information from the main CPU 63, the number of which is greater than the number of types of information that need to be sent from the main CPU 63 to the management IC 66. This makes it possible to accommodate an increase or decrease in the number of types of information depending on the model of pachinko machine 10 without changing the configuration of the buffers 122a-122p. This makes it possible to increase the versatility of the management IC 66.

When history information is sent from the management IC 66 to the read terminal 68d, the history information includes correspondence information indicating the type of history target ball entry section that corresponds to the history information. This makes it possible to use the read history information to identify the manner in which the game ball entered each history target ball entry section.

By using the history information stored in the history memory 117, the management IC 66 calculates various parameters (1st to 8th parameters, 11th to 18th parameters, 21st to 26th parameters, 31st parameter, 41st to 42nd parameters) corresponding to the ball entry state of the game ball in the game area PA during a specified period. The various parameters resulting from these calculations are then displayed in sequence on the first to third notification display devices 69a to 69c. This makes it possible to notify the pachinko machine 10 of the various parameters that are the results of calculations using the history information.

Various parameters are calculated with the historical information corresponding to the situation where the front door frame 14 is open excluded. This makes it possible to derive various parameters in the normal situation where the front door frame 14 is closed. In addition, various parameters corresponding to the situation in the opening and closing execution mode and the situation in the high frequency support mode are calculated. This makes it possible for the manager of the amusement hall to grasp the manner in which game balls enter the game depending on each situation.

When history information in history memory 117 is output to an external device, a process for clearing history memory 117 is executed to initialize history memory 117. This makes it possible to prevent the occurrence of an event in which history information that would normally be stored is erased by overwriting, as a result of history information being stored in history memory 117 to the extent that it exceeds the storage capacity of history memory 117.

In a configuration in which an external output corresponding to the entry of a game ball into the first actuation port 33 or the second actuation port 34 is sent via the external terminal board 97, history information is stored in the history memory 117. This makes it possible to easily determine the number and frequency of game balls that have entered the first actuation port 33 or the second actuation port 34 by using the information outputted externally via the external terminal board 97, while accurately determining the number and frequency of game balls that have entered the history target entry portion by using the history information stored in the history memory 117.

The probability of a jackpot result in low probability mode varies depending on the setting state of the pachinko machine 10, from "Setting 1" to "Setting 6." This makes it possible to create favorable or unfavorable conditions for the probability of a jackpot result in low probability mode even with a single pachinko machine 10. This makes it possible to increase the interest of the game.

While the probability of a jackpot result in low probability mode varies depending on the setting state of the pachinko machine 10 from "Setting 1" to "Setting 6," the probability of a jackpot result in high probability mode does not vary depending on the setting state of the pachinko machine 10. This makes it possible to limit the effect of the setting state of the pachinko machine 10 on the probability of a jackpot result to the situation in low probability mode. In addition, since the high probability hit/miss table 64g referenced in high probability mode can be made common regardless of the setting state of the pachinko machine 10, it is possible to suppress an increase in the storage capacity for storing the hit/miss tables 64a to 64g in advance in the main ROM 64.

While the probability of a jackpot result in low probability mode varies depending on the setting state of the pachinko machine 10 from "Setting 1" to "Setting 6," the allocation manner of the types of jackpot results does not vary depending on the setting state of the pachinko machine 10. This makes it possible to limit the influence of the setting state of the pachinko machine 10 to the situation in low probability mode. In addition, since the allocation table 64h that is referenced when allocating the types of jackpot results can be made common regardless of the setting state of the pachinko machine 10, it is possible to suppress an increase in the storage capacity for storing the allocation table 64h in advance in the main ROM 64.

Even if a new setting is made to the setting state of the pachinko machine 10, the history information stored in the history memory 117 is not erased but is retained. This makes it possible to continue storing the previous history information in the history memory 117 even if a new setting is made to the setting state of the pachinko machine 10, and makes it possible to identify the results of management of the game history by using the history information accumulated in the history memory 117 over a long period of time.

In a configuration in which the history information stored in the history memory 117 is not erased but is retained even when a new setting is made to the setting state of the pachinko machine 10, when a new setting is made to the setting state of the pachinko machine 10, the corresponding history information is stored in the history memory 117. This makes it possible to distinguish between the history information before the new setting of the setting state of the pachinko machine 10 is made and the history information after the new setting is made.

When a new setting is made to the setting state of the pachinko machine 10 and the corresponding history information is stored in the history memory 117, information corresponding to the setting value is included in the history information. This makes it possible to identify the contents of the setting value that was previously set by referring to the history information.

When calculating various parameters at the calculation timing, the history information corresponding to the new setting of the setting state of the pachinko machine 10 in the history memory 117 may be used as a reference, and the various parameters may be calculated using history information stored later. In this case, it is possible to derive the results of the management of the game history at the timing after the new setting of the setting state of the pachinko machine 10 is performed as various parameters.

In addition, when various parameters are calculated at the calculation timing, the history information in the history memory 117 corresponding to the new setting of the setting state of the pachinko machine 10 and corresponding to the change in the setting value may be used as a reference, and the various parameters may be calculated using history information stored later. In this case, it is possible to derive the results of the management of the game history at the timing after the setting state of the pachinko machine 10 is changed as various parameters.

In addition, the circuit board box 60a of the main control device 60 is configured to have an opening for exposing the reading terminal 68d, but the circuit board box 60a may not have this opening and the reading terminal 69d may be covered by the opposing wall 60b. In this case, it is necessary to open the circuit board box 60a in order to connect an external device to the reading terminal 68d.

Second Embodiment
In this embodiment, the contents of the winning/losing table corresponding to the setting state of the pachinko machine 10 are different from those of the first embodiment. The following describes the configurations that are different from the first embodiment. Note that the description of the same configurations as the first embodiment will basically be omitted.

Figure 33 is an explanatory diagram for explaining the various tables stored in the main ROM 64 in this embodiment.

33, the main ROM 64 is provided with an area 161 for setting 1, an area 162 for setting 2, an area 163 for setting 3, an area 164 for setting 4, an area 165 for setting 5, and an area 166 for setting 6. The area 161 for setting 1 stores a low probability win/lose table 161a for setting 1 that is referenced when the setting state of the pachinko machine 10 is "setting 1" and the win/lose selection mode is the low probability mode, and a high probability win/lose table 161b for setting 1 that is referenced when the setting state of the pachinko machine 10 is "setting 1" and the win/lose selection mode is the high probability mode. The setting 2 area 162 stores a low probability win/loss table 162a for setting 2 that is referenced when the setting state of the pachinko machine 10 is "setting 2" and the win/loss selection mode is the low probability mode, and a high probability win/loss table 162b for setting 2 that is referenced when the setting state of the pachinko machine 10 is "setting 2" and the win/loss selection mode is the high probability mode. The setting 3 area 163 stores a low probability win/loss table 163a for setting 3 that is referenced when the setting state of the pachinko machine 10 is "setting 3" and the win/loss selection mode is the low probability mode, and a high probability win/loss table 163b for setting 3 that is referenced when the setting state of the pachinko machine 10 is "setting 3" and the win/loss selection mode is the high probability mode.

The area 164 for setting 4 stores a low-probability win/loss table 164a for setting 4 that is referenced when the setting state of the pachinko machine 10 is "setting 4" and the win/loss selection mode is the low probability mode, and a high-probability win/loss table 164b for setting 4 that is referenced when the setting state of the pachinko machine 10 is "setting 4" and the win/loss selection mode is the high probability mode. The area 165 for setting 5 stores a low-probability win/loss table 165a for setting 5 that is referenced when the setting state of the pachinko machine 10 is "setting 5" and the win/loss selection mode is the low probability mode, and a high-probability win/loss table 165b for setting 5 that is referenced when the setting state of the pachinko machine 10 is "setting 5" and the win/loss selection mode is the high probability mode. The area 166 for setting 6 stores a low probability win/lose table 166a for setting 6 that is referenced when the setting state of the pachinko machine 10 is "setting 6" and the win/lose selection mode is the low probability mode, and a high probability win/lose table 166b for setting 6 that is referenced when the setting state of the pachinko machine 10 is "setting 6" and the win/lose selection mode is the high probability mode.

The probability of winning the jackpot set in each of the low probability tables 161a to 166a is different from each other. Specifically, when the low probability table 161a for setting 1 is referenced, the probability of a jackpot result is about 1/320, when the low probability table 162a for setting 2 is referenced, the probability of a jackpot result is about 1/310, when the low probability table 163a for setting 3 is referenced, the probability of a jackpot result is about 1/300, when the low probability table 164a for setting 4 is referenced, the probability of a jackpot result is about 1/290, when the low probability table 165a for setting 5 is referenced, the probability of a jackpot result is about 1/280, and when the low probability table 166a for setting 6 is referenced, the probability of a jackpot result is about 1/270. As a result, when the setting state of the pachinko machine 10 is a high setting value, the probability of a jackpot result is more likely to occur in the low probability mode, which is advantageous for the player.

The probability of winning the jackpot set in each of the high probability tables 161b to 166b is different from each other. Specifically, when the high probability table 161b for setting 1 is referenced, the probability of a jackpot result is about 1/45, when the high probability table 162b for setting 2 is referenced, the probability of a jackpot result is about 1/40, when the high probability table 163b for setting 3 is referenced, the probability of a jackpot result is about 1/35, when the high probability table 164b for setting 4 is referenced, the probability of a jackpot result is about 1/30, when the high probability table 165b for setting 5 is referenced, the probability of a jackpot result is about 1/25, and when the high probability table 166b for setting 6 is referenced, the probability of a jackpot result is about 1/20. As a result, when the setting state of the pachinko machine 10 is a high setting value, the probability of a jackpot result is more likely to occur in the high probability mode, which is advantageous for the player.

In other words, in the first embodiment, the probability of winning a jackpot in low probability mode increases the higher the setting value of the pachinko machine 10, while the probability of winning a jackpot in high probability mode is the same regardless of the setting value of "Setting 1" to "Setting 6." In this embodiment, however, the probability of winning a jackpot in low probability mode and the probability of winning a jackpot in high probability mode both increase the higher the setting value of the pachinko machine 10. This makes it possible to increase the advantage of the player in having a high setting value set.

In addition, even the probability of winning a jackpot result in low probability mode in the case of the highest setting state "Setting 6" is set lower than the probability of winning a jackpot result in high probability mode in the case of the lowest setting state "Setting 1". This makes it possible to prevent the player's advantage from becoming extremely low when the pachinko machine 10 is set to "Setting 1", and also makes it possible to prevent the player's advantage from becoming extremely high when the pachinko machine 10 is set to "Setting 6".

On the other hand, as in the first embodiment, only one type of distribution table 64h is provided so that it is common to all settings from "Setting 1" to "Setting 6." This makes it possible to prevent any advantage or disadvantage in the distribution pattern of the jackpot result from being caused by the setting state of the pachinko machine 10, and also makes it possible to reduce the storage capacity required to previously store the distribution table 64h in the main ROM 64.

The probability of winning a jackpot in low probability mode is higher when the setting of the pachinko machine 10 is higher, while the probability of winning a jackpot in high probability mode is lower when the setting of the pachinko machine 10 is higher. In this case, it is possible to make it more advantageous for the player to have a higher setting of the pachinko machine 10 in low probability mode, and more advantageous for the player to have a lower setting of the pachinko machine 10 in high probability mode.

In addition, the probability of winning a jackpot in the high probability mode is higher when the setting state of the pachinko machine 10 is a higher setting value, while the probability of winning a jackpot in the low probability mode may be constant for the setting states of "Setting 1" to "Setting 6." In this case, the higher the setting state of the pachinko machine 10 is in the high probability mode, the more advantageous it is for the player, and in the low probability mode, it is possible to prevent any advantage or disadvantage due to the setting state of the pachinko machine 10.

Third Embodiment
In this embodiment, the handling of the management result of the game history when the setting state of the pachinko machine 10 is newly set is different from the first embodiment. The following describes the configuration that is different from the first embodiment. Note that the description of the same configuration as the first embodiment is basically omitted.

In addition to the memories in the first embodiment, the management IC 66 is provided with a separate storage memory 171 as a memory for storing information. FIG. 34 is an explanatory diagram for explaining the separate storage memory 171. The separate storage memory 171 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain memory, such as a NOR type flash memory or a NAND type flash memory, and is used for both reading and writing.

The separate storage memory 171 is provided with a first separate storage area 172, a second separate storage area 173, a third separate storage area 174, a fourth separate storage area 175, and a fifth separate storage area 176. The first to fifth separate storage areas 172 to 176 sequentially store information on the results of management of the game history calculated when the setting state of the pachinko machine 10 is newly set, more specifically, the various parameters (the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters) described in the first embodiment. In this case, when the setting state of the pachinko machine 10 is newly set, the various parameters are first stored in the first separate storage area 172, and thereafter, the area to be stored is switched so that the nth separate storage area 172 to 176 → the n+1th separate storage area 172 to 176 each time the setting state of the pachinko machine 10 is newly set. Then, if the setting state of the pachinko machine 10 is newly set after the various parameters have been stored in the fifth separate storage area 176, the various parameters are stored again in the first separate storage area 172. At this time, the various parameters already stored in the first separate storage area 172 are erased. As a result, the various parameters up to the time when the setting state of the pachinko machine 10 is newly set five times are stored in the separate storage memory 171, and for parameters exceeding five times, the oldest various parameters are erased and stored.

The various parameters stored in the first to fifth separate storage areas 172 to 176 can be read by an external device by connecting the external device to the reading terminal 68d. This makes it possible to grasp the results of game history management before new settings are made to the pachinko machine 10.

Next, the setting update recognition process in this embodiment executed by the management CPU 112 will be explained with reference to the flowchart in FIG. 35.

When the setting value update signal input to the 15th buffer 122o of the input port 121 switches from a LOW level to a HIGH level (step S1801: YES), the value of the setting value grasp counter in the management RAM 114 is set to "1" (step S1802). The setting value grasp counter is a counter for identifying the setting value of the pachinko machine 10 by the management CPU 112; for example, a setting value grasp counter value of "1" means "setting 1," and a setting value grasp counter value of "6" means "setting 6."

Then, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HIGH level again (step S1803). If a positive determination is made in step S1803, the value of the setting value grasp counter in the management RAM 114 is incremented by 1 (step S1804). This causes the setting value of the pachinko machine 10 identified by the management CPU 112 to increase by one level.

If a negative determination is made in step S1803, or if the processing of step S1804 is executed, it is determined whether or not a set value identification end command has been received from the main CPU 63 based on the input state of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S1805). If a negative determination is made in step S1805, the processing returns to step S1803.

If a positive judgment is made in step S1805, a process for monitoring repeated changes is executed (step S1806). The process for monitoring repeated changes is described in detail below, but executes a process for notifying the user when new settings of the setting state of the pachinko machine 10 are repeatedly made in a short period of time. In a configuration in which various parameters are stored in the separate storage memory 171 each time a new setting of the setting state of the pachinko machine 10 is made, it is expected that new settings of the setting state of the pachinko machine 10 will be repeatedly made in a short period of time in order to intentionally erase the management results of the game history when play has been performed over a predetermined period of time. In response to this, the process for monitoring repeated changes is executed, and a corresponding notification is executed when such an action is taken.

After that, various calculation processes are executed (step S1807). In the various calculation processes, the processes of steps S1402 to S1412 of the display output process (FIG. 30) in the first embodiment are executed. As a result, various parameters (1st to 8th parameters, 11th to 18th parameters, 21st to 26th parameters, 31st parameter, and 41st to 42nd parameters) are calculated using the history information stored in the history memory 117 at that time.

Then, the various parameters calculated in step S1807 are stored in the area currently being stored among the first to fifth separate storage areas 172-176 in the separate storage memory 171 (step S1808). A pointer information area is set in the separate storage memory 171 to enable the management CPU 112 to identify the area currently being stored among the first to fifth separate storage areas 172-176. The information in the pointer information area is updated so that when various parameters are stored in the area currently being stored among the first to fifth separate storage areas 172-176, the storage target is changed to the next area in the order. By executing the process of step S1808, the various parameters at that time are stored in the separate storage memory 171 for the new setting of the current setting state of the pachinko machine 10.

Then, the history memory 117 is cleared to "0" (step S1809). In other words, in this embodiment, the history information in the history memory 117 is erased not only when the history information is read by an external device connected to the reading terminal 68d, but also when the setting state of the pachinko machine 10 is newly set.

Then, RTC information, which is date information and time information, is read from the RTC 115 (step S1810). Then, a write process to the history memory 117 is executed (step S1811). In the write process, the pointer information of the history area 124 currently being written is identified by referring to the pointer area 126 of the history memory 117, and the RTC information read in step S1810 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written. In addition, both information for identifying the setting value and information on the value of the setting value grasp counter are written to the history information storage area 125 corresponding to the pointer information being written. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time when the setting was made, and information on the setting value when the setting was made is stored as history information.

After that, the target pointer is updated (step S1812). In this update, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by one. It is determined whether the pointer information after the increment of one has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after the increment of one is overwritten in the pointer area 126 as the new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

Next, the repeated change monitoring process executed in step S1806 will be explained with reference to the flowchart in FIG. 36.

First, it is determined whether the number of times a game has been played since the setting state of the pachinko machine 10 was last set is within a reference number (specifically, 100 times) (step S1901). Specifically, by counting the number of history information storage areas 125 in which correspondence information indicating the start of a game is stored in the history area 124 of the history memory 117, the number of times a game has been played since the setting state of the pachinko machine 10 was last set is determined, and it is further determined whether the determined number of times a game has been played is within a reference number (specifically, 100 times).

If the result of step S1901 is positive, the value of the repeat change counter provided in the separate storage memory 171 is incremented by 1 (step S1902). As already explained, the separate storage memory 171 is a memory that does not require an external power supply to store data, and therefore does not require an external power supply to store data of the repeat change counter.

Then, it is determined whether the value of the repeat change counter after adding 1 exceeds the notification reference value of "5" (step S1903). The notification reference value corresponds to the number of the first to fifth separate storage areas 172 to 176 provided in the separate storage memory 171. Therefore, in step S1903, it is determined whether the number of times the new settings of the setting state of the pachinko machine 10 have been repeated without the execution of a game play exceeding the reference number of times exceeds the number of the first to fifth separate storage areas 172 to 176.

If the determination in step S1903 is affirmative, a repeat change display process is executed (step S1904). In the repeat change display process, the display contents of the first to third notification display devices 69a to 69c are set to the repeat change display contents corresponding to the number of times that the new setting of the setting state of the pachinko machine 10 has been repeated in a short period of time that exceeds the notification reference value. The repeat change display contents are display contents that display "E" in all of the first to third notification display devices 69a to 69c, and this display content does not occur in other situations. In addition, the state in which the repeat change display contents are displayed in the first to third notification display devices 69a to 69c continues until the repeat change flag provided in the separate storage memory 171 is cleared to "0". The repeat change flag is a flag for the management side CPU 112 to identify that it is a situation in which the repeat change display contents should be displayed in the first to third notification display devices 69a to 69c. Also, if the repeat change flag is set to "1" and the repeat change display content is being displayed on the first to third notification display devices 69a to 69c, the display process (FIG. 31) in the first embodiment is not executed. After that, the repeat change flag in the separate storage memory 171 is set to "1" (step S1905).

If the determination in step S1901 is negative, the value of the repeat change counter in the separate storage memory 171 is cleared to "0" (step S1906). Then, on condition that the repeat change flag in the separate storage memory 171 is set to "1" (step S1907: YES), the display of the repeat change display contents on the first to third notification display devices 69a to 69c is terminated (step S1908), and the repeat change flag is cleared to "0" (step S1909).

The present embodiment described above provides the following excellent advantages:

When a new setting is made to the setting state of the pachinko machine 10, the history information stored in the history memory 117 is erased. This makes it possible to leave in the history memory 117 the history information from games played after a new setting is made to the setting state of the pachinko machine 10.

When a new setting is made to the setting state of the pachinko machine 10, various parameters are calculated as the results of managing the game history using the history information in the history memory 117 at that time. This makes it possible to grasp the results of managing the game history in the situation before the new setting is made to the setting state of the pachinko machine 10. Even if the history information in the history memory 117 is erased when a new setting is made to the setting state of the pachinko machine 10, it is possible to grasp the results of managing the game history based on the history information to be erased.

When a new setting is made in the pachinko machine 10, various parameters are calculated using the history information in the history memory 117 at that time, and the calculated various parameters are stored in the separate storage memory 171. As a result, even if a new setting is made in the pachinko machine 10, it is possible to grasp the management results of the game history in the situation before the setting was made at any time thereafter.

By providing multiple separate storage areas 172-176 in the separate storage memory 171, it is possible to store various parameters corresponding to the setting timing of multiple setting states. This makes it possible to grasp the management results of the game history over multiple periods based on the timing when the setting state was newly set. Furthermore, even if new settings of the setting state of the pachinko machine 10 are repeatedly made in a situation where no game is being played, it is possible to increase the likelihood that various parameters calculated using the history information of a situation where game play is actually being played will remain in the separate storage memory 171.

The various parameters stored in the first to fifth separate storage areas 172 to 176 can be read by an external device by connecting the external device to the reading terminal 68d. This makes it possible to grasp the results of game history management before new settings are made to the pachinko machine 10.

In a configuration in which various parameters are stored in the separate storage memory 171 each time a new setting is made to the setting state of the pachinko machine 10, it is expected that new settings of the setting state of the pachinko machine 10 will be made repeatedly in a short period of time in order to intentionally erase the management results of the game history when play has been performed over a predetermined period of time. In response to this, a process of monitoring repeated changes is executed, and if such an action is taken, a corresponding notification is issued. This makes it possible to notify an administrator or the like that new settings of the setting state of the pachinko machine 10 have been made repeatedly in a short period of time.

The fact that new settings of the pachinko machine 10 have been repeatedly made in a short period of time is notified by the first to third notification display devices 69a to 69c. This makes it possible to notify that new settings of the pachinko machine 10 have been repeatedly made in a short period of time by using the first to third notification display devices 69a to 69c for notifying the results of game history management.

In a situation where a notification should be given that new settings of the pachinko machine 10 have been repeatedly made in a short period of time, the first to third notification display devices 69a to 69c continue to display the repeated changes, and the first to third notification display devices 69a to 69c do not notify the results of the management of the game history during normal times. This makes it possible to emphasize the notification that new settings of the pachinko machine 10 have been repeatedly made in a short period of time.

In the above, a notification corresponding to the event where the number of times the game is played after the new setting of the setting state of the pachinko machine 10 is within a reference number of times exceeds a notification reference value and the event where the new setting is performed continues beyond the notification reference value, but the present invention is not limited to this. A notification corresponding to the event where the total number of game balls discharged from the play area PA after the new setting of the setting state of the pachinko machine 10 is within a reference number and the event where the new setting is performed continues beyond the notification reference value may be configured to be executed. Also, a notification corresponding to the event where the total number of game balls discharged into a predetermined ball entry section (e.g., any one of the outlet 24a, the general winning port 31, the first operating port 33, and the second operating port 34, or a predetermined combination) after the new setting of the setting state of the pachinko machine 10 is within a reference number and the event where the new setting is performed continues beyond the notification reference value may be configured to be executed. In addition, the system may be configured such that, when the total number of pieces of history information newly stored in the history memory 117 after a new setting of the setting state of the pachinko machine 10 is within a reference number, if the number of consecutive events for which the new setting is performed exceeds a notification reference value, a corresponding notification is issued.

In addition, if a new setting of the setting state of the pachinko machine 10 is performed within a monitoring reference period (e.g., 600 seconds) that exceeds the notification reference value, a corresponding notification may be issued.

In addition, in a situation where the number of times a game has been played since a new setting of the setting state of the pachinko machine 10 is made is within a reference number of times, and the number of consecutive times that the new setting is made exceeds a notification reference value, a corresponding notification is executed. However, it may also be configured so that in a situation where the number of times a game has been played since a new setting of the setting state of the pachinko machine 10 is made is within a reference number of times, and the number of consecutive times that the setting value has been changed exceeds a notification reference value, a corresponding notification is executed.

In addition, in a situation where the number of times a game has been played since a new setting of the setting state of the pachinko machine 10 is made is within a reference number of times, a corresponding notification is executed if the number of times that the new setting is made exceeds a notification reference value and the number of times that the new setting is made continues to exceed a notification reference value. However, it may also be configured so that a corresponding notification is executed if the number of times that a game has been played since a new setting of the setting state of the pachinko machine 10 is made is within a reference number of times, and the number of times that the new setting is used to calculate various parameters continues to exceed a notification reference value.

In addition, if the number of times a game has been played since a new setting of the pachinko machine 10 was made is within a reference number of times, and the number of consecutive events in which the new setting is made exceeds a reference value, a corresponding notification is issued. In addition to or instead of this, the progress of play may be restricted for a predetermined period of time (e.g., one hour).

Fourth Embodiment
This embodiment differs from the third embodiment in that the repeated change monitoring process is executed by the main CPU 63. The following describes the configuration that differs from the third embodiment. Note that the description of the same configuration as the third embodiment is basically omitted.

Figure 37 is a flowchart showing the repeat change monitoring process executed by the main CPU 63. The repeat change monitoring process is executed when the setting value update process (step S118) is executed in the main process ( Figure 9 ). In other words, the repeat change monitoring process is executed when the setting state of the pachinko machine 10 is newly set. However, this is not limited to this, and the repeat change monitoring process may be configured to be executed when the setting value is changed.

First, it is determined whether the number of times a game has been played since the setting state of the pachinko machine 10 was last set is within a reference number (specifically, 100 times) (step S2001). The main RAM 65 is provided with a game count counter for measuring the number of times a game has been played since the setting state of the pachinko machine 10 was newly set, and the main CPU 63 adds 1 to the value of the game count counter each time a new game is played. This game count counter is excluded from being cleared to "0" even when the clear process of the main RAM 65 (steps S105, S117) is executed.

If the determination in step S2001 is positive, the value of the repeat change counter provided in the main RAM 65 is incremented by 1 (step S2002). The repeat change counter is excluded from being cleared to "0" even when the clear process of the main RAM 65 (steps S105 and S117) is executed.

Then, it is determined whether the value of the repeat change counter after adding 1 exceeds the notification reference value of "5" (step S2003). The notification reference value corresponds to the number of the first to fifth separate storage areas 172 to 176 provided in the separate storage memory 171. Therefore, in step S2003, it is determined whether the number of times the new settings of the setting state of the pachinko machine 10 have been repeated without the execution of a game play exceeding the reference number of times exceeds the number of the first to fifth separate storage areas 172 to 176.

If a positive judgment is made in step S2003, the repeat change flag stored in the main RAM 65 is set to "1" (step S2004). The repeat change flag is a flag for the main CPU 63 to identify a situation in which a repeat change notification should be made. The repeat change flag is excluded from being cleared to "0" even when the clear process of the main RAM 65 (steps S105, S117) is executed.

If the result of step S2001 is negative, the value of the repeat change counter in the main RAM 65 is cleared to "0" (step S2005). Then, if the repeat change flag in the main RAM 65 is set to "1" (step S2006: YES), the repeat change flag is cleared to "0" (step S2007).

In the repeat change monitoring process, if the repeat change flag in the main RAM 65 is set to "1" (step S2008: YES), a repeat change notification command is sent to the audio and light-emitting control device 81 (step S2009). When the audio and light-emitting control device 81 receives a repeat change notification command, it causes the pattern display device 41, the display light-emitting unit 53, and the speaker unit 54 to notify the repeat change. The repeat change notification continues until the supply of operating power to the audio and light-emitting control device 81 is stopped.

The above configuration makes it possible to notify the user that new settings of the pachinko machine 10 have been repeatedly made in a short period of time based on control by the main CPU 63. In addition, since the notification is made by the pattern display device 41, the display light-emitting unit 53, and the speaker unit 54, it is possible to make the administrator aware that new settings of the pachinko machine 10 have been repeatedly made in a short period of time without having to open the gaming machine main body 12 forward relative to the outer frame 11.

In addition to or instead of a configuration in which a notification command for repeated changes is sent from the main CPU 63 to the sound and light emission control device 81 when new settings of the setting state of the pachinko machine 10 are made repeatedly within a short period of time, a corresponding external output may be provided.

Also, the host CPU 63 may be configured to execute the process of monitoring repeated changes in this embodiment, while the management CPU 112 may be configured to execute the process of monitoring repeated changes in the third embodiment. This makes it possible to closely monitor whether new settings for the setting state of the pachinko machine 10 are repeatedly made within a short period of time.

Fifth embodiment
In this embodiment, the processing configuration of the setting update recognition process in the management CPU 112 is different from that of the third embodiment. The configuration that differs from the third embodiment will be described below. Note that the description of the same configuration as the third embodiment will basically be omitted.

Figure 38 is a flowchart showing the setting update recognition process in this embodiment executed by the management CPU 112.

When the setting value update signal input to the 15th buffer 122o of the input port 121 switches from a LOW level to a HIGH level (step S2101: YES), the value of the setting value grasp counter in the management RAM 114 is set to "1" (step S2102). The setting value grasp counter is a counter for identifying the setting value of the pachinko machine 10 by the management CPU 112; for example, a setting value grasp counter value of "1" means "setting 1," and a setting value grasp counter value of "6" means "setting 6."

Then, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HIGH level again (step S2103). If a positive determination is made in step S2103, the value of the setting value grasp counter in the management RAM 114 is incremented by 1 (step S2104). This causes the setting value of the pachinko machine 10 identified by the management CPU 112 to increase by one level.

If a negative determination is made in step S2103, or if the processing of step S2104 is executed, it is determined whether or not a set value identification end command has been received from the main CPU 63 based on the input state of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S2105). If a negative determination is made in step S2105, the processing returns to step S2103.

If a positive judgment is made in step S2105, it is judged whether or not a predetermined number of predetermined history information pieces exist in the history memory 117 (step S2106). Specifically, by counting the number of history information storage areas 125 in which correspondence information indicating the start of a game is stored in the history area 124 of the history memory 117, the number of game times executed since the setting state of the pachinko machine 10 was last set is grasped, and further, it is judged whether or not the grasped number of game times exceeds a reference number (specifically, 100 times). However, this is not limited to this, and it may be configured to judge in step S2106 whether or not the number of history information storage areas 125 in which correspondence information indicating that a game ball has been discharged from the game area PA is stored exceeds a reference number (specifically, 1000 balls). Also, in step S2106, it may be determined whether the number of history information storage areas 125 in which correspondence information indicating that a game ball has entered a predetermined ball entry portion (for example, any one of the out port 24a, the general winning port 31, the first actuation port 33, and the second actuation port 34, or a predetermined combination) is stored exceeds a reference number (specifically, 1000). Also, in step S2106, it may be determined whether the total number of pieces of history information stored in the history memory 117 exceeds a reference number (specifically, 1000).

In the above, a notification corresponding to the event where the number of times the game is played after the new setting of the setting state of the pachinko machine 10 is within a reference number of times exceeds a notification reference value and the event where the new setting is performed continues beyond the notification reference value, but the present invention is not limited to this. A notification corresponding to the event where the total number of game balls discharged from the play area PA after the new setting of the setting state of the pachinko machine 10 is within a reference number and the event where the new setting is performed continues beyond the notification reference value may be configured to be executed. Also, a notification corresponding to the event where the total number of game balls discharged into a predetermined ball entry section (e.g., any one of the outlet 24a, the general winning port 31, the first operating port 33, and the second operating port 34, or a predetermined combination) after the new setting of the setting state of the pachinko machine 10 is within a reference number and the event where the new setting is performed continues beyond the notification reference value may be configured to be executed. In addition, the system may be configured such that, when the total number of pieces of history information newly stored in the history memory 117 after a new setting of the setting state of the pachinko machine 10 is within a reference number, if the number of consecutive events for which the new setting is performed exceeds a notification reference value, a corresponding notification is issued.

If the determination in step S2106 is positive, various calculation processes are executed (step S2107). In the various calculation processes, the processes in steps S1402 to S1412 of the display output process (FIG. 30) in the first embodiment are executed. As a result, various parameters (1st to 8th parameters, 11th to 18th parameters, 21st to 26th parameters, 31st parameter, and 41st to 42nd parameters) are calculated using the history information stored in the history memory 117 at that time.

Then, the various parameters calculated in step S2107 are stored in the area currently being stored among the first to fifth separate storage areas 172-176 in the separate storage memory 171 (step S2108). A pointer information area is set in the separate storage memory 171 to enable the management CPU 112 to identify the area currently being stored among the first to fifth separate storage areas 172-176. The information in the pointer information area is updated so that when various parameters are stored in the area currently being stored among the first to fifth separate storage areas 172-176, the storage target is changed to the next area in the order. By executing the process of step S2108, the various parameters at that time are stored in the separate storage memory 171 for the new setting of the current setting state of the pachinko machine 10.

If a negative determination is made in step S2106, or if the processing of step S2108 is executed, the history memory 117 is cleared to "0" (step S2109). In other words, in this embodiment, the history information in the history memory 117 is erased not only when the history information is read by an external device connected to the reading terminal 68d, but also when the setting state of the pachinko machine 10 is newly set.

Then, RTC information, which is date information and time information, is read from the RTC 115 (step S2110). Then, a write process to the history memory 117 is executed (step S2111). In the write process, the pointer information of the history area 124 currently being written is identified by referring to the pointer area 126 of the history memory 117, and the RTC information read in step S2110 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written. In addition, both information for identifying the setting value and information on the value of the setting value grasp counter are written to the history information storage area 125 corresponding to the pointer information being written. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time when the setting was made, and information on the setting value when the setting was made is stored as history information.

After that, the target pointer is updated (step S2112). In this update, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by one. It is determined whether the pointer information after the increment of one has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after the increment of one is overwritten in the pointer area 126 as the new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

According to the above configuration, when the setting state of the pachinko machine 10 is newly set, various parameters are calculated using the history information stored in the history memory 117, and the various parameters are stored in the separate storage memory 171, provided that a predetermined number of pieces of history information are stored in the history memory 117. This makes it possible to store information on the management results of the game history as a result of actual play, in the separate storage memory 171, even if new settings of the setting state of the pachinko machine 10 are repeatedly performed in a short period of time.

The processing of step S2109 may be performed on the condition that the processing of steps S2107 and S2108 has been performed. In other words, the history information stored in the history memory 117 is erased on the condition that a predetermined number of pieces of history information or more are stored in the history memory 117. This makes it possible to prevent the history information in the history memory 117 from being erased even if new settings of the setting state of the pachinko machine 10 are repeatedly performed in a short period of time.

Sixth Embodiment
In this embodiment, the configuration of the history memory 117 is different from that of the first embodiment. The configuration that differs from the first embodiment will be described below. Note that the description of the same configuration as the first embodiment will basically be omitted.

Figure 39 is an explanatory diagram for explaining the configuration of the history memory 117 in this embodiment.

The history memory 117 includes a total area 141, a first state area 142, a second state area 143, and a third state area 144. Each of these areas 141 to 144 includes a first to fourteenth counter 141a to 141n, 142a to 142n, 143a to 143n, and 144a to 144n. The first counter 141a to 144a of each of the areas 141 to 144 stores information on the number of times the output state of the first signal input to the first buffer 122a has been changed from a LOW level to a HIGH level. The second counter 141b to 144b of each of the areas 141 to 144 stores information on the number of times the output state of the second signal input to the second buffer 122b has been changed from a LOW level to a HIGH level. The third counters 141c to 144c in each of the areas 141 to 144 store information on the number of times the output state of the third signal input to the third buffer 122c has been changed from a LOW level to a HIGH level. The fourth counters 141d to 144d in each of the areas 141 to 144 store information on the number of times the output state of the fourth signal input to the fourth buffer 122d has been changed from a LOW level to a HIGH level. The fifth counters 141e to 144e in each of the areas 141 to 144 store information on the number of times the output state of the fifth signal input to the fifth buffer 122e has been changed from a LOW level to a HIGH level. The sixth counters 141f to 144f in each of the areas 141 to 144 store information on the number of times the output state of the sixth signal input to the sixth buffer 122f has been changed from a LOW level to a HIGH level. The seventh counters 141g to 144g of each of the areas 141 to 144 store information on the number of times the output state of the seventh signal input to the seventh buffer 122g has been changed from a LOW level to a HIGH level. The eighth counters 141h to 144h of each of the areas 141 to 144 store information on the number of times the output state of the eighth signal input to the eighth buffer 122h has been changed from a LOW level to a HIGH level. The ninth counters 141i to 144i of each of the areas 141 to 144 store information on the number of times the output state of the ninth signal input to the ninth buffer 122i has been changed from a LOW level to a HIGH level. The tenth counters 141j to 144j of each of the areas 141 to 144 store information on the number of times the output state of the tenth signal input to the tenth buffer 122j has been changed from a LOW level to a HIGH level. The eleventh counters 141k to 144k of each of the areas 141 to 144 store information on the number of times the output state of the eleventh signal input to the eleventh buffer 122k has changed from a low level to a high level. The twelfth counters 141l to 144l of each of the areas 141 to 144 store information on the number of times the output state of the twelfth signal input to the twelfth buffer 122l has changed from a low level to a high level. The thirteenth counters 141m to 144m of each of the areas 141 to 144 store information on the number of times the output state of the thirteenth signal input to the thirteenth buffer 122m has changed from a low level to a high level. The fourteenth counters 141n to 144n of each of the areas 141 to 144 store information on the number of times the output state of the fourteenth signal input to the fourteenth buffer 122n has changed from a low level to a high level.

Figure 40 is a flowchart showing the history setting process in this embodiment executed by the management CPU 112.

First, the number of buffers to be checked by the management CPU 112 among the first to fourteenth buffers 122a to 122n is set in the check target counter of the management RAM 114 (step S2201). Specifically, the number of correspondence areas in the correspondence memory 116 among the first to fourteenth correspondence areas 123a to 123n that store information other than information indicating that they are blank is identified, and the information for the identified number is set in the check target counter. In this pachinko machine 10, information other than information indicating that they are blank is stored in the first to eleventh correspondence areas 123a to 123k, so in step S2201 the check target counter is set to "11".

Then, it is determined whether the buffer 122a-122n corresponding to the current counter to be checked is a buffer to which a status information signal is input (step S2202). Specifically, it is determined whether any of the following correspondence information is stored in the correspondence area 123a-123n corresponding to the current value of the counter to be checked: information indicating the open/close execution mode, information indicating the high frequency support mode, or information indicating the front door frame 14.

If the determination in step S2202 is affirmative, a setting process for state information is executed (step S2203). In this setting process, when the output state of the eighth signal indicating whether or not the opening/closing execution mode is in progress is switched from LOW level to HI level, first state information indicating that the opening/closing execution mode is in progress is stored in the management RAM 114, and when the output state of the eighth signal is switched from HI level to LOW level, the first state information is erased from the management RAM 114. In addition, when the output state of the ninth signal indicating whether or not the high frequency support mode is in progress is switched from LOW level to HI level, second state information indicating that the high frequency support mode is in progress is stored in the management RAM 114, and when the output state of the ninth signal is switched from HI level to LOW level, the second state information is erased from the management RAM 114. In addition, when the output state of the 10th signal, which indicates whether the front door frame 14 is open or not, switches from a LOW level to a HIGH level, information on the third state, which indicates that the front door frame 14 is open, is stored in the management RAM 114, and when the output state of the 10th signal switches from a HIGH level to a LOW level, information on the third state is erased from the management RAM 114.

If a negative judgment is made in step S2202, or if the processing of step S2203 is executed, it is judged whether the output state of the input signal from the main CPU 63 to the buffer corresponding to the current value of the counter to be checked among the first to fourteenth buffers 122a to 122n has been switched from a LOW level to a HIGH level by checking whether the numerical information stored in the buffer corresponding to the current value of the counter to be checked among the first to fourteenth buffers 122a to 122n has been changed from "0" to "1" (step S2204). Note that, if the numerical information stored in the eighth buffer 122h has been changed from "0" to "1" in a situation where the current value of the counter to be checked corresponds to the eighth buffer 122h, the information of the first state is stored in the management RAM 114 in step S2203, and an affirmative judgment is made in step S2204. In addition, if the value of the current counter to be checked is a value corresponding to the ninth buffer 122i and the numerical information stored in the ninth buffer 122i is changed from "0" to "1", the second state information is stored in the management RAM 114 in step S2203, and a positive determination is made in step S2204. In addition, if the value of the current counter to be checked is a value corresponding to the tenth buffer 122j and the numerical information stored in the tenth buffer 122j is changed from "0" to "1", the third state information is stored in the management RAM 114 in step S2203, and a positive determination is made in step S2204.

If the determination in step S2204 is positive, an addition process is performed on the corresponding total counter (step S2205). In this addition process, one is added to the value of the counter that corresponds to the current value of the counter to be checked, among the first to fourteenth total counters 141a to 141n in the total area 141 of the history memory 117. For example, if the value of the counter to be checked is "11", the eleventh total counter 141k is added, if the value of the counter to be checked is "5", the fifth total counter 141e is added, and if the value of the counter to be checked is "1", the first total counter 141a is added.

Then, by referring to the state information of the management RAM 114, it is determined whether or not the state is the first state, i.e., whether or not the state is in the open/close execution mode (step S2206). If the state is the first state (step S2206: YES), an increment process is performed on the corresponding counter for the first state (step S2207). In this increment process, one is incremented from the value of the counter corresponding to the current value of the counter to be checked among the first to fourteenth counters 142a to 142n for the first state in the first state area 142 of the history memory 117. For example, if the value of the counter to be checked is "11", the eleventh counter 142k for the first state is the increment target, if the value of the counter to be checked is "5", the fifth counter 142e for the first state is the increment target, and if the value of the counter to be checked is "1", the first counter 142a for the first state is the increment target.

Then, by referring to the state information of the management RAM 114, it is determined whether or not the state is the second state, i.e., whether or not the state is in the high frequency support mode (step S2208). If the state is the second state (step S2208: YES), an increment process is performed on the corresponding counter for the second state (step S2209). In this increment process, one is incremented from the value of the counter corresponding to the current value of the counter to be checked among the first to fourteenth counters 143a to 143n for the second state in the second state area 143 of the history memory 117. For example, if the value of the counter to be checked is "11", the eleventh counter 143k for the second state is the increment target, if the value of the counter to be checked is "5", the fifth counter 143e for the second state is the increment target, and if the value of the counter to be checked is "1", the first counter 143a for the second state is the increment target.

Then, by referring to the state information of the management RAM 114, it is determined whether or not the state is the third state, that is, whether or not the front door frame 14 is open (step S2210). If the state is the third state (step S2210: YES), an increment process is performed on the corresponding counter for the third state (step S2211). In this increment process, one is incremented from the value of the counter corresponding to the current value of the counter to be checked among the first to fourteenth counters 144a to 144n for the third state in the third state area 144 of the history memory 117. For example, if the value of the counter to be checked is "11", the eleventh counter 144k for the third state is the increment target, if the value of the counter to be checked is "5", the fifth counter 144e for the third state is the increment target, and if the value of the counter to be checked is "1", the first counter 144a for the third state is the increment target.

If a negative judgment is made in step S2204, if a negative judgment is made in step S2210, or if the processing of step S2211 is executed, the value of the confirmation target counter in the management RAM 114 is decremented by 1 (step S2212). Then, it is determined whether the value of the confirmation target counter after the decrement is "0" (step S2213). If the value of the confirmation target counter is 1 or greater (step S2213: NO), the processing from step S2202 onwards is executed for the confirmation target corresponding to the new confirmation target counter value.

By executing the history setting process as described above, the number of times game balls enter the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34, the number of times the open/close execution mode has occurred, the number of times the high frequency support mode has occurred, and the number of times a game has occurred are stored as number information, rather than as history information as in the first embodiment above. This makes it possible to reduce the storage capacity required in the history memory 117, compared to a configuration in which each piece of history information is stored individually.

By storing the number of times information instead of history information in this way, there is no need to execute a process to derive the number of times information from the history information when calculating various parameters. This makes it possible to reduce the processing load for calculating various parameters.

Next, the setting update recognition process in this embodiment executed by the management CPU 112 will be explained with reference to the flowchart in FIG. 41.

When the setting value update signal input to the 15th buffer 122o of the input port 121 switches from a LOW level to a HIGH level (step S2301: YES), the value of the setting value grasp counter in the management RAM 114 is set to "1" (step S2302). The setting value grasp counter is a counter for identifying the setting value of the pachinko machine 10 by the management CPU 112; for example, a setting value grasp counter value of "1" means "setting 1," and a setting value grasp counter value of "6" means "setting 6."

Then, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HIGH level again (step S2303). If a positive determination is made in step S2303, the value of the setting value grasp counter in the management RAM 114 is incremented by 1 (step S2304). This causes the setting value of the pachinko machine 10 identified by the management CPU 112 to increase by one level.

If a negative determination is made in step S2303, or if the processing of step S2304 is executed, it is determined whether or not a set value identification end command has been received from the main CPU 63 based on the input state of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S2305). If a negative determination is made in step S2305, the processing returns to step S2303.

If a positive judgment is made in step S2305, the eleventh total counter 141k, which measures the number of times a game has been played in the total area 141 in the history memory 117, the eighth total counter 141h, which measures the number of times the open/close execution mode has occurred in the total area 141 in the history memory 117, and the ninth total counter 141i, which measures the number of times the high frequency support mode has occurred in the total area 141 in the history memory 117, are each cleared to "0" (steps S2306 to S2308). As a result, the number of times a game has been played, the number of times the open/close execution mode has occurred, and the number of times the high frequency support mode has occurred are cleared to "0" in response to the new setting of the setting state of the pachinko machine 10. Therefore, the calculation results of the 31st parameter indicating the number of times the open/close execution mode occurs per unit game, the 41st parameter indicating the number of times the high-frequency support mode occurs per unit game, and the 42nd parameter indicating the ratio of the number of times the high-frequency support mode occurs to the number of times the open/close execution mode occurs correspond to the game content after the setting state of the pachinko machine 10 is newly set. In a configuration in which the probability of winning the jackpot result changes when the setting value of the pachinko machine 10 is changed, by making the calculation results of the 31st parameter, the 41st parameter, and the 42nd parameter correspond to the game content after the setting state of the pachinko machine 10 is newly set as described above, it becomes possible to determine whether the calculation results of the 31st parameter, the 41st parameter, and the 42nd parameter are appropriate based on the current setting value.

On the other hand, even if a new setting is made to the setting state of the pachinko machine 10, counters other than the eighth counter 141h for the total, the ninth counter 141i for the total, and the eleventh counter 141k for the total are not cleared to "0" in the history memory 117. This makes it possible to manage the number of balls entering each history target ball entry section or the frequency of balls entering each section based on the long-term game history, without being affected by the new setting of the setting state of the pachinko machine 10.

According to the above configuration, the number of times game balls enter the outlet 24a, the general winning port 31, the special winning device 32, the first operating port 33, and the second operating port 34, the number of times the open/close execution mode occurs, the number of times the high frequency support mode occurs, and the number of times a game has occurred are stored as number information, rather than as history information as in the first embodiment. This makes it possible to reduce the storage capacity required in the history memory 117, compared to a configuration in which each piece of history information is stored individually.

In addition, because the information is stored as frequency information rather than history information in this way, there is no need to execute a process to derive frequency information from history information when calculating various parameters. This makes it possible to reduce the processing load for calculating various parameters.

The information on the number of times the game is played, the number of times the open/close execution mode occurs, and the number of times the high-frequency support mode occurs is cleared to "0" when the setting state of the pachinko machine 10 is newly set. Therefore, the calculation results of the 31st parameter indicating the number of times the open/close execution mode occurs per unit game, the 41st parameter indicating the number of times the high-frequency support mode occurs per unit game, and the 42nd parameter indicating the ratio of the number of times the high-frequency support mode occurs to the number of times the open/close execution mode occurs correspond to the game content after the setting state of the pachinko machine 10 is newly set. In a configuration in which the probability of winning the jackpot is changed when the setting value of the pachinko machine 10 is changed, by making the calculation results of the 31st parameter, the 41st parameter, and the 42nd parameter correspond to the game content after the setting state of the pachinko machine 10 is newly set as described above, it becomes possible to determine whether the calculation results of the 31st parameter, the 41st parameter, and the 42nd parameter are appropriate based on the current setting value.

On the other hand, even if a new setting is made to the setting state of the pachinko machine 10, counters other than the eighth counter 141h for the total, the ninth counter 141i for the total, and the eleventh counter 141k for the total are not cleared to "0" in the history memory 117. This makes it possible to manage the number of balls entering each history target ball entry section or the frequency of balls entering each section based on the long-term game history, without being affected by the new setting of the setting state of the pachinko machine 10.

The configuration of the history memory 117 as in this embodiment may be applied to the first to fifth embodiments described above and the embodiments described after this embodiment. For example, when applied to the first embodiment, the information in the history memory 117 is maintained as is even if a new setting is made to the setting state of the pachinko machine 10. Also, when applied to the third embodiment, the entire history memory 117 is cleared to "0" when a new setting is made to the setting state of the pachinko machine 10.

In addition, the process of steps S2306 to S2308 may be executed in the setting update recognition process (FIG. 41) when the setting value of the pachinko machine 10 is changed. This makes it possible to clear to "0" the information on the number of times play has been performed, the information on the number of times the open/close execution mode has occurred, and the information on the number of times the high frequency support mode has occurred, even if a new setting has been made to the setting state of the pachinko machine 10, if the setting value has not been changed before and after the setting has been made, and to clear to "0" the information on the number of times play has been performed, the information on the number of times the open/close execution mode has occurred, and the information on the number of times the high frequency support mode has occurred, if the setting value of the pachinko machine 10 has been changed.

Also, in the setting update recognition process (FIG. 41), before the processes of steps S2306 to S2308 are executed, various parameters may be calculated using the counters 141 to 144 in the history memory 117, and the calculated various parameters may be stored in the calculation result memory 131.

Seventh embodiment
In this embodiment, the configuration of the history memory 117 is different from that of the first embodiment. The configuration that differs from the first embodiment will be described below. Note that the description of the same configuration as the first embodiment will basically be omitted.

Figure 42 is an explanatory diagram for explaining the configuration of the history memory 117 in this embodiment.

The history memory 117 includes history memories 181 to 186 corresponding to the setting states of the pachinko machine 10, "setting 1" to "setting 6." Specifically, a history memory 181 for setting 1 is provided in correspondence with "setting 1," a history memory 182 for setting 2 is provided in correspondence with "setting 2," a history memory 183 for setting 3 is provided in correspondence with "setting 3," a history memory 184 for setting 4 is provided in correspondence with "setting 4," a history memory 185 for setting 5 is provided in correspondence with "setting 5," and a history memory 186 for setting 6 is provided in correspondence with "setting 6."

Each of the history memories 181-186 for settings 1-6 is provided with a combination of the history area 124 and the pointer area 126 of the history memory 117 in the first embodiment. This makes it possible to store history information corresponding to each of the setting states of the pachinko machine 10, "setting 1" to "setting 6". In this case, when a new setting of the setting state of the pachinko machine 10 is made, the history memories 181-186 corresponding to the setting value for the new setting are set as the storage target for history information, so it is possible to store history information by setting value without erasing history information when a new setting state of the pachinko machine 10 is made. In addition, various parameters are calculated using history information corresponding to the currently set setting state of the pachinko machine 10, so it is possible to appropriately derive various parameters corresponding to each setting value.

Note that the history memories 181-186 for settings 1-6 may each be configured to contain a combination of the total area 141, first state area 142, second state area 143, and third state area 144 in the sixth embodiment.

Next, the setting update recognition process in this embodiment executed by the management CPU 112 will be explained with reference to the flowchart in FIG. 43.

When the setting value update signal input to the 15th buffer 122o of the input port 121 switches from LOW level to HIGH level (step S2401: YES), the value of the setting value grasp counter provided in the calculation result memory 131 is set to "1" (step S2402). The setting value grasp counter is a counter for identifying the setting value of the pachinko machine 10 by the management side CPU 112. For example, a setting value grasp counter value of "1" means "setting 1", and a setting value grasp counter value of "6" means "setting 6". In this embodiment, the setting value grasp counter is provided in the calculation result memory 131, which is a memory that does not require an external power supply to retain memory, so the value stored in the setting value grasp counter is retained even if the supply of operating power to the management IC 66 is stopped.

Then, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HIGH level again (step S2403). If a positive determination is made in step S2403, the value of the setting value grasp counter in the calculation result memory 131 is incremented by 1 (step S2404). This causes the setting value of the pachinko machine 10 identified by the management CPU 112 to increase by one level.

If a negative determination is made in step S2403, or if the processing of step S2404 is executed, it is determined whether or not a set value identification end command has been received from the main CPU 63 based on the input state of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S2405). If a negative determination is made in step S2405, the processing returns to step S2403.

If the determination in step S2405 is affirmative, the history memories 181 to 186 corresponding to the value of the setting value grasp counter of the calculation result memory 131 are set as the storage target of the history information and the reference target when calculating various parameters (step S2406). Specifically, if the value of the setting value grasp counter is "1", it means that it has been set to "setting 1", so the history memory 181 for setting 1 is set as the storage target of the history information and the reference target when calculating various parameters. Also, if the value of the setting value grasp counter is "2", it means that it has been set to "setting 2", so the history memory 182 for setting 2 is set as the storage target of the history information and the reference target when calculating various parameters. Also, if the value of the setting value grasp counter is "3", it means that it has been set to "setting 3", so the history memory 183 for setting 3 is set as the storage target of the history information and the reference target when calculating various parameters. Furthermore, if the value of the setting value grasp counter is "4", this means that it has been set to "setting 4", so the history memory 184 for setting 4 is set as the storage target for history information and the reference target when calculating various parameters. If the value of the setting value grasp counter is "5", this means that it has been set to "setting 5", so the history memory 185 for setting 5 is set as the storage target for history information and the reference target when calculating various parameters. If the value of the setting value grasp counter is "6", this means that it has been set to "setting 6", so the history memory 186 for setting 6 is set as the storage target for history information and the reference target when calculating various parameters.

Then, RTC information, which is date information and time information, is read from RTC 115 (step S2407). Then, a write process to history memory 117 is executed (step S2408). In this write process, the history memory 181-186 set as the storage target of history information in step S2406 is selected from the history memories 181-186 for settings 1-6. Then, by referring to the pointer area 126 in the history memory 181-186 that is the storage target, the pointer information of the history area 124 that is the current write target is identified, and the RTC information read in step S2407 is written to the history information storage area 125 of the history area 124 that corresponds to the pointer information that is the write target. In addition, information for identifying that it is a setting value is written to the history information storage area 125 that corresponds to the pointer information that is the write target. This causes the combination of information indicating that the setting state of the pachinko machine 10 has been newly set and the RTC information corresponding to the date and time when the setting was made to be stored as history information.

After that, the target pointer is updated (step S2409). In this update, the history memory 181-186 set as the target for storing history information in step S2406 is selected from the history memories 181-186 for settings 1-6, and the numerical information stored in the pointer area 126 of the history memory 181-186 is read and incremented by one. It is determined whether the pointer information after the increment of one has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after the increment of one is overwritten in the pointer area 126 as the new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

According to the above configuration, the history memory 117 is provided with history memories 181-186 for settings 1-6 corresponding to "setting 1"-"setting 6", respectively. This makes it possible to store game history corresponding to each of the setting states of the pachinko machine 10, "setting 1"-"setting 6". In this case, when a new setting is made to the setting state of the pachinko machine 10, the history memories 181-186 corresponding to the setting value for the new setting are set as the storage target for history information, so that it is possible to store history information by setting value without erasing history information when a new setting state of the pachinko machine 10 is made. In addition, various parameters are calculated using history information corresponding to the currently set setting state of the pachinko machine 10, so it is possible to appropriately derive various parameters corresponding to each setting value.

Note that the history memory 117 is not limited to a configuration in which six memories, history memories 181-186 for settings 1-6, are provided, and a configuration in which an area corresponding to history memory 181 for setting 1, an area corresponding to history memory 182 for setting 2, an area corresponding to history memory 183 for setting 3, an area corresponding to history memory 184 for setting 4, an area corresponding to history memory 185 for setting 5, and an area corresponding to history memory 186 for setting 6 are provided for one memory may also be used.

Eighth embodiment
In this embodiment, the configuration of the history memory 117 is different from that of the first embodiment. The configuration that differs from the first embodiment will be described below. Note that the description of the same configuration as the first embodiment will basically be omitted.

Figure 44 is an explanatory diagram for explaining the configuration of the history memory 117 in this embodiment.

The history memory 117 includes a first history memory 191 and a second history memory 192. Each of the first history memory 191 and the second history memory 192 includes a combination of the history area 124 and the pointer area 126 of the history memory 117 in the first embodiment. In this case, when a new setting of the setting state of the pachinko machine 10 is performed in a situation where history information is stored using one of the first history memory 191 and the second history memory 192, the history information in the one history memory 191 and the second history memory 192 can be left without being erased until a predetermined number or more of history information is stored in the other history memory 191 and the second history memory 192, and new history information can be stored in both history memories 191 and the second history memory 192 until a predetermined number or more of history information is stored in the other history memory 191 and the second history memory 192.

Next, the setting update recognition process in this embodiment executed by the management CPU 112 will be explained with reference to the flowchart in FIG. 45.

When the setting value update signal input to the 15th buffer 122o of the input port 121 switches from a LOW level to a HIGH level (step S2501: YES), the value of the setting value grasp counter provided in the management RAM 114 is set to "1" (step S2502). The setting value grasp counter is a counter for identifying the setting value of the pachinko machine 10 by the management CPU 112; for example, a setting value grasp counter value of "1" means "setting 1," and a setting value grasp counter value of "6" means "setting 6."

Then, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HIGH level again (step S2503). If a positive determination is made in step S2503, the value of the setting value grasp counter in the management RAM 114 is incremented by 1 (step S2504). This causes the setting value of the pachinko machine 10 identified by the management CPU 112 to increase by one level.

If a negative determination is made in step S2503, or if the processing of step S2504 is executed, it is determined whether or not a set value identification end command has been received from the main CPU 63 based on the input state of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S2505). If a negative determination is made in step S2505, the processing returns to step S2503.

If the determination in step S2505 is affirmative, the setting change occurrence flag provided in the calculation result memory 131 is set to "1" (step S2506). The setting change occurrence flag is a flag for the management side CPU 112 to identify whether or not, after the setting state of the pachinko machine 10 is newly set, the other history memory 191, 192 is to be used as the storage target for history information in addition to the history memory 191, 192 that was previously set as the storage target for history information among the first history memory 191 and the second history memory 192. In addition, since the setting change occurrence flag is provided in the calculation result memory 131, which is a memory that does not require an external power supply to store the memory, the value stored in the setting change occurrence flag is stored and retained even if the supply of operating power to the management IC 66 is stopped.

Then, RTC information, which is date information and time information, is read from the RTC 115 (step S2507). Then, a write process is executed to each history memory 191, 192 (step S2508). In the write process, the pointer information of the history area 124 currently being written is identified by referring to the pointer area 126 of the first history memory 191, and the RTC information read in step S2507 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written. In addition, both information for identifying the setting value and information on the value of the setting value grasp counter are written to the history information storage area 125 corresponding to the pointer information being written. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time when the setting was made, and information on the setting value when the setting was made is stored as history information in the first history memory 191. In addition, in this write process, the pointer information of the history area 124 currently being written is identified by referring to the pointer area 126 of the second history memory 192, and the RTC information read in step S2507 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written. In addition, both information for identifying the setting value and information on the value of the setting value grasp counter are written to the history information storage area 125 corresponding to the pointer information being written. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time when the setting was made, and information on the setting value when the setting was made is stored as history information in the second history memory 192.

After that, the update process of each target pointer is executed (step S2509). In this update process, first, the numerical information stored in the pointer area 126 of the first history memory 191 is read and 1 is added. It is determined whether the pointer information after the addition of 1 exceeds the maximum value of the pointer information in the history area 124. If the maximum value is not exceeded, the pointer information after the addition of 1 is overwritten in the pointer area 126 as the pointer information to be newly written. If the maximum value is exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information. In addition, in this update process, the numerical information stored in the pointer area 126 of the second history memory 192 is read and 1 is added. It is determined whether the pointer information after the addition of 1 exceeds the maximum value of the pointer information in the history area 124. If the maximum value is not exceeded, the pointer information after the addition of 1 is overwritten in the pointer area 126 as the pointer information to be newly written. If the maximum value is exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

Next, the history setting process in this embodiment executed by the management CPU 112 will be explained with reference to the flowchart in FIG. 46.

If the setting change occurrence flag of the calculation result memory 131 is not set to "1" (step S2601: NO), this means that the history information should be stored only in the first history memory 191 or the second history memory 192 that is the storage target. In this case, the history memories 191 and 192 that are currently the storage targets are identified (step S2602). A storage target flag is provided in the calculation result memory 131, and if the value of the storage target flag is "0", the first history memory 191 is the storage target, and if the value of the storage target flag is "1", the second history memory 192 is the storage target. Note that the storage target flag is provided in the calculation result memory 131, which is a memory that does not require an external power supply to store data, so the value of the storage target flag is stored and retained even if the supply of operating power to the management IC 66 is stopped.

Then, a history setting execution process is executed for the history memories 191, 192 to be stored (step S2603). Specifically, the processes of steps S1101 to S1112 of the history setting process (FIG. 26) in the first embodiment are executed for one of the history memories 191, 192 to be stored. As a result, history information is stored in one of the history memories 191, 192 to be stored.

On the other hand, if the setting change occurrence flag of the calculation result memory 131 is set to "1" (step S2601: YES), it means that the situation is such that history information should be stored not only in the first history memory 191 or the second history memory 192 that is the storage target, but also in the other. In this case, the history setting execution process is executed for both history memories 191, 192 (step S2604). Specifically, first, the process of steps S1101 to S1112 of the history setting process in the first embodiment (FIG. 26) is executed for the first history memory 191. As a result, the history information is stored in the first history memory 191. After that, the process of steps S1101 to S1112 of the history setting process in the first embodiment (FIG. 26) is executed for the second history memory 192. As a result, the history information is stored in the second history memory 192.

When the processing of step S2603 is executed or when the processing of step S2604 is executed, it is determined whether the setting change occurrence flag of the calculation result memory 131 is set to "1" (step S2605). When a positive determination is made in step S2605, it is determined whether or not a predetermined number or more of ball discharge history exists in the non-storage target history memories 191, 192 (step S2606). Specifically, when the value of the storage target flag of the calculation result memory 131 is "0", the first history memory 191 is the storage target, so it is determined whether or not a predetermined number (specifically, "1000") or more of history information indicating that game balls have been discharged from the game area PA is stored in the second history memory 192. Furthermore, when the value of the storage target flag in the calculation result memory 131 is "1", the second history memory 192 is the storage target, so it is determined whether or not a predetermined number (specifically, "1000") or more of history information indicating that a game ball has been discharged from the game area PA is stored in the first history memory 191. Note that, instead of determining whether or not a predetermined number (specifically, "1000") or more of history information indicating that a game round has been played is stored, it may be configured to determine whether or not a predetermined number (specifically, "100") or more of history information indicating that a game round has been played is stored.

If the determination in step S2606 is affirmative, a process for changing the storage target is executed (step S2607). In the process for changing the storage target, the first history memory 191 or the second history memory 192 is changed to be the storage target by setting the value of the storage target flag of the calculation result memory 131 to a value between two values that is different from the current value. Specifically, if the value of the storage target flag is "0", the storage target is changed from the first history memory 191 to the second history memory 192 by setting the storage target flag to "1". Also, if the value of the storage target flag is "1", the storage target is changed from the second history memory 192 to the first history memory 191 by clearing the storage target flag to "0". As a result, the history memories 191 and 192 in which only history information from games executed after the new setting of the setting state of the pachinko machine 10 is performed is set as the storage target. Various parameters are then calculated using the history information in the newly stored history memories 191, 192, making it possible to derive various parameters for games played after the new settings of the pachinko machine 10 have been made.

Then, a clear process is executed for either the first history memory 191 or the second history memory 192, whichever had been the storage target up until that point (step S2608). Specifically, if the value of the storage target flag is "0", the second history memory 192 is cleared to "0", and if the value of the storage target flag is "1", the first history memory 191 is cleared to "0". Then, the setting change occurrence flag of the calculation result memory 131 is cleared to "0" (step S2609).

Next, the display output process in this embodiment executed by the management CPU 112 will be explained with reference to the flowchart in FIG. 47.

If it is the calculation timing (step S2701: YES), the first history memory 191 or the second history memory 192 to be stored is identified (step S2702). Specifically, if the value of the storage target flag of the calculation result memory 131 is "0", the first history memory 191 is identified as the storage target, and if the value of the storage target flag is "1", the second history memory 192 is identified as the storage target. Then, by using the history information stored in the history memories 191 and 192 to be stored identified in step S2702, steps S1402 to S1412 of the display output process (FIG. 30) in the first embodiment are executed to calculate various parameters (1st to 8th parameters, 11th to 18th parameters, 21st to 26th parameters, 31st parameter, 41st to 42nd parameters), and the calculated various parameters are stored in the calculation result memory 131 (step S2703). In this case, even if the setting change occurrence flag in the calculation result memory 131 is set to "1" and history information is stored in both the first history memory 191 and the second history memory 192, various parameters are calculated using one of the history memories 191, 192 that is the storage target.

If a negative determination is made in step S2701, or if the processing of step S2703 is executed, display processing is executed (step S2704). The processing content of the display processing is the same as the display processing in the first embodiment described above (FIG. 31).

According to the above configuration, the first history memory 191 and the second history memory 192 are provided as the history memory 117, and when a new setting is made to the setting state of the pachinko machine 10, the history memories 191 and 192 that had been the storage targets are still the storage targets, while history information is also stored in the history memories 191 and 192 that are not the storage targets. Then, when a predetermined number or more of history information corresponding to the discharge of game balls from the play area PA is stored in the history memories 191 and 192 that are not the storage targets, the history memories 191 and 192 that are not the storage targets are still the storage targets, and the history memories 191 and 192 that were the storage targets are cleared to "0". As a result, when a new setting is made to the setting state of the pachinko machine 10, it is possible to calculate various parameters using only the history information of the games played at the newly set setting values.

On the other hand, according to the above configuration, even if the settings of the pachinko machine 10 are repeatedly changed in a short period of time to prevent the calculation of various parameters from being performed appropriately, the history memories 191, 192 to be stored are maintained without being changed. This makes it possible to properly derive the management results of the game history up to that point, even if the settings of the pachinko machine 10 are repeatedly changed in a short period of time.

The history memory 117 is not limited to a configuration in which two memories, a first history memory 191 and a second history memory 192, are provided, and a configuration in which a first history area corresponding to the first history memory 191 and a second history area corresponding to the second history memory 192 are provided for one memory may also be used.

Also, a configuration may be provided in which only one history memory 117 is provided. In this case, when the total number of game balls discharged from the game area PA after the new setting of the setting state of the pachinko machine 10 is reached or exceeds a predetermined number, the history information before the timing when the new setting of the setting state of the pachinko machine 10 is erased, and the history information after the timing when the setting is made is stored without being erased. This makes it possible to erase the history information before the timing when the new setting of the setting state of the pachinko machine 10 is made at the timing when a predetermined number of history information or more is accumulated after the new setting of the setting state of the pachinko machine 10. Also, by storing the history information corresponding to the new setting of the setting state of the pachinko machine 10 in the history memory 117 at the time when the new setting of the setting state is made, it becomes possible to distinguish the history information before the time when the new setting of the setting state is made from the history information after the new setting in the history memory 117.

The timing for erasing the history information is not limited to when the total number of game balls discharged from the game area PA becomes equal to or exceeds a predetermined number after the setting state of the pachinko machine 10 is newly set, but may be when the number of game plays executed becomes equal to or exceeds a predetermined number after the setting state of the pachinko machine 10 is newly set.

In addition, even if a new setting is made to the setting state of the pachinko machine 10, if the setting value has not been changed before and after the setting, the history memories 191, 192 to be stored as described above will not be changed and the history information will not be erased. However, if a new setting is made to the setting state of the pachinko machine 10 and the setting value has been changed before and after the setting, the history memories 191, 192 to be stored as described above will be changed and the history information will be erased.

Ninth embodiment
In this embodiment, the type of buffers for which the type of input signal is determined in the design stage of the management IC 66 among the first to sixteenth buffers 122a to 122p of the input port 121 in the management I/F 111 differs from that of the first embodiment. Also, the processing configuration executed by the main CPU 63 to cause the management CPU 112 to identify the type of input signal differs from that of the first embodiment. The configurations that differ from the first embodiment will be described below. Note that descriptions of the same configurations as the first embodiment will basically be omitted.

Figure 48 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I/F 111 in this embodiment.

The first to seventh buffers 122a to 122g and the sixteenth buffer 122p receive the same types of signals as in the first embodiment above. In detail, the first buffer 122a receives a first signal corresponding to the detection result of the first winning opening detection sensor 42a, the second buffer 122b receives a second signal corresponding to the detection result of the second winning opening detection sensor 43a, the third buffer 122c receives a third signal corresponding to the detection result of the third winning opening detection sensor 44a, the fourth buffer 122d receives a fourth signal corresponding to the detection result of the special electric detection sensor 45a, the fifth buffer 122e receives a fifth signal corresponding to the detection result of the first operating opening detection sensor 46a, the sixth buffer 122f receives a sixth signal corresponding to the detection result of the second operating opening detection sensor 47a, the seventh buffer 122g receives a seventh signal corresponding to the detection result of the outlet detection sensor 48a, and the sixteenth buffer 122p receives an output instruction signal.

On the other hand, in the first embodiment described above, a signal corresponding to the opening/closing execution mode is input as the eighth signal to the eighth buffer 122h, a signal corresponding to the high frequency support mode is input as the ninth signal to the ninth buffer 122i, a signal corresponding to the front door frame 14 is input as the tenth signal to the tenth buffer 122j, a signal corresponding to the start of a game round is input as the eleventh signal to the eleventh buffer 122k, and a setting value update signal is input to the fifteenth buffer 122o, but in this embodiment, the buffers to which these signals are input are different. Specifically, a signal corresponding to the start of a game round is input to the 11th buffer 122k as a game round signal, a setting value update signal is input to the 12th buffer 122l, a signal corresponding to the open/close execution mode is input to the 13th buffer 122m as an open/close execution mode in progress signal, a signal corresponding to the high frequency support mode is input to the 14th buffer 122n as a high frequency support mode in progress signal, and a signal corresponding to the front door frame 14 is input to the 15th buffer 122o as a door open signal.

The input of a game signal to the 11th buffer 122k, the input of a set value update signal to the 12th buffer 122l, the input of an open/close execution mode signal to the 13th buffer 122m, the input of a high frequency support mode signal to the 14th buffer 122n, the input of a door open signal to the 15th buffer 122o, and the input of an output instruction signal to the 16th buffer 122p were determined during the design stage of the management IC 66, and the management CPU 112 can specify that the above-mentioned signals corresponding to the 11th to 16th buffers 122k to 122p are input without receiving instructions from the main CPU 63. On the other hand, the type of signals input to the 1st to 10th buffers 122a to 122j was not determined during the design stage of the management IC 66, and the types of these signals are specified by the management CPU 112 upon receiving instructions from the main CPU 63. The process for identifying the type of signal is executed when the supply of operating power to the main CPU 63 and the management CPU 112 starts, as in the first embodiment.

Figure 49 is a flowchart showing the recognition process of this embodiment executed by the main CPU 63. Note that the recognition process is executed in step S111 of the main process (Figure 9) as in the first embodiment.

First, the recognition output counter in the main RAM 65 is set to "10", which is the number of the first to tenth buffers 122a to 122j that are to be recognized for the signal type (step S2801). Then, output processing of the identification start signal is executed (step S2802). In this output processing, the output states of the first signal input to the first buffer 122a, the open/close execution mode signal input to the thirteenth buffer 122m, and the high frequency support mode signal input to the fourteenth buffer 122n are set to a HI level, thereby starting output of the identification start signal. The period for which these signals are maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output states of these signals.

Then, the information on the number of outputs corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64, and the read information on the number of outputs is set in the output count counter provided in the main RAM 65 (step S2803). The output count counter is a counter for the main CPU 63 to identify the number of times the type identification signal has been output.

In this embodiment, when the management CPU 112 is made to recognize the type of signal input to the first buffer 122a to the tenth buffer 122j, a type identification signal is output the same number of times as the number of prize balls set for the ball entry section corresponding to that type of signal. The management CPU 112 stores information corresponding to the number of times the type identification signal has been received for each of the first buffer 122a to the tenth buffer 122j in the first to tenth correspondence areas 123a to 123j of the correspondence memory 116. In other words, the type of signal input to the first buffer 122a to the tenth buffer 122j is understood as the number of prize balls set for the ball entry section corresponding to that type of signal.

In step S2803, if the value of the recognition output counter is any of "10", "9" and "8", the output count counter is set to "10" corresponding to the number of prize balls in the general winning port 31. If the value of the recognition output counter is "7", the output count counter is set to "15" corresponding to the number of prize balls in the special winning device 32. If the value of the recognition output counter is "6", the output count counter is set to "1" corresponding to the number of prize balls in the first operating port 33. If the value of the recognition output counter is "5", the output count counter is set to "1" corresponding to the number of prize balls in the second operating port 34. If the value of the recognition output counter is "4", the output count counter is set to "0" since the output counter corresponds to the outlet 24a but the payout of the game balls is not executed even if the game ball enters the outlet 24a. Also, if the value of the recognition output counter is between "3" and "1," there is no corresponding ball entry section and it is blank, so the output count counter is set to "0."

After that, the output process of the start trigger signal is executed (step S2804). In this output process, the output state of the first signal input to the first buffer 122a is set to a HI level, thereby starting the output of the start trigger signal. The period during which the first signal is maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the first signal.

Then, on condition that the value of the output count counter in the main RAM 65 is not "0" (step S2805: YES), i.e., on condition that a value of 1 or more was set in the output count counter in step S2803, the process proceeds to step S2806. In step S2806, output processing of a type identification signal is executed. In this output processing, the output state of the second signal input to the second buffer 122b is set to a HI level, thereby starting output of the type identification signal. The period during which the second signal is maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the second signal.

Then, the value of the output count counter in the main RAM 65 is decremented by 1 (step S2807), and it is determined whether the value of the output count counter after decrement is "0" (step S2808). If the value of the output count counter is 1 or more (step S2808: NO), the process returns to step S2806.

If a positive judgment is made in step S2805, or if a positive judgment is made in step S2808, output processing of the end trigger signal is executed (step S2809). In this output processing, the output state of the third signal input to the third buffer 122c is set to a HI level, thereby starting output of the end trigger signal. The period during which the third signal is maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the third signal.

Then, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S2810), and it is determined whether the value of the recognition output counter after the decrement is "0" (step S2811). If the value of the recognition output counter is 1 or greater (step S2811: NO), the process returns to step S2803, and processing is performed to recognize the type of signal corresponding to the value of the recognition output counter after the decrement.

On the other hand, if the value of the recognition output counter is "0" (step S2811: YES), output processing of the identification end signal is executed (step S2812). In this output processing, the output states of the third signal input to the third buffer 122c, the open/close execution mode signal input to the thirteenth buffer 122m, and the high frequency support mode signal input to the fourteenth buffer 122n are set to a HI level, thereby starting output of the identification end signal. The period during which these signals are maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output states of these signals.

Next, the management process in this embodiment executed by the management CPU 112 will be described with reference to the flowchart in FIG. 50. The management process starts when the supply of operating power to the management CPU 112 starts, as in the first embodiment.

First, it is determined whether reception of the identification start signal from the main CPU 63 has ended (step S2901). If the identification start signal has not been received, the process for setting update recognition is executed in step S2902, and then the process of step S2901 is executed again. The process content of the process for setting update recognition is the same as that of the first embodiment described above.

When reception of the identification start signal from the main CPU 63 has ended (step S2901: YES), the value of the setting target counter in the management RAM 114 is cleared to "0" (step S2903). Thereafter, on the condition that a start trigger signal has been received from the main CPU 63 (step S2904: YES), the process proceeds to step S2905. In step S2905, it is determined whether a type identification signal has been received from the main CPU 63. When a type identification signal has been received (step S2905: YES), the value of the reception count counter provided in the management RAM 114 is incremented by 1 (step S2906). The reception count counter is a counter for the management CPU 112 to identify the number of times the type identification signal has been received from the main CPU 63. The value of the reception count counter is cleared to "0" when a positive determination is made in step S2904.

If a negative judgment is made in step S2905, or if the processing of step S2906 is executed, it is judged whether or not a termination trigger signal has been received from the main CPU 63 (step S2907). If a termination trigger signal has not been received (step S2907: NO), the process returns to step S2905. If a termination trigger signal has been received (step S2907: YES), the correspondence setting process is executed (step S2908). In the correspondence setting process, the value set in the reception count counter is stored in the correspondence area corresponding to the current value of the setting target counter in the management RAM 114, among the first to tenth correspondence areas 123a to 123j of the correspondence memory 116. In this case, the first correspondence area 123a, the second correspondence area 123b, and the third correspondence area 123c are set to "10" corresponding to the number of prize balls in the general winning port 31, the fourth correspondence area 123d is set to "15" corresponding to the number of prize balls in the special winning device 32, the fifth correspondence area 123e is set to "1" corresponding to the number of prize balls in the first operating port 33, and the sixth correspondence area 123f is set to "1" corresponding to the number of prize balls in the second operating port 34. In addition, the seventh to twelfth correspondence areas 123g to 123l are set to "0". After that, the value of the setting target counter in the management side RAM 114 is incremented by 1 (step S2909).

If a negative judgment is made in step S2904, or if the processing of step S2909 is executed, it is judged whether or not reception of the identification end signal from the main CPU 63 has ended (step S2910). If reception of the identification end signal has not ended (step S2910: NO), the process returns to step S2904, and, on the condition that a start trigger signal is received from the main CPU 63 (step S2904: YES), the processing of steps S2905 and onward is executed. If reception of the identification end signal from the main CPU 63 has ended (step S2910: YES), the history setting processing of step S2911, the display output processing of step S2912, and the external output processing of step S2913 are repeatedly executed.

Figure 51 is a time chart showing how information on the correspondence between the first to tenth buffers 122a to 122j and the types of signals input to these buffers 122a to 122j is stored in the correspondence memory 116. FIG. 51(a) shows a period during which the output state of the first signal is at a HI level, FIG. 51(b) shows a period during which the output state of the second signal is at a HI level, FIG. 51(c) shows a period during which the output state of the third signal is at a HI level, FIG. 51(d) shows a period during which the output state of the open/close execution mode signal is at a HI level, FIG. 51(e) shows a period during which the output state of the high frequency support mode signal is at a HI level, FIG. 51(f) shows an execution period of an identification state during which a process is executed to identify the correspondence between the first to tenth buffers 122a to 122j and the types of signals input to these buffers 122a to 122j, FIG. 51(g) shows the timing at which the value of the reception counter in the management RAM 114 is incremented by 1, and FIG. 51(h) shows the timing at which the correspondence setting process (step S2908) is executed by the management CPU 112.

When the supply of operating power to the main CPU 63 and the management CPU 112 is started, the output states of the first signal, the open/close execution mode signal, and the high-frequency support mode signal are changed from LOW level to HI level at the timing of t1 as shown in Figures 51(a), 51(d), and 51(e). This starts the output of the identification start signal from the main CPU 63 to the management CPU 112. Then, at the timing of t2, the output states of the first signal, the open/close execution mode signal, and the high-frequency support mode signal are changed from HI level to LOW level. This stops the output of the identification start signal from the main CPU 63 to the management CPU 112. At the timing of t2, the management CPU 112 makes a positive determination in step S2901 of the management process (Figure 50), and enters the identification state as shown in Figure 51(f).

After that, the output state of the first signal is maintained at a HI level from time t3 to time t4 as shown in FIG. 51(a). This results in a state in which a start trigger signal has been output to the management CPU 112. Then, the output state of the second signal is maintained at a HI level from time t5 to time t7 as shown in FIG. 51(b). This results in a state in which a type identification signal has been output once to the management CPU 112. In this case, at time t6, the value of the reception count counter in the management RAM 114 is incremented by 1 as shown in FIG. 51(g).

After that, the output state of the third signal is maintained at HI level from timing t8 to timing t10 as shown in FIG. 51(c). This results in a state in which a termination trigger signal is output to the management CPU 112. In this case, at timing t9, the management CPU 112 executes a correspondence setting process as shown in FIG. 51(h). Since the value of the reception count counter is "1" when the correspondence setting process is executed, the information "1" is stored as the correspondence information in the correspondence areas 123a to 123j of the current setting target in the correspondence memory 116.

After that, the output state of the first signal is maintained at HI level from timing t11 to timing t12 as shown in FIG. 51(a). This results in a state in which a start trigger signal is output to the management CPU 112. Then, the output state of the second signal is maintained at HI level from timing t13 to timing t15, from timing t16 to timing t18, from timing t19 to timing t21, and from timing t22 to timing t24 as shown in FIG. 51(b). This results in a state in which a type identification signal has been output once to the management CPU 112. In this case, the value of the reception counter in the management RAM 114 is incremented by 1 at timing t14, timing t17, timing t20, and timing t23 as shown in FIG. 51(g).

After that, the output state of the third signal is maintained at HI level from timing t25 to timing t27 as shown in FIG. 51(c). This results in a state in which a termination trigger signal is output to the management CPU 112. In this case, at timing t26, the management CPU 112 executes a correspondence setting process as shown in FIG. 51(h). Since the value of the reception count counter is "10" when the correspondence setting process is executed, the information "10" is stored as the correspondence information in the correspondence areas 123a to 123j of the current setting target in the correspondence memory 116.

After that, at the timing of t28, as shown in FIG. 51(c), FIG. 51(d), and FIG. 51(e), the output states of the third signal, the open/close execution mode signal, and the high-frequency support mode signal are changed from LOW level to HI level. This starts the output of the identification end signal from the main CPU 63 to the management CPU 112. After that, at the timing of t29, the output states of the third signal, the open/close execution mode signal, and the high-frequency support mode signal are changed from HI level to LOW level. This stops the output of the identification end signal from the main CPU 63 to the management CPU 112. At the timing of t29, the management CPU 112 makes a positive determination in step S2910 of the management process (FIG. 50), and the identification state is released as shown in FIG. 51(f).

In this embodiment, since the information on the number of prize balls is stored as the correspondence information, the history information stored in the history memory 117 includes the information on the number of prize balls corresponding to the ball entry part that triggered the storage of the history information as the correspondence information. In this configuration, if there are multiple ball entry parts with the same number of prize balls, the ball entry parts cannot be distinguished in the history information. Specifically, since the first actuation port 33 and the second actuation port 34 both have one prize ball, the first actuation port 33 and the second actuation port 34 cannot be distinguished in the history information. In such circumstances, the number of prize balls in the first actuation port 33 and the second actuation port 34 may be made different. As a result, even in a configuration in which history information is stored as in this embodiment, it is possible to distinguish the first actuation port 33 and the second actuation port 34 in the history information.

According to the embodiment described above in detail, not only the setting value update signal and the output instruction signal, but also the information corresponding to whether a game has started, the information corresponding to whether the opening/closing execution mode is in, the information corresponding to whether the high frequency support mode is in, and the information corresponding to whether the front door frame 14 is open can be identified by the management CPU 112 as the signal path corresponding to these information without receiving the correspondence information from the main CPU 63. In this case, only the information corresponding to the detection results of each ball entry detection sensor 42a to 48a is the information that the main CPU 63 needs to make the management CPU 112 recognize the correspondence between each information and each signal path 118a to 118j. Then, when the correspondence information is made to the management CPU 112, the number of pulse signals equal to the number of winning balls corresponding to each ball entry detection sensor 42a to 48a is output from the main CPU 63 to the management CPU 112 using the second signal. This makes it possible to simplify the configuration for transmitting the correspondence information.

Tenth embodiment
In this embodiment, the configuration for providing the information of each shot result to the management IC 66 is different from that of the first embodiment. The configuration that differs from the first embodiment will be described below. Note that the description of the same configuration as the first embodiment will be basically omitted.

Figure 52 is an explanatory diagram showing the configuration of the signal path for inputting the detection results of each ball entry detection sensor 42a to 48a to the main CPU 63 and the management IC 66.

The detection result of the first winning port detection sensor 42a is input to the main CPU 63 through the first signal path SL11. The detection result of the second winning port detection sensor 43a is input to the main CPU 63 through the second signal path SL12. The detection result of the third winning port detection sensor 44a is input to the main CPU 63 through the third signal path SL13. The detection result of the special electric current detection sensor 45a is input to the main CPU 63 through the fourth signal path SL14. The detection result of the first operating port detection sensor 46a is input to the main CPU 63 through the fifth signal path SL15. The detection result of the second operating port detection sensor 47a is input to the main CPU 63 through the sixth signal path SL16. The detection result of the outlet detection sensor 48a is input to the main CPU 63 through the seventh signal path SL17.

The first branch path SL21 is formed by branching from the middle of the first signal path SL11, and the first branch path SL21 is electrically connected to the management IC 66. The second branch path SL22 is formed by branching from the middle of the second signal path SL12, and the second branch path SL22 is electrically connected to the management IC 66. The third branch path SL23 is formed by branching from the middle of the third signal path SL13, and the third branch path SL23 is electrically connected to the management IC 66. The fourth branch path SL24 is formed by branching from the middle of the fourth signal path SL14, and the fourth branch path SL24 is electrically connected to the management IC 66. The fifth branch path SL25 is formed by branching from the middle of the fifth signal path SL15, and the fifth branch path SL25 is electrically connected to the management IC 66. In addition, a sixth branch path SL26 is formed by branching off from a midpoint of the sixth signal path SL16, and the sixth branch path SL26 is electrically connected to the management IC 66. In addition, a seventh branch path SL27 is formed by branching off from a midpoint of the seventh signal path SL17, and the seventh branch path SL27 is electrically connected to the management IC 66.

With the above configuration, the detection results of each ball entry detection sensor 42a to 48a are input to the management IC 66 without the intervention of processing by the main CPU 63. This eliminates the need for the main CPU 63 to execute processing to make the management CPU 112 recognize the results of each ball entry at the outlet 24a, general winning port 31, special electric winning device 32, first operating port 33, and second operating port 34, making it possible to reduce the processing load on the main CPU 63.

In addition, the branching points of each of the branching paths SL21 to SL27 from each of the signal paths SL11 to SL17 are located inside the MPU 62. This makes it difficult to access the branching points and each of the branching paths SL21 to SL27 from outside, and makes it possible to prevent fraudulent acts such as inputting abnormal ball-scoring results only to the management IC 66.

Eleventh embodiment
In this embodiment, the configuration of the display device for displaying the results of the game history management is different from that of the first embodiment. The configuration that differs from the first embodiment will be described below. Note that the description of the same configuration as the first embodiment will basically be omitted.

Figure 53 is a front view of the main control device 60 in this embodiment.

In the first embodiment, the main control device 60 was provided with a first notification display device 69a, a second notification display device 69b, and a third notification display device 69c, but in this embodiment, a first notification display device 201, a second notification display device 202, a third notification display device 203, and a fourth notification display device 204 are provided. These first to fourth notification display devices 201 to 204 are arranged side by side on the element mounting surface of the main control board 61.

The first to fourth alarm display devices 201-204 are all segment displays in which seven LED display segments are arranged, but are not limited to this and may be a single light-emitting body of a multi-color type, a liquid crystal display device, or an organic EL display. The first to fourth alarm display devices 201-204 are all installed so that their display surfaces face the direction in which the element mounting surface of the main control board 61 faces, and are covered by the opposing wall portion 60b of the board box 60a. In this case, since the board box 60a is formed transparent, it is possible to visually observe the display surfaces of the first to fourth alarm display devices 201-204 housed within the board box 60a from outside the board box 60a. In addition, the main control device 60 is mounted on the back surface of the resin base 21 so that the opposing wall portion 60b, which faces the element mounting surface of the main control board 61 in the board box 60a, faces the rear of the pachinko machine 10. Therefore, when the gaming machine main body 12 is opened toward the front of the pachinko machine 10 relative to the outer frame 11 and the rear surface of the resin base 21 is exposed toward the front of the pachinko machine 10, it becomes possible to visually observe the display surfaces of the first to fourth notification display devices 201 to 204 through the opposing wall portion 60b.

The display surface of the first notification display device 201 displays alphabets such as "A", "E", "H", "L", and "O". On the other hand, the second notification display device 202, the third notification display device 203, and the fourth notification display device 204 display numbers in the range of "0" to "9". The first to fourth notification display devices 201 to 204 are used to notify the results of game history management. In this case, the first notification display device 201 and the second notification display device 202 display information corresponding to the type of game history management result to be notified (the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameters, and the forty-first to forty-second parameters in the first embodiment), and the third notification display device 203 and the fourth notification display device 204 display information corresponding to the content of the game history management result of the type to be notified.

In detail, the types of the game history management results in the first embodiment include the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameters, and the forty-first to forty-second parameters. The first notification display device 201 displays a display corresponding to the type of the parameter group to be notified. Specifically, if any of the first to eighth parameters are to be notified, the first notification display device 201 displays "A", if any of the eleventh to eighteenth parameters are to be notified, the first notification display device 201 displays "E", if any of the twenty-first to twenty-sixth parameters are to be notified, the first notification display device 201 displays "H", if any of the thirty-first parameters are to be notified, the first notification display device 201 displays "L", and if the forty-first to forty-second parameters are to be notified, the first notification display device 201 displays "O".

The second notification display device 202 displays the order of the game history management results for the parameter group being notified, in a sequence that corresponds to the type of game history management result being notified. Taking the parameter group of parameters 1 to 8 as an example, when the first parameter is the subject of notification, a "1" is displayed on the second notification display device 202, when the second parameter is the subject of notification, a "2" is displayed on the second notification display device 202, when the third parameter is the subject of notification, a "3" is displayed on the second notification display device 202, when the fourth parameter is the subject of notification, a "4" is displayed on the second notification display device 202, when the fifth parameter is the subject of notification, a "5" is displayed on the second notification display device 202, when the sixth parameter is the subject of notification, a "6" is displayed on the second notification display device 202, when the seventh parameter is the subject of notification, a "7" is displayed on the second notification display device 202, and when the eighth parameter is the subject of notification, an "8" is displayed on the second notification display device 202. In addition, taking the parameter group of parameters 21 to 26 as an example, if the 21st parameter is the subject of notification, the second notification display device 202 displays "1", if the 22nd parameter is the subject of notification, the second notification display device 202 displays "2", if the 23rd parameter is the subject of notification, the second notification display device 202 displays "3", if the 24th parameter is the subject of notification, the second notification display device 202 displays "4", if the 25th parameter is the subject of notification, the second notification display device 202 displays "5", and if the 26th parameter is the subject of notification, the second notification display device 202 displays "6".

With regard to the display contents of the third notification display device 203 and the fourth notification display device 204 in detail, the parameter to be notified is multiplied by 100, and the number corresponding to the tens digit of the value is displayed on the third notification display device 203, and the number corresponding to the ones digit is displayed on the fourth notification display device 204.

In the first to fourth display devices 201 to 204, the displays corresponding to the calculation results of the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters are switched in sequence in a predetermined order, and after the calculation result of the forty-second parameter, which is the last parameter to be displayed, is displayed, the calculation result of the first parameter, which is the first parameter to be displayed. In this case, the period during which the calculation result of one parameter is continuously displayed is two seconds. In contrast, the calculation cycle of the various parameters in the management CPU 112 is 51 seconds, and the number of various parameters is 25. Therefore, the various parameters calculated by the management CPU 112 become the subject of notification in the first to fourth display devices 201 to 202 at least once.

As in the first embodiment, the first to fourth notification display devices 201 to 204 not only notify the results of the game history management, but also display a value corresponding to the current setting value in a changeable state in which the setting state of the pachinko machine 10 can be changed. Specifically, in the changeable state, the first to third notification display devices 201 to 203 are turned off, while the fourth notification display device 204, which is located at the right end of the first to fourth notification display devices 204 arranged horizontally, displays a value corresponding to the current setting value. In other words, when "Setting 1" is selected in the changeable state, "1" is displayed on the fourth alert display device 204, when "Setting 2" is selected in the changeable state, "2" is displayed on the fourth alert display device 204, when "Setting 3" is selected in the changeable state, "3" is displayed on the fourth alert display device 204, when "Setting 4" is selected in the changeable state, "4" is displayed on the fourth alert display device 204, when "Setting 5" is selected in the changeable state, "5" is displayed on the fourth alert display device 204, and when "Setting 6" is selected in the changeable state, "6" is displayed on the fourth alert display device 204.

Next, the electrical configuration for performing various displays on the first to fourth alarm display devices 201 to 204 based on the control of the MPU 62 will be described. FIG. 54 is a block diagram for explaining the electrical configuration for performing various displays on the first to fourth alarm display devices 201 to 204 based on the control of the MPU 62.

As already explained, the main control board 61 is provided with an MPU 62 and the first to fourth notification display devices 201 to 204. The main control board 61 is also provided with a first display IC 205, a second display IC 206, a third display IC 207, and a fourth display IC 208.

The first display IC 205 is provided in correspondence with the first alarm display device 201, and is electrically connected to the MPU 62 via signal path SL31 and to the first alarm display device 201 via signal path SL32. The first display IC 205 is provided with a storage buffer for storing display data received from the MPU 62, and performs display control of the first alarm display device 201, i.e., light emission control of each display segment, according to the display data stored in the storage buffer. When operating power is supplied, the first display IC 205 can store and hold the display data stored in the storage buffer, and causes the first alarm display device 201 to continuously display the display content corresponding to the stored display data. Then, when the display data is changed by the MPU 62, the display of the first alarm display device 201 is changed to the display content corresponding to the changed display data. In addition, after the supply of operating power to the first display IC 205 has started and the display data has not yet been set by the MPU 62, the display data will be all "0" data, in which case the first notification display device 201 will be in a non-display state, i.e., turned off.

However, this is not limited to the above configuration, and the first display IC 205 may be configured to store and hold display data even when the supply of operating power to the pachinko machine 10 is stopped by supplying backup power to the first display IC 205. In this case, when the supply of operating power to the pachinko machine 10 is started, the display that was being performed on the first notification display device 201 immediately before the supply of operating power to the pachinko machine 10 was stopped will be started on the first notification display device 201.

The second display IC 206 is provided corresponding to the second alarm display device 202, and is electrically connected to the MPU 62 by signal path SL33 and to the second alarm display device 202 by signal path SL34. The second display IC 206 is provided with a storage buffer for storing display data received from the MPU 62, and performs display control of the second alarm display device 202, i.e., light emission control of each display segment, according to the display data stored in the storage buffer. When operating power is supplied, the second display IC 206 can store and hold the display data stored in the storage buffer, and causes the second alarm display device 202 to continuously display the display content corresponding to the stored display data. Then, when the display data is changed by the MPU 62, the display of the second alarm display device 202 is changed to the display content corresponding to the changed display data. In addition, after the supply of operating power to the second display IC 206 has started and the display data has not yet been set by the MPU 62, the display data will be all "0" data, in which case the second notification display device 202 will be in a non-display state, i.e., off state.

However, this is not limited to the above configuration, and the second display IC 206 may be configured to store and hold display data even when the supply of operating power to the pachinko machine 10 is stopped by supplying backup power to the second display IC 206. In this case, when the supply of operating power to the pachinko machine 10 is started, the display that was being performed on the second notification display device 202 immediately before the supply of operating power to the pachinko machine 10 was stopped will be started on the second notification display device 202.

The third display IC 207 is provided in correspondence with the third alarm display device 203, and is electrically connected to the MPU 62 via signal path SL35 and to the third alarm display device 203 via signal path SL36. The third display IC 207 is provided with a storage buffer for storing display data received from the MPU 62, and performs display control of the third alarm display device 203, i.e., light emission control of each display segment, according to the display data stored in the storage buffer. When operating power is supplied, the third display IC 207 can store and hold the display data stored in the storage buffer, and causes the third alarm display device 203 to continuously display the display content corresponding to the stored display data. Then, when the display data is changed by the MPU 62, the display of the third alarm display device 203 is changed to the display content corresponding to the changed display data. In addition, after the supply of operating power to the third display IC 207 has started and the display data has not yet been set by the MPU 62, the display data will be all "0" data, in which case the third notification display device 203 will be in a non-display state, i.e., turned off.

However, this is not limited to the above configuration, and the third display IC 207 may be configured to store and hold display data even when the supply of operating power to the pachinko machine 10 is stopped by supplying backup power to the third display IC 207. In this case, when the supply of operating power to the pachinko machine 10 is started, the display that was being performed on the third notification display device 203 immediately before the supply of operating power to the pachinko machine 10 was stopped will be started on the third notification display device 203.

The fourth display IC 208 is provided in correspondence with the fourth alarm display device 204, and is electrically connected to the MPU 62 via signal path SL37 and to the fourth alarm display device 204 via signal path SL38. The fourth display IC 208 is provided with a storage buffer for storing display data received from the MPU 62, and performs display control of the fourth alarm display device 204, i.e., light emission control of each display segment, according to the display data stored in the storage buffer. When operating power is supplied, the fourth display IC 208 can store and hold the display data stored in the storage buffer, and causes the fourth alarm display device 204 to continuously display the display content corresponding to the stored display data. Then, when the display data is changed by the MPU 62, the display of the fourth alarm display device 204 is changed to the display content corresponding to the changed display data. In addition, after the supply of operating power to the fourth display IC 208 has started and the display data has not yet been set by the MPU 62, the display data will be all "0" data, in which case the fourth notification display device 204 will be in a non-display state, i.e., off state.

However, this is not limited to the above configuration, and the fourth display IC 208 may be configured to store and hold display data even when the supply of operating power to the pachinko machine 10 is stopped by supplying backup power to the fourth display IC 208. In this case, when the supply of operating power to the pachinko machine 10 is started, the display that was being performed on the fourth alert display device 204 immediately before the supply of operating power to the pachinko machine 10 was stopped will be started on the fourth alert display device 204.

The display data is output to the first to fourth display ICs 205 to 208 by the MPU 62, but the output setting of the display data is performed by the main CPU 63 and the management CPU 112, respectively. That is, the main CPU 63 executes display control of the first to fourth notification display devices 201 to 204, and the management CPU 112 executes display control of the first to fourth notification display devices 201 to 204. In this case, the period during which the display data output setting is performed in each of the main CPU 63 and the management CPU 112 is adjusted so that the display data output setting is not performed at the same time in the main CPU 63 and the management CPU 112. Specifically, after the supply of operating power to the MPU 62 is started, in a changeable state in which the setting state of the pachinko machine 10 can be changed, the main CPU 63 performs the output setting of the display data, but the management CPU 112 does not perform the output setting of the display data. On the other hand, in a state in which the setting value is not changeable, the management CPU 112 performs the output setting of the display data, but the main CPU 63 does not perform the output setting of the display data.

If the display data output setting by the main CPU 63 and the display data output setting by the management CPU 112 are performed synchronously, the display data output setting by the main CPU 63 takes precedence. However, this is not limited to this, and the display data output setting by the management CPU 112 may take precedence.

Next, the display process in this embodiment executed by the management CPU 112 will be explained with reference to the flowchart in FIG. 55.

First, the value of the update timing counter in the management RAM 114 is decremented by 1 (step S3001). The update timing counter is a counter that allows the management CPU 112 to determine whether it is time to update the display contents of the game history management results in the first to fourth notification display devices 201 to 204. After that, it is determined whether the value of the update timing counter after decrementing by 1 is "0" to determine whether it is time to update the display contents of the first to fourth notification display devices 201 to 204 (step S3002).

If a positive judgment is made in step S3002, the value of the display target counter in the management RAM 114 is incremented by 1 (step S3003). Then, if the value of the display target counter after incrementing by 1 exceeds the maximum value of "24" (step S3004: YES), the value of the display target counter is cleared to "0" (step S3005). The display target counter is a counter that allows the management CPU 112 to identify the type of parameter that is to be displayed in the first to fourth alarm display devices 201 to 204. There is a one-to-one correspondence between the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters and the possible values of the display target counter, "0" to "24". For example, when the value of the display object counter is "0", the first parameter, which is the first display object, becomes the display object of the first to fourth notification display devices 201 to 204, and when the value of the display object counter is "24", the 42nd parameter, which is the last display object, becomes the display object of the first to fourth notification display devices 201 to 204.

If a negative judgment is made in step S3004, or if the processing of step S3005 is executed, display data corresponding to the type of parameter corresponding to the value of the display target counter is read from the management side ROM 113 (step S3006). Then, a setting process of the display data corresponding to the first alarm display device 201 is executed (step S3007), and a setting process of the display data corresponding to the second alarm display device 202 is executed (step S3008). For example, if the value of the display target counter is "0" and the first parameter is the display target, display data for displaying "A" on the first alarm display device 201 is output to the first display IC 205, and display data for displaying "1" on the second alarm display device 202 is output to the second display IC 206. Also, for example, if the value of the display target counter is "24" and the 42nd parameter is the display target, display data for displaying "O" on the first alarm display device 201 is output to the first display IC 205, and display data for displaying "2" on the second alarm display device 202 is output to the second display IC 206.

Then, a parameter corresponding to the value of the counter to be displayed is read from the calculation result memory 131, and the display data corresponding to the tens digit and the ones digit of the result obtained by multiplying the read parameter by 100 are read from the management side ROM 113 (step S3009). Then, the display of the third alert display device 203 is controlled so that the number corresponding to the tens digit of the result is displayed (step S3010), and the display of the fourth alert display device 204 is controlled so that the number corresponding to the ones digit is displayed (step S3011). For example, if the result of multiplying by 100 is "53", display data for displaying "5" on the third alert display device 203 is output to the third display IC 207, and display data for displaying "3" on the fourth alert display device 204 is output to the fourth display IC 208.

Then, the update timing counter in the management RAM 114 is set to a value corresponding to 2 seconds as the value corresponding to the next update timing (step S3012).

By executing the display process as described above, the game history management results are displayed on the first to fourth notification display devices 201 to 204. The game history management results are displayed regardless of whether or not play is continuing, and regardless of whether or not the gaming machine main body 12 has been opened relative to the outer frame 11 and the main control device 60 is visible from the front of the pachinko machine 10. By executing display control of the first to fourth notification display devices 201 to 204 in this way regardless of the game situation or the state of the pachinko machine 10, it is possible to simplify the processing configuration for display control of the first to fourth notification display devices 201 to 204.

The display of the game history management results on the first to fourth notification display devices 201 to 204 begins after the supply of operating power to the management CPU 112 has started and after the identification end command has been received from the main CPU 63. In this case, the information stored in the calculation result memory 131, like the information stored in the history memory 117, is stored and retained even when the supply of operating power to the pachinko machine 10 has been stopped, so that when the supply of operating power to the management CPU 112 has started, the game history management results calculated before the supply of operating power to the management CPU 112 was stopped are displayed.

While operating power is being supplied to the first to fourth display ICs 205-208, they store and hold the display data output from the MPU 62, and control the display of the corresponding first to fourth notification display devices 201-204 according to that display data. Therefore, after the display of the game history management results begins, the first to fourth notification display devices 201-204 are never turned off (i.e., not displayed), but are turned on (i.e., displayed) to display some kind of information.

Next, the setting value update process in this embodiment executed by the main CPU 63 will be explained with reference to the flowchart in FIG. 56.

First, the first to third display devices 201 to 203 are turned off (step S3101). Specifically, display data that is all "0" is output to the first to third display ICs 205 to 207. As a result, all display segments of the first to third display devices 201 to 203 are turned off, and the first to third display devices 201 to 203 are turned off. Note that immediately after the supply of operating power to the pachinko machine 10 is started, all display segments of the first to fourth display devices 201 to 204 are turned off, and the first to fourth display devices 201 to 204 are turned off. Therefore, step S3101 is a process for maintaining the first to third display devices 201 to 203 in the turned off state, and also a process for turning off any of the first to third display devices 201 to 203 in the turned on state if any of them is turned on due to some influence.

Then, the setting value counter in the main RAM 65 is set to "1" (step S3102). The setting value counter is a counter that allows the main CPU 63 to identify which setting value the setting state of the pachinko machine 10 is. By setting the setting value counter to "1", when the setting value update process is executed, the setting value becomes "Setting 1" regardless of the previous setting value.

After that, a process to start displaying the setting value in the fourth display notification device 204 is executed (step S3103). In the process to start displaying the setting value, display data for displaying "1" is output to the fourth display IC 208. As a result, the number "1" corresponding to "Setting 1" is displayed on the fourth notification display device 204.

After that, on the condition that the setting key insertion section 68a has not been turned OFF (step S3104: NO), it is determined whether the update button 68b has been pressed once (step S3105). Specifically, it is determined whether the signal from the sensor that detects the pressing of the update button 68b has switched from a LOW level to a HIGH level. If a negative determination is made in step S3105, the process returns to step S3104, and it is determined whether the setting key insertion section 68a has been turned OFF.

If the update button 68b has been pressed once (step S3105: YES), the value of the setting value counter in the main RAM 65 is incremented by 1 (step S3106). If the value of the setting value counter after incrementing by 1 exceeds "6" (step S3107: YES), the setting value counter is set to "1" (step S3108). As a result, the setting value is updated to the next higher level each time the update button 68b is pressed, and if the update button 68b is pressed once when the setting is "setting 6", the setting will return to "setting 1".

If a negative judgment is made in step S3107, or if the processing of step S3108 is executed, a display update process of the setting value in the fourth alert display device 204 is executed (step S3109). In the display update process of the setting value, display data for displaying a number corresponding to the value of the setting value counter in the main RAM 65 is output to the fourth display IC 208. As a result, a number corresponding to the current setting value is displayed on the fourth alert display device 204. By checking the fourth alert display device 204, the manager of the gaming hall can grasp the setting state of the pachinko machine 10 after pressing the update button 68b.

After executing the process of step S3109, the process returns to step S3104, and it is determined whether the setting key insertion section 68a has been turned OFF. If it has not been turned OFF (step S3104: NO), the process of steps S3105 and onwards is executed again. If it has been turned OFF (step S3104: YES), the process of starting display of the management results on the first to fourth alarm display devices 201 to 204 is executed (step S3110).

In this display start process, a command to start displaying the management results is sent from the main CPU 63 to the management CPU 112. The management CPU 112, which has received the command to start displaying the management results, executes a process to display the first parameter from among the various parameters stored in the calculation result memory 131. The process content in this case is the same as steps S3006 to S3012 in the display process (FIG. 55). As a result, a display corresponding to the first parameter calculated immediately before the operating power of the pachinko machine 10 was previously stopped is performed on the first to fourth notification display devices 201 to 204.

Next, the display modes of the first to fourth notification display devices 201 to 204 when the game history management results are displayed and when the setting state of the pachinko machine 10 is updated will be described. Figure 57(a) is an explanatory diagram for explaining the display modes of the first to fourth notification display devices 201 to 204 when the game history management results are displayed, and Figure 57(b) is an explanatory diagram for explaining the display modes of the first to fourth notification display devices 201 to 204 when the setting state of the pachinko machine 10 is changed.

When the gaming history management results are displayed, at least one display segment is illuminated in each of the first to fourth display devices 201 to 204 as shown in FIG. 57(a). In other words, each of the first to fourth display devices 201 to 204 is in a display state. This is the same regardless of whether the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameters, or the forty-first to forty-second parameters are the ones to be notified. This allows the manager of the gaming hall to visually confirm that all of the first to fourth display devices 201 to 204 are in a display state and to ascertain that the gaming history management results are being displayed on the first to fourth display devices 201 to 204.

On the other hand, when the setting state of the pachinko machine 10 is changed, all display segments are turned off in each of the first to third alert display devices 201 to 203 as shown in FIG. 57(b). In other words, each of the first to third alert display devices 201 to 203 is turned off. Also, the fourth alert display device 204 displays one of the numbers "1" to "6." In this way, the fourth alert display device 204 displays one of the numbers "1" to "6" and each of the first to third alert display devices 201 to 203 is turned off, allowing the manager of the amusement hall to know that the first to fourth alert display devices 201 to 204 are displaying values corresponding to the setting values, and to clearly understand the current setting values.

Next, we will explain how the first to fourth alarm display devices 201 to 204 enter a display state, with reference to the time charts in Figures 58 (a) to 58 (h). FIG. 58(a) shows a period during which the setting state of the pachinko machine 10 is changeable, FIG. 58(b) shows the timing of updating the setting display on the first to fourth display devices 201 to 204, FIG. 58(c) shows a period during which the results of game history management are displayed on the first to fourth display devices 201 to 204, FIG. 58(d) shows the timing of updating the display corresponding to the results of game history management on the first to fourth display devices 201 to 204, FIG. 58(e) shows a period during which the first display device 201 is in a display state, FIG. 58(f) shows a period during which the second display device 202 is in a display state, FIG. 58(g) shows a period during which the third display device 203 is in a display state, and FIG. 58(h) shows a period during which the fourth display device 204 is in a display state.

When the setting key insertion section 68a is turned ON and the supply of operating power to the pachinko machine 10 is started, the setting state of the pachinko machine 10 is changed at timing t1 as shown in FIG. 58(a). At timing t1, the setting display is updated as shown in FIG. 58(b), and the fourth notification display device 204 is turned on and continues to be displayed as shown in FIG. 58(h). In this case, since "Setting 1" is selected, the fourth notification display device 204 displays "1". On the other hand, at timing t1, the first to third notification display devices 201 to 203 are kept in a non-display state, that is, all display segments are turned off, as shown in FIG. 58(e) to FIG. 58(g).

After that, at times t2, t3, t4, and t5, the setting value is changed by operating the update button 68b, which results in the setting value display being updated at each of these times, as shown in FIG. 58(b). In this case, as shown in FIG. 58(h), the display content of the fourth alert display device 204 is switched to a number corresponding to the changed setting value at each of these times, but the fourth alert display device 204 is maintained in a display state, including each time the display content is switched. Meanwhile, as shown in FIG. 58(e) to FIG. 58(g), the first to third alert display devices 201 to 203 are maintained in a non-display state, that is, all display segments are turned off, at each of these setting value display update times.

Then, at the timing of t6, the setting key insertion section 68a is turned OFF, thereby terminating the changeable state as shown in FIG. 58(a). In this case, at the timing of t6, the display period for the game history management results begins as shown in FIG. 58(c). Specifically, the display of the first parameter stored in the calculation result memory 131 begins. Therefore, at the timing of t6, the first to third notification display devices 201 to 203 are switched from a non-display state to a display state as shown in FIG. 58(e) to FIG. 58(g), and the fourth notification display device 204 maintains its display state although the display content is changed.

After that, at times t7, t8, t9, t10, t11, and t12, the display of the gaming history management results is updated as shown in Fig. 58(d). In this case, as shown in Fig. 58(e) to Fig. 58(h), the first to fourth notification display devices 201 to 204 will switch to the display content corresponding to the updated gaming history management results at each of these times, but all of the first to fourth notification display devices 201 to 204 will be maintained in the display state, including at each time when this display content is switched.

The present embodiment described above provides the following excellent advantages:

In a configuration in which the game history management results are displayed on the first to fourth notification display devices 201 to 204, when the setting state of the pachinko machine 10 is in a changeable state in which it is possible to change the setting state, a corresponding display is made on the first to fourth notification display devices 201 to 204. This makes it possible to use the first to fourth notification display devices 201 to 204 not only for displaying the game history management results, but also as display devices for making a corresponding display in the changeable state.

A distinction is made between the period during which the first to fourth notification display devices 201-204 display the game history management results and the period during which the first to fourth notification display devices 201-204 display information corresponding to the setting value being in a changeable state. This makes it possible to identify which display is being made on the first to fourth notification display devices 201-204 by understanding the state in which the display is being made on the first to fourth notification display devices 201-204.

When a display corresponding to a changeable state of the setting value is made, the first to fourth notification display devices 201 to 204 are controlled to have a different display mode than when the gaming history management results are displayed. This makes it possible to identify which display is being made on the first to fourth notification display devices 201 to 204 by grasping the display mode of the first to fourth notification display devices 201 to 204.

Multiple notification display devices 201-204 are provided. This makes it possible to perform a wide variety of displays corresponding to the results of game history management. Furthermore, the presence of multiple notification display devices 201-204 makes it possible to greatly differ the display mode when the results of game history management are displayed from when a display corresponding to the changeable state of the setting value is performed.

When a display corresponding to the changeable state of the setting value is made, the first to third notification display devices 201-203, which are not in a hidden state when displaying the game history management results, are in a hidden state. This makes it possible to clearly identify which of the display of the game history management results and the display corresponding to the changeable state of the setting value are being made on the first to fourth notification display devices 201-204, simply by checking whether the first to third notification display devices 201-203 are in a hidden state.

When a display corresponding to a changeable state of the setting value is made, the fourth notification display device 204 is in a display state, and the display content is the display content that can be displayed on the fourth notification display device 204 when displaying the results of game history management. By allowing the display content on the fourth notification display device 204 to overlap in this way, it is possible to avoid restricting the display content when the results of game history management are displayed and when a display corresponding to a changeable state of the setting value is made. Even if the display content on the fourth notification display device 204 is configured to overlap in this way, when a display corresponding to a changeable state of the setting value is made, the first to third notification display devices 201 to 203 are made non-displayed, so it is possible to identify which display is being made on the first to fourth notification display devices 201 to 204.

When the game history management results are displayed, the first to fourth notification display devices 201 to 204 are each in a display state. This makes it possible to clearly differentiate the display modes of the first to fourth notification display devices 201 to 204 between when the game history management results are displayed and when a display corresponding to a changeable state of the setting value is made.

When the gaming history management results are displayed, the first to fourth notification display devices 201-204 are not maintained in a non-display state even if the type of gaming history management result to be displayed is changed. This makes it possible to identify the gaming history management results regardless of the timing at which the first to fourth notification display devices 201-204 are checked when the gaming history management results are displayed. Also, regardless of the timing at which the first to fourth notification display devices 201-204 are checked, it becomes possible to identify which of the display of the gaming history management results and the display corresponding to the changeable state of the setting value is being displayed on the first to fourth notification display devices 201-204.

When a display corresponding to a changeable state of the setting value is being made, only one of the fourth notification display devices 204 is in a display state. This makes it easier to know whether a display corresponding to a changeable state of the setting value is being made.

In a configuration in which the first to fourth notification display devices 201 to 204 are arranged horizontally, only the fourth notification display device 204, which is located at the right end, is used to display the setting value in a changeable state. This makes it easier to know whether a display corresponding to a changeable state of the setting value is being displayed.

When the game history management results are displayed, the first and second notification display devices 201 and 202 are used to display a result corresponding to the type of game history management result to be displayed, and the third and fourth notification display devices 203 and 204 are used to display a result corresponding to the content of the game history management result. This makes it easier to understand the game history management result. In this case, when the setting value is in a changeable state, the first and second notification display devices 201 and 202, which display the type of game history management result, are both in a non-display state. This means that the non-display state of the first and second notification display devices 201 and 202 for displaying the type corresponds to the changeable state of the setting value, making it easier to understand that a display corresponding to the changeable state of the setting value is being performed.

In addition, when a display corresponding to a changeable state of the setting value is made, not only the first notification display device 201 and the second notification display device 202, which display the type of the game history management result, but also the third notification display device 203, which displays the content of the game history management result, is made invisible. This makes it easier to understand that a display corresponding to a changeable state of the setting value is being made.

In a configuration in which display data is output from the MPU 62 to the first to fourth display ICs 205-208, and the first to fourth display ICs 205-208 cause the first to fourth notification display devices 201-204 to perform a predetermined display in accordance with the display data, the display data is stored and held in the first to fourth display ICs 205-208. As a result, even if the execution of processing for progressing the game is stopped in the main CPU 63 due to the occurrence of a radio wave detection abnormality or vibration detection abnormality (when a positive judgment is made in step S306), it is possible to maintain the display of the game history management results in the first to fourth notification display devices 201-204.

In addition, among the first to fourth alert display devices 201-204, the targets that are in the non-display state (all lights off state) in the changeable state in which the setting state of the pachinko machine 10 can be changed are not limited to the first to third alert display devices 201-203, but may be the first and second alert display devices 201 and 202. In this case, the third alert display device 203 may be configured to display a predetermined display (for example, a display of "5") that is different from the content of the current setting value, and the fourth alert display device 204 may be configured to display a number corresponding to the current setting value, or the fourth alert display device 204 may be configured to display a predetermined display (for example, a display of "5") that is different from the content of the current setting value, and the third alert display device 203 may be configured to display a number corresponding to the current setting value. Also, the first alert display device 201 and the third alert display device 203 may be configured to be in a non-display state (all lights off state) and the second alert display device 202 and the fourth alert display device 204 may be configured to be in a display state, the first alert display device 201 and the fourth alert display device 204 may be configured to be in a non-display state (all lights off state) and the second alert display device 202 and the third alert display device 203 may be configured to be in a display state, or the second alert display device 202 and the fourth alert display device 204 may be configured to be in a non-display state (all lights off state) and the first alert display device 201 and the third alert display device 203 may be configured to be in a display state.

In addition, in a changeable state in which the setting state of the pachinko machine 10 can be changed, only the first alarm display device 201 may be configured to be in a non-display state (all lights off state), only the second alarm display device 202 may be configured to be in a non-display state (all lights off state), only the third alarm display device 203 may be configured to be in a non-display state (all lights off state), or only the fourth alarm display device 204 may be configured to be in a non-display state (all lights off state).

In addition, in a changeable state in which the setting state of the pachinko machine 10 can be changed, only the first notification display device 201 may be configured to be in a display state, only the second notification display device 202 may be configured to be in a display state, or only the third notification display device 203 may be configured to be in a display state.

Twelfth embodiment
In this embodiment, the display contents of the first notification display device 201 and the second notification display device 202 in the state in which the setting value can be changed are different from those of the eleventh embodiment. The following describes the configurations that are different from the eleventh embodiment. Note that the description of the same configurations as the eleventh embodiment will basically be omitted.

Figure 59 (a) is an explanatory diagram for explaining the configuration of the first notification display device 201, and Figure 59 (b) is an explanatory diagram for explaining the configuration of the second notification display device 202.

As shown in FIG. 59(a), the first alarm display device 201 has seven display segments 1 to 7 201a to 201g. Each of the first to seventh display segments 201a to 201g is formed in a rod shape and has an LED or other light emitter inside. These seven display segments 1 to 7 201a to 201g are arranged so that the first alarm display device 201 is a so-called seven-segment display.

As shown in FIG. 59(b), the second alarm display device 202 has seven display segments, numbered 1 to 7, 202a to 202g. Each of the first to seventh display segments 202a to 202g is formed in a rod shape and has an LED or other light emitter inside. These seven display segments, numbered 1 to 7, 202a to 202g, are arranged so that the second alarm display device 202 is a so-called 7-segment display.

Figure 60 is an explanatory diagram for explaining the display contents of the first notification display device 201 and the second notification display device 202 when the first to fourth notification display devices 201 to 204 display the results of game history management and when displaying that the setting state of the pachinko machine 10 is in a changeable state in which it is possible to change it.

The display contents of the first notification display device 201 and the second notification display device 202 when displaying the results of game history management are the same as those of the eleventh embodiment. Therefore, the first notification display device 201 displays any of "A", "E", "H", "L" or "O", and the second notification display device 202 displays any of "1" to "8".

In this case, each of the first to seventh display segments 201a to 201g of the first alarm display device 201 becomes an illumination target when at least one of the following displays is displayed on the first alarm display device 201: "A", "E", "H", "L", and "O". In other words, there are no display segments 201a to 201g that do not become illumination targets when the first alarm display device 201 displays any of "A", "E", "H", "L", and "O".

Similarly, for the second alert display device 202, each of the first to seventh display segments 202a to 202g of the second alert display device 202 is subject to illumination when at least one of the numbers "1" to "8" is displayed on the second alert display device 202. In other words, there are no display segments 202a to 202g that are not subject to illumination when any of the numbers "1" to "8" is displayed on the second alert display device 202.

In a changeable state in which the setting state of the pachinko machine 10 can be changed, the second display segment 201b and the fifth display segment 201e are illuminated in the first alert display device 201. As already explained, the second display segment 201b and the fifth display segment 201e can be illuminated when the first alert display device 201 displays the results of game history management. Furthermore, in any case in which the first alert display device 201 displays the results of game history management, the second display segment 201b and the fifth display segment 201e are illuminated. On the other hand, the display content of the first alert display device 201 in which only the second display segment 201b and the fifth display segment 201e are illuminated among the first to seventh display segments 201a to 201g does not exist when the results of game history management are displayed. This makes it possible to display a display mode on the first notification display device 201 that is not displayed when displaying the gaming history management results while using the display segments 201b and 201e that can be illuminated when displaying the gaming history management results when the setting value is in a changeable state. Therefore, it is possible to cause the first notification display device 201 to perform a display corresponding to the changeable state of the setting value while also using the display segments 201a to 201g that are used when displaying the gaming history management results.

In the state where the setting value can be changed, the third display segment 202c of the second notification display device 202 is in a light-emitting state. As already explained, the third display segment 202c can be in a light-emitting state when the second notification display device 202 displays the game history management results. On the other hand, the display content of the second notification display device 202, in which only the third display segment 202c of the first to seventh display segments 202a to 202g is in a light-emitting state, does not exist when the game history management results are displayed. This makes it possible to display a display mode that is not displayed when the game history management results are displayed on the second notification display device 202 while using the display segment 202c that can be in a light-emitting state when displaying the game history management results in the state where the setting value can be changed. Therefore, it is possible to display a display corresponding to the state where the setting value can be changed on the second notification display device 202 while also using the display segments 202a to 202g that are used when displaying the game history management results.

Next, the setting value update process in this embodiment executed by the main CPU 63 will be explained with reference to the flowchart in FIG. 61.

First, the process of starting the display of the setting values in the first and second notification display devices 201 and 202 is executed (step S3201). Specifically, for the first notification display device 201, display data is output to the first display IC 205, in which the second display segment 201b and the fifth display segment 201e are illuminated, and the other display segments 201a, 201c, 201d, 201f, and 201g are turned off. For the second notification display device 202, display data is output to the second display IC 206, in which the third display segment 202c is illuminated, and the other display segments 202a, 202b, 202d to 202g are turned off. This starts a display on the first notification display device 201 and the second notification display device 202 to notify that the setting state of the pachinko machine 10 is in a changeable state in which it is possible to change the setting state.

Then, the third alarm display device 203 is turned off (step S3202). Specifically, display data that is all "0" is output to the third display IC 207. As a result, all display segments of the third alarm display device 203 are turned off, and the third alarm display device 203 is turned off.

Then, the setting value counter in the main RAM 65 is set to "1" (step S3203). The setting value counter is a counter that allows the main CPU 63 to identify which setting value the setting state of the pachinko machine 10 is. By setting the setting value counter to "1", when the setting value update process is executed, the setting value becomes "Setting 1" regardless of the previous setting value.

After that, a process to start displaying the setting value on the fourth alarm display device 204 is executed (step S3204). In the process to start displaying the setting value, display data for displaying "1" is output to the fourth display IC 208. As a result, the number "1" corresponding to "Setting 1" is displayed on the fourth alarm display device 204.

After that, on the condition that the setting key insertion section 68a has not been turned OFF (step S3205: NO), it is determined whether the update button 68b has been pressed once (step S3206). Specifically, it is determined whether the signal from the sensor that detects the pressing of the update button 68b has switched from a LOW level to a HIGH level. If a negative determination is made in step S3206, the process returns to step S3205, and it is determined whether the setting key insertion section 68a has been turned OFF.

If the update button 68b has been pressed once (step S3206: YES), the value of the setting value counter in the main RAM 65 is incremented by 1 (step S3207). If the value of the setting value counter after incrementing by 1 exceeds "6" (step S3208: YES), the setting value counter is set to "1" (step S3209). As a result, the setting value is updated to the next higher level each time the update button 68b is pressed, and if the update button 68b is pressed once when the setting is "setting 6", the setting will return to "setting 1".

If a negative judgment is made in step S3208, or if the processing of step S3209 is executed, a display update process of the setting value in the fourth alert display device 204 is executed (step S3210). In the display update process of the setting value, display data for displaying a number corresponding to the value of the setting value counter in the main RAM 65 is output to the fourth display IC 208. As a result, a number corresponding to the current setting value is displayed on the fourth alert display device 204. By checking the fourth alert display device 204, the manager of the gaming hall can grasp the setting state of the pachinko machine 10 after pressing the update button 68b.

After executing the process of step S3210, the process returns to step S3205, and it is determined whether the setting key insertion section 68a has been turned OFF. If it has not been turned OFF (step S3205: NO), the process of steps S3206 and onwards is executed again. If it has been turned OFF (step S3205: YES), the process of starting display of the management results on the first to fourth alarm display devices 201 to 204 is executed (step S3211).

In this display start process, a command to start displaying the management results is sent from the main CPU 63 to the management CPU 112. The management CPU 112, which has received the command to start displaying the management results, executes a process to display the first parameter from among the various parameters stored in the calculation result memory 131. The process content in this case is the same as steps S3006 to S3012 in the display process (FIG. 55). As a result, a display corresponding to the first parameter calculated immediately before the operating power of the pachinko machine 10 was previously stopped is performed on the first to fourth notification display devices 201 to 204.

The present embodiment described above provides the following excellent advantages:

When the game history management results are displayed, the display segments 201a-201g, 202a-202g of the first and second notification display devices 201, 202 that can be illuminated are illuminated to display a state corresponding to the changeable state of the setting value. This makes it possible to diversify the display of the game history management results while placing as few restrictions as possible on the content of the display corresponding to the game history management results. On the other hand, for each of the first notification display device 201 and the second notification display device 202, the combinations of the display segments 201a-201g, 202a-202g that are illuminated when a display corresponding to the changeable state of the setting value is performed are combinations that do not exist when the game history management results are displayed. As a result, by determining the combination of display segments 201a-201g and 202a-202g that are illuminated on the first and second notification display devices 201 and 202, respectively, it is possible to determine which of the display results of game history management and the display corresponding to the changeable state of the setting value is being displayed.

For the first notification display device 201 and the second notification display device 202, there are no display segments 201a-201g, 202a-202g that do not light up even if all patterns of the game history management results are displayed. This makes it possible to diversify the display corresponding to the game history management results without restricting the display content of the game history management results as much as possible.

When a display corresponding to the changeable state of the setting value is made, the third notification display device 203, which is not made invisible when displaying the game history management results, is made invisible. As a result, by checking not only the display contents of the first notification display device 201 and the second notification display device 202 but also whether the third notification display device 203 is in a hidden state, it is possible to clearly identify which of the display of the game history management results and the display corresponding to the changeable state of the setting value is being made by the first to fourth notification display devices 201 to 204.

The first and second notification display devices 201 and 202 are not limited to a configuration in which only one type of display content is set corresponding to the changeable state in which the setting state of the pachinko machine 10 can be changed, and multiple types may be set. In this case, the display order of the multiple types of display content may be predetermined, and the display content to be displayed may be changed according to the display order each time a new changeable state is executed. Even if there are multiple types of display content corresponding to the changeable state of the setting value, these display contents are displayed using the display segments 201a to 201g and 202a to 202g that are illuminated when the management results of the game history are displayed, and are not displayed when the management results of the game history are displayed.

In addition, when displaying the game history management results or when displaying a display corresponding to a changeable state in which the setting state of the pachinko machine 10 can be changed, the first and second notification display devices 201 and 202 may be configured to flash in one case, and to keep the display on in the other case. In this case, the manager of the game hall can specify whether the display corresponds to the game history management results or the changeable state depending on whether the display is flashing or on, so the combination of the display segments 201a to 201g, 202a to 202g that are in the light-emitting state in the display corresponding to the changeable state may be a combination used when displaying the game history management results, or may be a combination that is not used when displaying the game history management results. In addition, the first notification display device 201 and the second notification display device 202 may be configured to have a configuration in which the light-on period and the light-off period in the flashing display are mutually consistent, may be configured to be completely different, or may be configured to overlap only partially.

Thirteenth embodiment
This embodiment differs from the eleventh embodiment in that when an abnormal state occurs in the pachinko machine 10, a corresponding display is performed using the first to fourth notification display devices 201 to 204. The following describes the configuration that differs from the eleventh embodiment. Note that the description of the same configuration as the eleventh embodiment will basically be omitted.

Figure 62 is an explanatory diagram for explaining the configuration of the abnormality display area 211 provided in the main RAM 65.

The abnormality display area 211 is an area for storing information on abnormal conditions to be displayed on the first to fourth alarm display devices 201 to 204. The abnormality display area 211 is provided with a plurality of unit areas 211a to 211d. Specifically, a first unit area 211a, a second unit area 211b, a third unit area 211c, and a fourth unit area 211d are provided. Each of the first to fourth unit areas 211a to 211d can store one piece of information on an abnormal condition of the pachinko machine 10. In other words, the abnormality display area 211 can store and hold up to four pieces of information on an abnormal condition of the pachinko machine 10.

In this embodiment, all information on abnormal conditions occurring in the pachinko machine 10 is identified by the main CPU 63. For example, if an abnormality occurs with respect to the payout of game balls (for example, the lower tray 56a is full, there are no balls in the tank 75, or a payout abnormality by the payout device 76), a command corresponding to the abnormality is transmitted from the payout CPU 92 to the main CPU 63. In addition, the pachinko machine 10 is provided with a radio wave detection sensor and a vibration detection sensor (not shown), and when the radio wave detection sensor detects an illegal radio wave, a corresponding abnormality signal is transmitted to the main CPU 63, and when the vibration detection sensor detects an abnormal vibration, a corresponding abnormality signal is transmitted to the main CPU 63. In addition, based on identifying that normal signals are no longer being transmitted from each of the ball entry detection sensors 42a to 49a, the occurrence of a disconnection abnormality in these ball entry detection sensors 42a to 49a is identified.

The types of abnormal conditions identified by the main CPU 63 are greater than the maximum number of abnormal condition information items that can be stored in the abnormality display area 211. This means that if multiple abnormal conditions occur simultaneously, it is expected that new abnormal condition information will occur even though the maximum number of abnormal condition information items has already been stored in the abnormality display area 211. In response to this, a storage priority is set for the abnormal condition information during the setup stage of the pachinko machine 10, and if a new abnormal condition occurs in a situation where the maximum number of abnormal condition information items have already been stored in the abnormality display area 211, the abnormal condition information item with the higher storage priority will remain in the abnormality display area 211. This makes it possible to prioritize the notification of abnormal conditions with higher storage priority items.

Next, the abnormality setting process executed by the main CPU 63 will be described with reference to the flowchart in FIG. 63. Note that the abnormality setting process is executed as the first process of the timer interrupt process (FIG. 11).

First, it is determined whether an abnormality has occurred (step S3301). The types of abnormality that can be displayed include a full lower tray 56a, no balls in the tank 75, a payout error by the payout device 76, a radio wave detection error, a vibration detection error, and a disconnection error in each ball entry detection sensor 42a to 49a. The number of types of abnormality that can be displayed is greater than the number of the first to fourth unit areas 211a to 211d provided in the abnormality display area 211.

If a positive judgment is made in step S3301, it is judged whether or not information on the abnormal condition corresponding to the currently occurring abnormal display object has already been stored in any of the first to fourth unit areas 211a to 211d of the abnormality display area 211 (step S3302). If information on the abnormal condition corresponding to the currently occurring abnormal display object has already been stored, it is not stored in the abnormality display area 211. This makes it possible to prevent information on the same type of abnormal condition from being redundantly stored in the abnormality display area 211.

If a negative judgment is made in step S3302, it is judged whether the value of the abnormality target counter provided in the main RAM 65 is the maximum value (specifically, "4") (step S3303). The abnormality target counter is a counter that allows the main CPU 63 to identify the number of areas in which abnormality information is stored among the first to fourth unit areas 211a to 211d in the abnormality display area 211.

If the value of the abnormality object counter is the maximum value (step S3303: YES), a priority comparison process is executed (step S3304). In the priority comparison process, first, the abnormality information with the lowest storage priority is identified among the abnormality information stored in the first to fourth unit areas 211a to 211d of the abnormality display area 211. The storage priority is determined in advance at the design stage of the pachinko machine 10, and specifically, the storage priority increases in the following order: full bottom tray 56a → no balls in tank 75 → vibration detection abnormality → payout abnormality by payout device 76 → disconnection abnormality of ball entry detection sensor 42a to 49a → radio wave detection abnormality. In the priority comparison process, a comparison is made to determine which of the information on the abnormality with the lowest storage priority stored in the first to fourth unit areas 211a to 211d and the currently occurring abnormality display object has a higher storage priority.

If the storage priority of the currently occurring abnormality display object is low (step S3305: NO), information on the abnormal state corresponding to the currently occurring abnormality display object is not stored in the abnormality display area 211. This makes it possible to leave information on the abnormal state with a high storage priority in the abnormality display area 211 in a configuration in which the number of types of abnormality display objects is greater than the number of the first to fourth unit areas 211a to 211d provided in the abnormality display area 211.

If the storage priority of the currently occurring abnormality display target is higher (step S3305: YES), the setting process of the abnormality display area 211 is executed (step S3306). In the setting process of the abnormality display area 211, which is executed when a positive determination is made in step S3305, the information of the abnormality state corresponding to the currently occurring abnormality display target is overwritten in the unit area 211a to 211d identified as storing information of the abnormality state with the lowest storage priority.

On the other hand, if the value of the abnormality object counter in the main RAM 65 has not reached the maximum value (step S3303: NO), the value of the abnormality object counter is incremented by 1 (step S3307), and then the setting process of the abnormality display area 211 is executed (step S3306). In this setting process, one area is selected from the unit areas 211a to 211d in which no abnormality state information is stored in the abnormality display area 211, and the abnormality state information corresponding to the currently occurring abnormality display object is stored in the selected area.

In step S3306, if only one abnormality information is stored in the abnormality display area 211, the abnormality information is stored in the first unit area 211a, and if multiple abnormality information is stored in the abnormality display area 211, the abnormality information is stored in the nth unit areas 211a to 211b in ascending order of the area with the smallest value of "n".

In the abnormality setting process, it is determined whether an event that clears the abnormality display has occurred (step S3308). For example, it is determined whether a command has been received from the payout side CPU 92 indicating that the full state of the lower tray 56a has been cleared, that the no balls state of the tank 75 has been cleared, or that a payout abnormality by the payout device 76 has been cleared. It is also determined whether an abnormality clearing operation has been performed in response to the occurrence of a radio wave detection abnormality, whether an abnormality clearing operation has been performed in response to the occurrence of a vibration detection abnormality, or whether an abnormality clearing operation has been performed in response to the occurrence of a disconnection abnormality.

If the determination in step S3308 is positive, the process of erasing the abnormality display area 211 is executed (step S3309). In the erasure process, it is determined whether or not the abnormality information corresponding to the abnormality display target that has been released this time is stored in any of the first to fourth unit areas 211a to 211d of the abnormality display area 211, and if it is stored, the abnormality information is erased by clearing the area in which it is stored to "0". In this case, if there is only one abnormality information stored in the abnormality display area 211 after erasure, the abnormality information is stored in the first unit area 211a, and if there are multiple abnormality information stored in the abnormality display area 211 after erasure, the abnormality information is stored in the n-th unit areas 211a to 211b in order from the area with the smallest "n" value. In addition, the value of the abnormality target counter in the main RAM 65 is decremented by 1 (step S3310).

In the abnormality setting process, it is determined whether or not an operation to start an abnormality display has occurred (step S3311). The operation to start an abnormality display is performed by pressing the update button 68b with the gaming machine body 12 open forward relative to the outer frame 11 in a situation in which the setting state of the pachinko machine 10 is not in a changeable state in which it is possible to change the setting state.

If a positive judgment is made in step S3311, it is judged whether or not information on one or more abnormal conditions is stored in the abnormality display area 211 (step S3312). If no information on an abnormal condition is stored, abnormality display is not initiated in the first to fourth alarm display devices 201 to 204. This makes it possible to prevent abnormality display from being initiated even when there is no information on an abnormal condition to be notified.

If a positive determination is made in step S3312, the abnormality display flag provided in the main RAM 65 is set to "1" (step S3313). The abnormality display flag is a flag for the main CPU 63 to identify a situation in which the display corresponding to the game history management results should be stopped and a display corresponding to the abnormal state information stored in the abnormality display area 211 should be performed on the first to fourth notification display devices 201 to 204. Note that even if an operation to start the abnormality display is performed when the abnormality display flag has already been set to "1", a negative determination is made in step S3311.

Then, a process for setting the display of the management results to be stopped is executed (step S3314). In this process, a display stop command is sent to the management CPU 112, which temporarily stops the update of the display of the game history management results on the first to fourth notification display devices 201 to 204. Upon receiving the display stop command, the management CPU 112 stops the execution of the display process (FIG. 55). However, even if the management CPU 112 receives the display stop command, it does not set display data to be all "0" data in the first to fourth display ICs 205 to 208. Therefore, the display of the game history management results at that time continues on the first to fourth notification display devices 201 to 204 until the display data is sent from the main CPU 63 to the first to fourth display ICs 205 to 208.

In the abnormality setting process, it is determined whether or not an operation to end the abnormality display has occurred (step S3315). The operation to end the abnormality display is performed by pressing the reset button 68c with the gaming machine body 12 open forward against the outer frame 11 in a situation in which the setting state of the pachinko machine 10 is not in a changeable state in which it is possible to change the setting state of the pachinko machine 10. If a positive determination is made in step S3315, the abnormality display flag in the main RAM 65 is cleared to "0" (step S3316). Note that even if an operation to end the abnormality display is performed in a situation in which the value of the abnormality display flag is already "0", a negative determination is made in step S3315.

After that, the display of the management result is canceled (step S3317). In the cancellation process, a cancellation command is sent to the management CPU 112 to cancel the state in which the update of the display of the management result of the game history in the first to fourth display devices 201 to 204 is canceled. By receiving the cancellation command, the management CPU 112 resumes the execution of the display process (FIG. 55). However, even if the management CPU 112 receives the cancellation command, it does not set display data that becomes all "0" data in the first to fourth display ICs 205 to 208. Therefore, until the display data is sent from the management CPU 112 to the first to fourth display ICs 205 to 208, the abnormal display at that time continues in the first to fourth display devices 201 to 204. In addition, even if the update of the display of the management result of the game history is canceled, the management CPU 112 continues to store history information and calculate various parameters, and the results of calculating various parameters are stored in the calculation result memory 131. Therefore, when the state in which the update of the display of the game history management results was suspended is released, the display of the most recent game history management results will immediately resume on the first through fourth notification display devices 201 through 204.

In the abnormality setting process, if the abnormality display flag in the main RAM 65 is set to "1" (step S3318: YES), the abnormality display process is executed (step S3319). Figure 64 is a flowchart showing the abnormality display process.

First, the first and second alarm display devices 201, 202 are turned off (step S3401). Specifically, display data that is all "0" is output to the first and second display ICs 205, 206. As a result, all display segments of the first and second alarm display devices 201, 202 are turned off, and the first and second alarm display devices 201, 202 are turned off.

Then, the value of the update timing counter provided in the main RAM 65 is decremented by 1 (step S3402). The update timing counter is a counter that allows the main CPU 63 to determine whether it is time to update the display contents of the abnormality display on the first to fourth alarm display devices 201 to 204. If the value of the update timing counter is already "0", this state is maintained. Then, by determining whether the value of the update timing counter is "0", it is determined whether it is time to update the display contents of the first to fourth alarm display devices 201 to 204 (step S3403).

If the determination in step S3403 is affirmative, the display object counter in the main RAM 65 is updated (step S3404). In this update process, if this is the first abnormality display process since the abnormality display flag in the main RAM 65 was set to "1", the display object counter is set to "0". The values of the display object counter correspond to the first to fourth unit areas 211a to 211d of the abnormality display area 211, and specifically, the value of "0" of the display object counter corresponds to the first unit area 211a, the value of "1" of the display object counter corresponds to the second unit area 211b, the value of "2" of the display object counter corresponds to the third unit area 211c, and the value of "3" of the display object counter corresponds to the fourth unit area 211d. In the update process, if this is not the first abnormality display process since the abnormality display flag in the main RAM 65 was set to "1", the value of the display object counter is incremented by 1.

Then, it is determined whether abnormal state information is stored in the area corresponding to the current value of the display target counter among the first to fourth unit areas 211a to 211d (step S3405). Here, as already explained, if only one abnormal state information is stored, the abnormal state information is stored in the first unit area 211a, and if multiple abnormal state information is stored, the abnormal state information is stored in the n-th unit areas 211a to 211b in order from the area with the smallest value of "n". Therefore, if abnormal state information is not stored in the area corresponding to the current value of the display target counter, abnormal state information is not stored in the area corresponding to a value larger than the value of the display target counter. Also, if the value of the display target counter after adding 1 exceeds the maximum value "3", there is no corresponding area in the first place, so it is treated as if no abnormal state information is stored.

If a positive judgment is made in step S3405, the value of the display target counter in the main RAM 65 is cleared to "0" (step S3406). At this point, it is assumed that all abnormal conditions that are the subject of abnormality display in a situation where an abnormality display is being performed are cancelled. In this case, even in a situation where abnormality display processing is being executed, no abnormality information is stored in the abnormality display area 211. In such a situation, a display indicating that no abnormality information is stored is performed on the third and fourth alarm display devices 203, 204.

When a negative judgment is made in step S3405, or when the process of step S3406 is executed, display data for the display target corresponding to the value of the display target counter in the main RAM 65 is read from the main ROM 64 (step S3407). Specifically, information stored in the area corresponding to the value of the display target counter in the main RAM 65 among the first to fourth unit areas 211a to 211d of the abnormality display area 211 is read. Then, display data corresponding to that information is read from the main ROM 64. The display data is set in one-to-one correspondence with the abnormality information, and the display contents of the third and fourth notification display devices 203 and 204 based on the display data differ for each type of abnormality information. In addition, there is also display data corresponding to the absence of abnormality information, and this display data differs from the display data corresponding to the abnormality information. Therefore, when abnormality information does not exist, the display contents of the third and fourth notification display devices 203 and 204 are different from the display contents when abnormality information exists.

On the other hand, the display contents of the display corresponding to the abnormal state information on the third and fourth notification display devices 203, 204 and the display contents of the display corresponding to the absence of abnormal state information overlap with the display contents when the game history management results are displayed on the third and fourth notification display devices 203, 204 and the display contents of the setting value on the fourth notification display device 204. In contrast, when the game history management results are displayed, all of the first to fourth notification display devices 201-204 are in a display state, and in a changeable state in which the setting state of the pachinko machine 10 can be changed, the first to third notification display devices 201-203 are in a non-display state and the fourth notification display device 204 is in a display state, and when an abnormality is displayed, the first and second notification display devices 201, 202 are in a non-display state and the third and fourth notification display devices 203, 204 are in a display state, so that even if the display contents overlap as described above, the manager of the game hall can understand which situation the display corresponds to.

Then, the display of the third alarm display device 203 is controlled according to the display data read in step S3407 (step S3408), and the display of the fourth alarm display device 204 is controlled (step S3409). In this case, whether a display corresponding to information on an abnormal state is made or a display corresponding to the absence of information on an abnormal state is made, neither the third alarm display device 203 nor the fourth alarm display device 204 is in a non-display state (i.e., they are not in a completely off state), but in some display state.

Then, the update timing counter in the main RAM 65 is set to a value corresponding to 2 seconds as the value corresponding to the next update timing (step S3410).

The present embodiment described above provides the following excellent advantages:

In a configuration in which the results of game history management are displayed on the first to fourth notification display devices 201 to 204, displays corresponding to abnormal conditions of the pachinko machine 10 are made on the first to fourth notification display devices 201 to 204. This makes it possible to use the first to fourth notification display devices 201 to 204 not only for displaying the results of game history management, but also as display devices for making displays corresponding to abnormal conditions.

When the first to fourth display devices 201 to 204 are made to display an abnormal state when no abnormal state has occurred in the pachinko machine 10, the first to fourth display devices 201 to 204 display an indication that no abnormal state has occurred. This makes it possible to clearly identify whether or not an abnormal state has occurred in the pachinko machine 10 by checking the first to fourth display devices 201 to 204.

A distinction is made between the period during which the first to fourth alert display devices 201-204 display the game history management results and the period during which the first to fourth alert display devices 201-204 display information corresponding to abnormal conditions of the pachinko machine 10. This makes it possible to identify which display is being made on the first to fourth alert display devices 201-204 by understanding the status of the display being made on the first to fourth alert display devices 201-204.

When a display corresponding to an abnormal state of the pachinko machine 10 is made, the first to fourth notification display devices 201 to 204 are controlled to display in a different manner than when the results of the game history management are displayed. This makes it possible to identify which display is being made on the first to fourth notification display devices 201 to 204 by grasping the display manner of the first to fourth notification display devices 201 to 204.

Multiple notification display devices 201-204 are provided. This makes it possible to perform a wide variety of displays corresponding to the results of game history management. Furthermore, the presence of multiple notification display devices 201-204 makes it possible to greatly differ the display mode when the results of game history management are displayed from when a display corresponding to an abnormal state of the pachinko machine 10 is performed.

When a display corresponding to an abnormal state of the pachinko machine 10 is made, the first and second notification display devices 201, 202, which are not in a hidden state when displaying the game history management results, are in a hidden state. This makes it possible to clearly identify which of the display of the game history management results and the display corresponding to the abnormal state of the pachinko machine 10 is being made by the first to fourth notification display devices 201-204, simply by checking whether the first and second notification display devices 201, 202 are in a hidden state.

When a display corresponding to an abnormal state of the pachinko machine 10 is made, the third and fourth notification display devices 203, 204 are in a display state, and the display contents are the display contents that can be displayed on the third and fourth notification display devices 203, 204 when displaying the game history management results. By allowing the display contents on the third and fourth notification display devices 203, 204 to overlap in this way, it is possible to avoid restricting the display contents when the game history management results are displayed and when a display corresponding to an abnormal state of the pachinko machine 10 is made. Even if the display contents on the third and fourth notification display devices 203, 204 are configured to overlap in this way, when a display corresponding to an abnormal state of the pachinko machine 10 is made, the first and second notification display devices 201, 202 are made in a non-display state, so it is possible to identify which display is being made on the first to fourth notification display devices 201 to 204.

In addition, if an operation to start the abnormality display is performed when no abnormality information is stored in the abnormality display area 211, a display corresponding to the fact that no abnormality information is stored at that time may be displayed in the first to fourth alarm display devices 201 to 204.

<Fourteenth embodiment>
In this embodiment, the processing configuration of the management output process executed by the main CPU 63 is different from that of the first embodiment. The configurations different from the first embodiment will be described below. Note that the description of the same configurations as the first embodiment will basically be omitted.

Figure 65 is a flowchart showing the management output process in this embodiment executed by the main CPU 63.

First, it is determined whether the management start flag provided in the main RAM 65 is set to "1" (step S3501). The management start flag is a flag for the main CPU 63 to specify whether or not it is a situation in which history information should be stored in the history memory 117. In this embodiment, after the supply of operating power to the pachinko machine 10 has started (i.e., after the supply of operating power to the MPU 62 has started), the history memory 117 does not store history information until the total number of game balls discharged from the play area PA becomes equal to or greater than the number corresponding to the management start reference value, and when the total number of game balls discharged from the play area PA becomes equal to or greater than the number corresponding to the management start reference value, the history memory 117 starts storing history information. At the shipping stage of the pachinko machine 10, the operation of the pachinko machine 10 may be checked before shipping, and at that time, game balls are placed in each ball entry section and the subsequent operation is checked. In response to this, by not storing history information in the history memory 117 until the total number of game balls discharged from the play area PA after the supply of operating power to the pachinko machine 10 begins reaches or exceeds the management start reference value, it is possible to prevent ball entry results and the like during the above-mentioned operation check from being stored as history information.

If a negative judgment is made in step S3501, the start management counter provided in the main RAM 65 is set to "7" (step S3502). The start management counter is a counter that allows the main CPU 63 to determine which of the seven ball entry detection sensors 42a to 48a is in a situation where the ball detection state needs to be determined when the management start flag is not set to "1".

Then, it is determined whether the output flag of the main RAM 65 corresponding to the value of the start-time management counter is set to "1" (step S3503). Specifically, if the value of the start-time management counter is "7" and corresponds to the first winning port detection sensor 42a, it is determined whether the first output flag is set to "1", if the value of the start-time management counter is "6" and corresponds to the second winning port detection sensor 43a, it is determined whether the second output flag is set to "1", if the value of the start-time management counter is "5" and corresponds to the third winning port detection sensor 44a, it is determined whether the third output flag is set to "1", if the value of the start-time management counter is "4" and corresponds to the special power detection sensor 45a, it is determined whether the third ...5" and corresponds to the special power detection sensor 45a, it is determined whether the third output flag is set to "1", if the value of the start-time management counter is "5" and corresponds to the special power detection sensor 45a, it is determined whether the third output flag is set to "1", if the value of the start-time management counter is "5" and corresponds to the special power detection sensor 45a, it is determined whether the third output flag is set to "1", if the value of the start-time management counter is "5" and corresponds to the special power detection sensor 45a, it is determined whether the third output flag is set to "1", if the value of the start-time management counter is " If the value of the start management counter is "3" and corresponds to the first actuation port detection sensor 46a, the fifth output flag is determined to be set to "1". If the value of the start management counter is "2" and corresponds to the second actuation port detection sensor 47a, the sixth output flag is determined to be set to "1". If the value of the start management counter is "1" and corresponds to the out port 24a, the seventh output flag is determined to be set to "1". As already explained, the first to seventh output flags are set to "1" in the ball entry detection process (Figure 15).

If a positive judgment is made in step S3503, the output flag corresponding to the value of the start-time management counter is cleared to "0" (step S3504). After that, the value of the discharged ball number counter provided in the main RAM 65 is incremented by 1 (step S3505). The discharged ball number counter is a counter that allows the main CPU 63 to determine the total number of game balls discharged from the game area PA when the management start flag in the main RAM 65 is not set to "1".

Then, it is determined whether the value of the discharged number counter is equal to or greater than the management start reference value (step S3506). The management start reference value is set to "300", but is not limited to this and may be a number less than "300" or a number greater than "300".

If a negative judgment is made in step S3503, or if a negative judgment is made in step S3506, the value of the start-time management counter in the main RAM 65 is decremented by 1 (step S3507). Then, it is determined whether the value of the start-time management counter after the decrement is "0" (step S3508). If a negative judgment is made in step S3508, the process returns to step S3503, and if a positive judgment is made in step S3508, the management output process is terminated.

On the other hand, if the value of the discharged number counter in the main RAM 65 is equal to or greater than the management start reference value (step S3506: YES), the management start flag in the main RAM 65 is set to "1" (step S3509). Then, management processing is executed (step S3510). Also, if the management start flag is set to "1" and a positive judgment is made in step S3501, management processing is executed (step S3510). The processing content of the management processing is the same as steps S1001 to S1012 of the management output processing (Figure 25) in the first embodiment described above.

According to the above configuration, after the supply of operating power to the pachinko machine 10 has started (i.e., after the supply of operating power to the MPU 62 has started), the history memory 117 does not store history information until the total number of game balls discharged from the play area PA reaches or exceeds the number corresponding to the management start reference value, and when the total number of game balls discharged from the play area PA reaches or exceeds the number corresponding to the management start reference value, the history memory 117 starts storing history information. At the shipping stage of the pachinko machine 10, an operation check of the pachinko machine 10 may be performed before shipping, and at that time, game balls are placed in each ball entry section and the subsequent operation is checked. In contrast, by not storing history information in the history memory 117 until the total number of game balls discharged from the play area PA reaches or exceeds the management start reference value after the supply of operating power to the pachinko machine 10 has started, it is possible to prevent the ball entry results during the above-mentioned operation check from being stored as history information.

In the configuration in which the history information is not stored in the history memory 117 until the total number of game balls discharged from the play area PA after the supply of operating power to the pachinko machine 10 is started as described above reaches or exceeds the number corresponding to the management start reference value, the management result of the game history during that period cannot be calculated. In such a situation, the first to fourth notification display devices 201 to 204 may be configured to display a message corresponding to the situation. For example, the first to fourth notification display devices 201 to 204 may be configured to have all display segments illuminated. The display content is not displayed in either the case of displaying the game history management result or the case of displaying the changeable state in which the setting state of the pachinko machine 10 can be changed, so that it is possible to identify whether the situation is such that the history information is not stored by checking the first to fourth notification display devices 201 to 204.

The setting state of the information of the management start flag of the main RAM 65 may be different depending on whether the setting state of the pachinko machine 10 is in a changeable state in which it is possible to change the setting state of the pachinko machine 10 after the start of the supply of operating power to the pachinko machine 10. FIG. 66 is a flowchart showing the main processing in this alternative embodiment executed by the main CPU 63. In steps S3601 to S3609, the same processing as steps S101 to S109 of the main processing (FIG. 9) in the first embodiment is executed, and in steps S3611 to S3620, the same processing as steps S110 to S119 of the main processing (FIG. 9) in the first embodiment is executed. On the other hand, in this alternative embodiment, if a positive judgment is made in step S3608, the management start flag of the main RAM 65 is cleared to "0" (step S3610), and after executing the processing of step S3620, the management start flag of the main RAM 65 is set to "1" (step S3621). According to this configuration, if the process for setting a new setting state of the pachinko machine 10 is not executed, the history memory 117 is prevented from storing history information until the total number of game balls discharged from the play area PA after the supply of operating power to the pachinko machine 10 begins becomes equal to or greater than the management start reference value, and if the process for setting a new setting state of the pachinko machine 10 is executed, the history memory 117 stores history information regardless of the number of game balls discharged after the supply of operating power to the pachinko machine 10 begins. This makes it possible to manage the game history immediately after the supply of operating power to the pachinko machine 10 begins in a situation where there is a high possibility that the operation check at the time of shipment of the pachinko machine 10 will not be applicable.

In addition, instead of a configuration in which history information is not stored in the history memory 117 until the total number of game balls discharged from the play area PA after the supply of operating power to the pachinko machine 10 begins reaches or exceeds the management start reference value, a configuration may be adopted in which an area is provided separate from the history memory 117 for storing history information until the total number of game balls reaches or exceeds the management start reference value. This makes it possible to identify the management results of the game history in that situation.

In addition, as a condition for the occurrence of a situation in which history information is not stored in the history memory 117 from when the supply of operating power to the pachinko machine 10 begins until the total number of game balls discharged from the play area PA becomes equal to or greater than the management start reference value, a condition may be added in which the supply of operating power to the pachinko machine 10 begins when no history information is stored in the history memory 117. In this case, if the supply of operating power to the pachinko machine 10 begins when history information is already stored in the history memory 117, history information will be stored in the history memory 117 from the beginning, regardless of whether the total number of game balls discharged from the play area PA becomes equal to or greater than the management start reference value.

In addition to or instead of a configuration in which history information is not stored in the history memory 117 until the total number of game balls discharged from the play area PA after the supply of operating power to the pachinko machine 10 begins reaches or exceeds the management start reference value, if an abnormal state such as a radio wave detection abnormality or vibration detection abnormality occurs, history information may not be stored in the history memory 117 until the abnormal state is resolved. This makes it possible to prevent history information from being stored for events that occur in an abnormal state.

In addition to or instead of a configuration in which history information is not stored in the history memory 117 until the total number of game balls discharged from the game area PA after the supply of operating power to the pachinko machine 10 begins reaches or exceeds the management start reference value, history information may not be stored in the history memory 117 when the game machine main body 12 or the front door frame 14 is open. This makes it possible to prevent history information from being stored for events that occur when the game machine main body 12 or the front door frame 14 is open.

<Fifteenth embodiment>
In this embodiment, the entity that executes the process for managing the game history is different from that of the first embodiment. The following describes the configuration that is different from the first embodiment. Note that the description of the same configuration as the first embodiment will basically be omitted.

In the first embodiment, the MPU 62 is provided with a management IC 66, but in this embodiment, the MPU 62 is not provided with a management IC 66. Instead of providing a management IC 66, in this embodiment, the main CPU 63 executes processing for managing the game history. In addition, in this embodiment, the main CPU 63 executes various controls by distinguishing between specific control and non-specific control. Specifically, control related to the management of the game history is considered to be non-specific control, and control other than non-specific control, including control for progressing the game based on the game operation by the player, is considered to be specific control.

Specifically, the specific control includes all of the controls by the main processing (FIG. 9) that are executed when the supply of operating power to the main CPU 63 is started. In this embodiment, the recognition process (step S111), the data output process (step S112), and the setting value update signal output process (step S119) of the main processing (FIG. 9) in the first embodiment are not executed. In this embodiment, the timer interrupt process is periodically executed by interrupting the processes in steps S113 to S116 in the main processing (FIG. 9), and all of the various processes in the timer interrupt process other than the management process described below are included in the specific control. In addition, some of the management processes are also included in the specific control.

Figure 67 is an explanatory diagram for explaining the setting mode of programs and data in the main ROM 64. In accordance with the distinction between specific control and non-specific control in the control executed by the main CPU 63, as shown in Figure 67, the addresses of the areas in the main ROM 64 where programs and data for specific control are stored and programs and data for non-specific control are stored are clearly distinguished.

Specifically, specific control programs are stored in a concentrated manner in the area of each successive address within the range of addresses X(1) to X(k+2). In addition, addresses X(k+3) to X(k+5) successive to addresses X(1) to X(k+2) are unused area addresses where no data is stored, and specific control data are stored in a concentrated manner in the area of each successive address within the range of addresses X(k+6) to X(m+2). In addition, addresses X(m+3) to X(m+5) successive to addresses X(k+6) to X(m+2) are unused area addresses where no data is stored, and non-specific control programs are stored in a concentrated manner in the area of each successive address within the range of addresses X(m+6) to X(n+2). In addition, addresses X(n+3) to X(n+5) that are consecutive to addresses X(m+6) to X(n+2) are unused area addresses where no data is stored, and non-specific control data is collectively stored in each consecutive address area within the range of addresses X(n+6) to X(p+2). The relationship between the above programs and data and addresses is set in both the physical addresses in the main ROM 64 and the logical addresses on the memory map recognized by the main CPU 63.

As described above, the program and data for specific control and the program and data for non-specific control are stored in different address ranges regardless of the execution order of the process for executing the corresponding control. Therefore, when checking only the program and data for specific control, it is necessary to check only the address range area in which the program and data for specific control are stored, and when checking only the program and data for non-specific control, it is necessary to check only the address range area in which the program and data for non-specific control are stored. Therefore, it is possible to efficiently check the program and data for specific control and non-specific control separately. It is also possible to efficiently correct the program and data for specific control and non-specific control separately.

By setting an address range for an unused area in which no data is stored between the address range of the area in which the program for specific control and the data for specific control are stored and the address range of the area in which the program for non-specific control and the data for non-specific control are stored, it becomes easier to grasp the boundary between the address range for specific control and the address range for non-specific control when performing a check.

In the address range for specific control and the address range for non-specific control, programs and data are stored in different address ranges, regardless of the execution order of the processes for executing the corresponding controls, which makes it possible to efficiently check programs and data separately. In addition, an address range for an unused area in which no data is stored is set between the address range of the area in which the program is stored and the address range of the area in which the data is stored, which makes it easier to grasp the boundary between the address range of the program and the address range of the data when checking.

Figure 68 is an explanatory diagram for explaining the setting mode of each area in the main RAM 65. In accordance with the fact that the control executed by the main CPU 63 is distinguished between specific control and non-specific control, as shown in Figure 68, the address range of the work area 221 for specific control and the stack area 222 for specific control is also clearly distinguished from the address range of the work area 223 for non-specific control and the stack area 224 for non-specific control in the main RAM 65.

Specifically, the area of each successive address within the range of addresses Y(1) to Y(r+2) is set as the work area 221 for specific control. In addition, addresses Y(r+3) to Y(r+5) successive to addresses Y(1) to Y(r+2) are unused area addresses, and the area of each successive address within the range of addresses Y(r+6) to Y(s+2) is set as the stack area 222 for specific control. In addition, addresses Y(s+3) to Y(s+5) successive to addresses Y(r+6) to Y(s+2) are unused area addresses, and the area of each successive address within the range of addresses Y(s+6) to Y(t+2) is set as the work area 223 for non-specific control. Additionally, addresses Y(t+3) to Y(t+5) that are successive to addresses Y(s+6) to Y(t+2) are unused area addresses, and the areas of successive addresses within the range of addresses Y(t+6) to Y(u+2) are set as stack areas 224 for non-specific control. The relationship between each area and address as described above is set in both the physical addresses in the main RAM 65 and the logical addresses on the memory map recognized by the main CPU 63.

As described above, the work area 221 for specific control and the work area 223 for non-specific control are set separately, so that different areas of the main RAM 65 are used when performing various calculations when the main CPU 63 executes specific control and when it executes non-specific control. This makes it possible to prevent an event from occurring in which information in the main RAM 65 required for the execution of one of specific control and non-specific control is erased when the other is executed. Incidentally, a load command is issued by the main CPU 63 when writing information to each work area 221, 223 and reading information from each work area 221, 223.

By setting the stack area 222 for specific control and the stack area 224 for non-specific control separately, different areas of the main RAM 65 are used when saving information stored in the register of the main CPU 63 and when storing information of the return address in the program when the main CPU 63 executes specific control and non-specific control. This makes it possible to prevent an event in which information used in the other is erased when saving information stored in the register of the main CPU 63 and storing information of the return address in the program while one of the specific control and non-specific control is being executed. Incidentally, when writing information to each stack area 222, 224, a push command is issued by the main CPU 63, and when reading information from each stack area 222, 224, a pop command is issued by the main CPU 63. When reading information from each stack area 222, 224, the writing order to the stack areas 222, 224 is such that the later information is read first.

Here, when the main CPU 63 executes processing corresponding to specific control, the main CPU 63 can write information to the work area 221 for specific control and the stack area 222 for specific control, and can read information from the work area 221 for specific control and the stack area 222 for specific control. On the other hand, when the main CPU 63 executes processing corresponding to specific control, the main CPU 63 can read information from the work area 223 for non-specific control and the stack area 224 for non-specific control, but cannot write information to the work area 223 for non-specific control and the stack area 224 for non-specific control. This makes it possible to prevent information used in processing corresponding to non-specific control from being accidentally erased when processing corresponding to specific control is being executed.

In addition, when the main CPU 63 executes processing corresponding to non-specific control, the main CPU 63 can write information to the work area 223 for non-specific control and the stack area 224 for non-specific control, and can read information from the work area 223 for non-specific control and the stack area 224 for non-specific control. On the other hand, when the main CPU 63 executes processing corresponding to non-specific control, the main CPU 63 can read information from the work area 221 for specific control and the stack area 222 for specific control, but cannot write information to the work area 221 for specific control and the stack area 222 for specific control. This makes it possible to prevent information used in processing corresponding to specific control from being accidentally erased when processing corresponding to non-specific control is being executed.

Note that backup power is supplied to the main RAM 65 even after the power to the pachinko machine 10 is cut off, and this backup power is supplied to all of the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control. As a result, the information stored in the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control is retained as long as backup power is being supplied, even after the power to the pachinko machine 10 is cut off.

Next, the timer interrupt processing in this embodiment executed by the main CPU 63 will be described with reference to the flowchart in FIG. 69. The timer interrupt processing is executed periodically (e.g., every 4 milliseconds) when the processing of steps S113 to S116 is being executed in the main processing (FIG. 9) in the same manner as in the first embodiment. Note that the program corresponding to the timer interrupt processing is set in the program for specific control.

Steps S3701 to S3718 execute the same processing as steps S301 to S318 of the timer interrupt processing (FIG. 11) in the first embodiment. These processes are executed by the main CPU 63 using a program for specific control and data for specific control. In step S3719 in the timer interrupt processing, management processing is executed. When the management processing is executed, a subroutine program corresponding to the management processing set in the program for specific control is executed, and when the subroutine program is executed, information for specifying the return address of the timer interrupt processing after the management processing is executed is written to the stack area 222 for specific control by a push command. Then, when the management processing is completed, information for specifying the return address is read by a pop command, and the program returns to the timer interrupt processing program indicated by the return address.

Figure 70 is a flowchart showing the management process. Note that steps S3801 to S3805 in the management process are executed by the main CPU 63 using a program for specific control and data for specific control.

First, to prohibit the occurrence of timer interrupt processing (FIG. 69), interrupt prohibition is set (step S3801). This makes it possible to prevent the timer interrupt processing (FIG. 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

After that, the information in the flag register of the main CPU 63 is saved to the specific control stack area 222 by the push command "PUSH PSW" (step S3802). The flag register includes a carry flag, zero flag, P/V flag, sign flag, and half carry flag, and the information in the flag register changes depending on the execution results of arithmetic instructions, rotate instructions, input/output instructions, and the like. By saving such flag register information before the program of the subroutine corresponding to the management execution process is started, it becomes possible to save the flag register information in the state before it changes after the call of the subroutine or the start of the subroutine in the specific control stack area 222. The amount of information in the flag register is 1 byte.

Then, the management execution process is started by reading out a subroutine program corresponding to the management execution process set in the program for non-specific control (step S3803). In this case, information for specifying the return address of the management process after the management execution process is executed is written into the stack area 222 for specific control by a push command. Then, when the management execution process is completed, information for specifying the return address is read out by a pop command, and the process returns to the program for the management process indicated by the return address.

When returning to the management processing program after the management execution processing is executed, the flag register information saved in the stack area 222 for specific control in step S3802 is restored to the flag register of the main CPU 63 by a pop command as "POP PSW" (step S3804). This causes the flag register information of the main CPU 63 to return to the information at the time step S3802 was executed. In other words, the flag register information of the main CPU 63 returns to the information for executing specific control.

Then, the interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing (FIG. 69) is prohibited to a state in which it is permitted (step S3805). This allows a new execution of the timer interrupt processing.

Figure 71 is a flowchart showing the management execution process. Note that steps S3901 to S3915 in the management execution process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

First, the load command sets "LD SP, Y(u+2)" to the stack pointer of the main CPU 63 as a fixed address at the start of non-specific control (step S3901). The stack pointer is an area in which address information is set for the main CPU 63 to specify the storage area to which information is to be written by the push command in the stack areas 222 and 224. Each time a push command is executed, the stack pointer information is updated to the address information of the storage area to which the next order is to be written, and each time a pop command is executed, the stack pointer information is updated to the address information of the storage area to which the previous order is to be written. In addition, when the stack area 224 for non-specific control is used, the information to be stored is stored from the storage area of the last address in the stack area 224 for non-specific control, and each time information to be stored is added, the storage area to be stored is changed to the first address side in the stack area 224 for non-specific control. Therefore, in step S3901, the stack pointer is set to the information of the last address in the stack area 224 for non-specific control. This same process of storing information from the memory area with the last address to the memory area with the first address also applies to the stack area 222 for specific control.

Incidentally, for both the specific control stack area 222 and the non-specific control stack area 224, if an additional push command is executed even though information has been set in all memory areas, all areas of the main RAM 65 are cleared to "0" as an abnormality has occurred in the memory process. This makes it possible to prevent the game from continuing as is despite an abnormality occurring in the memory process.

Thereafter, the information in the WA register of the master CPU 63 is saved to the WA buffer set in the work area 223 for non-specific control by a load command as "LD (_WABUF), WA" (step S3902). Also, the information in the BC register of the master CPU 63 is saved to the BC buffer set in the work area 223 for non-specific control by a load command as "LD (_BCBUF), BC" (step S3903). Also,
The load command is "LD (_DEBUF), DE" to save the information in the DE register of the master CPU 63 to the DE buffer set in the work area 223 for non-specific control (step S3904). The load command is "LD (_HLBUF), HL" to save the information in the HL register of the master CPU 63 to the HL buffer set in the work area 223 for non-specific control (step S3905). The load command is "LD (_IXBUF), IX" to save the information in the IX register of the master CPU 63 to the IX buffer set in the work area 223 for non-specific control (step S3906). The load command is "LD (_IYBUF), IY" to save the information in the IY register of the master CPU 63 to the IY buffer set in the work area 223 for non-specific control (step S3907).

In addition to the flag register already described, the main CPU 63 also contains various general-purpose registers, auxiliary registers, and index registers. In this case, in steps S3902 to S3907, the information of some of these general-purpose registers, auxiliary registers, and index registers, namely the WA register, BC register, DE register, HL register, IX register, and IY register, is saved to the corresponding buffer in the non-specific control work area 223. Note that the amount of information in the WA register, BC register, DE register, HL register, IX register, and IY register is all 2 bytes.

The WA register, BC register, DE register, HL register, IX register, and IY register are registers used in the check process (step S3908), which is a process corresponding to non-specific control. By saving the information set in such registers to the work area 223 for non-specific control prior to execution of the check process (step S3908), it is possible to save the information in these registers used during specific control before non-specific control is started. Therefore, even if these registers are overwritten during non-specific control, by restoring the information saved in the work area 223 for non-specific control to these registers when non-specific control is terminated, it is possible to restore the state of these registers to the state corresponding to specific control before non-specific control was executed.

In addition, instead of saving all the information of the various general-purpose registers, auxiliary registers, and index registers to the work area 223 for non-specific control, the information of the WA register, BC register, DE register, HL register, IX register, and IY register to be used in the check process, which is a process corresponding to the non-specific control, is selectively saved to the work area 223 for non-specific control, thereby making it possible to reduce the capacity reserved for saving the register information in the work area 223 for non-specific control. Therefore, it is possible to save the above-mentioned register information while securing a large capacity of the work area 223 for non-specific control that is available during the check process. Of course, for the various general-purpose registers, auxiliary registers, and index registers in the main CPU 63 other than the WA register, BC register, DE register, HL register, IX register, and IY register, the information set before the process corresponding to the non-specific control is started is stored and held until the process corresponding to the non-specific control is completed and the process corresponding to the specific control is resumed.

In addition, by saving the register information to the work area 223 for non-specific control instead of saving it to the stack area 224 for non-specific control, it is possible to keep the capacity of the stack area 224 for non-specific control small. In addition, when using the stack area 224 for non-specific control, as already explained, the writing order of information is such that later information is read out first. Therefore, if the reading order of information is shifted due to some kind of noise or the like, all information in the subsequent reading order will be restored to different registers. The probability of such an event occurring increases as the amount of information saved to the stack area 224 for non-specific control increases. In contrast, by saving the register information to the work area 223 for non-specific control, it is possible to prevent such an event from occurring even when there is a lot of information to be saved.

After the processes of steps S3902 to S3907 are executed, a check process is executed (step S3908). When the check process is executed, a subroutine program corresponding to the check process set in the program for non-specific control is executed, and when the program for the subroutine is executed, information for specifying the return address of the management execution process after the execution of the check process is written to the stack area 224 for non-specific control by a push command. Then, when the check process is completed, information for specifying the return address is read by a pop command, and the program returns to the program for the management execution process indicated by the return address. Details of the check process will be explained later.

After the check process is executed, a load command is issued to set Y(r+α) in the stack pointer of the main CPU 63 as a fixed address at the time of returning to specific control, as "LD SP, Y(r+α)" (step S3909). The address of Y(r+α) is set as an address between Y(r+8) and Y(s) in the stack area 222 for specific control.

The amount of information stored in the stack area 222 for specific control immediately before the subroutine of the management execution process is executed in step S3803 of the management process (FIG. 70) is always constant, and accordingly, the information of the stack pointer of the main CPU 63 at that timing (i.e., the value of the stack pointer) is constant. In this case, the information stored in the stack area 222 for specific control includes, for example, the return address information of the management process (FIG. 70) after the management execution process (FIG. 71) is completed, and the return address information of the timer interrupt process (FIG. 69) after the management process (FIG. 70) is completed. The above-mentioned fixed information of the stack pointer is Y(r+α). Therefore, when the check process, which is the process corresponding to the non-specific control, is completed and the process corresponding to the specific control is returned to, the fixed information Y(r+α) is set in the stack pointer of the main CPU 63, thereby making it possible to restore the information of the stack pointer to the information immediately before the process corresponding to the non-specific control is started. By setting fixed information in the stack pointer in this way, the stack pointer information is restored to the information immediately before the processing corresponding to the non-specific control is started, eliminating the need to save the stack pointer information of the main CPU 63 corresponding to the specific control in the main RAM 65 before starting the processing corresponding to the non-specific control. This makes it possible to reduce the processing load and eliminates the need to reserve an area in the main RAM 65 for the save.

Then, the information saved in the WA buffer of the work area 223 for non-specific control is overwritten in the WA register of the main CPU 63 by a load command as "LD WA, (_WABUF)" (step S3910). Also, the information saved in the BC buffer of the work area 223 for non-specific control is overwritten in the BC register of the main CPU 63 by a load command as "LD BC, (_BCBUF)" (step S3911). Also, the information saved in the DE buffer of the work area 223 for non-specific control is overwritten in the DE register of the main CPU 63 by a load command as "LD DE, (_DEBUF)" (step S3912). Also, the information saved in the HL buffer of the work area 223 for non-specific control is overwritten in the HL register of the main CPU 63 by a load command as "LD HL, (_HLBUF)" (step S3913). Also, the load command "LD IX, (_IXBUF)" overwrites the IX register of the main CPU 63 with the information saved in the IX buffer of the work area 223 for non-specific control (step S3914). Also, the load command "LD IY, (_IYBUF)" overwrites the IY register of the main CPU 63 with the information saved in the IY buffer of the work area 223 for non-specific control (step S3915). By executing the processes of steps S3910 to S3915, it is possible to restore the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 to the information corresponding to specific control immediately before the process corresponding to non-specific control is started.

Here, when processing corresponding to non-specific control is executed, the information stored in the flag register and various registers of the main CPU 63 is not saved to the main RAM 65 when processing corresponding to specific control is resumed. This eliminates the need to secure a memory area for saving the above information in the work area 221 for specific control and the stack area 222 for specific control.

In addition, the information stored in the flag register and various registers of the main CPU 63 when processing corresponding to non-specific control is executed is information that will not be used when processing corresponding to non-specific control is started again after returning to processing corresponding to specific control. In other words, information required for multiple processing times of processing corresponding to non-specific control executed with processing corresponding to specific control in between is stored in the work area 223 for non-specific control or the stack area 224 for non-specific control, and is not stored in the flag register and various registers of the main CPU 63. Therefore, even if the information stored in the flag register and various registers of the main CPU 63 is not saved to the main RAM 65 when processing corresponding to non-specific control is executed, no problem occurs in executing processing corresponding to non-specific control.

Next, the check process executed by calling a subroutine program in step S3908 will be described. This check process executes a process for collecting information on game history, a process for deriving the results of game history management, and a process for notifying the results of that management. In other words, the process for collecting information on game history, a process for deriving the results of game history management, and a process for notifying the results of that management are executed as processes corresponding to non-specific control.

Before explaining the check process, we will explain the contents of the various areas 231-234 of the work area 223 for non-specific control that are used to manage the game history. Figure 72 is an explanatory diagram for explaining the various areas 231-234 of the work area 223 for non-specific control that are used to manage the game history.

The non-specific control work area 223 is provided with a normal counter area 231, an open/close execution mode counter area 232, and a high-frequency support mode counter area 233. Each of these areas 231 to 233 is provided with a general winning counter 231a, 232a, 233a, a special line winning counter 231b, 232b, 233b, a first operation counter 231c, 232c, 233c, a second operation counter 231d, 232d, 233d, and an out counter 231e, 232e, 233e. The general winning counters 231a, 232a, 233a are counters for counting the number of game balls that enter the general winning port 31 from a predetermined measurement start trigger. The special electric winning counters 231b, 232b, and 233b are counters for counting the number of game balls that enter the special electric winning device 32 from a predetermined measurement start trigger. The first operation counters 231c, 232c, and 233c are counters for counting the number of game balls that enter the first operation port 33 from a predetermined measurement start trigger. The second operation counters 231d, 232d, and 233d are counters for counting the number of game balls that enter the second operation port 34 from a predetermined measurement start trigger. The out counters 231e, 232e, and 233e are counters for counting the number of game balls that enter the out port 24a from a predetermined measurement start trigger.

The counters 231a to 231e in the normal counter area 231 are used to count the number of game balls that have entered the target ball entry sections 24a, 31 to 34 when the front door frame 14 is closed and the game is not in the open/close execution mode or the high-frequency support mode. The counters 232a to 232e in the open/close execution mode counter area 232 are used to count the number of game balls that have entered the target ball entry sections 24a, 31 to 34 when the front door frame 14 is closed and the game is in the open/close execution mode. The counters 233a to 233e in the high-frequency support mode counter area 233 are used to count the number of game balls that have entered the target ball entry sections 24a, 31 to 34 when the front door frame 14 is closed and the game is in the high-frequency support mode.

The reason why the situation where the front door frame 14 is in an open state is not included in the measurement is to exclude from the measurement the number of balls that enter the ball entry sections 24a, 31-34 by hand when the front door frame 14 is open. However, this is not limited to this, and the situation where the front door frame 14 is in an open state may be included in the measurement in the same way as the situation where the front door frame 14 is in a closed state.

In addition to the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233, the non-specific control work area 223 also has a calculation result storage area 234. The calculation result storage area 234 is an area for storing information on the game history management results calculated using the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233. The game history management result information stored in the calculation result storage area 234 is stored and held until the newly calculated game history management result information is overwritten by the newly calculated information.

Figure 73 is a flowchart showing the check process executed by calling the subroutine program in step S3908. The processes in steps S4001 to S4008 in the check process, including the subroutine process, are executed in the main CPU 63 using the non-specific control program and non-specific control data. When the subroutine process is executed, the return address information after the execution of the subroutine process is written in the non-specific control stack area 224 in the storage area corresponding to the current stack pointer value of the main CPU 63, and the stack pointer value is updated to the address information of the storage area to be stored in the next order. When the subroutine process is completed, the return address information is read from the storage area corresponding to the previous order value with respect to the current stack pointer value of the main CPU 63, and the program corresponding to the return address information is returned to, and the stack pointer value is updated to the address information of the storage area from which the return address information was read.

In the check process, if the front door frame 14 is in the open state (step S4001: YES), the normal ball entry management process (step S4004), the ball entry management process during the open/close execution mode (step S4005), and the ball entry management process during the high frequency support mode (step S4006) are not executed, and the result calculation process (step S4007) and display process (step S4008) described below are executed. Since the game area PA is formed by the space partitioned in front and back by the back surface of the window panel 52 provided in the front door frame 14 and the front surface of the game board 24, when the front door frame 14 is in the open state, the game area PA is opened toward the front, and even if a game ball is launched toward the game area PA in this situation, the game ball cannot flow down the game area PA normally. Furthermore, when game balls enter the ball entry sections 24a, 31-34 while the front door frame 14 is open, this occurs when the manager of the amusement hall opens the front door frame 14 for maintenance or to resolve malfunctions, and game balls enter as a result of care, etc. This type of game ball entry is not a game ball that enters during normal game play, so there is no need to manage such game ball entries. Therefore, in the check process, none of the processes in steps S4004 to S4006 are executed when the front door frame 14 is open as described above.

If the front door frame 14 is closed and is not in the opening/closing execution mode or the high-frequency support mode (steps S4001 to S4003: NO), normal goal entry management processing is executed (step S4004). Also, if the front door frame 14 is closed and is in the opening/closing execution mode (step S4001: NO, step S4002: YES), goal entry management processing during the opening/closing execution mode is executed (step S4005). Also, if the front door frame 14 is closed and is in the high-frequency support mode (step S4001: NO, step S4003: YES), goal entry management processing during the high-frequency support mode is executed (step S4006).

Figure 74 is a flowchart showing the normal entry management process in step S4004.

When it is determined that one game ball has been detected by the first winning hole detection sensor 42a (step S4101: YES), i.e., when it is confirmed that the signal received from the first winning hole detection sensor 42a has switched from LOW level to HIGH level, when it is determined that one game ball has been detected by the second winning hole detection sensor 43a (step S4103: YES), i.e., when it is confirmed that the signal received from the second winning hole detection sensor 43a has switched from LOW level to HIGH level, or when it is determined that one game ball has been detected by the third winning hole detection sensor 44a (step S4105: YES), i.e., when it is confirmed that the signal received from the third winning hole detection sensor 44a has switched from LOW level to HIGH level, the value of the normal general winning counter 231a is incremented by 1 (steps S4102, S4104, S4106).

If the ball entry management process is performed during the opening and closing execution mode, the value of the general winning counter 232a for the opening and closing execution mode is incremented by 1 as the process corresponding to steps S4102, S4104, and S4106, and if the ball entry management process is performed during the high frequency support mode, the value of the general winning counter 233a for the high frequency support mode is incremented by 1 as the process corresponding to steps S4102, S4104, and S4106. In addition, in the ball entry detection process (step S3709) of the timer interrupt process (FIG. 69) executed as the process corresponding to the specific control, the detection results of the first to third winning hole detection sensors 42a to 44a are also monitored, and if it is determined that one game ball has been detected by any of the first to third winning hole detection sensors 42a to 44a, a process is executed to pay out the number of game balls corresponding to the general winning hole 31.

If it is determined that one game ball has been detected by the special electric detection sensor 45a (step S4107: YES), that is, if it is confirmed that the signal received from the special electric detection sensor 45a has switched from a LOW level to a HIGH level, the value of the normal special electric winning counter 231b is incremented by 1 (step S4108).

If the ball entry management process is during the opening and closing execution mode, the value of the special electric winning counter 232b for the opening and closing execution mode is incremented by 1 as the process corresponding to step S4108, and if the ball entry management process is during the high frequency support mode, the value of the special electric winning counter 233b for the high frequency support mode is incremented by 1 as the process corresponding to step S4108. In addition, the detection result of the special electric detection sensor 45a is also monitored in the ball entry detection process (step S3709) of the timer interrupt process (Figure 69) executed as the process corresponding to the specific control, and if it is determined that one game ball has been detected by the special electric detection sensor 45a, a process is executed to pay out the number of game balls corresponding to the special electric winning device 32, and a process is executed to identify the trigger for ending the round game.

If it is determined that one game ball has been detected by the first actuation port detection sensor 46a (step S4109: YES), that is, if it is confirmed that the signal received from the first actuation port detection sensor 46a has switched from a LOW level to a HIGH level, the value of the normal first actuation counter 231c is incremented by 1 (step S4110).

If the ball entry management process is during the opening and closing execution mode, the value of the first operation counter 232c for the opening and closing execution mode is incremented by 1 as the process corresponding to step S4110, and if the ball entry management process is during the high-frequency support mode, the value of the first operation counter 233c for the high-frequency support mode is incremented by 1 as the process corresponding to step S4110. In addition, the detection result of the first operation port detection sensor 46a is also monitored in the ball entry detection process (step S3709) of the timer interrupt process (FIG. 69) executed as the process corresponding to the specific control, and if it is determined that one game ball has been detected by the first operation port detection sensor 46a, a process is executed to pay out the number of game balls corresponding to the first operation port 33, and a process is executed to identify the trigger for obtaining reserved information for the special chart.

If it is determined that one game ball has been detected by the second actuation port detection sensor 47a (step S4111: YES), i.e., if it is confirmed that the signal received from the second actuation port detection sensor 47a has switched from a LOW level to a HIGH level, the value of the normal second actuation counter 231d is incremented by 1 (step S4112).

If the ball entry management process is during the opening and closing execution mode, the value of the second operation counter 232d for the opening and closing execution mode is incremented by 1 as a process corresponding to step S4112, and if the ball entry management process is during the high-frequency support mode, the value of the second operation counter 233d for the high-frequency support mode is incremented by 1 as a process corresponding to step S4112. In addition, the detection result of the second operation port detection sensor 47a is also monitored in the ball entry detection process (step S3709) of the timer interrupt process (FIG. 69) executed as a process corresponding to specific control, and if it is determined that one game ball has been detected by the second operation port detection sensor 47a, a process is executed to pay out the number of game balls corresponding to the second operation port 34, and a process is executed to identify the trigger for obtaining reserved information for the special chart.

If it is determined that one game ball has been detected by the outlet detection sensor 48a (step S4113: YES), i.e., if it is confirmed that the signal received from the outlet detection sensor 48a has switched from a LOW level to a HIGH level, the value of the normal out counter 231e is incremented by 1 (step S4114).

If the goal entry management process is in the open/close execution mode, the value of the out counter 232e for the open/close execution mode is incremented by 1 as the process corresponding to step S4114, and if the goal entry management process is in the high frequency support mode, the value of the out counter 233e for the high frequency support mode is incremented by 1 as the process corresponding to step S4114. In addition, the detection result of the out port detection sensor 48a is not monitored in the goal entry detection process (step S3709) of the timer interrupt process (Figure 69) executed as the process corresponding to specific control.

By executing the processing of steps S4004 to S4006 as described above, the number of game balls entering the general winning port 31 is measured using the general winning counters 231a, 232a, and 233a, the number of game balls entering the special winning device 32 is measured using the special winning counters 231b, 232b, and 233b, the number of game balls entering the first operating port 33 is measured using the first operating counters 231c, 232c, and 233c, the number of game balls entering the second operating port 34 is measured using the second operating counters 231d, 232d, and 233d, and the number of game balls entering the out port 24a is measured using the out counters 231e, 232e, and 233e. This makes it possible for the main CPU 63 to grasp the ball entry history for each ball entry section 24a, 31 to 34. In addition, by providing separate counter areas 231 for normal use, 232 for the open/close execution mode, and 233 for the high-frequency support mode, the main CPU 63 can grasp the history of balls entering each of the ball entry sections 24a, 31-34 by distinguishing between a situation that is neither the open/close execution mode nor the high-frequency support mode, a situation that is the open/close execution mode, and a situation that is the high-frequency support mode.

Returning to the explanation of the check process (FIG. 73), if a positive judgment is made in step S4001, if the process of step S4004 is executed, if the process of step S4005 is executed, or if the process of step S4006 is executed, then a result calculation process is executed in step S4007, and a display process is executed in step S4008.

Figure 75 is a flowchart showing the result calculation process of step S4007.

First, it is determined whether the management start flag provided in the work area 223 for non-specific control is set to "1" (step S4201). The management start flag is a flag for the main CPU 63 to specify whether or not it is a situation in which collection of game history should be executed to calculate the management result of the game history. In this embodiment, when the supply of operating power to the pachinko machine 10 is started for the first time after the manufacture of the pachinko machine 10 (i.e., when the supply of operating power to the MPU 62 is started), collection of game history for calculating the management result of the game history is not executed until the total number of game balls discharged from the play area PA becomes equal to or greater than the number corresponding to the management start reference value, and collection of game history for calculating the management result of the game history is executed when the total number of game balls discharged from the play area PA becomes equal to or greater than the number corresponding to the management start reference value. At the shipping stage of the pachinko machine 10, the operation check of the pachinko machine 10 may be performed before shipping, and at that time, game balls are placed in each ball entry section and the subsequent operation is checked. In response to this, by not collecting the game history for calculating the game history management results until the total number of game balls discharged from the game area PA after the supply of operating power to the pachinko machine 10 begins and reaches or exceeds the management start reference value, it becomes possible to prevent ball entry results, etc., during the operation check described above from being collected as game history for calculating the game history management results.

Here, when the supply of operating power to the pachinko machine 10 is started for the first time after the manufacture of the pachinko machine 10 (i.e. when the supply of operating power to the MPU 62 is started), the value of the management start flag is "0". In this case, the values of the counters 231a to 231e in the normal counter area 231, the values of the counters 232a to 232e in the open/close execution mode counter area 232, and the values of the counters 233a to 233e in the high frequency support mode counter area 233 are also "0". On the other hand, when the supply of operating power to the pachinko machine 10 is stopped while the value of the management start flag is "1", and then the supply of operating power to the pachinko machine 10 is started while backup power is being supplied to the main RAM 65, the value of the management start flag remains "1". In this case, the values of the counters 231a to 231e in the normal counter area 231, the values of the counters 232a to 232e in the open/close execution mode counter area 232, and the values of the counters 233a to 233e in the high-frequency support mode counter area 233 are also maintained in the state before the supply of operating power to the pachinko machine 10 was stopped. With the above configuration, when the value of the management start flag is "0", the values of the counters 231a to 231e in the normal counter area 231, the values of the counters 232a to 232e in the open/close execution mode counter area 232, and the values of the counters 233a to 233e in the high-frequency support mode counter area 233 are also "0".

Incidentally, when the clearing process of the main RAM 65 is executed in step S105 or step S117 in the main processing (Figure 9), the work area 221 for specific control and the stack area 222 for specific control are the targets of the clearing process, and the work area 223 for non-specific control and the stack area 224 for non-specific control are excluded from the targets of the clearing process. This prevents the manager of the amusement hall from intentionally clearing the work area 223 for non-specific control and the stack area 224 for non-specific control to "0".

In addition, the main CPU 63 may be configured to check whether or not an abnormality has occurred in the work area 223 for non-specific control and the stack area 224 for non-specific control in a timer interrupt process (FIG. 69) described later, and if an abnormality is confirmed, the work area 223 for non-specific control and the stack area 224 for non-specific control are cleared to "0". This makes it possible to initialize the work area 223 for non-specific control and the stack area 224 for non-specific control when an abnormality occurs. In addition, in this configuration, if an abnormality occurs in the work area 223 for non-specific control, the work area 223 for non-specific control may be cleared to "0" without clearing the stack area 224 for non-specific control to "0", and if an abnormality occurs in the stack area 224 for non-specific control, the stack area 224 for non-specific control may be cleared to "0" without clearing the work area 223 for non-specific control to "0". In addition, even if an abnormality occurs in the work area 223 for non-specific control and the stack area 224 for non-specific control, the calculation result storage area 234 may be configured to be excluded from being cleared to "0".

If the determination in step S4201 is negative, the total number is calculated by adding up all the values of the counters 231a to 231e in the normal counter area 231, the values of the counters 232a to 232e in the open/close execution mode counter area 232, and the values of the counters 233a to 233e in the high frequency support mode counter area 233 (step S4202). Then, it is determined whether the calculated total number is greater than the management start reference value of "300" (step S4203).

If the result of the positive judgment in step S4203 is positive, the management start flag for the non-specific control work area 223 is set to "1" (step S4204). In addition, the counters 231a to 231e in the normal counter area 231, the counters 232a to 232e in the open/close execution mode counter area 232, and the counters 233a to 233e in the high frequency support mode counter area 233 are all cleared to "0" (step S4205). As a result, all information on the game history collected until the total number of game balls discharged from the game area PA after the supply of operating power to the pachinko machine 10 has started (i.e., after the supply of operating power to the MPU 62 has started) becomes equal to or greater than the number corresponding to the management start reference value is erased. Therefore, it is possible to prevent the collection of game history for calculating the management result of the game history from being executed until the total number of game balls discharged from the game area PA after the supply of operating power to the pachinko machine 10 has started becomes equal to or greater than the management start reference value.

If the determination in step S4201 is positive, the total number is calculated in the same manner as in step S4202 (step S4206). That is, the total number is calculated by adding up the values of the counters 231a to 231e in the normal counter area 231, the values of the counters 232a to 232e in the open/close execution mode counter area 232, and the values of the counters 233a to 233e in the high frequency support mode counter area 233. Then, it is determined whether the calculated total number is equal to or greater than the calculation reference number of "6000" (step S4207).

If the determination in step S4207 is affirmative, calculation processing of various parameters is executed (step S4208). Specifically, assuming that the values of the various counters 231a to 231e in the normal counter area 231 are K61 to K65, the values of the various counters 232a to 232e in the open/close execution mode counter area 232 are K71 to K75, and the values of the various counters 233a to 233e in the high frequency support mode counter area 233 are K81 to K85, the following 61st to 68th parameters are calculated.
Parameter 61: Total number of game balls paid out (K61 + K71 + K81 × number of prize balls for winning the general winning port 31 + K62 + K72 + K82 × number of prize balls for winning the special winning device 32 + K63 + K73 + K83 × number of prize balls for winning the first operating port 33 + K64 + K74 + K84 × number of prize balls for winning the second operating port 34) / total number of game balls discharged from the skill area PA (K61 + Parameter 62: Total number of game balls paid out during normal play (K61 x "Number of prize balls for winning at the general winning port 31" + K62 x "Number of prize balls for winning at the special winning device 32" + K63 x "Number of prize balls for winning at the first operating port 33" + K64 x "Number of prize balls for winning at the second operating port 34") /The ratio of the total number of game balls discharged from the skill area PA during normal times (K61 + K62 + K63 + K64 + K65) ・The 63rd parameter: The total number of game balls paid out during the opening and closing execution mode (K71 x "Number of prize balls for winning the general winning port 31" + K72 x "Number of prize balls for winning the special winning device 32" + K73 x "Number of prize balls for winning the first operating port 33" + K74 x "Number of prize balls for winning the second operating port 34") /Open The ratio of the total number of game balls discharged from the skill area PA during the closed execution mode (K71 + K72 + K73 + K74 + K75) 64th parameter: The total number of game balls paid out during the high frequency support mode (K81 x "number of prize balls for winning the general winning port 31" + K82 x "number of prize balls for winning the special winning device 32" + K83 x "number of prize balls for winning the first operating port 33" + K84 x "number of prize balls for winning the second operating port 34" 65th parameter: Total number of game balls entering the general winning port 31 (K61+K71+K81)/Ratio of total number of game balls discharged from the game area PA in high frequency support mode (K81+K82+K83+K84+K85) 66th parameter: Total number of game balls entering the general winning port 31 (K61+K71+K81)/Ratio of total number of game balls discharged from the game area PA (K61+K62+K63+K64+K65+K71+K72+K73+K74+K75+K81+K82+K83+K84+K85) 66th parameter: The ratio of the total number of game balls entering the first operating port 33 (K63 + K73 + K83) / the total number of game balls discharged from the game area PA (K61 + K62 + K63 + K64 + K65 + K71 + K72 + K73 + K74 + K75 + K81 + K82 + K83 + K84 + K85) 67th parameter: ("K62 + K72 + K82" x "Number of winning balls for winning into the special electric winning device 32" + "K64 + K74 + K84" x "2 Ratio of "K61 + K71 + K81" x "number of prize balls for winning at the general winning port 31" + "K62 + K72 + K82" x "number of prize balls for winning at the special line winning device 32" + "K63 + K73 + K83" x "number of prize balls for winning at the first operating port 33" + "K64 + K74 + K84" x "number of prize balls for winning at the second operating port 34") to the total number of game balls paid out; 68th parameter: "K6 2+K72+K82" x "number of prize balls for winning the special electric winning device 32" / total number of game balls paid out ("K61+K71+K81" x "number of prize balls for winning the general winning port 31" + "K62+K72+K82" x "number of prize balls for winning the special electric winning device 32" + "K63+K73+K83" x "number of prize balls for winning the first operating port 33" + "K64+K74+K84" x "number of prize balls for winning the second operating port 34") ratio. Then, the 61st to 68th parameters calculated in step S4208 are overwritten in the calculation result storage area 234 (step S4209). In this case, the 61st to 68th parameters of the calculation results in the previous processing round that were already stored in the calculation result storage area 234 are erased. Furthermore, even when the supply of operating power to the pachinko machine 10 is stopped, backup power is supplied to the main RAM 65, so when the backup power is being supplied, even if the supply of operating power to the pachinko machine 10 has just started, information on the 61st to 68th parameters calculated before the supply of operating power to the pachinko machine 10 was stopped is stored in the calculation result memory area 234.

Then, the counters 231a to 231e in the normal counter area 231, the counters 232a to 232e in the open/close execution mode counter area 232, and the counters 233a to 233e in the high frequency support mode counter area 233 are all cleared to "0" (step S4210). This makes it possible to erase the game history information once the 61st to 68th parameters have been calculated.

In addition, immediately after the management start flag is set to "1", the processing of steps S4208 to S4210 may be executed if the total number of game balls discharged from the play area PA is equal to or greater than the value obtained by subtracting the management start reference value from the calculation reference number, and thereafter, the processing of steps S4208 to S4210 may be executed if the total number of game balls discharged from the play area PA is equal to or greater than the calculation reference number.

Figure 76 is a flowchart showing the display process of step S4008 in the check process (Figure 73).

First, the value of the update timing counter provided in the work area 223 for non-specific control is decremented by 1 (step S4301). The update timing counter is a counter for the main CPU 63 to identify that it is time to update the display contents of the game history management results in the first to third notification display devices 69a to 69c. The main CPU 63 notifies the calculation results of the 61st to 68th parameters by controlling the display of the first to third notification display devices 69a to 69c. In this case, the first notification display device 69a displays information corresponding to the type of parameter to be notified. In addition, the number corresponding to the tens digit of the value obtained by multiplying the parameter to be notified by 100 is displayed on the second notification display device 69b, and the number corresponding to the ones digit is displayed on the third notification display device 69c. In the first to third notification display devices 69a to 69c, the displays corresponding to the calculation results of the 61st to 68th parameters are switched in sequence in a predetermined order, and after the calculation result of the 68th parameter, which is the last to be displayed, is displayed, the calculation result of the 61st parameter, which is the first to be displayed, is displayed. In this case, the period during which the calculation result of one parameter is continuously displayed is 10 seconds.

The calculation period for the 61st to 68th parameters in the main CPU 63 is 60 minutes at the shortest. In contrast, the number of parameters 61st to 68th is eight, and the period during which the calculation result of one parameter is continuously displayed is 10 seconds. Therefore, the 61st to 68th parameters calculated by the main CPU 63 are displayed at least once on the first to third notification display devices 69a to 69c.

When the process of step S4301 is executed, it is determined whether the value of the update timing counter after subtracting 1 is "0" to determine whether it is time to update the display contents of the first to third alarm display devices 69a to 69c (step S4302). If a positive determination is made in step S4302, the value of the display target counter provided in the work area 223 for non-specific control is incremented by 1 (step S4303). Then, if the value of the display target counter after incrementing 1 exceeds the maximum value of "7" (step S4304: YES), the value of the display target counter is cleared to "0" (step S4305).

The display object counter is a counter that allows the main CPU 63 to identify the type of parameter that is the display object on the first to third notification display devices 69a to 69c. There is a one-to-one correspondence between the 61st to 68th parameters and the possible values of the display object counter, "0" to "7." For example, when the value of the display object counter is "0," the 61st parameter, which is the first display object, becomes the display object on the first to third notification display devices 69a to 69c, and when the value of the display object counter is "7," the 68th parameter, which is the last display object, becomes the display object on the first to third notification display devices 69a to 69c.

If a negative judgment is made in step S4304, or if the processing of step S4305 is executed, the display of the first notification display device 69a is controlled so that information corresponding to the type of parameter corresponding to the value of the counter to be displayed is displayed (step S4306). In addition, the parameter corresponding to the value of the counter to be displayed is read from the calculation result storage area 234, and the read parameter is multiplied by 100 so that the number corresponding to the tens digit is displayed on the second notification display device 69b and the number corresponding to the ones digit is displayed on the third notification display device 69c (step S4307).

Here, a display IC is provided corresponding to each of the first to third alarm display devices 69a to 69c. In step S4306, the main CPU 63 outputs display data to the display IC corresponding to the first alarm display device 69a, and in step S4307, the main CPU 63 outputs display data to the display IC corresponding to the second alarm display device 69b and the display IC corresponding to the third alarm display device 69c. When operating power is supplied to these display ICs, they can store and hold display data, and cause the display content corresponding to the stored and held display data to be continuously displayed on the corresponding alarm display devices 69a to 69c. Then, when the display data is changed by the main CPU 63, the display of the alarm display devices 69a to 69c is changed to the display content corresponding to the changed display data. As a result, even after the management execution process (FIG. 71), which is the process corresponding to non-specific control, ends and returns to the process corresponding to specific control, the display corresponding to the display data set in the execution status of the process corresponding to non-specific control continues on the first to third notification display devices 69a to 69c.

Then, the update timing counter in the non-specific control work area 223 is set to a value corresponding to 10 seconds as the value corresponding to the next update timing (step S4308).

By executing the display process as described above, when the supply of operating power to the main CPU 63 has begun, the game history management results are displayed on the first to third notification display devices 69a to 69c. The game history management results are displayed regardless of whether or not play is continuing, and regardless of whether or not the gaming machine main body 12 has been opened relative to the outer frame 11 and the main control device 60 is visible from the front of the pachinko machine 10. By executing display control of the first to third notification display devices 69a to 69c in this way regardless of the game situation or the state of the pachinko machine 10, it is possible to simplify the processing configuration for display control of the first to third notification display devices 69a to 69c.

The present embodiment described above provides the following excellent advantages:

The main RAM 65 is provided with a work area 221 for specific control and a stack area 222 for specific control, and a work area 223 for non-specific control and a stack area 224 for non-specific control. The work area 221 for specific control and the stack area 222 for specific control are capable of storing and reading information when a process corresponding to specific control is executed by the main CPU 63 using a program for specific control and data for specific control, whereas the work area 221 for specific control and the stack area 222 for specific control are capable of storing and reading information when a process corresponding to non-specific control is executed by the main CPU 63 using a program for non-specific control and data for non-specific control, and are not capable of storing information. The work area 223 for non-specific control and the stack area 224 for non-specific control are capable of storing and reading information when a process corresponding to non-specific control is executed by the main CPU 63, whereas the work area 223 for non-specific control and the stack area 224 for non-specific control are capable of storing and reading information when a process corresponding to non-specific control is executed by the main CPU 63, and are not capable of storing information when a process corresponding to specific control is executed by the main CPU 63, and are not capable of reading information. This allows the work area 221 for specific control and the stack area 222 for specific control to be treated as dedicated storage areas for processing corresponding to specific control, while the work area 223 for non-specific control and the stack area 224 for non-specific control can be treated as dedicated storage areas for processing corresponding to non-specific control. This makes it possible to clearly differentiate the storage destination of information in the main RAM 65 for processing corresponding to specific control and processing corresponding to non-specific control. This makes it possible to prevent information used in processing corresponding to specific control and processing corresponding to non-specific control from being erased when one of the other processing is executed.

The processing corresponding to the specific control includes processing for controlling the progress of the game, and the processing corresponding to the non-specific control includes processing for managing the game history. As described above, the work area 221 for specific control and the stack area 222 for specific control are treated as dedicated storage areas for the processing corresponding to the specific control, and the work area 223 for non-specific control and the stack area 224 for non-specific control are treated as dedicated storage areas for the processing corresponding to the non-specific control. This makes it possible to prevent information used in the processing for managing the game history, such as information stored in the normal counter area 231, the open/close execution mode counter area 232, the high frequency support mode counter area 233, and the calculation result storage area 234, from being overwritten when the processing for controlling the progress of the game is executed.

A normal counter area 231, an open/close execution mode counter area 232, a high frequency support mode counter area 233, and a calculation result storage area 234 are provided in the main RAM 65, in which information for managing the game history is stored. This allows the main CPU 63 to complete the processing for managing the game history. It is also possible to prevent unauthorized access to or unauthorized modification of the game history information and the information of various parameters calculated using the game history information.

When the situation changes from one in which processing corresponding to specific control is being performed to one in which processing corresponding to non-specific control is being performed, or when the situation changes to one in which processing corresponding to non-specific control is being performed, the information in the various registers of the main CPU 63 is saved to the main RAM 65. This makes it possible to prevent information stored in the various registers of the main CPU 63 from being overwritten when processing corresponding to specific control is executed when processing corresponding to non-specific control is executed. In addition, when or after processing corresponding to non-specific control is terminated, the information saved in the main RAM 65 is restored to the various registers of the main CPU 63. This makes it possible to execute processing corresponding to specific control from the state of the various registers of the main CPU 63 before the processing corresponding to the non-specific control is executed when processing corresponding to non-specific control is terminated.

When the state where processing corresponding to specific control is being executed changes to a state where processing corresponding to non-specific control is being executed, or when the state where processing corresponding to non-specific control is being executed changes, the information in some of the various registers in the main CPU 63 is saved to the main RAM 65. This makes it possible to reduce the storage capacity required in the main RAM 65 to save the information in the registers of the main CPU 63.

When the situation changes from one in which processing corresponding to specific control is being performed to one in which processing corresponding to non-specific control is being performed, or when the situation changes to one in which processing corresponding to non-specific control is being performed, information in the various registers of the main CPU 63 that are the target of information storage in the processing corresponding to non-specific control is saved to the main RAM 65. This makes it possible to reduce the storage capacity required in the main RAM 65 to save the information in the registers of the main CPU 63, while making it possible to resume the processing corresponding to specific control from the state of the registers of the main CPU 63 before the processing corresponding to the non-specific control is completed.

When processing corresponding to non-specific control is started, the information in the flag register of the main CPU 63 is saved to the stack area 222 for specific control in the processing corresponding to specific control, and the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 is saved to the work area 223 for non-specific control in the processing corresponding to non-specific control. This makes it possible to save the information at a time that is favorable for each piece of information stored in the various registers of the main CPU 63, and also makes it possible to distribute the processing for saving information between the processing corresponding to specific control and the processing corresponding to non-specific control.

The flag register includes a carry flag, zero flag, P/V flag, sign flag, and half carry flag, and the information in the flag register changes depending on the execution results of an arithmetic instruction, a rotate instruction, an input/output instruction, etc. In this case, the information in the flag register is saved in the stack area 222 for specific control by the processing corresponding to specific control before the processing corresponding to non-specific control is started. This makes it possible to save the information in the flag register in the state before it changes after the call of a subroutine corresponding to non-specific control or the start of the subroutine in the stack area 222 for specific control.

By saving the information of the WA register, BC register, DE register, HL register, IX register, and IY register to the work area 223 for non-specific control instead of saving it to the stack area 224 for non-specific control, it is possible to reduce the capacity of the stack area 224 for non-specific control. In addition, when using the stack area 224 for non-specific control, the order in which information is written is such that later information is read first. Therefore, if the order in which information is read is shifted due to some kind of noise or the like, all information in the subsequent read order will be restored to different registers. The probability of such an event occurring increases as the amount of information saved to the stack area 224 for non-specific control increases. In contrast, by saving the register information to the work area 223 for non-specific control, it is possible to prevent such an event from occurring even when there is a lot of information to be saved.

When the state where processing corresponding to specific control is executed changes to a state where processing corresponding to non-specific control is executed or when the state where processing corresponding to non-specific control is executed is reached, the information of the stack pointer of the main CPU 63 becomes fixed information, and the stack pointer information is not saved to the main RAM 65 when processing corresponding to non-specific control is started. This eliminates the need to secure capacity in the main RAM 65 for saving the stack pointer information, making it possible to reduce the storage capacity of the main RAM 65 accordingly. Even in this configuration where the stack pointer information is not saved, when the state where processing corresponding to specific control is executed changes to a state where processing corresponding to non-specific control is executed or when the state where processing corresponding to non-specific control is executed is reached, the stack pointer information of the main CPU 63 becomes fixed information, so that even if the stack pointer information is not saved as described above, when processing corresponding to non-specific control is completed, it is possible to restore the stack pointer information before the processing corresponding to the non-specific control was started.

In addition, when processing corresponding to non-specific control is executed, the information in the flag register of the main CPU 63 is saved to the main RAM 65 in processing corresponding to specific control, but this is not limited to this, and the information in the flag register may be saved to the main RAM 65 in processing corresponding to non-specific control. Also, after processing corresponding to non-specific control is completed, the information is restored to the flag register of the main CPU 63 in processing corresponding to specific control, but this is not limited to this, and the information is restored to the flag register in processing corresponding to non-specific control.

In addition, the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 is saved to the main RAM 65 in the process corresponding to the non-specific control after the process corresponding to the non-specific control is started, but this is not limited to this, and the information in these registers may be saved to the main RAM 65 in the process corresponding to the specific control.In addition, when the process corresponding to the non-specific control is terminated, the information is restored to each of the above registers in the process corresponding to the non-specific control, but this is not limited to this, and the information is restored to each of the above registers in the process corresponding to the specific control after the process corresponding to the non-specific control is terminated.

<Sixteenth embodiment>
In this embodiment, the processing configuration of the management process is different from that of the fifteenth embodiment. The configuration that differs from the fifteenth embodiment will be described below. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 77 is a flowchart showing the management process in this embodiment executed by the main CPU 63. Note that the processes in steps S4401 to S4405 in the management process are executed by the main CPU 63 using a program for specific control and data for specific control.

First, to prohibit the occurrence of timer interrupt processing (FIG. 69), interrupt prohibition is set (step S4401). This makes it possible to prevent the timer interrupt processing (FIG. 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

Then, the load command "LD (_PSWBUF), PSW" is used to save the flag register information of the main CPU 63 to the PSW buffer set in the work area 221 for specific control (step S4402). The flag register includes a carry flag, zero flag, P/V flag, sign flag, and half carry flag, and the flag register information changes depending on the execution results of arithmetic instructions, rotate instructions, input/output instructions, and the like. By saving such flag register information before the program of the subroutine corresponding to the management execution process is started, it is possible to save the flag register information in the state before it changes after the subroutine is called or started in the work area 221 for specific control.

Then, the management execution process is started by reading out a subroutine program corresponding to the management execution process set in the program for non-specific control (step S4403). In this case, information for specifying the return address of the management process after the management execution process is executed is written into the stack area 222 for specific control by a push command. Then, when the management execution process is completed, information for specifying the return address is read out by a pop command, and the process returns to the program for the management process indicated by the return address.

When returning to the management processing program after the management execution processing is executed, the flag register information saved in the PSW buffer in the work area 221 for specific control in step S4402 is restored to the flag register of the main CPU 63 by a load command as "LD PSW, (_PSWBUF)" (step S4404). This causes the flag register information of the main CPU 63 to return to the information at the time step S4402 was last executed. In other words, the flag register information of the main CPU 63 returns to the information for executing specific control.

After that, the interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing (Figure 69) is prohibited to a state in which it is permitted (step S4405). This allows a new execution of the timer interrupt processing.

With the above configuration, the information in the flag register of the main CPU 63 immediately before switching from specific control to non-specific control is saved in the work area 221 for specific control, not in the stack area 222 for specific control. This makes it possible to save the information in the flag register while minimizing the capacity of the stack area 222 for specific control.

The PSW buffer in the work area 221 for specific control is secured as a dedicated area, but is not limited to this, and may be configured as a shared area in which other information can also be written. In other words, since there is no need to save the information in the flag register of the main CPU 63 corresponding to the specific control in a situation where the management process is not being executed, a shared area that is also used as a PSW buffer when performing a predetermined arithmetic process in the process corresponding to the specific control in a situation where the management process is not being executed may be configured to be used. In this case, since the shared area will be used reliably to save the information in the flag register when the management process is executed, it is necessary to configure the shared area so that information other than the information in the flag register, that is no longer necessary before the management process is executed, is written to the shared area.

Seventeenth embodiment
In this embodiment, the processing configuration of the management execution process is different from that of the fifteenth embodiment. The following describes the configuration that is different from the fifteenth embodiment. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 78 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that the processes in steps S4501 to S4515 in the management execution process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

First, as in step S3901 of the management execution process (FIG. 71) in the 15th embodiment, a load command is used to set "LD SP, Y(u+2)" to Y(u+2) as a fixed address at the start of non-specific control in the stack pointer of the main CPU 63 (step S4501).

After that, the information in the WA register of the master CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the information of the current stack pointer of the master CPU 63 by a push command "PUSH WA" (step S4502). In this case, the information in the WA register is saved to a memory area corresponding to the fixed address set in the stack pointer of the master CPU 63 in step S4501. In addition, the information in the stack pointer of the master CPU 63 is updated to the information of the address of the memory area to be written to next.

Then, by using a push command "PUSH BC", the information in the BC register of the main CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the main CPU 63 (step S4503). In addition, the stack pointer information of the main CPU 63 is updated to the address information of the memory area to be written to next.

Then, the information in the DE register of the main CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the main CPU 63 by a push command "PUSH DE" (step S4504). In addition, the stack pointer information of the main CPU 63 is updated to the address information of the memory area to be written to next.

Then, by using the push command "PUSH HL", the information in the HL register of the main CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the main CPU 63 (step S4505). In addition, the stack pointer information of the main CPU 63 is updated to the address information of the memory area to be written to next.

Then, the information in the IX register of the main CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the main CPU 63 by a push command "PUSH IX" (step S4506). In addition, the stack pointer information of the main CPU 63 is updated to the address information of the memory area to be written to next.

After that, the information in the IY register of the main CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the main CPU 63 by a push command "PUSH IY" (step S4507). In addition, the stack pointer information of the main CPU 63 is updated to the address information of the memory area to be written to next.

After steps S4502 to S4507 are executed, a check process is executed (step S4508). When the check process is executed, a subroutine program corresponding to the check process set in the program for non-specific control is executed. When the subroutine program is executed, information for identifying the return address of the management execution process after the check process is executed is written by a push command to a memory area in the stack area 224 for non-specific control corresponding to the current stack pointer information of the main CPU 63. Then, when the check process is completed, information for identifying the return address is read by a pop command, and the program for the management execution process indicated by the return address is returned to. The contents of the check process are the same as those of the fifteenth embodiment.

After that, as in step S3909 of the management execution process (FIG. 71) in the above fifteenth embodiment, a load command is used to set "LD SP, Y(r+α)" to Y(r+α) as a fixed address at the time of return to specific control in the stack pointer of the main CPU 63 (step S4509). The address of Y(r+α) is set as an address between Y(r+8) and Y(s) in the stack area 222 for specific control.

After that, the IY register of the main CPU 63 is overwritten with the information saved in the memory area corresponding to the previous order information in the non-specific control stack area 224 by the pop command "POP IY" (step S4510). In addition, the stack pointer information of the main CPU 63 is updated to the address information of the memory area to be written in the previous order.

After that, the IX register of the main CPU 63 is overwritten with the information saved in the memory area corresponding to the previous order information in the non-specific control stack area 224 by a pop command as "POP IX" (step S4511). In addition, the stack pointer information of the main CPU 63 is updated to the address information of the memory area to be written in the previous order.

After that, the POP HL command is used to overwrite the HL register of the main CPU 63 with the information saved in the memory area corresponding to the previous order information with respect to the current stack pointer information of the main CPU 63 in the non-specific control stack area 224 (step S4512). In addition, the stack pointer information of the main CPU 63 is updated to the address information of the memory area to be written in the previous order.

After that, the DE register of the main CPU 63 is overwritten with the information saved in the memory area corresponding to the previous order information in the stack area 224 for non-specific control by a pop command as "POP DE" (step S4513). In addition, the stack pointer information of the main CPU 63 is updated to the address information of the memory area to be written in the previous order.

After that, the POP BC command is used to overwrite the BC register of the main CPU 63 with the information saved in the memory area corresponding to the previous order information with respect to the current stack pointer information of the main CPU 63 in the non-specific control stack area 224 (step S4514). In addition, the stack pointer information of the main CPU 63 is updated to the address information of the memory area to be written in the previous order.

After that, the WA register of the main CPU 63 is overwritten with the information saved in the memory area corresponding to the previous order information for the current stack pointer information of the main CPU 63 in the non-specific control stack area 224 by a pop command as "POP WA" (step S4515). In addition, the stack pointer information of the main CPU 63 is updated to the address information of the memory area to be written in the previous order.

By executing the processing of steps S4510 to S4515, it is possible to restore the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 to the information corresponding to specific control immediately before the processing corresponding to non-specific control is started.

In addition to the flag register, the main CPU 63 also has various general-purpose registers, auxiliary registers, and index registers. In this case, in steps S4502 to S4507, the information of some of these general-purpose registers, auxiliary registers, and index registers, namely, the WA register, BC register, DE register, HL register, IX register, and IY register, is saved to the stack area 224 for non-specific control. These WA register, BC register, DE register, HL register, IX register, and IY register are registers used in the check process (step S4508), which is a process corresponding to non-specific control. By saving the information set in such registers to the stack area 224 for non-specific control prior to the execution of the check process (step S4508), it is possible to save the information of these registers used during specific control before the non-specific control is started. Therefore, even if these registers are overwritten during non-specific control, when the non-specific control is terminated, the information saved in the stack area 224 for non-specific control is restored to these registers, making it possible to restore the state of these registers to the state corresponding to the specific control before the non-specific control was executed.

In addition, instead of saving all the information of the various general-purpose registers, auxiliary registers, and index registers to the stack area 224 for non-specific control, the information of the WA register, BC register, DE register, HL register, IX register, and IY register to be used in the check process, which is a process corresponding to the non-specific control, is selectively saved to the stack area 224 for non-specific control, thereby making it possible to reduce the capacity reserved for saving register information in the stack area 224 for non-specific control. Therefore, it is possible to save the above-mentioned register information while securing a large capacity for the stack area 224 for non-specific control that is available during the check process.

<Eighteenth embodiment>
In this embodiment, the processing configuration of the management execution process is different from that of the fifteenth embodiment. The following describes the configuration that is different from the fifteenth embodiment. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 79 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that the processes in steps S4601 to S4605 in the management execution process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

First, as in step S3901 of the management execution process (FIG. 71) in the 15th embodiment, a load command is used to set "LD SP, Y(u+2)" to Y(u+2) as a fixed address at the start of non-specific control in the stack pointer of the main CPU 63 (step S4601).

After that, the load command "LD (_ALLBUF), ALL" is used to save the information of all registers of the main CPU 63 to the ALL buffer set in the work area 223 for non-specific control (step S4602). As a result, not only the information of the WA register, BC register, DE register, HL register, IX register, and IY register used in the check process, which is a process corresponding to non-specific control, but also the information of all registers including other registers are saved together in the ALL buffer of the work area 223 for non-specific control. By saving all registers of the main CPU 63 to the work area 223 for non-specific control in this way, there is no need to selectively save the information of the registers of the main CPU 63.

Here, the registers to be saved include the flag register. The flag register information is saved to the stack area 222 for specific control in step S3802 of the management process (Figure 70), but in step S4602, the flag register information is saved to the work area 223 for non-specific control. This eliminates the need to selectively save the information in the registers of the main CPU 63, including the flag register information. Even if the flag register information is saved in a redundant manner in this way, the information is restored from the stack area 222 for specific control to the flag register of the main CPU 63 in step S3804 of the management process (Figure 70) after the management execution process is completed, so that when returning to the process corresponding to specific control, the information in the flag register of the main CPU 63 can be restored to the state it was in immediately before the management execution process was executed.

Then, the check process is executed (step S4603). When the check process is executed, a subroutine program corresponding to the check process set in the program for non-specific control is executed. When the subroutine program is executed, information for identifying the return address of the management execution process after the check process is executed is written by a push command to a memory area in the stack area 224 for non-specific control corresponding to the current stack pointer information of the main CPU 63. Then, when the check process is completed, information for identifying the return address is read by a pop command, and the program for the management execution process indicated by the return address is returned to. The contents of the check process are the same as those of the fifteenth embodiment.

After that, as in step S3909 of the management execution process (FIG. 71) in the above fifteenth embodiment, a load command is used to set "LD SP, Y(r+α)" to Y(r+α) as a fixed address at the time of return to specific control in the stack pointer of the main CPU 63 (step S4604). The address of Y(r+α) is set as an address between Y(r+8) and Y(s) in the stack area 222 for specific control.

Then, the information saved in the ALL buffer of the work area 223 for non-specific control is overwritten in the registers corresponding to each of the main CPUs 63 by a load command "LD ALL, (_ALLBUF)" (step S4605). This makes it possible to restore each piece of information in all registers of the main CPU 63 to the information corresponding to specific control immediately before the processing corresponding to non-specific control is started.

According to the above configuration, by saving the register information of the main CPU 63 to the work area 223 for non-specific control instead of saving it to the stack area 224 for non-specific control, it is possible to keep the capacity of the stack area 224 for non-specific control small. In addition, when using the stack area 224 for non-specific control, the writing order of information is such that later information is read first. Therefore, if the reading order of information is shifted due to some kind of noise or the like, all information in the subsequent read order will be restored to different registers. The probability of such an event occurring increases as the amount of information saved to the stack area 224 for non-specific control increases. In contrast, by saving the register information to the work area 223 for non-specific control, it is possible to prevent such an event from occurring even when there is a lot of information to be saved.

In addition, when the register information of the main CPU 63 is saved to the work area 223 for non-specific control, the information of all registers, including not only the WA register, BC register, DE register, HL register, IX register, and IY register used in the check process, which is a process corresponding to non-specific control, but also other registers, is saved together in the ALL buffer of the work area 223 for non-specific control. By saving all registers of the main CPU 63 to the work area 223 for non-specific control in this way, there is no need to selectively save the register information of the main CPU 63.

In addition, the information in all registers of the main CPU 63 is saved to the main RAM 65 in the process corresponding to the non-specific control after the process corresponding to the non-specific control is started, but this is not limited to this, and the information in all registers may be saved to the main RAM 65 in the process corresponding to the specific control. Also, when the process corresponding to the non-specific control is terminated, the information is restored to all registers in the process corresponding to the non-specific control, but this is not limited to this, and the information is restored to all registers in the process corresponding to the specific control after the process corresponding to the non-specific control is terminated.

<Nineteenth embodiment>
In this embodiment, the processing configuration of the management execution process is different from that of the fifteenth embodiment. The configuration that differs from the fifteenth embodiment will be described below. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 80 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that the processes in steps S4701 to S4706 in the management execution process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

First, the stack pointer information of the main CPU 63 is saved to the SP buffer set in the work area 223 for non-specific control by a load command "LD (_SPBUF), SP" (step S4701). As a result, the stack pointer information corresponding to the specific control immediately before the processing corresponding to the non-specific control is started is saved to the work area 223 for non-specific control.

Then, as in step S3901 of the management execution process (FIG. 71) in the 15th embodiment, a load command is used to set "LD SP, Y(u+2)" and set Y(u+2) as a fixed address at the start of non-specific control in the stack pointer of the main CPU 63 (step S4702).

After that, the information of all the registers of the main CPU 63 is evacuated by a push command as "PUSH ALL" to a memory area in the non-specific control stack area 224 corresponding to the information of the current stack pointer of the main CPU 63 and a memory area continuous from that memory area (step S4703). In this case, since it is not possible to store the information of all the registers of the main CPU 63 in one memory area in the non-specific control stack area 224, the memory area corresponding to the information of the current stack pointer of the main CPU 63 in the non-specific control stack area 224 and a memory area continuous from that memory area are set as the destination for evacuating the register information as described above. In addition, the stack pointer information of the main CPU 63 is updated to the address information of the memory area to be written next in the order in which the last information was stored when evacuating the information of all the registers.

Then, the check process is executed (step S4704). When the check process is executed, a subroutine program corresponding to the check process set in the program for non-specific control is executed. When the subroutine program is executed, information for identifying the return address of the management execution process after the check process is executed is written by a push command to a memory area in the stack area 224 for non-specific control corresponding to the information of the current stack pointer of the main CPU 63. Then, when the check process is completed, information for identifying the return address is read by a pop command, and the program for the management execution process indicated by the return address is returned to. The contents of the check process are the same as those of the fifteenth embodiment.

After that, the pop command "POP ALL" overwrites the information saved in the memory area corresponding to the current stack pointer information of the main CPU 63 in the stack area 224 for non-specific control and in the memory area adjacent to that memory area in the registers corresponding to the main CPU 63 (step S4705). This makes it possible to restore the information in all registers of the main CPU 63 to the information corresponding to specific control immediately before the processing corresponding to non-specific control was started.

Then, the information saved in the SP buffer of the work area 223 for non-specific control is overwritten to the stack pointer of the main CPU 63 by a load command as "LD SP, (_SPBUF)" (step S4706). As a result, the information in the stack pointer of the main CPU 63 is restored to the information corresponding to the specific control immediately before the processing corresponding to the non-specific control is started.

According to the above configuration, when the register information of the main CPU 63 is saved to the stack area 224 for non-specific control, not only the WA register, BC register, DE register, HL register, IX register, and IY register used in the check process, which is a process corresponding to non-specific control, but also the information of all registers, including other registers, is saved together in the stack area 224 for non-specific control. By saving all registers of the main CPU 63 to the stack area 224 for non-specific control in this way, there is no need to selectively save the register information of the main CPU 63.

The information of the stack pointer corresponding to the specific control immediately before the processing corresponding to the non-specific control is started is saved in the work area 223 for non-specific control. As a result, even if the information of the stack pointer corresponding to the specific control immediately before the processing corresponding to the non-specific control is started is configured to be variable, when the processing corresponding to the non-specific control ends and returns to the processing corresponding to the specific control, it is possible to restore the information of the stack pointer of the main CPU 63 to the information corresponding to the specific control immediately before the processing corresponding to the non-specific control is started.

In addition, the information in all registers of the main CPU 63 is saved to the main RAM 65 in the process corresponding to the non-specific control after the process corresponding to the non-specific control is started, but this is not limited to this, and the information in all registers may be saved to the main RAM 65 in the process corresponding to the specific control. Also, when the process corresponding to the non-specific control is terminated, the information is restored to all registers in the process corresponding to the non-specific control, but this is not limited to this, and the information is restored to all registers in the process corresponding to the specific control after the process corresponding to the non-specific control is terminated.

<Twentieth embodiment>
In this embodiment, the processing configuration of the management process and the management execution process is different from that of the fifteenth embodiment. The configurations that are different from the fifteenth embodiment will be described below. Note that the description of the same configurations as the fifteenth embodiment will basically be omitted.

Figure 81 is a flowchart showing the management process in this embodiment, which is executed by the main CPU 63. Note that the processes in steps S4801 to S4811 in the management process are executed by the main CPU 63 using a program for specific control and data for specific control.

First, to prohibit the occurrence of timer interrupt processing (FIG. 69), interrupt prohibition is set (step S4801). This makes it possible to prevent the timer interrupt processing (FIG. 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

After that, the information in the flag register of the main CPU 63 is saved to the stack area 222 for specific control by a push command as "PUSH PSW" (step S4802). The flag register includes a carry flag, zero flag, P/V flag, sign flag, and half carry flag, and the information in the flag register changes depending on the execution results of arithmetic instructions, rotate instructions, input/output instructions, and the like. By saving such flag register information before the program of the subroutine corresponding to the management execution process is started, it becomes possible to save the information in the flag register in the state before it changes after the subroutine is called or started in the stack area 222 for specific control.

Then, the WA register of the master CPU 63 is cleared to "0" by a load command as "LD WA, 0" (step S4803). The BC register of the master CPU 63 is cleared to "0" by a load command as "LD BC, 0" (step S4804). The DE register of the master CPU 63 is cleared to "0" by a load command as "LD DE, 0" (step S4805). The HL register of the master CPU 63 is cleared to "0" by a load command as "LD HL, 0" (step S4806). The IX register of the master CPU 63 is cleared to "0" by a load command as "LD IX, 0" (step S4807). The IY register of the master CPU 63 is cleared to "0" by a load command as "LD IY, 0" (step S4808).

In addition to the flag register, the main CPU 63 also contains various general-purpose registers, auxiliary registers, and index registers. In this case, in steps S4803 to S4808, the WA register, BC register, DE register, HL register, IX register, and IY register, which are some of the general-purpose registers, auxiliary registers, and index registers, are cleared to "0". The WA register, BC register, DE register, HL register, IX register, and IY register are used in the check process (step S4902), which is a process corresponding to non-specific control. By clearing such registers to "0" prior to the execution of the management execution process (step S4809), which is a process corresponding to non-specific control, it is possible to set the state of these registers to the state immediately after the supply of operating power to the main CPU 63 is started, before the process corresponding to non-specific control is started.

In addition, the information in the WA register, BC register, DE register, HL register, IX register, and IY register before the processing corresponding to the non-specific control is started is unnecessary for the processing corresponding to the specific control after the processing corresponding to the non-specific control is completed. Therefore, even if the information in these registers is cleared to "0" without being saved, no problems will occur in the processing corresponding to the specific control that is restored after the processing corresponding to the non-specific control is completed.

After steps S4803 to S4808 have been executed, the subroutine program corresponding to the management execution process set in the program for non-specific control is read out, thereby starting the management execution process (step S4809). In this case, information for specifying the return address of the management process after the management execution process is executed is written into the stack area 222 for specific control by a push command. Then, when the management execution process ends, information for specifying the return address is read out by a pop command, and the program for the management process indicated by the return address is returned to.

When returning to the management processing program after the management execution processing is executed, the flag register information saved in the stack area 222 for specific control in step S4802 is restored to the flag register of the main CPU 63 by a pop command as "POP PSW" (step S4810). This causes the flag register information of the main CPU 63 to return to the information at the time step S4802 was last executed. In other words, the flag register information of the main CPU 63 returns to the information for executing specific control.

Then, the interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing (FIG. 69) is prohibited to a state in which it is permitted (step S4811). This allows a new execution of the timer interrupt processing.

Figure 82 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that the processes in steps S4901 to S4909 in the management execution process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

First, as in step S3901 of the management execution process (Figure 71) in the 15th embodiment, a load command is used to set "LD SP, Y(u+2)" to Y(u+2) as a fixed address at the start of non-specific control in the stack pointer of the main CPU 63 (step S4901).

Then, the check process is executed (step S4902). When the check process is executed, a subroutine program corresponding to the check process set in the program for non-specific control is executed, and when the subroutine program is executed, information for specifying the return address of the management execution process after the check process is executed is written to the stack area 224 for non-specific control by a push command. Then, when the check process is completed, information for specifying the return address is read by a pop command, and the program returns to the management execution process program indicated by the return address. The contents of the check process are the same as those of the fifteenth embodiment described above.

After that, the WA register of the master CPU 63 is cleared to "0" by a load command as "LD WA, 0" (step S4903). The BC register of the master CPU 63 is cleared to "0" by a load command as "LD BC, 0" (step S4904). The DE register of the master CPU 63 is cleared to "0" by a load command as "LD DE, 0" (step S4905). The HL register of the master CPU 63 is cleared to "0" by a load command as "LD HL, 0" (step S4906). The IX register of the master CPU 63 is cleared to "0" by a load command as "LD IX, 0" (step S4907). The IY register of the master CPU 63 is cleared to "0" by a load command as "LD IY, 0" (step S4908).

As already explained, the WA register, BC register, DE register, HL register, IX register, and IY register are registers used in the check process (step S4902), which is a process corresponding to non-specific control. By clearing such registers to "0" prior to returning from the process corresponding to non-specific control to the process corresponding to specific control, it is possible to set the state of these registers to the state they were in immediately after the supply of operating power to the main CPU 63 was started, before returning to the process corresponding to specific control.

In addition, the information in the WA register, BC register, DE register, HL register, IX register, and IY register before the processing corresponding to the specific control is started is unnecessary for the processing corresponding to the non-specific control after the processing corresponding to the specific control is completed. Therefore, even if the information in these registers is cleared to "0" without being saved, no problems will occur in the processing corresponding to the non-specific control that is restored after the processing corresponding to the specific control is completed.

After that, as in step S3909 of the management execution process (FIG. 71) in the above fifteenth embodiment, a load command is used to set "LD SP, Y(r+α)" to Y(r+α) as a fixed address at the time of return to specific control in the stack pointer of the main CPU 63 (step S4909). The address of Y(r+α) is set as an address between Y(r+8) and Y(s) in the stack area 222 for specific control.

According to the above configuration, when processing corresponding to non-specific control is started after processing corresponding to specific control is being executed, the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 are cleared to "0". This eliminates the need to save the information in each of these registers to the main RAM 65. Therefore, there is no need to secure capacity for saving each of these pieces of information.

The WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 are also cleared to "0" when returning to processing corresponding to specific control from a situation in which processing corresponding to non-specific control is being executed. This makes it possible to return the state of each of these registers to the state it was in immediately before processing corresponding to non-specific control was started when returning to processing corresponding to specific control.

The state where each of the above registers is cleared to "0" is the state when the supply of operating power to the MPU 62 is started. This makes it possible to simplify the processing configuration for setting each of the above registers to a predetermined state when starting processing corresponding to non-specific control and when returning to processing corresponding to specific control.

When starting processing corresponding to non-specific control and when returning to processing corresponding to specific control, the registers that are cleared to "0" are some of the various registers in the main CPU 63. This makes it possible to reduce the processing load for setting each of the above registers to a predetermined state when starting processing corresponding to non-specific control and when returning to processing corresponding to specific control.

When starting processing corresponding to non-specific control and when returning to processing corresponding to specific control, the WA register, BC register, DE register, HL register, IX register, and IY register are cleared to "0," but other registers are not cleared to "0." This makes it possible to prevent information necessary for processing corresponding to specific control from being erased when processing corresponding to non-specific control begins.

In addition, information in registers other than the WA register, BC register, DE register, HL register, IX register, and IY register is not saved to the main RAM 65 when processing corresponding to non-specific control begins. This eliminates the need to reserve an area in the main RAM 65 for saving this information.

The information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 before processing corresponding to non-specific control is started is information that is not used in processing corresponding to specific control after processing corresponding to non-specific control is completed. This makes it possible to prevent the processing corresponding to specific control after processing corresponding to non-specific control is completed from being affected, even if the above registers are configured to be cleared to "0" when processing corresponding to non-specific control is started.

In addition, instead of clearing the WA, BC, DE, HL, IX, and IY registers of the main CPU 63 to "0" in steps S4803 to S4808 in the management process (FIG. 81), these registers may be initialized. In other words, when the supply of operating power to the MPU 62 is started, the registers of the main CPU 63 are once cleared to "0" and then the information of each register is set to the initial state, but in steps S4803 to S4808, each register may be set to this initial state. In this case, by configuring each register to be set to the above-mentioned initial state in steps S4903 to S4908 as well, when returning to the process corresponding to specific control, it is possible to return the state of each register to the state immediately before the process corresponding to non-specific control was started.

In addition, instead of clearing the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 to "0" in steps S4803 to S4808 in the management process (FIG. 81), all of these registers may be set to "1." In this case, by setting all of the above registers to "1" in steps S4903 to S4908 as well, when returning to the process corresponding to specific control, it is possible to return the state of each of these registers to the state it was in immediately before the process corresponding to non-specific control was started.

In addition, when processing corresponding to non-specific control is executed, the information in the flag register of the main CPU 63 is saved to the main RAM 65 in processing corresponding to specific control, but this is not limited to this, and the information in the flag register may be saved to the main RAM 65 in processing corresponding to non-specific control.In addition, after processing corresponding to non-specific control is completed, the information is restored to the flag register of the main CPU 63 in processing corresponding to specific control, but this is not limited to this, and the information is restored to the flag register in processing corresponding to non-specific control.

In addition, the process of clearing the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 to "0" is configured to be executed in the process corresponding to specific control before the process corresponding to non-specific control is started, but this is not limited to this, and the process of clearing these registers to "0" may be executed in the process corresponding to non-specific control.In addition, the process of clearing each of the above registers to "0" when the process corresponding to non-specific control is terminated is configured to be executed in the process corresponding to non-specific control, but this is not limited to this, and the process of clearing each of the above registers to "0" may be executed in the process corresponding to specific control after the process corresponding to non-specific control is terminated.

In addition, in the management process (FIG. 81), the "PUSH PSW" process in step S4802 is executed before each register is set to "0" in steps S4803 to S4808. Alternatively, the "PUSH PSW" process in step S4802 may be executed after each register is set to "0" in steps S4803 to S4808 and before the subroutine program corresponding to the management execution process is read in step S4809. This makes it possible to save the information in the flag register after it has been changed by the load command in steps S4803 to S4808 to the specific control stack area 222.

<Twenty-first embodiment>
In this embodiment, the configuration for collecting information on game history is different from that of the fifteenth embodiment. The configuration that differs from the fifteenth embodiment will be described below. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 83 is an explanatory diagram for explaining the electrical configuration in this embodiment.

The MPU 62 is provided with a main CPU 63, a main ROM 64, and a main RAM 65, similar to the fifteenth embodiment. Also, unlike the fifteenth embodiment, a management RAM 241 is electrically connected to the MPU 62. In other words, a management RAM 241 is provided in addition to the main RAM 65 built into the MPU 62, and the management RAM 241 is externally attached to the MPU 62.

As in the fifteenth embodiment, the main RAM 65 is provided with a work area 221 for specific control, a stack area 222 for specific control, a work area 223 for non-specific control, and a stack area 224 for non-specific control. Therefore, when the main CPU 63 executes processing corresponding to specific control using the program for specific control and data for specific control in the main ROM 64, the work area 221 for specific control and the stack area 222 for specific control in the main RAM 65 are used, and when the main CPU 63 executes processing corresponding to non-specific control using the program for non-specific control and data for non-specific control in the main ROM 64, the work area 223 for non-specific control and the stack area 224 for non-specific control in the main RAM 65 are used.

The management RAM 241 is provided with a normal counter area 231, an open/close execution mode counter area 232, a high-frequency support mode counter area 233, and a calculation result storage area 234. The contents of each of these areas 231 to 234 are the same as those in the fifteenth embodiment. In this embodiment, management execution processing including a check process is executed as processing corresponding to non-specific control in the main CPU 63. In the check process, the game history is collected through updating the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233, as in the fifteenth embodiment, and the 61st to 68th parameters calculated using the collected game history are written to the calculation result storage area 234. In other words, the management RAM 241 is used when the main CPU 63 executes processing corresponding to non-specific control, and therefore the management RAM 241 is used as a work area for non-specific control.

In addition, when collecting game history and calculating parameters 61 to 68 using the collected history information, the work area 223 for non-specific control and the stack area 224 for non-specific control in the main RAM 65 are used as appropriate.

According to the above configuration, the normal counter area 231, the open/close execution mode counter area 232, the high frequency support mode counter area 233, and the calculation result storage area 234 are provided in the management RAM 241 externally attached to the MPU 62. This makes it possible to store collected game history information while avoiding an increase in the required storage capacity in the non-specific control work area 223 in the main RAM 65, and to store the 61st to 68th parameters calculated using the game history. It is also possible to increase the storage capacity for storing game history information while using a general-purpose MPU 62.

When collecting game history and using the collected history information to calculate parameters 61 to 68, the work area 223 for non-specific control and the stack area 224 for non-specific control in the main RAM 65 are used as appropriate. This makes it possible to prevent an extreme drop in processing speed when processing history information.

In addition to or instead of the configuration in which the management RAM 241 is provided with the normal counter area 231, the open/close execution mode counter area 232, the high frequency support mode counter area 233, and the calculation result storage area 234, a storage area corresponding to the history memory 117 in the first embodiment may be set. In this case, it is necessary to increase the storage capacity required to store the history information, but since the management RAM 241 external to the MPU 62 is used as a storage means for storing the history information, it is possible to flexibly respond to an increase in storage capacity.

<Twenty-second embodiment>
In this embodiment, the processing configuration executed by the main CPU 63 is different from that of the fifteenth embodiment. The configuration that differs from the fifteenth embodiment will be described below. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 84 is a flowchart showing the main processing in this embodiment executed by the main CPU 63. Note that the processing of steps S5001 to S5019 in the main processing is executed by the main CPU 63 using a program for specific control and data for specific control.

First, the power-on wait process is executed (step S5001). In this power-on wait process, for example, the main process is started and a predetermined wait time (specifically, one second) elapses before proceeding to the next process. During the execution period of this power-on wait process, the operation start and initial settings of the pattern display device 41 are completed. After that, access to the main RAM 65 is permitted (step S5002).

Then, it is determined whether the reset button 68c has been pressed (step S5003), whether the setting key insertion section 68a has been turned ON using the setting key (step S5004), whether the front door frame 14 is open relative to the inner frame 13 (step S5005), and whether the gaming machine main body 12 is open relative to the outer frame 11 (step S5006).

In this embodiment, a front door open sensor 95 for detecting whether the front door frame 14 is open relative to the inner frame 13 is electrically connected to the main CPU 63, and the detection result of the front door open sensor 95 is input to the main CPU 63. In this case, when the front door frame 14 is closed relative to the inner frame 13, the front door open sensor 95 transmits a closed detection signal to the main CPU 63, and when the front door frame 14 is open relative to the inner frame 13, the front door open sensor 95 transmits an open detection signal to the main CPU 63. When the main CPU 63 receives a closed detection signal from the front door open sensor 95, it determines that the front door frame 14 is closed, and when it receives an open detection signal from the front door open sensor 95, it determines that the front door frame 14 is open.

In this embodiment, a main body open sensor 96 for detecting whether the gaming machine main body 12 is in an open state relative to the outer frame 11 is electrically connected to the main CPU 63, and the detection result of the main body open sensor 96 is input to the main CPU 63. In this case, when the gaming machine main body 12 is in a closed state relative to the outer frame 11, the main body open sensor 96 transmits a closed detection signal to the main CPU 63, and when the gaming machine main body 12 is in an open state relative to the outer frame 11, the main body open sensor 96 transmits an open detection signal to the main CPU 63. When the main CPU 63 receives a closed detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in a closed state, and when it receives an open detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in an open state.

If the reset button 68c is pressed (step S5003: YES) and a negative judgment is made in any of steps S5004 to S5006, a clear process for non-setting update is executed (step S5007). In the clear process for non-setting update, the specific control work area 221 is cleared to "0" except for the area (specifically, the setting value counter) in which the setting value information indicating the setting state of the pachinko machine 10 is set in the specific control work area 221, and the initial setting is performed for the area cleared to "0". As a result, the area indicating whether the winning/losing lottery mode is the high probability mode or not is cleared to "0", so that the winning/losing lottery mode becomes the low probability mode regardless of the winning/losing lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. In addition, the game round is not being executed, and the open/close execution mode is not being executed, and further, the normal map display unit 38a is not displayed in a variable manner and the normal power role 34a is in a closed state. In addition, the reserved storage area 65a and the regular power reserved area 65c provided in the work area 221 for specific control are also cleared to "0", so that the reserved information for the special map display section 37a is erased and the reserved information for the regular map display section 38a is erased. In addition, in the clearing process for non-setting updates, the stack area 222 for specific control is cleared to "0". In addition, in the clearing process for non-setting updates, various registers of the main CPU 63 are also cleared to "0" before being initialized.

In the clearing process when updating non-settings, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0". This makes it possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" even if the supply of operating power to the pachinko machine 10 is started while the reset button 68c is pressed.

If the reset button 68c is not pressed (step S5003: NO), it is determined whether the power failure flag is set to "1" (step S5008). The power failure flag is provided in the work area 221 for specific control, and if the supply of operating power to the main CPU 63 is stopped and the predetermined power failure processing is executed normally, the power failure flag is set to "1". If the power failure flag is set to "1", it is determined whether the checksum calculation result matches the checksum saved at the time of power interruption, that is, the validity of the stored data (step S5009). If the clear processing at the time of non-setting update is executed in step S5007, or if the judgment is affirmative in step S5009, it is determined whether the setting value of the pachinko machine 10 is normal by checking the value of the setting value counter in the work area 221 for specific control (step S5010). Specifically, if the setting value set in the setting value counter is any of "setting 1" to "setting 6", it is determined to be normal, and if it is "0" or 7 or more, it is determined to be abnormal.

If a negative judgment is made in any of steps S5008 to S5010, an operation prohibition process is executed. In the operation prohibition process, an error notification process is executed to notify the hall manager or the like of the occurrence of an error (step S5011), and then an infinite loop is entered. The operation prohibition process is released by executing a clear process (step S5018) when updating settings, which will be described later.

If the determination is affirmative in all of steps S5008 to S5010, a power-on setting process is executed (step S5012). In the power-on setting process, a predetermined area of the work area 221 for specific control, such as the initialization of the power outage flag, is set to an initial value, and a command corresponding to the current game state is sent to the sound and light emission control device 81.

The main CPU 63 is configured to periodically execute timer interrupt processing, but timer interrupt processing is prohibited from occurring when main processing is started. This state in which timer interrupt processing is prohibited is released when step S5012 is completed and before step S5013 is executed, and timer interrupt processing is permitted to be executed. As a result, when the supply of operating power to the main CPU 63 is started, the power-on setting process of step S5012 is completed, and timer interrupt processing is not executed until the stage before step S5013 is started. Therefore, processing to progress the game in the main CPU 63 is not started until this situation is reached.

Then, the process proceeds to the remaining process of steps S5013 to S5016. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but there is a remaining time between one timer interrupt processing and the next timer interrupt processing. This remaining time varies depending on the processing completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining process of steps S5013 to S5016. In this respect, the remaining process of steps S5013 to S5016 can be said to be non-periodic processing that is executed non-periodically. In steps S5013 to S5016, the same processing is executed as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

On the other hand, if the reset button 68c is pressed (step S5003: YES) and all of steps S5004 to S5006 are judged to be positive, a process for updating the setting value is executed. Specifically, a copy process of the setting value is executed first (step S5017). In the copy process, the information of the setting value counter used to specify the setting value of the pachinko machine 10 in the work area 221 for specific control is stored in a copy area provided in the work area 221 for specific control. As a result, even if the information of the setting value counter is cleared to "0" in the clear process (step S5018) executed afterwards when the setting value is updated, it is possible to grasp the setting value of the pachinko machine 10 before the clear process (i.e., the setting value of the pachinko machine 10 before the supply of operating power to the pachinko machine 10 is stopped) when the setting value is updated.

Then, the clearing process at the time of updating the settings is executed (step S5018). In the clearing process at the time of updating the settings, the work area 221 for specific control is cleared to "0" except for the area indicating whether the winning/losing lottery mode in the work area 221 for specific control is the high probability mode or not and the copy area, and the initial setting is performed for the area cleared to "0". As a result, the game round is not being executed, the open/close execution mode is not being executed, and further, the normal map display section 38a is not displaying a variable display and the normal power role 34a is in a closed state. In addition, the reserved storage area 65a and the normal power reserved area 65c provided in the work area 221 for specific control are also cleared to "0", so that the reserved information for the special map display section 37a is erased and the reserved information for the normal map display section 38a is erased. In addition, in the clearing process at the time of updating the settings, the stack area 222 for specific control is cleared to "0" and the initial setting is performed for the area cleared to "0". In addition, in the clearing process when updating the settings, the setting value counter used to identify the setting value of the pachinko machine 10 is cleared to "0." In addition, in the clearing process when updating the settings, various registers of the main CPU 63 are also cleared to "0" before performing initial settings.

On the other hand, the clearing process when updating the settings does not clear to "0" the area indicating whether the win/lose lottery mode is a high probability mode or not, so even if the setting value update process (step S5019) is executed, it is possible to maintain the win/lose lottery mode in the mode before the supply of operating power to the pachinko machine 10 was stopped. Also, since the clearing process when updating the settings does not clear to "0" the copy area, it is possible to subsequently identify the setting value that was set before the clearing process when updating the settings was executed.

The clearing process during setting updates does not clear the work area 223 for non-specific control and the stack area 224 for non-specific control to "0." This makes it possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" even if a setting value update process that can change the setting values of the pachinko machine 10 is executed.

Then, in step S5019, the setting value update process is executed, and the process proceeds to step S5012. The setting value update process is described below. FIG. 85 is a flowchart showing the setting value update process. Note that the processes in steps S5101 to S5114 in the setting value update process are executed in the main CPU 63 using a program for specific control and data for specific control.

First, the setting value counter provided in the work area 221 for specific control is set to "1" (step S5101). The setting value counter is a counter that allows the main CPU 63 to identify which setting value the setting state of the pachinko machine 10 is. By setting the setting value counter to "1", when the setting value update process is executed, the setting value becomes "Setting 1" regardless of the previous setting value.

Then, a process to start displaying the setting value is executed (step S5102). In the process to start displaying the setting value, the display of the third notification display device 69c is controlled so that the number "1" corresponding to "Setting 1" is displayed. When changing the setting value, the manager of the gaming hall can grasp the current setting state of the pachinko machine 10 by checking the third notification display device 69c.

Then, it is determined whether or not one game ball has been detected by the outlet detection sensor 48a (step S5103). Specifically, it is determined whether or not the signal received from the outlet detection sensor 48a has switched from a LOW level to a HIGH level. If a negative determination is made in step S5103, it is determined whether or not the update button 68b has been pressed once (step S5104). Specifically, it is determined whether or not the signal from the sensor that detects the pressing of the update button 68b has switched from a LOW level to a HIGH level. If a negative determination is made in step S5104, the process returns to step S5103, and it is determined whether or not one game ball has been detected by the outlet detection sensor 48a.

If the update button 68b has been pressed once (step S5104: YES), the value of the setting value counter in the work area 221 for specific control is incremented by 1 (step S5105). If the value of the setting value counter after incrementing by 1 exceeds "6" (step S5106: YES), the setting value counter is set to "1" (step S5107). As a result, the setting value is updated to the next higher level each time the update button 68b is pressed, and if the update button 68b is pressed once when the setting is "setting 6", the setting will return to "setting 1".

If a negative judgment is made in step S5106, or if the processing of step S5107 is executed, a display update process of the setting value is executed (step S5108). In the display update process of the setting value, the display of the third notification display device 69c is controlled so that a number corresponding to the value of the setting value counter in the work area 221 for specific control is displayed. By checking the third notification display device 69c, the manager of the gaming hall can grasp the setting state of the pachinko machine 10 after pressing the update button 68b.

After executing the process of step S5108, the process returns to step S5103, and it is determined whether or not one game ball has been detected by the outlet detection sensor 48a. If one game ball has not been detected by the outlet detection sensor 48a (step S5103: NO), the process of steps S5104 and onward is executed again. If one game ball has been detected by the outlet detection sensor 48a (step S5103: YES), it is determined whether or not the setting key insertion unit 68a has switched from the ON state to the OFF state (step S5109). In this case, it is not determined whether or not the setting key insertion unit 68a is in the OFF state, but rather whether or not a switch from the ON state to the OFF state has occurred, and if it is determined that the switch has occurred, a positive determination is made in step S5109.

If it has not been switched to the OFF state (step S5109: NO), the process of step S5109 is executed again. This causes the process to wait for the progress of the process until the setting key insertion section 68a is turned OFF. If it has been switched to the OFF state (step S5109: YES), a process to end the display of the setting value is executed (step S5110). In the process to end the display of the setting value, the display of the setting value on the third notification display device 69c is ended. In this case, the display of information on various parameters stored in the calculation result storage area 234 provided in the work area 223 for non-specific control is started on the first to third notification display devices 69a to 69c.

Then, a comparison process of the set values is executed (step S5111). In the comparison process of the set values, it is determined whether the information of the set value counter in the work area 221 for specific control matches the information stored in the copy area in the work area 221 for specific control. In other words, it is determined whether the set value that was set before the supply of operating power to the pachinko machine 10 was stopped is the same as the set value set in the current set value update process.

If the setting value that was set before the supply of operating power to the pachinko machine 10 was stopped is the same as the setting value set in this setting value update process (step S5112: NO), a process for notifying when no change has been made is executed (step S5113). In the process for notifying when no change has been made, a setting maintain command indicating that the setting value has not been changed is sent to the sound and light emission control device 81. Upon receiving the setting maintain command, the sound and light emission control device 81 causes the display light emitting unit 53 to emit light in a manner corresponding to maintaining the setting, and causes the speaker unit 54 to output a sound saying "The setting has been maintained." In addition, a text image saying "The setting has been maintained" is displayed on the pattern display device 41.

These notifications are maintained until the notification execution period (e.g., 10 seconds) has elapsed since the setting maintenance command was sent, and are terminated when the notification execution period has elapsed. However, this is not limited to this, and the notification may be terminated when the notification termination operation is performed by the manager of the game hall. The notification termination operation may be, for example, pressing the update button 68b or the reset button 68c. By checking the notification, the manager of the game hall can understand that the setting value has been maintained. In addition, in the notification process when no change is made, the display content on at least one of the first to third notification display devices 69a to 69c may be set to display content corresponding to the setting maintenance, thereby notifying that the setting value has been maintained, or an external output may be provided indicating that the setting value has been maintained.

If the setting value that was set before the supply of operating power to the pachinko machine 10 was stopped is not the same as the setting value set in this setting value update process (step S5112: YES), a notification process at the time of change is executed (step S5114). In the notification process at the time of change, a setting change command indicating that the setting value has been changed is sent to the sound and light emission control device 81. Upon receiving the setting change command, the sound and light emission control device 81 causes the display light emitting unit 53 to emit light in a manner corresponding to the setting change, and outputs a sound saying "The setting has been changed" from the speaker unit 54. In addition, a text image saying "The setting has been changed" is displayed on the pattern display device 41.

These notifications are maintained until the notification execution period (e.g., 10 seconds) has elapsed since the setting change command was sent, and are terminated when the notification execution period has elapsed. However, this is not limited to this, and the notification may be terminated when the notification termination operation is performed by the manager of the game hall. The notification termination operation may be, for example, pressing the update button 68b or the reset button 68c. By checking the notification, the manager of the game hall can understand that the setting value has been changed. In addition, in the notification process when the setting value is changed, the display content on at least one of the first to third notification display devices 69a to 69c may be changed to display content corresponding to the setting change, so that the setting value has been changed. An external output indicating that the setting value has been changed may be provided.

As described above, in this embodiment, in order for the setting value update process to be executed, not only must the setting key insertion section 68a be turned ON, but the reset button 68c must also be pressed, the front door frame 14 must be in the open state, and the gaming machine main body 12 must be in the open state. This makes it difficult to fraudulently execute the setting value update process.

In addition, the front door frame 14 and the gaming machine body 12 must be in an open state in order for the setting value update process to be executed. As a result, even if someone attempts to execute the setting value update process fraudulently, the fraudulent act will be noticeable because the front door frame 14 and the gaming machine body 12 are in an open state, making it easier for the manager of the amusement hall to discover the fraudulent act.

In particular, in order to execute the setting value update process, it is necessary not only to open the gaming machine main body 12, which is necessary to expose the main control device 60, but also to open the front door frame 14, which makes it possible to make the fraudulent acts more complicated and makes the fraudulent acts more noticeable.

In addition, in a configuration in which the game does not return to the process for progressing the game if the setting value update process is not completed, in order to confirm the setting value selected in the setting value update process and end the setting value update process, it is necessary to insert a game ball into the outlet 24a to have the outlet detection sensor 48a detect the game ball, and then turn off the setting key insertion unit 68a. This makes it possible to make it difficult to perform the operation to end the setting value update process and return to the process for progressing the game, even if the setting value update process is executed fraudulently.

In addition, the setting value that was set before the supply of operating power to the pachinko machine 10 was stopped is compared with the setting value selected in the setting value update process, and a notification is issued corresponding to whether or not the two setting values are the same. This allows the manager of the amusement hall to easily understand whether or not the setting value was changed by the setting value update process.

Figure 86 is a flowchart showing the timer interrupt processing in this embodiment executed by the main CPU 63. The timer interrupt processing is executed periodically (e.g., every 4 milliseconds) when the processing of steps S5013 to S5016 is being executed in the main processing (Figure 84). Note that the program corresponding to the timer interrupt processing is set in the program for specific control.

Steps S5201 to S5205 execute the same processes as steps S301 to S305 of the timer interrupt process (FIG. 11) in the first embodiment. These processes are executed by the main CPU 63 using a program for specific control and data for specific control.

Then, the setting confirmation process is executed (step S5206). When the setting confirmation process is executed, a subroutine program corresponding to the setting confirmation process set in the program for specific control is executed, and when the subroutine program is executed, information for specifying the return address of the timer interrupt process after the setting confirmation process is executed is written to the stack area 222 for specific control by a push command. Then, when the setting confirmation process is completed, information for specifying the return address is read by a pop command, and the program returns to the timer interrupt process program indicated by the return address.

Figure 87 is a flowchart showing the setting confirmation process. Note that the processing of steps S5301 to S5312 in the setting confirmation process is executed by the main CPU 63 using a program for specific control and data for specific control.

First, it is determined whether the third notification display device 69c is displaying a setting value corresponding to the information of the setting value counter in the work area 221 for specific control (step S5301). If a negative determination is made in step S5301, it is determined whether the mode is neither a game time nor an open/close execution mode (step S5302), whether the picture display unit 38a is displaying a variable pattern time, and whether the normal power role 34a is in a normal power open state in which it can be opened (step S5303), whether the front door frame 14 is in an open state relative to the inner frame 13 (step S5304), whether the gaming machine main body 12 is in an open state relative to the outer frame 11 (step S5305), and whether the setting key insertion unit 68a is turned ON (step S5306). Whether the front door frame 14 is open or not is determined based on the detection result of the front door open sensor 95, similar to step S5005 in the main processing (Figure 84), and whether the gaming machine main body 12 is open or not is determined based on the detection result of the main body open sensor 96, similar to step S5006 in the main processing (Figure 84).

If a negative judgment is made in any of steps S5302 to S5306, this setting confirmation process ends without executing the processes of steps S5307 to S5309. If a positive judgment is made in all of steps S5302 to S5306, a process to start displaying the setting value is executed (step S5307). In the process to start displaying the setting value, the display of the third notification display device 69c is controlled so that the setting value number corresponding to the information of the setting value counter in the work area 221 for specific control is displayed. When checking the setting value, the manager of the gaming hall can visually check the third notification display device 69c to grasp the current setting state of the pachinko machine 10.

After that, the game stop flag provided in the work area 221 for specific control is set to "1" (step S5308). The game stop flag is a flag for the master CPU 63 to identify whether or not a situation exists in which a positive judgment is made in step S5207 in the timer interrupt process (FIG. 86) and the processes of steps S5208 to S5221 are not executed, that is, whether or not the execution of the processes for progressing the game should be stopped. By setting the game stop flag to "1", a positive judgment is made in step S5207 of the timer interrupt process (FIG. 86) and the processes of steps S5208 to S5221 are not executed. This allows the setting value to be checked in a situation in which the execution of the processes for progressing the game is stopped. However, even if the game stop flag is set to "1", steps S5201 to S5205 of the timer interrupt process (Figure 86) are executed, so even if the set value is being checked, power outage monitoring is executed, the winning random number counter C1, the big win type counter C2, the reach random number counter C3, and the random number initial value counter CINI are updated, and further fraud detection is executed.

Then, a confirmation notification start command is sent to the audio and light-emitting control device 81 (step S5309). By receiving the confirmation notification start command, the audio and light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the setting confirmation in progress, and causes the speaker unit 54 to output a voice message saying "Settings are being confirmed." In addition, the pattern display device 41 is caused to display a text image saying "Settings are being confirmed." These notifications continue until a confirmation notification end command is received from the main CPU 63. Note that a configuration may also be adopted in which an external output is provided to indicate that the setting value is being confirmed.

As described above, under the condition that the game is not in play mode or open/close execution mode, and further, the game is not in a state in which the image on the normal picture display unit 38a is changing, or the normal power open state in which the normal power device 34a can be opened, a display for checking the setting value is displayed on the third notification display device 69c, making it possible to prevent the setting value from being checked while the game is being played.

In addition, in order for the display for checking the set value to be displayed on the third notification display device 69c, not only must the setting key insertion section 68a be turned ON, but the front door frame 14 must also be in the open state, and the gaming machine main body 12 must also be in the open state. This makes it difficult to fraudulently display the display for checking the set value.

In addition, in order for the display for checking the set value to be displayed on the third notification display device 69c, the front door frame 14 and the gaming machine main body 12 must be in an open state. As a result, even if someone tries to fraudulently display the display for checking the set value, the fraudulent behavior will be noticeable because the front door frame 14 and the gaming machine main body 12 are in an open state, making it easier for the manager of the amusement hall to discover the fraudulent behavior.

In particular, in order to have the display for checking the setting value displayed on the third notification display device 69c, it is necessary to open not only the gaming machine main body 12, which is necessary to expose the main control device 60, but also the front door frame 14, which makes it possible to make the above-mentioned fraudulent acts more complicated and makes the above-mentioned fraudulent acts more noticeable.

If a positive judgment is made in step S5301, it is judged whether or not the setting key insertion section 68a has been turned OFF (step S5310). If it has been turned OFF (step S5310: YES), the game stop flag in the work area 221 for specific control is cleared to "0" (step S5311). As a result, a negative judgment is made in step S5207 of the timer interrupt process (Figure 86), resulting in a situation in which the processes of steps S5208 to S5221 are executed. This releases the state in which the execution of processes for progressing the game is stopped.

Then, a confirmation notification end command is sent to the audio and light-emitting control device 81 (step S5312). By receiving the confirmation notification end command, the audio and light-emitting control device 81 ends the notification indicating that the setting values in the pattern display device 41, the display light-emitting unit 53, and the speaker unit 54 are being confirmed.

Returning to the explanation of the timer interrupt process (FIG. 86), after the setting confirmation process of step S5206 is completed, it is determined whether or not play is stopped (step S5207). In this case, if the game stop flag in the work area 221 for specific control is set to "1" in the setting confirmation process of step S5206, a positive determination is made in step S5207 and the processes of steps S5208 to S5221 are not executed. Also, if the occurrence of fraud is detected in the fraud detection process of step S5205, a positive determination is made in step S5207 and the processes of steps S5208 to S5221 are not executed.

Steps S5208 to S5219 execute the same processing as steps S307 to S318 of the timer interrupt processing (FIG. 11) in the first embodiment described above. These processing steps are executed by the main CPU 63 using a program for specific control and data for specific control. Also, step S5221 executes the same processing as step S3719 of the timer interrupt processing (FIG. 69) in the fifteenth embodiment described above.

Meanwhile, in step S5220, RAM monitoring processing is executed. When the RAM monitoring processing is executed, a subroutine program corresponding to the RAM monitoring processing set in the program for specific control is executed, and when the program for the subroutine is executed, information for specifying the return address of the timer interrupt processing after the RAM monitoring processing is executed is written to the stack area 222 for specific control by a push command. Then, when the RAM monitoring processing is completed, information for specifying the return address is read by a pop command, and the program returns to the timer interrupt processing program indicated by the return address.

Figure 88 is a flowchart showing the RAM monitoring process. Note that steps S5401 to S5412 in the RAM monitoring process are executed by the main CPU 63 using a program for specific control and data for specific control.

First, a monitoring process of the work area 221 for specific control is executed (step S5401). In the monitoring process, whether or not an abnormality occurs in the information stored in the work area 221 for specific control due to noise or the like is monitored. This monitoring method is arbitrary, but for example, a method of monitoring whether or not the state of a memory area in the work area 221 for specific control in which information is not written by various controls in the main CPU 63 is different from the initial state, and judging that an abnormality has occurred when the state is different from the initial state, can be mentioned. In this case, if the initial state of the memory area is a state of "0", it is judged that an abnormality has occurred when "1" is stored in the memory area, and if the initial state of the memory area is a state of "1", it is judged that an abnormality has occurred when the memory area is a value of "0". In addition to the above monitoring method, a configuration may be used in which an abnormality is judged to have occurred when the value of a specified byte is a value different from the value that can be set in a normal state.

If it is determined in step S5401 that an abnormality exists (step S5402: YES), execute the processes in steps S5409 to S5412. If it is determined in step S5401 that an abnormality does not exist (step S5402: NO), proceed to step S5403.

In step S5403, a monitoring process of the stack area 222 for specific control is executed. In this monitoring process, whether or not an abnormality has occurred in the information stored in the stack area 222 for specific control due to noise or the like is monitored. This monitoring method is arbitrary, but for example, a method of monitoring whether or not the state of a memory area in the stack area 222 for specific control in which no information is written by various controls in the main CPU 63 is different from the initial state, and judging that an abnormality has occurred when the state is different from the initial state, can be mentioned. In this case, if the initial state of the memory area is a state where the value of "0" is set, it is judged that an abnormality has occurred when "1" is stored in the memory area, and if the initial state of the memory area is a state where the value of "1" is set, it is judged that an abnormality has occurred when the value of the memory area is "0". In addition to the above monitoring method, a configuration may be used in which an abnormality is judged to have occurred when the value of a specified byte is a value different from the value that can be set in a normal state.

If it is determined in step S5403 that an abnormality exists (step S5404: YES), execute the processes in steps S5409 to S5412. If it is determined in step S5403 that an abnormality does not exist (step S5404: NO), proceed to step S5405.

In step S5405, a monitoring process of the work area 223 for non-specific control is executed. In the monitoring process, whether or not an abnormality occurs in the information stored in the work area 223 for non-specific control due to noise or the like is monitored. This monitoring method is arbitrary, but for example, a method of monitoring whether or not the state of a memory area in the work area 223 for non-specific control in which information is not written by various controls in the main CPU 63 is different from the initial state, and judging that an abnormality has occurred when the state is different from the initial state, can be mentioned. In this case, if the initial state of the memory area is a state where the value of "0" is set, it is judged that an abnormality has occurred when "1" is stored in the memory area, and if the initial state of the memory area is a state where the value of "1" is set, it is judged that an abnormality has occurred when the value of the memory area is "0". In addition to the above monitoring method, a configuration may be used in which an abnormality is judged to have occurred when the value of a specified byte is a value different from the value that can be set in a normal state.

If it is determined in step S5405 that an abnormality exists (step S5406: YES), execute the processes of steps S5409 to S5412. If it is determined in step S5405 that an abnormality does not exist (step S5406: NO), proceed to step S5407.

In step S5407, a monitoring process of the non-specific control stack area 224 is executed. In this monitoring process, whether or not an abnormality has occurred in the information stored in the non-specific control stack area 224 due to noise or the like is monitored. This monitoring method is arbitrary, but for example, a method of monitoring whether or not the state of the memory area in the non-specific control stack area 224 in which information is not written by various controls in the main CPU 63 is different from the initial state, and judging that an abnormality has occurred when the state is different from the initial state, can be mentioned. In this case, if the initial state of the memory area is a state where the value of "0" is set, it is judged that an abnormality has occurred when "1" is stored in the memory area, and if the initial state of the memory area is a state where the value of "1" is set, it is judged that an abnormality has occurred when the value of the memory area is "0". In addition to the above monitoring method, a configuration may be used in which an abnormality is judged to have occurred when the value of a specified byte is a value different from the value that can be set in a normal state.

If it is determined in step S5407 that an abnormality exists (step S5408: YES), the processes of steps S5409 to S5412 are executed. Specifically, a setting value copy process is executed first (step S5409). In this copy process, the setting value counter information used to identify the setting value of the pachinko machine 10 in the work area 221 for specific control is stored in a copy area provided in the work area 221 for specific control. As a result, even if the setting value counter information is cleared to "0" in the abnormality clear process (step S5410) executed subsequently, it is possible to know the setting value of the pachinko machine 10 before the abnormality clear process was executed.

Then, a clear process is performed when an abnormality occurs (step S5410). In the clear process when an abnormality occurs, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control are cleared to "0". After clearing to "0", an initial setting is performed. In other words, in the RAM monitoring process, if it is determined that an abnormality has occurred in any one of the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control are cleared to "0". This makes it possible to prevent any process corresponding to specific control and any process corresponding to non-specific control from being executed in the current state when there is a possibility that some information abnormality has occurred in the main RAM 65.

When the stack area 222 for specific control is cleared to "0", the return address information after the RAM monitoring process is executed is also erased. Therefore, when the stack area 222 for specific control is cleared to "0", after the process of step S5412 is completed, a specific program is returned to unambiguously. Specifically, the process is configured to unambiguously return to the process of step S5013 in the main process (FIG. 22). However, the program to which the specific control is returned unambiguously is not limited to step S5013, and may be step S5221 in the timer interrupt process (FIG. 86). Furthermore, when the stack area 222 for specific control is cleared to "0", the stack pointer of the main CPU 63 is also set to the address of the first memory area in the storage order in the stack area 222 for specific control.

Then, an abnormal command indicating that the abnormal clear process has occurred is sent to the sound and light emission control device 81 (step S5411). By receiving the abnormal command, the sound and light emission control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the forced clear, and causes the speaker unit 54 to output a voice saying "Forced clear has been performed." In addition, the pattern display device 41 is made to display a text image saying "Forced clear has been performed." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the above notification may be terminated when the notification termination operation is performed by the manager of the game hall. For example, the update button 68b may be pressed as the notification termination operation, or the reset button 68c may be pressed. By confirming the above notification, the manager of the game hall can understand that the main RAM 65 has been forced cleared.

Then, the setting value update process is executed (step S5412). In other words, when the abnormality clear process is executed, the setting value counter in the work area 221 for specific control is cleared to "0", and the setting value update process is executed to reset the setting value of the pachinko machine 10. The processing content of the setting value update process is the same as step S5019 of the main process (Fig. 84). Therefore, each time the update button 68b is pressed once, the setting value is updated by one step, and the selected setting value is confirmed by detecting a game ball with the outlet detection sensor 48a. The setting value being updated and the confirmed setting value are displayed on the third notification display device 69c. After that, when the setting key insertion section 68a switches from the ON state to the OFF state, it is determined that the end condition of the setting value update process is satisfied.

Here, the termination condition is not determined to be met just because the setting key insertion section 68a is in the OFF state; the termination condition is determined to be met when the setting key insertion section 68a switches from the ON state to the OFF state. When the setting value update process is executed in the RAM monitoring process (Figure 88), the setting key insertion section 68a is in the OFF state at the start of the setting value update process, so in order to establish the termination condition of the setting value update process, it is necessary to insert the setting key into the setting key insertion section 68a and turn it ON once, and then turn it OFF. This makes it possible to prevent the setting value update process from terminating even if the correct operation has not been performed by the amusement hall manager.

When the setting key insertion section 68a switches from ON to OFF and the end condition of the setting value update process is satisfied, step S5111 in the setting value update process (FIG. 85) is executed to compare whether the setting value stored in the copy area in the work area 221 for specific control is the same as the setting value currently set in the setting value counter in the work area 221 for specific control. In other words, it is determined whether the setting value that was set before the abnormality clear process (step S5410) was executed is the same as the setting value set in the current setting value update process. If the two setting values are the same (step S5112: NO), the non-change notification process (step S5113) is executed to perform the setting maintenance notification already described. On the other hand, if the two setting values are different (step S5112: YES), the change notification process (step S5114) is executed to perform the setting change notification already described.

The present embodiment described above provides the following excellent advantages:

In order for the setting value update process to be executed when the supply of operating power to the pachinko machine 10 is started, not only must the setting key insertion section 68a be turned ON, but the reset button 68c must also be pressed, the front door frame 14 must be in the open state, and the gaming machine main body 12 must be in the open state. This makes it difficult for someone to fraudulently execute the setting value update process.

The front door frame 14 and the gaming machine body 12 must be in an open state in order for the setting value update process to be executed. As a result, even if someone attempts to execute the setting value update process fraudulently, the front door frame 14 and the gaming machine body 12 are in an open state, making the fraudulent act noticeable, and making it easier for the manager of the amusement hall to discover the fraudulent act.

In particular, in order to execute the setting value update process, it is necessary not only to open the gaming machine main body 12, which is necessary to expose the main control device 60, but also to open the front door frame 14, which makes it possible to make the fraudulent acts more complicated and makes the fraudulent acts more noticeable.

In a configuration in which the process for progressing the game is not returned to if the setting value update process is not completed, in order to confirm the setting value selected in the setting value update process and end the setting value update process, it is necessary to insert a game ball into the outlet 24a to have the outlet detection sensor 48a detect the game ball, and then turn off the setting key insertion unit 68a. This makes it possible to make it difficult to perform operations to end the setting value update process and return to the process for progressing the game, even if the setting value update process is executed fraudulently.

The setting value that was set before the supply of operating power to the pachinko machine 10 was stopped is compared with the setting value selected in the setting value update process, and a notification is issued corresponding to whether or not the two setting values are the same. This allows the manager of the amusement hall to easily understand whether or not the setting value was changed by the setting value update process.

By having the third notification display device 69c display a message to check the setting value when the game is not in play or open/close execution mode, and when the game is not in a state where the image on the normal picture display unit 38a is not changing, or when the normal power device 34a is not in a normal power open state in which it can be opened, it is possible to prevent the setting value from being checked while the game is being played.

In order for the display for checking the set value to be displayed on the third notification display device 69c, not only must the setting key insertion section 68a be turned ON, but the front door frame 14 must also be in the open state, and the gaming machine main body 12 must also be in the open state. This makes it difficult to fraudulently display the display for checking the set value.

In order for the display for checking the set value to be displayed on the third notification display device 69c, the front door frame 14 and the gaming machine main body 12 must be in an open state. As a result, even if someone tries to fraudulently display the display for checking the set value, the fraudulent behavior will be noticeable because the front door frame 14 and the gaming machine main body 12 are in an open state, making it easier for the manager of the amusement hall to discover the fraudulent behavior.

In particular, in order to have the display for checking the setting value displayed on the third notification display device 69c, it is necessary to open not only the gaming machine main body 12, which is necessary to expose the main control device 60, but also the front door frame 14, making it possible to make the above-mentioned fraudulent acts more complicated and to make the above-mentioned fraudulent acts more noticeable.

If it is determined that an abnormality has occurred in any one of the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control are cleared to "0". This makes it possible to prevent any processing corresponding to specific control and any processing corresponding to non-specific control from being executed in the current state if there is a possibility that some information abnormality has occurred in the main RAM 65.

In the process corresponding to the specific control, not only the work area 221 for specific control and the stack area 222 for specific control, but also the work area 223 for non-specific control and the stack area 224 for non-specific control are monitored for information anomalies. This makes it possible to simplify the processing configuration compared to a configuration in which information anomalies are monitored separately for processes corresponding to specific control and processes corresponding to non-specific control.

If it is determined that an abnormality has occurred in any one of the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control, not only the work area 221 for specific control and the stack area 222 for specific control, but also the work area 223 for non-specific control and the stack area 224 for non-specific control are cleared to "0" in the process corresponding to the specific control. This makes it possible to simplify the processing configuration compared to a configuration in which "0" clearing is performed separately for the process corresponding to specific control and the process corresponding to non-specific control.

When an abnormality occurs and the abnormality clear process is executed, the setting value update process is executed. This makes it possible to prevent the game from proceeding even if the setting value has not been set. In this case, if the setting value set before the abnormality clear process is executed and the setting value set in the setting value update process after the abnormality clear process are executed are the same, a setting maintenance notification is issued. As a result, even if the abnormality clear process is executed, the setting value set in the previous situation is reset to be notified, and it is possible to clearly inform the player that the setting value has not changed even if the abnormality clear process is executed. Incidentally, since it is common for the setting values of each pachinko machine 10 installed in amusement halls to be recorded, it is possible to execute the setting value update process after the abnormality clear process is executed so that the recorded setting value is used.

The conditions for executing the setting value update process when the supply of operating power to the pachinko machine 10 is started may be different from those in the above embodiment. Figure 89 is a flowchart showing another form of main processing. In this main processing, steps S5501 to S5506 and steps S5508 to S5520 execute the same processes as steps S5001 to S5019 in the main processing (Figure 84) in the above embodiment. Meanwhile, in this main processing, in step S5507, it is determined whether the operating handle of the launch operating device 28, which is operated to launch the game ball into the game area PA, has been rotated from the initial rotation position. Then, when the reset button 68c is pressed (step S5503: YES), the setting key insertion section 68a is turned ON (step S5504: YES), the front door frame 14 is opened relative to the inner frame 13 (step S5505: YES), the gaming machine main body 12 is opened relative to the outer frame 11 (step S5506: YES), and the operation handle of the launch operation device 28 is rotated from the initial rotation position (step S5507: YES), the setting value update process (step S5520) is executed. As a result, in order to execute the setting value update process when the supply of operating power to the pachinko machine 10 is started, it is necessary not only to insert the setting key into the setting key insertion section 68a and perform the ON operation, but also to start the supply of operating power to the pachinko machine 10 with the operating handle of the launch operation device 28 rotated. Therefore, it is possible to make it difficult to perform an act of illegally changing the setting value. Note that, instead of determining whether the operating handle of the firing operation device 28 has been rotated from the initial rotation position in step S5507, the configuration may be such that it determines whether the firing operation device 28 has been touched by the player.

In addition, the conditions for the setting value update process to be executed when the supply of operating power to the pachinko machine 10 is started are set to both that the front door frame 14 is open relative to the inner frame 13 and that the gaming machine main body 12 is open relative to the outer frame 11, but it is also possible to set only one of these conditions.

In addition, the condition for executing the setting value update process when the supply of operating power to the pachinko machine 10 is started is that the reset button 68c is pressed, but the configuration may be such that this condition is not set.

In addition, a configuration may be adopted in which the condition for executing the setting value update process when the supply of operating power to the pachinko machine 10 is started is that the supply of operating power to the pachinko machine 10 is started in a situation where a gaming ball is detected by the gate detection sensor 49a. As a result, in order for the setting value update process to be executed when the supply of operating power to the pachinko machine 10 is started, it is necessary not only to insert the setting key into the setting key insertion section 68a and turn it ON, but also to start the supply of operating power to the pachinko machine 10 with a gaming ball remaining in the through gate 35. This makes it difficult to perform an act of illegally changing the setting value.

In addition, the contents of the operation for confirming the set value in the set value update process may be different from those in the above embodiment. FIG. 90 is a flowchart showing a set value update process in another form. In this set value update process, steps S5601 to S5602 and steps S5604 to S5614 execute the same processes as steps S5101 to S5102 and steps S5104 to S5114 of the set value update process in the above embodiment (FIG. 85). On the other hand, in this set value update process, in step S5603, it is not determined whether or not the outlet detection sensor 48a has detected a game ball, but rather it is determined whether or not the ON continuation period during which the ON signal is continuously output from the gate detection sensor 49a is equal to or longer than the end reference period (specifically, 5 seconds). Then, if a positive determination is made in step S5603, the selected set value is confirmed and the process proceeds to step S5609. According to this configuration, in order to confirm the selected set value, it is necessary to intentionally hold the game ball in the through gate 35 for more than the end reference period. In a situation where a normal game is being played, a game ball will not remain in the through gate 35 for a period longer than the end reference period. This makes it possible to make it so that the conditions for finalizing the selected setting value are not met or are difficult to meet in a situation where a normal game is being played. Also, even if the setting value update process is started fraudulently, it is possible to make it difficult to perform an operation to finalize the setting value selected in the setting value update process.

In addition, in the setting value update process, the selected setting value may be confirmed when the operating handle of the firing operation device 28 is rotated from the initial rotation position, or the selected setting value may be confirmed when the firing operation device 28 is touched by the player.

In addition, in the setting value update process, the selected setting value may be determined when the special electric detection sensor 45a detects that a game ball has entered the special electric winning device 32 provided with an opening and closing member, or the selected setting value may be determined when the second operating port detection sensor 47a detects that a game ball has entered the second operating port 34 provided with an opening and closing member. In this case, in order to determine the selected setting value, it is necessary to manually open the target ball entry section and then handle the game ball, making it difficult to fraudulently change the setting value.

In addition, in the setting value update process, the selected setting value may be determined based on the detection of a game ball entering the first ball entry section and then the detection of a game ball entering the second ball entry section. In this case, in order to determine the selected setting value, it is necessary to manually enter game balls into multiple ball entry sections in a specified order, making it difficult to illegally change the setting value. In this case, by making both the first ball entry section and the second ball entry section ball entry sections that are not provided with opening and closing members, it is possible to prevent the ease of performing regular work from being extremely reduced.

In addition, in the setting value update process, the setting key insertion section 68a may be switched from the ON state to the OFF state, so that the selected setting value is confirmed and the end condition for the setting value update process is met.

In addition, the operation for updating the setting value by one step in the setting value update process is not limited to pressing the update button 68b, but may be configured so that the setting value is updated by one step by pressing the reset button 68c.

In addition, when the reset button 68c is pressed and the setting key insertion section 68a is turned ON by the setting key, the supply of operating power to the pachinko machine 10 is started, and when the front door frame 14 is not open relative to the inner frame 13 or the gaming machine main body 12 is not open relative to the outer frame 11, the configuration is not limited to one in which the clear process at the time of non-setting update (step S5007) is executed, and the clear process at the time of non-setting update may not be executed. This makes it possible to prevent the clear process at the time of non-setting update from being executed against the will of the manager of the gaming hall.

In addition, when the supply of operating power to the pachinko machine 10 is started in a situation where the reset button 68c is pressed and the setting key insertion section 68a is not turned ON by the setting key, and when the front door frame 14 is not open relative to the inner frame 13 or the gaming machine main body 12 is not open relative to the outer frame 11, the configuration is not limited to one in which the clear process at the time of non-setting update (step S5007) is executed, and the clear process at the time of non-setting update may not be executed. This makes it difficult to illegally execute the clear process at the time of non-setting update.

<Twenty-third embodiment>
In this embodiment, the processing configuration of the main processing is different from that of the twenty-second embodiment. The configuration that differs from the twenty-second embodiment will be described below. Note that the description of the same configuration as the twenty-second embodiment will basically be omitted.

Figure 91 is a flowchart showing the main processing in this embodiment executed by the main CPU 63. Note that the processing of steps S5701 to S5720 in the main processing is executed by the main CPU 63 using a program for specific control and data for specific control.

First, the power-on wait process is executed (step S5701). In this power-on wait process, for example, the main process is started and then a predetermined wait time (specifically, one second) elapses before proceeding to the next process. During the execution period of this power-on wait process, the operation start and initial settings of the pattern display device 41 are completed. After that, access to the main RAM 65 is permitted (step S5702).

Then, based on the detection result of the front door open sensor 95, it is determined whether or not the front door frame 14 is open relative to the inner frame 13 (step S5703), based on the detection result of the main body open sensor 96, it is determined whether or not the gaming machine main body 12 is open relative to the outer frame 11 (step S5704), and it is determined whether or not the reset button 68c has been pressed (step S5705). If a negative determination is made in any of steps S5703 to S5705, the processing of steps S5706 to S5714 is executed. The processing of these steps S5706 to S5714 is the same as steps S5008 to S5016 in the main processing (Figure 84) in the above-mentioned 22nd embodiment.

If all of steps S5703 to S5705 are judged to be positive, a selection process is executed (step S5715). In the selection process, a process is executed to determine whether the situation is one in which a clear process is executed when no settings are updated and the setting value update process is not executed, or one in which a clear process is executed when settings are updated and the setting value update process is executed, based on a selection operation by the manager of the amusement hall. Specifically, each time the update button 68b is pressed once, the situation is switched from one of the above situations being selected to the other situation being selected. Note that the selection operation may be performed by operating the reset button 68c, or may be performed by operating another operating unit. In addition, if a situation in which the clear process is executed when the setting is not updated and the setting value update process is not executed is selected, the first notification display device 69a displays "O" and the second notification display device 69b and the third notification display device 69c are turned off, and if a situation in which the clear process is executed when the setting is updated and the setting value update process is executed is selected, the second notification display device 69b displays "O" and the first notification display device 69a and the third notification display device 69c are turned off. In addition, if the reset button 68c is pressed continuously for a confirmation selection period (specifically, 10 seconds) or more, the selected one of the above situations is confirmed as the current selection target.

The configuration may be such that when the update button 68b is continuously pressed for a selection period (specifically, 10 seconds) or longer, the selected one of the above situations is confirmed as the current selection target, or when another operating unit is continuously pressed for a selection period (specifically, 10 seconds) or longer, the selected one of the above situations is confirmed as the current selection target. Also, the configuration may be such that when the operating handle of the firing operating device 28 is rotated, the selected one of the above situations is confirmed as the current selection target.

In the selection process, if the situation in which the clear process for non-setting updates is executed and the setting value update process is not executed is confirmed as the current selection target (step S5716: NO), the clear process for non-setting updates is executed (step S5717). The processing content of the clear process for non-setting updates is the same as that of step S5007 in the main process (FIG. 84) in the above 22nd embodiment.

In the selection process, if the situation in which the clear process at the time of updating the settings and the setting value update process are executed is confirmed as the current selection target (step S5716: YES), the setting value copy process is executed (step S5718), the clear process at the time of updating the settings is executed (step S5719), and the setting value update process is executed (step S5720). The processing content of these steps S5718 to S5720 is the same as steps S5017 to S5019 of the main process (Figure 84) in the above 22nd embodiment.

With the above configuration, even if the configuration does not include the setting key insertion unit 68a, the amusement hall manager can select between a situation in which the clear process is executed when no setting is updated and the setting value update process is not executed, and a situation in which the clear process is executed when the setting is updated and the setting value update process is executed.

In addition to when executing the setting value update process, even when executing the clear process when no setting update is performed, when the reset button 68c is pressed, not only does it have to start supplying operating power to the pachinko machine 10, but it also has to open the front door frame 14 relative to the inner frame 13 and open the gaming machine main body 12 relative to the outer frame 11. This makes it difficult to fraudulently execute the clear process when no setting update is performed.

In addition, the conditions for the selection process to be executed when the supply of operating power to the pachinko machine 10 is started are set to both that the front door frame 14 is open relative to the inner frame 13 and that the gaming machine main body 12 is open relative to the outer frame 11, but it is also possible to set only one of these conditions.

In addition, as a condition for executing the selection process when the supply of operating power to the pachinko machine 10 is started, a condition that the launch handle of the launch operation device 28 is rotated, a condition that the launch operation device 28 is touched, or a condition that a game ball is detected by the gate detection sensor 49a may be added.

<Twenty-fourth embodiment>
In this embodiment, the processing configuration of the RAM monitoring process is different from that of the twenty-second embodiment. The configuration that differs from the twenty-second embodiment will be described below. Note that the description of the same configuration as the twenty-second embodiment will basically be omitted.

Figure 92 is a flowchart showing the RAM monitoring process in this embodiment, which is executed by the main CPU 63. Note that the processes in steps S5801 to S5814 in the RAM monitoring process are executed by the main CPU 63 using a program for specific control and data for specific control.

First, a monitoring process of the work area 221 for specific control is executed (step S5801). The contents of the monitoring process are the same as step S5401 of the RAM monitoring process (FIG. 88) in the 22nd embodiment. If it is determined in step S5801 that an abnormality exists (step S5802: YES), the processes of steps S5805 to S5808 are executed.

If it is determined in step S5801 that no abnormality exists (step S5802: NO), a monitoring process of the specific control stack area 222 is executed (step S5803). The contents of this monitoring process are the same as step S5403 of the RAM monitoring process (FIG. 88) in the 22nd embodiment. If it is determined in step S5803 that an abnormality exists (step S5804: YES), the processes of steps S5805 to S5808 are executed.

Regarding the processing of steps S5805 to S5808 in detail, a copy process of the setting values is first executed (step S5805). In this copy process, the information of the setting value counter used to identify the setting value of the pachinko machine 10 in the work area 221 for specific control is stored in a copy area provided in the work area 221 for specific control. As a result, even if the information of the setting value counter is cleared to "0" in the subsequent abnormality clear process (step S5806), it is possible to know the setting value of the pachinko machine 10 before the abnormality clear process was executed.

Then, a clear process is performed when an abnormality occurs (step S5806). In the clear process when an abnormality occurs, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is cleared to "0". After clearing to "0", the initial settings are performed. On the other hand, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0". In other words, in the RAM monitoring process in this embodiment, when it is determined that an abnormality has occurred in either the work area 221 for specific control or the stack area 222 for specific control, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is cleared to "0". This makes it possible to prevent the process corresponding to the specific control from being executed in the current state when there is a possibility that some information abnormality has occurred in the work area 221 for specific control or the stack area 222 for specific control. Furthermore, even if an information abnormality occurs in the work area 221 for specific control or the stack area 222 for specific control, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0", so that it is possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" as a result of an information abnormality in the work area 221 for specific control or the stack area 222 for specific control.

When the stack area 222 for specific control is cleared to "0", the return address information after the RAM monitoring process is executed is also erased. Therefore, when the stack area 222 for specific control is cleared to "0", after the process of step S5808 is completed, a specific program is returned to unambiguously. Specifically, the process is configured to unambiguously return to the process of step S5013 in the main process (FIG. 22). However, the program to which the specific control is returned unambiguously is not limited to step S5013, and may be step S5221 in the timer interrupt process (FIG. 86). Furthermore, when the stack area 222 for specific control is cleared to "0", the stack pointer of the main CPU 63 is also set to the address of the first memory area in the memory order in the stack area 222 for specific control.

Then, an abnormal command indicating that the abnormal clear process has occurred is sent to the sound and light emission control device 81 (step S5807). By receiving the abnormal command, the sound and light emission control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the forced clear, and causes the speaker unit 54 to output a voice saying "Forced clear has been performed." In addition, the pattern display device 41 is configured to display a text image saying "Forced clear has been performed." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the above notification may be terminated when the notification termination operation is performed by the manager of the game hall. For example, the update button 68b may be pressed as the notification termination operation, or the reset button 68c may be pressed. By confirming the above notification, the manager of the game hall can understand that the work area 221 for specific control and the stack area 222 for specific control have been forced cleared.

Then, the setting value update process is executed (step S5808). The processing content of the setting value update process is the same as that of step S5412 in the RAM monitoring process (Figure 88) in the 22nd embodiment.

If it is determined that there is no abnormality in both steps S5801 and S5803 (steps S5802 and S5804: NO), a monitoring process of the work area 223 for non-specific control is executed (step S5809). The contents of the monitoring process are the same as step S5405 of the RAM monitoring process (FIG. 88) in the 22nd embodiment. If it is determined that there is an abnormality in step S5809 (step S5810: YES), the work area 223 for non-specific control is cleared to "0" and initialized (step S5811). In this case, the normal counter area 231, the counter area 232 for the open/close execution mode, the counter area 233 for the high frequency support mode, the calculation result storage area 234, and the management start flag are all cleared to "0". This makes it possible to resolve the information abnormality in the work area 223 for non-specific control.

On the other hand, in step S5811, the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control are not cleared to "0". This makes it possible to prevent the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control from being cleared to "0" even if an information abnormality occurs in the work area 223 for non-specific control.

In step S5811, the normal counter area 231, the counter area for opening and closing execution mode 232, the counter area for high-frequency support mode 233, and the calculation result storage area 234 may be cleared to "0", but the management start flag may not be cleared to "0". In step S5811, the normal counter area 231, the counter area for opening and closing execution mode 232, the counter area for high-frequency support mode 233, and the management start flag may be cleared to "0", but the calculation result storage area 234 may not be cleared to "0". In step S5811, the normal counter area 231, the counter area for opening and closing execution mode 232, and the counter area for high-frequency support mode 233 may be cleared to "0", but the calculation result storage area 234 and the management start flag may not be cleared to "0".

If a negative determination is made in step S5810 or if the processing of step S5811 is executed, a monitoring process of the stack area 224 for non-specific control is executed (step S5812). The content of this monitoring process is the same as that of step S5407 of the RAM monitoring process (FIG. 88) in the 22nd embodiment described above. If it is determined in step S5812 that an abnormality exists (step S5813: YES), the stack area 224 for non-specific control is cleared to "0" and initialized (step S5814). This makes it possible to resolve the information abnormality in the stack area 224 for non-specific control.

On the other hand, in step S5814, the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control are not cleared to "0". This makes it possible to prevent the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control from being cleared to "0" even if an information anomaly occurs in the stack area 224 for non-specific control.

According to the above configuration, if it is determined that an abnormality has occurred in either the work area 221 for specific control or the stack area 222 for specific control, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is cleared to "0". This makes it possible to prevent the processing corresponding to the specific control from being executed in the current state if there is a possibility that some information abnormality has occurred in the work area 221 for specific control or the stack area 222 for specific control.

Even if an information abnormality occurs in the work area 221 for specific control or the stack area 222 for specific control, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0". This makes it possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" as a result of an information abnormality in the work area 221 for specific control or the stack area 222 for specific control.

Even if an information abnormality occurs in the work area 223 for non-specific control, the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control are not cleared to "0". This makes it possible to prevent the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control from being cleared to "0" in response to an information abnormality in the work area 223 for non-specific control.

Even if an information abnormality occurs in the stack area 224 for non-specific control, the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control are not cleared to "0". This makes it possible to prevent the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control from being cleared to "0" as a result of an information abnormality in the stack area 224 for non-specific control.

In addition, if an information abnormality occurs in the work area 221 for specific control, the work area 221 for specific control except for the copy area is cleared to "0", but the stack area 222 for specific control may not be cleared to "0".

Also, if an information anomaly occurs in the stack area 222 for specific control, the stack area 222 for specific control may be cleared to "0", but the work area 221 for specific control may not be cleared to "0". In this case, the processing of steps S5805 to S5808 may not be executed even if the stack area 222 for specific control is cleared to "0".

<Twenty-fifth embodiment>
In this embodiment, the processing configuration for monitoring whether or not an information anomaly has occurred in each of the areas 221 to 224 of the main RAM 65 is different from that of the 22nd embodiment. The configuration that differs from the 22nd embodiment will be described below. Note that the description of the same configuration as the 22nd embodiment will basically be omitted.

Figure 93 is a flowchart showing the RAM monitoring process in this embodiment, which is executed by the main CPU 63. Note that the processes in steps S5901 to S5908 in the RAM monitoring process are executed by the main CPU 63 using a program for specific control and data for specific control.

First, a monitoring process of the work area 221 for specific control is executed (step S5901). The contents of the monitoring process are the same as step S5401 of the RAM monitoring process (FIG. 88) in the 22nd embodiment. If it is determined in step S5901 that an abnormality exists (step S5902: YES), the processes of steps S5905 to S5908 are executed.

If it is determined in step S5901 that no abnormality exists (step S5902: NO), a monitoring process of the specific control stack area 222 is executed (step S5903). The contents of this monitoring process are the same as those of step S5403 in the RAM monitoring process (FIG. 88) in the 22nd embodiment. If it is determined in step S5903 that an abnormality exists (step S5904: YES), the processes of steps S5905 to S5908 are executed.

Regarding the process of steps S5905 to S5908 in detail, a copy process of the setting values is first executed (step S5905). In this copy process, the information of the setting value counter used to identify the setting value of the pachinko machine 10 in the work area 221 for specific control is stored in a copy area provided in the work area 221 for specific control. As a result, even if the information of the setting value counter is cleared to "0" in the subsequent abnormality clear process (step S5906), it is possible to know the setting value of the pachinko machine 10 before the abnormality clear process was executed.

Then, a clear process is performed when an abnormality occurs (step S5906). In the clear process when an abnormality occurs, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is cleared to "0". In addition, after clearing to "0", the initial setting is performed. On the other hand, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0". In other words, in the RAM monitoring process in this embodiment, when it is determined that an abnormality has occurred in either the work area 221 for specific control or the stack area 222 for specific control, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is cleared to "0". This makes it possible to prevent the process corresponding to the specific control from being executed in the current state when there is a possibility that some information abnormality has occurred in the work area 221 for specific control or the stack area 222 for specific control. Furthermore, even if an information abnormality occurs in the work area 221 for specific control or the stack area 222 for specific control, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0", so that it is possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" as a result of an information abnormality in the work area 221 for specific control or the stack area 222 for specific control.

Then, an abnormal command indicating that a clear process has occurred during an abnormality is sent to the sound and light emission control device 81 (step S5907). By receiving the abnormal command, the sound and light emission control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the forced clear of the work area 221 for specific control and the stack area 222 for specific control, and causes the speaker unit 54 to output a voice saying, "A forced clear has been performed for specific control." In addition, the pattern display device 41 is made to display a text image saying, "A forced clear has been performed for specific control." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the above notification may be terminated when a notification termination operation is performed by the manager of the game hall. For example, the update button 68b may be pressed as the notification termination operation, or the reset button 68c may be pressed. By checking the above notification, the manager of the amusement hall can understand that the work area 221 for specific control and the stack area 222 for specific control have been forcibly cleared.

Then, the setting value update process is executed (step S5908). The processing content of the setting value update process is the same as that of step S5412 in the RAM monitoring process (Figure 88) in the 22nd embodiment.

As described above, in the RAM monitoring process executed using the program for specific control and data for specific control, the work area 221 for specific control and the stack area 222 for specific control are monitored for information abnormalities, but the work area 223 for non-specific control and the stack area 224 for non-specific control are not monitored for information abnormalities. The monitoring of the work area 223 for non-specific control and the stack area 224 for non-specific control for information abnormalities is executed by a process corresponding to non-specific control in which the program for non-specific control and data for non-specific control are used.

Figure 94 is a flowchart showing the management execution process in this embodiment executed by the main CPU 63. Note that the management execution process is executed by reading out a subroutine program in the management process (Figure 70) in the same way as in the 15th embodiment. Also, the processes in steps S6001 to S6016 in the management execution process are executed in the main CPU 63 using a program for non-specific control and data for non-specific control.

Steps S6001 to S6008 and steps S6010 to S6016 execute the same processing as steps S3901 to S3915 of the management execution process (FIG. 71) in the fifteenth embodiment. In addition, step S6009 executes another monitoring process. When the other monitoring process is executed, a subroutine program corresponding to the other monitoring process set in the program for non-specific control is executed, and when the program for the subroutine is executed, information for specifying the return address of the management execution process after the execution of the other monitoring process is written to the stack area 224 for non-specific control by a push command. Then, when the other monitoring process is completed, information for specifying the return address is read by a pop command, and the program for the management execution process indicated by the return address is returned to.

Figure 95 is a flowchart showing the separate monitoring process. Note that the processing of steps S6101 to S6108 in the separate monitoring process is executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

First, a monitoring process is performed on the work area 223 for non-specific control (step S6101). The content of this monitoring process is the same as step S5405 of the RAM monitoring process (FIG. 88) in the 22nd embodiment. If it is determined in step S6101 that there is an abnormality (step S6102: YES), the work area 223 for non-specific control is cleared to "0" and initialized (step S6103). In this case, the normal counter area 231, the counter area 232 for opening/closing execution mode, the counter area 233 for high frequency support mode, the calculation result storage area 234, and the management start flag are all cleared to "0". This makes it possible to resolve the information abnormality in the work area 223 for non-specific control.

On the other hand, in step S6103, the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control are not cleared to "0". This makes it possible to prevent the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control from being cleared to "0" even if an information anomaly occurs in the work area 223 for non-specific control.

In step S6103, the normal counter area 231, the counter area for opening and closing execution mode 232, the counter area for high-frequency support mode 233, and the calculation result storage area 234 may be cleared to "0", but the management start flag may not be cleared to "0". In step S6103, the normal counter area 231, the counter area for opening and closing execution mode 232, the counter area for high-frequency support mode 233, and the management start flag may be cleared to "0", but the calculation result storage area 234 may not be cleared to "0". In step S6103, the normal counter area 231, the counter area for opening and closing execution mode 232, and the counter area for high-frequency support mode 233 may be cleared to "0", but the calculation result storage area 234 and the management start flag may not be cleared to "0".

Then, the clear notification process is executed (step S6104). In the clear notification process, a command indicating that the work area 223 for non-specific control has been cleared to "0" is sent to the voice light emission control device 81. By receiving the command, the voice light emission control device 81 causes the display light emitting unit 53 to emit light in a manner corresponding to the forced clearing of the work area 223 for non-specific control, and causes the speaker unit 54 to output a voice saying "The history information has been forcibly cleared." In addition, the pattern display device 41 is made to display a text image saying "The history information has been forcibly cleared." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the above notification may be terminated when a notification termination operation is performed by the manager of the game hall. For example, the update button 68b may be pressed as the notification termination operation, or the reset button 68c may be pressed. By checking the above notification, the manager of the amusement hall can understand that the work area 223 for non-specific control has been forcibly cleared.

If a negative determination is made in step S6102 or if the processing of step S6104 is executed, a monitoring process of the stack area 224 for non-specific control is executed (step S6105). The content of this monitoring process is the same as that of step S5407 of the RAM monitoring process (FIG. 88) in the 22nd embodiment described above. If it is determined in step S6105 that an abnormality exists (step S6106: YES), the stack area 224 for non-specific control is cleared to "0" and initialized (step S6107). This makes it possible to resolve the information abnormality in the stack area 224 for non-specific control.

On the other hand, in step S6107, the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control are not cleared to "0". This makes it possible to prevent the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control from being cleared to "0" even if an information anomaly occurs in the stack area 224 for non-specific control.

Then, the clear notification process is executed (step S6108). In the clear notification process, a command indicating that the stack area 224 for non-specific control has been cleared to "0" is sent to the sound and light emission control device 81. By receiving the command, the sound and light emission control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the forced clearing of the stack area 224 for non-specific control, and causes the speaker unit 54 to output a voice saying "The stack for non-specific control has been forcibly cleared." In addition, the pattern display device 41 is made to display a text image saying "The stack for non-specific control has been forcibly cleared." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the above notification may be terminated when a notification termination operation is performed by the manager of the game hall. For example, the update button 68b may be pressed as the notification termination operation, or the reset button 68c may be pressed. By checking the above notification, the amusement hall manager can understand that the non-specific control stack area 224 has been forcibly cleared.

When the stack area 224 for non-specific control is forcibly cleared, the address of the program in step S6010 in the management execution process (FIG. 94) is set uniquely as the return address information after execution of another monitoring process. This makes it possible to return to the program that should have been returned to in the management execution process, even if the stack area 224 for non-specific control is forcibly cleared. Furthermore, when the stack area 224 for non-specific control is forcibly cleared, the stack pointer of the main CPU 63 is also set to the address of the first memory area in the storage order in the stack area 224 for non-specific control.

According to the above configuration, monitoring of whether an information abnormality has occurred in the work area 221 for specific control and the stack area 222 for specific control is performed by processing corresponding to specific control in the main CPU 63, and monitoring of whether an information abnormality has occurred in the work area 223 for non-specific control and the stack area 224 for non-specific control is performed by processing corresponding to non-specific control in the main CPU 63. This makes it possible not only to clearly distinguish between the areas 221-224 of the main RAM 65 to be used and the areas 221-224 of the main RAM 65 to be monitored, but also to clearly distinguish between the areas corresponding to specific control and the areas corresponding to non-specific control.

When the work area 223 for non-specific control is cleared to "0", the information of various registers of the main CPU 63 used in the process corresponding to the specific control and saved in the work area 223 for non-specific control is also cleared to "0". In this case, even if the process corresponding to the non-specific control is terminated and the process corresponding to the specific control is returned to, it may not be possible to return to the state before the process corresponding to the non-specific control was started. Therefore, when the work area 2223 for non-specific control is cleared to "0", the work area 221 for specific control and the stack area 222 for specific control may also be cleared to "0". In this configuration, the setting value counter in the work area 221 for specific control is also cleared to "0", so that when the process corresponding to the non-specific control is returned to the process corresponding to the specific control, the setting value update process may be executed first as the process corresponding to the specific control.

<Twenty-sixth embodiment>
In this embodiment, the processing configuration of the management process is different from that of the twentieth embodiment. The configuration that differs from the twentieth embodiment will be described below. Note that the description of the same configuration as the twentieth embodiment will basically be omitted.

Figure 96 is a flowchart showing the management process in this embodiment, which is executed by the main CPU 63. Note that the processes in steps S6201 to S6219 in the management process are executed by the main CPU 63 using a program for specific control and data for specific control.

First, to prohibit the occurrence of timer interrupt processing (FIG. 69), interrupt prohibition is set (step S6201). This makes it possible to prevent the timer interrupt processing (FIG. 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

Then, the information of the stack pointer of the main CPU 63 is overwritten in the HL register of the main CPU 63 by a load command "LD HL, SP" (step S6202). In this case, since the amount of information of the stack pointer is 16 bits and the amount of information of each of the H register and L register is 8 bits, the consecutive 8 bits of information from the upper side of the stack pointer are overwritten in the H register, and the consecutive 8 bits of information from the lower side of the stack pointer are overwritten in the L register.

Then, a load command is issued to clear to "0" a 1-byte storage area corresponding to the stack pointer information stored in the HL register of the master CPU 63 in the stack area 222 for specific control as "LD (HL), 0" (step S6203). Note that the HL register of the master CPU 63 has been overwritten with the stack pointer information of the master CPU 63 in step S6202, and the stack pointer information of the master CPU 63 has not been updated by the time the processing of step S6203 is executed. Therefore, in step S6203, a 1-byte storage area corresponding to the stack pointer information of the master CPU 63 in the stack area 222 for specific control is cleared to "0".

After that, the information of the stack pointer of the main CPU 63 is updated to the information of the address of the storage area to be written next in the stack area 222 for specific control by the load command as "LD SP, SP-1" (step S6204). When the stack area 222 for specific control is used, the information to be stored is stored from the storage area of the last address in the stack area 222 for specific control, and the storage destination storage area is changed toward the first address side in the stack area 222 for specific control each time information to be stored is added. Therefore, in step S6204, the information of the stack pointer of the main CPU 63 is updated to the information of the address corresponding to the storage area that is one address smaller in the stack area 222 for specific control. By executing the process of step S6204, the next storage area is set as the storage target of information by the next push command with respect to the storage area cleared to "0" in step S6203, and the storage area cleared to "0" in step S6203 is set as the target for reading information by the next pop command.

After that, the WA register of the master CPU 63 is cleared to "0" by a load command as "LD WA, 0" (step S6205). The BC register of the master CPU 63 is cleared to "0" by a load command as "LD BC, 0" (step S6206). The DE register of the master CPU 63 is cleared to "0" by a load command as "LD DE, 0" (step S6207). The HL register of the master CPU 63 is cleared to "0" by a load command as "LD HL, 0" (step S6208). The IX register of the master CPU 63 is cleared to "0" by a load command as "LD IX, 0" (step S6209). The IY register of the master CPU 63 is cleared to "0" by a load command as "LD IY, 0" (step S6210).

In addition to the flag register, the main CPU 63 also contains various general-purpose registers, auxiliary registers, and index registers. In this case, in steps S6205 to S6210, the WA register, BC register, DE register, HL register, IX register, and IY register, which are some of the general-purpose registers, auxiliary registers, and index registers, are cleared to "0". The WA register, BC register, DE register, HL register, IX register, and IY register are used in the management execution process (step S6212), which is a process corresponding to non-specific control. By clearing such registers to "0" prior to the execution of the management execution process (step S6212), which is a process corresponding to non-specific control, it is possible to set the state of these registers to the state immediately after the supply of operating power to the main CPU 63 is started, before the process corresponding to non-specific control is started.

In addition, the information in the WA register, BC register, DE register, HL register, IX register, and IY register before the processing corresponding to the non-specific control is started is unnecessary for the processing corresponding to the specific control after the processing corresponding to the non-specific control is completed. Therefore, even if the information in these registers is cleared to "0" without being saved, no problems will occur in the processing corresponding to the specific control that is restored after the processing corresponding to the non-specific control is completed.

Then, as "POP PSW", information is read from the previous memory area in the write order for the memory area corresponding to the information of the stack pointer of the main CPU 63 in the stack area 222 for specific control by a pop command, and the read information is overwritten in the flag register of the main CPU 63 (step S6211). The information of the stack pointer of the main CPU 63 immediately before the pop command of step S6211 is information corresponding to the memory area in the next write order for the memory area in the stack area 222 for specific control cleared to "0" in step S6203. Therefore, the memory area in the previous write order for the memory area corresponding to the information of the stack pointer of the main CPU 63 in the stack area 222 for specific control becomes the memory area cleared to "0" in step S6203. Then, by overwriting the information read from this memory area in the flag register of the main CPU 63, the flag register becomes cleared to "0". In addition, each storage area in the stack area 222 for specific control has an information volume of 8 bits (1 byte), and the flag register of the main CPU 63 also has an information volume of 8 bits (1 byte). By clearing the flag register to "0" prior to execution of the management execution process (step S6212), which is a process corresponding to non-specific control, it is possible to set the state of the flag register to the state immediately after the supply of operating power to the main CPU 63 is started, before the process corresponding to non-specific control is started.

Then, the management execution process is started by reading out a subroutine program corresponding to the management execution process set in the program for non-specific control (step S6212). In this case, information for specifying the return address of the management process after the management execution process is executed is written into the stack area 222 for specific control by a push command. Then, when the management execution process is completed, information for specifying the return address is read out by a pop command, and the process returns to the program for the management process indicated by the return address.

The processing contents of the management execution process are the same as those of the management execution process (Figure 82) in the twentieth embodiment described above. Therefore, after the check process is completed in the management execution process, the WA register, BC register, DE register, HL register, IX register, and IY register are cleared to "0". As a result, these registers are cleared to "0" prior to returning from processing corresponding to non-specific control to processing corresponding to specific control, and it is possible to set the state of these registers to the state immediately after the supply of operating power to the main CPU 63 is started before returning to processing corresponding to specific control.

When returning to the management processing program after the management execution process is executed, a process is executed to clear the flag register of the main CPU 63 to "0". In detail, first, a push command "PUSH HL" is issued to save the information in the HL register of the main CPU 63 to the stack area 222 for specific control (step S6213). After the push command is executed, the information in the stack pointer of the main CPU 63 becomes information corresponding to the next memory area in the write order relative to the memory area in which the information in the HL register was saved in the stack area 222 for specific control.

Then, the information of the stack pointer of the main CPU 63 is overwritten in the HL register of the main CPU 63 by a load command "LD HL, SP" (step S6214). In this case, since the amount of information of the stack pointer is 16 bits and the amount of information of each of the H register and L register is 8 bits, the consecutive 8 bits of information from the upper side of the stack pointer are overwritten in the H register, and the consecutive 8 bits of information from the lower side of the stack pointer are overwritten in the L register.

Then, a load command is issued to clear to "0" a 1-byte storage area corresponding to the stack pointer information stored in the HL register of the master CPU 63 in the stack area 222 for specific control as "LD (HL), 0" (step S6215). Note that the HL register of the master CPU 63 has been overwritten with the stack pointer information of the master CPU 63 in step S6214, and the stack pointer information of the master CPU 63 has not been updated by the time the processing of step S6215 is executed. Therefore, in step S6215, a 1-byte storage area corresponding to the stack pointer information of the master CPU 63 in the stack area 222 for specific control is cleared to "0".

After that, the information of the stack pointer of the main CPU 63 is updated to the information of the address of the storage area to be written next in the stack area 222 for specific control by the load command as "LD SP, SP-1" (step S6216). When the stack area 222 for specific control is used, the information to be stored is stored from the storage area of the last address in the stack area 222 for specific control, and the storage destination storage area is changed toward the first address side in the stack area 222 for specific control each time information to be stored is added. Therefore, in step S6216, the information of the stack pointer of the main CPU 63 is updated to the information of the address corresponding to the storage area on the side of the stack area 222 for specific control that is one address smaller. By executing the process of step S6216, the next storage area is set as the storage target of information by the next push command with respect to the storage area cleared to "0" in step S6215, and the storage area cleared to "0" in step S6215 is set as the target for reading information by the next pop command.

Then, as "POP PSW", information is read from the previous memory area in the write order for the memory area corresponding to the information of the stack pointer of the main CPU 63 in the stack area 222 for specific control by a pop command, and the read information is overwritten in the flag register of the main CPU 63 (step S6217). The information of the stack pointer of the main CPU 63 immediately before the pop command of step S6217 is information corresponding to the memory area in the next write order for the memory area in the stack area 222 for specific control cleared to "0" in step S6215. Therefore, the memory area in the previous write order for the memory area corresponding to the information of the stack pointer of the main CPU 63 in the stack area 222 for specific control becomes the memory area in the stack area 222 for specific control cleared to "0" in step S6215. Then, by overwriting the information read from this memory area in the flag register of the main CPU 63, the flag register becomes cleared to "0". Each memory area in the stack area 222 for specific control has an information volume of 8 bits (1 byte), and the flag register of the main CPU 63 also has an information volume of 8 bits (1 byte). By clearing the flag register to "0" after the management execution process (step S6212), which is a process corresponding to non-specific control, is executed, the state of the flag register can be set to the state immediately after the supply of operating power to the main CPU 63 is started after the process corresponding to non-specific control is completed. Furthermore, when the pop command is executed, the information of the stack pointer of the main CPU 63 is updated to information corresponding to the previous memory area in the stack area 222 for specific control in the writing order.

After that, the information of the HL register saved in the stack area 222 for specific control in step S6213 is restored to the HL register of the main CPU 63 by the pop command "POP HL" (step S6218). Note that since the HL register is cleared to "0" immediately before the management execution process (step S6212) ends, the information cleared to "0" is saved in the stack area 222 for specific control in step S6213, and the information cleared to "0" is restored to the HL register of the main CPU 63 in step S6218, so that the HL register of the main CPU 63 is cleared to "0". Also, when the pop command is executed, the information of the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two memory areas back in the writing order in the stack area 222 for specific control.

Then, the interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing (FIG. 69) is prohibited to a state in which it is permitted (step S6219). This allows a new execution of the timer interrupt processing.

The above configuration can achieve the following effects in addition to those described in the 20th embodiment.

When processing corresponding to non-specific control is started from a situation where processing corresponding to specific control is being executed, the flag register of the main CPU 63 is cleared to "0". This eliminates the need to save the information in the flag register used in the processing corresponding to specific control in the situation where processing corresponding to non-specific control is being executed in the main RAM 65. Therefore, there is no need to secure capacity for saving the information.

The flag register of the main CPU 63 is also cleared to "0" when returning to processing corresponding to specific control from a situation in which processing corresponding to non-specific control is being executed. This makes it possible to return the state of the flag register to the state it was in immediately before processing corresponding to non-specific control was started when returning to processing corresponding to specific control.

The state in which the flag register is cleared to "0" is the state when the supply of operating power to the MPU 62 is started. This makes it possible to simplify the processing configuration for setting the flag register to a predetermined state when starting processing corresponding to non-specific control and when returning to processing corresponding to specific control.

The information in the flag register of the main CPU 63 before processing corresponding to non-specific control is started is information that is not used in processing corresponding to specific control after processing corresponding to non-specific control is completed. This makes it possible to prevent the processing corresponding to specific control after processing corresponding to non-specific control is completed from being affected, even if the flag register is configured to be cleared to "0" when processing corresponding to non-specific control is started.

This configuration clears a specific memory area in the specific control stack area 222 to "0," and then overwrites the flag register with the information from the memory area that has been cleared to "0" using a pop command, thereby clearing the flag register to "0." This makes it possible to clear the flag register to "0" even in a configuration in which direct clearing of the flag register to "0" using a load command is restricted.

Instead of clearing the flag register to "0", the flag register may be initialized. That is, when the supply of operating power to the MPU 62 is started, the flag register of the main CPU 63 is once cleared to "0" and then information is set to the initial state, but the flag register may be set to this initial state in steps S6202 to S6204 and S6211. In this case, by configuring the flag register to be set to the above-mentioned initial state in steps S6213 to S6218 as well, it is possible to restore the state of the flag register to the state immediately before the processing corresponding to non-specific control was started when returning to processing corresponding to specific control.

In addition, instead of clearing the flag register of the main CPU 63 to "0" in steps S6202 to S6204 and step S6211, all of the flag registers may be set to "1". In this case, by also setting all of the flag registers to "1" in steps S6213 to S6218, when returning to processing corresponding to specific control, it is possible to return the state of the flag register to the state it was in immediately before processing corresponding to non-specific control was started.

In addition, instead of the processing of steps S6202 to S6204 and step S6211, the flag register of the main CPU 63 may be directly cleared to "0" by a load command as "LD PSW, 0".In addition, instead of the processing of steps S6213 to S6218, the flag register of the main CPU 63 may be directly cleared to "0" by a load command as "LD PSW, 0".

In addition, instead of executing the processes of steps S6213 and S6218, the HL register may be cleared to "0" by a load command such as "LD HL, 0". Even in this case, it is possible to restore the state of the HL register to the state it was in immediately before the management execution process, which is a process corresponding to non-specific control, was executed.

In addition, instead of a configuration in which the process of clearing the flag register to "0" is executed by a process corresponding to specific control, a configuration in which the process is executed by a process corresponding to non-specific control may be adopted.

<Twenty-seventh embodiment>
In this embodiment, the processing configuration of the management process is different from that of the twentieth embodiment. The configuration that differs from the twentieth embodiment will be described below. Note that the description of the same configuration as the twentieth embodiment will basically be omitted.

Figure 97 is a flowchart showing the management process in this embodiment executed by the main CPU 63. Note that the processes in steps S6301 to S6323 in the management process are executed by the main CPU 63 using a program for specific control and data for specific control.

First, to prohibit the occurrence of timer interrupt processing (FIG. 69), interrupt prohibition is set (step S6301). This makes it possible to prevent the timer interrupt processing (FIG. 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

After that, the push command "PUSH AF" is used to save the information in the A register and the flag register of the master CPU 63 to the memory area in the stack area 222 for specific control that corresponds to the current stack pointer information of the master CPU 63 and to the memory area in the next write order for that memory area (step S6302). Since the A register and flag register of the master CPU 63 each have an information volume of 8 bits (1 byte), the information in the A register and the information in the flag register are saved separately to two memory areas with consecutive addresses. Note that when the push command is executed, the information in the stack pointer of the master CPU 63 is updated to information corresponding to the memory area two places later in the write order in the stack area 222 for specific control.

After that, the A register information and flag register information saved in the stack area 222 for specific control in step S6302 are overwritten in the HL register of the master CPU 63 by the pop command "POP HL" (step S6303). In this case, the A register information saved in the stack area 222 for specific control is overwritten in the H register of the master CPU 63, and the flag register information saved in the stack area 222 for specific control is overwritten in the L register of the master CPU 63. The H register and L register of the master CPU 63 each have an information volume of 8 bits (1 byte). When the pop command is executed, the stack pointer information of the master CPU 63 is updated to information corresponding to the memory area two memory areas back in the writing order in the stack area 222 for specific control.

After that, the A register of the master CPU 63 is cleared to "0" by a load command as "LD A,0" (step S6304). Then, the information in the A register of the master CPU 63 is overwritten in the L register of the master CPU 63 by a load command as "LD L,A" (step S6305), and the information in the A register of the master CPU 63 is overwritten in the H register of the master CPU 63 by a load command as "LD H,A" (step S6306). Because the A register was cleared to "0" in step S6304, the information in the A register is overwritten in each of the L register and H register, and the L register and H register are each cleared to "0".

After that, the information in the HL register (i.e., the H register and L register) of the master CPU 63 is saved to the memory area in the stack area 222 for specific control corresponding to the current stack pointer information of the master CPU 63 and to the memory area in the next write order for that memory area by a push command "PUSH HL" (step S6307). Since the H register and L register of the master CPU 63 each have an information volume of 8 bits (1 byte), the information in the H register and the information in the L register are saved separately to two memory areas with consecutive addresses. Note that when the above push command is executed, the information in the stack pointer of the master CPU 63 is updated to the information corresponding to the memory area two places later in the write order in the stack area 222 for specific control.

Then, the BC register of the primary CPU 63 is cleared to "0" by a load command as "LD BC, 0" (step S6308). The DE register of the primary CPU 63 is cleared to "0" by a load command as "LD DE, 0" (step S6309). The IX register of the primary CPU 63 is cleared to "0" by a load command as "LD IX, 0" (step S6310). The IY register of the primary CPU 63 is cleared to "0" by a load command as "LD IY, 0" (step S6311).

In addition to the flag register, the main CPU 63 also has various general-purpose registers, auxiliary registers, and index registers. In this case, in steps S6308 to S6311, the BC register, DE register, IX register, and IY register, which are some of these general-purpose registers, auxiliary registers, and index registers, are cleared to "0". In addition, in steps S6305 and S6306, the HL register is cleared to "0". These BC register, DE register, HL register, IX register, and IY register are registers used in the management execution process (step S6313), which is a process corresponding to non-specific control. By clearing such registers to "0" prior to the execution of the management execution process (step S6313), which is a process corresponding to non-specific control, it is possible to set the state of these registers to the state immediately after the supply of operating power to the main CPU 63 is started before the process corresponding to non-specific control is started.

In addition, the information in the BC register, DE register, HL register, IX register, and IY register before the processing corresponding to the non-specific control is started is unnecessary for the processing corresponding to the specific control after the processing corresponding to the non-specific control is completed. Therefore, even if the information in these registers is cleared to "0" without being saved, no problems will occur in the processing corresponding to the specific control that is restored after the processing corresponding to the non-specific control is completed.

Then, as "POP AF", the H register information and L register information saved in the stack area 222 for specific control in step S6307 are overwritten in the A register and flag register of the main CPU 63 by a pop command (step S6312). In this case, the H register information saved in the stack area 222 for specific control is overwritten in the A register of the main CPU 63, and the L register information saved in the stack area 222 for specific control is overwritten in the flag register of the main CPU 63. Since the H register information and L register information saved in the stack area 222 for specific control are all "0" information, the A register of the main CPU 63 is cleared to "0" by the processing of step S6312, and the flag register of the main CPU 63 is cleared to "0". This makes it possible to set the state of the flag register to the state immediately after the supply of operating power to the main CPU 63 is started before the processing corresponding to non-specific control is started. When the above pop command is executed, the information in the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places back in the writing order in the specific control stack area 222.

Then, the subroutine program corresponding to the management execution process set in the program for non-specific control is read out, thereby starting the management execution process (step S6313). In this case, information for specifying the return address of the management process after the management execution process is executed is written into the stack area 222 for specific control by a push command. Then, when the management execution process is completed, information for specifying the return address is read out by a pop command, and the program for the management process indicated by the return address is returned to.

After the check process is completed in the management execution process, the BC register, DE register, HL register, IX register, and IY register are cleared to "0." This clears these registers to "0" prior to returning from processing corresponding to non-specific control to processing corresponding to specific control, making it possible to set the state of these registers to the state they are in immediately after the supply of operating power to the main CPU 63 begins before returning to processing corresponding to specific control.

When returning to the management processing program after the management execution process is executed, a process is executed to clear the flag register of the main CPU 63 to "0". In detail, first, a push command "PUSH HL" is issued to save the information in the HL register of the main CPU 63 to the stack area 222 for specific control (step S6314). After the push command is executed, the information in the stack pointer of the main CPU 63 becomes information corresponding to the next memory area in the write order relative to the memory area in which the information in the HL register was saved in the stack area 222 for specific control.

After that, the push command "PUSH AF" is used to save the information in the A register and the flag register of the master CPU 63 to the memory area in the stack area 222 for specific control that corresponds to the current stack pointer information of the master CPU 63 and to the memory area in the next write order for that memory area (step S6315). Since the A register and the flag register of the master CPU 63 each have an information volume of 8 bits (1 byte), the information in the A register and the information in the flag register are saved separately to two memory areas with consecutive addresses. Note that when the push command is executed, the information in the stack pointer of the master CPU 63 is updated to information corresponding to the memory area two places later in the write order in the stack area 222 for specific control.

After that, the A register information and flag register information saved in the stack area 222 for specific control in step S6315 are overwritten in the HL register of the master CPU 63 by the pop command "POP HL" (step S6316). In this case, the A register information saved in the stack area 222 for specific control is overwritten in the H register of the master CPU 63, and the flag register information saved in the stack area 222 for specific control is overwritten in the L register of the master CPU 63. The H register and L register of the master CPU 63 each have an information volume of 8 bits (1 byte). When the pop command is executed, the stack pointer information of the master CPU 63 is updated to information corresponding to the memory area two memory areas back in the writing order in the stack area 222 for specific control.

Then, the A register of the master CPU 63 is cleared to "0" by a load command as "LD A,0" (step S6317). Then, the information in the A register of the master CPU 63 is overwritten in the L register of the master CPU 63 by a load command as "LD L,A" (step S6318), and the information in the A register of the master CPU 63 is overwritten in the H register of the master CPU 63 by a load command as "LD H,A" (step S6319). Because the A register was cleared to "0" in step S6317, the information in the A register is overwritten in each of the L register and H register, and the L register and H register are each cleared to "0".

After that, the push command "PUSH HL" is used to save the information in the HL register (i.e., the H register and L register) of the master CPU 63 to the memory area in the stack area 222 for specific control that corresponds to the current stack pointer information of the master CPU 63 and to the memory area in the next write order for that memory area (step S6320). Since the H register and L register of the master CPU 63 each have an information volume of 8 bits (1 byte), the information in the H register and the information in the L register are saved separately to two memory areas with consecutive addresses. Note that when the above push command is executed, the information in the stack pointer of the master CPU 63 is updated to information corresponding to the memory area two places later in the write order in the stack area 222 for specific control.

Then, as "POP AF", the H register information and L register information saved in the stack area 222 for specific control in step S6320 are overwritten in the A register and flag register of the master CPU 63 by a pop command (step S6321). In this case, the H register information saved in the stack area 222 for specific control is overwritten in the A register of the master CPU 63, and the L register information saved in the stack area 222 for specific control is overwritten in the flag register of the master CPU 63. Since the H register information and L register information saved in the stack area 222 for specific control are all "0" information, the A register of the master CPU 63 is cleared to "0" by the processing of step S6321, and the flag register of the master CPU 63 is cleared to "0". By clearing the flag register to "0" after the management execution process (step S6313), which is a process corresponding to non-specific control, is executed, the state of the flag register can be set to the state immediately after the supply of operating power to the main CPU 63 is started after the process corresponding to non-specific control is completed. When the above pop command is executed, the information of the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places back in the writing order in the stack area 222 for specific control.

After that, the information of the HL register saved in the stack area 222 for specific control in step S6314 is restored to the HL register of the main CPU 63 by the pop command "POP HL" (step S6322). Note that since the HL register is cleared to "0" immediately before the management execution process (step S6313) ends, the information cleared to "0" is saved in the stack area 222 for specific control in step S6314, and the information cleared to "0" is restored to the HL register of the main CPU 63 in step S6322, so that the HL register of the main CPU 63 is cleared to "0". Also, when the pop command is executed, the information of the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places back in the writing order in the stack area 222 for specific control.

Then, the interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing (FIG. 69) is prohibited to a state in which it is permitted (step S6323). This allows a new execution of the timer interrupt processing.

According to the above configuration, it is possible to clear the flag register of the main CPU 63 to "0" without executing the process of clearing a specific memory area in the stack area 222 for specific control to "0" by a load command. This makes it possible to clear the flag register of the main CPU 63 to "0" even in a configuration in which clearing a specific memory area in the stack area 222 for specific control to "0" by a load command is restricted.

Instead of clearing the flag register to "0", the flag register may be initialized. In other words, when the supply of operating power to the MPU 62 is started, the flag register of the main CPU 63 is once cleared to "0" and then information is set to the initial state, but the flag register may be set to this initial state in steps S6302 to S6307 and step S6312. In this case, by configuring the flag register to be set to the above-mentioned initial state in steps S6314 to S6322 as well, when returning to processing corresponding to specific control, it is possible to return the state of the flag register to the state immediately before processing corresponding to non-specific control was started.

In addition, instead of clearing the flag register of the main CPU 63 to "0" in steps S6302 to S6307 and step S6312, all of the flag registers may be set to "1". In this case, by also setting all of the flag registers to "1" in steps S6314 to S6322, when returning to processing corresponding to specific control, it is possible to restore the state of the flag register to the state it was in immediately before processing corresponding to non-specific control was started.

The processing of steps S6302 and S6303 may also be omitted. In this case, the processing configuration can be simplified.

The processing of steps S6315 and S6316 may also be omitted. In this case, the processing configuration can be simplified.

Instead of executing the processes of steps S6302 to S6306, a configuration may be used in which the HL register is cleared to "0" by a load command as "LD HL, 0", the HL register that has been cleared to "0" is then saved to the stack area 222 for specific control by a push command, and the saved information is then restored to the AF register by a pop command, thereby clearing the flag register of the main CPU 63 to "0".

In addition, instead of a configuration in which the process of clearing the flag register to "0" is executed by a process corresponding to specific control, a configuration in which the process is executed by a process corresponding to non-specific control may be adopted.

<Twenty-eighth embodiment>
In this embodiment, the processing configuration of the management process is different from that of the fifteenth embodiment. The following describes the configuration that is different from the fifteenth embodiment. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 98 is a flowchart showing the management process in this embodiment executed by the main CPU 63. Note that the processes in steps S6401 to S6416 in the management process are executed by the main CPU 63 using a program for specific control and data for specific control.

First, to prohibit the occurrence of timer interrupt processing (FIG. 69), interrupt prohibition is set (step S6401). This makes it possible to prevent the timer interrupt processing (FIG. 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

After that, the information in the WA register (i.e., the W register and A register) of the master CPU 63 is saved by a push command as "PUSH WA" to the memory area in the stack area 222 for specific control corresponding to the current stack pointer information of the master CPU 63 and to the memory area in the next write order for that memory area (step S6402). Since the W register and A register of the master CPU 63 each have an information volume of 8 bits (1 byte), the information in the W register and A register is saved separately to two memory areas with consecutive addresses. Note that when the above push command is executed, the information in the stack pointer of the master CPU 63 is updated to information corresponding to the memory area two places later in the write order in the stack area 222 for specific control.

After that, the information in the flag register of the master CPU 63 is overwritten in the A register of the master CPU 63 by a load command as "LD A, PSW" (step S6403). In this case, the amount of information in both the flag register and the A register is 8 bits (1 byte). Then, the information in the A register of the master CPU 63 is saved in the FG buffer set in the work area 221 for specific control by a load command as "LD (_FGBUF), A" (step S6404). Since the A register has been overwritten with the information in the flag register in step S6403, the execution of step S6404 results in the information in the flag register being saved in the work area 221 for specific control.

After that, the information of the WA register saved in the stack area 222 for specific control in step S6402 is restored to the WA register of the main CPU 63 by a pop command as "POP WA" (step S6405). As a result, even if the A register is used to save the information of the flag register to the work area 221 for specific control, it is possible to restore the state of the A register to the state before the save. Note that when the pop command is executed, the information of the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places back in the writing order in the stack area 222 for specific control.

Then, the management execution process is started by reading out a subroutine program corresponding to the management execution process set in the program for non-specific control (step S6406). In this case, information for specifying the return address of the management process after the management execution process is executed is written into the stack area 222 for specific control by a push command. Then, when the management execution process is completed, information for specifying the return address is read out by a pop command, and the process returns to the program for the management process indicated by the return address.

The processing contents of the management execution process are the same as those of the management execution process (FIG. 71) in the fifteenth embodiment. Therefore, before the check process is started in the management execution process, the information of the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 is saved to the non-specific control work area 223, and after the check process is completed in the management execution process, the information saved to the non-specific control work area 223 is restored to the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63. This makes it possible to make the states of the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 the same before and after the check process.

However, this is not limited to the above, and the processing contents of the management execution process may be the same as the management execution process in the 17th embodiment (Figure 78), the same as the management execution process in the 18th embodiment (Figure 79), or the same as the management execution process in the 19th embodiment (Figure 80).

When returning to the management processing program after the management execution process is executed, a process is executed to restore the information in the flag register of the main CPU 63 to the state before the management execution process was executed. In detail, first, a push command "PUSH HL" is used to save the information in the HL register of the main CPU 63 to the stack area 222 for specific control (step S6407). After the push command is executed, the information in the stack pointer of the main CPU 63 becomes information corresponding to the memory area in the next write order in the stack area 222 for specific control relative to the memory area where the information in the HL register was saved.

Then, the information in the WA register of the master CPU 63 is saved to the specific control stack area 222 by a push command as "PUSH WA" (step S6408). After the execution of the push command, the information in the stack pointer of the master CPU 63 becomes information corresponding to the next memory area in the write order relative to the memory area in which the information in the WA register was saved in the specific control stack area 222.

Then, the information of the stack pointer of the main CPU 63 is overwritten in the HL register of the main CPU 63 by a load command as "LD HL, SP" (step S6409). In this case, since the amount of information of the stack pointer is 16 bits and the amount of information of each of the H register and L register is 8 bits, the consecutive 8 bits of information from the upper side of the stack pointer are overwritten in the H register, and the consecutive 8 bits of information from the lower side of the stack pointer are overwritten in the L register.

After that, the flag register information saved in the FG buffer in the work area 221 for specific control in step S6406 is overwritten in the A register of the master CPU 63 by a load command as "LD A, (_FGBUF)" (step S6410). Then, the A register information of the master CPU 63 is stored in a 1-byte memory area corresponding to the stack pointer information stored in the HL register of the master CPU 63 in the stack area 222 for specific control by a load command as "LD (HL), A" (step S6411). As a result, the flag register information saved in the FG buffer in the work area 221 for specific control in step S6404 is saved in the stack area 222 for specific control.

After that, the information of the stack pointer of the main CPU 63 is updated to the information of the address of the storage area to be written next in the stack area 222 for specific control by the load command as "LD SP, SP-1" (step S6412). When the stack area 222 for specific control is used, the information to be stored is stored from the storage area of the last address in the stack area 222 for specific control, and the storage destination storage area is changed toward the first address side in the stack area 222 for specific control each time information to be stored is added. Therefore, in step S6412, the information of the stack pointer of the main CPU 63 is updated to the information of the address corresponding to the storage area with one address smaller in the stack area 222 for specific control. By executing the process of step S6412, the next storage area is set as the storage target of information by the next push command with respect to the storage area where the information of the A register was saved in step S6411, and the storage area where the information of the A register was saved in step S6411 is set as the target for reading information by the next pop command.

Then, as "POP PSW", information is read from the previous memory area in the write order for the memory area corresponding to the information of the stack pointer of the main CPU 63 in the stack area 222 for specific control by the pop command, and the read information is overwritten in the flag register of the main CPU 63 (step S6413). The information of the stack pointer of the main CPU 63 immediately before the pop command of step S6413 is information corresponding to the memory area in the next write order for the memory area in which the information of the A register was saved in step S6411. Therefore, the memory area in the previous write order for the memory area corresponding to the information of the stack pointer of the main CPU 63 in the stack area 222 for specific control is the memory area in which the information of the A register was saved in step S6411. Then, by overwriting the information read from this memory area in the flag register of the main CPU 63, the information of the flag register saved in the FG buffer in the work area 221 for specific control in step S6404 is restored to the flag register of the main CPU 63. When the pop command is executed, the information in the stack pointer of the main CPU 63 is updated to information corresponding to the previous memory area in the specific control stack area 222.

After that, the information of the WA register saved in the stack area 222 for specific control in step S6408 is restored to the WA register of the main CPU 63 by a pop command as "POP WA" (step S6414). When the pop command is executed, the information of the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places back in the write order in the stack area 222 for specific control. Also, the information of the HL register saved in the stack area 222 for specific control in step S6407 is restored to the HL register of the main CPU 63 by a pop command as "POP HL" (step S6415). When the pop command is executed, the information of the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places back in the write order in the stack area 222 for specific control.

Then, the interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing (FIG. 69) is prohibited to a state in which it is permitted (step S6416). This allows a new execution of the timer interrupt processing.

According to the above configuration, when processing corresponding to non-specific control is started from a state in which processing corresponding to specific control is being executed, it is possible to save the information in the flag register of the main CPU 63 to the work area 221 for specific control instead of the stack area 222 for specific control. Then, when processing corresponding to specific control is returned to from a state in which processing corresponding to non-specific control is being executed, the information in the flag register saved in the work area 221 for specific control is restored to the flag register of the main CPU 63. As a result, since it is sufficient to restore information to the flag register of the main CPU 63 from the storage area of the work area 221 for specific control specified in the program without referring to the information in the stack pointer of the main CPU 63, it is possible to restore information to the flag register of the main CPU 63 even if the information in the stack pointer of the main CPU 63 is rewritten due to noise or the like.

In addition, instead of a configuration in which the process of saving the flag register information to the main RAM 65 is executed by a process corresponding to a specific control, it may be configured to be executed by a process corresponding to a non-specific control.In addition, instead of a configuration in which the process of restoring the flag register information saved to the main RAM 65 to the flag register of the main CPU 63 is executed by a process corresponding to a specific control, it may be configured to be executed by a process corresponding to a non-specific control.

<Twenty-ninth embodiment>
In this embodiment, the processing configuration of the management process is different from that of the fifteenth embodiment. The configuration that differs from the fifteenth embodiment will be described below. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 99 is a flowchart showing the management process in this embodiment executed by the main CPU 63. Note that the processes in steps S6501 to S6519 in the management process are executed by the main CPU 63 using a program for specific control and data for specific control.

First, to prohibit the occurrence of timer interrupt processing (FIG. 69), interrupt prohibition is set (step S6501). This makes it possible to prevent the timer interrupt processing (FIG. 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

After that, the push command "PUSH HL" is used to save the information in the HL register (i.e., the H register and L register) of the master CPU 63 to the memory area in the stack area 222 for specific control that corresponds to the current stack pointer information of the master CPU 63 and to the memory area in the next write order for that memory area (step S6502). Since the H register and L register of the master CPU 63 each have an information volume of 8 bits (1 byte), the information in the H register and L register is saved separately to two memory areas with consecutive addresses. Note that when the push command is executed, the information in the stack pointer of the master CPU 63 is updated to information corresponding to the memory area two places later in the write order in the stack area 222 for specific control.

After that, the push command "PUSH AF" is used to save the information in the A register and the flag register of the master CPU 63 to the memory area in the stack area 222 for specific control that corresponds to the current stack pointer information of the master CPU 63 and to the memory area in the next write order for that memory area (step S6503). Since the A register and flag register of the master CPU 63 each have an information volume of 8 bits (1 byte), the information in the A register and the information in the flag register are saved separately to two memory areas with consecutive addresses. Note that when the push command is executed, the information in the stack pointer of the master CPU 63 is updated to information corresponding to the memory area two places later in the write order in the stack area 222 for specific control.

After that, the A register information and flag register information saved in the stack area 222 for specific control in step S6503 are overwritten in the HL register of the master CPU 63 by a pop command as "POP HL" (step S6504). In this case, the A register information saved in the stack area 222 for specific control is overwritten in the H register of the master CPU 63, and the flag register information saved in the stack area 222 for specific control is overwritten in the L register of the master CPU 63. Note that when the pop command is executed, the stack pointer information of the master CPU 63 is updated to information corresponding to the memory area two memory areas back in the writing order in the stack area 222 for specific control.

After that, the information in the L register of the master CPU 63 is overwritten in the A register of the master CPU 63 by a load command as "LD A, L" (step S6505). Since the information in the flag register of the master CPU 63 has been overwritten in the L register in step S6504, the information in the L register is overwritten in the A register, and the information in the flag register is overwritten in the A register. Then, the information in the A register of the master CPU 63 is saved in the FG buffer set in the work area 221 for specific control by a load command as "LD (_FGBUF), A" (step S6506). Since the information in the flag register has been overwritten in the A register in step S6505, the information in the flag register is saved in the work area 221 for specific control by executing step S6506.

After that, the push command "PUSH HL" is used to save the information in the HL register (i.e., the H register and L register) of the master CPU 63 to the memory area in the stack area 222 for specific control that corresponds to the current stack pointer information of the master CPU 63 and to the memory area in the next write order for that memory area (step S6507). In this case, since the A register information and flag register information have been overwritten in the HL register in step S6504, in step S6507 the A register information and flag register information are saved in the stack area 222 for specific control. When the push command is executed, the stack pointer information of the master CPU 63 is updated to information corresponding to the memory area two places later in the write order in the stack area 222 for specific control.

Then, as "POP AF", the H register information and L register information saved in the stack area 222 for specific control in step S6507 are overwritten in the A register and flag register of the master CPU 63 by a pop command (step S6508). In this case, the H register information saved in the stack area 222 for specific control is overwritten in the A register of the master CPU 63, and the L register information saved in the stack area 222 for specific control is overwritten in the flag register of the master CPU 63. The H register information saved in the stack area 222 for specific control is the A register information at the time of step S6503, and the L register information saved in the stack area 222 for specific control is the flag register information at the time of step S6503. Therefore, by executing the process of step S6508, the state of the A register and flag register of the master CPU 63 is restored to the state at the time of step S6503. When the above pop command is executed, the information in the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places back in the writing order in the specific control stack area 222.

After that, the information of the HL register that was saved in the stack area 222 for specific control in step S6502 is restored to the HL register of the main CPU 63 by a pop command as "POP HL" (step S6509). This causes the state of the HL register of the main CPU 63 to return to the state at the time of step S6502. When the pop command is executed, the information of the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places back in the writing order in the stack area 222 for specific control.

Then, the management execution process is started by reading out a subroutine program corresponding to the management execution process set in the program for non-specific control (step S6510). In this case, information for specifying the return address of the management process after the management execution process is executed is written into the stack area 222 for specific control by a push command. Then, when the management execution process is completed, information for specifying the return address is read out by a pop command, and the process returns to the program for the management process indicated by the return address.

In addition, in the management execution process, before the check process is started, the information in the BC register, DE register, HL register, IX register, and IY register of the main CPU 63 is saved to the work area 223 for non-specific control, and after the check process is completed in the management execution process, the information saved in the work area 223 for non-specific control is restored to the BC register, DE register, HL register, IX register, and IY register of the main CPU 63. This makes it possible to keep the states of the BC register, DE register, HL register, IX register, and IY register of the main CPU 63 the same before and after the check process.

However, this is not limited to the above, and the processing contents of the management execution process may be the same as the management execution process in the 17th embodiment (Figure 78), the same as the management execution process in the 18th embodiment (Figure 79), or the same as the management execution process in the 19th embodiment (Figure 80).

When returning to the management processing program after the management execution process is executed, a process is executed to restore the information in the flag register of the main CPU 63 to the state before the management execution process was executed. In detail, first, a push command "PUSH HL" is used to save the information in the HL register of the main CPU 63 to the stack area 222 for specific control (step S6511). After the push command is executed, the information in the stack pointer of the main CPU 63 becomes information corresponding to the memory area in the next write order in the stack area 222 for specific control relative to the memory area where the information in the HL register was saved.

After that, the push command "PUSH AF" is used to save the information in the A register and the flag register of the master CPU 63 to the memory area in the stack area 222 for specific control that corresponds to the current stack pointer information of the master CPU 63 and to the memory area in the next write order for that memory area (step S6512). Since the A register and flag register of the master CPU 63 each have an information volume of 8 bits (1 byte), the information in the A register and the information in the flag register are saved separately to two memory areas with consecutive addresses. Note that when the push command is executed, the information in the stack pointer of the master CPU 63 is updated to information corresponding to the memory area two places later in the write order in the stack area 222 for specific control.

After that, the A register information and flag register information saved in the stack area 222 for specific control in step S6512 are overwritten in the HL register of the master CPU 63 by a pop command as "POP HL" (step S6513). In this case, the A register information saved in the stack area 222 for specific control is overwritten in the H register of the master CPU 63, and the flag register information saved in the stack area 222 for specific control is overwritten in the L register of the master CPU 63. Note that when the pop command is executed, the stack pointer information of the master CPU 63 is updated to information corresponding to the memory area two memory areas back in the writing order in the stack area 222 for specific control.

After that, the information in the flag register at the time of step S6503, which was saved in step S6506 to the FG buffer in the work area 221 for specific control, is overwritten in the A register of the master CPU 63 by a load command as "LD A, (_FGBUF)" (step S6514). Then, the information in the A register of the master CPU 63 is overwritten in the L register of the master CPU 63 by a load command as "LD L, A" (step S6515). Since the information in the flag register of the master CPU 63 at the time of step S6503 has been restored to the A register in step S6514, overwriting the information in the A register in the L register results in the L register being overwritten with the information in the flag register at the time of step S6503.

After that, the push command "PUSH HL" is used to save the information in the HL register (i.e., the H register and L register) of the master CPU 63 to the memory area in the specific control stack area 222 corresponding to the information of the current stack pointer of the master CPU 63 and to the memory area in the next write order for that memory area (step S6516). In this case, since the information in the A register at the time of step S6512 has been overwritten in the H register in step S6513, the information in the A register has been saved in the specific control stack area 222 in step S6516. Also, since the information in the flag register at the time of step S6503 has been overwritten in the L register in step S6515, the information in the flag register has been saved in the specific control stack area 222 in step S6516.

After that, the H register information and L register information saved in the stack area 222 for specific control in step S6516 are overwritten in the A register and flag register of the master CPU 63 by a pop command as "POP AF" (step S6517). In this case, the H register information saved in the stack area 222 for specific control is overwritten in the A register of the master CPU 63, and the L register information saved in the stack area 222 for specific control is overwritten in the flag register of the master CPU 63. The H register information saved in the stack area 222 for specific control is the A register information at the time of step S6512, and the L register information saved in the stack area 222 for specific control is the flag register information at the time of step S6503. Therefore, by executing the process of step S6517, the state of the A register of the master CPU 63 is restored to the state of step S6512, and the state of the flag register is restored to the state at the time of step S6503.

Incidentally, the A register of the main CPU 63 is not used in the management execution process. Therefore, the state of the A register at the time of step S6512 is the state of the A register at the time of step S6508, and the state of the A register at the time of step S6508 is the state of the A register at the time of step S6503. Therefore, by executing the process of step S6517, the states of the A register and flag register of the main CPU 63 are restored to the states at the time of step S6503. Note that when the above pop command is executed, the information of the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two memory areas back in the writing order in the stack area 222 for specific control.

After that, the HL register information saved in the specific control stack area 222 in step S6511 is restored to the HL register of the main CPU 63 by a pop command as "POP HL" (step S6518). This causes the state of the HL register of the main CPU 63 to return to the state at the time of step S6511. When the pop command is executed, the stack pointer information of the main CPU 63 is updated to information corresponding to the memory area two memory areas back in the writing order in the specific control stack area 222.

Then, the interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing (FIG. 69) is prohibited to a state in which it is permitted (step S6519). This allows a new execution of the timer interrupt processing.

With the above configuration, it is possible to save the information in the flag register of the main CPU 63 to the work area 221 for specific control by a load command without executing a process that directly overwrites the information in the flag register of the main CPU 63 to another register of the main CPU 63.

In addition, instead of executing the processes of steps S6505 to S6508, the process of step S6504 may be executed, and the information in the L register, which has been overwritten with the information in the flag register by a load command as "LD (_FGBUF), L", may be saved to the FG buffer, thereby saving the information in the flag register to the work area 221 for specific control.

In addition, instead of executing the processes of steps S6514 and S6515, the process of step S6513 may be executed, and then the information of the flag register saved in the work area 221 for specific control may be overwritten in the L register by a load command as "LD L, (_FGBUF)".

In addition, instead of a configuration in which the process of saving the flag register information to the main RAM 65 is executed by a process corresponding to a specific control, it may be configured to be executed by a process corresponding to a non-specific control.In addition, instead of a configuration in which the process of restoring the flag register information saved to the main RAM 65 to the flag register of the main CPU 63 is executed by a process corresponding to a specific control, it may be configured to be executed by a process corresponding to a non-specific control.

Thirtieth embodiment
In this embodiment, the processing configuration executed by the main CPU 63 is different from that of the fifteenth embodiment. The configuration that differs from the fifteenth embodiment will be described below. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 100 is a flowchart showing the main processing in this embodiment executed by the main CPU 63. Note that the processing of steps S6601 to S6621 in the main processing is executed using a program for specific control and data for specific control in the main CPU 63.

First, the power-on wait process is executed (step S6601). In this power-on wait process, for example, the main process is started and a predetermined wait time (specifically, one second) elapses before proceeding to the next process. During the execution period of this power-on wait process, the operation start and initial settings of the pattern display device 41 are completed. After that, access to the main RAM 65 is permitted (step S6602).

Then, it is determined whether the power outage flag provided in the work area 221 for specific control in the main RAM 65 is set to "1" (step S6603). If the power outage flag is set to "1" (step S6603: YES), a checksum is calculated for the work area 221 for specific control and the stack area 222 for specific control (step S6604).

The checksum can be calculated by any method, but one example is adding up all the numerical values in the memory area that is the target of the checksum calculation. This checksum calculation method is the same as the checksum calculation method used in the power outage processing described below. The checksum calculated in the power outage processing described below is stored in the work area 221 for specific control, but the memory area of the work area 221 for specific control in which this checksum is stored is excluded from the memory areas that are the target of the calculation when the checksum is calculated.

In other words, when the checksum is calculated, some of the storage areas in the work area 221 for specific control and the stack area 222 for specific control are used as the objects of calculation. The storage areas used as the objects of calculation are basically not rewritten with information when the supply of backup power to the work area 221 for specific control and the stack area 222 for specific control is continued from the time the checksum is calculated in the power failure processing when the supply of operating power to the MPU 62 is stopped until the supply of operating power to the MPU 62 is resumed and the processing of step S6604 is executed. Therefore, if the information in the work area 221 for specific control and the stack area 222 for specific control has not been changed between the time the supply of operating power to the MPU 62 is stopped and the time the supply of operating power to the MPU 62 is resumed, the checksum for the work area 221 for specific control and the stack area 222 for specific control is the same as that immediately before the supply of operating power to the MPU 62 is stopped. The storage area that is the subject of calculation when calculating this checksum includes an area (specifically, a setting value counter) in which setting value information indicating the setting state of the pachinko machine 10 is set in the work area 221 for specific control.

Then, the checksums for the work area 221 for specific control and the stack area 222 for specific control that were calculated and stored in the work area 221 for specific control during the power outage processing executed immediately before the supply of operating power to the MPU 62 was stopped are read from the work area 221 for specific control, and the read checksums are compared with the checksum calculated in step S6604 (step S6605). Then, it is determined whether these checksums match (step S6606).

Here, the power outage information storage process executed by the main CPU 63 will be described with reference to the flowchart in FIG. 101. Note that the power outage information storage process is executed in step S6801 in the timer interrupt process (FIG. 103) described later.

In the power outage information storage process, first, the repetition counter provided in the work area 221 for specific control is set to "10", which is the repetition count information for the power outage signal (step S6701), and the power outage detection counter provided in the work area 221 for specific control is cleared to "0" (step S6702).

After that, a process is executed to read the information of the power failure signal received at the input port of the MPU 62 (step S6703). In this case, if a power failure signal corresponding to no power failure (LOW level power failure signal) is received, information "0" is stored in the input port as non-power failure information, and if a power failure signal corresponding to a power failure (HI level power failure signal) is received, information "1" is stored in the input port as power failure occurrence information. In step S6703, a process is executed to read the information of the power failure signal into the register of the main CPU 63.

If the power outage signal information read in step S6703 corresponds to the occurrence of a power outage (power interruption) (step S6704: YES), the numerical information of the power outage detection counter is incremented by 1 (step S6705). If a negative determination is made in step S6704 or if the processing of step S6705 is executed, the numerical information of the repetition counter is decremented by 1 (step S6706). Then, it is determined whether the numerical information of the repetition counter after the decrement is "0" (step S6707). If a negative determination is made in step S6707, the process returns to step S6703 and the processing of steps S6703 to S6706 is repeated. On the other hand, if a positive determination is made in step S6707, the process proceeds to step S6708.

In step S6708, it is determined whether the current numerical information of the power outage detection counter is equal to or greater than the trigger reference number corresponding to the occurrence of a power outage. If it is less than the trigger reference number, the power outage information storage process is terminated. On the other hand, if it is equal to or greater than the trigger reference number, the power outage processing of steps S6709 to S6712 is executed.

Specifically, first, the power failure flag provided in the work area 221 for specific control is set to "1" (step S6709). As a result, if the power failure process is executed normally and the information is stored and maintained normally in the main RAM 65, the power failure flag in the work area 221 for specific control will be set to "1" when the supply of operating power to the main CPU 63 is resumed again.

Then, a checksum is calculated for the work area 221 for specific control and the stack area 222 for specific control (step S6710). In this case, the storage areas in the work area 221 for specific control and the stack area 222 for specific control that are the objects of calculation when calculating the checksum are the same as the storage areas in the work area 221 for specific control and the stack area 222 for specific control that are the objects of calculation of the checksum in step S6604 of the main processing (FIG. 100). In addition, the storage areas that are the objects of calculation when calculating this checksum include an area in the work area 221 for specific control where information on a setting value indicating the setting state of the pachinko machine 10 is set (specifically, a setting value counter). Then, the calculated checksum is stored in a storage area in the work area 221 for specific control for storing the checksum, which is excluded from the objects of calculation of the checksum.

Then, all output port information in the register of the main CPU 63 is set to "0" (step S6711), and access to the main RAM 65 is prohibited (step S6712). Then, an infinite loop continues until the power is completely cut off and processing can no longer be executed.

In addition, by executing the power outage information storage process as the first process of the timer interrupt process, it is no longer necessary to execute the timer interrupt process from the middle after power is restored. This eliminates the need to store the address of the process that was being executed when the power outage occurred as stack information in the main RAM 65, making it possible to reduce the processing load when a power outage occurs.

Returning to the explanation of the main process (FIG. 100), if a negative judgment is made in step S6603 or step S6606, a clear process for non-setting update is executed (step S6607). In the clear process for non-setting update, the work area 221 for specific control is cleared to "0" and the initial setting is executed, except for the area (specifically, the setting value counter) in which the setting value information indicating the setting state of the pachinko machine 10 is set in the work area 221 for specific control. As a result, the area indicating whether the winning/losing lottery mode is the high probability mode or not is cleared to "0", so that the winning/losing lottery mode becomes the low probability mode regardless of the winning/losing lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. In addition, the game round is not being executed, and the open/close execution mode is not being executed, and further, the normal map display unit 38a is not displayed in a variable manner and the normal power role 34a is in a closed state. In addition, the reserved storage area 65a and the regular power reserved area 65c provided in the work area 221 for specific control are also cleared to "0", so that the reserved information for the special map display section 37a is erased and the reserved information for the regular map display section 38a is erased. In addition, in the clearing process for non-setting updates, the stack area 222 for specific control is cleared to "0" and initial settings are performed. In addition, in the clearing process for non-setting updates, various registers of the main CPU 63 are also cleared to "0" and then initial settings are performed.

On the other hand, the clearing process during non-setting updates does not clear the work area 223 for non-specific control and the stack area 224 for non-specific control to "0". This makes it possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" even if the power outage processing was not executed normally and the power outage flag was not set to "1". Also, even if an abnormality occurs with the checksum for the work area 221 for specific control and the stack area 222 for specific control, it makes it possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0".

If a negative judgment is made in step S6603 or step S6606 and the clear process for non-update is executed in step S6607, the setting value of the pachinko machine 10 is judged to be normal or not by checking the value of the setting value counter in the work area 221 for specific control (step S6608). Specifically, if the setting value set in the setting value counter is any of "setting 1" to "setting 6", it is judged to be normal, and if it is "0" or 7 or more, it is judged to be abnormal. If the setting value is abnormal (step S6608: NO), a process (steps S6619 to S6621) for setting a new setting value, which will be described later, is executed. This makes it possible to monitor whether the setting value is normal or not even if a negative judgment is made in step S6603 or step S6606 and the clear process for non-update (step S6607) is executed, and to reset the setting value if it is abnormal.

If the setting value is normal (step S6608: YES), the power-on setting process is executed (step S6609). In the power-on setting process, a predetermined area of the work area 221 for specific control, such as the initialization of the power outage flag, is set to an initial value, and a command corresponding to the current game state is sent to the sound and light emission control device 81.

The main CPU 63 is configured to periodically execute timer interrupt processing, but timer interrupt processing is prohibited from occurring when main processing is started. This state in which timer interrupt processing is prohibited is released when step S6609 is completed and before step S6610 is executed, and timer interrupt processing is permitted to be executed. As a result, when the supply of operating power to the main CPU 63 is started, the power-on setting process of step S6609 is completed, and timer interrupt processing is not executed until the stage before step S6610 is started. Therefore, processing to progress the game in the main CPU 63 is not started until this situation is reached.

Then, the process proceeds to the remaining process of steps S6610 to S6613. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but there is a remaining time between one timer interrupt processing and the next timer interrupt processing. This remaining time varies depending on the processing completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining process of steps S6610 to S6613. In this respect, the remaining process of steps S6610 to S6613 can be said to be non-periodic processing that is executed non-periodically. In steps S6610 to S6613, the same processing is executed as steps S113 to S116 of the main processing (FIG. 9) in the first embodiment described above.

As described above, in this embodiment, when the supply of operating power to the main CPU 63 is started, if the power failure flag in the work area 221 for specific control is not set to "1" or the checksum does not match, the clear process for non-setting update is executed, and if the setting value is normal (step S6608: YES), the process proceeds to the process for progressing the game. As a result, even if the power failure process was not executed normally and the power failure flag was not set to "1", it is not necessary to turn the power on and off again after the supply of operating power to the main CPU 63 is started. Furthermore, even if an abnormality occurs in the checksum for the work area 221 for specific control and the stack area 222 for specific control, it is not necessary to turn the power on and off again after the supply of operating power to the main CPU 63 is started.

If the determination is positive in both step S6603 and step S6606, the setting value of the pachinko machine 10 is checked to determine whether it is normal or not by checking the value of the setting value counter in the work area 221 for specific control (step S6614). Specifically, if the setting value set in the setting value counter is any of "Setting 1" to "Setting 6," it is determined to be normal, and if it is "0" or 7 or greater, it is determined to be abnormal. If the setting value is abnormal (step S6614: NO), processing is executed to set a new setting value (steps S6619 to S6621), which will be described later.

If the setting value is normal (step S6614: YES), it is determined whether the reset button 68c has been pressed (step S6615), whether the setting key insertion section 68a has been turned ON using the setting key (step S6616), whether the front door frame 14 is open relative to the inner frame 13 (step S6617), and whether the gaming machine main body 12 is open relative to the outer frame 11 (step S6618).

In this embodiment, a front door open sensor 95 for detecting whether the front door frame 14 is open relative to the inner frame 13 is electrically connected to the main CPU 63, and the detection result of the front door open sensor 95 is input to the main CPU 63. In this case, when the front door frame 14 is closed relative to the inner frame 13, the front door open sensor 95 transmits a closed detection signal to the main CPU 63, and when the front door frame 14 is open relative to the inner frame 13, the front door open sensor 95 transmits an open detection signal to the main CPU 63. When the main CPU 63 receives a closed detection signal from the front door open sensor 95, it determines that the front door frame 14 is closed, and when it receives an open detection signal from the front door open sensor 95, it determines that the front door frame 14 is open.

In addition, in this embodiment, a main body open sensor 96 for detecting whether the gaming machine main body 12 is in an open state relative to the outer frame 11 is electrically connected to the main CPU 63, and the detection result of the main body open sensor 96 is input to the main CPU 63. In this case, when the gaming machine main body 12 is in a closed state relative to the outer frame 11, the main body open sensor 96 transmits a closed detection signal to the main CPU 63, and when the gaming machine main body 12 is in an open state relative to the outer frame 11, the main body open sensor 96 transmits an open detection signal to the main CPU 63. When the main CPU 63 receives a closed detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in a closed state, and when it receives an open detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in an open state.

If the reset button 68c has not been pressed (step S6615: NO), the power-on setting process is executed in step S6609, and the remaining processes in steps S6610 to S6613 are repeated. In other words, if the reset button 68c has not been pressed, the process proceeds to control the progress of the game without executing the process of clearing the work area 221 for specific control and the stack area 222 for specific control.

If the reset button 68c is pressed (step S6615: YES) and a negative judgment is made in any of steps S6616 to S6618, the process executes a clear process for when settings are not updated (step S6607), and then, on the condition that the setting values are normal (step S6608: YES), the process proceeds to a process for controlling the progress of the game in steps S6609 and onward. The details of the clear process for when settings are not updated have already been explained.

If the reset button 68c is pressed (step S6615: YES) and all of steps S6616 to S6618 return a positive result, processing is performed to update the setting value. Also, if it is determined in step S6608 or step S6614 that the setting value is abnormal, processing is performed to update the setting value.

Specifically, first, a copy process of the setting values is executed (step S6619). In this copy process, the information of the setting value counter used to identify the setting value of the pachinko machine 10 in the work area 221 for specific control is stored in a copy area provided in the work area 221 for specific control. As a result, even if the information of the setting value counter is cleared to "0" in the clear process (step S6620) executed afterwards when the setting value is updated, it is possible to know the setting value of the pachinko machine 10 before the clear process (i.e., the setting value of the pachinko machine 10 before the supply of operating power to the pachinko machine 10 was stopped) when the setting value was updated.

After that, the clearing process at the time of updating the settings is executed (step S6620). In the clearing process at the time of updating the settings, the work area 221 for specific control is cleared to "0" and the initial setting is executed, except for the area indicating whether the winning/losing lottery mode in the work area 221 for specific control is the high probability mode or not and the copy area. As a result, the game round is not being executed, the open/close execution mode is not being executed, and further, the normal map display section 38a is not displayed in a variable manner and the normal power role 34a is in a closed state. In addition, the reserved storage area 65a and the normal power reserved area 65c provided in the work area 221 for specific control are also cleared to "0", so that the reserved information for the special map display section 37a is erased and the reserved information for the normal map display section 38a is erased. In addition, in the clearing process at the time of updating the settings, the stack area 222 for specific control is cleared to "0" and the initial setting is executed. In addition, in the clearing process at the time of updating the settings, the setting value counter used to specify the setting value of the pachinko machine 10 is cleared to "0". In addition, when the settings are updated, the various registers of the main CPU 63 are cleared to "0" before the initial settings are performed.

On the other hand, the clearing process when the settings are updated does not clear to "0" the area indicating whether the win/lose lottery mode is a high probability mode, so even if the setting value update process (step S6621) is executed, the win/lose lottery mode can be maintained in the mode before the supply of operating power to the pachinko machine 10 was stopped. Also, the clearing process when the settings are updated does not clear the copy area to "0", so it is possible to identify the setting value that was set before the clearing process when the settings were updated. Note that this is not limited to the above configuration, and the clearing process when the settings are updated may be configured not to clear to "0" the setting value counter used to identify the setting value of the pachinko machine 10, and the clearing process when the settings are updated may be configured to clear to "0" the area indicating whether the win/lose lottery mode is a high probability mode.

The clearing process during setting updates does not clear the work area 223 for non-specific control and the stack area 224 for non-specific control to "0." This makes it possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" even if a setting value update process that can change the setting values of the pachinko machine 10 is executed.

Then, in step S6621, a setting value update process is executed. The processing content of the setting value update process is the same as the setting value update process in the 22nd embodiment (FIG. 85). After the setting value update process is executed, the process proceeds to step S6609 and subsequent steps for controlling the progress of the game.

According to the above configuration, if the setting value is abnormal, the setting value update process is started without requiring any special operation by the amusement hall manager. Then, when the setting value update process is completed, the process moves to a process for controlling the progress of the game. This makes it possible to play in a situation where the setting value is set to the normal setting. On the other hand, since the setting key insertion section 68a must be turned OFF using the setting key to complete the setting value update process, it is possible to prevent the occurrence of an incident in which the setting value is arbitrarily set by someone other than the amusement hall manager and game play is started.

Next, we will explain the configuration for forcibly stopping the progress of the game when the main CPU 63 is unable to perform various processes normally. Figure 102 (a) is a block diagram for explaining the configuration of the MPU 62.

As shown in FIG. 102(a), the MPU 62 is provided with a main CPU 63, a main ROM 64, and a main RAM 65, as well as a reset signal output unit 251 and a program monitoring unit 252. The reset signal output unit 251 has a function of outputting a reset signal to the main CPU 63. Specifically, when operating power is supplied from the power supply/launch control device 78 and the output disable condition is not satisfied, the reset signal output unit 251 outputs a reset signal to the main CPU 63 as a HI level signal, and when operating power is not supplied from the power supply/launch control device 78 or when operating power is supplied but the output disable condition is satisfied, the reset signal is not output to the main CPU 63. When operating power is supplied from the power supply/launch control device 78 and a reset signal is received from the reset signal output unit 251, the main CPU 63 executes various processes, and when operating power is supplied from the power supply/launch control device 78 and the reset signal is not received from the reset signal output unit 251, the main CPU 63 does not execute various processes when operating power is supplied from the power supply/launch control device 78 but the reset signal is not received from the reset signal output unit 251. In addition, when operating power is being supplied from the power supply/launch control device 78, the main CPU 63 starts the main processing (Figure 100) when the state changes from not receiving a reset signal from the reset signal output unit 251 to receiving a reset signal.

The program monitoring unit 252 has a function of monitoring whether the main CPU 63 is in a state in which various processes can be performed normally. Specifically, the program monitoring unit 252 monitors whether the value of a program counter provided in the main CPU 63 is an abnormal value. The program counter is for storing an address at which an instruction to be executed in the main CPU 63 is stored. The program counter has set values that it can take, and the program monitoring unit 252 monitors whether the value of the program counter is a value other than the possible values. In addition, the program monitoring unit 252 monitors whether the address specified as the write destination area when writing information to the work area 221 for specific control by a load command is an abnormal address. The program monitoring unit 252 may be configured to monitor whether the address specified as the read target area when reading information from the work area 221 for specific control by a load command is an abnormal address.

When the program monitoring unit 252 determines that the program counter value is abnormal, or that the address specified when writing information by a load command is abnormal, it outputs a monitoring abnormality signal to the reset signal output unit 251. When the reset signal output unit 251 receives a monitoring abnormality signal from the program monitoring unit 252, it temporarily stops outputting the reset signal even if operating power is being supplied from the power supply/launch control device 78, and after stopping outputting the reset signal for the duration of the stop, it resumes outputting the reset signal. The duration of the stop is a period sufficient for the main CPU 63 to identify that output of the reset signal has been stopped. As a result, when the program counter value becomes abnormal, or when the address specified when writing information by a load command becomes abnormal, the main processing is executed by the main CPU 63 through OFF/ON of the reset signal.

Figure 102(b) is a time chart showing the output of a reset signal by the reset signal output unit 251. Figure 102(b1) shows the period during which operating power is supplied from the power supply and launch control device 78, Figure 102(b2) shows the period during which a reset signal is output from the reset signal output unit 251, and Figure 102(b3) shows the timing at which a monitoring abnormality signal is output from the program monitoring unit 252.

First, to explain the case where a monitoring abnormality signal is not output from the program monitoring unit 252, the supply of operating power from the power supply and launch control device 78 to the MPU 62 begins at timing t1 as shown in FIG. 102(b1), and the output of a reset signal from the reset signal output unit 251 begins at timing t2 as shown in FIG. 102(b). After that, the supply of operating power from the power supply and launch control device 78 to the MPU 62 is stopped at timing t3 as shown in FIG. 102(b1), and the output of the reset signal from the reset signal output unit 251 is stopped at timing t4 as shown in FIG. 102(b2).

Next, a case where a monitoring abnormality signal is output from the program monitoring unit 252 will be explained. At timing t5, as shown in FIG. 102(b1), the power supply and launch control device 78 starts supplying operating power to the MPU 62, and at timing t6, as shown in FIG. 102(b), the reset signal output unit 251 starts outputting a reset signal. Then, at timing t7, the program counter value becomes abnormal, or the address specified when writing information by a load command becomes abnormal, and as shown in FIG. 102(b3), a monitoring abnormality signal is output from the program monitoring unit 252 to the reset signal output unit 251. As a result, as shown in FIG. 102(b2), the output of the reset signal from the reset signal output unit 251 is temporarily stopped at timing t7, and then resumed at timing t8.

In this case, the main CPU 63 stops the execution of various processes at the timing of t7, and starts the main processing (Fig. 100) at the timing of t8 when the rising edge of the reset signal is confirmed. However, since the power failure processing is not being executed when the main CPU 63 stops the execution of various processes, the main processing (Fig. 100) is started in a situation where the power failure flag in the work area 221 for specific control is not set to "1", and the main processing (Fig. 100) is started without saving the checksums for the work area 221 for specific control and the stack area 222 for specific control. Therefore, in the main processing (Fig. 100), a negative judgment is made at step S6603 or step S6606, and the clear processing at the time of non-setting update (step S6607) is executed. This makes it possible to execute a clear process during non-setting update in which a specified storage area of the work area 221 for specific control and the stack area 222 for specific control are cleared to "0" when a monitoring abnormality signal is output from the program monitoring unit 252 because the program counter value becomes abnormal or the address specified when writing information by a load command becomes abnormal.

However, in the clearing process during non-setting updates, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0". This makes it possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" even if a monitoring abnormality signal is output from the program monitoring unit 252 because the program counter value becomes an abnormal value or the address specified when writing information by a load command becomes an abnormal address.

Returning to the explanation of FIG. 102(b), thereafter, at timing t9, the supply of operating power from the power supply and launch control device 78 to the MPU 62 is stopped as shown in FIG. 102(b1), and the output of the reset signal from the reset signal output unit 251 is stopped at timing t10 as shown in FIG. 102(b2).

Next, the timer interrupt processing in this embodiment executed by the main CPU 63 will be described with reference to the flowchart in FIG. 103. The timer interrupt processing is executed periodically (e.g., every 4 milliseconds) when the processing of steps S6610 to S6613 is being executed in the main processing (FIG. 100). Note that the program corresponding to the timer interrupt processing is set in the program for specific control.

Steps S6801 to S6819 are the same as steps S5201 to S5219 of the timer interrupt process (FIG. 86) in the 22nd embodiment. These processes are executed in the main CPU 63 using a program for specific control and data for specific control. Then, setting monitoring processing is executed (step S6820). FIG. 104 is a flowchart showing the setting monitoring processing.

The setting value counter in the work area 221 for specific control is checked to determine whether the setting value of the pachinko machine 10 is normal or not (step S6901). Specifically, if the setting value set in the setting value counter is any of "Setting 1" to "Setting 6," it is determined to be normal, and if it is "0" or 7 or greater, it is determined to be abnormal.

If the setting value is abnormal (step S6901: NO), a copy process of the setting value is first executed (step S6902). In this copy process, the information of the setting value counter used to identify the setting value of the pachinko machine 10 in the work area 221 for specific control is stored in a copy area provided in the work area 221 for specific control. This makes it possible to grasp the setting value of the pachinko machine 10 before the setting value update process that is executed subsequently is executed.

Then, an abnormality command indicating that an abnormality has occurred in the set value is sent to the sound and light emission control device 81 (step S6903). By receiving the abnormality command, the sound and light emission control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the abnormality in the set value, and causes the speaker unit 54 to output a voice saying, "An abnormality in the set value has been detected." In addition, the pattern display device 41 is made to display a text image saying, "An abnormality in the set value has been detected." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the above notification may be terminated when an operation to terminate the notification is performed by the manager of the game hall. For example, the update button 68b may be pressed as the notification termination operation, or the reset button 68c may be pressed. By confirming the above notification, the manager of the game hall can understand that an abnormality in the set value has occurred.

Then, the setting value update process is executed (step S6904). That is, each time the timer interrupt process (Fig. 103) is executed, whether or not an abnormality has occurred in the setting value is monitored, and if an abnormality in the setting value is identified, the setting value update process is executed to reset the setting value of the pachinko machine 10. The processing content of the setting value update process is the same as the setting value update process (Fig. 85) in the 22nd embodiment. Therefore, each time the update button 68b is pressed once, the setting value is updated by one step, and the selected setting value is confirmed by detecting a game ball with the outlet detection sensor 48a. The setting value being updated and the confirmed setting value are displayed on the third notification display device 69c. Then, if the setting key insertion section 68a is switched from the ON state to the OFF state, it is determined that the end condition of the setting value update process is satisfied. After the setting value update process is executed, the process returns to the timer interrupt process (Fig. 103).

In the setting value update process, the termination condition is not determined to be met simply because the setting key insertion unit 68a is in the OFF state; the termination condition is determined to be met when the setting key insertion unit 68a switches from the ON state to the OFF state. When the setting value update process is executed in the setting monitoring process, the setting key insertion unit 68a is in the OFF state at the start of the setting value update process, so in order to satisfy the termination condition of the setting value update process, it is necessary to insert the setting key into the setting key insertion unit 68a and turn it ON once, and then turn it OFF. This makes it possible to prevent the setting value update process from terminating even if the proper operation has not been performed by the amusement hall manager.

When the setting key insertion section 68a switches from ON to OFF and the end condition of the setting value update process is satisfied, step S5111 in the setting value update process (FIG. 85) is executed to compare whether the setting value stored in the copy area in the work area 221 for specific control is the same as the setting value currently set in the setting value counter in the work area 221 for specific control. In other words, it is determined whether the setting value set before the setting value update process (step S6904) is executed is the same as the setting value set in the current setting value update process. If the two setting values are the same (step S5112: NO), the notification process for non-change (step S5113) is executed so that the setting maintenance notification already described is performed. On the other hand, if the two setting values are different (step S5112: YES), the notification process for change (step S5114) is executed so that the setting change notification already described is performed.

In a configuration in which a setting value update process is executed when a setting value abnormality occurs, a setting maintenance notification is issued if the setting value set before the setting value update process is executed is the same as the setting value set in the setting value update process. As a result, even if the setting value update process is executed due to a setting value abnormality, the setting maintenance notification is issued by resetting the setting value set in the previous situation, making it possible to clearly inform the player that the setting value has not changed even if the setting value update process is executed due to a setting value abnormality. Incidentally, since it is common for game halls to record the setting values of each pachinko machine 10 installed, it is possible to execute the setting value update process due to a setting value abnormality so that the recorded setting value is used.

Returning to the explanation of the timer interrupt process (FIG. 103), after the setting monitoring process is executed in step S6820, the management process is executed in step S6821. When the management process is executed, a subroutine program corresponding to the management process set in the program for specific control is executed, and when the subroutine program is executed, information for specifying the return address of the timer interrupt process after the management process is executed is written to the stack area 222 for specific control by a push command. Then, when the management process is completed, information for specifying the return address is read by a pop command, and the process returns to the timer interrupt process program indicated by the return address.

Figure 105 is a flowchart showing the management process in this embodiment, which is executed by the main CPU 63. Note that the processes in steps S7001 to S7005 in the management process are executed by the main CPU 63 using a program for specific control and data for specific control.

First, in order to prohibit the occurrence of timer interrupt processing (FIG. 103), interrupt prohibition is set (step S7001). This makes it possible to prevent the timer interrupt processing (FIG. 103), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described later), which is processing corresponding to non-specific control.

Then, the load command "LD (_PSWBUF), PSW" is used to save the flag register information of the main CPU 63 to the PSW buffer set in the work area 221 for specific control (step S7002). The flag register includes a carry flag, zero flag, P/V flag, sign flag, and half carry flag, and the flag register information changes depending on the execution results of arithmetic instructions, rotate instructions, input/output instructions, and the like. By saving such flag register information before the program of the subroutine corresponding to the management execution process is started, it is possible to save the flag register information in the state before it changes after the subroutine is called or started in the work area 221 for specific control.

Then, the management execution process is started by reading out a subroutine program corresponding to the management execution process set in the program for non-specific control (step S7003). In this case, information for specifying the return address of the management process after the management execution process is executed is written into the stack area 222 for specific control by a push command. Then, when the management execution process is completed, information for specifying the return address is read out by a pop command, and the process returns to the program for the management process indicated by the return address.

When the program for the management process is returned to after the management execution process is executed, the flag register information saved in the PSW buffer in the work area 221 for specific control in step S7002 is restored to the flag register of the main CPU 63 by a load command as "LD PSW, (_PSWBUF)" (step S7004). This causes the information in the flag register of the main CPU 63 to return to the information at the time step S7002 was last executed. In other words, the information in the flag register of the main CPU 63 returns to the information for executing specific control.

After that, the interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing (FIG. 103) is prohibited to a state in which it is permitted (step S7005). This allows a new execution of the timer interrupt processing.

Figure 106 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that the processes in steps S7101 to S7116 in the management execution process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

Steps S7101 to S7108 and steps S7110 to S7116 execute the same processing as steps S4501 to S4515 of the management execution process (FIG. 78) in the 17th embodiment. In addition, step S7109 executes another monitoring process. When the other monitoring process is executed, a subroutine program corresponding to the other monitoring process set in the program for non-specific control is executed, and when the subroutine program is executed, information for specifying the return address of the management execution process after the execution of the other monitoring process is written to the stack area 224 for non-specific control by a push command. Then, when the other monitoring process is completed, information for specifying the return address is read by a pop command, and the program for the management execution process indicated by the return address is returned to.

Figure 107 is a flowchart showing the separate monitoring process. Note that the processing of steps S7201 to S7206 in the separate monitoring process is executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

In the separate monitoring process, it is determined whether the value of the pointer indicating the processing position of the process being executed in the program for non-specific control is a value that exceeds the normal numerical range (step S7201). It is also determined whether the information stored in the normal counter area 231, the counter area for open/close execution mode 232, and the counter area for high frequency support mode 233 provided in the work area 223 for non-specific control is obviously abnormal (step S7202). For example, if the value of the normal out counter 231e in the normal counter area 231 is "0" but the value of the normal general winning counter 231a is 1000 or more in the normal counter area 231, it is determined that there is an abnormality. It is also determined whether the information stored in the calculation result storage area 234 provided in the work area 223 for non-specific control is obviously abnormal (step S7203). For example, if the 61st parameter is "0" but any of the 62nd to 64th parameters is not "0", it is determined that there is an abnormality.

If a positive judgment is made in any of steps S7201 to S7203, it is determined that an information abnormality has occurred in the work area 223 for non-specific control, and a partial clear process for the work area 223 for non-specific control is executed (step S7204). In the partial clear process, all storage areas in the work area 223 for non-specific control other than the management start flag are cleared to "0". In this case, the normal counter area 231, the counter area 232 for opening/closing execution mode, the counter area 233 for high frequency support mode, and the calculation result storage area 234 are all cleared to "0". This makes it possible to resolve the information abnormality in the work area 223 for non-specific control.

In addition, by not clearing the management start flag to "0", it is possible to maintain the state in which the management start flag is already set to "1", and it is possible to prevent restrictions on the collection of history information at the shipping stage of the pachinko machine 10 from occurring even if the pachinko machine 10 is already being used continuously at the gaming hall. However, this is not limited to this, and in step S7204, the entire work area 223 for non-specific control, including the management start flag, may be configured to be cleared to "0".

In addition, in step S7204, the stack area 224 for non-specific control is not cleared to "0". The stack area 224 for non-specific control stores information of various registers used in the processing corresponding to the specific control in steps S7102 to S7107 of the management execution processing (FIG. 106). In this case, by not clearing the stack area 224 for non-specific control to "0", it is possible to prevent the information of various registers used in the processing corresponding to this specific control, which is stored in the stack area 224 for non-specific control, from being erased. In addition, the stack area 224 for non-specific control stores information of the return address of the management execution processing (FIG. 106) after the separate monitoring processing is completed, and by not clearing the stack area 224 for non-specific control to "0", it is possible to prevent the information of this return address from being erased.

After that, the initial setting process is executed (step S7205). In the initial setting process, initial settings are made to the memory areas in the non-specific control work area 223 that were cleared to "0" in step S7204.

Then, the clear notification process is executed (step S7206). In the clear notification process, a command indicating that the work area 223 for non-specific control has been cleared to "0" is sent to the voice and light emission control device 81. By receiving the command, the voice and light emission control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the forced clearing of the work area 223 for non-specific control, and causes the speaker unit 54 to output a voice saying "The history information has been forcibly cleared." In addition, the pattern display device 41 is made to display a text image saying "The history information has been forcibly cleared." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the above notification may be terminated when a notification termination operation is performed by the manager of the game hall. For example, the update button 68b may be pressed as the notification termination operation, or the reset button 68c may be pressed. By checking the above notification, the manager of the amusement hall can understand that the work area 223 for non-specific control has been forcibly cleared.

If a negative judgment is made in all of steps S7201 to S7203, or if the processing of step S7206 is executed, the separate monitoring processing ends and the processing returns to the monitoring execution processing (Figure 106).

The present embodiment described above provides the following excellent advantages:

When the program monitoring unit 252 identifies that the address specified when writing information by a load command is an abnormal address, the reset signal output unit 251 turns the reset signal from OFF to ON, and the main CPU 63 executes the main processing (FIG. 100) in the same manner as when the supply of operating power is newly started. When the reset signal is turned from OFF to ON, the power failure flag in the work area 221 for specific control is not set to "1" and the checksum at the time of the power failure is not stored in the work area 221 for specific control, so that the clear processing at the time of non-setting update (step S6607) is forcibly executed. In the clear processing at the time of non-setting update, the memory areas other than the memory area in which the setting value of the pachinko machine 10 is stored in the work area 221 for specific control are cleared to "0" and the stack area 222 for specific control is cleared to "0", and the initial setting processing of these areas is executed. As a result, if there is a possibility that an information abnormality has occurred regarding the work area 221 for specific control or the stack area 222 for specific control, the information abnormality can be resolved by executing a "0" clear process and an initial setting process on the work area 221 for specific control and the stack area 222 for specific control.

When the program monitoring unit 252 identifies that the program counter value of the main CPU 63 is an abnormal value, the reset signal output unit 251 turns the reset signal from OFF to ON, and the main CPU 63 executes the main processing (FIG. 100) in the same manner as when the supply of operating power is newly started. When the reset signal is turned from OFF to ON, the power failure flag in the work area 221 for specific control is not set to "1" and the checksum at the time of the power failure is not stored in the work area 221 for specific control, so that the clear processing at the time of non-setting update (step S6607) is forcibly executed. In the clear processing at the time of non-setting update, the internal storage area of the main CPU 63, including various registers, is cleared to "0" and an initial setting process is executed. As a result, when there is a possibility that an information abnormality has occurred in the internal storage area of the main CPU 63, the information abnormality can be eliminated by clearing the internal storage area of the main CPU 63 to "0" and executing the initial setting process.

On the other hand, the clearing process during non-setting updates does not clear the work area 223 for non-specific control and the stack area 224 for non-specific control to "0". This makes it possible to prevent the information on the game history from being erased and to prevent the information on the management results of the game history from being erased even when an information anomaly is identified by the program monitoring unit 252 as described above and the internal memory area of the main CPU 63, the work area 221 for specific control, and the stack area 222 for specific control are cleared to "0" and an initial setting process is executed.

In a configuration in which a clear process (step S6607) is executed during non-setting update if the power outage flag is not set to "1" or the checksum does not match during main processing (Figure 100) when the supply of operating power to the main CPU 63 is started, and if the program monitoring unit 252 identifies the occurrence of an information anomaly, the reset signal is turned from OFF to ON so that the main processing (Figure 100) is executed in a situation in which the power outage flag is not set to "1" and the checksum is not stored. This makes it possible to eliminate the information anomaly identified by the program monitoring unit 252 by utilizing the configuration for eliminating the information anomaly when the supply of operating power is started.

In a configuration in which the main processing (Figure 100) monitors whether the checksum is normal when the supply of operating power to the main CPU 63 is started, the calculation of the checksum includes the work area 221 for specific control and the stack area 222 for specific control, but does not include the work area 223 for non-specific control and the stack area 224 for non-specific control. This makes it possible to determine whether an information abnormality has occurred only in the memory area corresponding to the specific control in the main RAM 65.

When the main processing (FIG. 100) when the supply of operating power to the main CPU 63 is started identifies that the checksum is abnormal, a clear process during non-setting update (step S6607) is executed. In the clear process during non-setting update, the work area 221 for specific control and the stack area 222 for specific control are cleared to "0" and an initial setting process is executed, whereas the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0". This makes it possible to prevent the process corresponding to specific control from continuing to be executed in the same state despite the occurrence of an information abnormality in the work area 221 for specific control and the stack area 222 for specific control, and also makes it possible to prevent the memory area corresponding to non-specific control in the main RAM 65 from being cleared to "0" in response to an information abnormality in the work area 221 for specific control and the stack area 222 for specific control.

In the power outage processing (steps S6709 to S6712) of the power outage information storage processing (Figure 101), a checksum is calculated for the work area 221 for specific control and the stack area 222 for specific control, but a checksum is not calculated for the storage area corresponding to non-specific control in the main RAM 65. This makes it possible to prevent the processing period required to complete the power outage processing from becoming excessively long.

When an abnormality is identified in the information stored in the work area 223 for non-specific control in another monitoring process (FIG. 107) executed in the process corresponding to non-specific control, the work area 223 for non-specific control is cleared to "0" in the other monitoring process (FIG. 107) which is the process corresponding to non-specific control, and an initial setting process is executed. This makes it possible to prevent the process corresponding to non-specific control from being executed in a state where the information in the work area 223 for non-specific control is retained as it is, even if some abnormality has occurred in the work area 223 for non-specific control. In addition, since the process of clearing the work area 223 for non-specific control to "0" and the process of initial setting are executed in the process corresponding to non-specific control, it is possible to prevent the process corresponding to specific control from being involved in updating the information in the work area 223 for non-specific control.

In another monitoring process (FIG. 107) corresponding to non-specific control, monitoring is performed to see if an abnormality has occurred in the work area 223 for non-specific control, and if an abnormality has occurred, a process of clearing the work area 223 for non-specific control to "0" and a process of initializing the work area 223 for non-specific control are performed. This makes it possible to monitor whether an abnormality has occurred in the work area 223 for non-specific control and to initialize the work area 223 for non-specific control as a series of processes in the process corresponding to non-specific control.

If the occurrence of an abnormality is identified in the information stored in the work area 223 for non-specific control in the separate monitoring process (FIG. 107) executed in the process corresponding to non-specific control, the work area 223 for non-specific control is cleared to "0" and initialized, but the stack area 224 for non-specific control is not cleared to "0" or initialized. This makes it possible to resolve the information abnormality in the work area 223 for non-specific control while preventing the information of various registers used in the process corresponding to specific control that has been saved in the stack area 224 for non-specific control and the return address information after the separate management process is completed from being erased.

The process of clearing the work area 221 for specific control and the stack area 222 for specific control to "0" and initializing them is executed by the process corresponding to the specific control, and the process of clearing the work area 223 for non-specific control to "0" and initializing them is executed by the process corresponding to the non-specific control. This makes it possible for such initialization processes to be treated as the work area 221 for specific control and the stack area 222 for specific control as dedicated memory areas for the process corresponding to the specific control, and for the work area 223 for non-specific control as dedicated memory areas for the process corresponding to the non-specific control.

In the main processing (FIG. 100), steps S6608 and S6614 are configured to monitor whether the set values are normal, but the processing to monitor whether these set values are normal may not be executed. This makes it possible to reduce the processing load of the processing at the start of the supply of operating power, which is executed when the supply of operating power to the main CPU 63 is started. Also, even if the processing at the start of the supply of operating power does not monitor whether the set values are normal, the setting monitoring processing (step S6820) of the timer interrupt processing (FIG. 103), which is executed after the processing at the start of the supply of operating power is completed, monitors whether the set values are normal, so that if the set values are abnormal, it is possible to deal with the situation.

Furthermore, the configuration is not limited to the configuration in which the setting monitoring process (step S6820) is executed each time the timer interrupt process (FIG. 103) is started, but may be configured such that the setting monitoring process (step S6820) is executed each time the timer interrupt process (FIG. 103) is executed a number of times (e.g., 10,000 times) that is set as multiple triggers. In this case, it is possible to periodically monitor whether the setting values are normal, while reducing the frequency with which the monitoring is executed.

The setting monitoring process (step S6820) may also be configured to be executed during the remaining processing (steps S6610 to S6613) in the main processing (Figure 100). In this case, it is possible to monitor whether the setting value is normal by utilizing the free time when the timer interrupt processing is not being executed.

Also, the configuration may be such that the setting monitoring process (step S6820) is executed when a new round of play is started. More specifically, the configuration may be such that the setting monitoring process (step S6820) is executed before the win/loss determination process is executed when a new round of play is started. This makes it possible to prevent the win/loss determination process from being executed in a situation where the setting value is abnormal.

In addition, when the setting value is identified as abnormal in the setting monitoring process (step S6820), instead of proceeding to the setting value update process (step S6904), the game stop flag provided in the work area 221 for specific control may be set to "1". In this case, since the processes of steps S6808 to S6821 are not executed by making a positive judgment in step S6807 in the timer interrupt process (Fig. 103), the progress of the game is stopped if the setting value is abnormal. However, since the processes of steps S6801 to S6806 are executed, power outage monitoring is executed, and the hit random number counter C1, the big win type counter C2, the reach random number counter C3, and the random number initial value counter CINI are updated, and further, fraud detection is executed. In addition, when the game stop flag is set to "1", a notification indicating that the setting value should be updated may be executed to prompt the execution of the setting value update process. In this case, the manager of the gaming hall who has confirmed the notification can turn the power OFF and then turn the power ON in a manner that executes the setting value update process, clearing the game stop flag to "0" and releasing the state in which game progress has been stopped, while also executing the setting value update process and setting the correct setting value.

In addition, if the setting monitoring process (step S6820) identifies an abnormal setting value, the main process (Fig. 100) may be started with the setting abnormality flag set in the work area 221 for specific control set to "1", and the game progress may be stopped with the setting abnormality flag set to "1", and the power must be turned OFF and ON to release the stopped state of the game progress. In this case, even if no operation is performed in the main process (Fig. 100) to execute the setting value update process, by forcibly executing the setting value update process when the setting abnormality flag is set to "1", it is possible to forcibly set a new setting value using the setting value update process set in the main process (Fig. 100).

Also, when the program monitoring unit 252 identifies the occurrence of an information abnormality and forcibly turns the reset signal from OFF to ON, an initialization process is executed on the work area 221 for specific control, so that the setting value of the pachinko machine 10 becomes "setting 1."Also, when the program monitoring unit 252 identifies the occurrence of an information abnormality and forcibly turns the reset signal from OFF to ON, an initialization process is executed on the work area 221 for specific control, and then a setting value update process is executed.

In addition, when the program monitoring unit 252 identifies the occurrence of an information abnormality, the reset signal may not be forcibly turned from OFF to ON, and a clear process (step S6607) may be executed when no setting is updated, or a clear process (step S6620) and a setting value update process (step S6621) may be executed when the setting is updated.

In addition, in the clear process when the setting is not updated (step S6607), the setting value of the pachinko machine 10 may be configured to be "Setting 1" by initializing the memory area that stores information on the setting value in the work area 221 for specific control, or may be configured to be a predetermined setting value other than "Setting 1". This makes it possible to set the setting value to a predetermined value when the clear process when the setting is not updated is executed.

In addition, in the clearing process when updating non-settings (step S6607), the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0", but they may be cleared to "0".

In addition, in step S7204 in the separate monitoring process (FIG. 107), the management start flag is not cleared to "0", but the management start flag may be cleared to "0". In addition, in step S7204 in the separate monitoring process (FIG. 107), the normal counter area 231, the open/close execution mode counter area 232, and the high frequency support mode counter area 233 may not be cleared to "0", and the calculation result storage area 234 may not be cleared to "0".

In addition, in step S7204 in the separate monitoring process (FIG. 107), a configuration may be adopted in which a "0" clear process and an initial setting process are performed not only on the work area 223 for non-specific control but also on the stack area 224 for non-specific control. In this case, it is preferable not to erase the information on the return address of the management execution process after the separate monitoring process is completed in the stack area 224 for non-specific control and the information of various registers used in the process corresponding to the specific control that has been saved in the stack area 224 for non-specific control.

The separate monitoring process (FIG. 107) may also be configured to monitor whether an abnormality has occurred in the non-specific control stack area 224, and if an abnormality is identified, to execute a process of clearing the non-specific control stack area 224 to "0" and an initial setting process. In this case, it is preferable not to erase the information on the return address of the management execution process in the non-specific control stack area 224 after the separate monitoring process has ended.

Furthermore, the configuration is not limited to one in which both the work area 221 for specific control and the stack area 222 for specific control are the subject of checksum calculation, and it may be a configuration in which only the work area 221 for specific control is the subject of checksum calculation, or a configuration in which only the stack area 222 for specific control is the subject of checksum calculation.

Thirty-first embodiment
In this embodiment, the processing configuration of the main processing executed by the main CPU 63 is different from that of the 30th embodiment. The configuration that differs from the 30th embodiment will be described below. Note that the description of the same configuration as the 30th embodiment will basically be omitted.

Figure 108 is a flowchart showing the main processing in this embodiment executed by the main CPU 63. Note that the processing of steps S7301 to S7322 in the main processing is executed using a program for specific control and data for specific control in the main CPU 63.

First, the power-on wait process is executed (step S7301). In this power-on wait process, for example, the main process is started and a predetermined wait time (specifically, one second) elapses before proceeding to the next process. During the execution period of this power-on wait process, the operation start and initial settings of the pattern display device 41 are completed. After that, access to the main RAM 65 is permitted (step S7302).

Then, it is determined whether the power outage flag provided in the work area 221 for specific control in the main RAM 65 is set to "1" (step S7303). If the power outage flag is set to "1" (step S7303: YES), a checksum is calculated for the work area 221 for specific control and the stack area 222 for specific control (step S7304). The method of calculating the checksum is the same as step S6604 in the main processing (Figure 100) in the 30th embodiment above.

Then, the checksums for the work area 221 for specific control and the stack area 222 for specific control that were calculated and stored in the work area 221 for specific control during the power outage processing executed immediately before the supply of operating power to the MPU 62 was stopped are read from the work area 221 for specific control, and the read checksums are compared with the checksum calculated in step S7304 (step S7305). Then, it is determined whether these checksums match (step S7306).

If a positive determination is made in step S7306, steps S7307 to S7320 are executed. In this case, the processing content of steps S7307 to S7314 is the same as steps S6614 to S6621 in the main processing (FIG. 100) in the 30th embodiment, and steps S7316 to S7320 are the same as steps S6609 to S6613 in the main processing (FIG. 100) in the 30th embodiment.

In addition, when the reset button 68c is pressed (step S7308: YES), if a negative judgment is made in any of steps S7309 to S7311, a clear process for non-setting update is executed (step S7315). The processing content of the clear process for non-setting update is the same as step S6607 in the main processing (FIG. 100) in the 30th embodiment. However, in this embodiment, after the clear process for non-setting update is executed, the process proceeds to steps S7316 to S7320 without judging whether the setting value is normal or not. The clear process for non-setting update (step S7315) is executed only if a negative judgment is made in any of steps S7309 to S7311. However, since the judgment of whether the setting value is normal or not is made in step S7307 before the processing of steps S7309 to S7311 is executed, it is not necessary to judge whether the setting value is normal or not after the clear process for non-setting update is executed.

If a negative judgment is made in step S7303 or step S7306, i.e., if the power failure flag in the work area 221 for specific control is not set to "1" or a checksum abnormality occurs, a clear process in the event of an abnormality is executed (step S7321). FIG. 109 is a flowchart showing the clear process in the event of an abnormality. Note that the processes in steps S7401 to S7405 in the clear process in the event of an abnormality are executed by the main CPU 63 using a program for specific control and data for specific control.

First, a clear process is performed on the work area 221 for specific control (step S7401). In this clear process, the work area 221 for specific control is cleared to "0" except for the area in which the setting value information indicating the setting state of the pachinko machine 10 is set in the work area 221 for specific control (specifically, the setting value counter), and the initial setting is performed for the area cleared to "0". As a result, the area indicating whether the winning/losing lottery mode is the high probability mode or not is cleared to "0", so that the winning/losing lottery mode becomes the low probability mode regardless of the winning/losing lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. In addition, the game round is not being executed, the open/close execution mode is not being executed, and further, the normal map display unit 38a is not displayed in a variable manner and the normal power role 34a is in a closed state. In addition, the reserved storage area 65a and the regular power reserved area 65c provided in the work area 221 for specific control are also cleared to "0", so that the reserved information for the special map display unit 37a is erased and the reserved information for the regular map display unit 38a is erased.

After that, a process for clearing the stack area 222 for specific control is executed (step S7402). In this process, the stack area 222 for specific control is cleared to "0" and an initial setting is performed.

After that, the information in the flag register of the main CPU 63 is saved to the stack area 222 for specific control by a push command as "PUSH PSW" (step S7403). The flag register includes a carry flag, zero flag, P/V flag, sign flag, and half carry flag, and the information in the flag register changes depending on the execution results of arithmetic instructions, rotate instructions, input/output instructions, and the like. By saving such flag register information before the program of a subroutine corresponding to a clear process for non-specific control is started, it becomes possible to save the information in the flag register in the state before it changes after the call of the subroutine or the start of the subroutine in the stack area 222 for specific control. The amount of information in the flag register is 1 byte.

Then, the clear processing for non-specific control is started by reading out a subroutine program corresponding to the clear processing for non-specific control set in the program for non-specific control (step S7404). In this case, information for specifying the return address of the clear processing in the event of an abnormality after the clear processing for non-specific control is executed is written into the stack area 222 for specific control by a push command. Then, when the clear processing for non-specific control is completed, information for specifying the return address is read out by a pop command, and the program for the clear processing in the event of an abnormality indicated by the return address is returned to.

When returning to the program for the abnormality clear process after the execution of the non-specific control clear process, the flag register information saved in the specific control stack area 222 in step S7402 is restored to the flag register of the main CPU 63 by a pop command as "POP PSW" (step S7405). This causes the flag register information of the main CPU 63 to return to the information at the time step S7402 was executed. In other words, the flag register information of the main CPU 63 returns to the information for executing specific control.

Figure 110 is a flowchart showing the clearing process for non-specific control. Note that the processes in steps S7501 to S7516 in the clearing process for non-specific control are executed in the main CPU 63 using the program for non-specific control and data for non-specific control.

First, a load command is used to set "LD SP, Y(u+2)" to the stack pointer of the main CPU 63 as a fixed address at the start of non-specific control, Y(u+2) (step S7501). In this case, the information of the last address in the stack area 224 for non-specific control is set to the stack pointer, similar to step S3901 of the management execution process (FIG. 71) in the 15th embodiment.

Thereafter, the information in the WA register of the master CPU 63 is saved to the WA buffer set in the work area 223 for non-specific control by a load command as "LD (_WABUF), WA" (step S7502). Also, the information in the BC register of the master CPU 63 is saved to the BC buffer set in the work area 223 for non-specific control by a load command as "LD (_BCBUF), BC" (step S7503). Also,
The load command is "LD (_DEBUF), DE" to save the information in the DE register of the master CPU 63 to the DE buffer set in the work area 223 for non-specific control (step S7504). The load command is "LD (_HLBUF), HL" to save the information in the HL register of the master CPU 63 to the HL buffer set in the work area 223 for non-specific control (step S7505). The load command is "LD (_IXBUF), IX" to save the information in the IX register of the master CPU 63 to the IX buffer set in the work area 223 for non-specific control (step S7506). The load command is "LD (_IYBUF), IY" to save the information in the IY register of the master CPU 63 to the IY buffer set in the work area 223 for non-specific control (step S7507).

In addition to the flag register already described, the main CPU 63 also contains various general-purpose registers, auxiliary registers, and index registers. In this case, in steps S7502 to S7507, the information of some of these general-purpose registers, auxiliary registers, and index registers, namely the WA register, BC register, DE register, HL register, IX register, and IY register, is saved to the corresponding buffer in the non-specific control work area 223. Note that the amount of information in the WA register, BC register, DE register, HL register, IX register, and IY register is all 2 bytes.

The WA register, BC register, DE register, HL register, IX register, and IY register are registers used in the partial clearing process (step S7508) and initial setting process (step S7509) of the work area 223 for non-specific control, which are processes corresponding to non-specific control. By saving the information set in such registers to the work area 223 for non-specific control prior to the partial clearing process (step S7508) and initial setting process (step S7509) of the work area 223 for non-specific control, it is possible to save the information of these registers used during specific control before the non-specific control is started. Therefore, even if these registers are overwritten during non-specific control, by restoring the information saved in the work area 223 for non-specific control to these registers when the non-specific control is terminated, it is possible to restore the state of these registers to the state corresponding to the specific control before the non-specific control is executed.

In addition, instead of saving all the information of the various general-purpose registers, auxiliary registers, and index registers to the work area 223 for non-specific control, the information of the WA register, BC register, DE register, HL register, IX register, and IY register to be used in the partial clearing process (step S7508) and initial setting process (step S7509) of the work area 223 for non-specific control, which are processes corresponding to the non-specific control, is selectively saved to the work area 223 for non-specific control, thereby making it possible to reduce the capacity reserved for saving the register information in the work area 223 for non-specific control. Therefore, it is possible to save the above-mentioned register information while securing a large capacity of the work area 223 for non-specific control that is available for the partial clearing process (step S7508) and initial setting process (step S7509) of the work area 223 for non-specific control. Of course, for the various general-purpose registers, auxiliary registers, and index registers in the main CPU 63, other than the WA register, BC register, DE register, HL register, IX register, and IY register, the information set before the processing corresponding to the non-specific control is started is stored and held until the processing corresponding to the non-specific control is completed and the processing corresponding to the specific control is resumed.

In addition, by saving the register information to the work area 223 for non-specific control instead of saving it to the stack area 224 for non-specific control, it is possible to reduce the capacity of the stack area 224 for non-specific control. In addition, when using the stack area 224 for non-specific control, as already explained, the writing order of information is such that later information is read first. Therefore, if the reading order of information is shifted due to some kind of noise or the like, all information in the subsequent read order will be restored to different registers. The probability of such an event occurring increases as the amount of information saved to the stack area 224 for non-specific control increases. In contrast, by saving the register information to the work area 223 for non-specific control, it is possible to prevent such an event from occurring even when there is a lot of information to be saved.

After steps S7502 to S7507 are executed, a partial clear process of the work area 223 for non-specific control is executed (step S7508). In this partial clear process, the storage areas of the work area 223 for non-specific control are cleared to "0" except for the storage areas in which the information of the various registers of the main CPU 63 used in the process corresponding to the specific control is saved. Specifically, among the storage areas of the work area 223 for non-specific control, the WA buffer, BC buffer, DE buffer, HL buffer, IX buffer, and IY buffer are not cleared to "0", while the storage areas other than these various buffers are cleared to "0".

In this case, the normal counter area 231, the open/close execution mode counter area 232, the high frequency support mode counter area 233, the calculation result storage area 234, and the management start flag are all cleared to "0". This makes it possible to eliminate information abnormalities in the work area 223 for non-specific control. Also, by not clearing to "0" the storage area in which the information of the various registers of the main CPU 63 used in the processing corresponding to specific control is saved, it becomes possible to restore the information used in the processing corresponding to specific control to the various registers of the main CPU 63 when the processing corresponding to non-specific control ends and returns to the processing corresponding to specific control.

In addition, in step S7508, the stack area 224 for non-specific control is not cleared to "0." The stack area 224 for non-specific control stores return address information for the clearing process (FIG. 109) in the event of an abnormality after the clearing process for non-specific control is completed, but by not clearing the stack area 224 for non-specific control to "0," it is possible to prevent this return address information from being erased.

After that, the initial setting process is executed (step S7509). In the initial setting process, initial settings are made to the storage areas in the non-specific control work area 223 that were cleared to "0" in step S7508.

After that, as in step S3909 of the management execution process (FIG. 71) in the 15th embodiment, a load command is issued to set Y(r+α) as a fixed address at the time of return to specific control in the stack pointer of the main CPU 63 as "LD SP, Y(r+α)" (step S7510). The address of Y(r+α) is set as an address between Y(r+8) and Y(s) in the stack area 222 for specific control.

Then, the information saved in the WA buffer of the work area 223 for non-specific control is overwritten in the WA register of the main CPU 63 by a load command as "LD WA, (_WABUF)" (step S7511). Also, the information saved in the BC buffer of the work area 223 for non-specific control is overwritten in the BC register of the main CPU 63 by a load command as "LD BC, (_BCBUF)" (step S7512). Also, the information saved in the DE buffer of the work area 223 for non-specific control is overwritten in the DE register of the main CPU 63 by a load command as "LD DE, (_DEBUF)" (step S7513). Also, the information saved in the HL buffer of the work area 223 for non-specific control is overwritten in the HL register of the main CPU 63 by a load command as "LD HL, (_HLBUF)" (step S7514). Also, the load command "LD IX, (_IXBUF)" overwrites the IX register of the main CPU 63 with the information saved in the IX buffer of the work area 223 for non-specific control (step S7515). Also, the load command "LD IY, (_IYBUF)" overwrites the IY register of the main CPU 63 with the information saved in the IY buffer of the work area 223 for non-specific control (step S7516). By executing the processes of steps S7511 to S7516, it is possible to restore the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 to the information corresponding to specific control immediately before the process corresponding to non-specific control was started.

According to the above configuration, if the power failure flag is not set to "1" in the main process (FIG. 108) executed when the supply of operating power to the main CPU 63 is started, or if the checksum is abnormal, the abnormality clear process (step S7321) is executed, and not only the work area 221 for specific control and the stack area 222 for specific control, but also the work area 223 for non-specific control is cleared to "0" and initialized. If an information abnormality occurs in the work area 221 for specific control, an information abnormality may also occur in the work area 223 for non-specific control. However, by initializing the work area 223 for non-specific control in the abnormality clear process, it is possible to prevent the process corresponding to non-specific control from being executed in the same state despite the information abnormality occurring in the work area 223 for non-specific control.

Even if the process of clearing to "0" and the process of initializing the work area 223 for non-specific control are executed in the abnormality clearing process (step S7321), the information of various registers used in the process corresponding to the specific control that was saved in the work area 223 for non-specific control is not cleared to "0". This makes it possible to execute the process of clearing to "0" and the process of initializing the work area 223 for non-specific control while not erasing the information used in the process corresponding to the specific control after the process corresponding to the non-specific control is completed.

Even if the process of clearing to "0" and initializing is performed on the work area 223 for non-specific control in the abnormality clear process (step S7321), the process of clearing to "0" and initializing is not performed on the stack area 224 for non-specific control. This makes it possible to prevent the return address information from being erased after the non-specific control clear process (Figure 110) is completed.

The process of clearing the work area 221 for specific control and the stack area 222 for specific control to "0" and the process of initializing are executed by the process corresponding to the specific control, and the process of clearing the work area 223 for non-specific control to "0" and the process of initializing are executed by the process corresponding to the non-specific control. This makes it possible for the work area 221 for specific control and the stack area 222 for specific control to be treated as a dedicated memory area for the process corresponding to the specific control, and for the process of clearing to "0" and the process of initializing, too, and for the work area 223 for non-specific control to be treated as a dedicated memory area for the process corresponding to the non-specific control.

Note that the configuration is not limited to one in which both the work area 221 for specific control and the stack area 222 for specific control are subject to checksum calculation, and it may be one in which only the work area 221 for specific control is subject to checksum calculation, or one in which only the stack area 222 for specific control is subject to checksum calculation.

The work area 223 for non-specific control may also be configured to be the target of checksum calculation. In this case, the work area 221 for specific control and the work area 223 for non-specific control may also be configured to be the target of checksum calculation, the stack area 222 for specific control and the work area 223 for non-specific control may also be configured to be the target of checksum calculation, or the work area 221 for specific control, the stack area 222 for specific control and the work area 223 for non-specific control may also be configured to be the target of checksum calculation.

The stack area 224 for non-specific control may also be configured to be the target of checksum calculation. In this case, the work area 221 for specific control and the stack area 224 for non-specific control may also be configured to be the target of checksum calculation, the stack area 222 for specific control and the stack area 224 for non-specific control may also be configured to be the target of checksum calculation, or the work area 221 for specific control, the stack area 222 for specific control and the stack area 224 for non-specific control may also be configured to be the target of checksum calculation.

Also, the work area 223 for non-specific control and the stack area 224 for non-specific control may be configured to be the targets of checksum calculation. In this case, the work area 221 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control may be configured to be the targets of checksum calculation, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control may be configured to be the targets of checksum calculation, or the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control may be configured to be the targets of checksum calculation.

In addition, in steps S7508 and S7509 in the non-specific control clear process (FIG. 110), the process of clearing to "0" and the initial setting process may be performed not only on the non-specific control work area 223 but also on the non-specific control stack area 224. In this case, it is preferable not to erase the return address information for the clear process in the event of an abnormality after the non-specific control clear process is completed.

In addition, in step S7508 in the clearing process for non-specific control (FIG. 110), the management start flag is cleared to "0", but the management start flag may not be cleared to "0". In addition, in step S7508 in the clearing process for non-specific control (FIG. 110), the normal counter area 231, the open/close execution mode counter area 232, and the high frequency support mode counter area 233 may not be cleared to "0", and the calculation result storage area 234 may not be cleared to "0".

Thirty-second embodiment
In this embodiment, the processing configuration for monitoring information abnormalities in the main RAM 65 using a checksum is different from that of the 30th embodiment. The configuration that differs from the 30th embodiment will be described below. Note that the description of the same configuration as the 30th embodiment will basically be omitted.

Figure 111 is a flowchart showing the power outage information storage process in this embodiment, which is executed by the main CPU 63. The power outage information storage process is executed in step S6801 in the timer interrupt process (Figure 103). The processes in steps S7601 to S7613 in the power outage information storage process are executed in the main CPU 63 using a program for specific control and data for specific control.

Steps S7601 to S7608 in the power outage information storage process execute the same process as steps S6701 to S6708 in the power outage information storage process (FIG. 101) in the 30th embodiment. If a power outage is identified, a positive determination is made in step S7608 and power outage processing in steps S7609 to S7613 is executed.

Specifically, first, the power failure flag provided in the work area 221 for specific control is set to "1" (step S7609). As a result, if the power failure process is executed normally and the information is stored and maintained normally in the main RAM 65, the power failure flag in the work area 221 for specific control will be set to "1" when the supply of operating power to the main CPU 63 is resumed again.

Then, the checksums are calculated for the specific control work area 221 and the specific control stack area 222 (step S7610). In this case, the storage areas in the specific control work area 221 and the specific control stack area 222 that are the objects of calculation when calculating the specific control checksum are the same as the storage areas in the specific control work area 221 and the specific control stack area 222 that are the objects of calculation of the specific control checksum in step S7701 of the checksum monitoring process (FIG. 112) described later. In addition, the storage areas that are the objects of calculation when calculating the specific control checksum include an area in the specific control work area 221 where information on the setting value indicating the setting state of the pachinko machine 10 is set (specifically, a setting value counter). Then, the calculated specific control checksum is stored in a storage area for storing the specific control checksum in the specific control work area 221, which is excluded from the objects of calculation of the specific control checksum.

Then, a checksum is calculated for the work area 223 for non-specific control and the stack area 224 for non-specific control (step S7611). In this case, the storage areas in the work area 223 for non-specific control and the stack area 224 for non-specific control that are the objects of calculation when calculating the checksum for non-specific control are the same as the storage areas in the work area 223 for non-specific control and the stack area 224 for non-specific control that are the objects of calculation of the checksum for non-specific control in step S7706 of the checksum monitoring process (FIG. 112) described below. Then, the calculated checksum for non-specific control is stored in a storage area for storing the checksum for non-specific control in the work area 221 for specific control, which is excluded from the objects of calculation of the checksum for specific control.

Then, all output port information in the register of the main CPU 63 is set to "0" (step S7612), and access to the main RAM 65 is prohibited (step S7613). Then, the infinite loop continues until the power is completely cut off and processing can no longer be executed.

Next, the checksum monitoring process executed by the main CPU 63 will be described with reference to the flowchart in FIG. 112. Note that the checksum monitoring process is executed in place of steps S6604 to S6606 in the main processing (FIG. 100). Also, the processes in steps S7701 to S7711 in the checksum monitoring process are executed by the main CPU 63 using a program for specific control and data for specific control.

First, a checksum for specific control is calculated for the work area 221 for specific control and the stack area 222 for specific control (step S7701). The method of calculating the checksum for specific control is the same as step S7610 in the power outage information storage process (FIG. 111). Then, the checksum for specific control calculated and stored in the work area 221 for specific control in step S7610 of the power outage process executed immediately before the supply of operating power to the MPU 62 was stopped is read from the work area 221 for specific control, and the read checksum for specific control is compared with the checksum for specific control calculated in step S7701 (step S7702). Then, it is determined whether the checksums for specific control match (step S7703).

If the checksums for specific control do not match (step S7703: NO), a clear process is performed on the work area 221 for specific control (step S7704). In this clear process, the work area 221 for specific control is cleared to "0" and an initial setting is performed, except for the area in the work area 221 for specific control in which the setting value information indicating the setting state of the pachinko machine 10 is set (specifically, the setting value counter). As a result, the area indicating whether the winning/losing lottery mode is a high probability mode or not is cleared to "0", so that the winning/losing lottery mode becomes a low probability mode regardless of the winning/losing lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. In addition, the game round is not being executed, and the open/close execution mode is not being executed, and further, the normal map display unit 38a is not displayed in a variable manner and the normal power role 34a is in a closed state. In addition, the reserved storage area 65a and the regular power reserved area 65c provided in the work area 221 for specific control are also cleared to "0", so that the reserved information for the special map display unit 37a is erased and the reserved information for the regular map display unit 38a is erased. In addition, in this clearing process, various registers of the main CPU 63 are also cleared to "0" and then initial settings are performed. In addition, the stack area 222 for specific control is cleared to "0" and initial settings are performed (step S7705).

If the determination in step S7703 is affirmative, or if the processing in step S7705 is executed, a checksum for non-specific control is calculated for the work area 223 for non-specific control and the stack area 224 for non-specific control (step S7706). The method of calculating the checksum for non-specific control is the same as that in step S7611 in the power failure information storage processing (FIG. 111). Then, the checksum for non-specific control calculated in step S7611 of the power failure processing executed immediately before the supply of operating power to the MPU 62 was stopped and stored in the work area 221 for specific control is read from the work area 221 for specific control, and the read checksum for non-specific control is compared with the checksum for non-specific control calculated in step S7706 (step S7707). Then, it is determined whether or not the checksums for non-specific control match (step S7708).

If the checksums for non-specific control do not match (step S7708: NO), the flag register information of the main CPU 63 is saved to the stack area 222 for specific control by a push command as "PUSH PSW" (step S7709). The flag register includes a carry flag, a zero flag, a P/V flag, a sign flag, and a half carry flag, and the information in the flag register changes depending on the execution results of an arithmetic instruction, a rotate instruction, an input/output instruction, and the like. By saving such flag register information before the program of a subroutine corresponding to the clear process for non-specific control is started, it is possible to save the flag register information in the state before it is changed after the subroutine is called or the subroutine is started to the stack area 222 for specific control. The amount of information in the flag register is 1 byte.

Then, the subroutine program corresponding to the non-specific control clear processing set in the non-specific control program is read out, thereby starting the non-specific control clear processing (step S7710). In this case, information for identifying the return address of the checksum monitoring processing after the non-specific control clear processing is executed is written to the specific control stack area 222 by a push command. Then, when the non-specific control clear processing is completed, information for identifying the return address is read out by a pop command, and the program returns to the checksum monitoring processing program indicated by the return address.

When returning to the program for the abnormality clear process after the execution of the non-specific control clear process, the flag register information saved in the specific control stack area 222 in step S7709 is restored to the flag register of the main CPU 63 by a pop command as "POP PSW" (step S7711). This causes the flag register information of the main CPU 63 to return to the information at the time step S7709 was executed. In other words, the flag register information of the main CPU 63 returns to the information for executing specific control.

Figure 113 is a flowchart showing the clearing process for non-specific control. Note that the processes in steps S7801 to S7818 in the clearing process for non-specific control are executed in the main CPU 63 using the program for non-specific control and data for non-specific control.

Steps S7801 to S7807 in the clearing process for non-specific control execute the same processing as steps S7501 to S7507 in the clearing process for non-specific control in the 31st embodiment (Figure 110).

After that, a partial clear process of the work area 223 for non-specific control is executed (step S7808). In this partial clear process, the memory areas of the work area 223 for non-specific control are cleared to "0" except for the memory areas in which the information of the various registers of the main CPU 63 used in the process corresponding to the specific control is saved. Specifically, among the memory areas of the work area 223 for non-specific control, the WA buffer, BC buffer, DE buffer, HL buffer, IX buffer, and IY buffer are not cleared to "0", while the memory areas other than these various buffers are cleared to "0".

In this case, the normal counter area 231, the open/close execution mode counter area 232, the high frequency support mode counter area 233, the calculation result storage area 234, and the management start flag are all cleared to "0". This makes it possible to eliminate information abnormalities in the work area 223 for non-specific control. Also, by not clearing to "0" the storage area in which the information of the various registers of the main CPU 63 used in the processing corresponding to specific control is saved, it becomes possible to restore the information used in the processing corresponding to specific control to the various registers of the main CPU 63 when the processing corresponding to non-specific control ends and returns to the processing corresponding to specific control.

After that, the initial setting process is executed (step S7809). In the initial setting process, initial settings are made to the storage areas in the non-specific control work area 223 that were cleared to "0" in step S7808.

After that, a partial clear process of the stack area 224 for non-specific control is executed (step S7810). In this partial clear process, among the storage areas of the stack area 224 for non-specific control, the storage areas other than the storage area in which the return address information of the checksum monitoring process (FIG. 112) after the clear process for non-specific control is completed are cleared to "0". This makes it possible to resolve the information anomaly in the stack area 224 for non-specific control while preventing the return address information of the checksum monitoring process (FIG. 112) after the clear process for non-specific control is completed from being erased.

After that, the initial setting process is executed (step S7811). In the initial setting process, initial settings are made to the memory area in the non-specific control stack area 224 that was cleared to "0" in step S7810.

Then, the processing of steps S7812 to S7818 is executed. These steps S7812 to S7818 are the same as steps S7510 to S7516 in the clearing process for non-specific control in the 31st embodiment (Figure 110).

According to the above configuration, the checksums for the work area 221 for specific control and the stack area 222 for specific control, and the checksums for the work area 223 for non-specific control and the stack area 224 for non-specific control are calculated separately. This makes it possible to identify information anomalies separately for the memory area corresponding to specific control in the main RAM 65 and the memory area corresponding to non-specific control in the main RAM 65.

If an abnormality is found in the checksum for specific control, a "0" clear process and initial setting process are performed on the work area 221 for specific control and the stack area 222 for specific control, and if an abnormality is found in the checksum for non-specific control, a "0" clear process and initial setting process are performed on the work area 223 for non-specific control and the stack area 224 for non-specific control. This makes it possible to narrow down the areas for which the "0" clear process and initial setting process are performed to those areas where a checksum abnormality has been identified.

The process of clearing the work area 221 for specific control and the stack area 222 for specific control to "0" and the process of initializing are executed by the process corresponding to the specific control, and the process of clearing the work area 223 for non-specific control to "0" and the process of initializing are executed by the process corresponding to the non-specific control. This makes it possible to treat the work area 221 for specific control and the stack area 222 for specific control as dedicated memory areas for the process corresponding to the specific control, and to treat the work area 223 for non-specific control as a dedicated memory area for the process corresponding to the non-specific control, even with regard to the process of clearing to "0" and the initial setting process.

In step S7808 in the clearing process for non-specific control (FIG. 113), the management start flag is cleared to "0", but the management start flag may not be cleared to "0". In addition, in step S7808 in the clearing process for non-specific control (FIG. 113), the normal counter area 231, the open/close execution mode counter area 232, and the high frequency support mode counter area 233 may not be cleared to "0", and the calculation result storage area 234 may not be cleared to "0".

Thirty-third embodiment
In this embodiment, the processing configuration executed by the main CPU 63 is different from that of the fifteenth embodiment. The configuration that differs from the fifteenth embodiment will be described below. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 114 is a flowchart showing the main processing in this embodiment that is executed by the main CPU 63. Note that the processing of steps S7901 to S7924 in the main processing is executed using a program for specific control and data for specific control in the main CPU 63.

First, the power-on initial setting process is executed (step S7901). In the power-on initial setting process, for example, the main process is started and then a predetermined wait time (specifically, one second) elapses before proceeding to the next process. During this predetermined wait period, the operation start and initial setting of the pattern display device 41 are completed. In addition, access to the main RAM 65 is permitted.

Then, the internal function register setting process is executed (step S7902). In the internal function register setting process, the interrupt period of the first timer interrupt process (FIG. 117), which is a process that periodically interrupts the main process and is started, is set to the first interrupt period (specifically, 4 milliseconds), and the interrupt period of the second timer interrupt process (FIG. 123), which is a process that periodically interrupts the main process and is started, is set to the second interrupt period (specifically, 2 milliseconds), which is shorter than the first interrupt period.

In other words, in this embodiment, there are first timer interrupt processing and second timer interrupt processing so that the interrupt period is relatively long and short as timer interrupt processing. Both the first timer interrupt processing and the second timer interrupt processing are started by interrupting the main processing. Also, the second timer interrupt processing is started by interrupting the first timer interrupt processing. On the other hand, the first timer interrupt processing is not started by interrupting the second timer interrupt processing. Also, if both the first timer interrupt processing and the second timer interrupt processing are not being executed and both the first interrupt period and the second interrupt period have elapsed, the second timer interrupt processing is started first regardless of the order in which the periods have elapsed. In this respect, it can be said that the second timer interrupt processing is started with priority over the first timer interrupt processing.

In the internal function register setting process, the first interrupt period of the first timer interrupt process is set in a specified register of the main CPU 63, and the second interrupt period of the second timer interrupt process is set in a specific register of the main CPU 63. In addition to setting the first and second interrupt periods, the internal function register setting process also executes processes for setting the numerical ranges of various counters, such as the numerical range of the jackpot random number counter C1.

Then, the start-up processing in progress flag provided in the work area 221 for specific control is set to "1" (step S7903). The start-up processing in progress flag is a flag for the main CPU 63 to identify a situation in which the first timer interrupt processing should be ended without executing the various processes set in the first timer interrupt processing even if the first timer interrupt processing is started. By setting the start-up processing in progress flag to "1", even if the first timer interrupt processing is started, the various processes set in the first timer interrupt processing will not be executed and the first timer interrupt processing will be ended.

After that, interrupt permission is set (step S7904). As a result, the first timer interrupt process (FIG. 117) is started by interrupting at the first interrupt period, and the second timer interrupt process (FIG. 123) is started by interrupting at the second interrupt period. However, since the start-up process in progress flag was set to "1" in step S7903, even if the first timer interrupt process is started, the first timer interrupt process ends without executing the various processes set in the first timer interrupt process.

Then, it is determined whether the reset button 68c has been pressed (step S7905). In other words, it is determined whether the power to the pachinko machine 10 has been turned on and the supply of operating power to the MPU 62 has started while the reset button 68c has been pressed. In this embodiment, the main control device 60 is provided with a setting key insertion section 68a and a reset button 68c, but is not provided with an update button 68b. Also, the main control device 60 is provided with first to fourth notification display devices 201 to 204, as in the 11th embodiment, instead of first to third notification display devices 69a to 69c.

If the reset button 68c is not pressed (step S7905: NO), it is determined whether the power outage flag provided in the work area 221 for specific control is set to "1" (step S7906). The power outage flag is set to "1" when power outage processing is executed in the power outage information storage processing (step S8202) of the first timer interrupt processing (FIG. 117) described later. The power outage flag is a flag that allows the main CPU 63 to determine whether power outage processing was performed appropriately the previous time the power was shut off.

If the power outage flag is set to "1" (step S7906: YES), a checksum is calculated for the work area 221 for specific control and the stack area 222 for specific control (step S7907). The method of calculating the checksum is arbitrary, but the calculation method is the same as the calculation method used when the checksum is calculated in the power outage processing in the power outage information storage processing (step S8202) of the first timer interrupt processing (FIG. 117) described below. The checksum calculated in the power outage processing is stored in the work area 221 for specific control, but the memory area of the work area 221 for specific control in which this checksum is stored is excluded from the memory areas that are the subject of calculation when the checksum is calculated.

In other words, when the checksum is calculated, the storage area to be calculated, which is a part of the storage area in the work area 221 for specific control and the stack area 222 for specific control, is the storage area to be calculated. This storage area to be calculated is a storage area in which information is not basically rewritten if the supply of power such as backup power to the work area 221 for specific control and the stack area 222 for specific control is continued from the time the checksum is calculated in the power failure processing when the supply of operating power to the MPU 62 is stopped until the supply of operating power to the MPU 62 is resumed and the processing of step S7907 is executed. Therefore, if the information in the work area 221 for specific control and the stack area 222 for specific control has not been changed from the time the supply of operating power to the MPU 62 is stopped until the supply of operating power to the MPU 62 is resumed, the checksum for the work area 221 for specific control and the stack area 222 for specific control is the same as that immediately before the supply of operating power to the MPU 62 is stopped. The storage areas that are the objects of calculation when calculating this checksum include an area (specifically, a setting value counter) in which setting value information indicating the setting state of the pachinko machine 10 is set in the work area 221 for specific control. Note that the work area 223 for non-specific control and the stack area 224 for non-specific control are not included in the calculation of the checksum.

Then, the checksums for the work area 221 for specific control and the stack area 222 for specific control that were calculated and stored in the work area 221 for specific control during the power outage processing executed immediately before the supply of operating power to the MPU 62 was stopped are read from the work area 221 for specific control, and the read checksums are compared with the checksum calculated in step S7907 (step S7908). Then, it is determined whether the checksums match (step S7909).

If a negative judgment is made in step S7906 or step S7909, that is, if the power failure flag is not set to "1" or the checksum does not match, the game stop flag provided in the work area 221 for specific control is set to "1" (step S7910). The game stop flag is a flag for the master CPU 63 to specify whether or not a positive judgment is made in step S8207 in the first timer interrupt processing (FIG. 117) described later and the processing of steps S8208 to S8221 is not executed, that is, whether or not the execution of the processing for progressing the game should be stopped. By setting the game stop flag to "1", a positive judgment is made in step S8207 of the first timer interrupt processing (FIG. 117) described later, and the processing of steps S8208 to S8221 is not executed. As a result, if the power outage flag is not set to "1" because power outage processing was not performed properly the previous time the power was cut off, game progress is stopped, and if the checksums do not match for at least one of the work area 221 for specific control and the stack area 222 for specific control because the information storage state has changed since the previous power outage, game progress is stopped.

In this case, the memory area that is the subject of calculation when calculating the checksum includes an area (specifically, a setting value counter) in which setting value information indicating the setting state of the pachinko machine 10 is set in the work area 221 for specific control as described above. Therefore, if an abnormality in the setting value occurs after the previous power outage, the checksum will not match, and the progress of the game will be halted.

On the other hand, even if the game stop flag is set to "1", steps S8202 to S8206 in the first timer interrupt process (Fig. 117) are executed. Therefore, even if the game progress is stopped, power outage monitoring is executed, the hit random number counter C1, the big win type counter C2, the reach random number counter C3, and the random number initial value counter CINI are updated, and further, fraud detection is executed.

Then, an abnormality command indicating that an abnormality occurred in the power failure flag or checksum at the start of the supply of operating power is sent to the sound and light emission control device 81 (step S7911). By receiving the abnormality command, the sound and light emission control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the information abnormality at the start of the supply of operating power, and causes the speaker unit 54 to output a voice saying "Please change the settings." In addition, a text image saying "Please change the settings" is displayed on the pattern display device 41. These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, even if the supply of operating power to the pachinko machine 10 is temporarily stopped, the above notification may be configured to continue when the supply of operating power to the pachinko machine 10 is resumed until the setting value update process (step S7918) is executed.

When the manager of the gaming hall confirms the above notification while the progress of the game is stopped, he or she will temporarily stop the supply of operating power to the pachinko machine 10, and then perform an operation to execute the setting value update process (step S7918) when the supply of operating power to the pachinko machine 10 is resumed. This makes it possible to set new setting values in the setting value update process (step S7918) if an abnormality occurs with the power outage flag or checksum when the supply of operating power begins.

In particular, the memory area that is the subject of calculation when calculating the checksum includes an area (specifically, a setting value counter) in which setting value information indicating the setting state of the pachinko machine 10 is set in the work area 221 for specific control as described above, so if an abnormality occurs in the checksum, there is a possibility that an abnormality has occurred in the setting value. In response to this, if an abnormality occurs with the checksum as described above, execution of a setting value update process (step S7918) is prompted, making it possible to prevent gameplay from being played with the abnormal setting value.

If the power failure flag is set to "1" and the checksum is normal (steps S7906 and S7909: YES), it is determined whether the setting key insertion unit 68a has been turned on using the setting key (step S7912), and it is determined whether the front door frame 14 is open relative to the inner frame 13 and the gaming machine main body 12 is open relative to the outer frame 11 (step S7913). The front door open sensor 95 is used to detect whether the front door frame 14 is open relative to the inner frame 13, as in the 30th embodiment, and the main body open sensor 96 is used to detect whether the gaming machine main body 12 is open relative to the outer frame 11, as in the 30th embodiment. If the setting key insertion section 68a is turned on using the setting key (step S7912: YES), and further, the front door frame 14 is open relative to the inner frame 13 and the gaming machine main body 12 is open relative to the outer frame 11 (step S7913: YES), a setting confirmation process is executed (step S7914). In the setting confirmation process, the first to fourth notification display devices 201 to 204, which are used to display various parameters that are the management results of the gaming history, execute a process to display a message indicating that the current setting value of the pachinko machine 10 is being confirmed and a message indicating the current setting value of the pachinko machine 10.

Figure 115 is a flowchart showing the setting confirmation process. Note that the processing of steps S8001 to S8003 in the setting confirmation process is executed using a program for specific control and data for specific control in the main CPU 63.

First, the setting confirmation display flag provided in the work area 221 for specific control is set to "1" (step S8001). The setting confirmation display flag is a flag for the main CPU 63 to identify that the current setting value of the pachinko machine 10 is being confirmed. By setting the setting confirmation display flag to "1", corresponding display control is performed on the first to fourth notification display devices 201 to 204 in the second timer interrupt process (FIG. 123) described below. As a result, the first to fourth notification display devices 201 to 204 display an indication that the current setting value of the pachinko machine 10 is being confirmed and an indication of the current setting value of the pachinko machine 10 is displayed.

Then, it is determined whether the setting key insertion unit 68a has been turned OFF using the setting key (step S8002). In this case, it may be configured to determine whether the setting key insertion unit 68a has switched from an ON state to an OFF state, or to determine whether the setting key insertion unit 68a is in an OFF state. If the setting key insertion unit 68a has not been turned OFF (step S8002: NO), the process of step S8002 is repeated.

If the setting key insertion section 68a has been turned OFF (step S8002: YES), the setting confirmation display flag in the specific control work area 221 is cleared to "0" (step S8003). This cancels the state in which the first to fourth notification display devices 201 to 204 display the indication that the current setting value of the pachinko machine 10 is being confirmed and the display showing the current setting value of the pachinko machine 10. In this case, the first to fourth notification display devices 201 to 204 start displaying the results of the game history management.

As described above, in this embodiment, the power to the pachinko machine 10 is turned on with the setting key insertion section 68a turned on by the setting key without pressing the reset button 68c. When the supply of operating power to the main CPU 63 starts and the main processing starts, the reset button 68c is not pressed and the setting key insertion section 68a is turned on, and the setting confirmation process is executed in a state in which processing is being executed when the supply of operating power starts, which is the state before the processing that enables the game to progress in the main processing is executed. This makes it possible to check the setting values when no game is being played.

Assuming that the setting value is checked while the game is continuing, for example, if the setting value is checked during the execution of a game round, there is a risk that the transition to the open/close execution mode will occur while the setting value is being checked. In this case, even though the open/close execution mode has started, it may not be possible to launch the game ball toward the special electric winning device 32. Also, if the setting value is checked during the execution of the open/close execution mode, the open/close execution mode will proceed while the setting value is being checked, so in this case too, there is a risk that the game ball will not be able to be launched toward the special electric winning device 32.

Assuming that the game progress is stopped when the setting value is confirmed, if the confirmation of the setting value is started while the game is being played, the process for stopping the game progress midway may become complicated. For example, if the confirmation of the setting value is started during the execution of a game round and the game progress is to be stopped midway, a process for stopping the game round midway is required. In this case, if the display of the pattern change in the pattern display device 41 is stopped midway when the confirmation of the setting value is started, and the display of the pattern change in the pattern display device 41 is resumed when the confirmation of the setting value is completed, a process that is that much more complicated is required. Also, for example, if the confirmation of the setting value is started during the execution of the opening and closing execution mode and the game progress is to be stopped midway, a process for stopping the opening and closing execution mode midway is required. Also, if the confirmation of the setting value is started during the execution of the display of the pattern change in the normal picture display unit 38a and the game progress is to be stopped midway, a process for stopping the display of the pattern change midway is required. In addition, if the confirmation of the setting value is started during the execution of the open execution state of the normal power role 34a and the progress of the game is to be stopped midway, a process is required to stop the open execution state midway. On the other hand, a configuration is also possible in which the confirmation of the setting value is performed after waiting until all games are completed. In this case, it becomes necessary to wait until a situation in which none of the game rounds, the open/close execution mode, the display of the changing patterns in the normal picture display section 38a, and the open execution state of the normal power role 34a are being executed, and there is a risk that the waiting time until the confirmation of the setting value can be started will be long.

In contrast to this, the setting confirmation process is executed in a state where the process at the start of the supply of operating power is being executed, which is the state before the process that enables game progress is executed in the main process that is executed when the supply of operating power to the main CPU 63 is started, and therefore the setting value is confirmed in a state where game progress has already been stopped. This makes it possible to avoid checking the setting value while game progress is in progress, and there is no need to stop game progress midway when checking the setting value, or to wait until game progress is stopped to check the setting value. This makes it possible to properly check the setting value.

Returning to the explanation of the main process (FIG. 114), if the reset button 68c is pressed (step S7905: YES), a RAM clear process is executed (step S7915). In the RAM clear process, the specific control work area 221 is cleared to "0" except for the area (specifically, the setting value counter) in which the setting value information indicating the setting state of the pachinko machine 10 is set in the specific control work area 221, and the initial setting is executed. As a result, the area indicating whether the winning/losing lottery mode is the high probability mode or not is cleared to "0", so that the winning/losing lottery mode becomes the low probability mode regardless of the winning/losing lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. In addition, the game round is not being executed, and the open/close execution mode is not being executed, and further, the normal map display unit 38a is not displayed in a variable manner and the normal power role 34a is in a closed state. In addition, the reserved storage area 65a and the regular power reserved area 65c provided in the work area 221 for specific control are also cleared to "0", so that the reserved information for the special map display unit 37a and the reserved information for the regular map display unit 38a are erased. In addition, in the RAM clear process, the stack area 222 for specific control is cleared to "0" and initial settings are performed. In addition, in the RAM clear process, various registers of the main CPU 63 are also cleared to "0" and then initial settings are performed. In this initial setting, the same process as the internal function register setting process (step S7902) in step S7902 is performed.

On the other hand, the RAM clearing process does not clear the work area 223 for non-specific control and the stack area 224 for non-specific control to "0". This makes it possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" by the clearing operation performed by the manager of the amusement hall.

Then, it is determined whether the setting key insertion unit 68a has been turned on using the setting key (step S7916), and whether the front door frame 14 is open relative to the inner frame 13 and the gaming machine main body 12 is open relative to the outer frame 11 (step S7917). The front door open sensor 95 is used to detect whether the front door frame 14 is open relative to the inner frame 13, as in the 30th embodiment, and the main body open sensor 96 is used to detect whether the gaming machine main body 12 is open relative to the outer frame 11, as in the 30th embodiment. If the setting key insertion unit 68a has been turned on using the setting key (step S7916: YES), and further, the front door frame 14 is open relative to the inner frame 13 and the gaming machine main body 12 is open relative to the outer frame 11 (step S7917: YES), the setting value update process is executed (step S7918).

Figure 116 is a flowchart showing the setting value update process. Note that the processing of steps S8101 to S8107 in the setting value update process is executed using a program for specific control and data for specific control in the main CPU 63.

First, the setting update display flag provided in the work area 221 for specific control is set to "1" (step S8101). The setting update display flag is a flag for the main CPU 63 to identify that the setting values of the pachinko machine 10 are being updated. By setting the setting update display flag to "1", corresponding display control is performed on the first to fourth alert display devices 201 to 204 in the second timer interrupt process (FIG. 123) described below. As a result, the first to fourth alert display devices 201 to 204 display an indication that the setting values of the pachinko machine 10 are being updated and a display showing the current setting values of the pachinko machine 10.

After that, it is determined whether the value of the setting value counter provided in the work area 221 for specific control is equal to or greater than 1, which corresponds to "setting 1," and equal to or less than 6, which corresponds to "setting 6" (step S8102). If the value of the setting value counter is "0" or equal to or greater than 7, a negative determination is made in step S8102, and the setting value counter is set to "1" (step S8103). As a result, the setting value of the pachinko machine 10 becomes "setting 1."

If a positive determination is made in step S8102 or if the processing of step S8103 is executed, it is determined whether the setting key insertion unit 68a has been turned OFF using the setting key (step S8104). In this case, the configuration may be such that it is determined whether the setting key insertion unit 68a has switched from an ON state to an OFF state, or it may be such that it is determined whether the setting key insertion unit 68a is in an OFF state.

If the setting key insertion section 68a is not turned off (step S8104: NO), and if the reset button 68c is pressed (step S8105: YES), the value of the setting value counter in the work area 221 for specific control is incremented by 1 (step S8106). As a result, the setting value is updated to the next higher setting value each time the reset button 68c is pressed. If the reset button 68c is not pressed (step S8105: NO) or the setting value counter is incremented by 1, the process returns to step S8102. However, if it is determined in step S8102 that the setting value counter is 7 or greater, the setting value counter is set to "1" in step S8103. As a result, if the reset button 68c is pressed once in the "setting 6" situation, the setting returns to "setting 1."

If the setting key insertion section 68a has been turned OFF (step S8104: YES), the setting update display flag in the work area 221 for specific control is cleared to "0" (step S8107). This cancels the state in which the first to fourth notification display devices 201 to 204 display an indication that the setting values of the pachinko machine 10 are being updated and the current setting values of the pachinko machine 10. In this case, the first to fourth notification display devices 201 to 204 start displaying the results of the game history management.

As described above, in this embodiment, when the power to the pachinko machine 10 is turned on while the reset button 68c is pressed, the supply of operating power to the main CPU 63 is started and the main processing is started, and the reset button 68c is pressed, and the RAM clear process (step S7915) is executed regardless of whether the setting key insertion section 68a is turned on or not. As a result, the operation of turning on the power to the pachinko machine 10 while pressing the reset button 68c is uniquely linked to the execution of the RAM clear process (step S7915), and the operation for causing the RAM clear process (step S7915) can be made easy to understand for the manager of the amusement hall.

Even if the RAM clear process (step S7915) is executed, the setting value counter in the work area 221 for specific control is not cleared to "0" and the information in the setting value counter is not changed. This makes it possible to prevent the setting value from being changed even if the RAM clear process (step S7915) is executed.

Not only is the power to the pachinko machine 10 turned on while pressing the reset button 68c, but also the setting value update process (step S7918) is executed based on the power being turned on while the setting key insertion section 68a is turned on with the setting key. As already explained, the setting confirmation process (step S7914) is executed based on the power being turned on while the setting key insertion section 68a is turned on with the setting key without pressing the reset button 68c. This makes it possible to make the ON operation of the setting key insertion section 68a a common operation for executing processing related to the setting value. This makes it possible to make the operation content for generating processing related to the setting value easy to understand for the manager of the game hall.

In addition, when the power of the pachinko machine 10 is turned on while the setting key insertion section 68a is turned on by the setting key, if the reset button 68c is not pressed, a setting confirmation process is executed, and if the reset button 68c is pressed, a setting value update process is executed. This makes it possible to differentiate between the setting confirmation process and the setting value update process, depending on whether the reset button 68c is pressed or not. This makes it possible to make the operation contents for executing the desired process between the setting confirmation process and the setting value update process easy to understand for the manager of the amusement hall. Also, by making the operation contents for executing the setting value update process more than the setting confirmation process, it becomes possible to make it particularly difficult to carry out fraudulent acts of setting value update processing.

Returning to the explanation of the main processing (FIG. 114), if the processing of step S7911 is executed, if a negative judgment is made in step S7912 or step S7913, if the processing of step S7914 is executed, if a negative judgment is made in step S7916 or step S7917, or if the processing of step S7918 is executed, the start-up processing in progress flag in the work area 221 for specific control is cleared to "0" (step S7919). By clearing the start-up processing in progress flag to "0", the state in which various processes set in the first timer interrupt processing are not executed even if the first timer interrupt processing is started is released. Note that in step S7919, the power outage flag in the work area 221 for specific control is also cleared to "0".

Then, a return command is sent to the sound and light control device 81 (step S7920). The return command includes information indicating the number of pending information for the special chart display unit 37a, information indicating the current win/lose lottery mode, information indicating the current support mode, information indicating whether the open/close execution mode is in progress, and information indicating whether a game round is in progress. These pieces of information are set based on the information stored in the work area 221 for specific control. By receiving the return command, the sound and light control device 81 sets the display contents of the pattern display device 41, the light emission contents of the display light-emitting unit 53, and the sound output contents of the speaker unit 54 to contents corresponding to the various information set in the return command.

Here, when checking the setting values of the pachinko machine 10, it is necessary to turn on the power of the pachinko machine 10 while turning on the setting key insertion section 68a with the setting key. In this case, if it becomes necessary to check the setting values during the execution of a game round, for example, the power of the pachinko machine 10 is turned off during the execution of the game round, and then the power of the pachinko machine 10 is turned on while turning on the setting key insertion section 68a with the setting key. In this case, since backup power is not supplied to the RAM provided in the sound and light emission control device 81, when the power of the pachinko machine 10 is turned off, the information for controlling the presentation for the game round in the RAM of the sound and light emission control device 81 is erased. In contrast, because backup power is supplied to the main RAM 65 and the clearing process of the main RAM 65 is not executed when the setting value is confirmed, if the power of the pachinko machine 10 is turned OFF during the execution of a game round and then the power of the pachinko machine 10 is turned ON while the setting key insertion section 68a is turned ON with the setting key, the display of the changing patterns will resume on the special pattern display section 37a after the setting confirmation process is executed, so that a situation will occur in which the pattern display device 41 does not display the changing patterns even though the special pattern display section 37a is displaying the changing patterns.

In response to this, a return command is sent to the audio and light emitting control device 81 after the setting confirmation process is completed, and the return command includes information indicating whether or not a game round is in progress. When the audio and light emitting control device 81 receives the return command, it starts displaying the changing patterns on the pattern display device 41. This makes it possible to prevent a situation in which the pattern display device 41 does not display the changing patterns even though the special pattern display unit 37a is displaying the changing patterns. This display of the changing patterns is performed at a relatively fast speed so that each of the patterns being displayed is indistinguishable or difficult to distinguish for the player. Furthermore, the return command does not include the results of the win/loss determination process and the allocation determination process for the game round to be resumed, and does not include information indicating the end timing of the game round to be resumed. Therefore, when the sound and light emission control device 81 starts the display of changing patterns on the pattern display device 41 based on a return command, if the game turn to be resumed corresponds to a miss result, when a command indicating the start of the next game turn or a command to start a demo display on the pattern display device 41 is received, the sound and light emission control device 81 ends the display of changing patterns based on the return command and starts the display corresponding to the newly received command, and if the game turn to be resumed corresponds to a jackpot result, when an opening command indicating the start of the open/close execution mode is received, the sound and light emission control device 81 ends the display of changing patterns based on the return command and starts the opening performance.

In addition, if the return command includes information indicating that the opening and closing execution mode is currently being executed, the sound and light emission control device 81 causes the pattern display device 41 to start a display effect indicating that the opening and closing execution mode is in progress. This makes it possible for the player to recognize that the opening and closing execution mode is being executed.

Then, the process proceeds to the remaining process of steps S7921 to S7924. In other words, the main CPU 63 is configured to periodically execute the first timer interrupt process (FIG. 117) and the second timer interrupt process (FIG. 123), but there is a remaining time between one timer interrupt process and the next timer interrupt process. This remaining time varies depending on the completion time of each timer interrupt process, but this irregular time is used to repeatedly execute the remaining process of steps S7921 to S7924. In this respect, the remaining process of steps S7921 to S7924 can be said to be non-periodic process that is executed non-periodically. In steps S7921 to S7924, the same process is executed as steps S113 to S116 of the main process (FIG. 9) in the first embodiment.

Next, the first timer interrupt process executed by the main CPU 63 will be described with reference to the flowchart in FIG. 117. As already explained, the first timer interrupt process is periodically started at a 4 millisecond period, which is the first interrupt period. Also, the program corresponding to the first timer interrupt process is set in the program for specific control.

First, it is determined whether the start-up processing flag in the work area 221 for specific control is set to "1" (step S8201). As already explained, the start-up processing flag is set to "1" in step S7903 of the main processing (FIG. 114). Then, if the start-up processing flag is set to "1" (step S8201: YES), the first timer interrupt processing is terminated without executing the various processes of steps S8202 to S8221. As a result, even if the first timer interrupt processing and the second timer interrupt processing are permitted to be executed early when the supply of operating power to the pachinko machine 10 is started and the main processing (FIG. 114) is started, it is possible to prevent the various processes for controlling the progress of the game from being executed in the first timer interrupt processing until the process at the start of the supply of operating power is completed and the execution of the process for controlling the progress of the game is permitted.

As already explained, the startup processing flag is cleared to "0" in step S7919 when the processing at the start of the supply of operating power in the main processing (FIG. 114) is completed. In the first timer interrupt processing, if the startup processing flag is not set to "1" (step S8201: NO), the processing from step S8202 onwards is executed.

In steps S8202 to S8219 and S8221, the same processing as steps S3701 to S3719 of the timer interrupt processing (FIG. 69) in the above-mentioned 15th embodiment is executed. These processings are executed by the main CPU 63 using a program for specific control and data for specific control. In this case, as already explained, if it is determined in the main processing (FIG. 114) that the power failure flag is not set to "1" (step S7906: NO) or if it is determined that the checksums do not match (step S7909: NO), the game stop flag in the work area 221 for specific control is set to "1" (step S7910). If the game stop flag is set to "1", the first timer interrupt processing executes the processing of steps S8201 to S8206, but does not execute the processing of steps S8208 to S8221 by making a positive determination in step S8207. As a result, if the power outage flag is not set to "1" because power outage processing was not performed properly the previous time the power was cut off, game progress is stopped, and if the checksums do not match for at least one of the work area 221 for specific control and the stack area 222 for specific control because the information storage state has changed since the previous power outage, game progress is stopped. For example, if the processing of step S8212 is not executed, the launch of game balls is prohibited. Also, if the processing of step S8214 is not executed, the execution of game rounds and open/close execution mode is prohibited. Also, if the processing of step S8218 is not executed, the payout of game balls is prohibited.

However, even in such a situation where the game progress is stopped, power outage monitoring is performed in step S8202, and the winning random number counter C1, the big win type counter C2, the reach random number counter C3, and the random number initial value counter CINI are updated in steps S8203 and S8204, and further fraud detection is performed in step S8206.

In the first timer interrupt process, the setting monitoring process is executed in step S8220. FIG. 118 is a flowchart showing the setting monitoring process. Note that the processing in steps S8301 to S8303 in the setting monitoring process is executed using a program for specific control and data for specific control in the main CPU 63.

The setting value counter in the work area 221 for specific control is checked to determine whether the setting value of the pachinko machine 10 is normal or not (step S8301). Specifically, if the setting value set in the setting value counter is any of "Setting 1" to "Setting 6," it is determined to be normal, and if it is "0" or 7 or greater, it is determined to be abnormal.

If the set value is abnormal (step S8301: NO), the game stop flag in the work area 221 for specific control is set to "1" (step S8302), similar to step S7910 in the main process (Fig. 114). By setting the game stop flag to "1", a positive judgment is made in step S8207 of the first timer interrupt process (Fig. 117), resulting in a situation in which the processing of steps S8208 to S8221 is not executed. As a result, if it is determined that the set value is abnormal, the progress of the game is stopped. On the other hand, even if the game stop flag is set to "1", the processing of steps S8202 to S8206 in the first timer interrupt process (Fig. 117) is executed, so that even if the progress of the game is stopped, power outage monitoring is executed, and the winning random number counter C1, the big win type counter C2, the reach random number counter C3, and the random number initial value counter CINI are updated, and further fraud detection is executed.

Then, an abnormal command indicating that the setting value is abnormal is sent to the audio light-emitting control device 81 (step S8303). By receiving the abnormal command, the audio light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the abnormal setting value, and causes the speaker unit 54 to output a voice saying "Please change the setting." In addition, a text image saying "Please change the setting" is displayed on the pattern display device 41. These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, even if the supply of operating power to the pachinko machine 10 is temporarily stopped, the above notification may be configured to continue when the supply of operating power to the pachinko machine 10 is resumed until the setting value update process (step S7918) of the main process (FIG. 114) is executed.

When the manager of the gaming hall confirms the above notification while the game progress is stopped, he or she will temporarily stop the supply of operating power to the pachinko machine 10, and then perform an operation to execute the setting value update process (step S7918) when the supply of operating power to the pachinko machine 10 is resumed. This makes it possible to set new setting values in the setting value update process (step S7918) if a setting value abnormality occurs.

Here, the process of monitoring whether the set value is abnormal is executed by the first timer interrupt process (Fig. 117) which is periodically started. This makes it possible to monitor whether the set value is abnormal even when a game is being played. This makes it possible to prevent play from continuing even if the set value is abnormal. Also, monitoring whether the set value is abnormal is executed every time a monitoring trigger occurs. This makes it possible to increase the frequency of monitoring whether the set value is abnormal.

In the main process (FIG. 114), there is no process for monitoring whether the set value is normal. If the process for monitoring whether the set value is normal is set in the process at the start of the supply of operating power in the main process (FIG. 114), not only the power failure flag and the checksum are monitored but also the set value must be monitored to see if it is normal at the start of the supply of operating power, which increases the monitoring load. Furthermore, if it is determined that the set value is abnormal at the start of the supply of operating power, the RAM clear process (step S7915) and the set value update process (step S7918) are executed, the processing configuration becomes more complicated. In contrast, since the process for monitoring whether the set value is normal is not set in the main process (FIG. 114), it is possible to make the processing configuration of the process at the start of the supply of operating power suitable. Also, even if the process for monitoring whether the set value is normal is not set in the process at the start of the supply of operating power, the configuration is such that the setting monitoring process (step S8220) is executed in the first timer interrupt process (FIG. 117) as described above, so that it is possible to deal with the abnormality of the set value.

In the configuration in which the first timer interrupt processing is executed as described above, in this embodiment, as already explained, there is a second timer interrupt processing (FIG. 123) in addition to the first timer interrupt processing (FIG. 117) as a timer interrupt processing, and the second timer interrupt processing is started by interrupting the first timer interrupt processing even if the first timer interrupt processing is being executed. In this case, although not shown in the first timer interrupt processing, the timer interrupt processing is prohibited and permitted before and after each process of steps S8201 to S8221. For example, the timer interrupt processing is prohibited before executing the lottery random number update processing (step S8203), and the timer interrupt processing is permitted after executing the lottery random number update processing (step S8203). This makes it possible to prevent the second timer interrupt processing from interrupting and starting while the lottery random number update processing is being executed. In addition, the timer interrupt process is prohibited before the special chart special power control process (step S8214) is executed, and the timer interrupt process is permitted after the special chart special power control process (step S8214) is executed. This makes it possible to prevent the second timer interrupt process from interrupting and starting while the special chart special power control process is being executed.

Next, we will explain the configuration for controlling the display of various display units by the main CPU 63. Figure 119 is a block diagram for explaining the configuration for controlling the display of various display units by the main CPU 63.

The objects for which display control is performed by the main CPU 63 include the special chart display unit 37a, the special chart reserved display unit 37b, the regular chart display unit 38a, the regular chart reserved display unit 38b, and the first to fourth notification display devices 201 to 204. All of these are provided as segment display units in which multiple display segments made of LEDs are arranged. These segment display units are illuminated when data corresponding to the illuminated state (for example, data "1", which is one of the binary data values) is set, and are turned off when data corresponding to the unlit state (for example, data "0", which is the other of the binary data values) is set.

The main control board 61 is provided with a first display circuit 261 corresponding to the special chart display unit 37a, a second display circuit 262 corresponding to the special chart reserved display unit 37b, a third display circuit 263 corresponding to the normal chart display unit 38a, a fourth display circuit 264 corresponding to the normal chart reserved display unit 38b, and a fifth display circuit 265 corresponding to the first to fourth notification display devices 201 to 204. Note that in the eleventh embodiment, the main control board 61 is provided with the first to fourth display ICs 205 to 208 in one-to-one correspondence with the first to fourth notification display devices 201 to 204, but in this embodiment, these first to fourth display ICs 205 to 208 are not provided.

The first display circuit 261 provides data corresponding to the supplied display data to each of the multiple display segments of the special display unit 37a. As a result, each display segment of the special display unit 37a becomes lit or unlit in a manner corresponding to the display data provided to the first display circuit 261. In this case, the first display circuit 261 can store and hold the provided display data for a predetermined period (e.g., 16 milliseconds), but after the predetermined period has passed, the display data gradually approaches an all-zero state. Therefore, the display segments of the special display unit 37a that are lit by the display data provided to the first display circuit 261 gradually become unlit as the predetermined period has passed without new display data being provided to the first display circuit 261. In addition, due to this configuration, not only when the display content of the special display unit 37a is changed, but also when the display content of the special display unit 37a is not changed, the same display data as that of the previous display data output processing is supplied to the first display circuit 261.

The number of display segments provided in the special chart display unit 37a is eight. Therefore, eight bits of data are provided to the first display circuit 261 as display data for controlling the display of the special chart display unit 37a.

The second display circuit 262 provides data corresponding to the supplied display data to each of the multiple display segments of the special drawing reservation display unit 37b. As a result, each display segment of the special drawing reservation display unit 37b becomes lit or unlit in a manner corresponding to the display data provided to the second display circuit 262. In this case, the second display circuit 262 can store and hold the provided display data for a predetermined period (for example, 16 milliseconds), but after the predetermined period has passed, the display data gradually approaches an all-"0" state. Therefore, the display segments of the special drawing reservation display unit 37b that are lit by the display data provided to the second display circuit 262 gradually become unlit as the predetermined period has passed without new display data being provided to the second display circuit 262. In addition, due to this configuration, not only when the display content of the special drawing reservation display unit 37b is changed, but also when the display content of the special drawing reservation display unit 37b is not changed, the same display data as that of the previous display data output processing is supplied to the second display circuit 262.

The number of display segments provided in the special drawing reservation display section 37b is four. Therefore, four bits of data are provided to the second display circuit 262 as display data for controlling the display of the special drawing reservation display section 37b. However, since the display data is provided in 8-bit units, 8 bits of data are also provided when display data is provided to the second display circuit 262, but four bits of that are used as display data for controlling the display of the special drawing reservation display section 37b.

The third display circuit 263 provides data corresponding to the supplied display data to each of the multiple display segments of the general map display unit 38a. As a result, each display segment of the general map display unit 38a is illuminated or turned off in a manner corresponding to the display data provided to the third display circuit 263. In this case, the third display circuit 263 can store and hold the provided display data for a predetermined period (for example, 16 milliseconds), but after the predetermined period has passed, the display data gradually approaches an all-zero state. Therefore, the display segments of the general map display unit 38a that are illuminated by the display data provided to the third display circuit 263 gradually turn off as the predetermined period passes without new display data being provided to the third display circuit 263. In addition, due to this configuration, not only when the display content of the general map display unit 38a is changed, but also when the display content of the general map display unit 38a is not changed, the same display data as that of the previous display data output processing is supplied to the third display circuit 263.

The number of display segments provided in the general map display unit 38a is eight. Therefore, eight bits of data are provided to the third display circuit 263 as display data for controlling the display of the general map display unit 38a.

The fourth display circuit 264 provides data corresponding to the supplied display data to each of the multiple display segments of the regular map reserved display unit 38b. As a result, each display segment of the regular map reserved display unit 38b is illuminated or turned off in a manner corresponding to the display data provided to the fourth display circuit 264. In this case, the fourth display circuit 264 can store and hold the provided display data for a predetermined period (for example, 16 milliseconds), but after the predetermined period has passed, the display data gradually approaches an all-zero state. Therefore, the display segments of the regular map reserved display unit 38b that are illuminated by the display data provided to the fourth display circuit 264 gradually turn off as the predetermined period passes without new display data being provided to the fourth display circuit 264. In addition, due to this configuration, not only when the display content of the regular map reserved display unit 38b is changed, but also when the display content of the regular map reserved display unit 38b is not changed, the same display data as that of the previous display data output processing is supplied to the fourth display circuit 264.

The number of display segments provided in the regular map pending display section 38b is four. Therefore, four bits of data are provided to the fourth display circuit 264 as display data for controlling the display of the regular map pending display section 38b. However, since the display data is provided in 8-bit units, 8 bits of data are also provided when display data is provided to the fourth display circuit 264, but four of these bits are used as display data for controlling the display of the regular map pending display section 38b.

The fifth display circuit 265 provides data corresponding to the supplied display data to each of the multiple display segments provided on the first to fourth display devices 201 to 204. As a result, each display segment of the first to fourth display devices 201 to 204 is illuminated or turned off in a manner corresponding to the display data provided to the fifth display circuit 265. In this case, the fifth display circuit 265 can store and hold the provided display data for a predetermined period (e.g., 16 milliseconds), but after the predetermined period has passed, the display data gradually approaches an all-zero state. Therefore, the display segments of the first to fourth display devices 201 to 204 that are illuminated by the display data provided to the fifth display circuit 265 gradually turn off as the predetermined period passes without new display data being provided to the fifth display circuit 265. Furthermore, with this configuration, not only when the display contents of the first to fourth notification display devices 201 to 204 are changed, but also when the display contents of the first to fourth notification display devices 201 to 204 are not changed, the same display data as that of the previous display data output process is supplied to the fifth display circuit 265.

Each of the first to fourth alert display devices 201 to 204 has seven display segments. Display data is provided in 8-bit units. When the display data of the first to fourth alert display devices 201 to 204 is provided to the fifth display circuit 265, 7-bit display data corresponding to the first alert display device 201 is provided as 8-bit data, then 7-bit display data corresponding to the second alert display device 202 is provided as 8-bit data, then 7-bit display data corresponding to the third alert display device 203 is provided as 8-bit data, and finally 7-bit display data corresponding to the fourth alert display device 204 is provided as 8-bit data.

In a configuration in which the first to fifth display circuits 261-265 are provided as described above, the main CPU 63 supplies display data to the display IC 266. In other words, the display ICs 266 are not provided one-to-one with the first to fifth display circuits 261-265, but rather one display IC 266 is provided so that it is common to all of the first to fifth display circuits 261-265. When the main CPU 63 supplies display data to the display IC 266, it also supplies type data to the display IC 266 indicating which of the first to fifth display circuits 261-265 the display data corresponds to.

Regarding the electrical connection between the main CPU 63 and the display IC 266, in detail, the main CPU 63 and the display IC 266 are electrically connected using a type data signal line LN1, a type clock signal line LN2, a display data signal line LN3, and a display clock signal line LN4. All of these signal lines LN1 to LN4 are signal lines for transmitting signals from the main CPU 63 to the display IC 266 in one-way communication.

The category data is transmitted from the main CPU 63 to the display IC 266 by serial communication using the category data signal line LN1. In this case, the division of each bit of the category data by serial communication is indicated by the category clock signal transmitted from the main CPU 63 to the display IC 266 using the category clock signal line LN2. The category data is data indicating which of the first to fifth display circuits 261 to 265 the display data to be transmitted corresponds to. The category data is transmitted as 5-bit data consisting of the first to fifth bits. If the display data corresponds to the first display circuit 261, the first bit becomes HI level and the other bits become LOW level. If the display data corresponds to the second display circuit 262, the second bit becomes HI level and the other bits become LOW level. If the display data corresponds to the third display circuit 263, the third bit becomes HI level and the other bits become LOW level. If the display data corresponds to the fourth display circuit 264, the fourth bit becomes HI level and the other bits become LOW level. If the display data corresponds to the fifth display circuit 265, the fifth bit will be at a high level and the other bits will be at a low level.

Display data is transmitted by serial communication from the main CPU 63 to the display IC 266 using the display data signal line LN3. In this case, the division of each bit of the display data by serial communication is indicated by a display clock signal transmitted from the main CPU 63 to the display IC 266 using the display clock signal line LN4. The display data is transmitted in 8-bit units using the 1st to 8th bits.

In the second timer interrupt process (FIG. 123) described later, the main CPU 63 transmits display data corresponding to each of the first to fifth display circuits 261-265 to the display IC 266. In this case, in one processing round of the second timer interrupt process, display data is transmitted to one of the first to fifth display circuits 261-265, and the display circuits 261-265 to which the display data is transmitted are changed one by one each time a new processing round of the second timer interrupt process occurs in the order of the nth display circuit → the n+1th display circuit. In addition, in the second timer interrupt process in the processing round following the processing round in which display data corresponding to the fifth display circuit 265, which is the last in the order, is transmitted, display data corresponding to the first display circuit 261, which is the first in the above order, is transmitted. In addition, in the second timer interrupt process in which display data is sent to one of the first to fourth display circuits 261 to 264, only one 8-bit display data is sent, but in the second timer interrupt process in which display data is sent to the fifth display circuit 265, four 8-bit display data are sent corresponding to the number of the first to fourth notification display devices 201 to 204.

In the configuration in which the main CPU 63 transmits display data as described above, various memory areas referenced by the main CPU 63 to transmit display data are set in the work area 221 for specific control and the work area 223 for non-specific control. Figure 120(a) is an explanatory diagram for explaining the various buffers 271-275 provided in the work area 221 for specific control, and Figure 120(b) is an explanatory diagram for explaining the various memory areas 234, 276 provided in the work area 223 for non-specific control.

As shown in FIG. 120(a), the work area 221 for specific control is provided with a first display data buffer 271, a second display data buffer 272, a third display data buffer 273, a fourth display data buffer 274, and a fifth display data buffer 275.

The first display data buffer 271 stores display data to be supplied to the first display circuit 261. As already explained, the first display circuit 261 is provided in correspondence with the special display unit 37a, so the first display data buffer 271 stores display data for causing the special display unit 37a to perform a predetermined display. In this case, the display data is stored in the first display data buffer 271 in the display control process (step S8216) based on the contents of the special display control process (step S8214) in the first timer interrupt process (Fig. 117). In addition, when the second timer interrupt process (Fig. 123) for transmitting display data to the first display circuit 261 is processed, the display data stored in the first display data buffer 271 is transmitted to the display IC 266 not only when the display data stored in the first display data buffer 271 has been changed, but also when the display data has not been changed.

The second display data buffer 272 stores display data to be supplied to the second display circuit 262. As already explained, the second display circuit 262 is provided in correspondence with the special drawing reserved display unit 37b, so the second display data buffer 272 stores display data for causing the special drawing reserved display unit 37b to perform a predetermined display. In this case, the display data is stored in the second display data buffer 272 in the display control process (step S8216) based on the contents of the special drawing special power control process (step S8214) in the first timer interrupt process (FIG. 117). In addition, when the second timer interrupt process (FIG. 123) for transmitting display data to the second display circuit 262 is processed, the display data stored in the second display data buffer 272 is transmitted to the display IC 266 not only when the display data stored in the second display data buffer 272 has been changed, but also when the display data has not been changed.

The third display data buffer 273 stores display data to be supplied to the third display circuit 263. As already explained, the third display circuit 263 is provided in correspondence with the normal map display unit 38a, so the third display data buffer 273 stores display data for causing the normal map display unit 38a to perform a specified display. In this case, the display data is stored in the third display data buffer 273 in the display control process (step S8216) based on the contents of the normal map normal power control process (step S8215) in the first timer interrupt process (FIG. 117). In addition, when the second timer interrupt process (FIG. 123) that transmits display data to the third display circuit 263 is processed, the display data stored in the third display data buffer 273 is transmitted to the display IC 266 not only when the display data stored in the third display data buffer 273 has been changed, but also when the display data has not been changed.

The fourth display data buffer 274 stores display data to be supplied to the fourth display circuit 264. As already explained, the fourth display circuit 264 is provided in correspondence with the normal map reserve display unit 38b, so the fourth display data buffer 274 stores display data for causing the normal map reserve display unit 38b to perform a specified display. In this case, the display data is stored in the fourth display data buffer 274 in the display control process (step S8216) based on the contents of the normal map normal power control process (step S8215) in the first timer interrupt process (FIG. 117). In addition, when the second timer interrupt process (FIG. 123) that transmits display data to the fourth display circuit 264 is processed, the display data stored in the fourth display data buffer 274 is transmitted to the display IC 266 not only when the display data stored in the fourth display data buffer 274 has been changed, but also when the display data has not been changed.

The fifth display data buffer 275 stores display data to be supplied to the fifth display circuit 265. As already explained, the fifth display circuit 265 is provided corresponding to the first to fourth alarm display devices 201 to 204, and therefore the fifth display data buffer 275 stores display data for causing the first to fourth alarm display devices 201 to 204 to perform a predetermined display. When the second timer interrupt process for transmitting display data to the fifth display circuit 265 is processed, the display data stored in the fifth display data buffer 275 is transmitted to the display IC 266 not only when the display data stored in the fifth display data buffer 275 has been changed, but also when the display data has not been changed.

The first to fourth notification display devices 201 to 204 display the results of the game history management, and when the setting confirmation process (FIG. 115) or the setting value update process (FIG. 116) is executed, a display corresponding to the current setting value is displayed. In this case, since the fifth display data buffer 275 is provided in the work area 221 for specific control, the process of storing display data in the fifth display data buffer 275 is performed as a process corresponding to specific control. On the other hand, the process of deriving the game history management results is performed as a process corresponding to non-specific control, and the 61st to 68th parameters, which are the results of the game history management, are displayed sequentially on the first to fourth notification display devices 201 to 204.

120(b), the work area 223 for non-specific control is provided with not only a calculation result storage area 234 for storing the 61st to 68th parameters, but also a display target setting area 276 for storing the parameters among the 61st to 68th parameters that are to be displayed on the first to fourth notification display devices 201 to 204. In this embodiment, as in the above-mentioned 15th embodiment, the period during which the calculation result of one parameter is continuously displayed is 10 seconds, so that in the process corresponding to non-specific control, the calculation result of the parameter to be displayed is read from the calculation result storage area 234 according to a predetermined display order every time 10 seconds elapses, and the calculation result of the parameter that has been read is stored in the display target setting area 276. Then, when the first to fourth notification display devices 201 to 204 are in a situation where they need to display the results of game history management, the display data stored in the display target setting area 276 is read out in the second timer interrupt process (FIG. 123), which is a process corresponding to specific control, and the read out display data is stored in the fifth display data buffer 275.

On the other hand, when the setting confirmation process (FIG. 115) is being executed, the display data is stored in the fifth display data buffer 275 so that the first to fourth notification display devices 201 to 204 display an indication that the current setting value of the pachinko machine 10 is being confirmed and display an indication of the current setting value of the pachinko machine 10 in the second timer interrupt process (FIG. 123), which is a process corresponding to the specific control. Also, when the setting value update process (FIG. 116) is being executed, the display data is stored in the fifth display data buffer 275 so that the first to fourth notification display devices 201 to 204 display an indication that the setting value of the pachinko machine 10 is being updated and display an indication of the current setting value of the pachinko machine 10 in the second timer interrupt process (FIG. 123), which is a process corresponding to the specific control.

In a configuration in which the first to fifth display data buffers 271 to 275 are provided as described above, the main CPU 63 reads display data from the display data buffers 271 to 275 corresponding to each processing round of the second timer interrupt processing (Figure 123) and transmits the read display data to the display IC 266, while also transmitting type data indicating which of the first to fifth display circuits 261 to 265 the display data corresponds to to the display IC 266. Figure 121 is an explanatory diagram for explaining the electrical configuration of the display IC 266.

As shown in FIG. 121, the display IC 266 includes a type data buffer 281, a selection signal output unit 282, a display data buffer 283, and a display data output unit 284. The display data buffer 283 stores display data received from the main CPU 63. The display data output unit 284 transmits the display data stored in the display data buffer 283 to the first to fifth display circuits 261 to 265. The type data buffer 281 stores type data received from the main CPU 63. The selection signal output unit 282 outputs a selection signal to specify the display circuit 261 to 265 among the first to fifth display circuits 261 to 265 that corresponds to the type data stored in the type data buffer 281 as the destination for receiving the display data.

In detail, as shown in FIG. 119, the display IC 266 and the first display circuit 261 are electrically connected using a display signal group 291. The display signal group 291 is provided so as to enable 8-bit display data to be transmitted at once, and the display data in 8-bit units is transmitted from the display IC 266 by parallel communication. In addition, a branch signal group 292 is provided by branching from the display signal group 291, and the branch signal group 292 is electrically connected to each of the second display circuit 262, the third display circuit 263, the fourth display circuit 264, and the fifth display circuit 265. The branch signal group 292 is provided so as to enable 8-bit display data to be transmitted at once, similar to the display signal group 291, and the display data in 8-bit units is transmitted from the display IC 266 by parallel communication.

By providing the display signal group 291 and branch signal group 292 as described above, when the display data stored in the display data buffer 283 is transmitted by the display data output unit 284, the display data is supplied to all of the first to fifth display circuits 261 to 265. In this case, the first to fifth selection signal lines 301 to 305 are provided to specify the display circuits 261 to 265 that should receive and use the supplied display data.

The first selection signal line 301 is provided to electrically connect the display IC 266 and the first display circuit 261. When type data corresponding to the first display circuit 261 is stored in the type data buffer 281, the selection signal output unit 282 of the display IC 266 transmits a first selection signal to the first display circuit 261 through the first selection signal line 301 in order to have the first display circuit 261 receive and use the display data supplied from the display data output unit 284. As a result, the display data supplied to all of the first to fifth display circuits 261 to 265 through the display signal group 291 and the branch signal group 292 is received and used only by the first display circuit 261.

The second selection signal line 302 is provided to electrically connect the display IC 266 and the second display circuit 262. When type data corresponding to the second display circuit 262 is stored in the type data buffer 281, the selection signal output unit 282 of the display IC 266 transmits a second selection signal to the second display circuit 262 through the second selection signal line 302 so that the second display circuit 262 receives and uses the display data supplied from the display data output unit 284. As a result, the display data supplied to all of the first to fifth display circuits 261 to 265 through the display signal group 291 and the branch signal group 292 is received and used only by the second display circuit 262.

The third selection signal line 303 is provided to electrically connect the display IC 266 and the third display circuit 263. When type data corresponding to the third display circuit 263 is stored in the type data buffer 281, the selection signal output unit 282 of the display IC 266 transmits a third selection signal to the third display circuit 263 through the third selection signal line 303 so that the third display circuit 263 receives and uses the display data supplied from the display data output unit 284. As a result, the display data supplied to all of the first to fifth display circuits 261 to 265 through the display signal group 291 and the branch signal group 292 is received and used only by the third display circuit 263.

The fourth selection signal line 304 is provided to electrically connect the display IC 266 and the fourth display circuit 264. When type data corresponding to the fourth display circuit 264 is stored in the type data buffer 281, the selection signal output unit 282 of the display IC 266 transmits a fourth selection signal to the fourth display circuit 264 through the fourth selection signal line 304 so that the fourth display circuit 264 receives and uses the display data supplied from the display data output unit 284. As a result, the display data supplied to all of the first to fifth display circuits 261 to 265 through the display signal group 291 and the branch signal group 292 is received and used only by the fourth display circuit 264.

The fifth selection signal line 305 is provided to electrically connect the display IC 266 and the fifth display circuit 265. When type data corresponding to the fifth display circuit 265 is stored in the type data buffer 281, the selection signal output unit 282 of the display IC 266 transmits a fifth selection signal to the fifth display circuit 265 through the fifth selection signal line 305 so that the fifth display circuit 265 receives and uses the display data supplied from the display data output unit 284. As a result, the display data supplied to all of the first to fifth display circuits 261 to 265 through the display signal group 291 and the branch signal group 292 is received and used only by the fifth display circuit 265.

Figure 122 is a time chart showing how type data and display data are transmitted from the main CPU 63 to the display IC 266, and how the display data transmitted from the display IC 266 is received by the first display circuit 261 or the second display circuit 262. FIG. 122(a) shows a period during which a type data signal is transmitted from the main CPU 63 to the display IC 266, FIG. 122(b) shows a period during which a type clock signal is transmitted from the main CPU 63 to the display IC 266, FIG. 122(c) shows a period during which a display data signal is transmitted from the main CPU 63 to the display IC 266, FIG. 122(d) shows a period during which a display clock signal is transmitted from the main CPU 63 to the display IC 266, FIG. 122(e) shows a period during which a first selection signal is transmitted from the display IC 266 to the first display circuit 261, FIG. 122(f) shows a period during which a second selection signal is transmitted from the display IC 266 to the second display circuit 262, and FIG. 122(g) shows a period during which display data is transmitted from the display IC 266 to the first to fifth display circuits 261 to 265. The same applies when display data is received in the third to fifth display circuits 263 to 265.

At timing t1 after the supply of operating power to the pachinko machine 10, including the main CPU 63, the display IC 266, and the first to fifth display circuits 261 to 265, has begun, the main CPU 63 begins transmitting category data and display data to the display IC 266. Specifically, as shown in FIG. 122(b), a pulsed category clock signal is transmitted at timings t1, t2, t3, t4, and t5, and as shown in FIG. 122(a), a pulsed category data signal is transmitted in response to the transmission of the pulsed category clock signal at timing t1. As a result, information corresponding to the first display circuit 261 is stored in the category data buffer 281 of the display IC 266.

As shown in FIG. 122(d), a pulsed display clock signal is transmitted at each of t1, t2, t3, t4, t5, t6, t7, and t8, and a pulsed display data signal is transmitted in response to the transmission of the pulsed display clock signal at each of t2, t3, t5, and t7, as shown in FIG. 122(c). As a result, display data corresponding to the above information format is stored in the display data buffer 283 of the display IC 266.

Then, at timing t9, as shown in FIG. 122(d), the transmission of the 8th bit of the display clock signal is completed, and at timing t9, as shown in FIG. 122(e), the selection signal output unit 282 of the display IC 266 starts transmitting a first selection signal to the first display circuit 261 corresponding to the type data stored in the type data buffer 281, and at timing t9, as shown in FIG. 122(g), the display data output unit 284 of the display IC 266 starts transmitting the display data stored in the display data buffer 283. As a result, the display data is received by the first display circuit 261 and used.

After that, at timing t10, as shown in Figures 122(a) to 122(d), the main CPU 63 starts to transmit new type data and display data to the display IC 266. In this case, at timing t10, as shown in Figures 122(e) and 122(g), the transmission of the first selection signal from the display IC 266 to the first display circuit 261 is stopped, and the transmission of display data from the display IC 266 to the first to fifth display circuits 261 to 265 is stopped.

Regarding the new transmission of category data and display data in detail, as shown in FIG. 122(b), a pulsed category clock signal is transmitted at timings t10, t11, t12, t13, and t14, and as shown in FIG. 122(a), a pulsed category data signal is transmitted in response to the transmission of a pulsed category clock signal at timing t11. As a result, information corresponding to the second display circuit 262 is stored in the category data buffer 281 of the display IC 266.

As shown in FIG. 122(d), a pulsed display clock signal is transmitted at each of t10, t11, t12, t13, t14, t15, t16, and t17, and as shown in FIG. 122(c), a pulsed display data signal is transmitted in response to the transmission of the pulsed display clock signal at each of t10, t11, t12, t15, t16, and t17. As a result, display data corresponding to the above information format is stored in the display data buffer 283 of the display IC 266.

Then, at the timing of t18, as shown in FIG. 122(d), the transmission of the 8th bit of the display clock signal is completed, and at the timing of t18, as shown in FIG. 122(f), the selection signal output unit 282 of the display IC 266 starts transmitting a second selection signal to the second display circuit 262 corresponding to the type data stored in the type data buffer 281, and at the timing of t18, as shown in FIG. 122(g), the display data output unit 284 of the display IC 266 starts transmitting the display data stored in the display data buffer 283. As a result, the display data is received by the second display circuit 262 and used.

For the first to fourth display circuits 261 to 264, only one display data is transmitted in the second timer interrupt process (FIG. 123) which is the target of transmitting display data, but for the fifth display circuit 265, four display data are transmitted in the second timer interrupt process (FIG. 123) which is the target of transmitting display data, corresponding to the number of the first to fourth notification display devices 201 to 204. As already explained, the second timer interrupt process (FIG. 123) is started at the second interrupt period (specifically, 2 milliseconds), but each processing time is set so that even in a processing round in which four display data are transmitted, one processing round is completed within the second interrupt period.

The above configuration makes it possible to transmit display data to multiple display circuits 261-265 using one display IC 266. Here, as already explained, each of the first to fifth display circuits 261-265 can store and hold the provided display data for a predetermined period (for example, 16 milliseconds), but after the predetermined period has passed, the display data will gradually approach an all-zero state. In this case, if the reception of display data in each display circuit 261-265 exceeds the predetermined period, even if the display content has not been changed in the special map display unit 37a, the special map reserved display unit 37b, the ordinary map display unit 38a, the ordinary map reserved display unit 38b, and the first to fourth notification display devices 201-204, the display segments that are in an illuminated state will temporarily approach an unlit state, which may result in the light flashing in the display segments. In contrast to this, in this embodiment, in addition to the first timer interrupt process (FIG. 117) that is started at the first interrupt period (specifically, 4 milliseconds), a second timer interrupt process (FIG. 123) that is started at a second interrupt period (specifically, 2 milliseconds) that is shorter than the first interrupt period is set, and the transmission of display data to the display IC 266 is performed in a consolidated manner in the second timer interrupt process.

The second timer interrupt process will be described below with reference to the flowchart in FIG. 123. Note that the processes in steps S8401 to S8413 in the second timer interrupt process are executed using a program for specific control and data for specific control in the main CPU 63.

First, interrupt prohibition is set to prohibit the occurrence of the first timer interrupt processing (FIG. 117) and the second timer interrupt processing (FIG. 123) (step S8401). By prohibiting the occurrence of the first timer interrupt processing (FIG. 117), it is possible to prevent the first timer interrupt processing (FIG. 117) from interrupting and starting the second timer interrupt processing (FIG. 123) even if the first interrupt period has elapsed. Also, by prohibiting the occurrence of the second timer interrupt processing (FIG. 123), it is possible to prevent the second timer interrupt processing (FIG. 123) from being started redundantly even if the second interrupt period has elapsed during the execution of the second timer interrupt processing (FIG. 123).

Then, it is determined whether the setting update display flag in the work area 221 for specific control is set to "1" (step S8402). The setting update display flag is a flag for the main CPU 63 to determine whether the setting value update process (FIG. 116) is being executed by the main CPU 63. As already explained, the setting value update process (FIG. 116) is executed in a situation where the process at the start of the supply of operating power is being executed in the main process (FIG. 114) when the supply of operating power to the main CPU 63 is started, but the second timer interrupt process (FIG. 123) is started by interrupting even when the process at the start of the supply of operating power is being executed. Therefore, even when the setting value update process (FIG. 116) is being executed by the main CPU 63, the second timer interrupt process (FIG. 123) is started by interrupting.

The setting update display flag being set to "1" means that the current processing of the second timer interrupt process (FIG. 123) is a processing run that was started by interrupting a situation in which the setting value update process (FIG. 116) is being executed by the main CPU 63. If a positive determination is made in step S8402, a setting process is executed in the fifth display data buffer 275 during the setting update (step S8403). In this setting process, display data is stored in the fifth display data buffer 275 to cause the first to fourth notification display devices 201 to 204 to display an indication that the setting value of the pachinko machine 10 is being updated and to display the current setting value of the pachinko machine 10.

When the display data stored in the fifth display data buffer 275 is transmitted to the fifth display circuit 265 via the display IC 266, the first to fourth display devices 201 to 204 display as shown in the explanatory diagram of FIG. 124(a). Specifically, when the first to fourth display devices 201 to 204 display an indication that the setting value is being updated, at least one display segment is illuminated in each of the first to fourth display devices 201 to 204. In other words, each of the first to fourth display devices 201 to 204 is in a display state. This allows the manager of the amusement hall to know that the first to fourth display devices 201 to 204 are not malfunctioning, even when an indication is being displayed that the setting value is being updated. Even when the game history management results are displayed, at least one display segment is illuminated in each of the first through fourth notification display devices 201-204, and each of the first through fourth notification display devices 201-204 is in a display state.

Regarding the display contents of the first to fourth notification display devices 201 to 204 in detail, in the first notification display device 201, one central display segment is illuminated and the remaining display segments are turned off. Even when the gaming history management results are displayed in the first to fourth notification display devices 201 to 204, one central display segment in the first notification display device 201 may be illuminated, but the display contents of the first notification display device 201 when the gaming history management results are displayed do not include display contents in which one central display segment is illuminated and the remaining display segments are turned off. This makes it possible to use display segments that may be illuminated even when the gaming history management results are displayed, while making the display contents of the first notification display device 201 in a situation where the setting value is being updated display contents that are not displayed in the gaming history management results.

In the second notification display device 202, as in the first notification display device 201, one central display segment is illuminated and the remaining display segments are turned off. Even when the gaming history management results are displayed in the first to fourth notification display devices 201 to 204, one central display segment in the second notification display device 202 may be illuminated, but the display content of the second notification display device 202 when the gaming history management results are displayed does not include display content in which one central display segment is illuminated and the remaining display segments are turned off. This makes it possible to use display segments that may be illuminated even when the gaming history management results are displayed, while making the display content of the second notification display device 202 in a situation where the setting value is being updated display content that is not displayed in the gaming history management results.

In the third notification display device 203, some of the display segments are illuminated and the remaining display segments are turned off so that the letter "H" is displayed. In this case, the illuminated display segments may be illuminated even when the game history management results are displayed on the first to fourth notification display devices 201 to 204, but the display content of the third notification display device 203 when the game history management results are displayed does not include the display content that displays the letter "H". This makes it possible to use the display segments that can be illuminated even when the game history management results are displayed, while making the display content of the third notification display device 203 when the setting value is being updated display content that is not displayed in the game history management results. Also, the display content of the third notification display device 203 when the setting value is being confirmed does not include the display content that displays the letter "H". This makes it possible to notify the manager of the game hall that the setting value is being updated by displaying "H" on the third notification display device 203.

In the fourth alert display device 204, some of the display segments are illuminated and the remaining display segments are turned off to display the current setting value. In the case of FIG. 124(a), the current setting value is "Setting 2", so the fourth alert display device 204 displays "2" corresponding to "Setting 2". By checking the fourth alert display device 204, the manager of the amusement hall can understand the current setting value. Note that the display content of the fourth alert display device 204 when the setting value is being updated can be displayed both in the situation where the game history management results are displayed and in the situation where the setting value is being checked.

Returning to the explanation of the second timer interruption process (FIG. 123), if a negative judgment is made in step S8402, it is judged whether or not the setting confirmation display flag in the work area 221 for specific control is set to "1" (step S8404). The setting confirmation display flag is a flag for the main CPU 63 to determine whether or not the setting confirmation process (FIG. 115) is being executed in the main CPU 63. As already explained, the setting confirmation process (FIG. 115) is executed in a situation where the process at the start of the supply of operating power is being executed in the main process (FIG. 114) when the supply of operating power to the main CPU 63 is started, but the second timer interruption process (FIG. 123) is started by interrupting even in a situation where the process at the start of the supply of operating power is being executed. Therefore, even in a situation where the setting confirmation process (FIG. 115) is being executed in the main CPU 63, the second timer interruption process (FIG. 123) is started by interrupting.

The setting confirmation display flag being set to "1" means that the current processing of the second timer interrupt process (FIG. 123) is a processing run that was started by interrupting a situation in which the setting confirmation process (FIG. 115) is being executed by the main CPU 63. If a positive determination is made in step S8404, a setting process is executed in the fifth display data buffer 275 during the setting confirmation (step S8405). In this setting process, display data is stored in the fifth display data buffer 275 to cause the first to fourth notification display devices 201 to 204 to display an indication that the setting values of the pachinko machine 10 are being confirmed and to display the current setting values of the pachinko machine 10.

When the display data stored in the fifth display data buffer 275 is sent to the fifth display circuit 265 via the display IC 266, the first to fourth display devices 201 to 204 display as shown in the explanatory diagram of FIG. 124(b). Specifically, when the first to fourth display devices 201 to 204 display an indication that the setting value is being updated, at least one display segment is illuminated in each of the first to fourth display devices 201 to 204. In other words, each of the first to fourth display devices 201 to 204 is in a display state. This allows the manager of the amusement hall to know that the first to fourth display devices 201 to 204 are not malfunctioning, even when an indication is being displayed that the setting value is being checked.

Regarding the display contents of the first to fourth notification display devices 201 to 204 in detail, in the first notification display device 201, one central display segment is illuminated and the remaining display segments are turned off. Even when the gaming history management results are displayed in the first to fourth notification display devices 201 to 204, one central display segment in the first notification display device 201 may be illuminated, but the display contents of the first notification display device 201 when the gaming history management results are displayed do not include display contents in which one central display segment is illuminated and the remaining display segments are turned off. This makes it possible to use display segments that may be illuminated even when the gaming history management results are displayed, while making the display contents of the first notification display device 201 in a situation where the setting values are being confirmed display contents that are not displayed in the gaming history management results.

In the second notification display device 202, as in the first notification display device 201, one central display segment is illuminated and the remaining display segments are turned off. Even when the gaming history management results are displayed in the first to fourth notification display devices 201 to 204, one central display segment in the second notification display device 202 may be illuminated, but the display content of the second notification display device 202 when the gaming history management results are displayed does not include display content in which one central display segment is illuminated and the remaining display segments are turned off. This makes it possible to use display segments that may be illuminated even when the gaming history management results are displayed, while making the display content of the second notification display device 202 in a situation where the setting value is being confirmed display content that is not displayed in the gaming history management results.

The display contents on the first notification display device 201 and the second notification display device 202 are the same whether the setting value is being updated or confirmed. This makes it possible to clearly inform the manager of the gaming hall through the display on the first notification display device 201 and the second notification display device 202 that the display subject on the first to fourth notification display devices 201 to 204 is not the result of game history management but the setting value.

In the third notification display device 203, some of the display segments are illuminated and the remaining display segments are turned off so that the letter "k" is displayed. In this case, the illuminated display segments may be illuminated even when the game history management results are displayed on the first to fourth notification display devices 201 to 204, but the display content of the third notification display device 203 when the game history management results are displayed does not include the display content that displays the letter "k". This makes it possible to use display segments that may be illuminated even when the game history management results are displayed, while making the display content of the third notification display device 203 when the setting value is being confirmed a display content that is not displayed in the game history management results. Also, while "H" is displayed on the third notification display device 203 when the setting value is being updated, "k" is displayed on the third notification display device 203 when the setting value is being confirmed. This makes it possible to notify the manager of the amusement hall whether the setting value is being updated or checked by checking the display content of the third notification display device 203.

In the fourth alert display device 204, some of the display segments are lit and the remaining display segments are turned off so that a display corresponding to the current setting value is displayed. In the case of FIG. 124(b), the current setting value is "Setting 2", so the fourth alert display device 204 displays "2" corresponding to "Setting 2". By checking the fourth alert display device 204, the manager of the amusement hall can understand the current setting value. Note that the display content of the fourth alert display device 204 when the setting value is being checked can be displayed both in a situation where the gaming history management results are displayed and in a situation where the setting value is being updated.

Returning to the explanation of the second timer interrupt process (FIG. 123), if a negative determination is made in step S8404, a setting process for the fifth display data buffer 275 during normal times is executed (step S8406). In this case, information is read from the display target setting area 276 in the work area 223 for non-specific control, and display data for causing the first to fourth alarm display devices 201 to 204 to display parameters corresponding to the read information is stored in the fifth display data buffer 275. The display data is transmitted to the fifth display circuit 265 via the display IC 266, and the first to fourth alarm display devices 201 to 204 display the calculation results of the parameters currently being displayed among the 61st to 68th parameters.

When the processing of step S8403, step S8405, or step S8406 is executed, the transmission state of the signal through the type data signal line LN1 and the type clock signal line LN2 is set to the OFF state (step S8407), and the transmission state of the signal through the display data signal line LN3 and the display clock signal line LN4 is set to the OFF state (step S8408). After that, the type counter provided in the work area 221 for specific control is updated (step S8409).

The type counter is a counter for the main CPU 63 to specify the display data transmission target among the first to fifth display data buffers 271 to 275 in the current processing of the second timer interrupt processing. When the type counter value is "1", the display data of the first display data buffer 271 is the transmission target, when the type counter value is "2", the display data of the second display data buffer 272 is the transmission target, when the type counter value is "3", the display data of the third display data buffer 273 is the transmission target, when the type counter value is "4", the display data of the fourth display data buffer 274 is the transmission target, when the type counter value is "5", the display data of the fifth display data buffer 275 is the transmission target. In the type counter update processing, the type counter value is incremented by 1, and when the type counter value after the increment exceeds the upper limit value "5", the type counter value is set to "1". As a result, the display data transmission target is changed sequentially among the first to fifth display data buffers 271 to 275 for each processing of the second timer interrupt processing.

Then, the type data corresponding to the value of the type counter is read from the main ROM 64 (step S8410). Specifically, if the type counter value is "1", the type data corresponding to the first display circuit 261 is read from the main ROM 64; if the type counter value is "2", the type data corresponding to the second display circuit 262 is read from the main ROM 64; if the type counter value is "3", the type data corresponding to the third display circuit 263 is read from the main ROM 64; if the type counter value is "4", the type data corresponding to the fourth display circuit 264 is read from the main ROM 64; and if the type counter value is "5", the type data corresponding to the fifth display circuit 265 is read from the main ROM 64.

Then, display data is read from the display data buffers 271-275 that correspond to the value of the type counter (step S8411). Specifically, if the type counter value is "1", display data is read from the first display data buffer 271; if the type counter value is "2", display data is read from the second display data buffer 272; if the type counter value is "3", display data is read from the third display data buffer 273; if the type counter value is "4", display data is read from the fourth display data buffer 274; and if the type counter value is "5", display data is read from the fifth display data buffer 275.

After that, a transmission process of various signals is executed (step S8412). In this transmission process, signals are output to the type data signal line LN1 and the type clock signal line LN2 so that the type data read in step S8410 is transmitted to the display IC 266. In addition, in this transmission process, signals are output to the display data signal line LN3 and the display clock signal line LN4 so that the display data read in step S8411 is transmitted to the display IC 266.

After that, interrupt permission is set to allow the first timer interrupt process (Figure 117) and the second timer interrupt process (Figure 123) to occur (step S8413).

The present embodiment described above provides the following excellent advantages:

By turning on the power to the pachinko machine 10 with the setting key insertion section 68a turned on by the setting key without pressing the reset button 68c, the supply of operating power to the main CPU 63 is started and the main processing (Figure 114) is started, but the reset button 68c is not pressed and the setting key insertion section 68a is turned on, and the setting confirmation process is executed in a state where processing is being executed when the supply of operating power begins, which is the state before the processing that enables the game to progress in the main processing is executed. This makes it difficult to illegally check the setting values.

Assuming that the setting value is checked while the game is continuing, for example, if the setting value is checked during the execution of a game round, there is a risk that the transition to the open/close execution mode will occur while the setting value is being checked. In this case, even though the open/close execution mode has started, it may not be possible to launch the game ball toward the special electric winning device 32. Also, if the setting value is checked during the execution of the open/close execution mode, the open/close execution mode will proceed while the setting value is being checked, so in this case too, there is a risk that the game ball will not be able to be launched toward the special electric winning device 32.

Assuming that the game progress is stopped when the setting value is confirmed, if the confirmation of the setting value is started while the game is being played, the process for stopping the game progress midway may become complicated. For example, if the confirmation of the setting value is started during the execution of a game round and the game progress is to be stopped midway, a process for stopping the game round midway is required. In this case, if the display of the pattern change in the pattern display device 41 is stopped midway when the confirmation of the setting value is started, and the display of the pattern change in the pattern display device 41 is resumed when the confirmation of the setting value is completed, a process that is that much more complicated is required. Also, for example, if the confirmation of the setting value is started during the execution of the opening and closing execution mode and the game progress is to be stopped midway, a process for stopping the opening and closing execution mode midway is required. Also, if the confirmation of the setting value is started during the execution of the display of the pattern change in the normal picture display unit 38a and the game progress is to be stopped midway, a process for stopping the display of the pattern change midway is required. In addition, if the confirmation of the setting value is started during the execution of the open execution state of the normal power role 34a and the progress of the game is to be stopped midway, a process is required to stop the open execution state midway. On the other hand, a configuration is also possible in which the confirmation of the setting value is performed after waiting until all games are completed. In this case, it becomes necessary to wait until a situation in which none of the game rounds, the open/close execution mode, the display of the changing patterns in the normal picture display section 38a, and the open execution state of the normal power role 34a are being executed, and there is a risk that the waiting time until the confirmation of the setting value can be started will be long.

In contrast to this, the setting confirmation process is executed in a state where the process at the start of the supply of operating power is being executed, which is the state before the process that enables game progress is executed in the main process that is executed when the supply of operating power to the main CPU 63 is started, and therefore the setting value is confirmed in a state where game progress has already been stopped. This makes it possible to avoid checking the setting value while game progress is in progress, and there is no need to stop game progress midway when checking the setting value, or to wait until game progress is stopped to check the setting value. This makes it possible to properly check the setting value.

By turning on the power to the pachinko machine 10 while pressing the reset button 68c, the supply of operating power to the main CPU 63 is started, and the main process (FIG. 114) is started. The reset button 68c is pressed, and the RAM clear process (step S7915) is executed regardless of whether the setting key insertion section 68a is turned on. As a result, the operation of turning on the power to the pachinko machine 10 while pressing the reset button 68c is uniquely linked to the execution of the RAM clear process (step S7915), and the operation to cause the RAM clear process (step S7915) to occur can be made easy to understand for the manager of the amusement hall.

Even if the RAM clear process (step S7915) is executed, the setting value counter in the work area 221 for specific control is not cleared to "0" and the information in the setting value counter is not changed. This makes it possible to prevent the setting value from being changed even if the RAM clear process (step S7915) is executed.

Not only is the power to the pachinko machine 10 turned on while pressing the reset button 68c, but also the setting value update process (step S7918) is executed based on the power being turned on while the setting key insertion section 68a is turned on with the setting key. As already explained, the setting confirmation process (step S7914) is executed based on the power being turned on while the setting key insertion section 68a is turned on with the setting key without pressing the reset button 68c. This makes it possible to make the ON operation of the setting key insertion section 68a a common operation for executing processing related to the setting value. This makes it possible to make the operation content for generating processing related to the setting value easy to understand for the manager of the game hall.

When the power of the pachinko machine 10 is turned on while the setting key insertion section 68a is turned on with the setting key, if the reset button 68c is not pressed, a setting confirmation process is executed, and if the reset button 68c is pressed, a setting value update process is executed. This makes it possible to differentiate between the setting confirmation process and the setting value update process, depending on whether the reset button 68c is pressed or not. This makes it possible to make the operation contents for executing the desired process between the setting confirmation process and the setting value update process easy to understand for the manager of the amusement hall. Also, by making the operation contents for executing the setting value update process more than the setting confirmation process, it becomes possible to make it particularly difficult to carry out fraudulent acts of setting value update processing.

The process of monitoring whether the set value is abnormal is executed by the first timer interrupt process (Fig. 117), which is periodically started. This makes it possible to monitor whether the set value is abnormal even when a game is being played. This makes it possible to prevent the game from continuing even if the set value is abnormal.

Monitoring whether the set value is abnormal is performed each time a monitoring trigger occurs. More specifically, it is performed each time the first timer interrupt process (Figure 117) is started. This makes it possible to increase the frequency with which the set value is monitored for abnormalities.

In the main process (FIG. 114), there is no process for monitoring whether the set value is normal. If the process for monitoring whether the set value is normal is set in the process at the start of the supply of operating power in the main process (FIG. 114), not only the power failure flag and the checksum are monitored but also the set value must be monitored to see if it is normal at the start of the supply of operating power, which increases the monitoring load. Furthermore, if it is determined that the set value is abnormal at the start of the supply of operating power, the RAM clear process (step S7915) and the set value update process (step S7918) are executed, the processing configuration becomes more complicated. In contrast, since the process for monitoring whether the set value is normal is not set in the main process (FIG. 114), it is possible to make the processing configuration of the process at the start of the supply of operating power suitable. Also, even if the process for monitoring whether the set value is normal is not set in the process at the start of the supply of operating power, the first timer interrupt process (FIG. 117) is configured to execute the setting monitoring process (step S8220), so that it is possible to deal with the abnormality of the set value.

Note that, as in the first embodiment, an update button 68b is provided, and in the setting value update process (FIG. 116), the setting value may be updated by one step each time the update button 68b is pressed, rather than the reset button 68c being pressed. In addition, when a setting key is inserted into the setting key insertion section 68a and rotated, positions corresponding to "Setting 1" to "Setting 6" are set as rotation positions, and the setting value corresponding to the rotation position of the setting key insertion section 68a may be set. In addition, the setting key insertion section 68a may be configured to be capable of being rotated further than the ON position, and the setting value being updated may be updated to the next setting value in the sequence each time a rotation operation beyond the ON position is performed.

In addition, in the setting value update process (Fig. 116), the setting key insertion section 68a may be turned OFF to confirm the selected setting value, and the setting value update process may be terminated by pressing the reset button 68c. In addition, in a configuration in which the update button 68b is provided, in the setting value update process (Fig. 116), the setting key insertion section 68a may be turned OFF to confirm the selected setting value, and the setting value update process may be terminated by pressing the update button 68b.

In addition, the condition for executing the setting value update process (Figure 116) may be such that the condition that the gaming machine main body 12 is in an open state is not set, or the condition that the front door frame 14 is in an open state is not set, or both the condition that the gaming machine main body 12 is in an open state and the condition that the front door frame 14 is in an open state are not set.

In addition, the condition for executing the setting confirmation process (Figure 115) may not be set so that the gaming machine main body 12 is in an open state, or the condition for the front door frame 14 to be in an open state may not be set, or both the condition for the gaming machine main body 12 to be in an open state and the condition for the front door frame 14 to be in an open state may not be set.

In addition, if the main process (FIG. 114) that is executed when the supply of operating power to the main CPU 63 is started determines that the power outage flag is not set to "1" or that the checksum is abnormal, a RAM clear process (step S7915) may be executed. In this case, after the RAM clear process (step S7915) is executed, a setting value update process (step S7918) may be executed, or a notification may be issued indicating that the setting value update process (step S7918) should be executed and the game progress may be stopped, or a process for controlling the game progress may be started.

In addition, instead of being configured in the main processing (FIG. 114) so that the setting confirmation process (step S7914) is executed after the process of determining whether the power outage flag is set to "1" and the process of comparing the checksums, it may be configured so that it is executed before these processes. In this case, it is possible to give priority to the process for confirming the setting value.

In addition, the configuration is not limited to the configuration in which the setting monitoring process (step S8220) is executed each time the first timer interrupt process (FIG. 117) is activated, and may be configured, for example, in such a way that the setting monitoring process (step S8220) is executed each time the first timer interrupt process (FIG. 117) is executed a number of times (e.g., 10,000 times) that is determined as a number of triggers. In this case, it is possible to periodically monitor whether the setting value is normal, while reducing the frequency with which the monitoring is executed.

The setting monitoring process (step S8220) may also be configured to be executed in the remaining processes (steps S7921 to S7924) in the main process (Figure 114). In this case, it is possible to monitor whether the setting value is normal by utilizing the free time when the first timer interrupt process (Figure 117) and the second timer interrupt process (Figure 123) are not being executed.

Also, the configuration may be such that the setting monitoring process (step S8220) is executed when a new round of play is started. More specifically, the configuration may be such that the setting monitoring process (step S8220) is executed before the win/loss determination process is executed when a new round of play is started. This makes it possible to prevent the win/loss determination process from being executed in a situation where the setting value is abnormal.

In addition, if the setting monitoring process (step S8220) identifies an abnormal setting value, the process may proceed to the setting value update process (step S7918).

In addition, if the setting monitoring process (step S8220) identifies an abnormal setting value, the main process (FIG. 114) may be started with a setting abnormality flag set to "1" in the work area 221 for specific control, and the game progress may be stopped with the setting abnormality flag set to "1", and the power must be turned OFF and ON to release the stopped state of the game progress. In this case, even if no operation is performed in the main process (FIG. 114) to execute the setting value update process, by forcibly executing the setting value update process when the setting abnormality flag is set to "1", it is possible to forcibly set a new setting value using the setting value update process set in the main process (FIG. 114).

In addition, the reserved information acquired when the game ball enters the first operating port 33 and the reserved information acquired when the game ball enters the second operating port 34 may be stored separately, and the first special chart display section and the second special chart display section may be provided as the special chart display section 37a corresponding to the reserved information. In this case, the display of the changing pattern in the first special chart display section and the display of the changing pattern in the second special chart display section may be executed in overlapping fashion, and when a predetermined game state is reached, the display of the changing pattern in either one of the special chart display sections may be configured to be extremely long. In this configuration, if the setting value is to be checked until the game is not being played, the waiting time will be long. In response to this, the setting confirmation process (step S7914) is executed in the process at the start of the supply of operating power in the main CPU 63, so that the setting value can be checked without causing the above-mentioned waiting time.

In addition, in the low frequency support mode, the duration of the changing display of the patterns in the normal picture display section 38a may be extremely long. In this configuration, if one waits to check the setting value until a situation in which no game is being played occurs, the waiting time becomes long. In response to this, by executing a setting confirmation process (step S7914) in the process when the supply of operating power to the main CPU 63 begins, it becomes possible to check the setting value without incurring the above-mentioned waiting time.

In addition, when the setting confirmation process (FIG. 115) is executed, the display contents of the first to fourth alert display devices 201 to 204 are not limited to those in the above embodiment. For example, instead of displaying the letter "k" on the third alert display device 203, only the central display segment may be illuminated, as with the first alert display device 201 and the second alert display device 202. In addition, the first to third alert display devices 201 to 203 may be turned off, and the fourth alert display device 204 may display a value corresponding to the current setting value.

In addition, when the setting value update process (FIG. 116) is executed, the display contents of the first to fourth alert display devices 201 to 204 are not limited to those in the above embodiment. For example, instead of displaying the letter "H" on the third alert display device 203, only the central display segment may be illuminated, as with the first alert display device 201 and the second alert display device 202. In addition, the first to third alert display devices 201 to 203 may be turned off, and the fourth alert display device 204 may display a value corresponding to the current setting value.

In addition, instead of a configuration in which the main CPU 63 transmits type data and display data to the display IC 266 simultaneously, the main CPU 63 may be configured to start transmitting the display data after starting transmitting the type data. In this case, the main CPU 63 may be configured to start transmitting the display data after starting transmitting the type data in the middle of transmitting the type data, or to start transmitting the display data after transmitting the type data is completed. In addition, the main CPU 63 may be configured to start transmitting the type data after starting transmitting the display data. In this case, the main CPU 63 may be configured to start transmitting the type data while transmitting the display data, or to start transmitting the type data after transmitting the display data is completed.

The display IC 266 is not limited to a configuration in which only one display IC 266 is provided so as to be common to the first to fifth display circuits 261 to 265, but may be provided in one-to-one correspondence with each of the first to fifth display circuits 261 to 265. In this configuration, if the period for storing and holding display data in each display IC provided in one-to-one correspondence with the first to fifth display circuits 261 to 265 is short, unintended blinking may occur in each display unit depending on the period for providing display data to each display IC. In response to this, by consolidating the process for transmitting display data in the second timer interrupt process (FIG. 123), which has a relatively short interrupt period as in the above embodiment, it is possible to shorten the period for providing display data to each display IC, and it is possible to prevent unintended blinking from occurring in each display unit.

In addition, instead of a configuration in which the winning random number counter C1 is provided in the main RAM 65, a configuration in which a random number circuit is provided to update the random number obtained in the win/loss determination process may be used. In this case, the internal function register setting process in the main process (Figure 114) will set up the random number of the random number circuit to correspond to the random number obtained in the win/loss determination process.

<Thirty-fourth embodiment>
In this embodiment, the processing configuration of the set value update process executed by the main CPU 63 is different from that of the 33rd embodiment. The configuration that differs from the 33rd embodiment will be described below. Note that the description of the same configuration as the 33rd embodiment will basically be omitted. In this embodiment, an update button 68b is provided on the main control board 61 as in the first embodiment.

Figure 125 is a flowchart showing the setting value update process in this embodiment, which is executed by the main CPU 63. Note that the processes in steps S8501 to S8508 in the setting value update process are executed using a program for specific control and data for specific control in the main CPU 63.

First, the setting update display flag provided in the work area 221 for specific control is set to "1" (step S8501). Then, it is determined whether the value of the setting value counter provided in the work area 221 for specific control is greater than or equal to 1, which corresponds to "setting 1," and less than or equal to 6, which corresponds to "setting 6" (step S8502). If the value of the setting value counter is "0" or greater than or equal to 7, a negative determination is made in step S8502, and the setting value counter is set to "1" (step S8503). As a result, the setting value of the pachinko machine 10 becomes "setting 1."

If the determination in step S8502 is affirmative or if the processing in step S8503 is executed, it is determined whether the reset button 68c is pressed (step S8504). If the reset button 68c is not pressed (step S8504: NO), and on the condition that the update button 68b is pressed (step S8505: YES), the value of the set value counter in the work area 221 for specific control is incremented by 1 (step S8506). As a result, the set value is updated to the next higher level each time the update button 68b is pressed. Also, if the update button 68b is not pressed (step S8505: NO) or the value of the set value counter is incremented by 1, the processing returns to step S8502. However, if it is determined in step S8502 that the value of the set value counter is 7 or more, the set value counter is set to "1" in step S8503. As a result, if the update button 68b is pressed once when the setting is "Setting 6," the setting will return to "Setting 1."

If the reset button 68c has been pressed (step S8504: YES), the current setting value is confirmed and the process proceeds to step S8507. In step S8507, it is determined whether the setting key insertion unit 68a has been turned OFF using the setting key. In this case, it may be configured to determine whether the setting key insertion unit 68a has switched from an ON state to an OFF state, or to determine whether the setting key insertion unit 68a is in an OFF state. If the setting key insertion unit 68a has not been turned OFF (step S8507: NO), the process of step S8507 is executed again.

If the setting key insertion section 68a is turned OFF (step S8507: YES), the setting update display flag in the work area 221 for specific control is cleared to "0" (step S8508).

According to the above configuration, in a configuration in which the setting value is updated by pressing the update button 68b, the setting value is confirmed by pressing the reset button 68c, and the setting key insertion section 68a is turned OFF to end the setting value update process. In other words, in order to end the setting value update process after updating the setting value in the setting value update process, it is necessary not only to turn OFF the setting key insertion section 68a but also to press the reset button 68c. This makes it difficult to illegally update the setting value and then play with that setting value.

<Other embodiments>
The present invention is not limited to the above-described embodiment, and various modifications and improvements are possible without departing from the spirit of the present invention. For example, the following modifications may be made. The following configurations of the other embodiments may be applied individually or in combination to the configurations of the above-described embodiment.

(1) In the first to fourteenth embodiments, the number of times the open/close execution mode occurs per unit game is calculated as a parameter indicating the frequency of the open/close execution mode. However, in addition to or instead of this, the number of times the open/close execution mode occurs may be calculated by dividing the number of times by the total number of game balls discharged from the game area PA. In addition to or instead of this, the number of times the open/close execution mode occurs may be calculated by dividing the number of times by the total number of balls that enter the first actuation port 33 and the number of balls that enter the second actuation port 34. This configuration may also be applied to the fifteenth to thirty-fourth embodiments.

(2) In the first to fourteenth embodiments, the number of times the high-frequency support mode occurs per unit play and the ratio of the number of times the high-frequency support mode occurs to the number of times the open/close execution mode occurs are calculated as parameters indicating the frequency of occurrence of the high-frequency support mode. However, in addition to or instead of this, the number of times the high-frequency support mode occurs may be calculated by dividing the result by the total number of game balls discharged from the play area PA. In addition to or instead of this, the number of times the high-frequency support mode occurs may be calculated by dividing the result by the total number of balls that enter the first actuation port 33 and the number of balls that enter the second actuation port 34. This configuration may also be applied to the fifteenth to thirty-fourth embodiments.

(3) The game result that triggers the opening and closing execution mode may include not only a big win result but also a small win result. When a small win result occurs, the opening and closing execution mode occurs, but the win/lose selection mode and the support mode do not change before and after the opening and closing execution mode. In addition, the opening and closing execution mode that results in a small win may be configured to be a low-frequency winning mode. In this case, when a big win result occurs, history information corresponding to the occurrence of the big win result may be stored in the history memory 117, and when a small win result occurs, history information corresponding to the occurrence of the small win result may be stored in the history memory 117. In addition, in this configuration, a parameter indicating the occurrence frequency of the big win result and a parameter indicating the occurrence frequency of the small win result may be calculated by using the history information stored in the history memory 117. In addition, this configuration may be applied to the above-mentioned fifteenth to thirty-fourth embodiments.

The probability of winning a small win result may be configured to change depending on the setting state of the pachinko machine 10, or may not change. When the probability of winning a small win result is configured to change depending on the setting state of the pachinko machine 10, the higher the setting value, the higher the probability of winning a small win result, or the higher the setting value, the lower the probability of winning a small win result.

In addition, in a configuration in which a small win result exists, the allocation ratio of the type of big win result in the case of a big win may be different between the reserved information acquired when the game ball enters the first operating port 33 and the reserved information acquired when the game ball enters the second operating port 34, and when aiming for the ball to enter the first operating port 33, a firing operation is performed so that the game ball flows down the area in the game area PA to the left of the variable display unit 36, and when aiming for the ball to enter the second operating port 34, a firing operation is performed so that the game ball flows down the area in the game area PA to the right of the variable display unit 36. Furthermore, a small win result may be generated based on the reserved information acquired when the game ball enters the first operating port 33.

In this configuration, the following 51st parameter may be present as a result of managing the game history. The normal period is the sum of the period during which the opening and closing execution mode is executed triggered by a small winning result based on the ball entering the first operating port 33 and the period during which the low-frequency support mode is executed instead of the opening and closing execution mode. The number of balls entering the out port 24a during the normal period is the number of balls entering K51, the number of balls entering the general winning port 31 during the normal period is the number of balls entering K52, the number of balls entering the special winning device 32 during the normal period is the number of balls entering K53, the number of balls entering the first operating port 33 during the normal period is the number of balls entering K54, and the number of balls entering the second operating port 34 during the normal period is the number of balls entering K55.
・The 51st parameter: the total number of game balls paid out during the normal period (K52 x "number of prize balls for winning the general winning port 31" + K53 x "number of prize balls for winning the special winning device 32" + K54 x "number of prize balls for winning the first operating port 33" + K55 x "number of prize balls for winning the second operating port 34") / the ratio of the total number of game balls discharged from the technique area PA during the normal period (K51 + K52 + K53 + K54 + K55). In the configuration in which the 51st parameter is calculated, if the probability of winning the small win varies depending on the setting state of the pachinko machine 10, the normal value of the 51st parameter will vary depending on the setting state of the pachinko machine 10. Therefore, it is preferable that the history information used to calculate the 51st parameter is erased when the setting state of the pachinko machine 10 is changed. On the other hand, if the probability of winning the small win result does not change according to the setting state of the pachinko machine 10, the normal value of the 51st parameter does not change according to the setting state of the pachinko machine 10. Therefore, it is preferable that the history information used to calculate the 51st parameter is not erased even if the setting state of the pachinko machine 10 is changed.

(4) In the first to fourteenth embodiments, instead of storing history information corresponding to the occurrence of the open/close execution mode in the history memory 117 regardless of the type of jackpot result, history information corresponding to the type of jackpot result may be stored in the history memory 117. In this case, a parameter indicating the frequency of occurrence for each type of jackpot result may be calculated. This configuration may also be applied to the fifteenth to thirty-fourth embodiments.

(5) In the first to fourteenth embodiments, the various parameters (the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters) are periodically calculated. However, the present invention is not limited to this. For example, the various parameters may be calculated when the total number of game balls discharged from the game area PA reaches a calculation trigger number (e.g., 10,000 balls), when the supply of operating power to the pachinko machine 10 is stopped, or when the number of game plays reaches a calculation trigger number (e.g., 1,000 times). In this case, the history memory 117 may be cleared to "0" when the various parameters are calculated. This configuration may also be applied to the fifteenth to thirty-fourth embodiments.

(6) In the first to fourteenth embodiments, all of the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters are calculated each time the timing for calculating various parameters is reached. However, the present invention is not limited to this. Only some of the various parameters are calculated at one calculation timing, and the parameter group to be calculated may be changed sequentially each time the timing for calculating is reached. For example, the first to eighth parameters may be calculated at one calculation timing, the eleventh to eighteenth parameters may be calculated at the next calculation timing, the twenty-first to twenty-sixth parameters may be calculated at the next calculation timing, the thirty-first parameter and the forty-first to forty-second parameters may be calculated at the next calculation timing, and the change of the calculation target in the above order may be repeated each time the timing for calculating is reached. This makes it possible to reduce the processing load for calculating parameters when a calculation timing is reached. This configuration may also be applied to the fifteenth to thirty-fourth embodiments.

(7) In the first to fourteenth embodiments, the calculation of various parameters may be performed using the history information in the history memory 117 on the condition that a game is being played. For example, the calculation of various parameters may be performed on the condition that a game ball is being supplied to the game area PA. This makes it possible to prevent the calculation of various parameters from being repeated unnecessarily even when a game is not being played. This configuration may also be applied to the fifteenth to thirty-fourth embodiments.

(8) In the first to fourteenth embodiments described above, the configuration is not limited to one in which a management IC 66 is provided separately from the main CPU 63, and the functions of the management IC 66 may be performed by the main CPU 63. In this case, the correspondence information is stored in advance in the main ROM 64. Also, a configuration may be adopted in which a history memory 117, a calculation result memory 131, and a separate storage memory 171 are provided separately from the main RAM 65, and the functions of the history memory 117, the calculation result memory 131, and the separate storage memory 171 are performed in the main RAM 65. In a configuration in which the functions of the history memory 117, the calculation result memory 131, and the separate storage memory 171 are performed in the main RAM 65, when the clear process (steps S105 and S117) of the main RAM 65 is performed, some or all of the areas corresponding to the history memory 117, the calculation result memory 131, and the separate storage memory 171 may be cleared to "0", or the areas corresponding to the history memory 117, the calculation result memory 131, and the separate storage memory 171 may be excluded from the targets of the "0" clear, and may be cleared to "0" when the corresponding clear conditions in each of the above embodiments are met. In addition, the manual operation contents for executing the clear process may be different between the areas corresponding to the history memory 117, the calculation result memory 131, and the separate storage memory 171 in the main RAM 65 and the other areas. In addition, the function of the management IC 66 may be performed by the audio and light emission control device 81.

(9) In the first to fourteenth embodiments, when a new setting is made to the setting state of the pachinko machine 10, the history information in the history memory 117 is stored and held without being erased, while the various parameters stored in the calculation result memory 131 may be erased. This makes it possible to prevent notification of the various parameters calculated before a new setting is made after the setting state is made. This configuration may also be applied to the fifteenth to thirty-fourth embodiments.

(10) In the third to fifth embodiments described above, even if a new setting is made to the setting state of the pachinko machine 10 (i.e., even if the main CPU 63 executes a setting value update process), if the setting value has not changed before and after the setting, the process of clearing the history memory 117 may not be executed. This makes it possible to prevent the history information in the history memory 117 from being erased even if the setting value has not been changed.

In this configuration, even if the clear process (step S117) is executed on all areas in the main RAM 65 for storing the setting values, the areas are not cleared to "0", so that the main CPU 63 can determine whether the setting value has changed before and after the setting value update process (step S118). In this case, if the main CPU 63 determines that the setting value has not changed, it may output a signal to the management CPU 112 so that the management CPU 112 does not execute the setting update recognition process, and if the main CPU 63 determines that the setting value has changed, it may output a signal to the management CPU 112 so that the management CPU 112 executes the setting update recognition process.

In addition, when a signal indicating that a new setting has been made to the setting state of the pachinko machine 10 is received from the main CPU 63, the management CPU 112 may be configured to determine whether or not the setting value has been changed by referring to the history information stored in the history memory 117. In this case, if the management CPU 112 determines that the setting value has not been changed, it is possible to not execute the process of clearing the history memory 117, and to execute the process of clearing the history memory 117 when the management CPU 112 determines that the setting value has been changed.

(11) In the third to fifth embodiments, even if a new setting is made to the setting state of the pachinko machine 10 (i.e., even if the main CPU 63 executes a setting value update process), if the setting value has not changed before and after the setting, the calculation process of various parameters triggered by the new setting of the setting state may not be executed. This makes it possible to prevent various parameters from being calculated in response to the new setting of the setting state even if the setting value has not been changed.

In this configuration, even if the clear process (step S117) is executed on all areas in the main RAM 65 for storing the setting values, the areas are not cleared to "0", so that the main CPU 63 can determine whether the setting value has changed before and after the setting value update process (step S118). In this case, if the main CPU 63 determines that the setting value has not changed, it may output a signal to the management CPU 112 so that the management CPU 112 does not execute the setting update recognition process, and if the main CPU 63 determines that the setting value has changed, it may output a signal to the management CPU 112 so that the management CPU 112 executes the setting update recognition process.

In addition, when a signal indicating that a new setting has been made to the setting state of the pachinko machine 10 is received from the main CPU 63, the management CPU 112 may be configured to determine whether or not the setting value has been changed by referring to the history information stored in the history memory 117. In this case, when the management CPU 112 determines that the setting value has not been changed, it is possible to prevent the execution of calculations of various parameters triggered by the new setting of the current setting state, and when the management CPU 112 determines that the setting value has been changed, it is possible to execute calculations of various parameters triggered by the new setting of the current setting state.

(12) In the third to fifth embodiments, when a new setting of the setting state of the pachinko machine 10 is made, various parameters are not calculated in the various calculation processes (step S1807) at that time, but the various parameters stored in the calculation result memory 131 at that time are stored in the area to be stored among the first to fifth separate storage areas 172 to 176 of the separate storage memory 171, and the information stored in the calculation result memory 131 is cleared to "0". In this case, since there is no need to calculate various parameters when a new setting of the setting state of the pachinko machine 10 is made, it is possible to complete the storage of various parameters in the separate storage memory 171 early.

(13) In the third to fifth embodiments, the contents of the various parameters stored in the first to fifth separate storage areas 172 to 176 of the separate storage memory 171 may be configured to be displayed on the first to third notification display devices 69a to 69c or other display devices by performing a specified display start operation. The specified display start operation may be performed by operating a dedicated operation unit, or a predetermined dedicated operation may be performed on an operation unit for performing other operations. This makes it possible to easily check the various parameters stored in the separate storage memory 171.

(14) Although the configuration is such that all of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 are targets for storing history information (or ball entry history), this is not limited to this, and only some of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 may be targets for storing history information. For example, only the general winning opening 31, special electric winning device 32, and second operating opening 34 may be targets for storing history information, or only the general winning opening 31 may be targets for storing history information. Even in this case, it is possible to grasp the ball entry patterns of game balls during a specified period for the ball entry sections for which history information is stored.

(15) Signal paths 118a-118c are set to transmit information corresponding to the ball's entry results for the first entry port detection sensor 42a, the second entry port detection sensor 43a, and the third entry port detection sensor 44a, respectively. However, this is not limited to this, and information corresponding to the ball entry results for the same type of entry port may be transmitted as one type of information even if there are multiple ball entry ports of the same type and multiple ball entry detection sensors corresponding to them. This makes it possible to reduce the number of types of information transmitted from the main CPU 63 to the management IC 66.

(16) In the first to fourteenth embodiments, the correspondence information indicating the correspondence between the type of information transmitted from the main CPU 63 to the management IC 66 and each of the buffers 122a to 122o is transmitted from the main CPU 63 to the management IC 66. However, this is not limited to the above, and the correspondence information may be pre-stored in the management IC 66. In this case, it is not necessary to execute a process to cause the management IC 66 to recognize the correspondence information, and therefore it is possible to reduce the processing load on the main CPU 63.

(17) In the first to fourteenth embodiments, the correspondence information indicating the correspondence between the type of information transmitted from the main CPU 63 to the management IC 66 and each of the buffers 122a to 122o is transmitted from the main CPU 63 to the management IC 66 when the supply of operating power to the main CPU 63 starts. However, the present invention is not limited to this. For example, the main CPU 63 and the management IC 66 may be capable of two-way communication, and the correspondence information may be transmitted from the main CPU 63 to the management IC 66 when a signal requesting the transmission of the correspondence information is received from the management IC 66. In this case, the correspondence memory 116 is provided as a non-volatile memory and is configured to be used for both reading and writing, and the correspondence information provided from the main CPU 63 to the management IC 66 after the shipment of the pachinko machine 10 is stored and held in the correspondence memory 116 even if the supply of operating power to the main CPU 63 is stopped. This makes it possible to reduce the frequency with which the correspondence information is transmitted.

(18) In the first to fourteenth embodiments, the correspondence information indicating the correspondence between the type of information transmitted from the main CPU 63 to the management IC 66 and each of the buffers 122a to 122o is transmitted from the main CPU 63 to the management IC 66 using the signal paths 118a to 118g for transmitting the information of the detection results of each ball entry detection sensor 42a to 48a. However, this is not limited to this, and a dedicated signal path may be provided for transmitting the correspondence information from the main CPU 63 to the management IC 66. This allows the management IC 66 to determine what type of information is being received from the main CPU 63 based on the type of buffer 122a to 122o that receives the information.

(19) In the first to fourteenth embodiments, information is transmitted from the main CPU 63 to the management IC 66, but information is not transmitted from the management IC 66 to the main CPU 63. However, the present invention is not limited to this, and information may be transmitted from the management IC 66 to the main CPU 63. For example, various parameters calculated by the management CPU 112 based on the history information may be transmitted to the main CPU 63. In this case, the main CPU 63 may directly execute notification control of the notification means so that a notification corresponding to the contents of the various parameters received is performed, or the main CPU 63 may transmit a command corresponding to the contents of the various parameters received to the audio and light-emitting control device 81, so that a notification corresponding to the contents of the various parameters is performed using the pattern display device 41, the display light-emitting unit 53, and the speaker unit 54.

(20) In the first to fourteenth embodiments, when the supply of operating power to the main CPU 63 is started, various parameters may be calculated by the main CPU 63 or the management CPU 112 based on the history information stored in the history memory 117, and the contents of the calculated various parameters may be notified using the symbol display device 41, the display light-emitting unit 53, the speaker unit 54, etc. In this case, when the game hall opens for business, it is possible to check whether the ball entry state in the game area PA on the previous business day was normal. This configuration may also be applied to the fifteenth to thirty-fourth embodiments.

(21) In the first to fourteenth embodiments, if the various parameters calculated based on the history information stored in the history memory 117 are abnormal, the pachinko machine 10 may be configured not to allow play to begin until a prohibition release operation is performed. The prohibition release operation may be, for example, a configuration in which the launch of game balls is prohibited, a configuration in which the ball entry detection sensors 42a to 49a are disabled, or a configuration in which the winning/losing determination process is not executed even if a winning entry occurs in the first operating port 33 or the second operating port 34. In addition, the prohibition release operation may be an operation in which the power supply of the pachinko machine 10 is turned on again with the reset button 68c pressed, or an operation of an operation means that becomes operable when the gaming machine main body 12 is opened relative to the outer frame 11. This makes it possible to prevent play from being continued in a situation in which the ball entry mode of the game ball in the game area PA is abnormal. In addition, it makes it possible to prevent play from being continued in a situation in which the frequency of occurrence of the opening/closing execution mode is abnormal. This configuration may also be applied to the above 15th to 34th embodiments.

(22) In the first to fourteenth embodiments, although the history information corresponding to the detection results of the ball entry detection sensors 42a to 48a is stored in the history memory 117, the calculation of various parameters using the history information may not be performed by either the main CPU 63 or the management CPU 112. In this case, the history information may be read by an external device electrically connected to the reading terminal 68d, and the calculation of various parameters using the read history information may be performed by the operator performing the reading operation, or the calculation of various parameters using the read history information may be performed in the external device. In this case, it is possible to reduce the processing load of the main CPU 63 and the management CPU 112. This configuration may also be applied to the fifteenth to thirty-fourth embodiments.

(23) In the first to fourteenth embodiments, the management IC 66 is provided with a power supply separate from the main CPU 63, and even if the supply of operating power to the main CPU 63 is stopped, the management IC 66 may be configured to be able to calculate various parameters using history information and output information on the history information or various parameters. This makes it possible to read the history information and various parameters using an external device even in a situation where the supply of operating power to the main CPU 63 is stopped.

(24) In the first to fourteenth embodiments, the read terminal 68d used to read the program from the main ROM 64 is configured to also be used as a terminal used to read history information or various parameters by an external device, but this is not limited to the above, and the terminal used to read history information or various parameters by an external device may be provided separately from the read terminal 68d for reading the program from the main ROM 64. In this case, the terminal used to read history information or various parameters may be provided in the MPU 62, or may be provided in a position on the main control board 61 separate from the MPU 62.

(25) In the first to fourteenth embodiments, the correspondence memory 116, the history memory 117, and the calculation result memory 131 are not limited to being provided as non-volatile storage means such as flash memory. For example, any of the memories 116, 117, and 131 may be provided as volatile storage means that require a supply of power to store and hold information, and backup power may be supplied to the memory so that information can be stored and held even if the supply of operating power to the main CPU 63 is stopped. In this case, a dedicated backup power device may be provided for the memory, or backup power may be supplied to the memory from the power supply and launch control device 78 that supplies backup power to the main RAM 65.

(26) In the first to fourteenth embodiments, the management IC 66 is not limited to a configuration in which the management side CPU 112 is provided as a general-purpose CPU and performs storage processing of history information and calculation processing of various parameters based on the programs and data stored in the management side ROM 113, and a hardware circuit designed to have these functions may be formed in the management IC 66. Specifically, for example, in the first embodiment, when the hardware circuit receives a signal from the main CPU 63 indicating that a game ball has been detected by any of the detection sensors 42a to 48a, the correspondence information corresponding to the buffer that received the signal is stored from the correspondence memory 116 to the history memory 117, and the information of the RTC 115 at that time is stored in the history memory 117. Also, in the sixth embodiment, for example, when the hardware circuit receives a signal from the main CPU 63 indicating that a game ball has been detected by any of the detection sensors 42a to 48a, the counter value corresponding to the buffer that received the signal is incremented by one. Furthermore, when a calculation trigger occurs in the first embodiment or the like, the hardware circuit calculates various parameters using the history information at that time. Furthermore, when a trigger for external output to the read terminal 68d occurs, the hardware circuit outputs the various parameters that are the calculation results to the outside, as well as the history information to the outside.

(27) In the first to fourteenth embodiments, the main CPU 63 and the management IC 66 may be configured as separate chips, as separate boards, or as separate control devices.

(28) The number of game balls entering the outlet 24a is counted, while history information including RTC information may be stored for game balls entering bonus-trigger entry sections that trigger the payout of prize balls and the win/lose determination process, such as the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34. This makes it possible to extract the history of game balls entering bonus-trigger entry sections, while calculating the frequency of game balls entering each bonus-trigger entry section relative to the total number of game balls dispensed.

(29) The configuration may include events other than those in the above embodiments as the predetermined events that trigger the storage of history information. For example, the configuration may be such that at least one of the following events is stored as history information: the lower tray 56a becoming full, the timing at which the full state began, and the timing at which the full state was released; the configuration may be such that at least one of the following events is stored as history information: the tank 75 becoming a ball-free state, the timing at which the ball-free state began, and the timing at which the ball-free state was released; and the configuration may be such that at least one of the following events is stored as history information: the dispensing device 76 becoming an abnormal state, the timing at which the abnormal state of the dispensing device 76 began, and the timing at which the abnormal state of the dispensing device 76 was released. In this case, it is possible to grasp the frequency of occurrence of these events.

(30) In the first embodiment, the 16th buffer 122p of the input port 121 in the management side I/F 111 corresponds to the output instruction signal, which is preset in the design stage of the management IC 66, but this is not limited to the above, and the management IC 66 may recognize that the 16th buffer 122p corresponds to the output instruction signal by transmitting a type identification command from the main CPU 63. In addition, in the first embodiment, the 15th buffer 122o of the input port 121 in the management side I/F 111 corresponds to the setting value update signal, which is preset in the design stage of the management IC 66, but this is not limited to the above, and the management IC 66 may recognize that the 15th buffer 122o corresponds to the setting value update signal by transmitting a type identification command from the main CPU 63. In this case, there is no need to set in advance in the management IC 66 the correspondence between each buffer 122a-122p and the type of signal input to those buffers 122a-122p.

(31) In the first to fourteenth embodiments, the management IC 66 may be configured to transmit a normal operation signal to the main CPU 63 when the management IC 66 is operating normally. In this case, the main CPU 63 can monitor whether the management IC 66 is operating normally.

(32) The display device that displays the setting values being updated in the setting value update process is not limited to the first to fourth notification display devices 201 to 204, and may be the pattern display device 41 or a dedicated display device. Also, the display device that displays the setting values in the setting confirmation process is not limited to the first to fourth notification display devices 201 to 204, and may be the pattern display device 41 or a dedicated display device.

(33) The operation unit operated to update the setting value in the setting value update process is not limited to the update button 68b, and may be the reset button 68c. In addition, the setting key insertion unit 68a may be configured so that positions corresponding to "Setting 1" to "Setting 6" are set as rotation operation positions when a setting key is inserted into the setting key insertion unit 68a and rotated, and the setting value corresponding to the rotation operation position of the setting key insertion unit 68a is set. In addition, the setting key insertion unit 68a may be configured to be capable of being rotated further than the ON position, and each time a rotation operation beyond the ON position is performed, the setting value being updated in the middle of updating may be updated to the next setting value in the sequence.

(34) In the first to tenth and fifteenth to twenty-first embodiments, the first to third notification display devices 69a to 69c are arranged side by side, but they may be arranged side by side vertically, diagonally, or in two rows, one above the other. In the eleventh to fourteenth embodiments, the first to fourth notification display devices 201 to 204 are arranged side by side, but they may be arranged side by side vertically, diagonally, or in two rows, one above the other. In the fifteenth to twenty-first embodiments, the first to fourth notification display devices 201 to 204 may be used as display devices for displaying the results of game history management.

(35) In the first to fourteenth embodiments, the history information used to calculate parameters whose normal values change according to the setting state of the pachinko machine 10 (hereinafter referred to as the history information of the change object) and the history information used to calculate parameters whose normal values do not change according to the setting state of the pachinko machine 10 (hereinafter referred to as the history information of the non-change object) may be stored in different areas in the history memory 117. In this case, when the setting state of the pachinko machine 10 is newly set or when the setting state of the pachinko machine 10 is changed, the area in the history memory 117 in which the history information of the change object is stored may be cleared to "0", while the area in the history memory 117 in which the history information of the non-change object is stored may not be cleared to "0". This allows accurate calculation of parameters whose normal values change according to the setting state of the pachinko machine 10 even after the setting value is changed, and the accuracy of calculation of parameters whose normal values do not change according to the setting state of the pachinko machine 10 can be improved. This configuration may also be applied to the fifteenth to twenty-first embodiments.

(36) In the above fifteenth to twenty-first embodiments, the stack area 222 for specific control and the stack area 224 for non-specific control may be configured not to be designated in advance in the main RAM 65. Even in this case, the areas corresponding to these stack areas 222, 224 will be designated in the main RAM 65 at the design stage of the pachinko machine 10, but if the storage capacity of the area is exceeded and the storage process for information designated in that area is executed, unintended information will be written to an area that was not originally intended, so the main RAM 65 may be configured to be cleared to "0".

(37) In the above fifteenth to twenty-first embodiments, when the clearing process of the main RAM 65 (steps S105, S117) is executed, the work area 221 for specific control and the stack area 222 for specific control are cleared to "0", but the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0". Alternatively, in the clearing process of the main RAM 65 (steps S105, S117), not only the work area 221 for specific control and the stack area 222 for specific control but also the work area 223 for non-specific control and the stack area 224 for non-specific control may be cleared to "0". Also, in the process of clearing the main RAM 65 (steps S105 and S117), not only the specific control work area 221 and the specific control stack area 222 but also the normal counter area 231, the open/close execution mode counter area 232, and the high frequency support mode counter area 233 are cleared to "0", but the calculation result storage area 234 may not be cleared to "0". In this case, it is possible to protect the information stored in the calculation result storage area 234.

(38) In the above fifteenth to twenty-fifth embodiments, the operation for clearing the specific control work area 221 and the specific control stack area 222 to "0" and the operation for clearing the non-specific control work area 223 and the non-specific control stack area 224 to "0" may be different operations. For example, when the supply of operating power to the pachinko machine 10 is started while the reset button 68c is being operated, the specific control work area 221 and the specific control stack area 222 are cleared to "0," and when the supply of operating power to the pachinko machine 10 is started while the update button 68b is being operated, the non-specific control work area 223 and the non-specific control stack area 224 are cleared to "0." This makes it possible to selectively erase each piece of information. In addition, in this configuration, when the supply of operating power to the pachinko machine 10 is started while both the update button 68b and the reset button 68c are being operated, the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control may all be cleared to "0." This makes it possible to improve the ease of use when erasing information from each of the areas 221 to 224 collectively in a configuration that allows selective erasure as described above.

(39) In the above fifteenth to eighteenth and twentieth embodiments, similar to the nineteenth embodiment, the stack pointer information of the main CPU 63 may be saved to the work area 223 for non-specific control when processing corresponding to non-specific control is started, and the saved information may be restored to the stack pointer of the main CPU 63 when processing corresponding to specific control is resumed. This makes it possible to restore the state of the stack pointer of the main CPU 63 to the state before processing corresponding to non-specific control is started when processing corresponding to non-specific control is completed, even if the stack pointer information of the main CPU 63 may change when processing corresponding to non-specific control is started.

(40) In the above fifteenth to twenty-fifth embodiments, a process for collecting information on game history, a process for calculating various parameters using the collected history information, and a process for notifying the results of the calculation are executed as processes corresponding to non-specific control. However, only some of these processes may be executed as processes corresponding to non-specific control, and the rest may be executed as processes corresponding to specific control. Furthermore, in addition to or instead of the process for collecting information on game history, the process for calculating various parameters using the collected history information, and the process for notifying the results of the calculation, a process other than these processes may be executed as processes corresponding to non-specific control. For example, at least one of the processes of fraud monitoring and notifying the results of monitoring may be executed as processes corresponding to non-specific control.

(41) In the above fifteenth to twenty-fifth embodiments, when the main CPU 63 returns from a state in which processing corresponding to non-specific control is being executed to processing corresponding to specific control, none of the flag register, stack pointer, and various registers of the main CPU 63 are saved to the main RAM 65. Alternatively, when the main CPU 63 returns from a state in which processing corresponding to non-specific control is being executed to processing corresponding to specific control, at least some of the information of the flag register, stack pointer, and various registers of the main CPU 63 may be saved to the main RAM 65, and the saved information may be restored to the corresponding memory area of the main CPU 63 when the processing corresponding to non-specific control is started again. This makes it possible to carry over and use the information of the main CPU 63 used in the processing corresponding to non-specific control.

(42) In the above fifteenth to twenty-fifth embodiments, various parameters are calculated when the total number of game balls discharged from the play area reaches 6,000. However, the total number of game balls that triggers the calculation may be more or less than 6,000. For example, various parameters may be calculated when the total number of game balls discharged from the play area reaches 60,000. In this case, the memory capacity required to store the game history information increases, but by storing the game history information in the management RAM 241 external to the MPU 62 as in the twenty-first embodiment, it is possible to flexibly respond to the increase in memory capacity.

(43) In the above fifteenth to twenty-fifth embodiments, the 61st to 68th parameters are calculated as the result of managing the game history. However, in addition to or instead of this, at least some of the 31st, 41st, and 42nd parameters in the first embodiment may be calculated.

(44) In the above fifteenth to twenty-fifth embodiments, when a process for newly setting the setting state of the pachinko machine 10 is executed or when the setting state of the pachinko machine 10 is changed, not only the work area 221 for specific control and the stack area 222 for specific control but also the work area 223 for non-specific control and the stack area 224 for non-specific control may be configured to be cleared to "0". In this case, when a process for newly setting the setting state of the pachinko machine 10 is executed or when the setting state of the pachinko machine 10 is changed, the normal counter area 231, the counter area 232 for the open/close execution mode, the counter area 233 for the high frequency support mode, and the calculation result storage area 234 are cleared to "0".

In addition, when a process for newly setting the setting state of the pachinko machine 10 is executed or when the setting state of the pachinko machine 10 is changed, not only the work area 221 for specific control and the stack area 222 for specific control but also the normal counter area 231, the counter area for opening/closing execution mode 232, and the counter area for high frequency support mode 233 are cleared to "0", but the calculation result storage area 234 may not be cleared to "0". In this case, it is possible to protect the information stored in the calculation result storage area 234.

In addition, when a process for setting a new setting state of the pachinko machine 10 is executed or when the setting state of the pachinko machine 10 is changed, the work area 221 for specific control and the stack area 222 for specific control are cleared to "0", but the work area 223 for non-specific control and the stack area 224 for non-specific control may not be cleared to "0". In this case, it is possible to protect the information stored in the work area 223 for non-specific control and the stack area 224 for non-specific control.

In addition, if the configuration (43) above is provided, when a process for newly setting the setting state of the pachinko machine 10 is executed or when the setting state of the pachinko machine 10 is changed, the history information for calculating the 31st parameter, 41st parameter, and 42nd parameter in the first embodiment above is erased, but the normal counter area 231, the open/close execution mode counter area 232, the high frequency support mode counter area 233, and the calculation result storage area 234 may not be cleared to "0".

(45) In the first to twenty-fifth embodiments described above, instead of using the total number of game balls discharged from the game area PA to calculate various parameters, the total number of game balls supplied to the game area PA may be used. In this case, for example, a detection sensor may be provided to detect game balls that have been launched from the game ball launching mechanism 27 and reached the game area PA, and the number of game balls supplied to the game area PA may be measured based on the detection result of the detection sensor. In this configuration, since it is not necessary to measure the number of game balls discharged from the outlet 24a, the outlet detection sensor 48a may not be provided.

(46) In the above fifteenth to twenty-fifth embodiments, at least a portion of the information in the various registers and stack pointer of the main CPU 63 may be saved to the stack area 222 for specific control or the stack area 224 for non-specific control by a load command. In this case, it is necessary to update the information in the stack pointer of the main CPU 63 when saving the information to the stack areas 222, 224. It is also possible to configure the information saved in the stack areas 222, 224 to be restored to the corresponding memory area of the main CPU 63 by a load command. In this case, too, it is necessary to update the information in the stack pointer of the main CPU 63 when restoring the information from the stack areas 222, 224.

(47) In each of the above embodiments, when the setting value update process is being executed, a corresponding notification may be issued by any of the pattern display device 41, the display light-emitting unit 53, and the speaker unit 54. This allows the manager of the gaming hall to clearly understand that the setting value update process is being executed.

(48) In each of the above embodiments, the history of newly set values may be stored in the main RAM 65. The history of newly set values may also be stored in a RAM provided in the audio/light-emitting control device 81. In this case, a command including information on the set value set in the set value update process is sent from the main CPU 63 to the audio/light-emitting control device 81 each time the set value update process is completed, and each time the audio/light-emitting control device 81 receives the command, information indicating that a new set value has been set and information indicating the set value at that time are cumulatively stored in the RAM of the audio/light-emitting control device 81. In this configuration, when a specified operation is performed, the setting history of the set values cumulatively stored in the RAM of the audio/light-emitting control device 81 may be displayed on the pattern display device 41.

(49) In each of the above embodiments, when a new setting value is set in the setting value update process, the information indicating the number of game balls to be paid out stored in the payout control device 77 is not erased. Alternatively, the information indicating the number of game balls to be paid out may be erased. Also, when the setting value update process is executed but the setting value is not changed, the information indicating the number of game balls to be paid out may not be erased, and when the setting value is changed, the information indicating the number of game balls to be paid out may be erased.

(50) In each of the above embodiments, when the setting value update process is executed but the setting value is not changed, the areas 221-224 of the main RAM 65 are not cleared to "0", and when the setting value is changed, at least some of the areas 221-224 of the main RAM 65 are cleared to "0". For example, when the setting value is changed, the areas other than the setting value counter in the work area 221 for specific control may be cleared to "0".

(51) In the above 22nd to 25th embodiments, the movement of the movable object related to the profit of the game may be continued even in a situation where the main CPU 63 is executing a process for confirming the setting value in the setting confirmation process (FIG. 87). For example, in a configuration in which a V zone and a non-V zone are provided in the ball entry means that allows balls to enter in the open/close execution mode, and a distribution member that distributes game balls that have entered the ball entry means to either the V zone or the non-V zone is provided, the operation of the distribution member may be continued even in a situation where the process for confirming the setting value is being executed in the setting confirmation process. In this case, it is possible to make it impossible to fraudulently create a situation in which the process for confirming the setting value is executed in the setting confirmation process and stop the operation of the distribution member. In addition to the above-mentioned distribution member, a movable object that continues to operate even when the process for confirming the setting value is being executed in the setting confirmation process can be a distribution member that distributes game balls to either an advantageous opening, which will result in a round of play being generated when a game ball enters the ball entry means, or an outlet, which will discharge a game ball that has entered the ball entry means without allowing it to enter the advantageous opening.

(52) In the above twenty-second to twenty-fifth embodiments, at least one of the work area 223 for non-specific control and the stack area 224 for non-specific control may be configured not to be monitored for information abnormalities. In this case, even if it is determined that an information abnormality has occurred in the work area 221 for specific control and the stack area 222 for specific control, by configuring the work area 223 for non-specific control and the stack area 224 for non-specific control not to be cleared to "0", it is possible to prevent a situation from occurring in which the work area 223 for non-specific control and the stack area 224 for non-specific control are cleared to "0" based on the occurrence of an information abnormality.

(53) In the above 22nd to 25th embodiments, the monitoring of whether or not an information abnormality has occurred in the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control may all be performed by processing corresponding to non-specific control. Also, the processing for clearing each of the areas 221 to 224 to "0" when an information abnormality has occurred may all be performed by processing corresponding to non-specific control.

(54) In each of the above embodiments, the main RAM 65 requires a power supply to store and retain information, and backup power is supplied to the main RAM 65 even when the power to the pachinko machine 10 is turned off. However, the main RAM 65 may be configured as a non-volatile memory that does not require a power supply to store and retain information.

(55) In each of the above embodiments, in the various clearing processes of the main RAM 65, instead of a configuration in which the target area of the main RAM 65 is initialized by executing a process of clearing to "0" and a process of initializing the target area, a configuration in which the target area is initialized by executing a process of initializing without executing a process of clearing to "0" may also be adopted.

(56) In each of the above embodiments, if the setting key insertion section 68a is turned ON when the supply of operating power to the main CPU 63 is started, the setting value update process may be executed without requiring any other operation. Also, instead of the setting key insertion section 68a that is turned ON/OFF by the setting key, a setting switch that is turned ON/OFF directly by hand may be provided. Also, if the setting key insertion section 68a is not provided, and the reset button 68c is pressed when the supply of operating power to the main CPU 63 is started, the setting value update process may be executed without requiring any other operation. In this case, a cover member may be provided so that it can be switched between a closed state that covers the reset button 68c and an open state that does not cover it, and a locking device may be provided to lock the cover member in the closed position.

(57) In the setting value update process, if the setting key insertion section 68a is held in the OFF position for a predetermined period of time, the selected setting value may be confirmed and the setting value update process may be terminated. In addition, if a termination reference period (e.g., 5 minutes) has elapsed since the setting value update process was started, the selected setting value may be automatically confirmed and the setting value update process may be terminated. In addition, in the setting value update process, if the update button 68b or the reset button 68c is pressed and held for a period of time equal to or longer than the termination reference period (e.g., 10 seconds), the selected setting value may be confirmed and the setting value update process may be terminated.

(58) In a configuration in which the setting key insertion section 68a can be rotated further than the ON position, and the setting value being updated is updated to the next setting value in sequence each time the setting key insertion section 68a is rotated beyond the ON position, a setting confirmation process that enables confirmation of the setting value may be started when the supply of operating power to the main CPU 63 is started with the setting key insertion section 68a operated to the ON position, and the setting confirmation process may be ended when the setting key insertion section 68a is operated to the OFF position. Also, a setting confirmation process that enables confirmation of the setting value may be started when the supply of operating power to the main CPU 63 is started with the update button 68b or the reset button 68c pressed, and the setting confirmation process may be ended when the pressing of the button is released. Also, instead of the setting key insertion section 68a that is turned ON/OFF by the setting key, a setting switch that is turned ON/OFF directly by hand is provided, and when the setting switch is turned ON and the supply of operating power to the main CPU 63 is started, the setting confirmation process that allows the setting value to be confirmed may be started, and when the setting switch is turned OFF or turned ON after the OFF operation, the setting confirmation process may be ended. Also, instead of the setting key insertion section 68a that is turned ON/OFF by the setting key, a setting switch that is turned ON/OFF directly by hand is provided, and when the setting switch is turned ON and the supply of operating power to the main CPU 63 is started, the setting confirmation process that allows the setting value to be confirmed may be started, and when the reset button 68c is pressed, the setting confirmation process may be ended.

(59) Instead of a configuration in which the display control device 82 is controlled by the audio and light emission control device 81 based on a command transmitted from the main control device 60, the display control device 82 may be configured to control the audio and light emission control device 81 based on a command transmitted from the main control device 60. Also, instead of a configuration in which the audio and light emission control device 81 and the display control device 82 are provided separately, both control devices may be provided as a single control device, the functions of one of the two control devices may be integrated into the main control device 60, or both functions of the two control devices may be integrated into the main control device 60. Also, the configuration of the command transmitted from the main control device 60 to the audio and light emission control device 81 and the configuration of the command transmitted from the audio and light emission control device 81 to the display control device 82 may be arbitrary.

(60) The present invention can also be applied to other types of pachinko machines that differ from the above-described embodiments, such as pachinko machines in which an electric device opens a predetermined number of times when a gaming ball enters a specific area of a special device, pachinko machines in which a right is generated and a jackpot is awarded when a gaming ball enters a specific area of a special device, pachinko machines equipped with other devices, arrange ball machines, mahjong ball machines, and other gaming machines.

The present invention can also be applied to non-pinball gaming machines, such as slot machines, which have multiple reels with multiple patterns circumferentially attached, and which start the rotation of the reels by inserting a medal and operating a start lever, and which, after the reels stop when a stop switch is operated or a predetermined time has passed, award the player with a special prize, such as a medal payout, if a specific pattern or combination of specific patterns is formed on a winning line visible through a display window.

The present invention can also be applied to a gaming machine that combines a pachinko machine and a slot machine, in which the gaming machine body is supported on an outer frame so that it can be opened and closed, has a storage section and an intake device, and the reels start to rotate when a start lever is operated after a predetermined number of gaming balls stored in the storage section have been taken in by the intake device.

When the present invention is applied to a slot machine or a gaming machine that combines a pachinko machine and a slot machine, for example, the result of the lottery process for the role executed when starting one game based on the operation of the start lever may be stored as history information, and the actual probability of winning for each role may be calculated using the history information. When a transition to a special gaming state such as a bonus game occurs, it may be stored as history information, and the actual probability of transition to the special gaming state may be calculated using the history information. Alternatively, the ratio of the number of games stayed in the special gaming state to the total number of games played may be calculated. The history information and various parameters may be readable by an external device, or a notification corresponding to the calculation result of various parameters may be made by the gaming machine itself. In addition, a configuration may be made in which there are multiple setting states such as "Setting 1" to "Setting 6," and the winning probability in the lottery process for the role may be changed depending on the setting state. In this case, the configurations in the above embodiments may be applied to the handling of history information when the setting state is newly set or the setting value is changed, the calculation of various parameters, and the handling of repeated changes.

(61) The characteristic configurations of the first to thirty-fourth embodiments may be applied to each other in any combination. For example, the characteristic configurations of the first embodiment, the sixth embodiment, the tenth embodiment, and the thirtieth embodiment may be combined; the characteristic configurations of the second embodiment, the fourth embodiment, the eighth embodiment, the eleventh embodiment, and the thirty-third embodiment may be combined; the characteristic configurations of the first embodiment, the fifteenth embodiment, the twenty-first embodiment, the twenty-ninth embodiment, and the thirty-fourth embodiment may be combined; and the characteristic configurations of the second embodiment, the sixteenth embodiment, and the twenty-second embodiment may be combined. In addition, the configurations of the other forms may be applied in any combination to a configuration in which the characteristic configurations of the first to thirty-fourth embodiments are applied in a predetermined combination.

<Inventions extracted from the above embodiments>
The following describes the features of the inventions extracted from each of the above-mentioned embodiments, while indicating, as necessary, the effects, etc. In the following, for ease of understanding, the corresponding configurations in each of the above-mentioned embodiments are appropriately indicated in parentheses, but the present invention is not limited to the specific configurations indicated in parentheses.

<Features Group A>
Feature A1. A setting means (a function for executing a setting value update process in the master CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
a history storage execution means (a function of executing a history setting process in the management CPU 112) for storing history information of a game corresponding to a predetermined event that occurs as a result of the game being played in a history storage means (a history memory 117);
an information erasing means for erasing at least a part of the history information stored in the history storage means when at least one condition is that the setting value to be used has been set by the setting means (a function for executing the process of step S1809 in the management CPU 112 in the third embodiment, a function for executing the process of step S2109 in the management CPU 112 in the fifth embodiment, a function for executing the processes of steps S2306 to S2308 in the management CPU 112 in the sixth embodiment, and a function for executing the process of step S2608 in the management CPU 112 in the eighth embodiment);
A gaming machine comprising:

According to feature A1, the setting value to be used is set from among multiple setting values corresponding to the player's degree of advantage, so the player will expect that the more advantageous setting value will be the one to be used. Furthermore, when a specified event occurs, corresponding history information is stored in the history storage means. This makes it possible for the gaming machine to store and hold information for managing the number of times or frequency of occurrence of a specified event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a specified event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information.

In this case, at least a portion of the history information stored in the history storage means is erased when at least one of the conditions is that the setting value to be used has been newly set. This makes it possible to adjust the contents of the history storage means so that the frequency of occurrence of a specified event can be appropriately managed in a situation after the setting value to be used has been newly set.

Feature A2. A ball entry means (first actuation port 33, second actuation port 34) through which a game ball flowing down the game area can enter;
An information acquisition means (a function for executing the process of step S401 in the main CPU 63) for acquiring special information based on the game ball entering the ball entry means;
An assignment determination means (a function for executing the processes of steps S503 and S504 in the main CPU 63) for determining whether the special information corresponds to the assignment information;
A bonus awarding means (a function for executing the processes of steps S409 to S412 in the master CPU 63) for awarding a bonus (opening/closing execution mode) to a player based on the result of the bonus correspondence that the special information corresponds to the bonus information in the bonus determination,
A gaming machine according to feature A1, characterized in that the probability of the award corresponding result being obtained in the award judgment varies depending on the set value.

According to feature A2, it is possible to vary the probability of a grant corresponding result in accordance with a set value in a so-called pachinko machine. In this case, by having the configuration of feature A1 described above, it is possible to adjust the contents of the history storage means so as to appropriately manage the frequency of occurrence of a specified event in a situation after the probability of a grant corresponding result has been changed.

Feature A3. The gaming machine according to feature A1 or A2, characterized in that the information erasing means erases all of the history information stored in the history storage means under at least one condition that the setting value to be used has been set by the setting means.

According to feature A3, when the setting value to be used is newly set, all history information stored in the history storage means is erased, making it possible to identify the frequency of occurrence of a specified event based on the timing when the setting value to be used is newly set.

Feature A4. The gaming machine according to feature A1 or A2, characterized in that the information erasing means erases a portion of the history information stored in the history storage means and leaves a portion of the history information stored in the history storage means, on at least one condition that the setting value to be used has been set by the setting means.

According to feature A4, when a new setting value to be used is set, it is possible to erase history information that is not necessary for managing the frequency of occurrence of a specified event thereafter, and to leave history information that is necessary for managing the frequency of occurrence of a specified event thereafter. This makes it possible to appropriately manage the frequency of occurrence of a specified event after a new setting value to be used is set.

Feature A5. The history information stored in the history storage means includes first history information (history information indicating that an opening/closing execution mode has occurred) in which the occurrence probability of the predetermined event corresponding to the history information varies according to the set value, and second history information (history information indicating that a game ball has been discharged from the game area PA) in which the occurrence probability does not vary according to the set value,
The gaming machine described in feature A4, characterized in that the information erasing means erases the first history information stored in the history storage means and leaves the second history information stored in the history storage means, under at least one condition that the setting value to be used has been set by the setting means.

According to feature A5, when a new setting value to be used is set, the first history information corresponding to a predetermined event whose occurrence probability varies according to the setting value is erased, and the second history information corresponding to a predetermined event whose occurrence probability does not vary according to the setting value is not erased. As a result, if the first history information before the setting value to be used is newly set is carried over after the setting value is newly set, the first history information that is not preferable for identifying the occurrence frequency of the predetermined event corresponding to the first history information can be erased when the setting value is newly set. On the other hand, by not erasing the second history information even if the setting value to be used is newly set, it is possible to secure a large number of second history information to be referenced when identifying the occurrence frequency of the predetermined event corresponding to the second history information, and therefore it is possible to accurately identify the occurrence frequency of the predetermined event corresponding to the second history information.

Feature A6. A ball entry means (first actuation port 33, second actuation port 34) through which a game ball flowing down the game area can enter;
An information acquisition means (a function for executing the process of step S401 in the main CPU 63) for acquiring special information based on the game ball entering the ball entry means;
An assignment determination means (a function for executing the processes of steps S503 and S504 in the main CPU 63) for determining whether the special information corresponds to the assignment information;
A bonus awarding means (a function for executing the processes of steps S409 to S412 in the master CPU 63) for awarding a bonus (opening/closing execution mode) to a player based on the result of the bonus correspondence that the special information corresponds to the bonus information in the bonus determination,
The probability of the award corresponding result being obtained in the award determination varies according to the set value,
the first history information includes information corresponding to the granting of the benefit,
The gaming machine described in feature A5, wherein the second history information includes information corresponding to the ejection of a gaming ball from the gaming area in a predetermined manner.

According to feature A6, the probability of awarding a bonus varies depending on the set value, so by erasing the first history information when a new set value to be used is set, it becomes possible to determine the frequency of awarding a bonus under the circumstances of the newly set set value. On the other hand, since the frequency with which game balls are discharged from the game area does not vary depending on the set value, by not erasing the second history information even when a new set value to be used is set, it becomes possible to accurately determine the frequency with which game balls are discharged from the game area in a predetermined manner.

Feature A7. The gaming machine according to any one of Features A1 to A6, wherein the information erasing means erases at least a portion of the history information when the setting value to be used is set by the setting means and a predetermined amount or more of the history information is stored in the history storage means.

According to feature A7, if the history storage means does not store a predetermined amount of predetermined history information, the history information is not erased even if a new setting value to be used is set. This makes it possible to prevent the history information from being repeatedly erased in the history storage means even if new setting values are repeatedly set in a situation where play is not being performed.

Feature A8. A gaming machine according to any one of Features A1 to A7, characterized in that it is equipped with information derivation means (a function for executing the process of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the process of step S2107 in the management CPU 112 in the fifth embodiment) that derives aspect information corresponding to the results of a game during a predetermined period of time using the history information stored in the history storage means, with at least one condition being that the setting value to be used has been set by the setting means.

According to Feature A8, in a configuration including Feature A1 above, in which at least a portion of the history information stored in the history storage means is erased when at least one condition is that a new setting of a setting value to be used is made, when a new setting of a setting value to be used is made, behavior information corresponding to the game results during a specified period is derived using the history information stored in the history storage means. As a result, even if at least a portion of the history information is erased when a setting value is changed, it is possible to grasp the results of game history management, such as the frequency of occurrence of a specified event in the situation before the setting value was changed.

Feature A9. The gaming machine described in Feature A8, characterized in that it is provided with a behavior information storage means (separate storage memory 171) that stores the behavior information derived by the information derivation means.

According to feature A9, when a new setting of the setting value to be used is made and the history information stored in the history storage means is used to derive behavior information corresponding to the game results during a specified period, the behavior information is stored in the behavior information storage means. As a result, even if the setting value is changed, it is possible to grasp the management results of the game history in the situation before the setting value was changed at any time thereafter.

Feature A10. The gaming machine described in Feature A9, wherein the mode information storage means is capable of storing a plurality of pieces of mode information.

According to feature A10, since it is possible to store multiple pieces of behavior information in the behavior information storage means, it is possible to grasp the results of managing the game history over multiple periods based on the timing at which the setting value was newly set. In addition, even if new setting of the setting value is repeatedly performed in a situation where no game is being played, it is possible to increase the likelihood that behavior information derived using history information of a situation where game play is actually being performed will remain in the behavior information storage means.

Feature A11. The aspect information storage means is capable of storing a predetermined number of the aspect information,
This gaming machine is characterized by being equipped with a means for executing special processing when the setting of the setting value to be used by the setting means occurs more than the specified number of times under specified conditions (in the third embodiment, a function for executing monitoring processing of repeated changes in the management CPU 112, and in the fourth embodiment, a function for executing monitoring processing of repeated changes in the main CPU 63), as described in feature A9 or A10.

According to feature A11, when new setting values are repeatedly set in a situation where no game is being played, special processing is executed in order to prevent the behavior information derived using the history information of the situation where the game is actually being played from remaining in the behavior information storage means. This makes it possible to deal with such behavior.

Feature A12. The gaming machine according to any one of Features A8 to A11, wherein the information derivation means derives the behavior information when a predetermined amount or more of the history information is stored in the history storage means.

According to feature A12, since behavior information is derived when a predetermined amount or more of predetermined history information is stored in the history storage means, it is possible to prevent behavior information from being derived unnecessarily.

Feature A13. The gaming machine according to any one of Features A1 to A12, characterized in that the information erasing means does not erase the history information until a specific amount or more of the predetermined history information is stored in the history storage means after the setting means sets the setting value to be used, and erases the history information stored in the history storage means before the setting value was set when a specific amount or more of the predetermined history information is stored in the history storage means after the setting means sets the setting value to be used.

According to feature A13, even if a new setting of the setting value to be used is made, the history information stored before the setting is made is not erased until a specific amount of predetermined history information is newly stored in the history storage means. This makes it possible to identify the management results of the game history for a specified period of time even if a new setting of the setting value is made.

Feature A14: The history storage means includes a first history storage means (first history memory 191) and a second history storage means (second history memory 192);
The history storage execution means includes:
a means for storing the history information corresponding to the predetermined event in both the first history storage means and the second history storage means when the predetermined event occurs during a predetermined period from when the setting value to be used is set by the setting means to when a release condition is satisfied (a function for executing the process of step S2604 in the management CPU 112);
a means for storing the corresponding history information in one of the first history storage means and the second history storage means, which is set as a storage target, when the specified event occurs during a period other than the specified period (a function for executing the process of step S2603 in the management side CPU 112);
Equipped with
A gaming machine described in any one of features A1 to A13, characterized in that when the release condition is met, the information erasing means erases the history information stored in the first history storage means or the second history storage means, whichever was previously set as the storage target.

According to feature A14, even if a new setting value to be used is set, the history information stored before the setting is made is not erased until a specific amount of history information is newly stored in the history storage means. This makes it possible to identify the results of managing the game history for a specified period of time even if a new setting value is set. In addition, this effect can be achieved simply by appropriately changing the history storage means to store the history information between the first history storage means and the second history storage means.

Feature A15. The gaming machine described in Feature A14, characterized in that it is equipped with information derivation means (a function for executing the process of step S2703 in the management CPU 112) that derives behavior information corresponding to the results of a game during a predetermined period of time using the history information stored in the one of the first history storage means and the second history storage means that is set as the storage target.

According to feature A15, even in a situation where a new setting of the set value causes history information to be stored in both the first history storage means and the second history storage means, it is possible to appropriately derive behavior information using the history information.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features A1 to A15. This allows for a synergistic effect to be achieved through the combined configuration.

<Characteristics Group B>
Feature B1. A setting means (a function for executing a setting value update process in the master CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
a history storage execution means (a function of executing a history setting process in the management CPU 112) for storing history information of a game corresponding to a predetermined event that occurs as a result of the game being played in a history storage means (a history memory 117);
Equipped with
A gaming machine characterized in that the specified history information stored in the history storage means before the setting value to be used is set by the setting means is stored and retained in the history storage means even after the setting value to be used is set by the setting means.

According to feature B1, the setting value to be used is set from among multiple setting values corresponding to the player's degree of advantage, so the player will expect that the more advantageous setting value will be the one to be used. Furthermore, when a specified event occurs, corresponding history information is stored in the history storage means. This makes it possible for the gaming machine to store and hold information for managing the number of times or frequency of occurrence of a specified event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a specified event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information.

In this case, even if a new setting value to be used is set, the history information stored in the history storage means is not erased but is retained. This makes it possible to continue storing the previous history information in the history storage means even if a new setting value to be used is set, and makes it possible to identify the results of game history management by using the history information accumulated in the history storage means over a long period of time.

Feature B2. The gaming machine described in Feature B1, characterized in that the history storage execution means includes a setting time storage execution means (a function for executing the process of step S1307 in the management CPU 112 in the first embodiment, and a function for executing the process of step S2408 in the management CPU 112 in the seventh embodiment) that stores the corresponding history information in the history storage means when the setting value to be used is set by the setting means.

According to feature B2, in a configuration in which history information is not erased but is stored and maintained even when a new setting value to be used is set, history information corresponding to the new setting of the setting value to be used is stored in the history storage means. This makes it possible to distinguish between history information before the new setting value to be used is set and history information after it is set.

Feature B3. The gaming machine according to Feature B2, wherein the setting storage execution means stores information corresponding to the set setting value as the history information in the history storage means when the setting value to be used is set by the setting means.

Feature B3 makes it possible to identify the contents of previously set values by referring to history information.

Feature B4. A gaming machine according to any one of Features B1 to B3, characterized in that the history storage means includes a plurality of corresponding history storage means (history memories 181 to 186 for settings 1 to 6) corresponding to the plurality of types of setting values that can be set by the setting means.

According to feature B4, since a correspondence history storage means is provided corresponding to each set value, it is possible to store history information separately for each set value.

Feature B5. A gaming machine according to Feature B4, characterized in that when the setting means sets the setting value to be used, the corresponding history storage means corresponding to the set setting value is set as the storage target for the history information thereafter (a function for executing the process of step S2406 in the management CPU 112).

According to feature B5, when a new setting value to be used is set, the corresponding history storage means corresponding to that setting value is set as the storage target for subsequent history information, making it possible to store history information separately for each setting value.

Feature B6. The gaming machine described in Feature B5 is characterized in that it is equipped with information derivation means (a function for executing display output processing in the management CPU 112) that derives behavior information corresponding to game results during a predetermined period of time using the history information stored in the corresponding history storage means that is the storage target.

According to feature B6, in a configuration in which history information is stored separately for each setting value, it is possible to derive mode information corresponding to the currently set setting value.

Feature B7. A ball entry means (first actuation port 33, second actuation port 34) through which a game ball flowing down the game area can enter;
An information acquisition means (a function for executing the process of step S401 in the main CPU 63) for acquiring special information based on the game ball entering the ball entry means;
An assignment determination means (a function for executing the processes of steps S503 and S504 in the main CPU 63) for determining whether the special information corresponds to the assignment information;
A bonus awarding means (a function for executing the processes of steps S409 to S412 in the master CPU 63) for awarding a bonus (opening/closing execution mode) to a player based on the result of the bonus correspondence that the special information corresponds to the bonus information in the bonus determination,
A gaming machine according to any one of features B1 to B6, characterized in that the probability of the award corresponding result being obtained in the award determination varies depending on the set value.

Feature B7 makes it possible to vary the probability of a corresponding result being awarded in a so-called pachinko machine according to a set value.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features B1 to B7. This allows for a synergistic effect to be achieved through the combined configuration.

<Characteristics Group C>
Feature C1. A setting means (a function for executing a setting value update process in the master CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
a history storage execution means (a function of executing a history setting process in the management CPU 112) for storing history information of a game corresponding to a predetermined event that occurs as a result of the game being played in a history storage means (a history memory 117);
a post-setting handling means (a function for executing the processes of step S2506 and steps S2605 to S2609 in the management CPU 112) that does not erase the history information from the time when the setting value to be used is set by the setting means until a specific amount or more of the predetermined history information is stored in the history storage means;
A gaming machine comprising:

According to feature C1, the setting value to be used is set from among multiple setting values corresponding to the player's degree of advantage, so the player will expect that the more advantageous setting value will be the one to be used. Furthermore, when a specified event occurs, corresponding history information is stored in the history storage means. This makes it possible for the gaming machine to store and hold information for managing the number of times or frequency of occurrence of a specified event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a specified event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information.

In this case, even if a new setting of the setting value to be used is made, the history information stored before the setting is made will not be erased until a specific amount of predetermined history information is newly stored in the history storage means. This makes it possible to identify the management results of the game history for a specified period of time even if a new setting of the setting value is made.

Feature C2. The gaming machine described in Feature C1, wherein the post-setting response means erases the history information stored in the history storage means before the setting value was set when the history information stored in the history storage means is equal to or exceeds the specific amount after the setting value to be used is set by the setting means.

According to feature C2, when a specific amount of history information that enables the determination of the management results of the game history for a specific period of time after the setting value is newly set is stored in the history storage means, the history information that was stored in the history storage means before the setting value was newly set is erased. This makes it possible to prevent unnecessary history information from continuing to be stored in the history storage means.

Feature C3. The history storage means includes a first history storage means (first history memory 191) and a second history storage means (second history memory 192),
The history storage execution means includes:
a means for storing the history information corresponding to the predetermined event in one of the first history storage means and the second history storage means, which is set as a storage target when the predetermined event occurs (a function for executing the process of step S2603 in the management side CPU 112);
a means for storing the history information corresponding to the occurrence of the predetermined event in both the first history storage means and the second history storage means until the predetermined amount or more of the history information is stored in the one of the first history storage means and the second history storage means that is not set as the storage target from the time when the setting value to be used is set by the setting means, (a function for executing the process of step S2604 in the management side CPU 112);
Equipped with
The post-setting response means includes:
a means for changing the storage target between the first history storage means and the second history storage means when a predetermined amount or more of history information is stored in the one of the first history storage means and the second history storage means that is not set as the storage target after the setting value to be used is set by the setting means; and
a means for deleting the history information of the one of the first history storage means and the second history storage means that has been set as the storage target up until that point, when the predetermined amount of history information is stored in the one of the first history storage means and the second history storage means that has not been set as the storage target after the setting means has set the setting value to be used; and
The gaming machine according to feature C1 or C2, characterized in that it is equipped with:

According to feature C3, even if a new setting value to be used is set, the history information stored before the setting is made is not erased until a specific amount of history information is newly stored in the history storage means. This makes it possible to identify the results of managing the game history for a specified period of time even if a new setting value is set. In addition, this effect can be achieved simply by appropriately changing the history storage means to store the history information between the first history storage means and the second history storage means.

Feature C4. The gaming machine described in Feature C3 is characterized in that it is equipped with information derivation means (a function for executing the process of step S2703 in the management CPU 112) that derives behavior information corresponding to the results of a game during a predetermined period of time using the history information stored in the one of the first history storage means and the second history storage means that is set as the storage target.

According to feature C4, even in a situation where a new setting of the set value causes history information to be stored in both the first history storage means and the second history storage means, it is possible to appropriately derive behavior information using the history information.

Feature C5. A ball entry means (first actuation port 33, second actuation port 34) through which a game ball flowing down the game area can enter;
An information acquisition means (a function for executing the process of step S401 in the main CPU 63) for acquiring special information based on the game ball entering the ball entry means;
An assignment determination means (a function for executing the processes of steps S503 and S504 in the main CPU 63) for determining whether the special information corresponds to the assignment information;
A bonus awarding means (a function for executing the processes of steps S409 to S412 in the master CPU 63) for awarding a bonus (opening/closing execution mode) to a player based on the result of the bonus correspondence that the special information corresponds to the bonus information in the bonus determination,
A gaming machine according to any one of features C1 to C4, characterized in that the probability of the award corresponding result being obtained in the award judgment varies depending on the set value.

Feature C5 makes it possible to vary the probability of a corresponding result being awarded in a so-called pachinko machine according to a set value.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features C1 to C5. This allows for a synergistic effect to be achieved through the combined configuration.

<Feature D group>
Feature D1. A setting means (a function for executing a setting value update process in the master CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
a special execution means for executing a special process under at least one condition that the setting of the setting value to be used by the setting means is executed in a special situation (a function for executing a process for monitoring repeated changes in the management CPU 112 in the third embodiment, a function for executing a process for monitoring repeated changes in the main CPU 63 in the fourth embodiment, and a function for making a negative determination in step S2106 in the management CPU 112 in the fifth embodiment);
A gaming machine comprising:

According to feature D1, the setting value to be used is set from among multiple setting values corresponding to the player's degree of advantage, so the player will hope that the more advantageous setting value will be the setting value to be used. In this case, special processing is executed under at least one condition that the new setting value to be used is set in a special situation. This makes it possible to deal with cases in which a new setting value is set under unfavorable circumstances.

Feature D2. The gaming machine described in Feature D1, wherein the special execution means executes the special process under at least one condition that the setting of the setting value to be used by the setting means has been executed a specific number of times or more in the special situation.

According to feature D2, even if a new setting of the setting value to be used in a special situation is performed, if the number of times the setting value is set is less than a specific number of times, the special processing is not performed. This makes it possible to prevent the special processing from being performed even when a regular worker sets a new setting value in a special situation less than a specific number of times.

Feature D3. The gaming machine described in Feature D1 or D2, characterized in that the special execution means executes the special process under at least one condition that the setting of the setting value to be used by the setting means has been executed in a situation where, as the special situation, a game has not been played since the setting of the setting value to be used by the setting means has been executed or a game has not been played at a predetermined level since the setting of the setting value to be used by the setting means has been executed.

According to feature D3, when a new setting value to be used is set in a situation where no game is being played or where no game is being played substantially, special processing is executed, so that it is possible to deal with such an action when it occurs.

Feature D4. A gaming machine according to any one of features D1 to D3, characterized in that the special execution means executes a notification process as the special process.

According to feature D4, the notification process is executed under at least one condition that a new setting of the setting value to be used is performed in a special situation. This makes it possible to prompt the user to take action when a new setting of the setting value is performed under unfavorable circumstances.

Feature D5. A history storage execution means (a function for executing a history setting process in the management CPU 112) for storing history information of a game corresponding to a predetermined event that occurs as a result of the game being played in the history storage means (history memory 117);
information derivation means for deriving aspect information corresponding to game results during a predetermined period of time using the history information stored in the history storage means, with at least one condition being that the setting value to be used has been set by the setting means (a function for executing the process of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the process of step S2107 in the management CPU 112 in the fifth embodiment);
A gaming machine described in any one of features D1 to D4, characterized in that it is equipped with:

According to feature D5, when a specified event occurs, the corresponding history information is stored in the history storage means. This makes it possible for the gaming machine to store and hold information for managing the number of times or frequency of occurrence of the specified event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of the specified event. In addition, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information.

In this case, when a new setting value to be used is set, the history information stored in the history storage means is used to derive behavior information corresponding to the game results during a specified period. This makes it possible to grasp the results of game history management, such as the frequency of occurrence of a specified event in the situation before the setting value was changed.

Feature D6. The gaming machine described in Feature D5, wherein the special execution means, under at least one condition that the setting of the setting value to be used by the setting means is executed in the special situation, does not cause the information derivation means to derive the mode information as the special process.

According to feature D6, even if a new setting of the setting value to be used is performed, if the setting is performed in an unfavorable situation, the behavior information is not derived. This makes it possible to prevent the behavior information from being derived unnecessarily.

Feature D7. The gaming machine according to feature D5 or D6, characterized in that it is provided with a behavior information storage means (separate storage memory 171) that stores the behavior information derived by the information derivation means.

According to feature D7, when a new setting of the setting value to be used is made and the history information stored in the history storage means is used to derive behavior information corresponding to the game results during a specified period, the behavior information is stored in the behavior information storage means. As a result, even if the setting value is changed, it is possible to grasp the management results of the game history in the situation before the setting value was changed at any time thereafter.

Feature D8. The gaming machine described in Feature D7, characterized in that the mode information storage means is capable of storing multiple pieces of mode information.

According to feature D8, since it is possible to store multiple pieces of behavior information in the behavior information storage means, it is possible to grasp the results of managing the game history over multiple periods based on the timing when the setting value was newly set. In addition, even if new setting values are repeatedly set in a situation where no game is being played, it is possible to increase the likelihood that behavior information derived using history information of a situation where game play is actually being played will remain in the behavior information storage means.

Feature D9. The aspect information storage means is capable of storing a predetermined number of the aspect information;
The gaming machine described in feature D7 or D8, wherein the special execution means executes the special processing when the setting of the setting value to be used by the setting means occurs more than the specified number of times in the special situation.

According to feature D9, when new setting values are repeatedly set in a situation where no game is being played, special processing is executed in order to prevent the behavior information derived using the history information of the situation where the game is actually being played from remaining in the behavior information storage means. This makes it possible to deal with such behavior.

Feature D10. A ball entry means (first actuation port 33, second actuation port 34) through which a game ball flowing down the game area can enter;
An information acquisition means (a function for executing the process of step S401 in the main CPU 63) for acquiring special information based on the game ball entering the ball entry means;
An assignment determination means (a function for executing the processes of steps S503 and S504 in the main CPU 63) for determining whether the special information corresponds to the assignment information;
A bonus awarding means (a function for executing the processes of steps S409 to S412 in the master CPU 63) for awarding a bonus (opening/closing execution mode) to a player based on the result of the bonus correspondence that the special information corresponds to the bonus information in the bonus determination,
A gaming machine described in any one of features D1 to D9, characterized in that the probability of the award corresponding result being obtained in the award judgment varies depending on the set value.

Feature D10 makes it possible to vary the probability of a corresponding result being awarded in a so-called pachinko machine according to a set value.

In addition, any one or more of the following configurations may be applied to the configurations of features D1 to D10: features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7. This allows for a synergistic effect to be achieved through the combined configuration.

<Features Group E>
Feature E1. A setting means (a function for executing a setting value update process in the master CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
a history storage execution means (a function of executing a history setting process in the management CPU 112) for storing history information of a game corresponding to a predetermined event that occurs as a result of the game being played in a history storage means (a history memory 117);
information derivation means for deriving aspect information corresponding to game results during a predetermined period of time using the history information stored in the history storage means, with at least one condition being that the setting value to be used has been set by the setting means (a function for executing the process of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the process of step S2107 in the management CPU 112 in the fifth embodiment);
A gaming machine comprising:

According to feature E1, the setting value to be used is set from among multiple setting values corresponding to the player's degree of advantage, so the player will expect that the more advantageous setting value will be the one to be used. Furthermore, when a specified event occurs, corresponding history information is stored in the history storage means. This makes it possible for the gaming machine to store and hold information for managing the number of times or frequency of occurrence of a specified event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a specified event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information.

In this case, when a new setting value to be used is set, the history information stored in the history storage means is used to derive behavior information corresponding to the game results during a specified period. This makes it possible to grasp the results of game history management, such as the frequency of occurrence of a specified event in the situation before the setting value was changed.

Feature E2. The gaming machine described in Feature E1, characterized in that it is equipped with a behavior information storage means (separate storage memory 171) that stores the behavior information derived by the information derivation means.

According to feature E2, when a new setting of the setting value to be used is made and the history information stored in the history storage means is used to derive behavior information corresponding to the game results during a specified period, the behavior information is stored in the behavior information storage means. As a result, even if the setting value is changed, it is possible to grasp the management results of the game history in the situation before the setting value was changed at any time thereafter.

Feature E3. The gaming machine described in Feature E2, wherein the mode information storage means is capable of storing a plurality of pieces of mode information.

According to feature E3, since it is possible to store multiple pieces of behavior information in the behavior information storage means, it is possible to grasp the results of managing the game history over multiple periods based on the timing when the setting value was newly set. Furthermore, even if new setting of the setting value is repeated under circumstances in which no game is being played, it is possible to increase the likelihood that behavior information derived using history information of a situation in which game play is actually being played will remain in the behavior information storage means.

Feature E4: The aspect information storage means is capable of storing a predetermined number of pieces of aspect information;
This gaming machine is a gaming machine described in feature E2 or E3, characterized in that it is equipped with a means for executing special processing when the setting of the setting value to be used by the setting means occurs more than the specified number of times under specified conditions (in the third embodiment, a function for executing monitoring processing of repeated changes in the management CPU 112, and in the fourth embodiment, a function for executing monitoring processing of repeated changes in the main CPU 63).

According to feature E4, when new setting values are repeatedly set in a situation where no game is being played, special processing is executed in order to prevent the behavior information derived using the history information of the situation where the game is actually being played from remaining in the behavior information storage means. This makes it possible to deal with such behavior.

Feature E5. The gaming machine according to any one of Features E1 to E4, wherein the information derivation means derives the behavior information when a predetermined amount or more of the history information is stored in the history storage means.

According to feature E5, since behavior information is derived when a predetermined amount or more of predetermined history information is stored in the history storage means, it is possible to prevent behavior information from being derived unnecessarily.

Feature E6. A ball entry means (first actuation port 33, second actuation port 34) through which a game ball flowing down the game area can enter;
An information acquisition means (a function for executing the process of step S401 in the main CPU 63) for acquiring special information based on the game ball entering the ball entry means;
An assignment determination means (a function for executing the processes of steps S503 and S504 in the main CPU 63) for determining whether the special information corresponds to the assignment information;
A bonus awarding means (a function for executing the processes of steps S409 to S412 in the master CPU 63) for awarding a bonus (opening/closing execution mode) to a player based on the result of the bonus correspondence that the special information corresponds to the bonus information in the bonus determination,
A gaming machine described in any one of features E1 to E5, characterized in that the probability of the award corresponding result being obtained in the award judgment varies depending on the set value.

Feature E6 makes it possible to vary the probability of a corresponding result being awarded in a so-called pachinko machine according to a set value.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features E1 to E6. This allows for a synergistic effect to be achieved through the combined configuration.

The invention relating to the above-mentioned feature group A, feature group B, feature group C, feature group D, and feature group E can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine that stores gaming balls given to a player, and the gaming balls stored in the tray storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out from, for example, a payout device to the tray storage section. In addition, a configuration in which an upper tray storage section and a lower tray storage section are provided as the tray storage section is also known for a pachinko machine, and in this case, the gaming balls stored in the upper tray storage section are guided to the gaming ball launching device, and the gaming balls that are surplus in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the reels have stopped rotating corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, gaming machines such as those exemplified above need to be properly managed, and there is still room for improvement in this regard.

<Feature Group F>
Feature F1. A ball entry means (first actuation port 33, second actuation port 34) through which a game ball flowing down the game area can enter;
An information acquisition means (a function for executing the process of step S401 in the main CPU 63) for acquiring special information based on the game ball entering the ball entry means;
An assignment determination means (a function for executing the processes of steps S503 and S504 in the main CPU 63) for determining whether the special information corresponds to the assignment information;
A bonus granting means (a function for executing the processes of steps S409 to S412 in the master CPU 63) that grants a bonus (opening/closing execution mode) to a player based on the result of the bonus correspondence that the special information corresponds to the bonus information in the bonus determination;
A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the advantage degree of the player;
Equipped with
The award determination means has a high probability mode and a low probability mode as a mode of the award determination such that the probability of the award corresponding result being obtained is relatively high and low,
A gaming machine characterized in that the probability of achieving the award corresponding result at least in the low probability mode varies according to the set value.

Feature F1 makes it possible to vary the probability of a bonus corresponding result in at least the low probability mode in a so-called pachinko machine according to a set value. This makes it possible to create a situation in which the probability of a bonus corresponding result in the low probability mode is favorable or unfavorable even in a single gaming machine. This makes it possible to increase the interest of the game.

Feature F2. The gaming machine described in Feature F1, characterized in that the probability of the corresponding result being awarded in the high probability mode does not vary according to the set value.

According to feature F2, the probability of an award corresponding result in low probability mode is changed according to the set value, while the probability of an award corresponding result in high probability mode is not changed according to the set value, thereby making it possible to limit the influence of the set value to the situation in low probability mode.

Feature F3. There are multiple types of the above benefits,
A gaming machine according to feature F1 or F2, characterized in that the selection mode of the benefit does not change according to the set value.

According to feature F3, the probability of a corresponding award result in low probability mode is changed according to a set value, while the manner in which the bonus is selected is not changed according to the set value, thereby making it possible to limit the influence of the set value to the situation in low probability mode.

In addition, any one or more of the following configurations may be applied to the configurations of features F1 to F3: features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7. This allows for a synergistic effect to be achieved through the combined configuration.

The invention relating to the above feature group F can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine that stores gaming balls given to a player, and the gaming balls stored in the tray storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out from, for example, a payout device to the tray storage section. In addition, a configuration in which an upper tray storage section and a lower tray storage section are provided as the tray storage section is also known for a pachinko machine, and in this case, the gaming balls stored in the upper tray storage section are guided to the gaming ball launching device, and the gaming balls that are surplus in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the reels have stopped rotating corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary to improve the entertainment value of the game, and there is still room for improvement in this regard.

<Feature Group G>
Feature G1. A history storage execution means (a function for executing a history setting process in the management CPU 112) for storing history information of a game corresponding to a predetermined event that occurs when the game is executed in the history storage means (history memory 117);
information derivation means for deriving aspect information corresponding to game results during a predetermined period of time using the history information stored in the history storage means (a function for executing the processes of steps S1402 to S1412 in the management CPU 112 in the first embodiment, a function for executing the process of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the process of step S2107 in the management CPU 112 in the fifth embodiment);
a first information display control means (a function of executing a display process in the management CPU 112) for controlling the display of an information display means (the first to third notification display devices 69a to 69c in the first to tenth embodiments, and the first to fourth notification display devices 201 to 204 in the eleventh to fourteenth embodiments) so that a display corresponding to the aspect information derived by the information derivation means is performed;
A second information display control means for controlling the display of the information display means so that a display corresponding to another information different from the aspect information is performed (in the first to tenth embodiments, a function for executing the processing of steps S202 and S208 in the main CPU 63; in the eleventh embodiment, a function for executing the processing of steps S3101, S3103, and S3109 in the main CPU 63; in the twelfth embodiment, a function for executing the processing of steps S3201, S3202, S3204, and S3210 in the main CPU 63; in the thirteenth embodiment, a function for executing the processing for abnormality display in the main CPU 63);
A gaming machine comprising:

According to feature G1, when a predetermined event occurs, history information corresponding to the event is stored in the history storage means. This allows the gaming machine to store and hold information for managing the number of occurrences or frequency of occurrence of the predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of the predetermined event. Furthermore, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by using the history information stored in the history storage means, behavior information corresponding to the results of play during a predetermined period is derived. Then, a display corresponding to the behavior information is performed by the information display means. This makes it possible to grasp the results of management of the game history, such as the frequency of occurrence of the predetermined event. Furthermore, the information display means not only displays corresponding to the behavior information but also displays corresponding to other information. This makes it possible to effectively use the information display means.

Feature G2. The gaming machine described in Feature G1, characterized in that the period during which the information display means displays the mode information is distinguished from the period during which the information display means displays the other information.

According to feature G2, by grasping the state in which the display is being performed on the information display means, it is possible to identify whether the display is being performed on the information display means, which of the display corresponding to the mode information and the display corresponding to the different information, is being performed.

Feature G3. The gaming machine described in Feature G1 or G2, characterized in that the second information display control means controls the display of the information display means so that a display mode different from the display mode when a display corresponding to the mode information is made is made, thereby making a display corresponding to the different information.

According to feature G3, by grasping the display mode of the information display means, it is possible to identify whether the display corresponding to the mode information or the display corresponding to the different information is being performed on the information display means.

Feature G4. The gaming machine according to any one of Features G1 to G3, characterized in that the information display means includes a plurality of individual information display means (first to third notification display devices 69a to 69c in the first to tenth embodiments, and first to fourth notification display devices 201 to 204 in the eleventh to fourteenth embodiments) each capable of performing a plurality of types of display.

According to feature G4, a wide variety of behavioral information can be displayed by using multiple individual information display means to display information corresponding to behavioral information. In addition, the existence of multiple individual information display means makes it possible to greatly differ the display mode between a case where a display corresponding to behavioral information is performed and a case where a display corresponding to other information is performed.

Feature G5. The gaming machine described in Feature G4, characterized in that when the second information display control means causes a display corresponding to the different information to be performed, a predetermined individual information display means (the first alert display device 69a and the second alert display device 69b in the first to tenth embodiments, the first alert display device 201, the second alert display device 202, and the third alert display device 203 in the eleventh and twelfth embodiments, and the first alert display device 201 and the second alert display device 202 in the thirteenth embodiment) among the plurality of individual information display means that is not in a non-display state when a display corresponding to the aspect information is performed is in a non-display state.

According to feature G5, a specific individual information display means that is not in a hidden state when a display corresponding to mode information is made is in a hidden state when a display corresponding to other information is made. This makes it possible to clearly identify whether a display corresponding to mode information or a display corresponding to other information is being made, simply by grasping the type of individual information display means that is in a hidden state.

Feature G6. When the second information display control means causes a display corresponding to the different information to be performed, a specific individual information display means (the third alert display device 69c in the first to tenth embodiments, the fourth alert display device 204 in the eleventh and twelfth embodiments, and the third alert display device 203 and the fourth alert display device 204 in the thirteenth embodiment) that is in a display state when the aspect information is displayed among the plurality of individual information display means is in a display state;
A gaming machine as described in feature G5, characterized in that the display content of the specific individual information display means when a display corresponding to the other information is made can be displayed on the specific individual information display means when a display corresponding to the status information is made.

According to feature G6, the display content that can be displayed when a display corresponding to mode information is made on a specific individual information display means can also be displayed when a display corresponding to other information is made, making it possible to avoid restricting the display content when a display corresponding to mode information is made. Also, even if a specific individual information display means is configured to be able to display the same content, a specific individual information display means that has the configuration of feature G5 above and is not in a hidden state when a display corresponding to mode information is made will be in a hidden state when a display corresponding to other information is made, making it possible to identify which display is being made on multiple individual information display means.

Feature G7. The gaming machine described in Feature G5 or G6, wherein the first information display control means sets each of the plurality of individual information display means to a display state when performing a display corresponding to the mode information.

According to feature G7, when a display corresponding to mode information is made, each of the multiple individual information display means is in a display state, making it possible to clearly distinguish this from a case where a display corresponding to other information is made in which a specific individual information display means is in a non-display state.

Feature G8. The gaming machine described in any one of Features G5 to G7, wherein the first information display control means sequentially changes the display of the status information on the information display means, and even when the display of the status information is changed, the predetermined individual information display means is not maintained in a non-display state.

According to feature G8, when a display corresponding to the mode information is being displayed, the specified individual information display means is not maintained in a non-display state. This makes it possible to identify whether a display corresponding to the mode information or a display corresponding to the different information is being displayed on the multiple individual information display means, regardless of the timing at which the multiple individual information display means are checked.

Feature G9. The gaming machine described in any one of Features G5 to G8, characterized in that the second information display control means causes one specific individual information display means (the third notification display device 69c in the first to tenth embodiments, and the fourth notification display device 204 in the eleventh and twelfth embodiments) among the plurality of individual information display means to display the different information, and causes the remaining individual information display means to be in a non-display state.

According to feature G9, when a display corresponding to different information is made, only one individual information display means is in a display state, making it easier to know whether a display corresponding to different information is made or not.

Feature G10. The individual information display means are arranged in a predetermined direction;
A gaming machine described in feature G9, characterized in that the specific individual information display means is located at the end of the multiple individual information display means arranged in the specified direction in the specified direction.

According to feature G10, one individual information display means on which a display corresponding to different information is performed is located at the end in a specified direction, making it easier to grasp whether a display corresponding to different information is being performed.

Feature G11. The first information display control means performs display corresponding to the type of the aspect information to be displayed on the individual information display means of the type display object that is a part of the plurality of individual information display means (the first notification display device 69a in the first to tenth embodiments, the first notification display device 201 and the second notification display device 202 in the eleventh to fourteenth embodiments), and performs display corresponding to the content of the aspect information to be displayed on the individual information display means of the result display object that is a part of the plurality of individual information display means (the second notification display device 69b and the third notification display device 69c in the first to tenth embodiments, the third notification display device 203 and the fourth notification display device 204 in the eleventh to fourteenth embodiments);
A gaming machine described in any one of features G5 to G10, wherein the specified individual information display means corresponds to the individual information display means of the type display target.

According to feature G11, when a display corresponding to mode information is made, a display corresponding to the type of mode information to be displayed is made in the individual information display means of the type display target, and a display corresponding to the content of the mode information to be displayed is made in the individual information display means of the result display target. This makes it easier to grasp the mode information to be displayed. In this case, when a display corresponding to other information is made, the individual information display means of the type display target is in a hidden state, so the hidden state of type display corresponds to other information, making it easier to grasp that other information is being displayed.

Feature G12: The information display means has a plurality of unit light-emitting elements (display segments 201a to 201g, 202a to 202g), and is configured to be able to perform a predetermined display by a combination of unit light-emitting elements that are in a light-emitting state among the plurality of unit light-emitting elements;
The second information display control means causes a display corresponding to the other information to be made by turning on a unit light-emitting unit among the plurality of unit light-emitting units that can be turned on when a display corresponding to the status information is made, and causes a combination of the unit light-emitting units that are turned on when a display corresponding to the other information is made to be a combination that does not exist when a display corresponding to the status information is made.

According to feature G12, by making the unit light-emitting units that can be made to emit light when a display corresponding to the mode information is made emit light, a display corresponding to the other information is made, which makes it possible to diversify the display corresponding to the mode information without placing restrictions on the content of the display corresponding to the mode information as much as possible. On the other hand, the combination of unit light-emitting units that emit light when a display corresponding to the other information is made is a combination that does not exist when a display corresponding to the mode information is made. As a result, by grasping the combination of unit light-emitting units that emit light, it becomes possible to grasp whether a display corresponding to the mode information or a display corresponding to the other information is being made.

Feature G13: The display mode of the display corresponding to the mode information in the information display means is in a plurality of modes;
A gaming machine as described in feature G12, characterized in that among the plurality of unit light-emitting units, there are no unit light-emitting units that do not emit light even when all of the displays corresponding to the mode information of the plurality of modes are performed.

According to feature G13, when a display corresponding to the aspect information is made, any combination of unit light-emitting elements is made to emit light, so that it is possible to diversify the display corresponding to the aspect information without restricting the content of the display corresponding to the aspect information as much as possible.

Feature G14: The information display means includes a plurality of individual information display means including a specific individual information display means (the third notification display device 69c in the first to tenth embodiments, the fourth notification display device 204 in the eleventh and twelfth embodiments, and the third notification display device 203 and the fourth notification display device 204 in the thirteenth embodiment),
The gaming machine described in feature G12 or G13, wherein the second information display control means, when causing a display corresponding to the different information to be performed, causes a predetermined individual information display means (the first alert display device 69a and the second alert display device 69b in the first to tenth embodiments, the first alert display device 201, the second alert display device 202, and the third alert display device 203 in the 11th and 12th embodiments, and the first alert display device 201 and the second alert display device 202 in the 13th embodiment) among the plurality of individual information display means to be in a non-display state when a display corresponding to the aspect information is performed.

According to feature G14, a specific individual information display means that is not in a hidden state when a display corresponding to mode information is made is in a hidden state when a display corresponding to other information is made. This makes it possible to clearly identify whether a display corresponding to mode information or a display corresponding to other information is being made, simply by grasping the type of individual information display means that is in a hidden state.

Feature G15: Equipped with a setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
A gaming machine described in any one of features G1 to G14, characterized in that the second information display control means causes a display corresponding to the other information to be performed in a situation where the setting value can be changed.

According to feature G15, the information display means that displays information corresponding to the mode information can also be used as a display means for notifying the user that the setting value can be changed.

Feature G16. The gaming machine described in Feature G15, wherein the second information display control means displays information corresponding to a currently selected setting value as the display corresponding to the different information.

According to feature G16, the information display means that displays the mode information can also be used as a display means for displaying the setting value that is being changed.

Feature G17. The gaming machine described in any one of Features G1 to G16, characterized in that the second information display control means causes a display corresponding to an abnormal state of the gaming machine to be displayed as a display corresponding to the other information.

According to feature G17, the information display means for displaying information corresponding to the status information can also be used as a display means for displaying information corresponding to an abnormal state of the gaming machine.

Feature G18. The gaming machine described in Feature G17, wherein the second information display control means, when causing a display corresponding to the abnormal condition to be displayed in a situation in which the abnormal condition is not occurring, causes a display corresponding to the absence of the abnormal condition to be displayed.

Feature G18 makes it possible to clearly identify whether an abnormal condition has occurred by checking the information display means.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features G1 to G18. This allows for a synergistic effect to be achieved through the combined configuration.

<Feature H Group>
Feature H1. A history storage execution means (a function for executing a history setting process in the management CPU 112) for storing history information of a game corresponding to a predetermined event that occurs when the game is executed in the history storage means (history memory 117);
information derivation means for deriving aspect information corresponding to game results during a predetermined period of time using the history information stored in the history storage means (a function for executing the processes of steps S1402 to S1412 in the management CPU 112 in the first embodiment, a function for executing the process of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the process of step S2107 in the management CPU 112 in the fifth embodiment);
a first information display control means (a function of executing a display process in the management CPU 112) for controlling the display of an information display means (the first to third notification display devices 69a to 69c in the first to tenth embodiments, and the first to fourth notification display devices 201 to 204 in the eleventh to fourteenth embodiments) so that a display corresponding to the aspect information derived by the information derivation means is performed;
A second information display control means for controlling the display of the information display means so that a display corresponding to another information different from the aspect information is performed (in the first to tenth embodiments, a function for executing the processing of steps S202 and S208 in the main CPU 63; in the eleventh embodiment, a function for executing the processing of steps S3101, S3103, and S3109 in the main CPU 63; in the twelfth embodiment, a function for executing the processing of steps S3201, S3202, S3204, and S3210 in the main CPU 63; in the thirteenth embodiment, a function for executing the processing for abnormality display in the main CPU 63);
Equipped with
the information display means has a plurality of unit light-emitting elements (display segments 201 a to 201 g, 202 a to 202 g) and is configured to be able to perform a predetermined display by a combination of unit light-emitting elements that are in a light-emitting state among the plurality of unit light-emitting elements;
The second information display control means causes a display corresponding to the other information to be displayed by causing unit light-emitting units among the plurality of unit light-emitting units that can be made to emit light when a display corresponding to the status information is made to emit light, and is characterized in that the combination of unit light-emitting units that are made to emit light when a display corresponding to the other information is made is a combination that does not exist when a display corresponding to the status information is made.

According to feature H1, when a predetermined event occurs, history information corresponding to the event is stored in the history storage means. This allows the gaming machine to store and hold information for managing the number of occurrences or frequency of occurrence of the predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of the predetermined event. Furthermore, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by using the history information stored in the history storage means, behavior information corresponding to the results of play during a predetermined period is derived. Then, a display corresponding to the behavior information is performed by the information display means. This makes it possible to grasp the results of management of the game history, such as the frequency of occurrence of the predetermined event. Furthermore, the information display means not only displays corresponding to the behavior information but also displays corresponding to other information. This makes it possible to effectively use the information display means.

In addition, by making the unit light-emitting units that can be made to emit light when a display corresponding to the mode information is made emit light, a display corresponding to the other information is made, which makes it possible to diversify the display corresponding to the mode information without placing restrictions on the content of the display corresponding to the mode information as much as possible. On the other hand, the combination of unit light-emitting units that emit light when a display corresponding to the other information is made is a combination that does not exist when a display corresponding to the mode information is made. In this way, by knowing the combination of unit light-emitting units that emit light, it becomes possible to know whether a display corresponding to the mode information or a display corresponding to the other information is being made.

Feature H2. The display mode of the display corresponding to the mode information in the information display means is in a plurality of modes,
A gaming machine as described in feature H1, characterized in that among the plurality of unit light-emitting units, there are no unit light-emitting units that do not emit light even when all of the displays corresponding to the state information of the plurality of states are performed.

According to feature H2, when a display corresponding to the aspect information is made, any combination of unit light-emitting elements is made to emit light, so that it is possible to diversify the display corresponding to the aspect information without restricting the content of the display corresponding to the aspect information as much as possible.

Feature H3. The information display means includes a plurality of individual information display means including a specific individual information display means (the third notification display device 69c in the first to tenth embodiments, the fourth notification display device 204 in the eleventh and twelfth embodiments, and the third notification display device 203 and the fourth notification display device 204 in the thirteenth embodiment),
The gaming machine described in feature H1 or H2, characterized in that when the second information display control means causes a display corresponding to the different information to be performed, a predetermined individual information display means (the first alert display device 69a and the second alert display device 69b in the first to tenth embodiments, the first alert display device 201, the second alert display device 202, and the third alert display device 203 in the 11th and 12th embodiments, and the first alert display device 201 and the second alert display device 202 in the 13th embodiment) among the plurality of individual information display means that is not in a hidden state when a display corresponding to the aspect information is performed is in a hidden state.

According to feature H3, a specific individual information display means that is not in a hidden state when a display corresponding to the mode information is made is in a hidden state when a display corresponding to the other information is made. This makes it possible to clearly identify whether a display corresponding to the mode information or a display corresponding to the other information is being made, simply by grasping the type of individual information display means that is in a hidden state.

Feature H4. The gaming machine described in Feature H3, wherein the first information display control means sets each of the multiple individual information display means to a display state when performing a display corresponding to the mode information.

According to feature H4, when a display corresponding to mode information is made, each of the multiple individual information display means is in a display state, making it possible to clearly distinguish this from a case where a display corresponding to other information is made in which a specific individual information display means is in a non-display state.

Feature H5. The gaming machine described in Feature H3 or H4, wherein the first information display control means sequentially changes the display of the status information on the information display means, and even when the display of the status information is changed, the predetermined individual information display means is not maintained in a non-display state.

According to feature H5, when a display corresponding to the aspect information is being made, the specific individual information display means is not maintained in a non-display state. This makes it possible to identify whether a display corresponding to the aspect information or a display corresponding to the different information is being made on the multiple individual information display means, regardless of the timing at which the multiple individual information display means are checked.

Feature H6. Equipped with a setting means (a function for executing a setting value update process in the master CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
A gaming machine described in any one of features H1 to H5, characterized in that the second information display control means causes a display corresponding to the other information to be performed in a situation in which the setting value can be changed.

According to feature H6, the information display means that displays the status information can also be used as a display means for notifying the user that the setting value can be changed.

Feature H7. The gaming machine described in Feature H6, wherein the second information display control means displays information corresponding to a currently selected setting value as the display corresponding to the different information.

According to feature H7, the information display means that displays the mode information can also be used as a display means for displaying the setting value that is being changed.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features H1 to H7. This allows for a synergistic effect to be achieved through the combined configuration.

<Characteristics Group I>
Feature I1. A history storage execution means (a function for executing a history setting process in the management CPU 112) for storing history information of a game corresponding to a predetermined event that occurs when the game is executed in the history storage means (history memory 117);
information derivation means for deriving aspect information corresponding to game results during a predetermined period of time using the history information stored in the history storage means (a function for executing the processes of steps S1402 to S1412 in the management CPU 112 in the first embodiment, a function for executing the process of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the process of step S2107 in the management CPU 112 in the fifth embodiment);
a first information display control means (a function of executing a display process in the management CPU 112) for controlling the display of an information display means (the first to fourth notification display devices 201 to 204) so that a display corresponding to the aspect information derived by the information derivation means is performed;
A second information display control means (a function of executing an abnormality display process in the main CPU 63) for controlling the display of the information display means so that a display corresponding to an abnormal state of the gaming machine is performed;
A gaming machine comprising:

According to feature I1, when a predetermined event occurs, history information corresponding to the event is stored in the history storage means. This allows the gaming machine to store and hold information for managing the number of occurrences or frequency of occurrence of the predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of the predetermined event. Furthermore, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by using the history information stored in the history storage means, behavior information corresponding to the results of play during a predetermined period is derived. Then, a display corresponding to the behavior information is performed by the information display means. This makes it possible to grasp the results of management of the game history, such as the frequency of occurrence of the predetermined event. Furthermore, the information display means not only displays corresponding to the behavior information, but also displays corresponding to abnormal states of the gaming machine. This makes it possible to effectively use the information display means.

Feature I2. The gaming machine described in Feature I1, wherein the second information display control means, when causing a display corresponding to the abnormal condition to be displayed in a situation in which the abnormal condition is not occurring, causes a display corresponding to the absence of the abnormal condition to be displayed.

According to feature I2, it is possible to clearly identify whether or not an abnormal condition has occurred by checking the information display means.

Feature I3. A gaming machine according to feature I1 or I2, characterized in that the period during which the information display means displays the status information is distinguished from the period during which the information display means displays the abnormal state.

According to feature I3, by grasping the state in which the display is being performed on the information display means, it is possible to identify whether the display corresponding to the status information or the display corresponding to the abnormal state is being performed on the information display means.

Feature I4. The gaming machine described in Feature G1 or G2, characterized in that the second information display control means controls the display of the information display means so that a display mode different from the display mode when a display corresponding to the status information is made is made, thereby making a display corresponding to the abnormal state.

According to feature I4, by grasping the display mode of the information display means, it is possible to identify whether the display corresponding to the mode information or the display corresponding to the abnormal state is being displayed on the information display means.

Feature I5. A gaming machine according to any one of Features I1 to I4, characterized in that the information display means includes a plurality of individual information display means (first to fourth notification display devices 201 to 204), each capable of displaying a plurality of types of information.

According to feature I5, a wide variety of status information can be displayed by using multiple individual information display means to display information corresponding to the status information. In addition, the existence of multiple individual information display means makes it possible to greatly differ the display mode between when a display corresponding to status information is displayed and when a display corresponding to an abnormal state is displayed.

Feature I6. The gaming machine described in Feature I5, characterized in that when the second information display control means causes a display corresponding to the abnormal state to be displayed, a predetermined individual information display means (the first alert display device 201 and the second alert display device 202) among the plurality of individual information display means that is not in a hidden state when a display corresponding to the mode information is performed is in a hidden state.

According to feature I6, a specific individual information display means that is not in a hidden state when a display corresponding to the mode information is made is in a hidden state when a display corresponding to an abnormal state is made. This makes it possible to clearly identify whether a display corresponding to the mode information or a display corresponding to an abnormal state is being made, simply by grasping the type of individual information display means that is in a hidden state.

Feature I7. When the second information display control means causes a display corresponding to the abnormal state to be performed, a specific individual information display means (the third notification display device 203 and the fourth notification display device 204) that is in a display state when the aspect information is displayed among the plurality of individual information display means is in a display state;
A gaming machine as described in feature I6, characterized in that the display content of the specific individual information display means when a display corresponding to the abnormal state is made can be displayed on the specific individual information display means when a display corresponding to the status information is made.

According to feature I7, the display content that can be displayed when a display corresponding to mode information is made on a specific individual information display means can also be displayed when a display corresponding to an abnormal state is made, making it possible to avoid restricting the display content when a display corresponding to mode information is made. Furthermore, even if a specific individual information display means is configured to be able to display the same content, a specific individual information display means that has the configuration of feature I7 and is not in a hidden state when a display corresponding to mode information is made becomes in a hidden state when a display corresponding to an abnormal state is made, making it possible to identify which display is being made on multiple individual information display means.

Feature I8. The gaming machine described in Feature I6 or I7, wherein the first information display control means sets each of the multiple individual information display means to a display state when performing a display corresponding to the mode information.

According to feature I8, when a display corresponding to status information is made, each of the multiple individual information display means is in a display state, making it possible to clearly distinguish this from a display corresponding to an abnormal state in which a specific individual information display means is in a non-display state.

Feature I9. The gaming machine described in any one of Features I6 to I8, wherein the first information display control means sequentially changes the display of the status information on the information display means, and even when the display of the status information is changed, the predetermined individual information display means is not maintained in a non-display state.

According to feature I9, when a display corresponding to the status information is being displayed, the specified individual information display means is not maintained in a non-display state. This makes it possible to identify whether a display corresponding to the status information or a display corresponding to an abnormal state is being displayed on the multiple individual information display means, regardless of the timing at which the multiple individual information display means are checked.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features I1 to I9. This allows for a synergistic effect to be achieved through the combined configuration.

<Characteristics Group J>
Feature J1. A history storage execution means (a function for executing a history setting process in the management CPU 112) for storing history information of a game corresponding to a predetermined event that occurs as a result of the game being played in the history storage means (history memory 117);
information derivation means for deriving aspect information corresponding to game results during a predetermined period of time using the history information stored in the history storage means (a function for executing the processes of steps S1402 to S1412 in the management CPU 112 in the first embodiment, a function for executing the process of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the process of step S2107 in the management CPU 112 in the fifth embodiment);
a first information display control means (a function of executing a display process in the management CPU 112) for controlling the display of an information display means (the first to third notification display devices 69a to 69c in the first to tenth embodiments, and the first to fourth notification display devices 201 to 204 in the eleventh to fourteenth embodiments) so that a display corresponding to the aspect information derived by the information derivation means is performed;
Equipped with
The first information display control means sequentially changes the display corresponding to the status information on the information display means, and is characterized in that the information display means is not maintained in a non-display state even when the display corresponding to the status information is changed.

According to feature J1, when a predetermined event occurs, history information corresponding to the event is stored in the history storage means. This allows the gaming machine to store and hold information for managing the number of occurrences or frequency of occurrence of the predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of the predetermined event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by using the history information stored in the history storage means, behavior information corresponding to the results of play during a predetermined period is derived. Then, a display corresponding to the behavior information is performed by the information display means. This makes it possible to grasp the results of management of the game history, such as the frequency of occurrence of the predetermined event. Furthermore, when a display corresponding to the behavior information is performed, the information display means is not maintained in a non-display state. This makes it possible to identify a display corresponding to the behavior information regardless of the timing at which the information display means is checked.

Feature J2. The gaming machine described in Feature J1 is characterized in that the information display means includes a plurality of individual information display means (first to third notification display devices 69a to 69c in the first to tenth embodiments, and first to fourth notification display devices 201 to 204 in the eleventh to fourteenth embodiments) each capable of performing a plurality of types of display.

According to feature J2, by using multiple individual information display means to display information corresponding to the behavior information, it is possible to display a wide variety of behavior information.

Feature J3. The gaming machine described in Feature J2, wherein the first information display control means sets each of the multiple individual information display means to a display state when performing a display corresponding to the mode information.

According to feature J3, when a display corresponding to the aspect information is made, each of the multiple individual information display means is in a display state, and is maintained in a display state even when the display corresponding to the aspect information is changed. This makes it easier to grasp the aspect information.

Feature J4. The gaming machine described in Feature J2 or J3, characterized in that the first information display control means causes a display corresponding to the type of the aspect information to be displayed on an individual information display means to be a type display target that is a part of the plurality of individual information display means (the first notification display device 69a in the first to tenth embodiments, and the first notification display device 201 and the second notification display device 202 in the eleventh to fourteenth embodiments), and causes a display corresponding to the content of the aspect information to be displayed on an individual information display means to be a result display target that is a part of the plurality of individual information display means (the second notification display device 69b and the third notification display device 69c in the first to tenth embodiments, and the third notification display device 203 and the fourth notification display device 204 in the eleventh to fourteenth embodiments).

According to feature J4, when a display corresponding to the aspect information is made, a display corresponding to the type of aspect information to be displayed is made in the individual information display means of the type display target, and a display corresponding to the content of the aspect information to be displayed is made in the individual information display means of the result display target. This makes it easier to grasp the aspect information to be displayed.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features J1 to J4. This allows for a synergistic effect to be achieved through the combined configuration.

<Feature K group>
Feature K1. The device is provided with a history storage execution means (a function for executing a history setting process in the management CPU 112) for storing history information of a game corresponding to a predetermined event that occurs when the game is executed, in the history storage means (the history memory 117);
The gaming machine is characterized in that the history storage execution means is equipped with a means (a function of making a negative judgment in step S3501 in the main CPU 63) that prevents the history information from being stored in the history storage means even if the specified event occurs when a restricted situation is present.

According to feature K1, when a specified event occurs, the corresponding history information is stored in the history storage means. This makes it possible for the gaming machine to store and hold information for managing the number of times or frequency of occurrence of a specified event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a specified event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, since the history information is not stored in a restricted situation even if a specified event occurs, it is possible to prevent the history information from being stored in a situation in which it is not desirable to store the history information.

Feature K2. The gaming machine described in Feature K1, characterized in that the restricted state can occur from when the supply of operating power to the history storage execution means starts until a restriction release event occurs.

Feature K2 makes it possible to prevent the occurrence of a specified event due to an operation check immediately after the start of the supply of operating power from being stored as history information.

Feature K3: A means for setting the limiting state when the supply of operating power to the history storage execution means is started and the limiting condition is satisfied (a function for executing the process of step S3610 in the main CPU 63);
A means for not setting the limiting state when the supply of operating power to the history storage execution means is started and the limiting condition is not satisfied (a function for executing the process of step S3621 in the main CPU 63);
The gaming machine described in feature K2 is characterized by being equipped with:

According to feature K3, the restricted situation may or may not be set depending on whether the restrictive condition is met. This makes it possible to avoid setting the restricted situation as necessary.

Feature K4. A gaming machine according to any one of Features K1 to K3, characterized in that the restricted state can occur from when the supply of operating power to the history storage execution means starts until the number of game balls discharged from the game area reaches or exceeds a predetermined reference number.

Feature K4 makes it possible to prevent history information from being stored until the number of game balls discharged from the game area reaches or exceeds a predetermined reference number after the supply of operating power begins.

Feature K5. A history storage execution means (a function for executing a normal ball entry management process in the main CPU 63, a ball entry management process during the opening and closing execution mode, and a ball entry management process during the high frequency support mode) for storing corresponding game history information in a history storage means (a normal counter area 231, a counter area 232 for the opening and closing execution mode, and a ball entry management process during the high frequency support mode) when a predetermined event occurs due to the execution of a game;
An information deriving means (a function for executing the process of step S4208 in the master CPU 63) for deriving behavior information corresponding to a game result during a predetermined period by utilizing the history information stored in the history storage means;
Equipped with
The gaming machine is characterized in that the information deriving means does not derive the status information when a restricted situation occurs.

According to feature K5, when a predetermined event occurs, the corresponding history information is stored in the history storage means. This allows the gaming machine to store and hold information for managing the number of times or frequency of occurrence of the predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of the predetermined event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, the history information stored in the history storage means is used to derive behavior information corresponding to the results of play during a predetermined period. This makes it possible to grasp the results of management of the game history, such as the frequency of occurrence of the predetermined event. Furthermore, since behavior information is not derived in the case of a restricted situation even if a predetermined event occurs, it is possible to prevent behavior information from being derived in a situation in which it is not desirable to derive behavior information.

Feature K6. The gaming machine described in Feature K5, characterized in that the restricted state can occur from when the supply of operating power to the history storage execution means begins until a restriction release event occurs.

Feature K6 makes it possible to prevent the derivation of behavior information using history information based on the occurrence of a specified event during an operation check immediately after the supply of operating power begins.

Feature K7. A gaming machine according to Feature K5 or K6, characterized in that the restricted state can occur from when the supply of operating power to the history storage execution means starts until the number of game balls discharged from the game area reaches or exceeds a predetermined reference number.

Feature K7 makes it possible to prevent the state information from being derived from the time when the supply of operating power starts until the number of game balls discharged from the game area reaches or exceeds a predetermined reference number.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features K1 to K7. This allows for a synergistic effect to be achieved through the combined configuration.

The invention relating to the above-mentioned feature group G, feature group H, feature group I, feature group J, and feature group K makes it possible to solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine that stores gaming balls given to a player, and the gaming balls stored in the tray storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out from, for example, a payout device to the tray storage section. In addition, a configuration in which an upper tray storage section and a lower tray storage section are provided as the tray storage section is also known for a pachinko machine, and in this case, the gaming balls stored in the upper tray storage section are guided to the gaming ball launching device, and the gaming balls that are surplus in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the reels have stopped rotating corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, gaming machines such as those exemplified above need to be properly managed, and there is still room for improvement in this regard.

<Feature L group>
Feature L1. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes;
The control means includes:
A first predetermined processing execution means for executing a first predetermined processing among the various processing (a function for executing processing other than the management execution processing in the main CPU 63 in the fifteenth to twenty-first embodiments);
A second predetermined processing execution means (a function of executing a management execution process in the main CPU 63 in the fifteenth to twenty-first embodiments) that executes a second predetermined processing among the various processing;
When the situation changes from the situation where the first predetermined process is being executed to the situation where the second predetermined process is being executed or when the situation where the second predetermined process is being executed is reached, a save execution means saves predetermined information, which is at least a part of the information stored in the internal storage means, to a predetermined storage means (main RAM 65) (in the fifteenth embodiment, a function for executing the processing of steps S3802 and steps S3902 to S3907 in the main CPU 63; in the sixteenth embodiment, a function for executing the processing of step S4402 in the main CPU 63; in the seventeenth embodiment, a function for executing the processing of steps S4502 to S4507 in the main CPU 63; in the eighteenth embodiment, a function for executing the processing of step S4602 in the main CPU 63; and in the nineteenth embodiment, a function for executing the processing of steps S4701 and S4703 in the main CPU 63).
a return execution means for returning the specified information saved in the specified storage means to the internal storage means when or after the second specified process is completed (in the fifteenth embodiment, a function for executing the processes of steps S3804 and S3910 to S3915 in the main CPU 63; in the sixteenth embodiment, a function for executing the processes of step S4404 in the main CPU 63; in the seventeenth embodiment, a function for executing the processes of steps S4510 to S4515 in the main CPU 63; in the eighteenth embodiment, a function for executing the processes of step S4605 in the main CPU 63; and in the nineteenth embodiment, a function for executing the processes of steps S4705 and S4706 in the main CPU 63);
A gaming machine comprising:

According to feature L1, when the situation changes from the execution of the first predetermined process to the execution of the second predetermined process or when the situation changes to the execution of the second predetermined process, at least a part of the information stored in the internal storage means is saved to the predetermined storage means. This makes it possible to prevent the information stored in the internal storage means from being rewritten when the first predetermined process is executed when the second predetermined process is executed. Also, when or after the second predetermined process is terminated, the information saved in the predetermined storage means is restored to the internal storage means. This makes it possible to execute a process different from the second predetermined process from the state of the internal storage means before the execution of the second predetermined process when the second predetermined process is terminated. As a result, it becomes possible to perform various controls in an optimal manner.

Feature L2. The gaming machine described in Feature L1, characterized in that the predetermined information is a portion of the information stored in the internal storage means.

According to feature L2, only a portion of the information stored in the internal storage means is evacuated to the specified storage means, making it possible to reduce the storage capacity required to evacuate the information from the internal storage means in the specified storage means.

Feature L3. The internal storage means includes at least a first storage area (the WA register, the BC register, the DE register, the HL register, the IX register, and the IY register) and a second storage area (registers other than the WA register, the BC register, the DE register, the HL register, the IX register, and the IY register);
the second predetermined process execution means is configured to store information in the first storage area during the second predetermined process, but not to store information in the second storage area;
The gaming machine according to feature L2, wherein the save execution means saves information stored in the first memory area to the specified memory means.

According to feature L3, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, information in the first storage area that is to be stored in the second predetermined process in the internal storage means is saved to the predetermined storage means. This makes it possible to reduce the storage capacity required to save information from the internal storage means in the predetermined storage means, while making it possible to execute a process different from the second predetermined process from the state of the internal storage means before the execution of the second predetermined process when the second predetermined process is completed.

Feature L4. The predetermined storage means is
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
A second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
A gaming machine according to any one of features L1 to L3, wherein the save execution means saves the specified information in the second specified memory area.

According to feature L4, by providing the predetermined storage means with a first predetermined storage area and a second predetermined storage area, it is possible to clearly differentiate the storage destination of information in the predetermined storage means between the first predetermined process and the second predetermined process. This makes it possible to prevent information used in one of the first and second predetermined processes from being erased when the other process is executed. In this case, when the situation changes from the execution of the first predetermined process to the execution of the second predetermined process or when the situation changes to the execution of the second predetermined process, at least a portion of the information stored in the internal storage means is saved to the second predetermined storage area. This makes it possible to save the information in the internal storage means immediately before the start of the second predetermined process, and to save the information without using the first predetermined storage area.

Feature L5. The save execution means is
A means for saving first predetermined information, which is a part of information stored in the internal storage means, to the first predetermined storage area in the first predetermined processing when the situation changes from the situation where the first predetermined processing is being executed to the situation where the second predetermined processing is being executed (a function for executing the processing of step S3802 in the main CPU 63 in the fifteenth embodiment, and a function for executing the processing of step S4402 in the main CPU 63 in the sixteenth embodiment);
A means for saving second predetermined information, which is a part of information stored in the internal storage means, in the second predetermined storage area in the second predetermined processing when the situation changes from the situation where the first predetermined processing is being executed to the situation where the second predetermined processing is being executed (in the fifteenth embodiment, a function for executing the processing of steps S3902 to S3907 in the main CPU 63; in the seventeenth embodiment, a function for executing the processing of steps S4502 to S4507 in the main CPU 63; in the eighteenth embodiment, a function for executing the processing of step S4602 in the main CPU 63; and in the nineteenth embodiment, a function for executing the processing of steps S4702 and S4703 in the main CPU 63);
A gaming machine according to feature L4, characterized in that it is equipped with:

According to feature L5, the first predetermined information, which is a portion of the information stored in the internal storage means, is saved to a first predetermined storage area by a first predetermined process, and the second predetermined information, which is a portion of the information stored in the internal storage means, is saved to a second predetermined storage area by a second predetermined process. This makes it possible to save each piece of information stored in the internal storage means at a time that is favorable for the information, and also makes it possible to distribute the process for saving the information between the first predetermined process and the second predetermined process.

Feature L6. The gaming machine described in Feature L5, wherein the first predetermined information is information in a flag register provided in the internal storage means.

Feature L6 makes it possible to appropriately save the information in the flag register when the first specified process is being executed.

Feature L7. The second predetermined storage area is
a stack area (non-specific control stack area 224) into which information can be written by a push command and into which information can be read by a pop command;
A work area (non-specific control work area 223) in which information can be written and read by a load command;
Equipped with
A gaming machine described in any one of features L4 to L6, wherein the save execution means saves the specified information to one of the stack area and the work area.

According to feature L7, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, at least a portion of the information stored in the internal storage means is saved to one of the stack area and the work area in the second predetermined storage area. This makes it possible to consolidate the destinations for saving information, and to simplify the processing configuration for saving and the processing configuration for restoring.

Feature L8. The gaming machine described in Feature L7, wherein the save execution means saves the specified information to the work area.

According to feature L8, since the work area is used as the destination for saving at least a portion of the information stored in the internal storage means, it is possible to save the information without making cumulative changes to the stack pointer.

Feature L9: The first predetermined storage area is capable of storing information and reading information when the first predetermined process is executed, and is capable of reading information but is not capable of storing information when the second predetermined process is executed;
A gaming machine described in any one of features L4 to L8, characterized in that the second specified memory area is capable of storing information and reading information when the second specified process is executed, and is capable of reading information but not storing information when the first specified process is executed.

Feature L9 makes it possible to treat the first specified memory area as a memory area dedicated to the first specified process, and to treat the second specified memory area as a memory area dedicated to the second specified process.

Feature L10. The predetermined storage means is
a stack area (non-specific control stack area 224) into which information can be written by a push command and into which information can be read by a pop command;
A work area (non-specific control work area 223) in which information can be written and read by a load command;
Equipped with
A gaming machine described in any one of features L1 to L9, wherein the save execution means saves the specified information to one of the stack area and the work area.

Feature L10 makes it possible to consolidate destinations for saving specific information, and simplifies the processing configuration for saving specific information and the processing configuration for restoring specific information.

Feature L11. The gaming machine described in Feature L10, wherein the save execution means saves the specified information to the work area.

According to feature L11, the destination for saving specific information is the work area, making it possible to save the information without making cumulative changes to the stack pointer.

Feature L12: The predetermined information is a part of the information stored in the internal storage means,
The gaming machine described in feature L11 is characterized in that the save execution means is provided with a means (a function of executing the processing of step S3802 in the main CPU 63) for saving specific information, which is a part of the information stored in the internal storage means, to the stack area when the situation changes from one in which the first specified processing is being executed to one in which the second specified processing is being executed or when the situation changes to one in which the second specified processing is being executed.

According to feature L12, in a configuration in which predetermined information is saved to a work area, specific information is saved to a stack area. This makes it possible to distribute and save information stored in the internal storage means to the work area and stack area.

Feature L13. The gaming machine described in Feature L12, characterized in that the predetermined information has a larger amount of information than the specific information.

According to feature L13, by saving predetermined information, which has a larger amount of information than specific information, in the work area, it is possible to prevent a large amount of information from being cumulatively stored in the stack area when saving information stored in the internal storage means.

Feature L14: When the state of executing the first predetermined process changes to the state of executing the second predetermined process, or when the state of executing the second predetermined process changes, information of the stack pointer provided in the internal storage means becomes fixed information;
A gaming machine described in any one of features L1 to L13, characterized in that information of a stack pointer provided in the internal storage means is not subject to saving by the save execution means.

According to feature L14, since there is no need to reserve capacity in the specified storage means for saving stack pointer information, it is possible to reduce the capacity of the specified storage means. Even in such a configuration in which stack pointer information is not saved, when the situation changes from the situation in which the first specified process is being executed to the situation in which the second specified process is being executed, or when the situation changes to the situation in which the second specified process is being executed, the stack pointer information becomes fixed information, so it is possible to restore the stack pointer information to the information before the second specified process was started without saving the stack pointer information as described above.

Feature L15. A gaming machine according to feature L14, characterized in that it is provided with a means for setting the fixed information in the stack pointer when or after the second predetermined process is completed (a function for executing the process of step S3909 in the main CPU 63 in the 15th embodiment, a function for executing the process of step S4509 in the main CPU 63 in the 17th embodiment, and a function for executing the process of step S4604 in the main CPU 63 in the 18th embodiment).

According to feature L15, when or after the second specified process is terminated, it is possible to restore the stack pointer information to the state before the second specified process was started.

Feature L16. A gaming machine according to feature L14 or L15, characterized in that it is provided with a means for setting second response start information corresponding to the second predetermined processing in the stack pointer when the situation changes from the situation where the first predetermined processing is being executed to the situation where the second predetermined processing is being executed or when the situation where the second predetermined processing is being executed is reached (in the fifteenth embodiment, a function for executing the processing of step S3901 in the main CPU 63; in the seventeenth embodiment, a function for executing the processing of step S4501 in the main CPU 63; in the eighteenth embodiment, a function for executing the processing of step S4601 in the main CPU 63).

According to feature L16, when the second predetermined process is started, second corresponding start information corresponding to the second predetermined process is set in the stack pointer, making it possible to store information in the stack area at an appropriate address in the second predetermined process.

Feature L17: The first predetermined process includes a process for controlling the progress of a game;
A gaming machine described in any one of features L1 to L16, wherein the second predetermined process includes a process for managing a gaming history.

According to feature L17, a process for controlling the progress of a game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, so that it is possible to prevent information used in the process for managing the game history from being rewritten when the process for controlling the progress of a game is executed.

Feature L18: The predetermined storage means is
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
A second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
The gaming machine described in feature L17 is characterized in that the second specified memory area is equipped with a history memory area (normal counter area 231, counter area 232 for opening/closing execution mode, counter area 233 for high frequency support mode) in which corresponding game history information is stored when a specified event occurs as a result of the game being played.

According to feature L18, when a predetermined event occurs, the corresponding history information is stored in the history storage area. This allows the gaming machine to store and hold information for managing the number of times or frequency of occurrence of the predetermined event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of the predetermined event. Furthermore, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by executing a process for controlling the progress of the game as the first predetermined process, and executing a process for managing the game history as the second predetermined process, it becomes possible to prevent the information stored in the history storage area from being rewritten when the process for controlling the progress of the game is executed.

Feature L19. The gaming machine described in Feature L18, characterized in that the second predetermined process execution means includes information derivation means (a function for executing the process of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to the game results during a predetermined period.

According to feature L19, by deriving behavior information corresponding to the results of play during a specified period of time using the history information stored in the history storage area, it becomes possible to grasp the results of management of the play history, such as the frequency of occurrence of a specified event.

Feature L20. The gaming machine described in Feature L19, characterized in that the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature L20, when behavior information corresponding to the results of a game during a specified period is derived using history information, the behavior information is stored in a behavior information storage area. This makes it possible to grasp the results of managing the game history at any time. In addition, by executing a process for controlling the progress of a game as the first specified process and a process for managing the game history as the second specified process, it becomes possible to prevent the information stored in the behavior information storage area from being overwritten when the process for controlling the progress of a game is executed.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features L1 to L20. This allows for a synergistic effect to be achieved through the combined configuration.

<Feature M group>
Feature M1. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes;
The control means includes:
A first predetermined processing execution means for executing a first predetermined processing among the various processing (a function for executing processing other than the management execution processing in the main CPU 63 in the fifteenth to twenty-first embodiments);
A second predetermined processing execution means (a function of executing a management execution process in the main CPU 63 in the fifteenth to twenty-first embodiments) that executes a second predetermined processing among the various processing;
When the situation changes from the situation where the first predetermined processing is being executed to the situation where the second predetermined processing is being executed or when the situation where the second predetermined processing is being executed is reached, a save execution means saves predetermined information, which is at least a part of the information stored in the internal storage means, to a predetermined storage means (main RAM 65) (in the fifteenth embodiment, a function for executing the processing of steps S3902 to S3907 in the main CPU 63; in the seventeenth embodiment, a function for executing the processing of steps S4502 to S4507 in the main CPU 63; in the eighteenth embodiment, a function for executing the processing of step S4602 in the main CPU 63; and in the nineteenth embodiment, a function for executing the processing of steps S4701 and S4703 in the main CPU 63);
A restoration execution means for restoring the predetermined information saved in the predetermined storage means to the internal storage means when or after the second predetermined process is completed (a function for executing the processes of steps S3910 to S3915 in the main CPU 63 in the fifteenth embodiment, a function for executing the processes of steps S4510 to S4515 in the main CPU 63 in the seventeenth embodiment, a function for executing the processes of step S4605 in the main CPU 63 in the eighteenth embodiment, and a function for executing the processes of steps S4705 and S4706 in the main CPU 63 in the nineteenth embodiment);
Equipped with
The save execution means saves the specified information into the specified storage means in response to a load command.

According to feature M1, when the situation changes from the situation where the first predetermined process is being executed to the situation where the second predetermined process is being executed or when the situation where the second predetermined process is being executed occurs, the predetermined information, which is at least a part of the information stored in the internal storage means, is saved to the predetermined storage means. This makes it possible to prevent the information stored in the internal storage means from being rewritten when the first predetermined process is executed when the second predetermined process is executed. In addition, when or after the second predetermined process is terminated, the predetermined information saved in the predetermined storage means is restored to the internal storage means. This makes it possible to execute a process different from the second predetermined process from the state of the internal storage means before the execution of the second predetermined process when the second predetermined process is terminated. When the situation changes from the situation where the first predetermined process is being executed to the situation where the second predetermined process is being executed or when the situation where the second predetermined process is being executed occurs, the predetermined information is saved to the predetermined storage means by a load command. This makes it possible to save the predetermined information without the need to change the stack pointer.

Feature M2. The predetermined storage means is
a stack area (non-specific control stack area 224) into which information can be written by a push command and into which information can be read by a pop command;
A work area (non-specific control work area 223) in which information can be written and read by a load command;
Equipped with
The gaming machine according to feature M1, wherein the save execution means saves the specified information in the work area.

According to feature M2, the destination for saving the specific information, which is at least a portion of the information stored in the internal storage means, is the work area, making it possible to save the information without making cumulative changes to the stack pointer.

Feature M3: The predetermined information is a part of the information stored in the internal storage means,
The gaming machine described in feature M2 is characterized in that the save execution means is equipped with a means (a function of executing the processing of step S3802 in the main CPU 63) for saving specific information, which is a part of the information stored in the internal storage means, to the stack area when the situation changes from one in which the first specified processing is being executed to one in which the second specified processing is being executed, or when the situation changes to one in which the second specified processing is being executed.

According to feature M3, in a configuration in which predetermined information is saved to a work area, specific information is saved to a stack area. This makes it possible to distribute and save information stored in the internal storage means to the work area and stack area.

Feature M4. The gaming machine described in Feature M3, characterized in that the predetermined information contains more information than the specific information.

According to feature M4, by saving predetermined information, which has a larger amount of information than specific information, in the work area, it is possible to prevent a large amount of information from being cumulatively stored in the stack area when saving information stored in the internal storage means.

Feature M5. The work area is
a first work area (a work area 221 for specific control) in which information is stored when the first predetermined process is executed;
A second work area (a work area 223 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
A gaming machine described in any one of features M2 to M4, wherein the save execution means saves the specified information in the second work area.

According to feature M5, by providing the work area with a first work area and a second work area, it is possible to clearly differentiate the storage destination of information in the work area between the first and second predetermined processes. This makes it possible to prevent information used in one of the first and second predetermined processes from being erased when the other process is executed. In this case, when the situation changes from the execution of the first predetermined process to the execution of the second predetermined process or when the situation changes to the execution of the second predetermined process, at least a portion of the information stored in the internal storage means is saved to the second work area. This makes it possible to save information in the internal storage means immediately before the start of the second predetermined process, and to save the information without using the first work area.

Feature M6: The first work area is capable of storing information and reading information when the first predetermined process is executed, and is capable of reading information but is not capable of storing information when the second predetermined process is executed;
A gaming machine as described in feature M5, characterized in that the second work area is capable of storing information and reading information when the second specified process is executed, and that when the first specified process is executed, information can be read but information cannot be stored.

Feature M6 makes it possible to treat the first work area as a dedicated memory area for the first specified process, and to treat the second work area as a dedicated memory area for the second specified process.

Feature M7. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes;
The control means includes:
A first predetermined processing execution means for executing a first predetermined processing among the various processing (a function for executing processing other than the management execution processing in the main CPU 63 in the fifteenth to twenty-first embodiments);
A second predetermined processing execution means (a function of executing a management execution process in the main CPU 63 in the fifteenth to twenty-first embodiments) that executes a second predetermined processing among the various processing;
When the situation changes from the situation where the first predetermined processing is being executed to the situation where the second predetermined processing is being executed or when the situation where the second predetermined processing is being executed is reached, a save execution means saves predetermined information, which is at least a part of the information stored in the internal storage means, to a predetermined storage means (main RAM 65) (in the fifteenth embodiment, a function for executing the processing of steps S3902 to S3907 in the main CPU 63; in the seventeenth embodiment, a function for executing the processing of steps S4502 to S4507 in the main CPU 63; in the eighteenth embodiment, a function for executing the processing of step S4602 in the main CPU 63; and in the nineteenth embodiment, a function for executing the processing of steps S4701 and S4703 in the main CPU 63);
A restoration execution means for restoring the predetermined information saved in the predetermined storage means to the internal storage means when or after the second predetermined process is completed (a function for executing the processes of steps S3910 to S3915 in the main CPU 63 in the fifteenth embodiment, a function for executing the processes of steps S4510 to S4515 in the main CPU 63 in the seventeenth embodiment, a function for executing the processes of step S4605 in the main CPU 63 in the eighteenth embodiment, and a function for executing the processes of steps S4705 and S4706 in the main CPU 63 in the nineteenth embodiment);
Equipped with
The predetermined storage means includes:
a stack area (non-specific control stack area 224) into which information can be written by a push command and into which information can be read by a pop command;
A work area (non-specific control work area 223) in which information can be written and read by a load command;
Equipped with
The gaming machine is characterized in that the save execution means saves the specified information to one of the stack area and the work area.

According to feature M7, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, the predetermined information, which is at least a portion of the information stored in the internal storage means, is saved to the predetermined storage means. This makes it possible to prevent the information stored in the internal storage means from being overwritten when the first predetermined process is executed when the second predetermined process is executed. Furthermore, when or after the second predetermined process is terminated, the predetermined information saved in the predetermined storage means is restored to the internal storage means. This makes it possible to execute a process different from the second predetermined process from the state of the internal storage means before the execution of the second predetermined process when the second predetermined process is terminated.

In addition, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, the above-mentioned predetermined information is saved to one of the stack area and the work area in the predetermined storage means. This makes it possible to consolidate the destinations for saving information, and to simplify the processing configuration for saving and the processing configuration for restoring.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features M1 to M7. This allows for a synergistic effect to be achieved through the combined configuration.

<Feature N group>
Feature N1. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes;
The control means includes:
A first predetermined processing execution means for executing a first predetermined processing among the various processing (a function for executing processing other than the management execution processing in the main CPU 63 in the fifteenth to twenty-first embodiments);
A second predetermined processing execution means (a function of executing a management execution process in the main CPU 63 in the fifteenth to twenty-first embodiments) that executes a second predetermined processing among the various processing;
Equipped with
A gaming machine characterized in that when the situation changes from one in which the first specified process is being executed to one in which the second specified process is being executed, the information of a stack pointer stored in the internal memory means becomes fixed information.

According to feature N1, when the situation changes from the execution of the first predetermined process to the execution of the second predetermined process, the stack pointer information stored in the internal storage means becomes fixed information, so there is no need to save the stack pointer information when starting the second predetermined process. This eliminates the need to secure a storage area for saving the stack pointer information. In addition, when the situation changes from the execution of the first predetermined process to the execution of the second predetermined process, the stack pointer information becomes fixed information, so it is possible to restore the stack pointer information to the state before the second predetermined process was started without having to save the stack pointer information as described above.

Feature N2. A gaming machine according to Feature N1, characterized in that it is provided with a means for setting the fixed information in the stack pointer when or after the second predetermined process is completed (a function for executing the process of step S3909 in the main CPU 63 in the fifteenth embodiment, a function for executing the process of step S4509 in the main CPU 63 in the seventeenth embodiment, and a function for executing the process of step S4604 in the main CPU 63 in the eighteenth embodiment).

According to feature N2, when or after the second specified process is terminated, it is possible to restore the stack pointer information to the state before the second specified process was started.

Feature N3. A gaming machine according to feature N1 or N2, characterized in that it is provided with a means for setting second response start information corresponding to the second predetermined processing in the stack pointer when the situation changes from one in which the first predetermined processing is being executed to one in which the second predetermined processing is being executed (in the fifteenth embodiment, a function for executing the processing of step S3901 in the main CPU 63; in the seventeenth embodiment, a function for executing the processing of step S4501 in the main CPU 63; in the eighteenth embodiment, a function for executing the processing of step S4601 in the main CPU 63).

According to feature N3, when the second predetermined process is started, second corresponding start information corresponding to the second predetermined process is set in the stack pointer, making it possible to store information in the stack area at an appropriate address in the second predetermined process.

Feature N4. When the situation where the first predetermined process is being executed changes to the situation where the second predetermined process is being executed or when the situation where the second predetermined process is being executed is reached, a save execution means for saving predetermined information, which is at least a part of the information stored in the internal storage means, to a predetermined storage means (main RAM 65) (in the fifteenth embodiment, a function for executing the processing of steps S3802 and steps S3902 to S3907 in the main CPU 63; in the sixteenth embodiment, a function for executing the processing of steps S4402 in the main CPU 63; in the seventeenth embodiment, a function for executing the processing of steps S4502 to S4507 in the main CPU 63; in the eighteenth embodiment, a function for executing the processing of step S4602 in the main CPU 63; in the nineteenth embodiment, a function for executing the processing of steps S4701 and S4703 in the main CPU 63);
a return execution means for returning the specified information saved in the specified storage means to the internal storage means when or after the second specified process is completed (in the fifteenth embodiment, a function for executing the processes of steps S3804 and S3910 to S3915 in the main CPU 63; in the sixteenth embodiment, a function for executing the processes of step S4404 in the main CPU 63; in the seventeenth embodiment, a function for executing the processes of steps S4510 to S4515 in the main CPU 63; in the eighteenth embodiment, a function for executing the processes of step S4605 in the main CPU 63; and in the nineteenth embodiment, a function for executing the processes of steps S4705 and S4706 in the main CPU 63);
Equipped with
A gaming machine described in any one of features N1 to N3, characterized in that information of a stack pointer provided in the internal storage means is not subject to saving by the save execution means.

According to feature N4, when the situation changes from the execution of the first predetermined process to the execution of the second predetermined process or when the situation changes to the execution of the second predetermined process, at least a part of the information stored in the internal storage means is saved to the specified storage means. This makes it possible to prevent the information stored in the internal storage means from being rewritten when the second predetermined process is executed. Also, when or after the second predetermined process is terminated, the information saved in the specified storage means is restored to the internal storage means. This makes it possible to execute a process different from the second predetermined process from the state of the internal storage means before the execution of the second predetermined process when the second predetermined process is terminated. Also, since the stack pointer information is not subject to saving, there is no need to secure capacity in the specified storage means to save the stack pointer information. This makes it possible to reduce the capacity of the specified storage means. Furthermore, even in a configuration in which the stack pointer information is not saved in this manner, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, the stack pointer information becomes fixed information, so it is possible to restore the stack pointer information to the information before the second predetermined process was started without having to save the stack pointer information as described above.

Feature N5. The predetermined storage means is
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
A second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
The gaming machine described in feature N4, wherein the save execution means saves the specified information to the second specified memory area.

According to feature N5, by providing the predetermined storage means with a first predetermined storage area and a second predetermined storage area, it is possible to clearly differentiate the storage destination of information in the predetermined storage means between the first predetermined process and the second predetermined process. This makes it possible to prevent information used in one of the first and second predetermined processes from being erased when the other process is executed. In this case, when the situation changes from the execution of the first predetermined process to the execution of the second predetermined process or when the situation changes to the execution of the second predetermined process, at least a portion of the information stored in the internal storage means is saved to the second predetermined storage area. This makes it possible to save the information in the internal storage means immediately before the start of the second predetermined process, and to save the information without using the first predetermined storage area.

Feature N6: The first predetermined memory area is capable of storing information and reading information when the first predetermined process is executed, and is capable of reading information but is not capable of storing information when the second predetermined process is executed;
A gaming machine as described in feature N5, characterized in that the second specified memory area is capable of storing information and reading information when the second specified process is executed, and when the first specified process is executed, information can be read but information cannot be stored.

Feature N6 makes it possible to treat the first specified memory area as a memory area dedicated to the first specified process, and to treat the second specified memory area as a memory area dedicated to the second specified process.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features N1 to N6. This allows for a synergistic effect to be achieved through the combined configuration.

<Characteristic group O>
Feature O1. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes;
The control means includes:
A first predetermined processing execution means for executing a first predetermined processing among the various processing (a function for executing processing other than the management execution processing in the main CPU 63 in the fifteenth to twenty-first embodiments);
A second predetermined processing execution means (a function of executing a management execution process in the main CPU 63 in the fifteenth to twenty-first embodiments) that executes a second predetermined processing among the various processing;
When the state where the first predetermined process is being executed is changed to the state where the second predetermined process is being executed or when the state where the second predetermined process is being executed is changed, a first state setting means (a function of executing the processes of steps S4803 to S4808 in the main CPU 63) sets the state of a predetermined memory area (WA register, BC register, DE register, HL register, IX register, and IY register), which is at least a part of the memory area in the internal memory means, to a predetermined state;
A second state setting means (a function of executing the processes of steps S4903 to S4908 in the main CPU 63) that sets the state of the predetermined storage area to the predetermined state when or after the second predetermined process is completed;
A gaming machine comprising:

According to feature O1, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed or when the situation changes to one in which the second predetermined process is being executed, the state of the predetermined storage area of the internal storage means is set to a predetermined state, and when the second predetermined process is terminated or after it has been terminated, the state of the predetermined storage area is set to the predetermined state again. This makes it possible to set the state of the predetermined storage area to a predetermined state before and after the second predetermined process. Therefore, it is possible to prevent the state of the predetermined storage area due to one of the first and second predetermined processes from affecting the other process. As a result, various controls can be performed in an optimal manner.

Feature O2. The gaming machine described in Feature O1, characterized in that the predetermined state is a state when the supply of operating power to the control means is started.

According to feature O2, the specified memory area is set to the specified state when the supply of operating power to the control means is started, so the processing configuration for setting the specified state can be simplified.

Feature O3. The gaming machine according to feature O1 or O2, wherein the predetermined state is a state in which the predetermined memory area is cleared to "0."

According to feature O3, the specified memory area is set to a "0" cleared state as the specified state, so the processing configuration for setting the specified state can be simplified.

Feature O4. A gaming machine according to any one of Features O1 to O3, characterized in that the specified memory area is a partial memory area in the internal memory means.

According to feature O4, only a portion of the storage area of the internal storage means is set to a predetermined state, which makes it possible to reduce the processing load required for setting the predetermined state.

Feature O5. The internal storage means includes at least the predetermined storage area and another storage area (registers other than the WA register, the BC register, the DE register, the HL register, the IX register, and the IY register);
the second predetermined process execution means is configured to store information in the predetermined storage area during the second predetermined process, but not to store information in the separate storage area;
A gaming machine described in feature O4, characterized in that the first state setting means and the second state setting means are configured not to change the state of the separate memory area.

According to feature O5, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, the predetermined storage area in the internal storage means in which information is to be stored in the second predetermined process is set to a predetermined state. This makes it possible to prevent the state of the predetermined storage area by the first predetermined process from affecting the second predetermined process. In addition, since the state of the separate storage area is not changed, it is possible to prevent setting the predetermined state when the second predetermined process is started from affecting the processing after the second predetermined process is completed.

Feature O6. A gaming machine according to any one of Features O1 to O5, characterized in that the information in the specified memory area before the first state setting means sets the specified state is information that is not used after the second specified process is completed.

According to feature O6, even if the specified memory area is set to a specified state when the second specified process is executed or when the second specified process is executed, it is possible to prevent the processing after the second specified process is completed from being affected.

Feature O7. When the situation where the first predetermined process is being executed changes to the situation where the second predetermined process is being executed or when the situation where the second predetermined process is being executed is reached, a save execution means (function for executing the process of step S4802 in the main CPU 63) saves predetermined information (information in the flag register), which is a part of the information stored in the internal storage means, to a predetermined storage means (main RAM 65);
A return execution means (a function of executing the processing of step S4810 in the main CPU 63) for returning the specified information saved in the specified storage means to the internal storage means when or after the second specified processing is terminated;
A gaming machine described in any one of features O1 to O6, characterized by comprising:

According to feature O7, when the situation changes from the execution of the first predetermined process to the execution of the second predetermined process or when the situation changes to the execution of the second predetermined process, the predetermined information, which is a part of the information stored in the internal storage means, is saved to the predetermined storage means. This makes it possible to prevent information stored in the internal storage means when the first predetermined process is executed and which will be necessary when the first predetermined process is subsequently executed from being overwritten when the second predetermined process is executed. Also, when or after the second predetermined process is terminated, the predetermined information saved in the predetermined storage means is restored to the internal storage means. This makes it possible to execute a process different from the second predetermined process from the state of the internal storage means before the execution of the second predetermined process when the second predetermined process is terminated.

Feature O8. The first predetermined process includes a process for controlling the progress of a game;
A gaming machine described in any one of features O1 to O7, characterized in that the second specified process includes a process for managing a gaming history.

According to feature O8, a process for controlling the progress of a game is executed as a first predetermined process, and a process for managing a game history is executed as a second predetermined process, so that it is possible to prevent information used in the process for managing a game history from being rewritten when the process for controlling the progress of a game is executed.

Feature O9. The predetermined storage means is
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
A second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
The gaming machine described in feature O8 is characterized in that the second specified memory area is provided with a history memory area (normal counter area 231, counter area 232 for opening/closing execution mode, counter area 233 for high frequency support mode) in which corresponding game history information is stored when a specified event occurs as a result of the game being played.

According to feature O9, when a specified event occurs, the corresponding history information is stored in the history storage area. This allows the gaming machine to store and hold information for managing the number of times or frequency of occurrence of the specified event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of the specified event. Furthermore, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by executing a process for controlling the progress of the game as the first specified process, and executing a process for managing the game history as the second specified process, it becomes possible to prevent the information stored in the history storage area from being rewritten when the process for controlling the progress of the game is executed.

Feature O10. The gaming machine described in Feature O9, characterized in that the second predetermined process execution means includes information derivation means (a function for executing the process of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to the game results during a predetermined period.

According to feature O10, by deriving behavior information corresponding to the results of play during a specified period of time using the history information stored in the history storage area, it becomes possible to grasp the results of management of the play history, such as the frequency of occurrence of a specified event.

Feature O11. The gaming machine described in Feature O10, characterized in that the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature O11, when behavior information corresponding to the results of a game during a specified period is derived using history information, the behavior information is stored in a behavior information storage area. This makes it possible to grasp the results of managing the game history at any time. In addition, by executing a process for controlling the progress of a game as the first specified process and a process for managing the game history as the second specified process, it becomes possible to prevent the information stored in the behavior information storage area from being overwritten when the process for controlling the progress of a game is executed.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features O1 to O11. This allows for a synergistic effect to be achieved through the combined configuration.

<Feature P group>
Feature P1. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes;
The control means includes:
A first predetermined processing execution means for executing a first predetermined processing among the various processing (a function for executing processing other than the management execution processing in the main CPU 63 in the fifteenth to twenty-first embodiments);
A second predetermined processing execution means (a function of executing a management execution process in the main CPU 63 in the fifteenth to twenty-first embodiments) that executes a second predetermined processing among the various processing;
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
A second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
A gaming machine comprising:

According to feature P1, a first predetermined storage area and a second predetermined storage area are provided, the first predetermined storage area is treated as a storage area dedicated to the first predetermined process, and the second predetermined storage area is treated as a storage area dedicated to the second predetermined process. This makes it possible to clearly differentiate the storage destination of information in the predetermined storage means between the first predetermined process and the second predetermined process. Therefore, it becomes possible to prevent information used in one of the first and second predetermined processes from being erased when the other process is executed.

Feature P2. The first predetermined process includes a process for controlling the progress of a game,
A gaming machine according to feature P1, characterized in that the second predetermined process includes a process for managing gaming history.

According to feature P2, a process for controlling the progress of a game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, so that it is possible to prevent information used in the process for managing the game history from being rewritten when the process for controlling the progress of a game is executed.

Feature P3. The gaming machine described in Feature P2, characterized in that the second predetermined storage area includes a history storage area (normal counter area 231, open/close execution mode counter area 232, high frequency support mode counter area 233) in which history information of a game corresponding to a predetermined event that occurs as a result of the game being played is stored.

According to feature P3, when a specified event occurs, the corresponding history information is stored in the history storage area. This allows the gaming machine to store and hold information for managing the number of times or frequency of occurrence of the specified event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of the specified event. Furthermore, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by executing a process for controlling the progress of the game as the first specified process, and executing a process for managing the game history as the second specified process, it becomes possible to prevent the information stored in the history storage area from being rewritten when the process for controlling the progress of the game is executed.

Feature P4. The gaming machine described in Feature P3, characterized in that the second predetermined process execution means includes information derivation means (a function for executing the process of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to the game results during a predetermined period.

According to feature P4, by deriving behavior information corresponding to the results of play during a specified period of time using the history information stored in the history storage area, it becomes possible to grasp the results of management of the play history, such as the frequency of occurrence of a specified event.

Feature P5. The gaming machine described in Feature P4, characterized in that the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature P5, when behavior information corresponding to the results of a game during a specified period is derived using history information, the behavior information is stored in the behavior information storage area. This makes it possible to grasp the results of game history management at any time. In addition, by executing a process for controlling the progress of a game as the first specified process and a process for managing the game history as the second specified process, it becomes possible to prevent the information stored in the behavior information storage area from being overwritten when the process for controlling the progress of a game is executed.

Feature P6: A first saving means for saving the first predetermined information, which is a part of the information stored in the internal storage means, in the first predetermined processing when the situation changes from the situation where the first predetermined processing is being executed to the situation where the second predetermined processing is being executed, to the first predetermined storage area in the first predetermined processing (a function for executing the processing of step S3802 in the main CPU 63 in the fifteenth embodiment, and a function for executing the processing of step S4402 in the main CPU 63 in the sixteenth embodiment);
A second saving means for saving second predetermined information, which is a part of information stored in the internal storage means, to the second predetermined storage area in the second predetermined processing when the situation changes from the situation where the first predetermined processing is being executed to the situation where the second predetermined processing is being executed (in the fifteenth embodiment, a function for executing the processing of steps S3902 to S3907 in the main CPU 63; in the seventeenth embodiment, a function for executing the processing of steps S4502 to S4507 in the main CPU 63; in the eighteenth embodiment, a function for executing the processing of step S4602 in the main CPU 63; and in the nineteenth embodiment, a function for executing the processing of steps S4701 and S4703 in the main CPU 63);
A gaming machine according to any one of features P1 to P5, characterized in that it is equipped with:

According to feature P6, the first predetermined information, which is a portion of the information stored in the internal storage means, is saved to a first predetermined storage area by a first predetermined process, and the second predetermined information, which is a portion of the information stored in the internal storage means, is saved to a second predetermined storage area by a second predetermined process. This makes it possible to save each piece of information stored in the internal storage means at a time that is favorable for that piece of information, and also makes it possible to distribute the process for saving information between the first predetermined process and the second predetermined process.

Feature P7: A first return execution means for returning the first predetermined information saved in the first predetermined storage area to the internal storage means when or after the second predetermined process is ended (a function for executing the process of step S3804 in the main CPU 63 in the fifteenth embodiment, and a function for executing the process of step S4404 in the main CPU 63 in the sixteenth embodiment);
A second return execution means for returning the second specified information saved in the second specified storage area to the internal storage means when or after the second specified processing is completed (in the fifteenth embodiment, a function for executing the processing of steps S3910 to S3915 in the main CPU 63; in the seventeenth embodiment, a function for executing the processing of steps S4510 to S4515 in the main CPU 63; in the eighteenth embodiment, a function for executing the processing of step S4605 in the main CPU 63; and in the nineteenth embodiment, a function for executing the processing of steps S4705 and S4706 in the main CPU 63);
The gaming machine described in feature P6 is characterized by comprising:

According to feature P7, when or after the second predetermined process is completed, the first predetermined information saved in the first predetermined storage area is restored to the internal storage means, and the second predetermined information saved in the second predetermined storage area is restored to the internal storage means, so that it is possible to restore the state of the internal storage means to the state before the second predetermined process was started.

Feature P8. The gaming machine described in Feature P6 or P7, characterized in that the first predetermined information includes information of a flag register provided in the internal storage means.

Feature P8 makes it possible to properly save the information in the flag register when the first specified process is being executed.

Feature P9. A gaming machine according to any one of features P6 to P8, characterized in that the second predetermined information includes information of all registers of the internal storage means.

According to feature P9, the information in all registers of the internal storage means is saved together, eliminating the need to selectively save register information.

Feature P10. The second predetermined storage area is
a stack area (non-specific control stack area 224) in which information is written by a push command and in which information is read by a pop command;
A work area (non-specific control work area 223) in which information is written and read by a load command;
Equipped with
The gaming machine described in feature P9, wherein the second save execution means saves the second specified information to one of the stack area and the work area.

According to feature P10, the information of all registers of the internal storage means is saved to one of the stack area and the work area in the second predetermined storage area. This makes it possible to consolidate the destinations for saving the information of all registers, and simplifies the processing configuration for saving and restoring the information.

Feature P11. The gaming machine described in Feature P10, wherein the second save execution means saves the second predetermined information in the stack area.

Feature P11 makes it possible to save the information in all registers without using the work area.

Feature P12. A gaming machine according to any one of features P6 to P11, characterized in that the second predetermined information includes stack pointer information of the internal storage means.

Feature P12 makes it possible to properly save stack pointer information when the first specified process is being executed.

In addition, any one or more of the following configurations may be applied to the configurations of features P1 to P12: features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7. This allows for a synergistic effect to be achieved through the combined configuration.

The invention relating to the above-mentioned feature group L, feature group M, feature group N, feature group O, and feature group P can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine that stores gaming balls given to a player, and the gaming balls stored in the tray storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entrance section provided in the gaming area, the gaming ball is paid out from a payout device to the tray storage section. In addition, a configuration in which an upper tray storage section and a lower tray storage section are provided as the tray storage section is also known in pachinko gaming machines, in which the gaming balls stored in the upper tray storage section are guided to the gaming ball launching device, and the gaming balls that are surplus in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the reels have stopped rotating corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, various controls need to be performed appropriately, and there is still room for improvement in this regard.

<Feature Q group>
Feature Q1. A control means (MPU 62) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when the processes are executed;
A history storage means (management RAM 241) that is provided as a chip separate from the control means and is capable of temporarily storing information;
Equipped with
The control means is a gaming machine characterized in that it is equipped with a history memory execution means (a function of executing normal ball entry management processing in the main CPU 63, ball entry management processing during the opening and closing execution mode, and ball entry management processing during the high frequency support mode) that stores the corresponding game history information in the history memory means when a specified event occurs as a result of the game being played.

According to feature Q1, when a specified event occurs, the corresponding history information is stored in the history storage means. This makes it possible for the gaming machine to store and hold information for managing the number of times or frequency of occurrence of the specified event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of the specified event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, since the history storage means is provided as a chip separate from the control means, it is possible to increase the memory capacity for storing history information while using a general-purpose control means.

Feature Q2. The gaming machine described in Feature Q1 is characterized in that the control means includes a predetermined storage means (main RAM 65) that temporarily stores information when various processes are executed.

According to feature Q2, in a configuration that includes not only a predetermined storage means provided in the control means but also a history storage means provided as a chip separate from the control means, it is possible to store and hold a large amount of history information by storing the history information in the history storage means.

Feature Q3. The gaming machine described in Feature Q2, wherein the control means temporarily stores information in the predetermined storage means when executing processing related to the history information.

According to feature Q3, in a configuration in which a history storage means for storing history information is provided as a chip separate from the control means, when processing related to the history information is executed, the information is temporarily stored in a predetermined storage means provided in the control means, so that it is possible to prevent an extreme decrease in processing speed when processing related to the history information is executed.

Feature Q4. A gaming machine according to any one of Features Q1 to Q3, characterized in that the control means includes information derivation means (a function for executing the process of step S4208 in the main CPU 63) that utilizes the history information stored in the history storage means to derive behavior information corresponding to game results during a predetermined period.

According to feature Q4, by deriving behavior information corresponding to the results of play during a specified period of time using the history information stored in the history storage means, it becomes possible to grasp the results of management of the play history, such as the frequency of occurrence of a specified event.

Feature Q5. The gaming machine described in Feature Q4, characterized in that the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature Q5, when behavior information corresponding to the results of play during a specified period is derived using history information, the behavior information is stored in the behavior information storage area. This makes it possible to grasp the results of game history management at any time.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features Q1 to Q5. This allows for a synergistic effect to be achieved through the combined configuration.

The invention relating to the above group of features Q can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine that stores gaming balls given to a player, and the gaming balls stored in the tray storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out from, for example, a payout device to the tray storage section. In addition, a configuration in which an upper tray storage section and a lower tray storage section are provided as the tray storage section is also known for a pachinko machine, and in this case, the gaming balls stored in the upper tray storage section are guided to the gaming ball launching device, and the gaming balls that are surplus in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the reels have stopped rotating corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, gaming machines such as those exemplified above need to be properly managed, and there is still room for improvement in this regard.

<Feature R group>
Feature R1. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
A situation generating means for generating a setting possible situation in which the setting means can set the setting value to be used based on the occurrence of a plurality of events including a first event and a second event when the supply of operating power to the control means having the setting means is started (a function for executing the processing of steps S5003 to S5006 in the main CPU 63 in the 22nd embodiment, a function for executing the processing of steps S5503 to S5507 in the main CPU 63 in another embodiment, and a function for executing the processing of steps S5703 to S5705 and step S5715 in the main CPU 63 in the 23rd embodiment);
A gaming machine comprising:

According to feature R1, the setting value to be used is set from among multiple setting values corresponding to the player's degree of advantage, so the player will hope that the more advantageous setting value will be the setting value to be used. In this case, in order for the setting value to be used to be set, multiple events including the first event and the second event must occur when the supply of operating power to the control means begins. This makes it difficult to fraudulently set the setting value to be used.

Feature R2. Equipped with an open detection means for detecting that the opening/closing body (front door frame 14) is in the open state (a function for executing the process of step S5005 in the main CPU 63 in the 22nd embodiment, a function for executing the process of step S5505 in the main CPU 63 in another embodiment, and a function for executing the process of step S5703 in the main CPU 63 in the 23rd embodiment),
The gaming machine described in feature R1, wherein the situation generation means determines that the first event has occurred based on the opening detection means detecting that the opening/closing body is in an open state.

According to feature R2, the opening and closing body must be in the open state in order for the setting value to be used to be set. This makes it possible to highlight the fraudulent act if someone tries to fraudulently set the setting value to be used, which makes it easier to discover the fraudulent act.

Feature R3. Equipped with separate opening grasping means for grasping that the separate opening/closing body (the gaming machine main body 12) is in the open state (a function for executing the process of step S5006 in the main CPU 63 in the 22nd embodiment, a function for executing the process of step S5506 in the main CPU 63 in another embodiment, and a function for executing the process of step S5704 in the main CPU 63 in the 23rd embodiment),
The gaming machine described in feature R2, wherein the situation generation means determines that the second event has occurred based on the separate opening detection means detecting that the separate opening/closing body is in an open state.

According to feature R3, in order to set the setting value to be used, not only is the opening and closing body required to be in the open state, but the separate opening and closing body must also be in the open state. This makes it difficult to fraudulently set the setting value to be used, and makes the fraudulent behavior more noticeable.

Feature R4: The setting means is configured to select the setting value to be used and/or set the setting value to be used based on the operation of a predetermined operation means (update button 68b, reset button 68c),
The gaming machine according to feature R2 or R3, wherein the predetermined operation means is configured to be operable by opening a separate opening/closing body.

According to feature R4, the setting value to be used cannot be set unless an opening/closing body that is different from the other opening/closing body that is opened to enable the operation of the specified operating means is opened. This makes it difficult to fraudulently set the setting value to be used, and makes the fraudulent behavior noticeable.

Feature R5. The opening and closing body defines the front side of the gaming machine of the gaming area into which the gaming balls flow,
A gaming machine described in any one of features R2 to R4, characterized in that the gaming area is opened to the front of the gaming machine by opening the opening/closing body.

According to feature R5, in order to set the setting value to be used, it is necessary to open the opening and closing body to open the gaming area to the front of the gaming machine. This makes it difficult to fraudulently set the setting value to be used, and makes the fraudulent behavior more noticeable.

Feature R6. A gaming machine according to any one of Features R1 to R5, characterized in that the situation generating means determines that one of the plurality of events has occurred based on a predetermined operation being performed using a setting key on a setting key insertion section (setting key insertion section 68a).

According to feature R6, in order to set the setting value to be used, it is necessary not only to perform a specific operation using the setting key on the setting key insertion section, but also to cause a different event to occur. This makes it difficult to fraudulently set the setting value to be used.

Feature R7. A gaming machine according to any one of features R1 to R6, characterized in that the situation generating means identifies that one of the plurality of events has occurred based on the occurrence of a predetermined game event (operation of the launch operating device 28, entry of a ball into the through gate 35) that occurs when a game is played.

According to feature R7, in order to set the setting value to be used, not only is it necessary to cause a specific game event that occurs when a game is played to occur, but it is also necessary to cause a different event to occur. This makes it difficult to fraudulently set the setting value to be used.

Feature R8. The gaming machine according to any one of features R1 to R7, characterized in that the situation generating means determines that one of the plurality of events has occurred based on the detection of a gaming ball by a ball entry detection means (gate detection sensor 49a) that detects that a gaming ball has entered a predetermined ball entry portion provided in the gaming area.

According to feature R8, in order to set the setting value to be used, it is necessary to have a game ball enter a specific ball entry section, and a separate event must occur. This makes it difficult to fraudulently set the setting value to be used.

Feature R9. A setting value notification means (a function of executing a setting confirmation process in the main CPU 63) that notifies the setting value to be used set by the setting means by a notification means,
The gaming machine described in any one of features R1 to R8, characterized in that the setting value notification means notifies the setting value to be used, which is set by the setting means, based on the occurrence of a plurality of events including the first event and the second event.

Feature R9 makes it difficult to fraudulently check setting values. In addition, the manager of the amusement hall only needs to cause the first and second events to occur whether setting the setting value to be used or checking the setting value, so the tasks are standardized and each task is easy to understand.

Feature R10. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
A situation generating means for generating a setting possible situation in which the setting means can set the setting value to be used based on the occurrence of a plurality of events including both a predetermined operation using a setting key on a setting key insertion section (setting key insertion section 68a) and another event different from the predetermined operation using the setting key on the setting key insertion section (a function for executing the processing of steps S5003 to S5006 in the main CPU 63 in the 22nd embodiment, a function for executing the processing of steps S5503 to S5507 in the main CPU 63 in another embodiment, and a function for executing the processing of steps S5703 to S5705 and step S5715 in the main CPU 63 in the 23rd embodiment);
A gaming machine comprising:

According to feature R10, the setting value to be used is set from among multiple setting values corresponding to the player's degree of advantage, so the player will hope that the more advantageous setting value will be the setting value to be used. In this case, in order to set the setting value to be used, it is necessary not only to perform a specified operation using the setting key on the setting key insertion section, but also to cause a different event to occur. This makes it difficult to fraudulently set the setting value to be used.

Feature R11. Equipped with an open detection means for detecting that the opening/closing body (front door frame 14) is in the open state (a function for executing the process of step S5005 in the main CPU 63 in the 22nd embodiment, a function for executing the process of step S5505 in the main CPU 63 in another embodiment, and a function for executing the process of step S5703 in the main CPU 63 in the 23rd embodiment),
The gaming machine described in feature R10, wherein the situation generation means determines that the different event has occurred based on the fact that the opening/closing body is in an open state being detected by the opening detection means.

According to feature R11, the opening and closing body must be in the open state in order for the setting value to be used to be set. This makes it possible to highlight the fraudulent act if someone tries to fraudulently set the setting value to be used, which makes it easier to discover the fraudulent act.

Feature R12. Equipped with separate opening grasping means for grasping that the separate opening/closing body (the gaming machine main body 12) is in the open state (a function for executing the process of step S5006 in the main CPU 63 in the 22nd embodiment, a function for executing the process of step S5506 in the main CPU 63 in another embodiment, and a function for executing the process of step S5704 in the main CPU 63 in the 23rd embodiment),
The gaming machine described in feature R11, wherein the situation generation means determines that one of the multiple events has occurred based on the fact that the separate opening/closing body is in an open state being detected by the separate opening detection means.

According to feature R12, in order to set the setting value to be used, not only is the opening and closing body required to be in the open state, but the separate opening and closing body must also be in the open state. This makes it difficult to fraudulently set the setting value to be used, and makes the fraudulent behavior more noticeable.

Feature R13: The setting means is configured to select the setting value to be used and/or set the setting value to be used based on the operation of a predetermined operation means (update button 68b, reset button 68c),
The gaming machine according to feature R11 or R12, wherein the predetermined operation means is configured to be operable by opening a separate opening/closing body.

According to feature R13, the setting value to be used cannot be set unless an opening/closing body that is different from the other opening/closing body that is opened to enable operation of the specified operating means is opened. This makes it difficult to fraudulently set the setting value to be used, and makes the fraudulent behavior noticeable.

Feature R14. The opening and closing body defines the front side of the gaming machine of the gaming area into which the gaming balls flow,
A gaming machine described in any one of features R11 to R13, characterized in that the gaming area is opened to the front of the gaming machine by opening the opening/closing body.

According to feature R14, in order to set the setting value to be used, it is necessary to open the opening and closing body to open the gaming area to the front of the gaming machine. This makes it difficult to fraudulently set the setting value to be used, and makes the fraudulent behavior more noticeable.

Feature R15. A gaming machine according to any one of features R10 to R14, characterized in that the situation generating means identifies that one of the plurality of events has occurred based on the occurrence of a predetermined game event (operation of the launch operating device 28, entry of a ball into the through gate 35) that occurs when a game is played.

According to feature R15, in order to set the setting value to be used, it is necessary not only to perform a predetermined operation using the setting key on the setting key insertion section, but also to cause a predetermined game event that occurs when a game is played. This makes it difficult to fraudulently set the setting value to be used.

Feature R16. A gaming machine according to any one of features R10 to R15, characterized in that the situation generating means determines that one of the plurality of events has occurred based on the detection of a gaming ball by a ball entry detection means (gate detection sensor 49a) that detects that a gaming ball has entered a predetermined ball entry portion provided in the gaming area.

According to feature R16, in order to set the setting value to be used, it is necessary not only to perform a predetermined operation using the setting key on the setting key insertion section, but also to have a game ball enter a predetermined ball entry section. This makes it difficult to fraudulently set the setting value to be used.

Feature R17: A setting value notification means (a function of executing a setting confirmation process in the main CPU 63) is provided for notifying the setting value to be used set by the setting means through a notification means;
The gaming machine described in any one of features R10 to R16, characterized in that the setting value notification means notifies the setting value to be used, which is set by the setting means, based on the occurrence of a plurality of events including both the specified operation using the setting key on the setting key insertion portion and the separate event.

Feature R17 makes it difficult to fraudulently check setting values. In addition, whether the amusement hall manager is setting a setting value to be used or checking a setting value, he or she only needs to perform a specific operation using the setting key in the setting key insertion section and cause a different event to occur, so the tasks are standardized and each task is easy to understand.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features R1 to R17. This allows for a synergistic effect to be achieved through the combined configuration.

The invention relating to the above feature group R can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine that stores gaming balls given to a player, and the gaming balls stored in the tray storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out from, for example, a payout device to the tray storage section. In addition, a configuration in which an upper tray storage section and a lower tray storage section are provided as the tray storage section is also known for a pachinko machine, and in this case, the gaming balls stored in the upper tray storage section are guided to the gaming ball launching device, and the gaming balls that are surplus in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the reels have stopped rotating corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary to deal with fraudulent activity against gaming machines, and there is still room for improvement in this regard.

<Characteristics Group S>
Feature S1. A setting means (a function for executing a setting value update process in the master CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
A situation generating means for generating a setting possible situation in which the setting means can set the setting value to be used (in the 22nd embodiment, a function for executing the processes of steps S5003 to S5006 and steps S5401 to S5408 in the main CPU 63; in another embodiment, a function for executing the processes of steps S5503 to S5507 in the main CPU 63; in the 23rd embodiment, a function for executing the processes of steps S5703 to S5705 and step S5715 in the main CPU 63; in the 24th embodiment, a function for executing the processes of steps S5801 to S5804 in the main CPU 63; and in the 25th embodiment, a function for executing the processes of steps S5901 to S5904 in the main CPU 63);
A setting value grasping means for grasping whether the setting value before the setting possible state is the same as the setting value set by the setting means (in the 22nd embodiment, a function for executing the processing of steps S5017 and steps S5111 to S5112 in the main CPU 63, and in another embodiment, a function for executing the processing of steps S5611 to S5612 in the main CPU 63);
A gaming machine comprising:

According to feature S1, the setting value to be used is set from among multiple setting values corresponding to the player's degree of advantage, so the player will expect the more advantageous setting value to be used. In this case, it is understood whether the setting value before the setting possible situation is the same as the setting value set in the setting possible situation. This makes it possible to execute processing corresponding to whether the setting values are the same across the setting possible situation. Therefore, when the setting value to be used is set, it is possible to create a favorable situation for the setting result, and it becomes possible to perform the setting value setting work in an optimal manner.

Feature S2. The gaming machine described in feature S1 is characterized by having a simultaneous processing means (a function for executing the processing of step S5113 in the main CPU 63 in the 22nd embodiment, and a function for executing the processing of step S5613 in the main CPU 63 in another embodiment) that executes a corresponding simultaneous processing based on the fact that the setting value grasping means has grasped that the setting value before the setting possible state is reached is the same as the setting value set by the setting means.

According to feature S2, when the setting values are the same across the settable situation, the same-time processing is executed, making it possible to create a situation that is favorable for the setting values being the same.

Feature S3. The gaming machine according to feature S2, wherein the simultaneous processing means executes processing for issuing a notification corresponding to the fact that the setting value has not been changed, as the simultaneous processing.

Feature S3 makes it possible to notify the manager of the gaming hall that the setting value is the same across setting possible situations.

Feature S4. A gaming machine according to any one of features S1 to S3, characterized in that it is provided with a non-identical time means (a function for executing the process of step S5114 in the main CPU 63 in the 22nd embodiment, or a function for executing the process of step S5614 in the main CPU 63 in another embodiment) that executes a corresponding non-identical time process based on the fact that the setting value grasping means has grasped that the setting value before the setting possible situation occurs is different from the setting value set by the setting means.

According to feature S4, if the setting value is not the same across the settable state, non-identical processing is executed, making it possible to create a favorable situation in response to the change in the setting value.

Feature S5. The gaming machine according to feature S4, wherein the non-identical time means executes a process for issuing a notification corresponding to a change in the setting value as the non-identical time process.

Feature S5 makes it possible to notify the manager of the amusement hall or other person that the setting value has been changed between setting possible situations.

Feature S6. The gaming machine according to any one of Features S1 to S5, characterized in that the situation generating means brings about the settable situation based on the occurrence of a need to erase information from the storage means that stores the setting value after the supply of operating power to the control means having the setting means has started.

According to feature S6, when it becomes necessary to erase information from the storage means that stores the setting value, the setting state becomes possible, so that it is possible to prevent gameplay from continuing even though the setting value information has been erased. In this case, the configuration of feature S1 described above is provided, and it is possible to grasp whether the setting value before the setting state becomes possible and the setting value set in the setting state are the same. This makes it possible to execute processing that corresponds to whether the setting values are the same across the setting state.

Feature S7. A gaming machine according to feature S6, characterized in that it is provided with a means for issuing a notification that the setting value has not been changed based on the setting value grasping means grasping that the setting value before the setting possible state is reached is the same as the setting value set by the setting means (a function for executing the process of step S5113 in the main CPU 63 in the 22nd embodiment, and a function for executing the process of step S5613 in the main CPU 63 in another embodiment).

According to feature S7, even if the setting becomes possible due to the information in the storage means being erased, if the setting value is the same between the setting possible situation, a notification is given that the setting value has not been changed. This makes it possible to notify the player that the setting value has not been changed even if the setting becomes possible during play, and allows the player to continue playing with peace of mind even if the setting becomes possible during play.

Feature S8. The situation generating means is
A first status generating means for causing the setting possible status to occur based on the start of the supply of operating power to the control means having the setting means (in the 22nd embodiment, a function for executing the processing of steps S5003 to S5006 in the main CPU 63, in another embodiment, a function for executing the processing of steps S5503 to S5507 in the main CPU 63, and in the 23rd embodiment, a function for executing the processing of steps S5703 to S5705 and step S5715 in the main CPU 63);
A second situation generating means for causing the setting possible situation to occur based on the occurrence of a need to erase information from the storage means for storing the setting value after the supply of operating power to the control means has started (a function for executing the processing of steps S5401 to S5408 in the main CPU 63 in the 22nd embodiment, a function for executing the processing of steps S5801 to S5804 in the main CPU 63 in the 24th embodiment, and a function for executing the processing of steps S5901 to S5904 in the main CPU 63 in the 25th embodiment);
Equipped with
A gaming machine described in any one of features S1 to S7, characterized in that the setting value grasping means grasps whether the setting value before the settable situation occurs is the same as the setting value set by the setting means, regardless of whether the settable situation is caused by the first situation generating means or the second situation generating means.

According to feature S8, when it becomes necessary to erase the information of the storage means that stores the set value, the setting status becomes available, so that it is possible to prevent gameplay from continuing despite the setting value information being erased. In this case, by using the same processing as when the setting status becomes available based on the start of the supply of operating power to the control means, when the setting status becomes available as a result of the information of the storage means being erased, it is possible to execute processing corresponding to whether the setting value is the same across the setting status.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features S1 to S8. This allows for a synergistic effect to be achieved through the combined configuration.

The invention relating to the above group of features S can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine that stores gaming balls given to a player, and the gaming balls stored in the tray storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out from, for example, a payout device to the tray storage section. In addition, a configuration in which an upper tray storage section and a lower tray storage section are provided as the tray storage section is also known for a pachinko machine, and in this case, the gaming balls stored in the upper tray storage section are guided to the gaming ball launching device, and the gaming balls that are surplus in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the reels have stopped rotating corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, when a set value that determines the advantageous degree of the gaming machine is set, it is necessary to create an optimal situation for that, and there is still room for improvement in this regard.

<Feature T group>
Feature T1. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes;
The control means includes:
A first predetermined processing execution means for executing a first predetermined processing among the various processing (a function for executing processing other than the management execution processing in the main CPU 63 in the fifteenth to twenty-fifth embodiments);
A second predetermined processing execution means (a function of executing a management execution process in the main CPU 63 in the fifteenth to twenty-fifth embodiments) that executes a second predetermined processing among the various processing;
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
A second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
a first monitoring execution means for monitoring whether the first predetermined storage area is normal or not (in the 22nd embodiment, a function for executing the processing of steps S5401 to S5404 in the main CPU 63; in the 24th embodiment, a function for executing the processing of steps S5801 to S5804 in the main CPU 63; in the 25th embodiment, a function for executing the processing of steps S5901 to S5904 in the main CPU 63; and in the 32nd embodiment, a function for executing the processing of steps S7701 to S7703 in the main CPU 63);
a second monitoring execution means for monitoring whether the second predetermined storage area is normal or not (in the 22nd embodiment, a function for executing the processes of steps S5405 to S5408 in the main CPU 63; in the 24th embodiment, a function for executing the processes of steps S5809, S5810, S5812, and S5813 in the main CPU 63; in the 25th embodiment, a function for executing the processes of steps S6101, S6102, S6105, and S6106 in the main CPU 63; and in the 32nd embodiment, a function for executing the processes of steps S7706 to S7708 in the main CPU 63);
A gaming machine comprising:

According to feature T1, a first predetermined storage area and a second predetermined storage area are provided, the first predetermined storage area is treated as a storage area dedicated to the first predetermined process, and the second predetermined storage area is treated as a storage area dedicated to the second predetermined process. This makes it possible to clearly differentiate the storage destination of information in the predetermined storage means between the first predetermined process and the second predetermined process. This makes it possible to prevent information used in one of the first and second predetermined processes from being erased when the other process is executed. In addition, by monitoring whether the first predetermined storage area is normal and monitoring whether the second predetermined storage area is normal, it becomes possible to identify whether the situation is such that each of the first and second predetermined processes can be executed normally.

Feature T2. The gaming machine described in Feature T1, characterized in that the monitoring by the first monitoring execution means and the monitoring by the second monitoring execution means are executed by either the first predetermined process or the second predetermined process.

According to feature T2, monitoring of whether the first specified storage area is normal and monitoring of whether the second specified storage area is normal are executed in one of the first specified process and the second specified process. This makes it possible to simplify the processing configuration compared to a configuration in which monitoring of each storage area is executed in a distributed manner between the first specified process and the second specified process.

Feature T3. A gaming machine according to feature T1 or T2, characterized in that the monitoring by the first monitoring execution means and the monitoring by the second monitoring execution means are performed by the first predetermined process.

According to feature T3, it is possible to consolidate and execute the monitoring of whether the first specified storage area is normal and the monitoring of whether the second specified storage area is normal in the first specified process.

Feature T4. A gaming machine according to any one of Features T1 to T3, characterized in that it is provided with a predetermined erasing means (a function for executing the process of step S5410 in the main CPU 63 in the 22nd embodiment, a function for executing the process of steps S5806, S5811, and S5814 in the main CPU 63 in the 24th embodiment, and a function for executing the process of steps S5906, S6103, and S6107 in the main CPU 63) that erases information from the first predetermined storage area based on the first monitoring execution means identifying that the first predetermined storage area is abnormal.

According to feature T4, if the first specified storage area is abnormal, the information in the first specified storage area is erased, thereby making it possible to prevent the first specified process from being executed while the first specified storage area remains in an abnormal state.

Feature T5. The gaming machine described in Feature T4, wherein the predetermined erasing means erases information from the first predetermined storage area and erases information from the second predetermined storage area based on the first monitoring execution means identifying that the first predetermined storage area is abnormal.

According to feature T5, if the first specified storage area is abnormal, not only the first specified storage area but also the second specified storage area is erased. This makes it possible to erase the information in the second specified storage area regardless of the monitoring results by the second monitoring execution means if there is a possibility that an abnormality has occurred in the second specified storage area.

Feature T6. The gaming machine described in Feature T4 or T5, wherein the predetermined erasing means erases information from the second predetermined storage area based on the second monitoring execution means identifying that the second predetermined storage area is abnormal.

According to feature T6, if the first specified storage area is abnormal, the information in the first specified storage area is erased, thereby making it possible to prevent the first specified process from being executed while the first specified storage area remains in an abnormal state.

Feature T7. The gaming machine described in Feature T6, characterized in that the predetermined erasing means erases the information in the second predetermined storage area and erases the information in the first predetermined storage area based on the second monitoring execution means identifying that the second predetermined storage area is abnormal.

According to feature T7, if the second specified storage area is abnormal, not only the second specified storage area but also the first specified storage area is erased. This makes it possible to erase the information in the first specified storage area regardless of the monitoring results by the first monitoring execution means when there is a possibility that an abnormality has occurred in the first specified storage area.

Feature T8. A gaming machine according to any one of Features T4 to T7, characterized in that the process for erasing information by the predetermined erasing means is executed by either the first predetermined process or the second predetermined process.

According to feature T8, the process of erasing information from each specified storage area based on the identification of an abnormality is executed in one of the first and second specified processes in a centralized manner. This makes it possible to simplify the processing configuration compared to a configuration in which the erasure of information from each storage area is executed in a distributed manner between the first and second specified processes.

Feature T9. A gaming machine according to any one of Features T4 to T7, characterized in that the process for erasing information by the predetermined erasing means is executed in the first predetermined process.

According to feature T9, it is possible to centralize and execute the process of erasing information from each specified storage area based on the identification of an abnormality in the first specified process.

Feature T10. The first predetermined process includes a process for controlling the progress of a game;
A gaming machine according to any one of features T1 to T9, wherein the second predetermined process includes a process for managing a gaming history.

According to feature T10, a process for controlling the progress of a game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, so that it is possible to prevent information used in the process for managing the game history from being rewritten when the process for controlling the progress of a game is executed.

Feature T11. The gaming machine described in Feature T10, characterized in that the second predetermined memory area includes a history memory area (normal counter area 231, open/close execution mode counter area 232, high frequency support mode counter area 233) in which history information of a game corresponding to a predetermined event that occurs as a result of the game being played is stored.

According to feature T11, when a predetermined event occurs, the corresponding history information is stored in the history storage area. This allows the gaming machine to store and hold information for managing the number of times or frequency of occurrence of the predetermined event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of the predetermined event. Furthermore, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by executing a process for controlling the progress of the game as the first predetermined process, and executing a process for managing the game history as the second predetermined process, it becomes possible to prevent the information stored in the history storage area from being rewritten when the process for controlling the progress of the game is executed.

Feature T12. The gaming machine described in Feature T11, characterized in that the second predetermined process execution means includes information derivation means (a function for executing the process of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to the game results during a predetermined period.

According to feature T12, by deriving behavior information corresponding to the results of play during a specified period of time using the history information stored in the history storage area, it becomes possible to grasp the results of management of the play history, such as the frequency of occurrence of a specified event.

Feature T13. The gaming machine described in feature T12, characterized in that the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature T13, when behavior information corresponding to the results of a game during a specified period is derived using history information, the behavior information is stored in a behavior information storage area. This makes it possible to grasp the results of managing the game history at any time. In addition, by executing a process for controlling the progress of a game as the first specified process and a process for managing the game history as the second specified process, it becomes possible to prevent the information stored in the behavior information storage area from being overwritten when the process for controlling the progress of a game is executed.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features T1 to T13. This allows for a synergistic effect to be achieved through the combined configuration.

<Characteristic U group>
Feature U1. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes;
The control means includes:
A first predetermined processing execution means for executing a first predetermined processing among the various processing (a function for executing processing other than the management execution processing in the main CPU 63 in the fifteenth to thirty-fourth embodiments);
A second predetermined processing execution means (a function of executing a management execution process in the main CPU 63 in the fifteenth to thirty-fourth embodiments) that executes a second predetermined processing among the various processing;
A state setting means for setting the state of a flag register provided in the internal storage means to a specific state when the state of executing the first predetermined process changes to a state of executing the second predetermined process or when the state of executing the second predetermined process changes to a state of executing the second predetermined process (in the 26th embodiment, a function for executing the processes of steps S6202 to S6204 and S6211 in the main CPU 63; in the 27th embodiment, a function for executing the processes of steps S6302 to S6307 and S6312 in the main CPU 63);
A gaming machine comprising:

According to feature U1, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, the state of the flag register of the internal storage means is set to a specific state. This makes it possible to start the second predetermined process in a situation in which the state of the flag register is a predetermined specific state. This makes it possible to perform various types of control in an optimal manner.

Feature U2. The gaming machine described in Feature U1, characterized in that the specific state is a state when the supply of operating power to the control means is started.

According to feature U2, the flag register is set to a specific state when the supply of operating power to the control means is started, so the processing configuration for setting the specific state can be simplified.

Feature U3. The gaming machine described in feature U1 or U2, wherein the specific state is a state in which the flag register is cleared to "0."

According to feature U3, the flag register is set to a specific state, cleared to "0," making it possible to simplify the processing configuration for setting the specific state.

Feature U4. A gaming machine according to any one of features U1 to U3, characterized in that it is provided with a means for causing the state of the flag register to become the specific state when or after the second predetermined process is completed (a function for executing the processes of steps S6213 to S6218 in the main CPU 63 in the 26th embodiment, and a function for executing the processes of steps S6314 to S6322 in the main CPU 63 in the 27th embodiment).

According to feature U4, the state of the flag register is set to a specific state not only when the state changes from the state in which the first predetermined process is being executed to the state in which the second predetermined process is being executed or when the state changes to the state in which the second predetermined process is being executed, but also when the second predetermined process is terminated or has been terminated. This makes it possible to resume the first predetermined process in a state in which the state of the flag register is in a predetermined specific state. It is also possible to set the state of the flag register to a specific state before and after the second predetermined process. This makes it possible to prevent the state of the flag register due to one of the first and second predetermined processes from affecting the other process.

Feature U5. The control means includes a predetermined storage means (main RAM 65) for temporarily storing information when the control means executes processing;
The state setting means includes:
A means for causing the state of a predetermined storage area in the predetermined storage means to become the specific state (in the 26th embodiment, a function for executing the processes of steps S6202 to S6204 in the main CPU 63, and in the 27th embodiment, a function for executing the processes of steps S6302 to S6307 in the main CPU 63);
A means for causing the information stored in the predetermined storage area to be stored in the flag register, thereby causing the state of the flag register to become the specific state (in the 26th embodiment, a function for executing the process of step S6211 in the main CPU 63, and in the 27th embodiment, a function for executing the process of step S6312 in the main CPU 63);
A gaming machine described in any one of features U1 to U4, characterized in that it is equipped with:

According to feature U5, even if the configuration does not allow the state of the flag register to be directly set to a specific state as a command from the control means, it is possible to set the state of the flag register to a specific state by writing information to a specified storage means and reading out that information.

Feature U6. The predetermined storage means is
a stack area (a stack area 222 for specific control) into which the control means can write information in response to a push command and into which the control means can read information in response to a pop command;
a work area (a work area 221 for specific control) in which the control means can write and read information in response to a load command;
Equipped with
A gaming machine described in feature U5, characterized in that the specified memory area is provided in the stack area.

According to feature U6, even if the configuration does not allow the information stored in the work area to be directly written to the flag register, it is possible to set the state of the flag register to a specific state by writing information to the stack area and reading that information.

Feature U7. When the situation changes from the situation where the first predetermined process is being executed to the situation where the second predetermined process is being executed or when the situation where the second predetermined process is being executed is reached, a means for causing the state of a predetermined register provided in the internal storage means to become a predetermined state (in the 26th embodiment, a function for executing the processes of steps S6205 to S6210 in the main CPU 63, and in the 27th embodiment, a function for executing the processes of steps S6308 to S6311 in the main CPU 63),
A gaming machine described in any one of features U1 to U6, characterized in that the state setting means sets the state of the flag register to the specific state after the state of the specified register is set to the specified state.

The state of the flag register can change each time various processes are executed by the control means. In this case, according to feature U7, the state of the flag register is set to a specific state after the state of the specified register is set to a specified state, so that it is possible to make the flag register be in a specific state immediately before the second specified process is started.

Feature U8. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes;
The control means is a gaming machine characterized in that it is equipped with a means for causing the state of the flag register to become a specific state (in the 26th embodiment, a function for executing the processing of steps S6202 to S6204 and step S6211 in the main CPU 63, and in the 27th embodiment, a function for executing the processing of steps S6302 to S6307 and step S6312 in the main CPU 63).

Feature U8 makes it possible to set the state of the flag register to a specific state as needed.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features U1 to U8. This allows for a synergistic effect to be achieved through the combined configuration.

<Feature V Group>
Feature V1. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes;
The control means includes:
A first predetermined processing execution means for executing a first predetermined processing among the various processing (a function for executing processing other than the management execution processing in the main CPU 63 in the fifteenth to thirty-fourth embodiments);
A second predetermined processing execution means (a function of executing a management execution process in the main CPU 63 in the fifteenth to thirty-fourth embodiments) that executes a second predetermined processing among the various processing;
a save execution means for saving information of a flag register provided in the internal storage means to a predetermined storage means (main RAM 65) when the state in which the first predetermined process is being executed changes to the state in which the second predetermined process is being executed or when the state in which the second predetermined process is being executed is reached (a function for executing the process of step S3802 in the main CPU 63 in the fifteenth embodiment, a function for executing the process of step S4402 in the main CPU 63 in the sixteenth embodiment, a function for executing the process of step S4802 in the main CPU 63 in the twentieth embodiment, a function for executing the process of steps S6402 to S6405 in the main CPU 63 in the twenty-eighth embodiment, and a function for executing the process of steps S6502 to S6509 in the main CPU 63 in the twenty-ninth embodiment);
a restoration execution means for restoring the information of the flag register saved in the predetermined storage means to the flag register when or after the second predetermined process is completed (a function for executing the process of step S3804 in the main CPU 63 in the fifteenth embodiment, a function for executing the process of step S4404 in the main CPU 63 in the sixteenth embodiment, a function for executing the process of step S4810 in the main CPU 63 in the twenty-eighth embodiment, a function for executing the processes of steps S6407 to S6415 in the main CPU 63 in the twenty-ninth embodiment, and a function for executing the processes of steps S6511 to S6518 in the main CPU 63 in the twenty-ninth embodiment);
A gaming machine comprising:

According to feature V1, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, the information in the flag register is saved to a predetermined storage means. This makes it possible to prevent the information stored in the flag register from being overwritten when the second predetermined process is executed. Furthermore, when or after the second predetermined process is terminated, the information saved in the predetermined storage means is restored to the flag register. This makes it possible to execute a process different from the second predetermined process from the state of the flag register before the execution of the second predetermined process when the second predetermined process is terminated. As a result, various controls can be performed in an optimal manner.

Feature V2. The predetermined storage means is
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
A second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
The gaming machine described in feature V1, wherein the save execution means saves the information of the flag register to the first specified memory area.

According to feature V2, by providing the predetermined storage means with a first predetermined storage area and a second predetermined storage area, it is possible to clearly differentiate the storage destination of information in the predetermined storage means between the first predetermined process and the second predetermined process. This makes it possible to prevent information used in one of the first and second predetermined processes from being erased when the other process is executed. In this case, when the situation changes from the execution of the first predetermined process to the execution of the second predetermined process or when the situation changes to the execution of the second predetermined process, the information in the flag register is saved to the first predetermined storage area. This makes it possible to save the information in the flag register immediately before the start of the second predetermined process, and to save the information without using the second predetermined storage area.

Feature V3. The first predetermined storage area is capable of storing and reading information when the first predetermined process is executed, and is capable of reading information but is not capable of storing information when the second predetermined process is executed;
A gaming machine as described in feature V2, characterized in that the second specified memory area is capable of storing information and reading information when the second specified process is executed, and is capable of reading information but not storing information when the first specified process is executed.

Feature V3 makes it possible to treat the first specified memory area as a memory area dedicated to the first specified process, and to treat the second specified memory area as a memory area dedicated to the second specified process.

Feature V4. The predetermined storage means is
a stack area (a stack area 222 for specific control) into which information can be written by a push command and into which information can be read by a pop command;
A work area (a work area 221 for specific control) in which information can be written and read by a load command;
Equipped with
A gaming machine described in any one of features V1 to V3, characterized in that the save execution means saves the information of the flag register to one of the stack area and the work area.

According to feature V4, when the situation changes from the execution of the first predetermined process to the execution of the second predetermined process, or when the situation changes to the execution of the second predetermined process, the information in the flag register is saved to one of the stack area and the work area in the second predetermined memory area. This makes it possible to consolidate the destinations for saving information, and to simplify the processing configuration for saving and the processing configuration for restoring.

Feature V5. The gaming machine described in Feature V4, wherein the save execution means saves the information in the flag register to the work area.

According to feature V5, the destination for saving the flag register information is the work area, so that the information can be saved without making cumulative changes to the stack pointer.

Feature V6. The save execution means is
A means for storing information of the flag register in a predetermined register provided in the internal storage means (a function for executing the processes of steps S6402 and S6403 in the main CPU 63 in the 28th embodiment, and a function for executing the processes of steps S6502 to S6505 in the main CPU 63 in the 29th embodiment);
A means for storing the information of the flag register stored in the predetermined register in the predetermined storage means (a function for executing the process of step S6404 in the main CPU 63 in the 28th embodiment, and a function for executing the process of step S6506 in the main CPU 63 in the 29th embodiment);
A gaming machine described in any one of features V1 to V5, characterized in that it is equipped with:

According to feature V6, even if the configuration does not allow the information in the flag register to be directly saved to the specified storage means as an instruction from the control means, it is possible to save the information in the flag register to the specified storage means by writing information to the specified register and writing the information stored in the specified register to the specified storage means.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features V1 to V6. This allows for a synergistic effect to be achieved through the combined configuration.

<Feature W group>
Feature W1. Equipped with a control means (main CPU 63) that executes various processes,
The control means includes:
A first predetermined processing execution means for executing a first predetermined processing among the various processing (a function for executing processing other than the management execution processing in the main CPU 63 in the fifteenth to thirty-fourth embodiments);
A second predetermined processing execution means (a function of executing a management execution process in the main CPU 63 in the fifteenth to thirty-fourth embodiments) that executes a second predetermined processing among the various processing;
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
A second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
An abnormal event monitoring means (program monitoring unit 252) for monitoring whether or not an abnormal event has occurred;
An erasure status generating means (a reset signal output unit 251) that can generate a status in which an information erasure process is executed on at least the first predetermined storage area based on the abnormal event being identified by the abnormal event monitoring means;
A gaming machine comprising:

According to feature W1, a first predetermined storage area and a second predetermined storage area are provided, and the first predetermined storage area is treated as a storage area dedicated to the first predetermined process, and the second predetermined storage area is treated as a storage area dedicated to the second predetermined process. This makes it possible to clearly differentiate the storage destination of information in the predetermined storage means between the first predetermined process and the second predetermined process. Therefore, it is possible to prevent information used in one of the first and second predetermined processes from being erased when the other process is executed. In addition, based on the identification that an abnormal event has occurred, an information erasure process is executed on at least the first predetermined storage area. This makes it possible to prevent the first predetermined process from being executed in a state in which the information in the first predetermined storage area is retained as is, despite the occurrence of an abnormal event.

Feature W2. The control means is
A means for executing a process for storing power failure response information when the supply of operating power to the control means is stopped (in the 30th embodiment, a function for executing the processes of steps S6709 and S6710 in the main CPU 63, and in the 32nd embodiment, a function for executing the processes of steps S7609 to S7611 in the main CPU 63);
When the supply of operating power to the control means is started and the processing at the start of supply is executed in a situation where the power failure response information is not stored, a means for erasing the information is executed at least for the first predetermined storage area (in the 30th embodiment, a function for executing the processing of step S6607 in the main CPU 63; in the 31st embodiment, a function for executing a clearing process in the event of an abnormality in the main CPU 63; in the 32nd embodiment, a function for executing the processing of steps S7704, S7705, S7808, and S7810 in the main CPU 63);
Equipped with
The gaming machine described in feature W1 is characterized in that the erasure status generation means causes the control means to execute processing at the start of supply in a situation where the power outage response information is not stored based on the abnormal event monitoring means identifying the occurrence of the abnormal event.

According to feature W2, when the supply of operating power to the control means is started and the supply start processing is executed in a situation where the power outage response information is not stored, the information erasure processing is executed at least for the first predetermined storage area, so that when the supply of operating power to the control means is started in a situation where the power outage processing is not properly performed, the first predetermined processing is not executed with the information in the first predetermined storage area retained as it is. In this case, based on the fact that an abnormal event has occurred, the supply start processing is executed by the control means in a situation where the power outage response information is not stored. This makes it possible to execute the information erasure processing in response to the occurrence of an abnormal event by utilizing the configuration that executes the information erasure processing when the supply start processing is executed by the control means in a situation where the power outage response information is not stored.

Feature W3: The control means executes various processes when a reset signal is received, and starts the process at the start of supply based on a change from a state in which the reset signal is not received to a state in which the reset signal is received while operating power is being supplied,
The gaming machine described in feature W2 is characterized in that the erasure status generating means, based on the abnormal event monitoring means identifying the occurrence of an abnormal event, causes the control means to create a status in which the reset signal is not received, and then creates a status in which the control means receives the reset signal.

Feature W3 makes it possible to achieve the excellent effects described above by switching the reception state of the reset signal.

Feature W4. The control means is configured to temporarily store information in an internal storage means (register and program counter of the main CPU 63) when executing a process, and is configured to temporarily save the information stored in the internal storage means to the first predetermined storage area;
the abnormal event monitoring means monitors whether or not an abnormality occurs in the information stored in the internal storage means as the abnormal event;
A gaming machine described in any one of features W1 to W3, characterized in that the erasure status generation means generates a situation in which the information erasure process is executed on at least both the first specified memory area and the internal memory means.

According to feature W4, the information stored in the internal storage means can be temporarily evacuated to the first predetermined storage area, so that if an abnormality occurs with the information stored in the internal storage means, there is a possibility that an abnormality also occurs with the information stored in the first predetermined storage area. In this case, if an abnormality occurs with the information stored in the internal storage means, an information erasure process is executed not only for the internal storage means but also for the first predetermined storage area. This makes it possible to prevent the first predetermined process from being executed in the same state, even if an abnormality has occurred with the information stored in the first predetermined storage area.

Feature W5. The gaming machine described in any one of Features W1 to W4, characterized in that the erasure status generating means prevents the information erasure process from being executed on the second predetermined storage area even if the abnormal event monitoring means identifies that the abnormal event has occurred.

Feature W5 makes it possible to store and retain information in the second specified storage area even if an abnormal event occurs.

Feature W6. The gaming machine described in any one of Features W1 to W4, characterized in that the erasure situation generating means generates a situation in which the information erasure process is executed for both the first specified storage area and the second specified storage area based on the abnormal event monitoring means identifying the occurrence of the abnormal event.

According to feature W6, when it is determined that an abnormal event has occurred, an information erasure process is executed for both the first and second specified storage areas. This makes it possible to prevent the first specified process from being executed in a state in which the information in the first specified storage area is retained as is despite the occurrence of an abnormal event, and also makes it possible to prevent the second specified process from being executed in a state in which the information in the second specified storage area is retained as is despite the occurrence of an abnormal event.

Feature W7. A gaming machine according to Feature W6, characterized in that the process of erasing the information from the first predetermined memory area is executed by the first predetermined process, and the process of erasing the information from the second predetermined memory area is executed by the second predetermined process.

According to feature W7, it is possible to treat the first specified storage area as a storage area dedicated to the first specified process and the second specified storage area as a storage area dedicated to the second specified process, even with regard to the information erasure process.

Feature W8. The first predetermined process includes a process for controlling the progress of a game;
A gaming machine described in any one of features W1 to W7, characterized in that the second specified process includes a process for managing a gaming history.

According to feature W8, a process for controlling the progress of a game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, so that it is possible to prevent information used in the process for managing the game history from being rewritten when the process for controlling the progress of a game is executed.

Feature W9. The gaming machine described in Feature W8, characterized in that the second predetermined memory area includes a history memory area (normal counter area 231, open/close execution mode counter area 232, high frequency support mode counter area 233) in which history information of a game corresponding to a predetermined event that occurs as a result of the game being played is stored.

According to feature W9, when a specified event occurs, the corresponding history information is stored in the history storage area. This allows the gaming machine to store and hold information for managing the number of times or frequency of occurrence of the specified event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of the specified event. Furthermore, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by executing a process for controlling the progress of the game as the first specified process, and executing a process for managing the game history as the second specified process, it becomes possible to prevent the information stored in the history storage area from being rewritten when the process for controlling the progress of the game is executed.

Feature W10. The gaming machine described in Feature W9, characterized in that the second predetermined process execution means includes information derivation means (a function for executing the process of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to the game results during a predetermined period.

According to feature W10, by deriving behavior information corresponding to the results of play during a specified period of time using the history information stored in the history storage area, it becomes possible to grasp the results of management of the play history, such as the frequency of occurrence of a specified event.

Feature W11. The gaming machine described in Feature W10, characterized in that the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature W11, when behavior information corresponding to the results of a game during a specified period is derived using history information, the behavior information is stored in a behavior information storage area. This makes it possible to grasp the results of game history management at any time. In addition, by executing a process for controlling the progress of a game as the first specified process and a process for managing the game history as the second specified process, it becomes possible to prevent the information stored in the behavior information storage area from being overwritten when the process for controlling the progress of a game is executed.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features W1 to W11. This allows for a synergistic effect to be achieved through the combined configuration.

<Characteristics Group X>
Feature X1. Equipped with a control means (main CPU 63) that executes various processes,
The control means includes:
A first predetermined processing execution means for executing a first predetermined processing among the various processing (a function for executing processing other than the management execution processing in the main CPU 63 in the fifteenth to thirty-fourth embodiments);
A second predetermined processing execution means (a function of executing a management execution process in the main CPU 63 in the fifteenth to thirty-fourth embodiments) that executes a second predetermined processing among the various processing;
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
A second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
The gaming machine is characterized in that the second specified processing execution means is provided with an erasure execution means for executing an information erasure processing on the second specified memory area as the second specified processing based on the occurrence of an erasure trigger (in the 25th embodiment, a function for executing the processing of steps S6103 and S6107 in the main CPU 63; in the 30th embodiment, a function for executing the processing of step S7204 in the main CPU 63; in the 31st embodiment, a function for executing the processing of step S7508 in the main CPU 63; and in the 32nd embodiment, a function for executing the processing of steps S7808 and S7810 in the main CPU 63).

According to feature X1, a first predetermined storage area and a second predetermined storage area are provided, the first predetermined storage area is treated as a storage area dedicated to the first predetermined process, and the second predetermined storage area is treated as a storage area dedicated to the second predetermined process. This makes it possible to clearly differentiate the storage destination of information in the predetermined storage means between the first predetermined process and the second predetermined process. Therefore, it is possible to prevent information used in the first predetermined process or the second predetermined process from being erased when one of the other processes is executed.

In addition, when an erasure trigger occurs, an information erasure process is executed on the second specified storage area, so it is possible to prevent the second specified process from being executed in a state where the information in the second specified storage area is retained as is, even if some abnormality has occurred in the second specified storage area. In addition, because the information erasure process is executed by the second specified process, it is possible to prevent the first specified process from being involved in updating the information in the second specified storage area.

Feature X2. The gaming machine described in Feature X1, wherein the erasure execution means executes the erasure process of the information on the second predetermined memory area while preventing information that is not to be erased (management monitoring flags, return address information, and information on various registers) from being erased.

According to feature X2, the process of erasing information from the second specified storage area is performed while preventing information from the second specified storage area that is not to be erased from the second specified storage area from being erased. This makes it possible to execute the process of erasing information from the second specified storage area while preventing necessary information from being erased as well.

Feature X3. The second predetermined processing execution means is a storage execution means for storing return correspondence information (return address information, various register information) required when returning to a situation in which the first predetermined processing is executed when the situation in which the first predetermined processing is executed changes to a situation in which the second predetermined processing is executed or when the situation in which the second predetermined processing is executed is reached in the second predetermined storage area (in the 30th embodiment, a function for executing the processing of steps S7102 to S7107 in the main CPU 63; in the 31st embodiment, a function for executing the processing of steps S7502 to S7507 in the main CPU 63; in the 32nd embodiment, a function for executing the processing of steps S7802 to S7807 in the main CPU 63).
The gaming machine described in feature X2, wherein the erasure execution means executes the information erasure process on the second specified memory area while preventing the return corresponding information from being erased as the non-erasure target information.

Feature X3 makes it possible to execute the information erasure process for the second specified storage area while preventing the erasure of the return correspondence information required when returning from a situation in which the second specified process is being executed to a situation in which the first specified process is being executed.

Feature X4. The gaming machine described in Feature X3, wherein the storage and execution means stores, as the return correspondence information, information on the return address of the program when the second predetermined process is ended and the first predetermined process is returned to in the second predetermined storage area.

According to feature X4, an information erasure process is performed on the second specified storage area while preventing the information of the return address of the program from being erased when returning to the first specified processing, so that even if an information erasure process is performed on the second specified storage area, it is possible to return to the specified program in the first specified processing when the second specified processing is completed.

Feature X5. The control means is configured to temporarily store information in an internal storage means (register of the main CPU 63) when executing processing,
The gaming machine according to feature X3 or X4, wherein the storage execution means stores the information stored in the internal storage means as the return correspondence information in the second predetermined storage area.

According to feature X5, an information erasure process is performed on the second specified storage area while preventing the information in the internal storage means used in the first specified process from being erased. Therefore, even if an information erasure process is performed on the second specified storage area, when the second specified process is completed, it is possible to restore the information used in the first specified process to the internal storage means.

Feature X6. The gaming machine according to any one of Features X1 to X5, characterized in that the erasure execution means executes the information erasure process on the second specified storage area based on the occurrence of an abnormality in the second specified storage area as the occurrence of the erasure trigger.

According to feature X6, when an abnormality occurs in the second specified storage area, an information erasure process is executed on the second specified storage area, so that it is possible to prevent the second specified process from being executed while an abnormality remains in the second specified storage area.

Feature X7. The gaming machine described in Feature X6, characterized in that the second predetermined process execution means includes a means for monitoring whether the second predetermined memory area is normal as the second predetermined process (in the 30th embodiment, a function for executing the processes of steps S7201 to S7203 in the main CPU 63).

According to feature X7, not only the process of erasing information from the second specified storage area, but also the monitoring of whether the second specified storage area is normal or not is executed in the second specified processing without the intervention of the first specified processing, so that the monitoring of whether the second specified storage area is normal or not and the execution of the process of erasing information from the second specified storage area can be executed as a series of processes in the second specified processing.

Feature X8. The first predetermined process includes a process for controlling the progress of a game;
A gaming machine according to any one of features X1 to X7, wherein the second predetermined process includes a process for managing a gaming history.

According to feature X8, a process for controlling the progress of a game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, so that it is possible to prevent information used in the process for managing the game history from being rewritten when the process for controlling the progress of a game is executed.

Feature X9. The gaming machine described in Feature X8, characterized in that the second predetermined storage area includes a history storage area (normal counter area 231, open/close execution mode counter area 232, high frequency support mode counter area 233) in which history information of a game corresponding to a predetermined event that occurs as a result of the game being played is stored.

According to feature X9, when a specified event occurs, corresponding history information is stored in the history storage area. This allows the gaming machine to store and hold information for managing the number of times or frequency of occurrence of the specified event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of the specified event. Furthermore, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by executing a process for controlling the progress of the game as the first specified process, and executing a process for managing the game history as the second specified process, it becomes possible to prevent the information stored in the history storage area from being rewritten when the process for controlling the progress of the game is executed.

Feature X10. The gaming machine described in Feature X9, characterized in that the second predetermined process execution means includes information derivation means (a function for executing the process of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to the game results during a predetermined period.

According to feature X10, by deriving behavior information corresponding to the results of play during a specified period of time using the history information stored in the history storage area, it becomes possible to grasp the results of management of the play history, such as the frequency of occurrence of a specified event.

Feature X11. The gaming machine described in Feature X10, characterized in that the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature X11, when behavior information corresponding to the results of a game during a specified period is derived using history information, the behavior information is stored in a behavior information storage area. This makes it possible to grasp the results of game history management at any time. In addition, by executing a process for controlling the progress of a game as the first specified process and a process for managing the game history as the second specified process, it becomes possible to prevent the information stored in the behavior information storage area from being overwritten when the process for controlling the progress of a game is executed.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features X1 to X11. This allows for a synergistic effect to be achieved through the combined configuration.

<Characteristic Group Y>
Feature Y1. Equipped with a control means (main CPU 63) that executes various processes,
The control means includes:
A first predetermined processing execution means for executing a first predetermined processing among the various processing (a function for executing processing other than the management execution processing in the main CPU 63 in the fifteenth to thirty-fourth embodiments);
A second predetermined processing execution means (a function of executing a management execution process in the main CPU 63 in the fifteenth to thirty-fourth embodiments) that executes a second predetermined processing among the various processing;
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
A second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
a first calculation means for calculating first reference numerical information corresponding to the plurality of pieces of information stored in the first predetermined storage area (in the 30th embodiment, a function for executing the processing of steps S6604 and S6710 in the main CPU 63; in the 31st embodiment, a function for executing the processing of step S7304 in the main CPU 63; and in the 32nd embodiment, a function for executing the processing of steps S7610 and S7701 in the main CPU 63);
A gaming machine comprising:

According to feature Y1, a first predetermined storage area and a second predetermined storage area are provided, the first predetermined storage area is treated as a storage area dedicated to the first predetermined process, and the second predetermined storage area is treated as a storage area dedicated to the second predetermined process. This makes it possible to clearly differentiate the storage destination of information in the predetermined storage means between the first predetermined process and the second predetermined process. Therefore, it is possible to prevent information used in one of the first and second predetermined processes from being erased when the other process is executed. In this case, first reference numerical information corresponding to the multiple pieces of information stored in the first predetermined storage area is calculated. By using the first reference numerical information, it is possible to identify whether an information anomaly has occurred only in the first predetermined storage area.

Feature Y2. The gaming machine described in Feature Y1, characterized in that it is equipped with information erasing means (a function for executing the process of step S6607 in the main CPU 63 in the 30th embodiment, a function for executing the process of steps S7401 and S7402 in the main CPU 63 in the 31st embodiment, and a function for executing the process of steps S7704 and S7705 in the main CPU 63) that causes information erasing processing to be executed on the first predetermined memory area based on the identification of the occurrence of an abnormality with respect to the first reference numerical information calculated by the first calculation means.

According to feature Y2, when an abnormality is identified with respect to the first reference numerical information, an information erasure process is executed for the first specified storage area, so that it is possible to prevent the first specified process from being executed in a state where the information in the first specified storage area is retained as is, even if an information abnormality has occurred.

Feature Y3. The first calculation means is
A first power failure calculation means for calculating the first reference numerical information when the supply of operating power to the control means is stopped (in the 30th embodiment, a function for executing the processing of step S6710 in the main CPU 63, and in the 32nd embodiment, a function for executing the processing of step S7610 in the main CPU 63);
A first power-on time calculation means for calculating the first reference numerical information when the supply of operating power to the control means is started (in the 30th embodiment, a function for executing the process of step S6604 in the main CPU 63, in the 31st embodiment, a function for executing the process of step S7304 in the main CPU 63, and in the 32nd embodiment, a function for executing the process of step S7701 in the main CPU 63);
Equipped with
The gaming machine described in feature Y2, characterized in that the information erasing means executes the information erasing process on at least the first specified memory area based on the fact that the first reference numerical information calculated by the first power outage calculation means does not match the first reference numerical information calculated by the first power on calculation means.

According to feature Y3, it is possible to determine whether information in the first specified storage area is stored across a situation in which the supply of operating power is stopped by calculating the first reference numerical information. If information in the first specified storage area is not stored across a situation in which the supply of operating power is stopped, an information erasure process is performed on the first specified storage area, so that it is possible to prevent the first specified process from being performed in a state in which the information in the first specified storage area is still retained despite the occurrence of an information anomaly.

Feature Y4. The gaming machine described in feature Y2 or Y3, characterized in that the information erasing means does not execute the information erasing process for the second predetermined memory area even if it identifies the occurrence of an abnormality in the first reference numerical information calculated by the first calculation means.

According to feature Y4, when an abnormality is identified with respect to the first reference numerical information, an information erasure process is performed on the first specified storage area, but an information erasure process is not performed on the second specified storage area. This makes it possible to prevent the information in the second specified storage area from being erased in a situation where an information abnormality has occurred in the first specified storage area.

Feature Y5. A gaming machine according to any one of features Y1 to Y4, characterized in that the first reference numerical information is information that does not change depending on the information stored in the second predetermined memory area.

According to feature Y5, in a configuration in which a first specified storage area and a second specified storage area exist, it is possible to individually identify information anomalies related to the first specified storage area by using the first reference numerical information.

Feature Y6. A gaming machine according to any one of features Y1 to Y5, characterized in that it is provided with a second calculation means (a function for executing the processing of steps S7611 and S7706 in the main CPU 63) for calculating second reference numerical information corresponding to the plurality of pieces of information stored in the second predetermined memory area.

According to feature Y6, second reference numerical information corresponding to the multiple pieces of information stored in the second specified storage area is calculated. By using the second reference numerical information, it is possible to determine whether an information anomaly has occurred only in the second specified storage area.

Feature Y7. The gaming machine described in Feature Y6 is characterized in that it is provided with a means (a function for executing the processes of steps S7808 and S7810 in the main CPU 63) for causing an information erasure process to be executed on at least the second predetermined memory area based on the identification of the occurrence of an abnormality with respect to the second reference numerical information calculated by the second calculation means.

According to feature Y7, when an abnormality is identified with respect to the second reference numerical information, an information erasure process is performed on the second specified storage area, so that it is possible to prevent the second specified process from being performed in a state where the information in the second specified storage area is retained as is despite the occurrence of an information abnormality.

Feature Y8. The first predetermined process includes a process for controlling the progress of a game;
A gaming machine described in any one of features Y1 to Y7, characterized in that the second predetermined process includes a process for managing a gaming history.

According to feature Y8, a process for controlling the progress of a game is executed as a first predetermined process, and a process for managing a game history is executed as a second predetermined process, so that it is possible to prevent information used in the process for managing a game history from being rewritten when the process for controlling the progress of a game is executed.

Feature Y9. The gaming machine described in Feature Y8, characterized in that the second predetermined memory area includes a history memory area (normal counter area 231, open/close execution mode counter area 232, high frequency support mode counter area 233) in which history information of a game corresponding to a predetermined event that occurs as a result of the game being played is stored.

According to feature Y9, when a specified event occurs, the corresponding history information is stored in the history storage area. This allows the gaming machine to store and hold information for managing the number of times or frequency of occurrence of the specified event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of the specified event. Furthermore, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by executing a process for controlling the progress of the game as the first specified process, and executing a process for managing the game history as the second specified process, it becomes possible to prevent the information stored in the history storage area from being rewritten when the process for controlling the progress of the game is executed.

Feature Y10. The gaming machine described in Feature Y9, characterized in that the second predetermined process execution means includes information derivation means (a function for executing the process of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to the game results during a predetermined period.

According to feature Y10, by deriving behavior information corresponding to the results of play during a specified period of time using the history information stored in the history storage area, it becomes possible to grasp the results of management of the play history, such as the frequency of occurrence of a specified event.

Feature Y11. The gaming machine described in Feature Y10, characterized in that the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature Y11, when behavior information corresponding to the results of a game during a specified period is derived using history information, the behavior information is stored in a behavior information storage area. This makes it possible to grasp the results of managing the game history at any time. In addition, by executing a process for controlling the progress of a game as the first specified process and a process for managing the game history as the second specified process, it becomes possible to prevent the information stored in the behavior information storage area from being rewritten when the process for controlling the progress of a game is executed.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features Y1 to Y11. This allows for a synergistic effect to be achieved through the combined configuration.

The invention relating to the above feature group T, feature group U, feature group V, feature group W, feature group X, and feature group Y can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine that stores gaming balls given to a player, and the gaming balls stored in the tray storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entrance section provided in the gaming area, the gaming ball is paid out from a payout device to the tray storage section. In addition, a configuration in which an upper tray storage section and a lower tray storage section are provided as the tray storage section is also known in pachinko gaming machines, in which the gaming balls stored in the upper tray storage section are guided to the gaming ball launching device, and the gaming balls that are surplus in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the reels have stopped rotating corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, various controls need to be performed appropriately, and there is still room for improvement in this regard.

<Characteristics Group Z>
Feature Z1. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
A situation generating means (a function of executing the processes of steps S7905, S7916, and S7917 in the main CPU 63) that makes it possible to set the setting value to be used by the setting means;
A setting notification means (a function for executing a setting confirmation process in the main CPU 63) that notifies the setting value of the target to be used in a situation where the setting is not possible when the supply of operating power to the control means (main CPU 63) having the setting means is started and processing at the start of supply is being executed;
A gaming machine comprising:

According to feature Z1, the setting value to be used is set from among multiple setting values corresponding to the player's degree of advantage, so the player will hope that the more advantageous setting value will be the setting value to be used. In this case, in order to check the setting value that is set to be used, it is necessary to temporarily stop the supply of operating power to the control means and then restart the supply of operating power to the control means. This makes it difficult to illegally check the setting value. In addition, since the setting value is notified when processing is being executed at the start of supply, there is no need to notify the setting value when play is interrupted. This makes it possible to preferably notify the setting value.

Feature Z2. The gaming machine described in Feature Z1, characterized in that the situation generating means causes the settable situation to occur in a situation in which the supply start processing is being executed.

According to feature Z2, it is possible to consolidate the setting possible situation in which the setting value to be used can be set and the situation in which the setting value to be used is notified in a situation in which it is not possible to set, into a situation in which processing is being performed at the start of supply.

Feature Z3. A first identification means (a function for executing the processes of steps S7912 and S7916 in the main CPU 63) for identifying the occurrence of a first trigger event is provided;
The gaming machine described in feature Z1 or Z2, characterized in that the setting notification means notifies the user of the setting value to be used in a situation that is not a settable situation, based on the situation in which the processing at the start of supply is being executed and the occurrence of the first trigger event has been identified by the first identification means.

According to feature Z3, in order to notify the setting value of the target device, it is necessary not only to start the supply of operating power to the control means but also to cause a first trigger event to occur. This makes it difficult to illegally check the setting value.

Feature Z4. The gaming machine described in Feature Z3, characterized in that the first triggering event is a predetermined operation being performed using a setting key on the setting key insertion section (setting key insertion section 68a).

According to feature Z4, in order to notify the settings of the target device, a specific operation must be performed using the setting key in the setting key insertion section. This makes it difficult to illegally check the setting values.

Feature Z5. The setting notification means notifies the setting value of the target to be used in the situation where the setting is not possible when a notification condition is satisfied based on the situation where the supply start processing is being executed and the occurrence of the first trigger event is identified by the first identification means,
the situation generating means sets the setting possible situation when a setting condition is satisfied based on a situation in which the supply start processing is being executed and the occurrence of the first trigger event is identified by the first identifying means,
A gaming machine described in feature Z3 or Z4, characterized in that the notification condition and the set condition are different.

According to feature Z5, in both cases of generating a setting possible situation and reporting the setting value of the target to be used, it is necessary to not only start the supply of operating power to the control means but also to generate a first trigger event. This makes it possible to make it difficult to fraudulently set the setting value of the target to be used and to fraudulently check the setting value of the target to be used. On the other hand, since the setting conditions for generating a setting possible situation and the reporting conditions for reporting the setting value of the target to be used are different, it is possible to independently generate either the setting possible situation or the situation in which the setting value of the target to be used is reported.

Feature Z6. A second identification means (a function for executing the process of step S7905 in the main CPU 63) for identifying the occurrence of a second trigger event is provided;
The set condition is established based on a situation in which, in a state in which the supply start processing is being executed, the occurrence of the first triggering event is identified by the first identification means and the occurrence of the second triggering event is identified by the second identification means,
The gaming machine described in feature Z5, characterized in that the notification condition is met based on a situation in which, when the processing at the start of supply is being executed, the occurrence of the first triggering event is identified by the first identification means, and the occurrence of the second triggering event is not identified by the second identification means.

According to feature Z6, in order to generate a setting possible state, it is necessary to start the supply of operating power to the control means and to generate not only the first triggering event but also the second triggering event. As a result, in both cases of setting the setting value to be used and of reporting the setting value to be used, in a configuration in which it is necessary to not only start the supply of operating power to the control means but also to generate the first triggering event, it is possible to make the operation for generating the setting possible state more complicated. Therefore, it is possible to more focused on preventing actions that attempt to fraudulently set the setting value to be used.

Feature Z7. The gaming machine described in Feature Z6, characterized in that the second triggering event is the operation of a specified operating means (reset button 68c).

According to feature Z7, in order to generate a setting possible state, it is necessary to start the supply of operating power to the control means and not only generate a first trigger event but also operate a specific operation means. This makes it difficult to fraudulently set the setting value to be used, while preventing the operation to legitimately generate a setting possible state from becoming excessively complicated.

Feature Z8. A gaming machine as described in feature Z6 or Z7, characterized in that it is provided with an information erasing means (a function for executing the processing of step S7915 in the main CPU 63) that executes an information erasing process based on the situation in which the occurrence of the second triggering event is identified by the second identification means in a situation in which the processing at the start of the supply is being executed.

According to feature Z8, by utilizing the second trigger event necessary to execute the information erasure process, it is possible to differentiate the condition for generating a setting possible situation from the condition for notifying the setting value to be used in a situation where the setting is not possible.

Feature Z9. The gaming machine described in Feature Z8, wherein the information erasing means executes the information erasing process even if the setting possible situation occurs.

Feature Z9 makes it possible to execute the information erasure process when the setting is possible.

Feature Z10. A gaming machine according to feature Z8 or Z9, characterized in that when the supply start processing is being executed and the occurrence of the second triggering event is identified by the second identification means but the occurrence of the first triggering event is not identified by the first identification means, the setting is not enabled but the information erasing process is executed by the information erasing means.

According to feature Z10, depending on whether or not a first trigger event occurs when the supply of operating power to the control means is started, it is possible to select between a case in which the information erasure process is executed and the setting is possible, and a case in which the information erasure process is executed but the setting is not possible.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features Z1 to Z10. This allows for a synergistic effect to be achieved through the combined configuration.

<Feature group a>
Feature a1. A setting means (a function for executing a setting value update process in the master CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
A situation generating means (a function of executing the processes of steps S7905, S7916, and S7917 in the main CPU 63) that makes it possible to set the setting value to be used by the setting means;
An information erasing means for executing information erasing processing (a function for executing the processing of step S7915 in the main CPU 63);
A setting notification means (a function for executing a setting confirmation process in the main CPU 63) for notifying the setting value of the target to be used in the situation where the setting is not possible;
A first identification means (a function for executing the processes of steps S7912 and S7916 in the main CPU 63) for identifying the occurrence of a first trigger event;
A second identification means (a function for executing the process of step S7905 in the main CPU 63) for identifying the occurrence of a second trigger event;
Equipped with
the situation generating means brings about the settable situation based on a situation in which the supply of operating power to the control means having the setting means is started and a process at the start of the supply is being executed, the occurrence of the first triggering event is identified by the first identifying means, and the occurrence of the second triggering event is identified by the second identifying means;
the information erasing means executes the information erasing process based on a situation in which the occurrence of the second triggering event is identified by the second identification means in a situation in which the process at the start of supply is being executed,
In a situation where the supply start processing is being executed, if the occurrence of the second triggering event is specified by the second specifying means and the occurrence of the first triggering event is not specified by the first specifying means, the information erasing process is executed by the information erasing means, although the setting is not possible.
The setting notification means notifies the user of the setting value to be used in a situation which is not a settable situation based on the situation in which the processing at the start of supply is being executed and the occurrence of the first triggering event is identified by the first identification means and the occurrence of the second triggering event is not identified by the second identification means.

According to feature a1, the setting value to be used is set from among multiple setting values corresponding to the player's degree of advantage, so the player will expect that the more advantageous setting value will be the one to be used. In addition, since the configuration allows for the execution of an information erasure process, it is possible to prevent play from being played despite the occurrence of an information anomaly. In addition, since the configuration allows for the notification of the setting value set to be used, it is possible to check the setting value.

In this case, in order to check the setting value that is set as the target for use, it is necessary to start the supply of operating power to the control means and to cause the first trigger event to occur. This makes it difficult to illegally check the setting value.

In addition, in order to generate a setting possible state, it is necessary to start the supply of operating power to the control means and to generate not only the first trigger event but also the second trigger event. This makes it possible to make the operation for generating a setting possible state more complicated in a configuration in which it is necessary not only to start the supply of operating power to the control means but also to generate the first trigger event, whether the setting value to be used is to be set or the setting value to be used is to be notified. This makes it possible to more focused on preventing actions that attempt to fraudulently set the setting value to be used.

In addition, by utilizing the second trigger event required to execute the information erasure process, it is possible to differentiate between the conditions for generating a setting possible state and the conditions for notifying the setting value to be used in a state where the setting is not possible.

In addition, depending on whether or not a first trigger event occurs when the supply of operating power to the control means is started, it is possible to select between a case in which the information erasure process is executed and the setting becomes possible, and a case in which the information erasure process is executed but the setting does not become possible.

Feature a2. The gaming machine described in feature a1, characterized in that the first triggering event is a predetermined operation being performed using a setting key on the setting key insertion section (setting key insertion section 68a).

According to feature a2, in order to notify the settings of the target device, a specific operation must be performed using the setting key in the setting key insertion section. This makes it difficult to illegally check the setting values.

Feature a3. The gaming machine described in feature a1 or a2, characterized in that the second triggering event is the operation of a predetermined operation means (reset button 68c).

According to feature a3, in order to generate a setting possible state, it is necessary to start the supply of operating power to the control means and to operate the specific operation means in addition to generating the first trigger event. This makes it difficult to fraudulently set the setting value to be used, while preventing the operation for legitimately generating the setting possible state from becoming excessively complicated.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features a1 to a3. This allows for a synergistic effect to be achieved through the combined configuration.

The invention relating to the above-mentioned feature group Z and feature group a can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine that stores gaming balls given to a player, and the gaming balls stored in the tray storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entrance section provided in the gaming area, the gaming ball is paid out from a payout device to the tray storage section. In addition, a configuration in which an upper tray storage section and a lower tray storage section are provided as the tray storage section is also known in pachinko gaming machines, in which the gaming balls stored in the upper tray storage section are guided to the gaming ball launching device, and the gaming balls that are surplus in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the reels have stopped rotating corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, a configuration is required that allows for convenient confirmation of the setting values that determine the advantageous degree of the gaming machine, and there is still room for improvement in this regard.

<Feature group b>
Feature b1. A setting means (a function for executing a setting value update process in the master CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
A situation generating means (a function of executing the processes of steps S7905, S7916, and S7917 in the main CPU 63) that makes it possible to set the setting value to be used by the setting means;
A setting monitoring means (a function for executing the process of step S8220 in the main CPU 63) for executing a setting monitoring process for monitoring whether the setting value of the target to be used is abnormal or not;
Equipped with
A gaming machine characterized in that the setting monitoring process is not included in the supply start process executed when the supply of operating power to a control means having the setting means is started.

According to feature b1, the setting value to be used is set from among multiple setting values corresponding to the player's degree of advantage, so the player will expect that the more advantageous setting value will be the setting value to be used. In addition, a setting monitoring process is executed to monitor whether the setting value to be used is abnormal, so if the setting value to be used is abnormal, it is possible to deal with it. In addition, since the processing at the start of supply does not include a setting monitoring process, it is possible to achieve the above-mentioned excellent effects while preventing an increase in the processing load of the processing at the start of supply.

Feature b2. The gaming machine described in feature b1, wherein the situation generating means generates the settable situation in a situation where the supply start processing is being executed.

According to feature b2, a setting possible situation occurs while the processing at the start of supply is being executed, so it is possible to set the setting value to be used before the start of play. In this case, the setting value to be used is set in the processing at the start of supply, so the processing load of the processing at the start of supply increases accordingly. In contrast, since the configuration of feature b1 is provided and the processing at the start of supply does not include a setting monitoring process, it is possible to monitor whether the setting value to be used is abnormal while preventing a further increase in the processing load of the processing at the start of supply.

Feature b3. The gaming machine described in feature b1 or b2, characterized in that the setting monitoring means executes the setting monitoring process after the process at the start of the supply is completed.

According to feature b3, the setting monitoring process is executed after the processing at the start of supply is completed, so it is possible to monitor whether the setting value of the target to be used is abnormal while preventing the processing load of the processing at the start of supply from increasing.

Feature b4. The gaming machine described in feature b3, wherein the setting monitoring means executes the setting monitoring process each time a monitoring trigger occurs after the process at the start of the supply is completed.

According to feature b4, after the processing at the start of supply is completed, the setting monitoring process is executed each time a monitoring trigger occurs, making it easier to identify if the setting value of the target to be used is abnormal.

Feature b5. The device includes a means for executing an interrupt process that is periodically started (a function for executing a first timer interrupt process in the main CPU 63);
A gaming machine described in any one of features b1 to b4, characterized in that the interrupt processing includes the setting monitoring processing.

According to feature b5, the setting monitoring process is executed each time the device is started periodically, which makes it possible to increase the frequency of monitoring whether the setting values of the target device are abnormal.

Feature b6. A gaming machine according to any one of features b1 to b5, characterized in that the setting monitoring means includes a means for regulating the progress of the game based on the determination in the setting monitoring process that the setting value of the target to be used is abnormal (a function for executing the processes of steps S8207 and S8302 in the main CPU 63).

According to feature b6, if it is determined that the setting value of the target to be used is abnormal, the progress of the game is restricted, so that it is possible to prevent the game from continuing even if the setting value of the target to be used is abnormal.

Feature b7. The gaming machine according to any one of features b1 to b6, characterized in that the setting monitoring means includes a means (a function for executing the process of step S8303 in the main CPU 63) for executing a notification that enables the player to recognize that the setting possible situation should be generated based on the setting monitoring process identifying that the setting value of the target to be used is abnormal.

According to feature b7, when it is determined that the setting value of the target to be used is abnormal, a notification is issued to enable the player to recognize that a setting possible situation should be generated, so that when the setting value of the target to be used becomes abnormal, it is possible to urge the manager of the amusement hall to resolve the abnormality.

In addition, any one or more of the configurations of features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, and features b1 to b7 may be applied to the configurations of features b1 to b7. This allows for a synergistic effect to be achieved through the combined configuration.

The invention relating to the above feature group b can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine that stores gaming balls given to a player, and the gaming balls stored in the tray storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entrance section provided in the gaming area, the gaming ball is paid out from a payout device to the tray storage section. In addition, a configuration in which an upper tray storage section and a lower tray storage section are provided as the tray storage section is also known in pachinko gaming machines, in which the gaming balls stored in the upper tray storage section are guided to the gaming ball launching device, and the gaming balls that are surplus in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the reels have stopped rotating corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary to appropriately manage the settings that determine the advantageous degree of the gaming machine, and there is still room for improvement in this regard.

The following shows the basic configuration of a gaming machine to which each of the above features can be applied or to which each feature can be applied.

Pachinko game machine: A game machine that has an operating means operated by the player, a game ball launching means that launches game balls based on the operation of the operating means, a ball passage that guides the launched game balls to a specified game area, and various game components arranged within the game area, and that awards a special prize to the player when the game ball passes through a specified passage section of each of the game components.

Slot machines and other reel-type gaming machines: gaming machines equipped with a picture display device that variably displays multiple pictures, in which the variable display of the multiple pictures is started by operating a start operation means, the variable display of the multiple pictures is stopped by operating a stop operation means or after a predetermined time has passed, and a bonus is given to the player according to the picture after the stop.

10... Pachinko machine, 12... Game machine main body, 14... Front door frame, 28... Firing operation device, 33... First operating port, 34... Second operating port, 35... Through gate, 49a... Gate detection sensor, 63... Main CPU, 65... Main RAM, 68a... Setting key insertion section, 68b... Update button, 68c... Reset button, 69a... First notification display device, 69b... Second notification display device, 69c... Third notification display device, 112... Management CPU, 117... History memory, 171... Separate storage memory, 181 to 186... History memory for settings 1 to 6, 191... First history memory, 192... Second history memory, 201... First notification display device 201a-201g...display segments, 202...second notification display device, 202a-202g...display segments, 203...third notification display device, 204...fourth notification display device, 221...work area for specific control, 222...stack area for specific control, 223...work area for non-specific control, 224...stack area for non-specific control, 231...normal counter area, 232...counter area for opening/closing execution mode, 233...counter area for high frequency support mode, 234...calculation result storage area, 241...management RAM, 251...reset signal output unit, 252...program monitoring unit.

Claims (1)

A front body of the gaming machine that can be opened and closed;
a game value providing means electrically connected to a predetermined detection means for detecting a game ball and for executing a process for providing a game value for a game;
A process execution means electrically connected to the game value providing means and executing a predetermined process;
In a gaming machine comprising:
The game value providing means includes:
a first reference information storage means for storing reference information, which is information used in a process for awarding the game value and is information to be referenced in response to detection by the predetermined detection means;
a first transmitting means for transmitting a reference information signal corresponding to the reference information stored in the first reference information storage means to the process executing means after a predetermined supply of power to the gaming machine is started and before execution of a predetermined process for progressing a game is started;
a second transmitting means for transmitting a predetermined information signal based on information acquired based on detection by the predetermined detecting means to the processing executing means;
a third transmitting means for transmitting a predetermined state signal to the process executing means when a front body of the gaming machine is opened and a predetermined state occurs;
a means for executing an erasure process of information in a predetermined storage area after a predetermined supply of power to the gaming machine is started and before the execution of the predetermined process is started based on the occurrence of a predetermined trigger;
Equipped with
The process execution means includes:
a second reference information storage means for storing reference information corresponding to the reference information signal transmitted from the game value providing means;
an execution means for executing the predetermined process based on the predetermined information signal transmitted from the second transmission means and the reference information stored in the second reference information storage means;
a processing result information storage means for storing processing result information which is information regarding a processing result of the predetermined processing by the execution means;
a means for storing information corresponding to the predetermined status signal transmitted from the third transmitting means when the predetermined status signal is received;
a means for erasing the processing result information stored in the processing result information storage means when a predetermined event occurs based on the performance of a predetermined operation;
Equipped with
The execution means executes the predetermined process when a predetermined execution trigger occurs, which is a trigger other than an execution instruction from the game value providing means and is a trigger for executing the predetermined process;
The game value providing means is a main control means for controlling the progress of a game,
The process execution means is a performance control means for controlling the execution of a performance,
the first transmitting means is configured to transmit the reference information signal to the processing executing means after the erasing process is executed when the predetermined trigger occurs;
A gaming machine characterized in that, when a predetermined event occurs in which control of the progress of the game is stopped, a predetermined control for transmitting the predetermined information signal by the second transmitting means is not executed.

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