JP7529139B2 - Silicon carbide semiconductor device, manufacturing method thereof, and power conversion device - Google Patents

Description

The present disclosure relates to a silicon carbide semiconductor device having a trench gate and a manufacturing method thereof, and a power conversion device using a silicon carbide semiconductor device having a trench gate.

There is known a power semiconductor device that incorporates a unipolar switching element such as a metal-oxide-semiconductor field-effect transistor (MOSFET) and a unipolar freewheeling diode such as a Schottky barrier diode (SBD). Such a semiconductor device can be realized by arranging a MOSFET cell and an SBD cell in parallel on the same chip, and generally by providing a Schottky electrode in a specific region within the chip and operating that region as an SBD.

By incorporating a free wheel diode into the switching element chip, costs can be reduced compared to when the free wheel diode is attached externally to the switching element. In particular, in MOSFETs that use silicon carbide (SiC) as the base material, one of the benefits is that bipolar operation caused by a parasitic pn diode can be suppressed by incorporating an SBD. This is because in silicon carbide semiconductor devices, the reliability of the element can be impaired due to the expansion of crystal defects caused by carrier recombination energy due to parasitic pn diode operation.

In addition, in a trench-gate MOSFET having a structure in which a gate electrode is embedded in a trench formed in a semiconductor layer, the channel can be formed on the sidewall of the trench, which improves the channel width density and reduces the on-resistance compared to a planar MOSFET having a structure in which a gate electrode is formed on the surface of the semiconductor layer. Therefore, a structure in which an SBD is built into a trench-gate MOSFET is known (for example, Patent Document 1).

JP 2019-218224 A

In such trench MOSFETs with built-in SBDs, a Schottky interface is formed on the trench sidewalls, but there are cases where the Schottky interface cannot be formed uniformly. If the Schottky interface cannot be formed uniformly, the Schottky barrier height becomes non-uniform, which can result in non-uniform leakage current during reverse bias or the occurrence of areas where the adhesion between the Schottky electrode and the semiconductor layer is reduced, causing the Schottky electrode to peel off in parts.

The present disclosure has been made to solve the above-mentioned problems, and aims to provide a highly reliable silicon carbide semiconductor device by forming a uniform Schottky interface, thereby making the leakage current at the Schottky interface uniform and suppressing peeling of the Schottky electrode at the Schottky interface.

a source region made of silicon carbide of the first conductivity type formed on at least a portion of the body region; a gate trench penetrating the source region and the body region to reach the drift layer; a gate electrode formed in the gate trench facing the body region via a gate insulating film; a Schottky trench formed so as to have a lower end at least within the drift layer; a Schottky electrode formed in the Schottky trench and mainly composed of Ti; and a reaction layer formed between the Schottky electrode and the drift layer in contact with a side surface of the Schottky trench, the reaction layer being made of TiSi having an atomic composition ratio of Ti to Si of 0.5 or more and having an atomic composition concentration of oxygen of 5% or less .

The silicon carbide semiconductor device disclosed herein can provide a highly reliable silicon carbide semiconductor device.

1 is a cross-sectional view of a silicon carbide semiconductor device in accordance with a first embodiment; 1 is a plan view of a silicon carbide semiconductor device in accordance with a first embodiment; 1 is a cross-sectional view of a silicon carbide semiconductor device during manufacture in accordance with a first embodiment; 1 is a cross-sectional view of a silicon carbide semiconductor device during manufacture in accordance with a first embodiment; 1 is a cross-sectional view of a silicon carbide semiconductor device during manufacture in accordance with a first embodiment; 1 is a cross-sectional view of a silicon carbide semiconductor device during manufacture in accordance with a first embodiment; 1 is a cross-sectional view of a silicon carbide semiconductor device during manufacture in accordance with a first embodiment; 1 is a cross-sectional view of a silicon carbide semiconductor device during manufacture in accordance with a first embodiment; 1 is a cross-sectional view of a silicon carbide semiconductor device during manufacture in accordance with a first embodiment; 1 is a cross-sectional view of a silicon carbide semiconductor device during manufacture in accordance with a first embodiment; 2 is a cross-sectional SEM view of a Schottky interface of the silicon carbide semiconductor device according to the first embodiment; 3 is a reference cross-sectional SEM view of a Schottky interface of a silicon carbide semiconductor device related to the first embodiment. FIG. FIG. 11 is a cross-sectional view of a silicon carbide semiconductor device according to a second embodiment. 11 is a cross-sectional view of a silicon carbide semiconductor device during manufacture in accordance with a second embodiment. FIG. 11 is a cross-sectional view of a silicon carbide semiconductor device during manufacture in accordance with a second embodiment. FIG. FIG. 11 is a cross-sectional view of a silicon carbide semiconductor device according to a third embodiment. FIG. 13 is a cross-sectional view of a silicon carbide semiconductor device according to a fourth embodiment. FIG. 13 is a schematic diagram showing the configuration of a power conversion device according to a fifth embodiment.

Hereinafter, the embodiments will be described with reference to the accompanying drawings. Note that the drawings are shown in a schematic manner, and the size and positional relationship of images shown in different drawings are not necessarily described accurately and may be changed as appropriate. In addition, in the following description, similar components are illustrated with the same reference numerals, and their names and functions are also the same. Therefore, detailed description thereof may be omitted.
In the following embodiments, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the conductivity types may be reversed.

Embodiment 1.
First, a silicon carbide semiconductor device according to a first embodiment of the present disclosure will be described.
Fig. 1 is a cross-sectional view of a portion of an active region of a trench-type silicon carbide MOSFET with built-in Schottky barrier diode (SiC trench MOSFET with built-in SBD) which is a silicon carbide semiconductor device according to embodiment 1. Fig. 2 is a plan view of the SiC trench MOSFET with built-in SBD shown in Fig. 1, at a certain depth where a trench is formed.

1, a drift layer 20 made of n-type silicon carbide is formed on the surface of a semiconductor substrate 10 made of n-type low-resistance silicon carbide. A body region 30 made of p-type silicon carbide is provided on the drift layer 20.
Gate trenches 91 and Schottky trenches 92 are alternately arranged in parallel in the drift layer 20 in which the body region 30 is formed. A source region 40 made of n-type silicon carbide is provided in a surface layer portion of the body region 30 adjacent to the gate trench 91. A low-resistance p-type contact region 35 is formed in a surface layer portion of the body region 30 between the gate trench 91 and the Schottky trench 92.

The gate trench 91 is formed so as to extend from the surface of the source region 40 through the source region 40 and the body region 30 to reach the drift layer 20. The Schottky trench 92 is formed so as to extend from the surface of the body region 30 through the body region 30 to reach the drift layer 20. A gate electrode 60 is formed in the gate trench 91 via a gate insulating film 50 made of silicon oxide. The gate electrode 60 is made of low-resistance polycrystalline silicon with a high impurity concentration. An interlayer insulating film 55 made of silicon oxide is formed on the gate electrode 60.

A Schottky electrode 81 containing Ti is formed in the Schottky trench 92, and a reaction layer 71 made of TiSi is formed at the interfaces between the Schottky trench 92 and the drift layer 20 and between the Schottky trench 92 and the body region 30. The reaction layer 71 and the Schottky electrode 81 as a whole form a Schottky connection with the drift layer 20.
A p-type first protection region 31 is formed in the drift layer 20 at the bottom of the gate trench 91. A p-type second protection region 32 is formed in the drift layer 20 at the bottom of the Schottky trench 92. The first protection region 31 and the second protection region 32 have the same depth and the same impurity concentration. A drain electrode 82 is formed on the back surface side of the semiconductor substrate 10.
In addition, an ohmic electrode 70 is formed on the contact region 35 and the source region 40 , and a source electrode 80 is formed on the ohmic electrode 70 and the Schottky electrode 81 .

2, in a plan view, p-type connection regions are formed at regular intervals along the longitudinal direction of the striped gate trench 91 and Schottky trench 92. The p-type connection region formed for the gate trench 91 is the first connection region 33, which is formed in the drift layer 20 so as to connect the first protection region 31 and the body region 30. The p-type connection region formed for the Schottky trench 92 is the second connection region 34, which is formed in the drift layer 20 so as to connect the second protection region 32 and the body region 30.

Here, the reaction layer 71 is a layer formed by the reaction of Ti and Si, and the atomic composition ratio of Ti to Si is 0.5 or more and 2.0 or less. The thickness of the reaction layer 71 is 1 nm or more and 50 nm or less. The reaction layer 71 between the drift layer 20 and the Schottky electrode 81 is formed uniformly.

Furthermore, the Schottky electrode 81 may be made of Ti, but at least the part closest to the semiconductor layer must be made of Ti, and it may also be a layered structure of Ti and another metal.

Next, a method for manufacturing the silicon carbide semiconductor device of the present embodiment will be described with reference to the cross-sectional views of FIGS. 3 to 10 corresponding to the cross section shown in FIG.
explain.

First, on a semiconductor substrate 10 made of n-type low-resistance silicon carbide having a first main surface that is a (0001) surface tilted by 1° or more in the <11-20> direction and a polytype of 4H, a drift layer 20 made of n-type silicon carbide with an impurity concentration of 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁷ cm ⁻³ or less and a thickness of 5 μm or more and 50 μm or less is epitaxially grown by chemical vapor deposition (CVD). The surface of the drift layer 20 also becomes a (0001) surface tilted by 1° or more in the <11-20> direction.

Next, p-type impurity Al (aluminum) is ion-implanted into the surface of the drift layer 20. At this time, the depth of the Al ion implantation is set to about 0.5 μm or more and 3 μm or less, which does not exceed the thickness of the drift layer 20. Furthermore, the impurity concentration of the ion-implanted Al is in the range of 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less, which is higher than the impurity concentration of the drift layer 20. The region into which Al ions are implanted by this process becomes the body region 30.

Next, an implantation mask is formed using photoresist or the like so that a predetermined portion of the body region 30 on the surface of the drift layer 20 is opened, and N (nitrogen) which is an n-type impurity is ion-implanted. The ion implantation depth of N is shallower than the thickness of the body region 30. The impurity concentration of the ion-implanted N is in the range of 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less, which exceeds the p-type impurity concentration of the body region 30. The region that exhibits n-type among the regions implanted with N in this process becomes the source region 40. After that, the implantation mask is removed.
In a similar manner, contact region 35 is formed by ion-implanting Al into a predetermined region of body region 30 adjacent to source region 40 so that the impurity concentration is in the range of 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less, which is higher than the impurity concentration of body region 30. Through this process, the structure shown in the cross-sectional view of FIG.

Next, a resist mask is formed to open a part of the region where the source region 40 is formed, and a gate trench 91 is formed by dry etching, penetrating the source region 40 and the body region 30 to reach the drift layer 20. Similarly, a resist mask is formed to open a part of the region where the source region 40 is not formed, and a Schottky trench 92 is formed by dry etching, penetrating the body region 30 to reach the drift layer 20.
At this time, the gate trench 91 and the Schottky trench 92 are formed so that their longitudinal direction is along the <11-20> direction. When the sidewalls of the gate trench 91 and the Schottky trench 92 are formed perpendicular to the surface of the drift layer 20, the longitudinal sidewalls of the gate trench 91 and the Schottky trench 92 are the (1-100) plane and the (-1100) plane. In reality, the longitudinal sidewalls of the gate trench 91 and the Schottky trench 92 form an angle of 80 degrees or more and 90 degrees or less with respect to the surface of the drift layer 20 or the first main surface which is the surface of the semiconductor substrate 10. Therefore, the longitudinal sidewalls of the gate trench 91 and the Schottky trench 92 are surfaces inclined at 10 degrees or less from the (1-100) plane and the (-1100) plane.
Here, the gate trench 91 and the Schottky trench 92 may be formed to the same depth by the same dry etching process. Through these steps, the structure shown in the cross section of FIG.

5, p-type impurities are ion-implanted into the drift layer 20 at the bottoms of the gate trench 91 and the Schottky trench 92 to form the first protection region 31 and the second protection region 32, respectively. The p-type impurity concentrations of the first protection region 31 and the second protection region 32 may be in the range of 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less. After the ion implantation, the resist mask is removed. In addition, a resist mask is formed with openings at the locations where the first connection region 33 and the second connection region 34 are to be formed, and the first connection region 33 and the second connection region 34 are formed by obliquely ion-implanting p-type impurities. The p-type impurity concentrations of the first connection region 33 and the second connection region 34 may be in the range of 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less. After the ion implantation, the resist mask is removed.
Next, annealing is performed in an inert gas atmosphere such as argon (Ar) gas at a temperature of 1300 to 1900° C. for 30 seconds to 1 hour by a heat treatment device. This annealing electrically activates the implanted N and Al ions.

Next, with the Schottky trench 92 covered with a protective insulating film, a gate insulating film 50 made of silicon oxide and having a thickness of 10 nm or more and 300 nm or less is formed in the gate trench 91. Next, a film made of conductive polycrystalline silicon and having a thickness of 300 nm or more and 2000 nm or less is formed in the gate insulating film 50 by a reduced pressure CVD method and patterned to form the gate electrode 60. After removing the protective insulating film, the cross-sectional view shown in FIG. 6 is formed.

Next, an interlayer insulating film 55 made of silicon oxide and having a thickness of 500 nm or more and 3000 nm or less is formed by low pressure CVD.
Next, interlayer insulating film 55 is etched to open the areas where source region 40 and contact region 35 are formed, and a metal such as Ni is deposited inside the opening and annealed, thereby forming ohmic electrode 70 made of a NiSi alloy layer (silicide) on source region 40 and contact region 35, as shown in the cross-sectional view of FIG. 7.

8, after removing the interlayer insulating film 55 in the Schottky trench 92, a Schottky electrode 81 made of Ti is formed by sputtering in the Schottky trench 92, on the ohmic electrode 70, and on the interlayer insulating film 55. A source electrode 80 containing Al is formed thereon by sputtering. The source electrode 80 may have a laminated structure of Al/Ti. A cross-sectional view of this state is shown in FIG.
Thereafter, with the Schottky electrode 81 formed in the Schottky trench 92, the structure is heated in an inert gas such as Ar by increasing the temperature from room temperature to a temperature of 400° C. or more and 600° C. or less at a temperature increase rate of 10° C./sec. The heating time for annealing at a temperature of 400° C. or more and 600° C. or less may be 5 minutes or more and 30 minutes or less.

By heating under such conditions, as shown in the cross-sectional view of FIG. 10, a reaction layer 71 made of TiSi is formed at the interface between the drift layer 20 and the Schottky electrode 81. As described above, the atomic composition ratio of Ti to Si in the reaction layer 71 is 0.5 or more and 2.0 or less. The thickness of the reaction layer 71 is 5 nm or more and 50 nm or less. The reaction layer 71 is formed uniformly in the region where the reaction layer 71 is formed. Since the reaction layer 71 is heated in an inert gas, the oxygen concentration in the reaction layer 71 is low, and the atomic composition concentration of oxygen in the reaction layer 71 is 5% or less. Since the reaction layer 71 is formed in a state where there is little oxygen, it is possible to prevent unevenness from being formed at the interface, and the reaction layer 71 is formed uniformly.
Furthermore, the longitudinal sidewalls of the gate trench 91 and the Schottky trench 92 are (1-100) and (-1100) planes that are not affected by the off-orientation of the semiconductor substrate 10, or planes inclined by 10 degrees or less from these planes, so that the reaction layer 71 can be formed uniformly on both longitudinal sidewall surfaces of the Schottky trench 92 regardless of the magnitude of the off-orientation of the semiconductor substrate 10.

Here, a cross-sectional SEM (Scanning Electron Microscope) diagram from the source electrode 80 to the drift layer 20 of the silicon carbide semiconductor device of the present embodiment is shown in Fig. 11. Fig. 11 shows a case where a Schottky electrode 81 is formed in a Schottky trench 92, the temperature is increased at a rate of 10°C/sec, and annealed in Ar gas at a temperature of 450°C for 10 minutes. In contrast, Fig. 12 is a cross-sectional SEM diagram (reference diagram) of a case where a Schottky electrode 81 is formed in a Schottky trench 92, the temperature is increased at a rate of 10°C/sec, and annealed in Ar gas at a temperature of 800°C for 10 minutes.
The Schottky interface of the silicon carbide semiconductor device of this embodiment annealed at 450° C. has a reaction layer 71 formed uniformly with approximately the same thickness, whereas the reference structure ( FIG. 12 ) annealed at 800° C. does not have a uniform interface.

Next, a backside ohmic electrode and a drain electrode 82 (not shown) are formed on the backside, thereby manufacturing an SBD-integrated SiC trench MOSFET, the cross-sectional view of which is shown in Figure 1.

In the above example, the silicon carbide layer in contact with the upper end of the Schottky trench 92 is a p-type body region 30, but an n-type low resistance region may also be formed here.

According to the silicon carbide semiconductor device of the present embodiment, not only is the Schottky barrier height of the SBD formed between the Schottky electrode 81 and the drift layer 20 constant in each Schottky trench 92, but also the variation with the Schottky barrier height of the SBD of the other Schottky trenches 92 in the chip is reduced. Therefore, it is possible to suppress a leakage current from flowing during off from a portion where the Schottky barrier height is partially small. In addition, the adhesion between the Schottky electrode 81 and the drift layer 20 on the sidewall of the Schottky trench 92 is improved, and partial peeling of the Schottky electrode 81 can be prevented, thereby obtaining a highly reliable silicon carbide semiconductor device.
Furthermore, since the longitudinal direction of the stripe-shaped Schottky trench 92 is formed parallel to the off-direction of the semiconductor substrate 10, i.e., along the off-direction, reaction layers 71 of the same properties and thickness can be formed on both longitudinal side walls of the Schottky trench 92 without being affected by the off-angle of the semiconductor substrate 10.

Embodiment 2.
13 is a cross-sectional view of a portion of an active region in a silicon carbide semiconductor device according to the second embodiment. The silicon carbide semiconductor device according to the present embodiment is different from the silicon carbide semiconductor device according to the first embodiment in that it further includes an ohmic electrode 70 between the body region 30 in contact with the Schottky trench 92 and the Schottky trench 92. That is, the ohmic electrode 70 formed on the contact region 35 and the source region 40 extends to an upper portion of the side wall of the Schottky trench 92. Other points are the same as those in the first embodiment, and therefore detailed description will be omitted.

In the silicon carbide semiconductor device of the present disclosure, the Schottky interface of the SBD formed between the Schottky electrode 81 and the drift layer 20 may be formed homogeneously, and the reaction layer 71 may not be present between the body region 30 and the Schottky electrode 81. In FIG. 13, the Schottky trench 92 is formed penetrating the contact region 35 and the body region 30. In the Schottky trench 92, the ohmic electrode 70 is formed in the entire region where the contact region 35 faces the Schottky trench 92 and in a part of the region where the body region 30 faces the Schottky trench 92. The reaction layer 71 is formed in the region of the Schottky trench 92 facing the lower part of the body region 30 and the drift layer 20.

Next, a method for manufacturing the silicon carbide semiconductor device according to the present embodiment will be described.
3 to 6 in the first embodiment. For the structure shown in Fig. 6, interlayer insulating film 55 is patterned so that interlayer insulating film 55 remains only on gate trench 91 and at the bottom of Schottky trench 92, as shown in a cross-sectional view in Fig. 14.
Next, as shown in the cross-sectional view of FIG. 15, similarly to the first embodiment, ohmic electrodes 70 are formed in the areas where the interlayer insulating film 55 is not formed, and the interlayer insulating film at the bottom of the Schottky trench 92 is removed.
Thereafter, a Schottky electrode 81 is formed and annealing is performed similar to that of embodiment 1, and then a drain electrode 82 is formed on the back surface side of semiconductor substrate 10, thereby manufacturing the silicon carbide semiconductor device of this embodiment having the cross-sectional view of Figure 13.

According to the silicon carbide semiconductor device of the present embodiment, the contact area between the contact region 35 and the ohmic electrode 70 can be increased, so that the contact resistance between the body region 30 and the Schottky electrode 81 and the source electrode 80 can be reduced. In addition, since there is no need to form a region between the contact region 35 and the Schottky trench 92, the width of the contact region 35 between the end of the source region 40 and the Schottky trench 92 in the cross-sectional lateral direction, that is, the width of the contact region 35, can be reduced. Therefore, the width on the cross section of the unit cell shown in the cross section of FIG. 13 can be reduced, and as a result, the amount of current flowing per unit area can be increased. In other words, the on-resistance of the chip can be reduced.

In addition, since an ohmic electrode 70 is formed at the upper end of the Schottky trench 92 by reacting a silicon carbide layer with a metal such as Ni, the corners of the upper end of the Schottky trench 92 are rounded. This improves the embeddability when embedding the Schottky electrode 81 in the Schottky trench 92, and allows for a higher manufacturing yield.

Embodiment 3.
Fig. 16 is a cross-sectional view of a portion of an active region in a silicon carbide semiconductor device according to embodiment 3. The silicon carbide semiconductor device according to the present embodiment in Fig. 16 differs from the silicon carbide semiconductor device according to embodiment 1 in that reaction layer 71 is not uniformly formed within Schottky trench 92. Other points are the same as those in embodiment 1, and therefore detailed description will be omitted.

In the silicon carbide semiconductor device of the present disclosure, it is sufficient that the Schottky interface of the SBD formed between the Schottky electrode 81 and the drift layer 20 is formed homogeneously, and the reaction layer 71 between the body region 30 and the Schottky electrode 81 does not need to be the same thickness as the reaction layer 71 formed between the Schottky electrode 81 and the drift layer 20. In addition, the reaction layer 71 between the body region 30 and the Schottky electrode 81 may not be present.

16, in the silicon carbide semiconductor device of this embodiment, the Schottky electrode 81 does not have to be embedded in the entire region where the body region 30 contacts the Schottky trench 92. When embedding the Schottky electrode 81 in the Schottky trench 92, the silicon carbide semiconductor device of this embodiment can be manufactured by not embedding the entire Schottky trench 92, or by removing the upper part after embedding. The upper part of the Schottky trench 92 where the Schottky electrode 81 is not embedded can be filled with the source electrode 80 to be formed later.

According to the silicon carbide semiconductor device of this embodiment, even if the Schottky electrode 81 is not embedded up to the upper part of the Schottky trench 92, a homogeneous reaction layer 71 can be formed between the drift layer 20 and the Schottky electrode 81, making it easier to manufacture.

Embodiment 4.
Fig. 17 is a cross-sectional view of a portion of an active region in a silicon carbide semiconductor device according to embodiment 4. In the silicon carbide semiconductor device according to the present embodiment shown in Fig. 17, an inclined surface 92T is formed on the side wall at the lower part of Schottky trench 92. Other points are the same as those in embodiment 1, and therefore detailed description will be omitted.

17 , in the silicon carbide semiconductor device of the present embodiment, in a region where the Schottky electrode 81 and the drift layer 20 face each other at the bottom of the Schottky trench 92, an inclined surface 92T is formed at an angle of 45 degrees with respect to the silicon carbide layer surface. A reaction layer 71 having a constant thickness is formed between the Schottky electrode 81 and the drift layer 20.
The boundary between the body region 30 and the Schottky electrode 81 is a plane perpendicular to the surface of the silicon carbide layer, and a reaction layer 71 is also formed at the interface.
The silicon carbide semiconductor device of the present embodiment can be manufactured by performing etching in two stages when etching Schottky trench 92 .

According to the silicon carbide semiconductor device of the present embodiment, the area of the Schottky interface can be increased for a trench of the same depth, and the unipolar current density that can flow per unit area can be increased.
In addition, since the angles formed by both corners of the bottom of Schottky trench 92 are obtuse angles, the embeddability of Schottky electrode 81 in Schottky trench 92 is improved, and the probability of a cavity-like space being formed in Schottky trench 92 can be further reduced.
Furthermore, according to the silicon carbide semiconductor device of the present embodiment, the corner portions of the bottom of Schottky trench 92 are covered with second protection region 32 of the second conductivity type, so that the electric field applied to gate insulating film 50 in the vicinity of the bottom of Schottky trench 92 can be reduced, and a more reliable silicon carbide semiconductor device can be obtained.

In this way, the silicon carbide semiconductor device of this embodiment has an SBD with a large area and consistent Schottky barrier height, making it a more reliable silicon carbide semiconductor device.

In the silicon carbide semiconductor device of this embodiment, the inclined surface 92T of Schottky trench 92 has been described as being inclined at an angle of 45 degrees with respect to the silicon carbide layer surface, but this angle does not necessarily have to be 45 degrees and may be an angle of 35 degrees or more and 60 degrees or less.
Furthermore, in the silicon carbide silicon carbide semiconductor device of this embodiment, the case has been described where the Schottky interfaces at which reaction layer 71 is formed are all inclined surfaces 92T, but even if part of the Schottky interface is formed on a surface that is not inclined surface 92T but is approximately perpendicular to the silicon carbide layer surface, the same effect can be achieved as long as reaction layer 71 is formed uniformly on both.

In the first to fourth embodiments, the Schottky electrode 81 and the source electrode 80 are formed separately. However, the Schottky electrode 81 and the source electrode 80 may be integrated into the same electrode as long as the bottom layer is made of Ti. In this case, the entire structure may be a laminated structure.

In addition, in the first to fourth embodiments, the method of forming the body region 30 and the source region 40 by ion implantation has been described, but the body region 30 and the source region 40 may be formed by other methods, for example, by an epitaxial method. Furthermore, although an example in which the body region 30 is formed over the entire surface has been described, the body region 30 may be formed in a part of the upper layer of the drift layer 20. In this case, the Schottky trench 92 may be provided directly from the surface of the drift layer 20, rather than penetrating the body region 30.

Furthermore, in the first to fourth embodiments, the first protection region 31 and the second protection region 32 are provided in the lower part of the trench, but the first protection region 31 and the second protection region 32 may be omitted in some cases. In this case, the first connection region 33 and the second connection region 34 may not be provided either.
Furthermore, the gate trenches 91 and the Schottky trenches 92 may be provided in a lattice shape instead of a stripe shape.

Furthermore, in the first to fourth embodiments, aluminum (Al) is used as the p-type impurity, but the p-type impurity may be boron (B) or gallium (Ga). The n-type impurity may be phosphorus (P) instead of nitrogen (N). In the MOSFETs described in the first and second embodiments, the gate insulating film does not necessarily have to be an oxide film such as SiO ₂ , and may be an insulating film other than an oxide film, or a combination of an insulating film other than an oxide film and an oxide film. In the above embodiments, specific examples of the crystal structure, the plane orientation of the main surface, the off-angle, and each implantation condition are described, but the applicable range is not limited to these numerical ranges.

In the above embodiment, the SBD is incorporated in a silicon carbide semiconductor device of a so-called vertical MOSFET in which the drain electrode 85 is formed on the back surface of the semiconductor substrate 10. However, the present invention can also be used in a so-called lateral MOSFET, such as a RESURF (Reduced SURface Field) MOSFET in which the drain electrode 85 is formed on the surface of the drift layer 20. Furthermore, the silicon carbide semiconductor device may be an insulated gate bipolar transistor (IGBT) in which the SBD is incorporated. The present invention can also be applied to a MOSFET or IGBT having a superjunction structure in which the SBD is incorporated.

Embodiment 5.
In the present embodiment, the silicon carbide semiconductor device according to the above-described first to fourth embodiments is applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, a case in which the present disclosure is applied to a three-phase inverter will be described below as a fifth embodiment.

Figure 18 is a block diagram showing the configuration of a power conversion system to which the power conversion device of this embodiment is applied.

The power conversion system shown in FIG. 18 is composed of a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source and supplies DC power to the power conversion device 200. The power source 100 can be composed of various things, for example, a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit connected to an AC system or an AC/DC converter. The power source 100 may also be composed of a DC/DC converter that converts the DC power output from the DC system into a specified power.

The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. As shown in Fig. 30 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202.
The drive circuit 202 controls each normally-off switching element to be turned off by setting the gate electrode voltage and the source electrode voltage to the same potential.

The load 300 is a three-phase motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific use, but is a motor mounted on various electrical devices, and is used, for example, as a motor for hybrid cars, electric cars, railroad cars, elevators, or air conditioning equipment.

The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (not shown), and converts the DC power supplied from the power source 100 into AC power by switching the switching elements, and supplies the AC power to the load 300. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full bridge circuit, and can be configured from six switching elements and six freewheel diodes connected in reverse parallel to each switching element. A silicon carbide semiconductor device manufactured by the manufacturing method of a silicon carbide semiconductor device according to any one of the above-mentioned embodiments 1 to 3 is applied to each switching element of the main conversion circuit 201. The six switching elements are connected in series with two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203 described later, the drive circuit 202 outputs to the control electrodes of each switching element a drive signal for turning the switching element on and a drive signal for turning the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.

The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on time of the switching elements according to the voltage to be output. Then, the control circuit 203 outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state at each time point, and an off signal is output to the switching element that should be in the off state. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.
In the power conversion device of the present embodiment, the silicon carbide semiconductor devices of the first to fourth embodiments are applied as the switching elements of the main conversion circuit 201, thereby realizing a power conversion device with low loss and improved reliability of high-speed switching.

In the present embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and the present disclosure may be applied to a single-phase inverter when supplying power to a single-phase load. In addition, the present disclosure can also be applied to a DC/DC converter or an AC/DC converter when supplying power to a DC load or the like.

Furthermore, the power conversion device to which the present disclosure is applied is not limited to the case where the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine or laser processing machine, or an induction heating cooker or a contactless power supply system, and can even be used as a power conditioner for a solar power generation system or a power storage system, etc.

10 semiconductor substrate, 20 drift layer, 30 body region, 31 first protection region, 32 second protection region, 33 first connection region, 34 second connection region, 35 contact region, 40 source region, 50 gate insulating film, 55 interlayer insulating film, 60 gate electrode, 70 ohmic electrode, 71 reaction layer, 80 source electrode, 81 Schottky electrode, 82 drain electrode, 91 gate trench, 92 Schottky trench, 100 power supply, 200 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 300 load.

Claims (7)

a drift layer made of first conductivity type silicon carbide formed on a first main surface of a semiconductor substrate made of first conductivity type silicon carbide;
a body region made of second conductivity type silicon carbide formed on the drift layer;
a source region made of silicon carbide of a first conductivity type formed on at least a portion of the body region;
a gate trench passing through the source region and the body region to reach the drift layer;
a gate electrode formed in the gate trench so as to face the body region via a gate insulating film;
a Schottky trench formed so that a lower end is located at least within the drift layer;
a Schottky electrode mainly composed of Ti formed in the Schottky trench;
a reaction layer formed between the Schottky electrode and the drift layer in contact with a side surface of the Schottky trench, the reaction layer being made of TiSi in which an atomic composition ratio of Ti to Si is 0.5 or more and an atomic composition concentration of oxygen is 5% or less . The silicon carbide semiconductor device according to claim 1 , wherein the reaction layer has a thickness of 1 nm or more. the semiconductor substrate is silicon carbide having a 4H polytype with the first main surface inclined from a (0001) plane by 1° or more in a <11-20>direction;
3. The silicon carbide semiconductor device according to claim 1, wherein the Schottky trenches are formed in a striped shape along a <11-20> direction. 4 . The silicon carbide semiconductor device according to claim 1 , wherein an angle that a sidewall in a longitudinal direction of the Schottky trench forms with the first main surface is in the range of 80 degrees or more and 90 degrees or less. the Schottky trench is formed through the body region;
The silicon carbide semiconductor device according to claim 1 , further comprising an ohmic electrode made of NiSi formed in a region where the Schottky trench contacts the body region. forming a drift layer made of first conductivity type silicon carbide on a first main surface of a semiconductor substrate made of first conductivity type silicon carbide;
forming a body region made of second conductivity type silicon carbide on the drift layer;
forming a source region made of silicon carbide of a first conductivity type on at least a portion of the body region;
forming a gate trench penetrating the source region and the body region to reach the drift layer;
forming a gate electrode in the gate trench so as to face the body region via a gate insulating film;
forming a Schottky trench having a lower end within at least the drift layer;
depositing a Schottky electrode mainly made of Ti inside the Schottky trench;
and increasing the temperature while the Schottky electrode is deposited, and then performing a heat treatment at a temperature of 400° C. or more and 600° C. or less to form a reaction layer made of TiSi so that the atomic composition concentration of oxygen is 5% or less . A main conversion circuit having the silicon carbide semiconductor device according to any one of claims 1 to 5, which converts input power and outputs the converted power;
a drive circuit that turns off the silicon carbide semiconductor device by making a voltage of a gate electrode of the silicon carbide semiconductor device the same as a voltage of a source electrode of the silicon carbide semiconductor device, and outputs a drive signal to the silicon carbide semiconductor device to drive the silicon carbide semiconductor device;
a control circuit that outputs a control signal to the drive circuit to control the drive circuit;
A power conversion device comprising:

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