JP7496245B2 - Gaming Machines - Google Patents

Description

The present invention relates to gaming machines such as pachinko machines and slot machines.

As a gaming machine of this type, one that has been proposed is capable of executing a basic process that is repeatedly executed for each unit of play, and an interrupt process that interrupts the basic process at regular time intervals to perform processing (see, for example, Patent Document 1).

JP 2020-39538 A

As with the gaming machine described in Patent Document 1, there is room for improvement in terms of data usage in controlling the switching of programs being executed.

The present invention aims to provide an amusement machine with improved control over switching between executed programs.

The gaming machine of claim 1 comprises:
In a gaming machine for playing a game,
A program execution means for executing a program using a plurality of registers,
The programs include a first program and a second program that is called and executed by the first program,
the plurality of registers include a first register group of registers consisting of a plurality of types of registers, and a second register group including a plurality of types of registers identical to the plurality of types of registers included in the first register group;
When executing the first program, a register belonging to the first register group is used;
When executing the second program, a register belonging to the second register group is used;
the first program includes a first basic program and a first interrupt program that is executed by interrupting execution of the first basic program,
the second program includes a second basic program called from the first basic program and a second interrupt program called from the first interrupt program,
when executing the first basic program, both of the first type registers and the second type registers included in the first register group are used, whereas when executing the second basic program, only the first type registers of the first type registers and the second type registers included in the second register group are used;
When the first interrupt program is executed, both of the third type registers and the fourth type registers included in the first register group are used, whereas when the second interrupt program is executed, only the third type registers of the third type registers and the fourth type registers included in the second register group are used.
It is characterized by the following.
According to this feature, when the second program is executed, the number of registers used is smaller than when the first program is executed, so that it is possible to prevent the second program from using erroneous data.

The present invention may have only the invention-specific matters described in the claims of the present invention, or may have the invention-specific matters described in the claims of the present invention as well as configurations other than the invention-specific matters.

1 is a front view of a slot machine according to an embodiment of the present invention; FIG. 2 is a block diagram showing the configuration of a slot machine. FIG. 4 is a diagram showing a memory map of a ROM and a RAM of a main control unit. FIG. 13 is a diagram showing the relationship between an internal capacity area and an external capacity area. FIG. 2 is a diagram for explaining a register; FIG. 2 is a diagram for explaining the correspondence between various processes and each register. FIG. 2 is a diagram for explaining the correspondence between basic processes and each register. 11 is a diagram for explaining the correspondence between interrupt processing and each register; FIG. FIG. 13 is a diagram for explaining a modified example of a register. 13 is a diagram for explaining the correspondence between in-capacity processing, out-capacity processing, and a shared register in a modified example of the register. FIG.

The following describes the form for implementing the gaming machine according to the present invention based on the examples.

[Form 1]
The gaming machine of form 1-1 is
In a gaming machine (slot machine 1) for playing games,
A program execution unit (main control unit 41) is provided for executing a program using a plurality of registers;
Among the programs, the specific program (interrupt processing) is composed of a main program (main routine (interrupt)) and a subprogram (subroutine (interrupt)) that is called and executed from the main program,
A specific register (IY register) among the plurality of registers is used in the subprogram (subroutine (interrupt)) and is not used in the main program (main routine (interrupt)).
According to this feature, the specific program is composed of a main program and a sub-program that is called and executed from the main program, and a specified register among the multiple registers is used by the sub-program and not by the main program, thereby preventing confusion of data stored in the specified register between the main program and the sub-program.

The gaming machine of aspect 1-2 is the gaming machine according to aspect 1-1,
The subprogram (subroutine (interrupt)) includes a plurality of types of subprograms,
The predetermined register (IY register) is characterized in that it is used in any one of the plurality of types of subprograms.
According to this feature, it is possible to prevent data stored in a predetermined register from being mixed up between the main program and one of the multiple types of subprograms in which the predetermined register is used.

The gaming machine of form 1-3 is,
In a gaming machine (slot machine 1) for playing games,
A program execution unit (main control unit 41) is provided for executing a program using a plurality of registers;
Among the programs, the specific program (interrupt processing) is composed of a main program (main routine (interrupt)) and a subprogram (subroutine (interrupt)) that is called and executed from the main program,
Among the plurality of registers, a specific register (D'E' register) is used in the main program (main routine (interrupt)) and is not used in the subprogram (subroutine (interrupt)).
According to this feature, the specific program is composed of a main program and a sub-program that is called and executed from the main program, and among the multiple registers, the specific register is used by the main program and not by the sub-program, thereby preventing confusion of data stored in the specific register between the main program and the sub-program.

The gaming machine of aspect 1-4 is the gaming machine according to aspect 1-3,
The subprogram (subroutine (interrupt)) includes a plurality of types of subprograms,
The special register (D'E' register) is characterized in that it is not used in any of the plurality of types of subprograms.
According to this feature, it is possible to prevent data stored in the specific register from being mixed up between the main program and any type of subprogram.

The gaming machine of aspect 1-5 is a gaming machine according to any one of aspects 1-1 to 1-4,
The specific program is characterized in that it is an interrupt program (interrupt process) that is executed when an interrupt occurs.
According to this feature, it is possible to prevent data stored in registers between the main program and the subprogram from becoming mixed up during execution of the interrupt program.

[Form 2]
The gaming machine of form 2-1 is,
In a gaming machine (slot machine 1) for playing games,
A program execution unit (main control unit 41) is provided for executing a program using a plurality of registers;
The program includes a basic program (basic processing) and an interrupt program (interrupt processing) that is executed by interrupting the execution of the basic program,
When executing the basic program (basic process), a first register (table register) is used,
A register to be used when executing the interrupt program (interrupt process) is switched from the first register (front register) to the second register (back register),
A register to be used when terminating the interrupt program (interrupt process) is returned from the second register (back register) to the first register (front register);
the plurality of registers include a special register (IX register) that can be used when executing the basic program (basic processing) and when executing the interrupt program (interrupt processing) in addition to the first register (front register) and the second register (back register),
The special register (IX register) is characterized in that it is used in the basic program (basic processing) and is not used in the interrupt program (interrupt processing).
According to this feature, the basic program uses a first register, while during execution of an interrupt program that interrupts the basic program, the register used switches from the first register to the second register, and the multiple registers include a special register that can be used when executing both the basic program and the interrupt program, separate from the first and second registers; however, since the special register is used by the basic program and not by the interrupt program, it is possible to prevent confusion between the data stored in the special registers between the basic program and the interrupt program.

The gaming machine according to aspect 2-2 is the gaming machine according to aspect 2-1,
the plurality of registers include a plurality of shared registers (IX register, IY register) that can be used when executing the basic program (basic processing) and when executing the interrupt program (interrupt processing) separately from the first register (front register) and the second register (back register),
The present invention is characterized in that none of the multiple shared registers (IX register, IY register), including the special register (IX register), is used in the interrupt program (interrupt process).
According to this feature, the multiple registers include multiple shared registers that can be used when executing both the basic program and the interrupt program, separate from the first and second registers, but none of the multiple shared registers, including the special registers, are used in the interrupt program, thereby preventing confusion of data stored in the shared registers, including the special registers, between the basic program and the interrupt program.

A gaming machine according to aspect 2-3 is a gaming machine according to aspect 2-1,
the plurality of registers include a plurality of shared registers (IX register, IY register) that can be used when executing the basic program (basic processing) and when executing the interrupt program (interrupt processing) in addition to the first register (front register) and the second register (back register),
Among the plurality of shared registers (IX register, IY register), at least the special register (IX register) is not used in the second program (interrupt processing).
According to this feature, the multiple registers include multiple shared registers that can be used when executing both the basic program and the interrupt program, separate from the first and second registers, but at least the special registers among the multiple shared registers are not used in the interrupt program, thereby preventing confusion of data stored in at least the special registers between the basic program and the interrupt program.

The gaming machine of form 2-4 is,
In a gaming machine (slot machine 1) for playing games,
A program execution unit (main control unit 41) is provided for executing a program using a plurality of registers;
The program includes a basic program (basic processing) and an interrupt program (interrupt processing) that is executed by interrupting the execution of the basic program,
When executing the basic program (basic process), a first register (table register) is used,
A register to be used when executing the interrupt program (interrupt process) is switched from the first register (front register) to the second register (back register),
A register to be used when terminating the interrupt program (interrupt process) is returned from the second register (back register) to the first register (front register);
the plurality of registers include a special register (IY register) that can be used when executing the basic program (basic processing) and when executing the interrupt program (interrupt processing) in addition to the first register (front register) and the second register (back register),
The special register (IY register) is characterized in that it is used in the interrupt program (interrupt processing) and is not used in the basic program (basic processing).
According to this feature, the basic program uses a first register, while during execution of an interrupt program that interrupts the basic program, the register used switches from the first register to the second register, and the multiple registers include a special register that can be used when executing both the basic program and the interrupt program, separate from the first and second registers; however, since the special register is used by the interrupt program and not by the basic program, it is possible to prevent confusion between the data stored in the special registers between the basic program and the interrupt program.

A gaming machine according to aspect 2-5 is a gaming machine according to aspect 2-4,
the plurality of registers include a plurality of shared registers (IX register, IY register) that can be used when executing the basic program (basic processing) and when executing the interrupt program (interrupt processing) separately from the first register (front register) and the second register (back register),
Among the plurality of shared registers (IX register, IY register), none of the shared registers including the special register (IY register) is used in the basic program (basic processing).
According to this feature, the multiple registers include multiple shared registers that can be used when executing both the basic program and the interrupt program, separate from the first and second registers, but none of the multiple shared registers, including the special registers, are used in the basic program, thereby preventing confusion of data stored in the shared registers, including the special registers, between the basic program and the interrupt program.

A gaming machine according to aspect 2-6 is a gaming machine according to aspect 2-4,
the plurality of registers include a plurality of shared registers (IX register, IY register) that can be used when executing the basic program (basic processing) and when executing the interrupt program (interrupt processing) in addition to the first register (front register) and the second register (back register),
Of the plurality of shared registers (IX register, IY register), at least the special register (IY register) is not used in the basic program (basic processing).
According to this feature, the multiple registers include multiple shared registers that can be used when executing both the basic program and the interrupt program, separate from the first and second registers, but at least the special registers among the multiple shared registers are not used in the basic program, thereby preventing confusion of data stored in at least the special registers between the basic program and the interrupt program.

A gaming machine according to any one of the aspects 2-1 to 2-6,
A value is set in the second register (back register) when the interrupt program (interrupt process) is executed.
According to this feature, when an interrupt program is executed, a new value is set instead of the value originally stored in the second register, thereby preventing the interrupt program from being executed with an unintended value.

[Form 3]
The gaming machine of form 3-1 is,
In a gaming machine (slot machine 1) for playing games,
A program execution unit (main control unit 41) is provided for executing a program using a plurality of registers;
The programs include a first program (a program within the capacity (a processing within the capacity)) and a second program (a program outside the capacity (a processing outside the capacity)) that is called and executed by the first program,
When the second program (out-of-capacity program (out-of-capacity processing)) is executed, data of the plurality of registers is saved, and when the second program (out-of-capacity program (out-of-capacity processing)) is terminated, the saved data of the plurality of registers is restored;
When the first program (in-memory program (in-memory processing)) is executed, a specific number of the plurality of registers are used;
When executing the second program (out-of-capacity program (out-of-capacity processing)), a number of registers among the plurality of registers that is less than the specific number (a portion of the registers used by the in-capacity program (in-capacity processing)) is used.
According to this feature, when the second program is executed, data in multiple registers is saved, and when the second program is terminated, the saved data in the multiple registers is restored; and since fewer registers are used when the second program is executed than when the first program is executed, it is possible to prevent the second program from using erroneous data.

The gaming machine of aspect 3-2 is the gaming machine according to aspect 3-1,
The first program (in-capacity program (in-capacity processing)) includes a first specific program (in-capacity processing (basic processing)) and a first predetermined program (in-capacity processing (interrupt processing)),
The second program (out-of-capacity program (out-of-capacity processing)) includes a second specific program (out-of-capacity processing (basic processing)) that is called from the first specific program (in-capacity processing (basic processing)) and executed, and a second predetermined program (out-of-capacity processing (interrupt processing)) that is called from the first predetermined program (in-capacity processing (interrupt processing)) and executed,
When the first specific program (in-capacity processing (basic processing)) is executed, a first specific number of registers among the plurality of registers are used;
When executing the second specific program (out-of-capacity processing (basic processing)), a number of registers among the plurality of registers that is less than the first specific number (a part of the registers used by the out-of-capacity processing (basic processing)) are used,
When the first predetermined program (interrupt processing) is executed, a second specific number of registers among the plurality of registers are used;
When the second specified program (out-of-capacity processing (interrupt processing)) is executed, a number of registers among the plurality of registers that is less than the second specific number (a portion of the registers used by the out-of-capacity processing (interrupt processing)) are used.
According to this feature, when the second specific program is executed, fewer registers are used than when the first specific program is executed, and when the second prescribed program is executed, fewer registers are used than when the first prescribed program is executed, thereby preventing the use of erroneous data by the second specific program and the second prescribed program.

[Form 4]
The gaming machine of form 4-1 is
In a gaming machine (slot machine 1) for playing games,
A program execution means (main control unit 41) for executing a program;
A stack area for saving data;
Equipped with
The programs include a first program (a program within the capacity (a processing within the capacity)) and a second program (a program outside the capacity (a processing outside the capacity)) that is called and executed by the first program,
the stack area includes a first stack area (internal stack area) for saving data by the first program (internal program (internal processing)), and a second stack area (external stack area) for saving data by the second program (external program (external processing));
switching a stack pointer indicating a data save address from the first stack area (internal stack area) to the second stack area (external stack area) when executing the second program (outside program (outside processing)), and returning the stack pointer to the first stack area (internal stack area) when terminating the second program (outside program (outside processing));
When the second program (out-of-capacity program (out-of-capacity processing)) is terminated, all of the data that was saved in the second stack area (out-of-capacity stack area) during execution of the second program is restored.
According to this feature, when the second program is executed, the stack pointer is switched from the first stack area to the second stack area, and when the second program is terminated, the stack pointer is returned to the first stack area. Furthermore, when the second program is terminated, all data that was saved in the second stack area during execution of the second program is restored and then the stack pointer is returned to the first stack area. This prevents the second program from being executed further while data used in the second program that was previously executed remains saved, and prevents confusion between data used in the second program that was previously executed and data to be used in the second program that is currently executed.

The gaming machine of aspect 4-2 is the gaming machine according to aspect 4-1,
The second program (out-of-capacity program (out-of-capacity processing)) includes a plurality of types of second programs,
When the second program is terminated, regardless of the type of the second program, all data that was saved in the second stack area (extra-capacity stack area) during execution of the second program is restored.
According to this feature, when terminating the second program, regardless of the type of second program, all data saved in the second stack area during execution of the second program is restored and then the stack pointer is returned to the first stack area. Therefore, regardless of the type of second program, it is possible to prevent confusion between data used in the second program executed previously and data to be used in the second program executed currently.

An embodiment of a slot machine to which the present invention is applied will be described with reference to the drawings. As shown in FIG. 1, the slot machine 1 of this embodiment is composed of a housing 1a with an open front and a front door 1b pivotally supported on the side end of the housing 1a. Inside the slot machine 1, reels 2L, 2C, and 2R on which the same number of different types of mutually identifiable symbols are arranged in a predetermined order are arranged in a horizontal direction, and as shown in FIG. 1, three consecutive symbols among the symbols arranged on these reels 2L, 2C, and 2R are displayed in three rows, top, middle, and bottom, in a see-through window 3 provided in the approximate center of the front of the slot machine 1 so that they can be seen from the player's side.

In this embodiment, a configuration using three reels is exemplified, but a configuration using only one reel, a configuration using two reels, or a configuration using four or more reels may also be used. Also, in this embodiment, the variable display unit that variably displays the patterns is made up of reels 2L, 2C, and 2R, but the variable display unit may be something other than a reel, and may be configured, for example, to be capable of variably displaying the patterns by moving a belt having multiple patterns arranged on its outer periphery. Also, in this embodiment, the variable display unit is made up of physical reels, but the variable display unit may also be made up of an image display device such as a liquid crystal display.

On the front of the slot machine 1, as shown in FIG. 1, there are provided a medal insertion section 4 into which medals can be inserted, a medal payout outlet 9 from which medals are paid out, a MAXBET switch 6 which is operated to use credits (the number of medals stored as the gaming value owned by the player) to set the maximum bet within a range of a prescribed number of bets determined according to the game status, a settlement switch 10 which is operated to settle the medals stored as credits and the medals used to set the bet (return the medals used to set the credits and the bet), a start switch 7 which is operated to start the game, stop switches 8L, 8C, 8R which are operated to stop the rotation of reels 2L, 2C, 2R, respectively, and a performance switch 56 which is used for performance, all of which can be operated by the player.

On the front of the slot machine 1, as shown in FIG. 1, there is provided a game display unit 13 provided with a credit indicator 11 that displays the number of medals stored as credits, a game support indicator 12 that displays the number of medals paid out when a win occurs, an error code indicating the content of an error when an error occurs, operation information (navigation notification) corresponding to the operation mode of the stop switches 8L, 8C, and 8R, etc., a 1BET LED 14 that lights up to indicate that the bet number is set to 1, a 2BET LED 15 that lights up to indicate that the bet number is set to 2, a 3BET LED 16 that lights up to indicate that the bet number is set to 3, a start valid LED 18 that lights up to indicate that the start operation of the game by operating the start switch 7 is valid, a zone display LED 19 that lights up to indicate that the game zone is controlled to an advantageous zone, and a replay in progress LED 20 that lights up to indicate that a replay game is in progress.

Inside the MAXBET switch 6 is a BET switch valid LED 21 (see FIG. 2) that lights up to indicate that the operation to set the bet amount by operating the MAXBET switch 6 is valid, and inside the stop switches 8L, 8C, 8R are left, center, and right stop valid LEDs 22L, 22C, 22R (see FIG. 2) that light up to indicate that the operation to stop the reels by the corresponding stop switches 8L, 8C, 8R is valid.

Also, a liquid crystal display 51 capable of displaying images is provided on the front of the slot machine 1. The liquid crystal display 51 has a liquid crystal panel that is transparent when no voltage is applied to the liquid crystal element, and is provided so that the display area is located in front of the reels 2L, 2C, and 2R (on the player's side) of the front door 1b. Each of the reels 2L, 2C, and 2R on the rear side of the liquid crystal display 51 can be seen from the player's side through the transparent area of the display area of the liquid crystal display 51 that corresponds to the see-through window 3 and the see-through window 3.

On the inside of the front door 1b of the slot machine 1, there are provided a reset switch 23 that detects a reset operation to release an error state from outside the slot machine 1 by operating a specific key, a setting value display 24 that displays the setting value at that time when the setting value is being changed or checked, a door open detection switch 25 that detects the open state of the front door 1b, a flow path switching solenoid 30 that selectively switches the flow path of medals inserted from the medal insertion portion 4 to either the hopper tank side or the medal payout outlet 9 side provided inside the slot machine 1, and a medal selector 29 having inserted medal sensors 31a to 31c that detect medals inserted from the medal insertion portion 4 and flowing down to the hopper tank side.

Inside the slot machine 1, there is also provided a reel unit 34 for spinning and stopping the aforementioned reels 2L, 2C, and 2R in response to a control signal from the main control unit 41, and a hopper unit 35 for paying out medals from the medal payout opening 9 in response to a control signal from the main control unit 41.

Inside the slot machine 1, there are provided a setting key switch 37 for switching between a setting change state and a setting confirmation state, a reset/setting switch 38 which functions as a reset switch for releasing an error state under normal circumstances and functions as a setting switch for changing the set value of the winning probability (ball payout rate) of the internal lottery described below in the setting change state, and a power switch 39 which is operated when turning the power on and off.

With the gaming control board 40 attached to a predetermined position inside the cabinet 1a inside the slot machine 1, a gaming machine information display 50 consisting of a four-digit seven-segment display is disposed below the front side (player side) of the gaming control board 40 (not shown). With the gaming control board 40 sealed in the board case, the display contents of the gaming machine information display 50 can be seen from outside the board case, and the gaming machine information based on the playing history of the slot machine 1, which is compiled by the main control unit 41 and displayed on the gaming machine information display 50, can be recognized by store clerks and the like.

As shown in FIG. 2, the slot machine 1 is provided with a game control board 40 and a presentation control board 90. The game is controlled by the game control board 40, and the presentation control board 90 controls the presentation according to the game status.

The game control board 40 is connected to the aforementioned MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R, settlement switch 10, reset switch 23, inserted medal sensors 31a-31c, reel sensor (not shown) of the reel unit 34, payout sensor and full sensor (not shown) of the hopper unit 35, setting key switch 37, and reset/setting switch 38, and detection signals from these connected switches are input.

The game control board 40 is also connected to the credit indicator 11, game auxiliary indicator 12, 1-3 BET LEDs 14-16, start enable LED 18, section indicator LED 19, replay in progress LED 20, BET switch enable LED 21, left, middle, right stop enable LEDs 22L, 22C, 22R, setting value indicator 24, flow path switching solenoid 30, reel unit 34, and hopper unit 35. These electrical components and the game machine information indicator 50 mounted on the game control board 40 are driven under the control of the main control unit 41 mounted on the game control board 40 and described below.

The game control board 40 is also equipped with a main control unit 41 that controls the game. The main control unit 41 includes a CPU 41a for performing calculations, a ROM 41b in which programs and the like are stored, and a RAM 41c in which work data is temporarily stored, and performs various controls according to the programs stored in the ROM 41b.

The CPU 41a executes the instructions at the addresses specified by the program counter in the programs stored in the ROM 41b. The program counter is incremented and updated each time an instruction is completed, so that the instructions at the addresses with the smallest values in the programs stored in the ROM 41b are executed in order.

The main control unit 41 includes a number of registers used by the CPU 41a to perform calculations. The registers include an accumulator register (A register), a flag register (F register), general-purpose registers (B register, C register, D register, E register, H register, L register), an index register (IX register, IY register), an interrupt register (I register), a refresh register (R register), a stack pointer register (SP register), a program counter register (PC register), and a transmission register. Among these registers, the accumulator register, the flag register, and the general-purpose register each include a front register and a back register that are configured to form a pair (hereinafter, the front register and the back register may be simply referred to as registers). The CPU 41a can update the value of a specified register or update a value (data) stored in a memory area of the RAM 41c specified by the value (address) of a specified register by executing various instructions, such as calculation instructions and read instructions, included in the program.

In addition, the flag register, one of the registers provided in the main control unit 41, is configured so that its state changes to indicate the result of an operation performed by an instruction executed by the CPU 41a, and the change in the state of the flag register can be used to cause the CPU 41a to perform processing according to the result of an operation performed by the previous instruction.

The flag register is also made up of multiple bits (8 bits in this embodiment), including a first bit (hereinafter sometimes referred to as a zero flag) and a second bit (hereinafter sometimes referred to as a carry flag) whose state can be changed depending on the result of the calculation instruction executed by the CPU 41a in order to reduce the processing load on the CPU 41a.

The main control unit 41 also transmits various commands to the sub-control unit 91. Commands transmitted from the main control unit 41 to the sub-control unit 91 are sent in only one direction, and no commands are sent from the sub-control unit 91 to the main control unit 41.

The main control unit 41 repeatedly loops processing according to the control state until the detection state of the various switches connected to the game control board 40 changes, and executes basic processing that transitions stepwise according to changes in the detection state of the various switches. The main control unit 41 also interrupts the basic processing and executes interrupt processing every time a timer interrupt occurs (about 0.56 milliseconds in this embodiment). The execution interval of the interrupt processing is set to a time longer than the combined time of the processing repeated according to the control state in the basic processing and the execution time of the interrupt processing, so that at least one cycle of the processing repeated according to the control state is always completed between the current and next interrupt processing.

The main control unit 41 can also save the values of the registers in the main control unit 41 by storing them in a specified order in a stack area of RAM 41c indicated by the stack pointer SP, and can restore the state of the corresponding registers to the state when they were saved by sequentially reading the register values saved in the stack area of RAM 41c from the stack area in the reverse order to when they were saved and setting them in the registers corresponding to that order.

The performance control board 90 is connected to the aforementioned performance switch 56, and its detection signal is input. In addition, the performance control board 90 is connected to performance devices such as the aforementioned LCD display 51, a speaker capable of outputting sound, and performance LEDs 57 used for performance and visible to the player, and the output state of these performance devices can be controlled by a sub-controller 91 mounted on the performance control board 90. The sub-controller 91 receives commands sent from the main control unit 41 and detection signals from the performance switch 56, and performs various controls for producing performances.

The slot machine 1 of this embodiment is configured so that the medal payout rate changes according to a set value. More specifically, the medal payout rate is changed by using the winning probability according to the set value in a lottery that affects the player's advantage, such as an internal lottery or an AT lottery. The set value has six levels, from 1 to 6, with 6 being the highest payout rate, and the payout rate decreasing as the value decreases in the order of 5, 4, 3, 2, and 1. In other words, when 6 is set as the set value, the player has the highest advantage, and the advantage decreases stepwise as the value decreases in the order of 5, 4, 3, 2, and 1.

To change the set value, it is necessary to turn on the power switch 39 of the slot machine 1 after turning on the setting key switch 37. When the power is turned on with the setting key switch 37 in the ON state, the set value read from the RAM 41c is displayed as the display value on the setting value display 24, and the setting state is changed so that the set value can be changed by operating the reset/set switch 38. When the reset/set switch 38 is operated in the setting change state, the display value displayed on the setting value display 24 is updated by one (when the reset/set switch 38 is operated again from the set value 6, it returns to the set value 1). When the start switch 7 is operated, the display value is confirmed as the set value. When the setting key switch 37 is turned off, the confirmed display value (set value) is stored in the RAM 41c of the main control unit 41, and the state is changed so that the game can proceed.

The setting key switch 37 and the reset/setting switch 38 are provided inside the slot machine 1 and cannot be operated unless the front door 1b, which can be opened by a specific key operation, is opened, and can only be operated by staff of the game arcade where the slot machine 1 is installed who possess a specific key. In particular, the setting key switch 37 requires further key operation, so that only staff of the game arcade who possess a key for operating the setting key switch 37 can operate it. The reset switch 23 does not require the front door 1b to be opened, but requires key operation using a specific key, so that only staff who possess the specific key can operate it. The reset/setting switch 38 also functions as a reset switch for canceling an error state under normal circumstances.

In the slot machine 1 of this embodiment, the main control unit 41 performs a power outage determination process to determine whether or not a voltage drop has been detected during interrupt processing, and if it is determined in the power outage determination process that a voltage drop has been detected, it executes a power outage process (main) to set data for determining whether or not the data in RAM 41c is normal at the next recovery.

The main control unit 41 is capable of restoring the processing state of the main control unit 41 to the state before the power outage based on the data stored in the RAM 41c, provided that the data in the RAM 41c is normal at the time of startup. On the other hand, if the data in the RAM 41c is not normal at startup, it determines that there is a RAM abnormality, sets an error flag indicating a RAM abnormality in the RAM 41c, and controls the RAM to an abnormal RAM state, disabling game progress. The RAM abnormal error state is released by transitioning to a setting change state and setting a new setting value, allowing game progress to be resumed.

In the slot machine 1 of this embodiment, when the main control unit 41 detects an abnormality during gameplay, it sets an error flag in the RAM 41c indicating the type of abnormality detected, and controls the state to a general error state, disabling gameplay. The general error state is released by a reset operation using the reset switch 23 or the reset/setting switch 38, allowing gameplay to continue. In the following, when there is no need to distinguish between the RAM abnormality error state and the general error state, they will simply be referred to as the error state.

When playing a game on the slot machine 1 of this embodiment, first, medals are inserted into the medal insertion section 4, or the MAXBET switch 6 is operated to set the number of bets using credits. When a specified number of bets determined according to the game state is set, a predetermined winning line LN (see FIG. 1, in this embodiment, it is set in the middle of the reels 2L, 2C, and 2R, i.e., across the symbols arranged horizontally in the middle row) becomes valid, and the operation of the start switch 7 becomes valid, that is, the game can be started. Note that if medals are inserted in excess of the maximum number of medals that corresponds to the game state, the amount is added to the credits. Note that, although only one winning line is applied in this embodiment, multiple winning lines may be applied.

In addition, in this embodiment, in order to make it easier to recognize that a combination of symbols that constitute a win has been lined up on the winning line LN, invalid lines LM1-6 are set up separately from the winning line LN. The invalid lines LM1-6 are not used to determine whether or not a win has been made, but rather, when a combination of symbols that constitute a win has been lined up on the winning line LN, a combination of suggestive symbols that suggests a win (for example, Bell a-Bell a-Bell a) is lined up on one of the invalid lines LM1-6, making it easier to recognize that a combination of symbols that constitute a win has been lined up on the winning line LN. In this embodiment, as shown in FIG. 1, six types of invalid lines are defined as invalid lines: an invalid line LM1 set across the symbols arranged horizontally on the upper row of reels 2L, 2C, and 2R, i.e., across the symbols arranged horizontally on the lower row of reels 2L, 2C, and 2R, i.e., across the symbols arranged horizontally on the lower row; an invalid line LM3 set across the symbols arranged downward to the right on the upper row of reel 2L, the middle row of reel 2C, and the lower row of reel 2R, i.e., across the symbols arranged upward to the right on the lower row of reel 2L, the middle row of reel 2C, and the upper row of reel 2R, i.e., across the symbols arranged in a small V shape on the upper row of reel 2L, the middle row of reel 2C, and the upper row of reel 2R.

When the start switch 7 is operated in a state where the game can be started, each of the reels 2L, 2C, and 2R rotates, and the symbols on each of the reels 2L, 2C, and 2R change continuously. When any of the stop switches 8L, 8C, and 8R are operated while the reels 2L, 2C, and 2R are rotating, stop control is performed on the corresponding reel 2L, 2C, and 2R, the rotation of that reel is stopped, and the symbol on that reel is derived and displayed as a display result in the see-through window 3.

In the stop control, control is performed to stop the rotation of reels 2L, 2C, and 2R corresponding to the operation within the maximum stop delay time (190 ms (milliseconds) in this embodiment) from when each stop switch is operated, and up to four frames of symbols can be pulled in before the maximum stop delay time (190 ms) has elapsed. In other words, in the stop control, it is possible to select one symbol from the symbol displayed when stop switches 8L, 8C, and 8R are operated and the symbols four frames ahead of that, for a total of five frames (pulling-in range), and lead it to reels 2L, 2C, and 2R.

In this way, in the stop control, when the stop switches 8L, 8C, and 8R corresponding to each reel 2L, 2C, and 2R are operated to stop the rotation, if the symbol constituting the winning combination that has been selected in the internal lottery described below is within a reel-in range of four frames from the symbol when the stop switch is operated, the symbol is reeled onto the winning line LN, and the rotation of the reel for which the stop switch is operated is stopped. On the other hand, if the symbol constituting the winning combination that has been selected in the internal lottery is not within the reel-in range, the symbol that does not constitute any winning combination is reeled onto the winning line LN, so that the symbol constituting the winning combination that has not been selected in the internal lottery does not stop on the winning line LN, and the rotation of the reel for which the stop switch is operated is stopped.

[Main control unit memory area and programs]
The main control unit 41 includes a ROM 41b having a memory area for storing predetermined programs and data, and a RAM 41c for temporarily storing data.

Figure 3 is an address map of the program/data area in ROM 41b and the available area in RAM 41c. As shown in Figure 3(a), the program/data area in ROM 41b includes an in-capacity program area in which in-capacity programs for controlling game progress are stored, an in-capacity data area in which in-capacity data used by the in-capacity programs is stored, unused area 1, an out-of-capacity program area in which out-of-capacity programs for controlling game progress that is not directly related to game progress, such as detecting errors, creating test signals, and displaying gaming machine information such as payout rates, are stored, an out-of-capacity data area in which out-of-capacity data used by the out-of-capacity programs is stored, and unused area 2.

The progression of a game refers to the progression of a series of processes that make up a game. In the case of a slot machine, this refers to the progression of the stages of setting the bet amount and making it possible to start the game, starting the game and spinning the reels, stopping the reels to derive the display result, and awarding value such as medals according to the display result. In the case of a pachinko game machine, this refers to the progression of the stages of determining whether a starting win has occurred, starting the variable display, stopping the variable display, and changing the game state.

In the following, processing performed by in-capacity programs may be referred to as in-capacity processing, and processing performed by out-of-capacity programs may be referred to as in-capacity processing.

As shown in FIG. 3(b), the available area of RAM 41c includes an internal RAM area used as work by internal programs, an external RAM area used as work by external programs, and an unused area 4. The internal RAM area includes internal work, an unused area 3, and an internal stack area, and the external RAM area includes external work and an external stack area. Note that in this embodiment, the internal stack area and the external stack area are each provided in separate areas, but it is also possible to provide a single stack area shared by internal and external programs.

The internal stack area is an area where the internal program temporarily saves data, and when the internal program saves data, the data is temporarily stored in the area at the address indicated by the internal stack pointer.

The off-capacity stack area is an area where off-capacity programs temporarily save data, and when off-capacity programs save data, the data is temporarily stored in the area at the address indicated by the off-capacity stack pointer.

In addition, the unused area 3 is an area that is not used by either in-capacity programs or out-of-capacity programs, and is an area that is surplus to the in-capacity RAM area of a predetermined capacity.

In addition, the unused area 4 is an area of 16 bytes or more that is not used by either the internal or external programs. Because the internal RAM area and the external RAM area are allocated to non-contiguous areas sandwiched between the unused area 4, the internal RAM area used by the internal programs related to the progress of the game and the external RAM area used by the external programs not related to the progress of the game can be easily identified based on the difference in memory area.

In the following, the internal program area, internal data area, and internal RAM area may be collectively referred to as the internal area, and the external program area, external data area, and external RAM area may be collectively referred to as the external area.

[Relationship between the capacity area and the non-capacity area]
As shown in Figure 4, the CPU 41a of the main control unit 41 calls an out-of-capacity program during processing based on a program within capacity, executes processing based on the out-of-capacity program, and returns to processing based on the program within capacity after the processing based on the out-of-capacity program is completed.

As shown in FIG. 4, in principle, when the CPU 41a executes processing based on an internal program, it references the internal data in the internal data area to execute the processing based on the internal program, and can use the internal RAM area as a work area to refer to and update the contents of the internal RAM area. In addition, in principle, when the CPU 41a executes processing based on an external program, it references the external data in the external data area to execute the processing based on the external program, and can use the external RAM area as a work area to refer to and update the contents of the external RAM area.

In addition, when executing processing based on an internal program, the CPU 41a does not update the external RAM area, but is able to refer to the external RAM area, and when executing processing based on an external program, the CPU 41a does not update the internal RAM area, but is able to refer to the internal RAM area.

[Register]
The main control unit 41 has a plurality of registers used by the main CPU 41a to perform calculations. The plurality of registers mainly includes a front register, a back register, and a common register. The front register and the back register are in a paired relationship, and when the front register is used, the back register cannot be used, and when the back register is used, the front register cannot be used. Furthermore, the back register can be used by inverting the front register, and the front register can be used by inverting the back register. Furthermore, the common register can be used when both the front register and the back register are used.

The table registers include the A register, F register, general-purpose registers (B register, C register (B register and C register are collectively called BC register), D register, E register (D register and E register are collectively called DE register), H register, L register (H register and L register are collectively called HL register)), and Q register. The A register and general-purpose registers store values used in calculations, the F register stores flags according to the results of calculations, and the Q register stores the upper address when specifying an address in a special instruction.

The back registers include the A' register, F' register, and general-purpose registers (B' register, C' register (B' register and C' register are collectively referred to as B'C' register), D' register, E' register (D' register and E' register are collectively referred to as D'E' register), H' register, and L' register (H' register and L' register are collectively referred to as H'L' register)) which are paired with the front registers A register, F register, and general-purpose register. The A' register and general-purpose registers store values used in calculations, and the F' register stores flags corresponding to the calculation results.

The common registers include the I register, R register, IX register, IY register, SP register, and PC register. The I register stores the upper address of the address (interrupt vector) to jump to when an interrupt occurs, the R register stores a value that counts the timing to refresh the memory, the IX register and IY register store values used in calculations, the SP register stores the value of the stack pointer that specifies the stack area, and the PC register stores the value of the program counter that indicates the address of the program being executed.

[Various processes executed by the main control unit]
Next, there will be described various processes executed by the main control unit 41. As shown in Fig. 6, the main control unit 41 can execute basic processes and interrupt processes as processes for controlling the slot machine 1.

The basic process is a process that repeatedly loops processing according to the control state until the control state changes, and is composed of a main routine (basic) and several types of subroutines (basic) that are called from the main routine (basic).

The main routine (basic) is a process that gradually transitions between multiple control states as the game progresses, and it is possible to call one of multiple types of subroutines (basic) as the program progresses.

A subroutine (basic) starts by being called by the main routine (basic), and when the subroutine (basic) ends, it returns to the caller of the main routine (basic).

As shown in FIG. 7, the basic processing is composed of in-capacity processing (basic) by in-capacity programs and out-capacity processing (basic) by out-capacity programs.

Depending on the progress of the program, the in-capacity process (basic) can call one of several types of out-of-capacity process (basic).

Out-of-capacity processing (basic) starts when it is called by in-capacity processing (basic), and returns to the caller of in-capacity processing (basic) when the out-of-capacity processing (basic) ends.

Out-of-capacity processing (basic) consists of a main routine (out-of-capacity, basic) and several types of subroutines (out-of-capacity, basic) that are called from the main routine (out-of-capacity, basic).

The main routine (outside capacity/basic) can call any of several types of subroutines (outside capacity/basic) depending on the progress of the program.

The subroutine (out of capacity, basic) starts by being called by the main routine (out of capacity, basic), and returns to the caller of the main routine (out of capacity, basic) when the subroutine (out of capacity, basic) ends.

Interrupt processing is executed by interrupting the basic processing whenever a timer interrupt occurs, and returns to the interrupt source of the basic processing when the interrupt processing ends. It consists of a main routine (interrupt) and several types of subroutines (interrupts) called from the main routine (interrupt).

The main routine (interrupt) can call one of several types of subroutines (interrupts) depending on the progress of the program.

A subroutine (interrupt) starts by being called by the main routine (interrupt), and returns to the caller of the main routine (interrupt) when the subroutine (interrupt) ends.

As shown in FIG. 8, the interrupt processing is composed of in-capacity processing (interrupt) by an in-capacity program and out-capacity processing (interrupt) by an out-capacity program.

The internal processing (interrupt) can call one of several types of external processing (interrupt) depending on the progress of the program.

Out-of-capacity processing (interrupt) starts when it is called by in-capacity processing (interrupt), and returns to the caller of the in-capacity processing (interrupt) when the out-of-capacity processing (interrupt) ends.

Out-of-capacity processing (interrupt) consists of a main routine (out-of-capacity, interrupt) and several types of subroutines (out-of-capacity, interrupt) that are called from the main routine (out-of-capacity, interrupt).

The main routine (out of capacity/interrupt) can call one of several types of subroutines (out of capacity/interrupt) depending on the progress of the program.

The subroutine (out of capacity, interrupt) starts by being called by the main routine (out of capacity, interrupt), and returns to the caller of the main routine (out of capacity, interrupt) when the subroutine (out of capacity, interrupt) ends.

[Regarding registers used in basic processing and interrupt processing]
Next, a register used by the main control unit 41 when executing basic processing and interrupt processing will be described.

As shown in FIG. 6, when executing the main routine (basic) in the basic processing, the main control unit 41 executes various processes using the table registers and the common registers. In more detail, the main routine (basic) uses the A register, F register, BC register, DE register, HL register, and Q register, that is, all the registers included in the table registers. Also, although the main routine (basic) can use all the registers included in the common registers, it uses the I register, R register, IX register, SP register, and PC register, and does not use the IY register.

The main control unit 41 also uses the table registers and the common registers to execute various processes when executing a subroutine (basic) in the basic process. In more detail, the subroutine (basic) uses the A register, F register, BC register, DE register, HL register, and Q register, that is, all the registers included in the table registers. In addition, the subroutine (basic) can use all the registers included in the common registers, but of these, the I register, R register, IX register, SP register, and PC register are used, and the IY register is not used.

As shown in FIG. 6, when a timer interrupt occurs during execution of a basic process and the main control unit 41 interrupts the basic process being executed to start interrupt processing, it first switches the register to be used from the front register to the back register.

When executing the main routine (interrupt) in interrupt processing, the main control unit 41 executes various processes using the hidden registers and the shared registers. In detail, in the main routine (interrupt), the A' register, F' register, B'C' register, D'E' register, and H'L' register are used among the hidden registers, that is, all registers included in the hidden registers. Also, in the main routine (interrupt), all registers included in the shared registers can be used, but of these, the R register, SP register, and PC register are used, and the I register, IX register, and IY register are not used.

In addition, when the main control unit 41 switches the register to be used from the front register to the back register, the value of the back register used in the previous interrupt process is stored, but in the current interrupt process, the value of the back register used in the previous interrupt process is not used, and the necessary value is stored in the back register again.

The main control unit 41 also uses the hidden registers and the common registers to execute various processes when executing a subroutine (interrupt) in interrupt processing. In more detail, all registers included in the hidden registers can be used in a subroutine (interrupt), but of these, the A' register, F' register, B'C' register, and H'L' register are used, and the D'E' register is not used. Also, all registers included in the common registers can be used in a subroutine (interrupt), but of these, the R register, IY register, SP register, and PC register are used, and the I register and IX register are not used.

In addition, when the main routine (interrupt) in the interrupt process ends, the main control unit 41 switches the registers used from the back registers to the front registers, and returns to the basic process that was being executed when the timer interrupt occurred.

In this way, in this embodiment, the front register is used in the basic process, and the back register replaced by the front register is used in the interrupt process that is executed by interrupting the basic process. Also, the IY register can be used when the basic process is executed and when the interrupt process is executed, but since the IY register is used in the interrupt process and not in the basic process, it is possible to prevent the data stored in the IY register from becoming mixed up between the basic process and the interrupt process.

In addition, in this embodiment, multiple registers consisting of the IX register and the IY register can be used both when basic processing is performed and when interrupt processing is performed. However, of the IX register and the IY register, the IX register is used for basic processing and the IY register is not used for basic processing, so that it is possible to prevent confusion between basic processing and interrupt processing of data stored in at least the IY register, out of the multiple registers consisting of the IX register and the IY register.

In this embodiment, the IX register out of the multiple registers consisting of the IX register and the IY register is used in the basic processing, but none of the multiple registers consisting of the IX register and the IY register may be used in the basic processing. With this configuration, the IX register and the IY register, which can be used when executing both the basic processing and the interrupt processing, are not used in the basic processing, so that it is possible to prevent the data stored in the multiple registers consisting of the IX register and the IY register from becoming mixed up between the basic processing and the interrupt processing.

In this embodiment, the front register is used in the basic process, and the back register replaced with the front register is used in the interrupt process that is executed by interrupting the basic process. The IX register can be used both when the basic process is executed and when the interrupt process is executed, but since the IX register is used in the basic process and not in the interrupt process, it is possible to prevent the data stored in the IX register from becoming mixed up between the basic process and the interrupt process.

In addition, in this embodiment, multiple registers consisting of the IX register and the IY register can be used both when basic processing is performed and when interrupt processing is performed, but of the IX register and the IY register, the IY register is used for interrupt processing and the IX register is not used for interrupt processing, so that it is possible to prevent confusion of data stored in at least the IX register, out of the multiple registers consisting of the IX register and the IY register, between basic processing and interrupt processing.

In this embodiment, the IY register out of the multiple registers consisting of the IX register and the IY register is used in interrupt processing, but none of the multiple registers consisting of the IX register and the IY register may be used in interrupt processing. With this configuration, the IX register and the IY register, which can be used when executing both basic processing and interrupt processing, are not used in interrupt processing, so that it is possible to prevent data stored in the multiple registers consisting of the IX register and the IY register from becoming mixed up between basic processing and interrupt processing.

In addition, in this embodiment, when executing an interrupt process, if the register used is switched from the front register to the back register, the value of the back register used in the previous interrupt process is stored. However, in the current interrupt process, the value of the back register used in the previous interrupt process is not used, and the necessary value is stored in the back register again, so that it is possible to prevent the interrupt process from being executed with an unintended value.

In this embodiment, the interrupt processing is composed of a main routine (interrupt) and a subroutine (interrupt) that is called and executed from the main routine (interrupt), and among the multiple registers used in the interrupt processing, the IY register is used in the subroutine (interrupt) and not in the main routine (interrupt), so that data stored in the IY register can be prevented from becoming mixed up between the main routine (interrupt) and the subroutine (interrupt).

In addition, the subroutines (interrupts) called from the main routine (interrupt) include multiple types of subroutines (interrupts), and the IY register is not used by all of the multiple types of subroutines (interrupts), but is used by one of the types of subroutines (interrupts). This prevents data stored in the IY register from becoming mixed up between the main routine (interrupt) and a subroutine (interrupt) that uses the IY register.

In this embodiment, the IY register is configured to be used in some types of subroutines (interrupts), but it may be configured to be used in all types of subroutines (interrupts), and even in this configuration, it is possible to prevent the data stored in the IY register from becoming mixed up between the main routine (interrupt) and the subroutine (interrupt).

In addition, in this embodiment, the interrupt processing is composed of a main routine (interrupt) and a subroutine (interrupt) that is called and executed from the main routine (interrupt), and the IY register among the multiple registers used in the interrupt processing is used in the subroutine (interrupt) and not used in the main routine (interrupt). However, a specific register among the multiple registers used in the basic processing may be used in the subroutine (basic) that constitutes the basic processing and not used in the main routine (basic). This configuration can prevent data stored in a specific register from becoming mixed up between the main routine (basic) and the subroutine (basic).

In this embodiment, the interrupt processing is composed of a main routine (interrupt) and a subroutine (interrupt) that is called and executed from the main routine (interrupt), and among the multiple registers used in the interrupt processing, the D'E' register is used in the main routine (interrupt) and not in the subroutine (interrupt), so that data stored in the D'E' register can be prevented from becoming mixed up between the main routine (interrupt) and the subroutine (interrupt).

In addition, the subroutines (interrupts) called from the main routine (interrupt) include multiple types of subroutines (interrupts), and the D'E' register is not used in any of the types of subroutines (interrupts). This prevents data stored in the D'E' register from becoming mixed up between the main routine (interrupt) and any type of subroutine (interrupt).

In this embodiment, the D'E' register is configured not to be used in any type of subroutine (interrupt), but it may be configured not to be used in a specific type of subroutine (interrupt) and to be used in other types of subroutines (interrupts). Even in such a configuration, it is possible to prevent the data stored in the D'E' register from becoming mixed up between the main routine (interrupt) and a specific type of subroutine (interrupt).

In addition, in this embodiment, the interrupt processing is composed of a main routine (interrupt) and a subroutine (interrupt) that is called and executed from the main routine (interrupt), and among the multiple registers used in the interrupt processing, the D'E' register is used in the main routine (interrupt) and not in the subroutine (interrupt). However, among the multiple registers used in the basic processing, a specific register may be used in the main routine (basic) that constitutes the basic processing and not in the subroutine (basic). By using such a configuration, it is possible to prevent data stored in a specific register from becoming mixed up between the main routine (basic) and the subroutine (basic).

[Regarding registers used in on-capacity and off-capacity processing]
Next, a description will be given of registers used by the main control unit 41 when performing in-capacity processing and out-capacity processing.

As shown in FIG. 7, when performing in-capacity processing (basic), the main control unit 41 executes various processes using the table registers and the common registers. In more detail, in in-capacity processing (basic), among the table registers, the A register, F register, BC register, DE register, HL register, and Q register are used, i.e., all the registers included in the table registers. Also, in in-capacity processing (basic), all the registers included in the common registers can be used, but of these, the I register, R register, IX register, SP register, and PC register are used, and the IY register is not used.

As shown in FIG. 7, when executing out-of-capacity processing (basic), the main control unit 41 calls the main routine (out-of-capacity/basic) from in-capacity processing (basic).

When the main control unit 41 starts the main routine (outside capacity/basic), it first saves the value of the internal stack pointer stored in the SP register to a specified area in the external RAM area, and then stores a value indicating the 0th stage of the external stack area in the SP register. This switches the area for saving data from the internal stack area to the external stack area.

Then, all values in the table registers and common registers are saved in a specified order to the area of the extra stack area indicated by the extra stack pointer.

When executing the main routine (outside capacity, basic), the main control unit 41 uses the table registers and the common registers to perform various calculations. In more detail, in the main routine (outside capacity, basic), all registers included in the table registers can be used, but of these, the A register, F register, BC register, HL register, and Q register are used, and the DE register is not used. Also, in the main routine (outside capacity, basic), all registers included in the common registers can be used, but of these, the I register, R register, SP register, and PC register are used, and the IX register and IY register are not used.

The main control unit 41 also executes the subroutine (outside capacity, basic) by calling the subroutine (outside capacity, basic) in the main routine (outside capacity, basic). At this time, the address of the caller is stored in the area of the out-of-capacity stack area indicated by the value stored in the SP register. Also, in the subroutine (outside capacity, basic), data may be saved to the out-of-capacity stack area, and the out-of-capacity stack area will be used up to N levels, and at this time the out-of-capacity stack pointer stored in the SP register becomes a value indicating the Nth level area of the out-of-capacity stack area.

As shown in FIG. 7, when executing a subroutine (outside capacity, basic), the main control unit 41 executes various processes using the table registers and the common registers. In more detail, in a subroutine (outside capacity, basic), all registers included in the table registers can be used, but of these, the A register, F register, BC register, HL register, and Q register are used, and the DE register is not used. Also, in a subroutine (outside capacity, basic), all registers included in the common registers can be used, but of these, the I register, R register, SP register, and PC register are used, and the IX register and IY register are not used.

As shown in FIG. 7, when the main control unit 41 ends the main routine (outside capacity, basic), it restores all the values of the table registers and common registers that were saved to the out-of-capacity stack area. As a result, all data saved to the out-of-capacity stack area is restored, and the out-of-capacity stack area becomes empty. The main control unit 41 then restores the value of the in-capacity stack pointer that was saved to a specified area in the out-of-capacity RAM area to the SP register. As a result, the area for saving data is switched from the out-of-capacity stack area to the in-capacity stack area. Then, the main routine (outside capacity, basic) is terminated and a return is made to the caller in the in-capacity processing (basic).

As shown in FIG. 8, when performing in-capacity processing (interrupt), the main control unit 41 executes various processes using the back registers and the common registers. In detail, in in-capacity processing (interrupt), among the back registers, the A' register, F' register, B'C' register, D'E' register, and H'L' register are used, that is, all the registers included in the back registers. Also, in in-capacity processing (interrupt), all the registers included in the common registers can be used, but of these, the R register, SP register, and PC register are used, and the I register, IX register, and IY register are not used.

As shown in FIG. 8, when executing out-of-capacity processing (interrupt), the main control unit 41 calls the main routine (out-of-capacity interrupt) from in-capacity processing (interrupt).

When the main control unit 41 starts the main routine (external/interrupt), it first saves the value of the internal stack pointer stored in the SP register to a specified area in the external RAM area, and then stores a value indicating the 0th stage of the external stack area in the SP register. This switches the area for saving data from the internal stack area to the external stack area.

Then, all values in the hidden and shared registers are saved in a specified order to the area of the extra stack area indicated by the extra stack pointer.

When executing the main routine (out of capacity/interrupt), the main control unit 41 uses the back registers and the common registers to execute various processes. In detail, all the registers included in the back registers can be used, but of these, the A' register, F' register, B'C' register, and H'L' register are used, and the D'E' register is not used. In addition, all the registers included in the common registers can be used, but of these, the R register, SP register, and PC register are used, and the I register, IX register, and IY register are not used.

The main control unit 41 also executes a subroutine (out of capacity, interrupt) by calling the subroutine (out of capacity, interrupt) in the main routine (out of capacity, interrupt). At this time, the address of the caller is stored in the area of the out of capacity stack area indicated by the value stored in the SP register. Also, in the subroutine (out of capacity, interrupt), data may be saved to the out of capacity stack area, and a maximum of N levels of the out of capacity stack area will be used. At this time, the out of capacity stack pointer stored in the SP register becomes a value indicating the Nth level of the out of capacity stack area.

As shown in FIG. 8, when executing a subroutine (out of capacity/interrupt), the main control unit 41 uses the back registers and the common registers to execute various processes. In more detail, in a subroutine (out of capacity/interrupt), all registers included in the back registers can be used, but of these, the A' register, F' register, B'C' register, and H'L' register are used, and the D'E' register is not used. In addition, all registers included in the common registers can be used, but of these, the R register, SP register, and PC register are used, and the I register, IX register, and IY register are not used.

As shown in FIG. 8, when the main control unit 41 ends the main routine (outside capacity/basic), it restores all the values of the hidden registers and common registers that were saved to the outside capacity stack area. As a result, all data saved to the outside capacity stack area is restored, and the outside capacity stack area becomes empty. The main control unit 41 then restores the value of the inside capacity stack pointer that was saved to a specified area in the outside capacity RAM area to the SP register. As a result, the area for saving data is switched from the outside capacity stack area to the inside capacity stack area. Then, the main routine (outside capacity/interrupt) is terminated and a return is made to inside capacity processing (interrupt).

In this way, in this embodiment, in the basic processing, it is possible to execute internal processing (basic) by an internal program, and external processing (basic) by an external program. When external processing (basic) is called from internal processing (basic) and executed, the values stored in all registers are first saved to the external stack area in RAM 41c, and when external processing (basic) is terminated, all values saved in the external stack area are restored to all corresponding registers.

In addition, when performing in-capacity processing (basic), 13 registers are used, including the A register, F register, BC register, DE register, HL register, Q register, I register, R register, SP register, and PC register, whereas when performing out-of-capacity processing (basic), 10 registers are used, including the A register, F register, BC register, HL register, I register, R register, SP register, and PC register. As a result, out-of-capacity processing (basic) uses only a portion of the multiple registers used by in-capacity processing (basic), and fewer registers are used when performing out-of-capacity processing (basic) than when performing in-capacity processing (basic), it is possible to prevent the use of incorrect data when performing out-of-capacity processing (basic).

In this embodiment, the out-of-capacity processing (basic) uses only a portion of the multiple registers used by the in-capacity processing (basic), so that fewer registers are used when executing the out-of-capacity processing (basic) than when executing the in-capacity processing (basic). However, different registers may be used for the out-of-capacity processing (basic) and the in-capacity processing (basic), and in such a configuration, the out-of-capacity processing (basic) may use fewer registers than the in-capacity processing (basic). Even in such a configuration, fewer registers are used than when executing the in-capacity processing (basic), so that the use of erroneous data due to the execution of the out-of-capacity processing (basic) can be prevented.

In addition, in this embodiment, in the interrupt processing, it is possible to execute in-capacity processing (interrupt) by an in-capacity program and out-capacity processing (interrupt) by an out-capacity program. When out-capacity processing (interrupt) is called from in-capacity processing (interrupt) and executed, the values stored in all registers are first saved to the out-capacity stack area in RAM 41c, and when the out-capacity processing (interrupt) is terminated, all values saved in the out-capacity stack area are restored to all the corresponding registers.

When performing in-capacity processing (interrupt), 11 registers are used, including the A' register, F' register, B'C' register, D'E' register, H'L' register, R register, SP register, and PC register, whereas when performing out-of-capacity processing (interrupt processing), 9 registers are used, including the A' register, F' register, B'C' register, H'L' register, R register, SP register, and PC register. As a result, out-of-capacity processing (interrupt) uses only a portion of the multiple registers used by in-capacity processing (interrupt), and fewer registers are used when performing out-of-capacity processing (interrupt) than when performing in-capacity processing (interrupt), which prevents the use of erroneous data due to the execution of out-of-capacity processing (interrupt).

In this embodiment, the out-of-capacity processing (interrupt) uses only some of the multiple registers used by the in-capacity processing (interrupt), so that fewer registers are used when executing the out-of-capacity processing (interrupt) than when executing the in-capacity processing (interrupt). However, different registers may be used for the out-of-capacity processing (interrupt) and the in-capacity processing (interrupt), and in such a configuration, the out-of-capacity processing (interrupt) may use fewer registers than the in-capacity processing (interrupt). Even in such a configuration, fewer registers are used than when executing the in-capacity processing (interrupt), so that the use of erroneous data due to the execution of the out-of-capacity processing (interrupt) can be prevented.

In this embodiment, it is possible to execute in-capacity processing by an in-capacity program and out-capacity processing by an out-capacity program, and when out-capacity processing is called from in-capacity processing and executed, the value of the in-capacity stack pointer stored in the SP register is saved and switched to a value indicating the out-capacity stack area, thereby switching the data saving destination from the in-capacity stack area to the out-capacity stack area. Also, when the out-capacity processing (basic processing) is terminated, the saved value of the in-capacity stack pointer is returned to the SP register, switching the data saving destination from the out-capacity stack area to the in-capacity stack area.

When the out-of-capacity processing ends, all data that was saved to the out-of-capacity stack area during the out-of-capacity processing is restored, and the data saving destination is then switched from the out-of-capacity stack area to the in-capacity stack area. This prevents further out-of-capacity processing from being performed while the data used in the previously executed out-of-capacity processing remains saved, and prevents confusion between the data used in the previously executed out-of-capacity processing and the data to be used in the currently executed out-of-capacity processing.

In addition, the out-of-capacity processing called from the in-capacity processing includes multiple types of out-of-capacity processing, and regardless of the type of out-of-capacity processing, when the out-of-capacity processing is terminated, all data that was saved to the out-of-capacity stack area during the execution of the out-of-capacity processing is restored, and then the data saving destination is switched from the out-of-capacity stack area to the in-capacity stack area. Therefore, regardless of the type of out-of-capacity processing, the data used in the previously executed out-of-capacity processing remains saved and further out-of-capacity processing is not executed, and confusion between the data used in the previously executed out-of-capacity processing and the data to be used in the currently executed out-of-capacity processing can be prevented.

In addition, regardless of the type of out-of-capacity processing, when the out-of-capacity processing ends, no data is stored in the out-of-capacity stack area. Therefore, when starting out-of-capacity processing, there is no need to restore the value of the out-of-capacity stack pointer that was set when the previous out-of-capacity processing ended. It is sufficient to always set the value of the out-of-capacity stack pointer to a value that indicates the 0th stage of the out-of-capacity stack area.

[Regarding modified registers]
Next, a modification of a plurality of registers used by the CPU 41a for performing calculations will be described with reference to FIGS.

In the example shown in Figures 5 to 8, the multiple registers mainly include a front register, a back register, and a common register, and for basic processing, the front register and the common register are used whether the processing is within the capacity or outside the capacity, and for interrupt processing, the back register and the common register are used whether the processing is within the capacity or outside the capacity. However, in the modified example shown in Figures 9 and 10, the multiple registers include an inside register, an outside register, and a common register.

The in-capacity register has a set of front and back registers, and the out-of-capacity register has a set of front and back registers that are different from those of the in-capacity register.

The main control unit 41 uses the in-capacity register during in-capacity processing, and during out-capacity processing, it switches the register used from the in-capacity register to the out-capacity register, and when the out-capacity processing is completed, it returns the register used from the out-capacity register to the in-capacity register, so that the in-capacity register is used during in-capacity processing and the out-capacity register is used during out-capacity processing.

The common register is also configured to be usable for both in-capacity and out-of-capacity processing.

As shown in FIG. 10, the IX and IY registers, which are common registers, can be used in both in-capacity processing and out-capacity processing, but of the IX and IY registers, the IX register is used in in-capacity processing and is not used in out-capacity processing. Also, of the IX and IY registers, the IY register is used in out-capacity processing and is not used in in-capacity processing.

Thus, in a modified example of the multiple registers, the multiple registers include in-capacity registers used in in-capacity processing, out-of-capacity registers used in out-of-capacity processing, and common registers that can be used in both in-capacity processing and out-of-capacity processing, and the in-capacity registers are used in in-capacity processing, and the out-of-capacity registers are used in out-of-capacity processing called from the in-capacity processing.

The multiple registers consisting of the IX register and the IY register can be used for both in-capacity processing and out-of-capacity processing, but of the multiple registers consisting of the IX register and the IY register, the IX register is used for in-capacity processing and not for out-of-capacity processing, which prevents the data stored in the IX register from becoming mixed up between in-capacity processing and out-of-capacity processing.

In addition, multiple registers consisting of the IX register and the IY register can be used for both in-capacity processing and out-of-capacity processing, but of the multiple registers consisting of the IX register and the IY register, the IY register is used for out-of-capacity processing and not for in-capacity processing, which prevents the data stored in the IY register from becoming mixed up between in-capacity processing and out-of-capacity processing.

In addition, of the multiple registers consisting of the IX register and the IY register, the IX register is used only for on-capacity processing and the IY register is used only for off-capacity processing. However, the multiple registers consisting of the IX register and the IY register may be used only for on-capacity processing, or the multiple registers consisting of the IX register and the IY register may be used only for off-capacity processing. By using such a configuration, it is possible to prevent the data stored in the multiple registers consisting of the IX register and the IY register from becoming mixed up during on-capacity processing and off-capacity processing.

[Effect 1]
In this embodiment, the interrupt processing is composed of a main routine (interrupt) and a subroutine (interrupt) that is called and executed from the main routine (interrupt), and among the multiple registers used in the interrupt processing, the IY register is used in the subroutine (interrupt) and not in the main routine (interrupt), thereby preventing confusion of data stored in the IY register between the main routine (interrupt) and the subroutine (interrupt).

In addition, in this embodiment, the subroutines (interrupts) called from the main routine (interrupt) include multiple types of subroutines (interrupts), and the IY register is not used by all of the multiple types of subroutines (interrupts), but is used by one of the types of subroutines (interrupts). This makes it possible to prevent data stored in the IY register from becoming mixed up between the main routine (interrupt) and a subroutine (interrupt) that uses the IY register.

In addition, in this embodiment, the interrupt processing is executed by interrupting the basic processing each time a timer interrupt occurs, and the IY register is used in the subroutine (interrupt) and not in the main routine (interrupt), so that data stored in the IY register can be prevented from becoming mixed up between the main routine (interrupt) and the subroutine (interrupt) that uses the IY register while the interrupt processing is being executed.

In this embodiment, the interrupt processing is composed of a main routine (interrupt) and a subroutine (interrupt) that is called and executed from the main routine (interrupt), and among the multiple registers used in the interrupt processing, the D'E' register is used in the main routine (interrupt) and not in the subroutine (interrupt), so that data stored in the D'E' register can be prevented from becoming mixed up between the main routine (interrupt) and the subroutine (interrupt).

In addition, in this embodiment, the subroutines (interrupts) called from the main routine (interrupt) include multiple types of subroutines (interrupts), and the D'E' register is not used in any of the types of subroutines (interrupts). This makes it possible to prevent the data stored in the D'E' register from becoming mixed up between the main routine (interrupt) and any type of subroutine (interrupt).

In addition, in this embodiment, the interrupt processing is executed by interrupting the basic processing each time a timer interrupt occurs, and the D'E' register is used in the main routine (interrupt) and not in the subroutine (interrupt), so that data stored in the D'E' register can be prevented from becoming mixed up between the main routine (interrupt) and the subroutine (interrupt) while the interrupt processing is being executed.

[Effect 2]
In this embodiment, the front register is used in the basic process, and the back register replaced with the front register is used in the interrupt process that is executed by interrupting the basic process. The IX register can be used when the basic process is executed and when the interrupt process is executed, but since the IX register is used in the basic process and not in the interrupt process, it is possible to prevent the data stored in the IX register from becoming mixed up between the basic process and the interrupt process.

In addition, in this embodiment, multiple registers consisting of the IX register and the IY register can be used both when basic processing is performed and when interrupt processing is performed, but of the IX register and the IY register, the IY register is used for interrupt processing and the IX register is not used for interrupt processing, so that it is possible to prevent confusion of data stored in at least the IX register, out of the multiple registers consisting of the IX register and the IY register, between basic processing and interrupt processing.

In addition, in this embodiment, multiple registers consisting of the IX register and the IY register can be used when basic processing is performed and when interrupt processing is performed, but it is also possible to configure the system so that neither the IX register nor the IY register is used for interrupt processing. With this configuration, the IX register and the IY register, which can be used when basic processing is performed and when interrupt processing is performed, are not used in interrupt processing, so that it is possible to prevent data stored in multiple registers consisting of the IX register and the IY register from becoming mixed up between basic processing and interrupt processing.

In this embodiment, the front register is used in the basic process, and the back register replaced with the front register is used in the interrupt process that is executed by interrupting the basic process. The IY register can be used when the basic process is executed and when the interrupt process is executed, but since the IY register is used in the interrupt process and not in the basic process, it is possible to prevent the data stored in the IY register from becoming mixed up between the basic process and the interrupt process.

In addition, in this embodiment, multiple registers consisting of the IX register and the IY register can be used both when basic processing is performed and when interrupt processing is performed. However, of the IX register and the IY register, the IX register is used for basic processing and the IY register is not used for basic processing, so that it is possible to prevent confusion between basic processing and interrupt processing between data stored in at least the IY register, out of the multiple registers consisting of the IX register and the IY register.

In addition, in this embodiment, multiple registers consisting of the IX register and the IY register can be used when basic processing is performed and when interrupt processing is performed, but it is also possible to configure the basic processing so that none of the IX register and the IY register are used. With this configuration, none of the multiple registers consisting of the IX register and the IY register that can be used when basic processing is performed and when interrupt processing is performed are used in the basic processing, so that it is possible to prevent confusion of data stored in the multiple registers consisting of the IX register and the IY register between basic processing and interrupt processing.

In addition, in this embodiment, when an interrupt process is executed and the register used is switched from the front register to the back register, the value in the back register used in the previous interrupt process is stored. However, in the current interrupt process, the value in the back register used in the previous interrupt process is not used, and the necessary value is stored in the back register again, so that the interrupt process can be prevented from being executed with an unintended value.

[Effect 3]
In this embodiment, it is possible to execute in-capacity processing by an in-capacity program, and out-capacity processing by an out-capacity program that is called and executed from the in-capacity program.When executing in-capacity processing, first the values stored in all registers are saved to an out-of-capacity stack area in RAM 41c, and when the out-of-capacity processing is terminated, all the values saved in the out-of-capacity stack area are restored to all the corresponding registers.

In addition, when out-of-capacity processing is performed, only a portion of the multiple registers used by in-capacity processing are used. Therefore, out-of-capacity processing uses only a portion of the multiple registers used by in-capacity processing, and fewer registers are used when out-of-capacity processing is performed than when in-capacity processing is performed, preventing the use of incorrect data when out-of-capacity processing is performed.

In addition, in this embodiment, in the basic processing, it is possible to execute internal processing (basic) by an internal program and external processing (basic) by an external program. When external processing (basic) is called from internal processing (basic) and executed, the values stored in all registers are first saved to the external stack area in RAM 41c, and when external processing (basic) is terminated, all values saved in the external stack area are restored to all corresponding registers.

In addition, when performing in-capacity processing (basic), 13 registers are used, including the A register, F register, BC register, DE register, HL register, Q register, I register, R register, SP register, and PC register, whereas when performing out-of-capacity processing (basic), 10 registers are used, including the A register, F register, BC register, HL register, I register, R register, SP register, and PC register. As a result, out-of-capacity processing (basic) uses only a portion of the multiple registers used by in-capacity processing (basic), and fewer registers are used when performing out-of-capacity processing (basic) than when performing in-capacity processing (basic), it is possible to prevent the use of incorrect data when performing out-of-capacity processing (basic).

In addition, in this embodiment, in the interrupt processing, it is possible to execute in-capacity processing (interrupt) by an in-capacity program and out-capacity processing (interrupt) by an out-capacity program. When out-capacity processing (interrupt) is called from in-capacity processing (interrupt) and executed, the values stored in all registers are first saved to the out-capacity stack area in RAM 41c, and when the out-capacity processing (interrupt) is terminated, all values saved in the out-capacity stack area are restored to all corresponding registers.

When performing in-capacity processing (interrupt), 11 registers are used, including the A' register, F' register, B'C' register, D'E' register, H'L' register, R register, SP register, and PC register, whereas when performing out-of-capacity processing (interrupt processing), 9 registers are used, including the A' register, F' register, B'C' register, H'L' register, R register, SP register, and PC register. As a result, out-of-capacity processing (interrupt) uses only a portion of the multiple registers used by in-capacity processing (interrupt), and fewer registers are used when performing out-of-capacity processing (interrupt) than when performing in-capacity processing (interrupt), preventing the use of incorrect data due to the execution of out-of-capacity processing (interrupt).

[Effect 4]
In this embodiment, it is possible to execute an in-capacity process by an in-capacity program and an out-capacity process by an out-capacity program, and when an out-capacity process is called from an in-capacity process and executed, the value of the in-capacity stack pointer stored in the SP register is saved and switched to a value indicating the out-capacity stack area, thereby switching the data save destination from the in-capacity stack area to the out-capacity stack area. Also, when the out-capacity process (basic process) is terminated, the saved value of the in-capacity stack pointer is returned to the SP register, thereby switching the data save destination from the out-capacity stack area to the in-capacity stack area.

When the out-of-capacity processing ends, all data that was saved to the out-of-capacity stack area during the out-of-capacity processing is restored, and the data saving destination is then switched from the out-of-capacity stack area to the in-capacity stack area. This prevents further out-of-capacity processing from being performed while the data used in the previously executed out-of-capacity processing remains saved, and prevents confusion between the data used in the previously executed out-of-capacity processing and the data to be used in the currently executed out-of-capacity processing.

In addition, the out-of-capacity processing called from the in-capacity processing includes multiple types of out-of-capacity processing, and regardless of the type of out-of-capacity processing, when the out-of-capacity processing is terminated, all data that was saved to the out-of-capacity stack area during the execution of the out-of-capacity processing is restored, and then the data saving destination is switched from the out-of-capacity stack area to the in-capacity stack area. Therefore, regardless of the type of out-of-capacity processing, the data used in the previously executed out-of-capacity processing remains saved and further out-of-capacity processing is not executed, and confusion between the data used in the previously executed out-of-capacity processing and the data to be used in the currently executed out-of-capacity processing can be prevented.

Although an embodiment of the present invention has been described above with reference to the drawings, the present invention is not limited to this embodiment, and it goes without saying that modifications and additions that do not deviate from the spirit of the present invention are also included in the present invention.

In the above embodiment, an example was described in which the present invention is applied to a slot machine in which the bet amount is set using medals and credits as gaming value, but it may also be applied to a slot machine in which the bet amount is set using gaming balls as gaming value, or a full credit type slot machine in which the bet amount is set using only credits as gaming value.

In addition, in the above embodiment and modified example, the present invention is applied to a slot machine 1, which is an example of a gaming machine, but the present invention is not limited to this and can be applied to any gaming machine that performs a specific game, such as a pachinko gaming machine in which a game is played by shooting a gaming ball into a game area, or even a general gaming machine other than a slot machine or a pachinko gaming machine.

1 Slot machine 2L, 2C, 2R Reel 6 MAXBET switch 7 Start switch 8L, 8C, 8R Stop switch 41 Main control unit 91 Sub control unit

Claims (1)

In a gaming machine for playing a game,
A program execution means for executing a program using a plurality of registers,
The programs include a first program and a second program that is called and executed by the first program,
the plurality of registers include a first register group of registers consisting of a plurality of types of registers, and a second register group including a plurality of types of registers identical to the plurality of types of registers included in the first register group;
When executing the first program, a register belonging to the first register group is used;
When executing the second program, a register belonging to the second register group is used;
the first program includes a first basic program and a first interrupt program that is executed by interrupting execution of the first basic program,
the second program includes a second basic program called from the first basic program and a second interrupt program called from the first interrupt program,
when executing the first basic program, both of the first type registers and the second type registers included in the first register group are used, whereas when executing the second basic program, only the first type registers of the first type registers and the second type registers included in the second register group are used;
A gaming machine in which, when executing the first interrupt program, both of the third type registers and the fourth type registers included in the first register group are used, while, when executing the second interrupt program, only the third type registers of the third type registers and the fourth type registers included in the second register group are used.

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