JP7412031B2 - gaming machine - Google Patents

Description

TECHNICAL FIELD The present invention relates to a gaming machine that uses a lottery to determine whether or not to award a gaming benefit to a player.

In a slot machine as a gaming machine, a winning combination is drawn in response to a player's bet on medals (game media) and operation of a start switch, and a plurality of reels with various symbols are rotated. Then, the reels are sequentially stopped according to the lottery results and the player's operation of the stop switch, and when the symbol combination corresponding to the winning combination is displayed on the active line, which is the payout target line, a predetermined number of symbols are displayed. Gaming profits (hereinafter simply referred to as gaming profits) are given to the player, such as the payout of medals.

In such gaming machines, it is desirable to effectively utilize the limited storage area in the memory in order to enhance the gameplay. For example, a technique is known in which management values are associated with control information in a data set table to effectively use memory (for example, Patent Document 1).

Japanese Patent Application Publication No. 2016-214339

By the way, in a slot machine, a winning type lottery may determine a selected winning type in which a correct winning combination with a large gaming profit and an incorrect winning combination with a smaller gaming profit than the correct winning combination overlap. When winning such a selected winning type, if the player operates the stop switch in the correct operation mode, the correct winning combination will become a prize-winner, and if the player operates the stop switch in an operating mode other than the correct answering mode, the incorrect winning combination will become possible to win. Become. Therefore, the player can understand that he has won the selected winning type by winning the incorrect winning combination, and that the operating mode he operated is not the correct operating mode.

However, if it becomes possible to determine the winning type by winning a winning combination, such as an incorrect winning combination, for example, there is a risk that the player will lose hope for the game.

In view of such problems, the present invention aims to provide a gaming machine that can improve gaming performance.

In order to solve the above problems, the gaming machine of the present invention includes a winning type lottery means for determining one of the plurality of winning types by lottery, and a plurality of types of symbols are arranged respectively based on the operation of a start switch. a reel control means for controlling the rotation of a plurality of reels and controlling each reel to stop in accordance with the operation of a stop switch; and a non-internal gaming state, and a bonus combination in the non-internal gaming state. A game state control means for shifting to one of a plurality of types of game states including an internal medium game state that is entered by winning a winning type, and a game section in which it is possible to perform auxiliary effects to assist in winning a specific role. and a performance state control means for determining either an advantageous section, which is an advantageous section, and a non-advantageous section, which is a game section other than the advantageous section, and the winning type lottery means, in the non-internal gaming state. , a specific winning type may be determined in which a first minor role whose payout is less than the specified number, a second minor role whose payout is less than the specified number, and a bonus role overlap, and the specific winning type is , a first operation mode in which the first reel is first stopped is set as a winning condition of the first small winning combination, and a second operation mode in which the second reel, which is different from the first reel, is first stopped; The operation mode is set as a winning condition for the second minor role, and the winning type lottery means selects a winning combination in which a correct winning combination with a payout of more than a specified number and an incorrect winning combination with a payout of less than the specified number overlap. The selected winning type may be such that the first operation mode is not set as a winning condition for the correct combination, but is set as a winning condition for the incorrect combination, and the selected winning type is set as a winning condition for the incorrect combination. The correct winning combination includes the first minor winning combination but does not include the second minor winning combination, and the winning type lottery means may perform a lottery to shift the non-advantageous area to the advantageous area. This is a winning type that cannot be played, and a special winning type that includes a replay combination may be determined, and the replay combination and the first minor combination have the same symbols corresponding to the first reel .

According to the present invention, it is possible to improve the gameplay.

FIG. 2 is an external view for explaining a schematic mechanical configuration of a slot machine. FIG. 2 is an external view of the slot machine with the front door opened for explaining the general mechanical configuration of the slot machine. It is a figure explaining the pattern arrangement of a reel, and an active line. 1 is a block diagram showing a schematic electrical configuration of a slot machine. FIG. It is an explanatory diagram for explaining a winning combination. It is a figure showing a winning type lottery table. It is a figure showing a winning type lottery table. It is an explanatory diagram for explaining transition of a game state. FIG. 3 is an explanatory diagram for explaining the transition of performance states. It is a figure explaining the internal state of a normal performance state. It is a figure explaining a state up lottery table. It is a figure explaining a CZ lottery table. It is a figure explaining the mode of a normal performance state. It is a figure explaining a migration lottery table. FIG. 2 is a diagram illustrating an overview of increase/decrease in medals when changing settings. It is a figure explaining a continuation lottery table and an advantageous continuation lottery table. It is a figure explaining reel production. It is a figure explaining a reel performance lottery table. 3 is a flowchart illustrating CPU initialization processing in the main control board. It is a flowchart explaining cold start processing in a main control board. 3 is a flowchart illustrating error stop processing in the main control board. 3 is a flowchart illustrating a setting value switching process in the main control board. 3 is a flowchart illustrating initialization start processing in the main control board. 3 is a flowchart illustrating state recovery processing in the main control board. It is a flowchart explaining game start processing in the main control board. It is a flowchart explaining the game medal insertion process in the main control board. It is a flowchart explaining internal lottery processing in a main control board. It is a flowchart explaining the pattern code setting process in the main control board. 3 is a flowchart illustrating execution flag setting processing in the main control board 200. FIG. 12 is a flowchart illustrating non-advantageous section processing executed in state-specific module execution processing. It is a flowchart explaining normal performance state processing executed in module execution processing by state. It is a flowchart explaining CZ effect state processing performed in module execution processing by state. It is a flowchart explaining the non-advantageous standby effect state processing executed in the module execution processing by state. It is a flowchart explaining the advantageous standby performance state processing executed in the module execution processing by state. It is a flowchart explaining processing during rotation of a drum in a main control board. It is a flow chart explaining rotation drum stop processing in a main control board. 3 is a flowchart illustrating display determination processing in the main control board. It is a flow chart explaining payout processing in a main control board. It is a flowchart explaining game transfer processing in the main control board. It is a flowchart explaining the normal AT performance state processing executed in the state-based module execution processing. 3 is a flowchart illustrating a power-off save process in the main control board. 3 is a flowchart illustrating timer interrupt processing in the main control board. FIG. 3 is a diagram for explaining electrical connections around a main CPU. FIG. 2 is a block diagram showing the internal configuration of a CPU core. FIG. 2 is a diagram illustrating the configuration of a register. FIG. 2 is an explanatory diagram showing a memory map. It is a flowchart showing specific processing of a COM_PRE module, a RAD_CHK module, a COM_CHK module, and a COM_LOT module. FIG. 2 is an explanatory diagram for explaining an example of commands for realizing a COM_PRE module, a RAD_CHK module, a COM_CHK module, and a COM_LOT module. FIG. 6 is an explanatory diagram for explaining the processing of the command “CP (HL), DE”. It is a flowchart showing specific processing of a COM_PRE2 module, a RAD_CHK2 module, a COM_CHK module, and a TABLSET module. FIG. 2 is an explanatory diagram for explaining an example of commands for realizing a COM_PRE2 module, a RAD_CHK2 module, a COM_CHK module, and a TABLSET module. 12 is a flowchart showing other processing of the COM_PRE module, RAD_CHK module, COM_LOT module, and TABLSET module. FIG. 2 is an explanatory diagram for explaining an example of commands for realizing a COM_PRE module, a RAD_CHK module, a COM_LOT module, and a TABLSET module. FIG. 2 is an explanatory diagram for explaining the arrangement of variables in memory.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The dimensions, materials, and other specific numerical values shown in these embodiments are merely illustrative to facilitate understanding of the invention, and do not limit the invention unless otherwise specified. In this specification and the drawings, elements with substantially the same functions and configurations are given the same reference numerals to omit redundant explanation, and elements not directly related to the present invention are omitted from illustration. do.

(Mechanical configuration of slot machine 100)
As shown in the external views of FIGS. 1 and 2, the slot machine 100 as a gaming machine includes a casing 102 with an open front, and a front surface that is rotatably arranged vertically in one end of the casing 102. An upper door 104 and a lower front door 106 are provided. A colorless and transparent symbol display window 108 made of a glass plate, a transparent resin plate, etc. is provided at the lower center of the upper front door 104, and a symbol display window 108 is provided in the housing 102 at a position corresponding to the symbol display window 108. , three reels 110 (left reel 110a, middle reel 110b, right reel 110c) are provided so as to be rotatable independently. On the outer peripheral surfaces of the left reel 110a, the middle reel 110b, and the right reel 110c, as shown in the pattern arrangement in FIG. Through the symbol display window 108, the player can visually recognize a total of nine consecutive symbols, three consecutive symbols on each of the left reel 110a, middle reel 110b, and right reel 110c located in the upper, middle, and lower rows.

An operation unit installation base 112 is formed on the upper part of the lower front door 106, and the operation unit installation base 112 is provided with a medal insertion unit 114, a bet switch 116, a start switch 118, a stop switch 120, a performance switch 122, etc. There is. The medal insertion unit 114 accepts the insertion of medals as gaming value through the medal insertion slot 114a. The bet switch 116 inserts (bets) a specified number of medals required for one game among the medals electrically stored (hereinafter simply referred to as credits) inside the slot machine 100.

The start switch 118 is constituted by a lever capable of detecting a tilting operation, for example, and detects a game start operation by a player. The stop switches 120 (stop switch 120a, stop switch 120b, stop switch 120c) are provided corresponding to the left reel 110a, middle reel 110b, and right reel 110c, respectively, and detect the player's stop operation. Note that when the stop switch 120 can be stopped, the first stop operation by the player on any of the stop switches 120a, 120b, and 120c is referred to as a first stop. After that, operating one of the two stop switches 120 that has not been stopped is called a second stop, and after the second stop, operating the last remaining stop switch 120 is called a third stop. . The effect switch 122 is composed of, for example, a press switch and a jog dial switch rotatably arranged around the press switch, and detects the player's press operation or rotation operation.

A liquid crystal display section 124 is provided at the upper center of the front upper door 104 to display various images associated with the performance. Further, on the upper part and on the left and right sides of the upper front door 104, display lamps 126 made of, for example, high-intensity light emitting diodes (LEDs) are provided. Furthermore, speakers 128 are provided at the left and right positions of the liquid crystal display section 124 on the back surface of the upper front door 104 and at the left and right positions on the back surface of the lower front door 106, for providing auditory effects such as sound effects and musical sounds.

The operation unit installation base 112 is provided with a main credit display unit 130 and a main payout display unit 132. Further, a sub-credit display section 134 and a sub-payout display section 136 are provided between the symbol display window 108 and the operation section installation stand 112. The main credit display section 130 and sub-credit display section 134 display the number of credited medals (credit number), and the main payout display section 132 and sub-payout display section 136 display the number of medals to be paid out. .

A medal dispensing device (medal hopper) 142 is provided below the reel 110 in the housing 102 for dispensing medals from the medal discharging port 140a. Furthermore, a receiving tray section 140 for storing medals dispensed from the medal ejection port 140a is provided at the lower front surface of the lower front door 106. Further, a power switch 144 is provided inside the housing 102. The power switch 144 is operated by an administrator who manages the slot machine 100 and is used to switch between two states: a power-off state and a power-on state.

Further, inside the housing 102, a setting key and a setting change switch (not shown) are provided on a main control board 200, which will be described later. In the slot machine 100, when the power is turned on via the power switch 144 with a predetermined key (operation key) inserted into the setting key and rotated from the OFF position to the ON position, the slot machine 100 shifts to the setting change mode. , the setting value can be changed (also simply referred to as setting change). The set value is a stepwise representation of the player's advantage (mechanical split), and is expressed in 6 levels from 1 to 6, for example. Generally, the larger the set value, the more advantageous the game is as a whole. It is set to be high (expected number of acquisitions is high). Then, each time the setting change switch is pressed in a state where settings can be changed, the setting value is incremented by 1, and the setting value is changed to one of the six setting values, for example, and the start switch 118 is operated. Then, the setting value is determined, and by returning the setting key to its original position (OFF position), the setting change mode ends and the game becomes possible. Note that the settings can only be changed for a certain period of time after the power switch 144 is operated and the power is turned on.

In the slot machine 100, when a game can be started and a prescribed number of medals are bet, the active line A becomes effective and the operation on the start switch 118 becomes effective. Here, bets can be made by inserting medals that have been credited through the operation of the bet switch 116, by inserting medals through the medal inserter 114, and by placing a replay combination, which will be described in detail later, on the active line A. This includes any case where medals are automatically inserted based on the situation. Further, the active line A is a line for determining whether or not a winning combination has been won, and in this embodiment, there is only one active line A. As shown in FIG. 3(b), the active line A is the upper row of the left reel 110a, the middle row of the middle reel 110b, and It is set as a line connecting the positions corresponding to the symbols that stop at the lower stage of the right reel 110c. The invalid line is used to determine the winning combination when it is difficult to understand the winning combination only by the symbol combination displayed on the active line A, and displays other symbol combinations that make it easier to understand the winning combination. In this embodiment, four invalid lines B1, B2, B3, and C shown in FIG. 3(b) are assumed.

Then, when the start switch 118 is operated by the player, the game is started, the left reel 110a, the middle reel 110b, and the right reel 110c are rotated, and a winning type lottery is executed. Thereafter, the corresponding left reel 110a, middle reel 110b, and right reel 110c are respectively stopped in accordance with the operation of the stop switches 120a, 120b, and 120c. Then, if a winning combination that can receive a medal payout is won based on the lottery result of the winning type lottery and the combination of symbols displayed on the active line A, a medal payout will be executed, and the winning type that can receive a medal payout will be executed. If the player does not win or wins but does not win, the game ends when the left reel 110a, middle reel 110b, and right reel 110c all stop.

In the present embodiment, the above-mentioned one game includes the insertion of medals through the medal insertion unit 114, the insertion of credited medals through the operation of the bet switch 116, or the replay combination displayed on the active line A. After one of the automatic insertions of medals is performed based on this, the rotation of the left reel 110a, middle reel 110b, and right reel 110c is controlled in response to the player's operation of the start switch 118, and a winning type lottery is executed. The left reel 110a, middle reel 110b, and right reel corresponding to the operated stop switches 120a, 120b, and 120c are selected according to the lottery results of the winning type lottery and the operation of the plurality of stop switches 120a, 120b, and 120c by the player. 110c is controlled to stop, and when a winning combination that can receive a payout of medals is won, it refers to the game until the payout of the medals is executed. In addition, if the winning type for which medals can be paid out is not won, or if the player wins but does not win, one game ends when the left reel 110a, middle reel 110b, and right reel 110c all stop. However, the start of one game may be read as the operation of the start switch 118 by the player instead of the above-mentioned insertion of medals or winning of the replay combination. Further, the number of times such one game is repeated is defined as the number of games.

FIG. 4 is a block diagram showing a schematic electrical configuration of the slot machine 100. As shown in FIG. 4, the slot machine 100 includes a main control board 200 (main control unit) that controls the progress of the game, and a sub-control board 202 (sub-control unit) that controls effects according to the progress of the game. A control board is provided that includes a control board. Further, transmission of electrical signals between the main control board 200 and the sub-control board 202 is limited to only one direction from the main control board 200 to the sub-control board 202 from the viewpoint of fraud prevention and the like.

(Main control board 200)
The main control board 200 has a semiconductor integrated circuit including a main CPU 200a as a central processing unit, a main ROM 200b storing programs etc., a main RAM 200c functioning as a work area, etc., and controls the entire slot machine 100 in an integrated manner. . Note that even if the power is turned off, the data in the main RAM 200c is retained without being erased unless the settings are changed and the RAM is cleared.

The main control board 200 also includes an initialization means 300, a bet means 302, and a winning type lottery means (lottery means) 304, which function when the main CPU 200a cooperates with the main RAM 200c based on a program stored in the main ROM 200b. , reel control means 306, determination means 308, payout control means 310, game state control means 312, presentation state control means (state control means, section control means) 314, command transmission means 316, and other functional units.

The main control board 200 receives various detection signals from the inserted medal detection section 414b that detects the insertion of medals into the medal insertion slot 114a, the bet switch 116, the start switch 118, and the stop switches 120a, 120b, and 120c. The main CPU 200a executes various processes based on the received detection signal.

The initialization means 300 executes initialization processing in the main control board 200. The betting means 302 bets medals for use in games. Based on the operation of the start switch 118, the winning type lottery means 304 performs a winning type lottery to determine the validity of the winning combination, more specifically, the validity of the winning type including the winning combination, as will be described in detail later.

The reel control means 306 controls the rotation of the left reel 110a, the middle reel 110b, and the right reel 110c in response to the operation of the start switch 118, and controls the rotation of the left reel 110a, middle reel 110b, and right reel 110c, respectively. In response to the operation of the stop switches 120a, 120b, and 120c, the corresponding left reel 110a, middle reel 110b, and right reel 110c are controlled to stop. In addition, the reel control means 306 activates the operation of the stop switches 120a, 120b, and 120c in the previous game in response to the operation of the start switch 118, and then displays the lottery results of the winning type lottery by the player. The time until the operation of the stop switches 120a, 120b, 120c is enabled (invalidated by the completion of the operation of the stop switches 120a, 120b, 120c in the previous game) is extended from the specified time, and during that time, the reel 110a , 110b, and 110c may be rotated in various ways (freeze effect). Reel effects include not enabling a switch that should have been enabled for a predetermined period of time, suspending a process that should have been executed for a predetermined period of time, or causing signals from a switch that should have been sent or received to be sent or received for a predetermined period of time. This can be achieved by not having it.

Further, a reel drive control section 150 is connected to the main control board 200. The reel drive control unit 150 drives the stepping motor 152 based on rotation start signals of the left reel 110a, middle reel 110b, and right reel 110c transmitted from the reel control means 306 in response to the operation signal of the start switch 118. do. In addition, the reel drive control unit 150 detects stop signals for each of the left reel 110a, the middle reel 110b, and the right reel 110c and the rotational position detection circuit 154, which are transmitted from the reel control means 306 in response to the operation signal of the stop switch 120. Based on the signal, driving of the stepping motor 152 is stopped.

The determining means 308 determines whether the symbol combination corresponding to the winning combination has been displayed on the active line A. Here, the display of a symbol combination corresponding to a winning combination on the active line A may simply be called winning. The payout control means 310 pays out medals in the number (value amount) corresponding to the winning combination based on the symbol combination corresponding to the winning combination being displayed on the active line A (winning). Further, a medal payout device 142 is connected to the main control board 200, and the payout control means 310 dispenses medals while counting the number of medals to be paid out.

The game state control means 312 refers to the result of the winning type lottery and the determination result of the determination means 308, and shifts the game state to one of a plurality of types of game states. Further, the performance state control means 314 refers to the result of the winning type lottery, the determination result of the determination means 308, and the transition information of the game state, and shifts the performance state to one of a plurality of types of performance states.

The command transmitting means 316 sends commands related to the game along with the operations of the betting means 302, the winning type lottery means 304, the reel control means 306, the determination means 308, the payout control means 310, the game state control means 312, the performance state control means 314, etc. are sequentially determined, and the determined commands are sequentially transmitted to the sub-control board 202.

Further, the main control board 200 is provided with a random number generator (random number generation means) 200d. The random number generator 200d sequentially increments the count value, loops it within a predetermined numerical range, and obtains a random number by extracting the count value at a predetermined time point. The random numbers generated by the random number generator 200d of the main control board 200 (hereinafter referred to as winning type lottery random numbers) are used to determine the gaming profit to be given to the player, for example, the winning type lottery means 304 to determine the winning type. .

(Sub control board 202)
Further, like the main control board 200, the sub control board 202 has various semiconductor integrated circuits including a sub CPU 302a which is a central processing unit, a sub ROM 302b in which programs etc. are stored, a sub RAM 302c which functions as a work area, etc. , particularly controls the presentation based on commands from the main control board 200. Further, like the main RAM 200c, the sub-RAM 302c is also connected to a backup power source (not shown), and even if the power is cut off, the data is retained without being erased. Note that the sub control board 202 is also provided with a random number generator (random number generation means) 302d, like the main control board 200, and the random numbers (hereinafter referred to as performance lottery random numbers) generated by the random number generator 302d are generated by the main control board 202. It is used to determine the mode of presentation.

Further, in the sub control board 202, the sub CPU 302a operates an initialization determining means 330, a command receiving means 332, an effect controlling means 334, etc., which function by cooperating with the sub RAM 302c based on the program stored in the sub ROM 302b. It has a functional part.

The initialization determining means 330 executes initialization processing in the sub control board 202. The command receiving means 332 receives commands from other control boards, such as the main control board 200, and processes the commands. The performance control means 334 receives the detection signal from the performance switch 122, and determines the performance of the game to be performed on each device of the liquid crystal display section 124, the speaker 128, and the performance lamp 126 based on the received command. Specifically, the production control means 334 controls the image data displayed on the liquid crystal display section 124 and the electricity for production through illumination devices such as the production lamp 126, the sub-credit display section 134, and the sub-payout display section 136. Decoration data is determined, and at the same time, audio data constituting the audio to be output from the speaker 128 is determined. Then, the performance control means 334 executes the determined game performance. Note that the production also includes auxiliary production. In the winning type lottery, when a selected winning type in which a correct winning combination (a specific winning combination) and an incorrect winning combination overlap is won, the correct answer of the stop switches 120a, 120b, and 120c, which is the winning condition for the correct winning combination, is used as an auxiliary performance. This is a performance that notifies you of the operation mode. With this auxiliary performance, the player can easily display the symbol combination corresponding to the correct winning combination on the active line A. A performance state in which such an auxiliary performance is executed is called an AT (assist time) performance state. In addition, a so-called ART gaming state may be used in which an AT performance state and an RT (replay time) gaming state in which the probability of winning a replay combination is high are proceeded in parallel.

In the following, notifications managed by boards other than the main control board 200, including the sub-control board 202, such as the liquid crystal display section 124, the production lamp 126, the speaker 128, the sub-credit display section 134, and the sub-payout display section 136, will be described. The means may be referred to as other notification means. On the other hand, notification means managed by the main control board 200, such as the main credit display section 130 and the main payout display section 132, are sometimes referred to as main notification means (instruction monitor). Further, the main notification means and other notification means capable of executing the auxiliary performance may be collectively referred to as auxiliary performance execution means. The performance state control means 314 causes the auxiliary performance execution means to execute the auxiliary performance in the AT performance state.

(Table used in main control board 200)
FIG. 5 is an explanatory diagram for explaining the winning combination, and FIGS. 6 and 7 are explanatory diagrams for explaining the winning type lottery table.

In the slot machine 100, as will be described in detail later, a plurality of types of gaming states and performance states are provided, and the gaming state and performance state are changed according to the progress of the game. In the main control board 200, a plurality of winning type lottery tables and the like corresponding to gaming states managed and controlled by the gaming state control means 312 are stored in the main ROM 200b. The winning type lottery means 304 draws a corresponding winning type lottery table into the main ROM 200b according to the current setting value (indicating the ease of obtaining a gaming profit in stages) stored in the main RAM 200c and the current gaming state. Based on the extracted winning type lottery table, it is determined which winning type lottery random number acquired in response to the operation signal of the start switch 118 corresponds to which winning type in the winning type lottery table.

Here, the winning combinations constituting the winning types extracted in the winning type lottery table include a replay winning combination, a minor winning combination, and a bonus winning combination. The replay combination is a combination that allows the player to play the game again without making a new bet for medals when a symbol combination corresponding to the replay combination is displayed on the active line A. A small winning combination is a winning combination in which a symbol combination corresponding to the small winning combination is displayed on the active line A, so that a predetermined number of medals can be paid out according to the symbol combination. In addition, for a bonus role, the symbol combination corresponding to the bonus role is displayed on the active line A, thereby changing the gaming state managed by the gaming state control means 312 to a bonus gaming state (a gaming state during RBB operation, which will be described later). This is a role that can be transitioned to.

As for the winning combination in this embodiment, as shown in FIG. 5, a winning combination "RBB" is provided as a bonus combination. In addition, winning combinations "Replay 1" to "Replay 7" are provided as replay combinations. In addition, as small prizes, winning prizes "small prize 1" to "small prize 45" are provided. In FIG. 5, one or more symbols constituting each winning combination are associated with each of the left reel 110a, middle reel 110b, and right reel 110c. In addition, in the following, the winning roles "Small role 1" to "Small role 17" will be referred to as the winning role "15 cards", the winning role "Small role 18" will be referred to as the winning role "14 cards", and the winning role "Small role 19". , "Small win 20" may be abbreviated as the winning combination "3-card combination," and the winning combinations "Small combination 21" to "Small combination 45" may be abbreviated as the winning combination "1-card combination."

Here, in this embodiment, when the stop switch 120 is operated by the player, if the symbols constituting the symbol combination corresponding to the winning combination that can be won are on the active line A, the reel control means At step 306, stop control is performed so that the symbol stops on the active line A. In addition, when the stop switch 120 is operated, the symbols constituting the symbol combination corresponding to the winning combination that can be won are not on the active line A, but four symbols in the opposite direction to the rotation direction of the reel 110 are displayed. If the number of symbols is within the range corresponding to the winning combination (draw-in range), the reel control means 306 sets the number of symbols that are apart from each other as the number of sliding symbols, and activates the symbols constituting the symbol combination corresponding to the winning combination. Stop control is performed so that the rotation is maintained for the number of sliding frames so as to be drawn onto line A, and then stopped. In addition, if there are multiple symbols on the reels 110 that correspond to winning combinations that can be won, and all of them are within the pull-in range of the reels 110, any of the symbols will be placed on the active line A according to a predetermined priority order. It is determined whether to draw the symbol upward, and stop control is performed so that the rotation is maintained for the number of sliding pieces so as to draw the prioritized symbol onto the active line A and then stopped. Note that when the stop switch 120 is pressed and a symbol that constitutes a symbol combination corresponding to a winning combination other than a winning combination that can be won is on the active line A, the reel control means 306 controls the symbol combination to A so-called kicking process is also executed in parallel to prevent the line from stopping on the effective line A. In addition, as will be described later, if the winning combination included in the winning type has an operation mode (operation order and operation timing) set as a winning condition, the reel control means 306 controls the winning combination according to the player's operation mode. Stop control is performed so that the symbol combination corresponding to the symbol combination can be displayed on the active line A.

For example, the symbols constituting the symbol combinations corresponding to the winning combination "Replay 1" and the winning combination "Small combination 17" are ensured to be displayed on the active line A on each reel 110 by the above-mentioned stop control. are arranged in Such a winning combination may be expressed as PB=1. On the other hand, for example, the symbols constituting the symbol combinations corresponding to the winning combination "Replay 2", the winning combinations "Small combination 1" to "Small combination 16", and the winning combination "RBB" are controlled by the above-mentioned stop control on each reel 110. Therefore, since the images are not necessarily arranged so as to be displayable on the effective line A, so-called omission may occur. Such a winning combination may be expressed as PB≠1.

As shown in FIGS. 6 and 7, in the winning type lottery table, multiple winning areas are divided, and the winning types that are subject to lottery differ depending on each game state, and the presence or absence of non-winning (loss) differs depending on each game state. or In FIGS. 6 and 7, the winning areas ( Although the winning type (winning type) is represented by "◎" or "○", in reality, a winning type lottery table corresponding to each of a plurality of gaming states is stored in the main ROM 200b. In addition, "◎" indicates that it is an advantageous section lottery possible winning type where a lottery to move to an advantageous section can be held, and "○" is a non-advantageous section lottery where it is impossible to conduct a lottery to transfer to an advantageous section. Indicates that it is a winning type.

In the winning type lottery table, each divided winning area is associated with a predetermined number (winning range value) that is a numerical value indicating the winning range, and the winning type. The total number of winning type lottery random numbers (65536) is obtained by summing up the numbers placed in the winning areas. Therefore, the probability that each winning type is determined is the value obtained by dividing the number associated with the winning area by the total number of winning type lottery random numbers. The winning type lottery means 304 sequentially obtains numbers from among the plurality of winning areas in the winning type lottery table, starting from the one with the highest number, based on the gaming state at that time, and uses the numbers as a winning type lottery random number. When the value after subtraction becomes less than 0, the winning type associated with the winning area at that time is determined as the lottery result of the winning type lottery. In addition, if the numbers of all the winning areas of winning area 1 and above are subtracted from the winning type lottery random number, and the value after subtraction is 0 or more, the winning type of winning area 0 is "lose". This is the lottery result.

Here, we will supplement the winning combination "RBB" that constitutes the winning type "RBB". The predetermined type 1 special accessory RB is an accessory that increases the number of combinations of symbols related to winnings for each specified number, or increases the probability that a conditional device related to winnings for each specified number will operate, and is predetermined. It is said to be able to operate when the game is played and continue to operate until the result of the game is obtained not more than 12 times. Here, the condition device is a device whose operation is a necessary condition for displaying a combination of symbols related to winning, replay, accessory, or operation of the accessory continuous operation device, A winning flag is a flag that is activated when a player wins a computer-based lottery held in a gaming machine. And, the accessory continuous activation device (winning combination "RBB") related to the first type special accessory that constitutes the winning type "RBB" is a device that can continuously operate the first type special accessory RB. This refers to a device that operates when a specific combination of symbols is displayed and ends the operation in a predetermined case.

According to the winning type lottery tables in FIGS. 6 and 7, for example, winning area 0 is associated with the winning type "Lose", and if you win this winning type, you will be eligible for any of the winning combinations shown in FIG. The corresponding symbol combination is also not displayed on the active line A, and no medals are paid out.

In addition, the winning area 1 is associated with the winning type "Small role ALL" which includes (wins) the winning roles "Small role 1" to "Small role 45" overlappingly, and the winning area 2 is , the winning type "3 pieces ALL" which includes the winning combinations "Small combination 19" and "Small combination 20" is associated, and the winning area 3 includes the winning combinations "Small combination 21" to "Small combination". The winning type "1 piece ALL" which includes "combination 45" is associated with the winning type "1 piece ALL".

Furthermore, the winning areas 4 to 7 are associated with the winning types "Replay 1" to "Replay 4" which include the winning combinations "Replay 1" to "Replay 7" in duplicate. In addition, below, the four winning types of winning areas 4 to 7 may be simply abbreviated as winning type "replay."

In addition, in winning areas 8 to 31, one of the correct winning combinations with a payout number of 15 pieces (winning combinations "Small Role 1" to ``Small Role 16'') and the incorrect winning combination with a payout number of 1 coin (winning combination). Selected winning types that overlap with any of the following ("Small role 21" to "Small role 40") ~ “Batting order bell A red 4”, “batting order bell B blue 1” ~ “batting order bell B blue 4”, “batting order bell B red 1” ~ “batting order bell B red 4”, “batting order bell A1” ~ “batting order bell A4," "batting order bell B1" to "batting order bell B4," respectively. Note that, hereinafter, the 24 winning types in winning areas 8 to 31 may be simply abbreviated as winning type "batting order bell."

In addition, in the winning areas 32 to 41, there is a winning combination "minor prize 18" in which the number of coins to be paid out is 14, a winning prize "minor prize 17" in which the number of coins to be paid out is 15 coins, and a winning prize in which the number of coins to be paid out is 1 coin. Contains duplicate roles such as "Small role 21", "Small role 22", "Small role 27", "Small role 28", "Small role 35", "Small role 36", and "Small role 43" The winning types "batting order chance 1" to "batting order chance 10" are associated with each other. Note that in the following, the ten winning types in the winning areas 32 to 41 may be simply abbreviated as the winning type "batting order chance."

In addition, in the winning areas 42 and 43, there are the winning combinations "Small combination 20" with a payout number of 3 pieces, and the winning combinations "Small combination 25", ``Small combination 26'', and ``Small combination 20'' with a payout number of 1 piece. The winning types "Common 3 pieces 1" and "Common 3 pieces 2" which include either "27" or "Small winning combination 28" are associated, respectively. In addition, below, the two winning types of the winning areas 42 and 43 may be simply abbreviated as the winning type "common 3 tickets".

In addition, in the winning area 44, the winning winnings “RBB”, the small winnings “small winning 21”, “small winning 23”, “small winning 24” (the first small winning), and “small winning 45” (the first small winning) are shown. The winning type "common 1 piece" (specific winning type) that includes the 2 small winnings) is associated with the winning type. Furthermore, the winning area 45 is associated with a winning type "Watermelon" which includes the winning winning combination "RBB" and the small winning combination "minor winning 43" overlappingly. Furthermore, the winning area 46 is associated with a winning type "Chance A" in which the winning winning combination "RBB" and the small winning combination "minor winning combination 44" are duplicated. Furthermore, the winning area 47 is associated with a winning type "Chance B" which includes the winning winning combination "RBB" and the small winning combination "minor winning 19" overlappingly. In addition, below, the two winning types of the winning areas 46 and 47 may be simply abbreviated as the winning type "chance".

Furthermore, the winning area 48 is associated with a winning type "weak cherry" in which the winning winning combination "RBB" and the small winning combination "minor winning combination 41" are duplicated. Furthermore, the winning area 49 is associated with a winning type "Strong Cherry" which includes the winning winning combination "RBB" and the small winning combination "minor winning 42" overlappingly. Furthermore, the winning area 50 is associated with a winning type "RBB" which includes the winning combination "RBB" alone. It should be noted that if the winning areas 44 to 49 are won in the RBB internal medium game state, only the small winning combination will be won.

If you win a winning type that includes multiple winning combinations, the winning conditions regarding which symbol combination corresponding to the winning combination will be preferentially displayed on the active line A, such as stop The order in which the switches 120a, 120b, and 120c are operated and the operation timing (operating position of the reel 110) of the stop switches 120b and 120c are set.

In the following explanation, the operation of the stop switches 120a, 120b, and 120c that stop the reels in the order of the left reel 110a, the middle reel 110b, and the right reel 110c will be referred to as "batting order 1", and The operation of the stop switches 120a, 120b, 120c to stop the reels in order is called "batting order 2", and the operation of the stop switches 120a, 120b, 120c to stop the reels in order of the middle reel 110b, left reel 110a, right reel 110c is called "batting order 2". 3", and the operation of the stop switches 120a, 120b, 120c to stop the reels in the order of the middle reel 110b, right reel 110c, and left reel 110a is "batting order 4", and the operation of the stop switches 120a, 120b, and 120c is set as "batting order 4", and the reels are stopped in the order of the right reel 110c, the left reel 110a, and the middle reel 110b. The operation of the stop switches 120a, 120b, 120c to stop the reels is defined as "batting order 5", and the operation of the stop switches 120a, 120b, 120c to stop the reels in the order of right reel 110c, middle reel 110b, and left reel 110a is "batting order 6". ”.

In addition, in "batting order 3", if the stop switch 120b is operated at the timing when the symbols with symbol numbers 1 to 10 arranged on the middle reel 110b are located on the active line A, "batting order 3 blue" (in the figure is blue)", and when the stop switch 120b is operated at the timing when the symbols numbered 0, 11 to 19 arranged on the middle reel 110b are located on the active line A, "batting order 3 red (in the figure is red). Similarly, in "batting order 4", the stop switch 120b is operated at the timing when the symbols numbered 1 to 10 arranged on the middle reel 110b are located on the active line A, "batting order 4 blue", The operation of the stop switch 120b at the timing when symbols numbered 0, 11 to 19 arranged on the middle reel 110b are positioned on the activated line A is defined as "batting order 4 red". In addition, in "batting order 5" and "batting order 6", the stop switch 120c is operated at the timing when the symbols numbered 1 to 10 arranged on the right reel 110c are located on the active line A. "Batting Order 5 Blue", "Batting Order 6 Blue", and "Batting Order 6 Blue" indicate that the stop switch 120c is operated at the timing when symbols numbered 0, 11 to 19 arranged on the right reel 110c are located on the active line A. batting order 5 red" and "batting order 6 red."

For example, in the RBB internal medium game state described later, if the winning type "batting order bell A blue 1" in winning area 8 is won and the correct operation mode (batting order 3 blue) is performed, the number of payouts is 15. Stop control is performed so that the symbol combination corresponding to the winning combination "Small combination 1" which is the correct combination is preferentially displayed on the active line A. In addition, when operations are performed using batting order 1 or batting order 2, the symbol combination corresponding to the winning combination "1-card combination", which is an incorrect combination with a payout of 1 card, will be preferentially displayed on active line A. When the stop control is performed and the operation is performed with batting order 3 red, batting order 4 (batting order 4 blue, batting order 4 red), the symbol corresponding to the winning combination "1 card combination" which is an incorrect combination with a payout number of 1 card. If the stop control is performed so that the combination is preferentially displayed on the active line A with a probability of 1/2, and the operation is performed using batting orders 5 and 6, a winning combination that is an incorrectly answered combination with a payout number of 1 coin is performed. Stop control is performed so that the symbol combination corresponding to the "one-card combination" is preferentially displayed on the active line A with a probability of 1/4.

Note that the winning probability (number) of each winning type in winning areas 8 to 23 is set to be equal. Further, the winning probability (number) of each winning type in the winning areas 24 to 31 is set to be equal. Since the player usually cannot know which winning type he has won, by providing the winning areas 8 to 31 as described above, it is difficult for the player to win the correct winning combination. Further, as described above, even if the stop switches 120a, 120b, and 120c are operated in an operation mode in which the incorrect combination is displayed preferentially, the symbol combination corresponding to the incorrect combination is not necessarily displayed on the active line A. Therefore, depending on the operation mode, there may be spillage (PB≠1).

In addition, when winning any of the above-mentioned winning types, the internal winning flag corresponding to each winning type is established (ON), and the stop control of each reel 110 is performed according to the establishment status of this internal winning flag. The Rukoto. At this time, if you win a winning type that includes a minor winning combination, but the symbol combination corresponding to these winning combinations cannot be displayed on the active line A in the game, after the game ends. The internal winning flag is turned off. In other words, the right to win a minor prize is limited only to the game in which the winning type that includes the minor prize is won, and the right cannot be carried over to the next game. On the other hand, if a winning type that includes the winning combination "RBB" is won, the RBB internal winning flag is established (ON) and the symbol combination corresponding to the winning combination "RBB" is placed on the active line A. The RBB internal winning flag is carried over across games until it is displayed. Furthermore, if the internal winning flag corresponding to a winning type that includes a replay combination is established, the symbol combination corresponding to one of the replay combinations included in that winning type will always be on the active line A. After the process necessary to play the next game without requiring medals is performed, the internal winning flag is turned off.

(Transition of gaming state)
Here, the transition of the gaming state will be explained using FIG. 8. Here, a plurality of gaming states are prepared, such as a non-internal gaming state, an RBB internal gaming state, and an RBB active gaming state. As will be described later, each gaming state is changed depending on winning, winning (activation), and termination of a bonus combination.

The non-internal gaming state is a gaming state that corresponds to an initial state among a plurality of gaming states. In such a non-internal gaming state, the probability of winning a replay combination is set to approximately 1/7.3. Furthermore, in the non-internal gaming state, the winning combination "RBB" is determined with a predetermined probability (for example, about 1/10).

The gaming state control means 312 changes the gaming state in response to winning of the winning combination "RBB". For example, in a game in which the winning combination "RBB" is won, when a symbol combination corresponding to the winning combination "RBB" is displayed on the active line A, the gaming state control means 312 changes the gaming state to the RBB active gaming state. Transfer (1).

In the RBB active gaming state, the winning probability of the replay combination is set to 0. In addition, in such a gaming state during RBB operation, the winning types that can be won are the winning type "Small win ALL" in the winning area 1, the winning type "3 pieces ALL" in the winning area 2, and the winning type "1" in the winning area 3. ``All sheets'' is set. If you win the winning type "Small role ALL", a symbol combination corresponding to any of the winning roles "Small role 1" to "Small role 45" will be displayed on the active line A, and you will win the winning type "3 pieces ALL". Then, the symbol combination corresponding to either the winning combination "Small combination 19" or "Small combination 20" is displayed on the active line A, and if the winning type "1 piece ALL" is won, the winning combination "Small combination 21" is displayed. The stop control is performed so that the symbol combination corresponding to any one of the "small winning combinations 45" is displayed on the active line A. Here, due to the configuration of such small winning combinations, the expected number of coins to be acquired per unit game in the gaming state during RBB operation is lowered.

When the condition for ending the gaming state during RBB operation is satisfied, that is, when the number of acquired coins reaches a predetermined number, the gaming state control means 312 shifts the gaming state to a non-internal gaming state (2).

On the other hand, in a game in which the winning combination "RBB" is won, if the symbol combination corresponding to the winning combination "RBB" cannot be displayed on the active line A, the gaming state control means 312 controls the gaming state within the RBB. Shift to medium game state (3).

In the RBB internal medium game state, the winning probability of the replay combination is set to approximately 1/5.9. Further, in the RBB internal medium game state, there is no possibility of winning the winning type "losing". In other words, if the symbol combination corresponding to the winning combination "RBB" could not be displayed on the active line A in a winning game with the winning combination "RBB", after that, the winning combination "RBB" would be smaller than the winning combination "RBB". Since the replay combination is controlled to stop on the active line A with priority, the symbol combination corresponding to the winning combination "RBB" cannot be displayed on the active line A. Therefore, once the gaming state shifts to the RBB internal medium gaming state, the RBB internal medium gaming state will be maintained without any subsequent gaming state transition. Here, while maintaining the RBB internal medium gaming state, an AT effect state is realized in the RBB internal medium gaming state.

Here, in the RBB internal medium game state, multiple types of correct combinations are won without overlapping each other, so it is possible to increase the chances of winning the correct combination, and as a result, for example, in the RBB internal medium game By performing the auxiliary performance in the AT performance state, medals can be easily obtained. On the other hand, in the RBB active gaming state, multiple types of correct winning combinations are won over and over again, so there are fewer opportunities to win the correct winning combination, so the correct winning combination is more likely to win than in the AT production state in other gaming states. This makes it difficult for players to increase the number of medals they own. Therefore, while the RBB active gaming state has the function of having a higher probability of winning winning combinations than the RBB internal playing state, in terms of medal acquisition performance, the RBB operating gaming state is the same as the RBB internal mid gaming state. It is possible to realize the specifications (accelerator RBB) that are inferior.

(Transition of production state)
FIG. 9 is an explanatory diagram for explaining the transition of the performance state. Hereinafter, the effect state to which the effect state control means 314 changes in the main control board 200 will be described in detail. In addition, below, the case where the gaming state is the RBB internal medium gaming state will be explained.

Here, in order to comprehensively and uniformly determine whether or not the gaming state with high medal acquisition performance is biased, a game section having performance related to the instruction function, that is, an auxiliary performance (instruction function) is executed. A game section that is advantageous to the player, including a game section, etc., is defined as an advantageous section. In addition, in the advantageous section, if the auxiliary effect is activated as a result of a lottery etc. related to the activation of the auxiliary effect on the main control board 200, the main control board 200 will be able to identify the content of the instruction. This is a game period in which information indicating the contents of the instruction may be transmitted to peripheral boards such as the sub-control board 202 only when displayed on the means. Further, unlike the advantageous section, a game section in which the auxiliary performance (instruction function) cannot be executed is defined as a non-advantageous section. Therefore, the plurality of performance states belong to either the advantageous section or the non-advantageous section which are the game sections. In this embodiment, almost all performance states belong to the advantageous section, and some performance states (here, the first game in the non-advantageous standby performance state) realize the non-advantageous section.

In addition, in the advantageous section, among the winning modes in which the correct winning combination would be missed if there is no auxiliary performance, in the selection winning type where the correct winning combination has the maximum payout (in this case, 15 coins), there will be assistance to assist the winning of the correct winning combination. When performing a performance (an auxiliary performance in which the maximum number of coins to be paid out can be obtained), the effect must be notified by, for example, lighting the section display 160.

In addition, in the non-advantageous section, it is possible to vary the winning probability for each winning type depending on the setting value, but the probability that determines the transition to the performance state with auxiliary performance (AT performance state) for the same winning type must not be different for each setting value. On the other hand, in the advantageous section, both the winning probability of the winning type and the probability of determining the transition (or addition) to the performance state with auxiliary performance (AT performance state) for the same winning type differ depending on the setting value. It is possible to do so.

Therefore, the performance state control means 314 not only manages the transition of the performance state, but also manages the transition between the non-advantageous section and the advantageous section. Furthermore, regardless of such management, the advantageous section is forcibly terminated when the following termination conditions are met. For example, the game is forcibly terminated when the value counted in the advantageous section reaches a predetermined value (for example, the number of staying games reaches 1500 games or the net increase in the number of coins exceeds 2400 coins). In either case, the performance state control means 314 resets all the information updated in the advantageous section (all variables that affect the performance related to the instruction function) by transitioning from the advantageous section to the non-advantageous section. .

(Non-AT performance state, AT performance state)
In the non-AT performance state, the frequency of execution of auxiliary performances is extremely lower than in the AT performance state, and since auxiliary performances are almost never performed, the number of medals that can be acquired is limited. Here, six performance states are provided as non-AT performance states: normal performance state, CZ performance state (chance zone performance state), specialized zone performance state, advantageous standby performance state, non-advantageous standby performance state, and pullback performance state. It is being

In the AT performance state, by causing the auxiliary performance execution means to perform the auxiliary performance when the selected winning type is won, it is possible to obtain a large number of medals while suppressing the consumption of medals. Therefore, by shifting to the AT performance state, the player can advance the game more advantageously than in the non-AT performance state. Here, four performance states are provided as AT performance states: OP performance state (opening performance state), normal AT performance state, continuous performance state, and special specialized zone performance state. Each production state will be explained individually below.

(Each production state)
The normal performance state is a performance state corresponding to an initial state among a plurality of performance states. The performance state control means 314 performs the CZ lottery in the normal performance state. The CZ lottery is a lottery to determine the transition to the CZ performance state, and the performance state control means 314 performs the CZ lottery with different probabilities for each winning type determined by the winning type lottery, as will be described in detail later. If the CZ lottery is won in the normal performance state, the performance state control means 314 shifts the performance state to the CZ performance state (1).

In the CZ performance state, the performance state control means 314 performs an AT lottery. The AT lottery is a lottery to determine the transition to the AT performance state (normal AT performance state), and the performance state control means 314 performs the AT lottery with different probabilities for each winning type determined by the winning type lottery. If the AT lottery is won in the CZ performance state, the performance state control means 314 shifts the performance state to the OP performance state, which is the AT performance state (2). Note that the CZ performance state can be said to be a performance state more advantageous than the normal performance state because it may be determined to shift to the normal AT performance state in which auxiliary performance is executed.

On the other hand, when a predetermined end condition (for example, a predetermined number of games are played without winning the AT lottery) is satisfied in the CZ performance state, the performance state control means 314 shifts the performance state to the normal performance state ( 3).

In addition, it is possible to set a predetermined ceiling condition (for example, normal performance state, CZ performance state, and pullback performance state (these are collectively 1 state) without shifting to any other presentation state (the number of ceiling games have elapsed) is established (so-called reaching the ceiling), the presentation state control means 314 shifts the presentation state to the OP presentation state. (2), (4).

In the OP performance state, the auxiliary performance is executed until a predetermined end condition (for example, the correct winning type is won five times and the auxiliary performance is executed five times) is satisfied. Then, when a predetermined end condition is satisfied in the OP performance state, the performance state control means 314 shifts the performance state to the specialized zone performance state (5). In the specialized zone performance state, the difference number of coins (net increase number) that can be acquired in the normal AT performance state to which the state will be transferred later is determined by lottery. The specialized zone performance state continues for 15 games, for example, and after 15 games have passed, the performance state control means 314 shifts the performance state to the normal AT performance state (6).

In the normal AT performance state (second state), the auxiliary performance is executed until a predetermined end condition (for example, obtaining the difference number of medals determined in the specialized zone) is satisfied. That is, the normal AT effect state is an AT effect state of the difference number management type. When a predetermined termination condition is satisfied in the normal AT performance state, the performance state control means 314 shifts the performance state to a standby performance state indicated by a dashed line (7), (8).

The standby performance state includes an advantageous standby performance state that is an advantageous section and a non-advantageous standby performance state that is a non-advantageous section. Although detailed explanation will be given later, in the final game in the normal AT performance state, the performance state control means 314 performs a continuous lottery to determine whether to transition (continue) to the normal AT performance state again. If the continuous lottery is won, the performance state control means 314 continues the advantageous section and temporarily shifts the performance state to an advantageous standby performance state (7). Furthermore, even if the continuation lottery is not won, the performance state control means 314 performs an advantageous continuation lottery when specific conditions are satisfied, and when the advantageous continuation lottery is won, the performance state control means 314 continues the advantageous section and maintains the performance state. is shifted to an advantageous standby performance state (7). On the other hand, if you do not win the continuous lottery and the specific conditions are not met, or if you do not win the advantageous continuous lottery even if the specific conditions are met, the production state control means 314 temporarily closes the advantageous section. At the same time as shifting to a non-advantageous section, the performance state is shifted to a non-advantageous standby performance state (8).

The standby performance state continues for two games whether it is an advantageous standby performance state or a non-advantageous standby performance state. If the continuous lottery is won and the state is shifted to the advantageous standby performance state, the performance state control means 314 shifts the performance state to the continuous performance state after two games have passed (9).

Further, if the player does not win the continuous lottery, and wins the advantageous continuous lottery and shifts to the advantageous standby performance state, the performance state control means 314 performs the continuous lottery in each of the two games. Then, after two games have passed, the performance state control means 314 shifts the performance state to the continuous performance state, regardless of whether the continuous lottery is won or not (9).

On the other hand, when the state is shifted to the non-advantageous standby performance state, in the first game, the performance state control means 314 performs an advantageous section shift lottery to determine whether or not to shift to the advantageous section. In addition, in the advantageous section transfer lottery of this embodiment, the winner is sure to win. Therefore, the performance state control means 314 shifts the game section to the advantageous section when the first game in the non-advantageous standby performance state ends. Further, when the state is shifted to the non-advantageous standby performance state, the performance state control means 314 performs a continuous lottery in each of the two games. Then, after two games have passed, the performance state control means 314 shifts the performance state to the continuous performance state, regardless of whether the continuous lottery is won or not (10).

The continuous performance state continues until a predetermined end condition (for example, 10 games have passed) is satisfied, and during that time, the performance control means 334 notifies the lottery result of the continuous lottery. If the player has won the continuous lottery, the performance state control means 314 shifts the state to the specialized zone performance state again (11). On the other hand, if the continuous lottery has not been won, the performance state control means 314 shifts the performance state to the return performance state (12). In addition, in the continuous performance state, when the continuous lottery has not been won, a so-called rewriting lottery may be performed in which the transition to the normal AT performance state is determined by lottery.

The pullback effect state continues until a predetermined end condition (for example, 30 games have passed) is satisfied, and during that time, the effect state control means 314 performs a pullback lottery in the normal AT effect state. Then, when winning the pullback lottery, the performance state control means 314 shifts the performance state to the specialized zone performance state (13). On the other hand, if the termination condition is satisfied without winning the pullback lottery, the performance state control means 314 shifts the performance state to the normal performance state (14).

By the way, in the normal performance state, CZ performance state, and pullback performance state shown by broken lines, when a predetermined winning type (for example, winning type "Replay 3", "Replay 4") is won by the winning type lottery, The effect state control means 314 determines by lottery whether or not to execute the lock 3 reel effect (freeze effect), which will be described in detail later. Then, when it is decided to execute the reel effect of lock 3, the reel control means 306 executes the reel effect of lock 3, and the effect state control means 314 changes the effect state to the special specialized zone effect state in the next game. (15).

The special specialized zone performance state is more advantageous to the player than the specialized zone performance state. Specifically, in the special specialized zone performance state, similar to the specialization zone performance state, the difference number (net increase number) that can be obtained in the normal AT performance state that will be transferred later will be determined by lottery. The determined difference number of sheets is more likely to be determined to be a larger value than in the specialized zone production state. For example, in the special specialized zone presentation state, a total of 2400 coins, which is the maximum net increase in the number of coins that can be acquired in one advantageous section, is determined. Note that the special specialized zone performance state may be shifted to the special specialized zone performance state not only when execution of the lock 3 reel performance is determined but also when a specific condition, which will be described in detail later, is satisfied.

Then, when the special specialized zone performance state ends, the performance state control means 314 shifts the performance state to the normal AT performance state (16).

(Details of normal performance state)
FIG. 10 is a diagram illustrating the internal state of the normal performance state. FIG. 11 is a diagram illustrating the status up lottery table. The normal performance state described above is provided with a plurality of internal states in which the probability of transition to the CZ performance state, that is, the probability of winning the CZ lottery differs. Specifically, as shown in FIG. 10, the normal performance state is provided with four internal states: a low accuracy state, a normal state, a high accuracy state, and a super accurate state. The low probability state is the state in which it is most difficult to win the CZ lottery. The normal state is a state where it is easier to win the CZ lottery than the low probability state, and it is more difficult to win the CZ lottery than the high probability state and the very high probability state. The high probability state is a state in which it is easier to win the CZ lottery than the low probability state and the normal state, and it is more difficult to win the CZ lottery than the ultra-high probability state. The super-certain state is the state in which it is most likely to win the CZ lottery.

When the normal AT performance state ends and the continuous lottery is not won and the performance state is transferred to the normal performance state via the pullback performance state, as shown in FIG. 10, the performance state control means 314 Set the internal state to low certainty. Therefore, at the beginning of the transition to the normal performance state, it is difficult to win the CZ lottery.

In the normal performance state, the performance state control means 314 performs a state-up lottery every game by referring to the state-up lottery table shown in FIG. According to the status up lottery table, a winning probability is set for each winning type determined by the winning type lottery means. In the status up lottery table, the winning type "strong cherry", which has the highest winning probability in the CZ lottery, which will be described in detail later, is also set to have the highest winning probability in the status up lottery. Therefore, when winning the winning type "Strong Cherry", not only the expectation that the player has won the CZ performance state but also the expectation that he has won the state-up lottery even if he does not win the CZ lottery increases.

Then, if the state-up lottery is won in the low probability state, the performance state control means 314 shifts the internal state to the normal state. Further, when winning the state-up lottery in the normal state, the effect state control means 314 shifts the internal state to the high-certain state. Further, when winning the state-up lottery in the high-certainty state, the performance state control means 314 shifts the internal state to the super-high-certainty state. In this way, the performance state control means 314 shifts the internal state to a state where the probability of winning the CZ lottery is high every time the state-up lottery is won.

Then, regardless of the internal state, if the CZ lottery is won, the performance state control means 314 shifts the performance state to the CZ performance state. After that, if the performance state is transferred to the normal performance state without winning the AT lottery in the CZ performance state, the performance state control means 314 changes the internal state to one of the normal state, high accuracy state, and super high accuracy state. transfer to crab. Note that the normal state, high-accuracy state, or ultra-high-accuracy state may be determined by lottery, or the transition may be made to transition to a preset internal state every time the transition to the normal performance state occurs. good.

In this way, in the slot machine 100, when the slot machine 100 is initially shifted to the normal performance state, it is shifted to the low probability state where it is least likely to win the CZ lottery, but the internal state is promoted by winning the state-up lottery. Furthermore, when transitioning from the CZ presentation state to the normal presentation state, the internal state is transferred to an internal state other than the low probability state in which it is most difficult to win the CZ lottery.

FIG. 12 is a diagram explaining the CZ lottery table. When the internal state of the normal performance state is a low probability state, the performance state control means 314 performs a CZ lottery with reference to the CZ lottery table for the low probability state shown in FIG. 12(a). Further, when the internal state of the normal performance state is the normal state, the performance state control means 314 performs the CZ lottery with reference to the CZ lottery table for the normal state shown in FIG. 12(b). Further, when the internal state of the normal performance state is a high probability state, the performance state control means 314 performs a CZ lottery with reference to the CZ lottery table for the high probability state shown in FIG. 12(c). Further, when the internal state of the normal performance state is a super high probability state, the production state control means 314 performs a CZ lottery by referring to the CZ lottery table for the super high probability state shown in FIG. 12(d).

According to the CZ lottery table shown in FIGS. 12(a) to 12(d), a probability (winning probability) for determining transition to the CZ performance state is set for each winning type. Therefore, the performance state control means 314 performs the CZ lottery by referring to any of the CZ lottery tables shown in FIGS. 12(a) to 12(d) based on the winning type determined by the winning type lottery. It turns out.

Furthermore, as is clear from the CZ lottery tables shown in FIGS. 12(a) to 12(d), it is easier to win the CZ lottery in the order of low probability state, normal state, high probability state, and super high probability state. is being done. Therefore, immediately after the normal AT performance state ends and the player does not win the continuous lottery and the performance state is transferred to the normal performance state via the pullback performance state, the player stays in a low probability state and does not win the CZ lottery. Since it is difficult to shift to the CZ performance state, the possibility of winning the AT lottery is also low.

On the other hand, if you win the state-up lottery or win the CZ lottery, your internal state will be either normal, or you will definitely transition to a high-certain state or ultra-high-certain state with a higher probability of winning than the normal state. Become. Therefore, the longer the number of games played in the normal performance state, the more likely it is to win the CZ lottery, and since it is easier to shift to the CZ performance state, the possibility of winning the AT lottery also increases. Thereby, the more the player plays the game, the more the player's desire to play the game increases.

Here, in the CZ lottery table shown in FIGS. 12(a) to 12(d), when it is decided to execute Lock 1 and Lock 2 as reel effects, which will be described in detail later, the winning type determined by the lottery Instead of the type, the CZ lottery is performed with the winning type "Lock 1" or the winning type "Lock 2". The winning type "Lock 1" and the winning type "Lock 2" are set to have a higher winning probability in the CZ lottery than the winning type won when the reel performance is determined. Therefore, when the reel performances of Lock 1 and Lock 2 are executed, the player's sense of expectation can be further heightened, and the player's desire to play can be improved.

(Normal performance mode)
FIG. 13 is a diagram illustrating the mode of the normal performance state. The normal performance state described above is managed by any one of a plurality of modes in addition to the internal state described above. In the normal performance state, there are four modes (transition conditions), mode A to mode D, as shown in FIG. 13(a). Modes A to D have different ceiling conditions, that is, the number of games until reaching the ceiling (hereinafter referred to as the number of ceiling games). In mode A, the number of ceiling games is set to 999 games, in mode B, the number of ceiling games is set to 777 games, in mode C, the number of ceiling games is set to 500 games, and in mode D In this case, the ceiling number of games is set to 100 games. Therefore, mode A can be said to be a disadvantageous condition because the number of ceiling games is larger than modes B to D, and the consumption of medals increases until the ceiling number of games is reached. Moreover, mode D can be said to be an advantageous condition compared to modes A to C because the number of ceiling games is smaller.

Then, in the second game in the non-advantageous standby performance state, the performance state control means 314 refers to the mode lottery table for the non-advantageous standby performance state shown in FIG. The mode will be determined by mode lottery. According to the mode lottery table in the non-advantageous standby performance state, mode B is determined with a 50% probability, mode C is determined with a 40% probability, and mode D is determined with a 10% probability. It should be noted that if the continuous lottery is won in the non-advantageous standby performance state, the mode lottery will not be performed.

Further, when winning the advantageous continuation lottery, in the second game in the advantageous standby performance state, the performance state control means 314 refers to the mode lottery table at the time of winning the advantageous continuation lottery shown in FIG. 13(c), and then The mode of the normal performance state to be transferred is determined by a mote lottery. According to the mode lottery table at the time of winning the advantageous continuation lottery, mode D is determined with a 100% probability. It should be noted that if the continuous lottery is won in the advantageous standby performance state, the mode lottery will not be performed. Therefore, if the continuous lottery is won in the normal AT presentation state, the mode lottery is not performed. That is, the mode lottery is performed only when the player wins the advantageous continuation lottery and does not win the subsequent continuation lottery. In such a case, you will not transition to the normal AT performance state via the specialized zone performance state, but will transition to the normal performance state via the pullback performance state, but after 100 games have passed, the ceiling It is possible to quickly return to the AT performance state (normal AT performance state).

By the way, when changing the settings, information such as the gaming state, performance state, and gaming section will be reset (initialized), so the gaming state will become a non-internal gaming state and the gaming section will become a non-advantageous section. . Further, the performance state at the time of setting change is set to a non-advantageous standby performance state.

Then, in the first game after the setting change, that is, the first game in the non-advantageous standby performance state, the advantageous section lottery is definitely won and the game section is shifted to the advantageous section. On the other hand, since the winning probability of the winning type including the winning combination "RBB" is about 1/10, the gaming state is unlikely to shift from the non-internal gaming state to another gaming state. That is, in the first game after the setting change, there is a high possibility that the gaming state will be maintained in the non-internal gaming state.

Therefore, in the second game after the setting change, that is, the second game in the non-advantageous standby performance state, when the gaming state is the non-internal game state, the performance state control means 314 sets the settings shown in FIG. 13(d). With reference to the mode lottery table at the time of change, the mode of the normal performance state to which the mode is to be transferred thereafter is determined by mode lottery. According to the mode lottery table at the time of setting change, mode A is determined with a probability of 50%, mode B is determined with a probability of 30%, and mode C is determined with a probability of 20%.

In this way, among the plurality of modes for managing the normal gaming state, mode A, which has the largest number of ceiling games, is determined only when the settings are changed.

FIG. 14 is a diagram illustrating the transition lottery table. As mentioned above, when the transition to the normal AT performance state is decided in the normal performance state and the CZ performance state, the execution of the lock 3 reel performance is not determined, and the specific conditions are not satisfied. In this case, the state will be transferred to the normal AT performance state via the OP performance state and the specialized zone performance state.

Here, in this embodiment, the specific condition is set that the number of continued games (number of continuous games) in the pullback performance state, normal performance state, and CZ performance state has reached 999 games. In order for the number of consecutive games to reach 999 games, mode A must be set. Mode A may be determined only when changing settings. In other words, except when it is decided to execute the lock 3 reel effect, the state may shift to the special specialized zone effect state if mode A is determined at the time of setting change and the number of consecutive games reaches 999 games. Only if you reach it. When mode A is determined at the time of setting change and the number of consecutive games reaches 999 games, the transition destination is determined with reference to the transition lottery table shown in FIG. According to the transition lottery table, the specialized zone via the OP performance state is determined with a 50% probability, and the special specialized zone performance state is determined with a 50% probability.

FIG. 15 is a diagram illustrating an overview of increase/decrease in medals when changing settings. In the slot machine 100, when a setting change is made (so-called first thing in the morning), 999 games may be determined as the ceiling game number in the first normal performance state. That is, the user may become addicted to the game in the initial normal performance state. In such a case, as shown in FIG. 15, a larger amount of medals will be consumed than in other cases. On the other hand, when the ceiling number of games reaches 999 games, the state may shift to a special specialized zone performance state, and the same profits as when the reel performance is determined can be obtained. Therefore, in such a case, as shown in FIG. 15, after a large amount of medals are consumed, it becomes possible to acquire a large amount of medals.

By doing this, it is possible to increase the so-called MY value, which is calculated by subtracting the minimum value (the minimum value of the net increase in the number of coins) from the maximum value (the maximum value of the net increase in the number of coins) in a day, and improve the player's desire to play. can be done.

FIG. 16 is a diagram illustrating a continuous lottery table and an advantageous continuous lottery table. As described above, the final game in the normal AT performance state and the continuation lottery to determine whether to continue the normal AT performance state in the standby performance state are performed. Here, in the continuous lottery, the continuous lottery is performed with reference to the continuous lottery table shown in FIGS. 16(a) and 16(b).

Specifically, when the normal AT performance state that is transferred for the first time from the normal performance state, CZ performance state, and pullback performance state ends (the so-called first win), and when the advantageous state that is transferred after winning the advantageous continuation lottery is In the standby performance state, the performance state control means 314 performs a continuous lottery by referring to the first continuous lottery table shown in FIG. 16(a). According to the continuous lottery table for the first round, there is a 1% probability of winning and a 99% probability of not winning, regardless of the set value.

Furthermore, when the second and subsequent normal AT presentation states are completed without passing through the normal presentation state, CZ presentation state, and pullback presentation state, the presentation state control means 314 controls the second and subsequent presentation states shown in FIG. 16(b). Continuous lottery is performed by referring to the continuous lottery table for. According to the continuous lottery table for second and subsequent rounds, there is an 80% probability of winning and a 20% probability of not winning, regardless of the set value.

In this way, it is difficult to win in the continuous lottery in the normal AT performance state at the first time, but it becomes easier to win in the continuous lottery in the normal AT performance state from the second time onwards.

Furthermore, even if the continuation lottery is not won, if the net increase in the number of tickets in the advantageous section is less than 400, the effect state control means 314 refers to the advantageous continuation lottery table shown in FIG. An advantageous continuation lottery will be held to continue the section. In the advantageous continuation lottery table, the probability of winning the advantageous continuation lottery is set to be different for each set value. Specifically, it is set so that the higher the set value is, the easier it is to win the advantageous continuation lottery. As mentioned above, if you win the advantageous continuation lottery, even if you do not win the continuation lottery, the normal production state mode will be set to mode D, so the ceiling number of games will be set to 100, and you will be able to enter the regular AT early. It will be shifted (returned) to the performance state.

As mentioned above, by making the continuation probability of the advantageous section different depending on the setting value, even if you do not win the continuous lottery, for example, the higher the setting, the earlier the return to the normal AT performance state, etc. It becomes a game experience and can improve the desire to play.

FIG. 17 is a diagram illustrating reel effects. In this embodiment, lock 1, lock 2, and lock 3 are provided as reel effects. In the reel performances of locks 1 to 3, at the start of the game, the reel control means 306 executes a reel performance that rotates the reels 110a, 110b, and 110c in reverse in stages. As shown in FIG. 17(a), in the reel performance of lock 1, the reel control means 306 executes a reel performance in which the reels 110a, 110b, 110c are rotated in reverse and once stopped, and then the rotating reels 110a, 110b , 110c. In addition, in the reel performance of lock 2, as shown in FIG. 17(b), the reel control means 306 executes a reel performance in which the reels 110a, 110b, and 110c are rotated in reverse and then stopped once, repeating twice, After that, the reels 110a, 110b, and 110c are rotated. In addition, in the reel performance of lock 3, as shown in FIG. 17(c), a reel performance is performed in which the reels 110a, 110b, 110c are rotated in reverse and then stopped once, three times, and then the reels 110a, 110b , 110c.

As described above, in this embodiment, reel effects of Lock 1 to Lock 3 are provided in which the number of reverse rotations of the reels 110a, 110b, and 110c differs stepwise. As described above, Lock 2 is more likely to win the CZ lottery than Lock 1, and Lock 3 is determined to transition to the special specialized zone presentation state. In other words, it is set such that the greater the number of reverse rotations, the greater the benefit to the player.

FIG. 18 is a diagram illustrating the reel performance lottery table. As shown in FIG. 18, the performance state control means 314 changes the state shown in FIG. With reference to the reel performance lottery table shown, whether or not lock 1 and lock 2 can be executed is determined by reel performance lottery. Whether locks 1 and 2 can be executed or not is determined by lottery when a so-called rare combination is won.

Further, when the winning type "Replay 3" or "Replay 4" is won in the winning type lottery, the performance state control means 314 refers to the reel performance lottery table shown in FIG. 18(b) and executes the lock 3. The success or failure will be determined by reel performance lottery.

However, if the total number of games in the normal performance state, CZ performance state, and pullback performance state is 400 games or less, the winning type will be selected by lottery as "Watermelon", "Chance", "Weak Cherry", or "Strong Cherry". When the winning result is won, the performance state control means 314 refers to the reel performance lottery table shown in FIG. 18(c) and determines whether or not Lock 1 and Lock 2 can be executed by reel performance lottery.

In addition, if the total number of games in the normal performance state, CZ performance state, and pullback performance state is 400 games or less, the performance state control will be applied when the winning type "Replay 3" or "Replay 4" is won by the winning type lottery. The means 314 refers to the reel effect lottery table shown in FIG. 18(d) and determines whether lock 3 can be executed or not by reel effect lottery.

According to the reel performance lottery table shown in FIGS. 18(a) to 18(d), if the total number of games in the normal performance state, CZ performance state, and pullback performance state is 400 games or less, Lock 2 and Lock The probability of winning 3 is set lower than in other cases. That is, when the total number of games in the normal performance performance, CZ performance state, and pullback performance state is 400 games or less, it becomes difficult for Lock 2 and Lock 3 to be won.

As a result, although it is difficult to win Lock 2 and Lock 3 at the beginning of the transition to the normal performance state, CZ performance state, and pullback performance state, after 400 games are exceeded, it becomes easier to win Lock 2 and Lock 3. It becomes easier for players to receive benefits (normal AT performance state or special specialized zone performance state), and it is possible to increase the player's desire to play by playing the number of games repeatedly.

Hereinafter, specific processing in the main control board 200 and the sub control board 202 will be explained based on a flowchart.

(CPU initialization process of main control board 200)
FIG. 19 is a flowchart illustrating CPU initialization processing in the main control board 200. When power is supplied from the power supply board, a system reset occurs in the main CPU 200a, and the main CPU 200a performs the following CPU initialization process (S100).

(Step S100-1)
When the power is turned on, the main CPU 200a reads a startup program from the main ROM 200b as an initial setting process, and performs setting processes necessary to execute various processes.

(Step S100-3)
The main CPU 200a sets a wait processing time in a timer counter.

(Step S100-5)
The main CPU 200a determines whether a power-off notice signal is detected. Note that the main control board 200 is provided with a power-off detection circuit, and when the power supply voltage falls below a predetermined value, a power-off warning signal is output from the power-off detection circuit. If a power cutoff notice signal is detected, the process moves to step S100-3, and if a power cutoff notice signal is not detected, the process moves to step S100-7.

(Step S100-7)
The main CPU 200a determines whether the wait processing time set in step S100-3 above has elapsed. As a result, if it is determined that the wait processing time has elapsed, the process moves to step S100-9, and if it is determined that the wait time has not elapsed, the process moves to step S100-5.

(Step S100-9)
The main CPU 200a executes necessary processing to permit access to the main RAM 200c.

(Step S100-11)
The main CPU 200a executes checksum confirmation processing. Here, the main CPU 200a calculates a checksum, and determines whether the calculated checksum does not match (is abnormal) the checksum saved when the power was turned off, and whether the backup is abnormal. Then, if the main CPU 200a determines that one or both of the backup and the checksum is abnormal, it turns on the backup abnormality flag, and if it determines that both the backup and the checksum are not abnormal, the main CPU 200a turns on the backup abnormality flag. Turn off.

(Step S100-13)
The main CPU 200a determines whether the backup abnormality flag is on. As a result, if it is determined that the backup abnormality flag is on, the process moves to step S110, and if it is determined that the backup abnormality flag is not on, the process moves to step S120.

(Step S110)
The main CPU 200a executes cold start processing. Note that this cold start processing will be described later.

(Step S120)
The main CPU 200a executes a setting value switching process for switching setting values. Note that this setting value switching process will be described later.

(Step S130)
The main CPU 200a executes a state recovery process to return to the state immediately before the power was turned off. Note that this state recovery process will be described later.

FIG. 20 is a flowchart illustrating the cold start process (S110) in the main control board 200.

(Step S110-1)
The main CPU 200a clears the used area in the main RAM 200c and executes a used area RAM check process to detect abnormalities in the used area.

(Step S110-3)
The main CPU 200a clears the separate area (unused area) in the main RAM 200c, and executes a separate area RAM check process to detect an abnormality in the separate area. Note that if an abnormality is detected in the separate area in the separate area RAM check process, the main CPU 200a turns on the RAM read/write error flag.

(Step S110-5)
The main CPU 200a sets an error code "EA" indicating an abnormality in the main RAM 200c.

(Step S110-7)
The main CPU 200a determines whether an abnormality is detected in step S110-1. As a result, if it is determined in step S110-1 that an abnormality is detected, the process moves to step S112, and if it is determined that no abnormality is detected in step S110-1, the process proceeds to step S110-9. Transfer processing.

(Step S110-9)
The main CPU 200a acquires a RAM read/write error flag that is turned on when an abnormality is detected in step S110-3.

(Step S110-11)
The main CPU 200a determines whether the RAM read/write error flag is on. As a result, if it is determined that the RAM read/write error flag is on, the process moves to step S112, and if it is determined that the RAM read/write error flag is not on, the process moves to step S120.

(Step S120)
The main CPU 200a executes a setting value switching process for switching setting values. Note that this setting value switching process will be described later.

(Step S110-13)
The main CPU 200a sets an error code "E7" indicating a backup error.

(Step S112)
The main CPU 200a executes error stop processing to stop the progress of the game due to an error. Note that this error stop processing will be described later.

FIG. 21 is a flowchart illustrating the error stop processing (S112) in the main control board 200.

(Step S112-1)
The main CPU 200a sets the initial stack pointer value as the address of the stack pointer.

(Step S112-3)
The main CPU 200a executes an error setting process for setting an error display and a warning sound.

(Step S112-5)
The main CPU 200a sets external signals 1 to 3 output bits off to turn off the output images of the bits corresponding to external signals 1 to 3.

(Step S112-7)
The main CPU 200a executes output port image set processing to update the output image for the bits set in step S112-5 above.

(Step S112-9)
The main CPU 200a shifts to an eternal loop. As a result, the progress of the game will be stopped.

FIG. 22 is a flowchart illustrating the setting value switching process (S120) in the main control board 200.

(Step S120-1)
The main CPU 200a acquires a signal from input port 1, and determines whether a set value switching condition is satisfied based on the acquired signal from input port 1. As a result, if it is determined that the set value switching condition is not satisfied, the set value switching process is ended, and if it is determined that the set value switching condition is satisfied, the process is moved to step S120-3. . Here, the signals of the input port 1 include a signal indicating whether the upper front door 104 and the lower front door 106 are open, and a signal indicating whether the setting key is turned on. Here, when a signal indicating that the upper front door 104 and lower front door 106 are open and a signal indicating that the setting key is turned on is obtained, the setting value switching condition is set. It is determined that this has been established.

(Step S120-3)
The main CPU 200a executes a RAM clearing process to clear the used area in the main RAM 200c that should be cleared when changing settings.

(Step S120-5)
The main CPU 200a executes table content setting processing to transfer the table data of the data table at the time of setting value switching to the main RAM 200c.

(Step S120-7)
The main CPU 200a sets a setting change start command in the transmission buffer indicating that setting value change is to be started.

(Step S120-9)
The main CPU 200a executes edge check processing to detect a falling edge (on edge) of a signal at an input port.

(Step S120-11)
The main CPU 200a obtains setting value data indicating current setting values.

(Step S120-13)
The main CPU 200a determines whether an on-edge of the setting change switch is detected in step S120-9. As a result, if it is determined that the on-edge of the setting change switch is not detected, the process moves to step S120-17, and if it is determined that the on-edge of the setting change switch is detected, the process moves to step S120-15. .

(Step S120-15)
The main CPU 200a increments the setting value data by one.

(Step S120-17)
The main CPU 200a determines whether the setting value data is within a range (1 to 6) that can be set as a setting value. As a result, if it is determined that the set value data is within the range, the process moves to step S120-21, and if it is determined that the set value data is not within the range, the process moves to step S120-19.

(Step S120-19)
The main CPU 200a sets the setting value data to 0.

(Step S120-21)
The main CPU 200a updates the setting value data to the value incremented or set in step S120-15 or step S120-19.

(Step S120-23)
The main CPU 200a executes display data conversion processing to display the set value on the main credit display section 130.

(Step S120-25)
The main CPU 200a determines whether an on-edge of the setting change switch is detected. As a result, if it is determined that the on-edge of the setting change switch is not detected, the process moves to step S120-31, and if it is determined that the on-edge of the setting change switch is detected, the process moves to step S120-27. move.

(Step S120-27)
The main CPU 200a determines whether the setting change switch is on. As a result, if it is determined that the setting change switch is on, the process moves to step S120-27, and if it is determined that the setting change switch is not on, the process moves to step S120-29.

(Step S120-29)
The main CPU 200a sets a setting value change switch interval timer.

(Step S120-31)
The main CPU 200a executes a timer wait process of waiting until the setting change switch interval timer reaches 0.

(Step S120-33)
The main CPU 200a determines whether an on-edge of the start switch 118 has been detected. As a result, if it is determined that the on-edge of the start switch 118 is not detected, the process moves to step S120-9, and if it is determined that the on-edge of the start switch 118 is detected, the process proceeds to step S120-35. move.

(Step S120-35)
The main CPU 200a determines whether the setting key is off. As a result, if it is determined that the setting key is off, the process moves to step S120-35, and if it is determined that the setting key is not off, the process moves to step S120-37.

(Step S120-37)
The main CPU 200a determines whether the setting key is on. As a result, if it is determined that the setting key is on, the process moves to step S120-37, and if it is determined that the setting key is not on, the process moves to step S122.

(Step S122)
The main CPU 200a executes initialization start processing to start initialization start. Note that this initialization start processing will be described later.

FIG. 23 is a flowchart illustrating the initialization start process (S122) in the main control board 200.

(Step S122-1)
The main CPU 200a sets a setting change end command in the transmission buffer indicating that the setting value change has been completed.

(Step S122-3)
The main CPU 200a sets a setting change state command in the transmission buffer indicating the state when the setting value change is completed.

(Step S122-5)
The main CPU 200a sets a wait timer at the start of initialization.

(Step S122-7)
The main CPU 200a executes a timer wait process of waiting until the wait timer reaches 0 at the start of initialization.

(Step S122-9)
The main CPU 200a executes a RAM clear process when changing settings to clear another area of the main RAM 200c.

(Step S122-11)
The main CPU 200a executes a RAM clearing process to clear the used area in the main RAM 200c that should be cleared when changing settings.

(Step S122-13)
The main CPU 200a sets a gaming state command indicating the current gaming state in the transmission buffer.

(Step S200)
The main CPU 200a executes a game start process for starting the game. Note that this game start process will be described later.

FIG. 24 is a flowchart illustrating the state recovery process (S130) in the main control board 200.

(Step S130-1)
The main CPU 200a restores the stack pointer.

(Step S130-3)
The main CPU 200a executes an unused area clearing process to clear an unused area of the main RAM 200c.

(Step S130-5)
The main CPU 200a clears the stack pointer storage buffer.

(Step S130-7)
The main CPU 200a sets (turns on) a flag after power-off recovery.

(Step S130-9)
The main CPU 200a executes port input processing to update the image of the input port.

(Step S130-11)
The main CPU 200a executes a manipulation target bit extraction process for extracting information on the manipulation target bit based on the image of the input port updated in step S130-9.

(Step S130-13)
The main CPU 200a sets the operation target bit extracted in step S130-11 above as the operation target bit in the previous state.

(Step S130-15)
The main CPU 200a acquires the motor phases of the reels 110a, 110b, and 110c. Here, a motor phase is set as the state of the reels 110a, 110b, and 110c. The motor phase indicates the operating state of the reels 110a, 110b, and 110c, that is, during acceleration, steady rotation, stop, and standby. Specifically, a 1-byte (memory unit) variable assigned to a motor phase is set according to the operating state of the stepping motor 152: accelerating = 3, steady rotation = 2, stopping = 1, and waiting = Changes to a value such as 0.

(Step S130-17)
The main CPU 200a determines whether any of the reels 110a, 110b, and 110c are rotating steadily or accelerating based on the motor phase acquired in step S130-15. As a result, if it is determined that none of the reels 110a, 110b, 110c is rotating normally or accelerating, the process moves to step S130-21, and one of the reels 110a, 110b, 110c is rotating normally or accelerating. If it is determined that it is inside, the process moves to step S130-19.

(Step S130-19)
The main CPU 200a executes rotation error processing to perform settings when an error is detected for the reels 110a, 110b, and 110c.

(Step S130-21)
The main CPU 200a restores the saved register group.

(Step S130-23)
The main CPU 200a allows the interrupt and ends the state recovery process. As a result, the main CPU 200a returns to the state immediately before the power was turned off.

FIG. 25 is a flowchart illustrating the game start process (S200) in the main control board 200.

(Step S200-1)
The main CPU 200a executes a re-gaming state identification signal output setting process for outputting a re-gaming state identification signal indicating whether or not it is a re-gaming.

(Step S200-3)
The main CPU 200a sets an input number display output bit off for turning off (turns off) a bit corresponding to the input number display that displays the number of medals inserted (bet number).

(Step S200-5)
The main CPU 200a executes output port image setting processing to update the output image for the bits set in step S200-3 above.

(Step S200-7)
The main CPU 200a sets a game start wait timer.

(Step S200-9)
The main CPU 200a executes a timer wait process of waiting until the game start wait timer reaches 0.

(Step S200-11)
The main CPU 200a executes one game RAM clearing process to clear an area that should be cleared for each game among the used areas in the main RAM 200c.

(Step S200-13)
The main CPU 200a executes a bonus signal setting process for setting a bonus signal.

(Step S200-15)
The main CPU 200a executes edge clear processing to clear edge information of the input port image.

(Step S210)
The main CPU 200a executes a game medal insertion process that accepts the insertion of medals. Note that this game medal insertion process will be described later.

FIG. 26 is a flowchart illustrating the game medal insertion process (S210) in the main control board 200.

(Step S210-1)
The main CPU 200a executes error confirmation processing to confirm the detection results of various errors.

(Step S210-3)
The main CPU 200a executes edge check processing to detect a falling edge (on edge) of a signal at an input port.

(Step S210-5)
The main CPU 200a acquires a door open error detection flag that is set to 1 when the front upper door 104 or the front lower door 106 is opened.

(Step S210-7)
The main CPU 200a determines whether the front upper door 104 and the front lower door 106 are closed based on the door open error detection flag acquired in step S210-5 above. As a result, if it is determined that the front upper door 104 and the front lower door 106 are closed, the process moves to step S210-17, and if at least one of the front upper door 104 or the front lower door 106 is not closed. If determined, the process moves to step S210-9.

(Step S210-9)
The main CPU 200a sets an error code "E8" indicating that at least one of the upper front door 104 and the lower front door 106 is open.

(Step S210-11)
The main CPU 200a displays an error, requests a warning sound, and executes error wait processing for waiting for error recovery.

(Step S210-13)
The main CPU 200a executes a setting value confirmation process to confirm the setting value.

(Step S210-15)
The main CPU 200a executes edge clear processing to clear edge information of the input port image.

(Step S210-17)
The main CPU 200a executes a credit button check process to refund the stored medals when a credit switch (not shown) for refunding the stored (credited) medals is pressed.

(Step S210-19)
The main CPU 200a executes processing related to a game medal insertion button for betting medals. Here, when the bet switch 116 is pressed, the player bets the stored (credited) medals up to a specified number, and subtracts the stored number of medals by the number of betted medals. Further, when medals are inserted through the medal slot 114a, bets are made up to a specified number of medals, and when more medals than the specified number are inserted, the corresponding amount is added to the stored number.

(Step S210-21)
The main CPU 200a executes game medal acquisition processing to check whether the number of inserted medals is a specified number.

(Step S210-23)
The main CPU 200a determines whether the number of inserted sheets is not the specified number based on the confirmation result in step S210-21. As a result, if it is determined that the number of inserted sheets is not the specified number, the process moves to step S210-1, and if it is determined that the number of inserted sheets is the specified number, the process moves to step S210-25.

(Step S210-25)
The main CPU 200a sets a start indicator output bit for turning on (lighting up) a start indicator (not shown) indicating whether or not the operation of the start switch 118 is valid.

(Step S210-27)
The main CPU 200a determines whether a falling edge (press) of the start switch 118 has been detected. As a result, if it is determined that the falling edge of the start switch 118 has not been detected, the process moves to step S210-1, and if it is determined that the falling edge of the start switch 118 has been detected, the process proceeds to step S210-1. Processing moves to -29.

(Step S210-29)
The main CPU 200a clears the main payout display section buffer in order to clear the display on the main payout display section 132.

(Step S210-31)
The main CPU 200a executes a re-gaming state identification signal clearing process to clear the re-gaming state identification signal.

(Step S210-33)
The main CPU 200a executes blocker closing preprocessing to turn off the start indicator.

(Step S210-35)
The main CPU 200a sets a lever press command indicating that the start switch 118 has been pressed in the transmission buffer.

(Step S220)
The main CPU 200a executes an internal lottery process for determining the winning type. Note that this internal lottery process will be described later.

FIG. 27 is a flowchart illustrating the internal lottery process (S220) in the main control board 200.

(Step S220-1)
The main CPU 200a acquires setting value data.

(Step S220-3)
The main CPU 200a sets an error code "EC" indicating a setting value abnormality error.

(Step S220-5)
The main CPU 200a determines whether the setting value data acquired in step S220-1 is abnormal. As a result, if it is determined that the set value data is abnormal, the process moves to step S112, and if it is determined that the set value data is not abnormal, the process moves to step S220-7.

(Step S220-7)
The main CPU 200a obtains the winning type lottery random number updated by the random number generator 200d.

(Step S220-9)
The main CPU 200a executes a state offset acquisition process to acquire an offset value related to the gaming state.

(Step S220-11)
The main CPU 200a sets the address of the internal lottery area definition table (winning type lottery table).

(Step S220-13)
The main CPU 200a sets the value indicated by the address obtained by adding the offset value obtained in step S220-9 above to the address set in step S220-11 above as the initial value of the winning area. Here, the first winning area in the winning type lottery table of the current gaming state is set as the initial value.

(Step S220-15)
The main CPU 200a acquires lottery data, which is a numerical value indicating the winning range of the winning area, and executes lottery data acquisition processing to shift the winning area by 1.

(Step S220-17)
The main CPU 200a determines whether or not to perform a winning type lottery. As a result, if it is determined that the winning type lottery will not be performed, the process moves to step S220-21, and if it is determined that the winning type lottery is to be performed, the process moves to step S220-19.

(Step S220-19)
The main CPU 200a subtracts the lottery data from the random number value.

(Step S220-21)
The main CPU 200a determines whether the subtraction result in step S220-19 is negative, that is, whether the winning area has been won by the winning type lottery. As a result, if it is determined that the player has won the winning type lottery, the process moves to step S230, and if it is determined that the player has not won the winning type lottery, the process moves to step S220-23.

(Step S220-23)
The main CPU 200a determines whether the winning type lottery has ended. As a result, if it is determined that the winning type lottery has not ended, the process moves to step S220-15, and if it is determined that the winning type lottery has ended, the process moves to step S220-25.

(Step S220-25)
The main CPU 200a clears the trigger role type.

(Step S230)
The main CPU 200a executes a symbol code setting process for setting a symbol code based on the winning area and the gaming state. Note that this symbol code setting process will be described later.

FIG. 28 is a flowchart illustrating the symbol code setting process (S230) in the main control board 200.

(Step S230-1)
The main CPU 200a acquires the winning area won in step S220, and executes a gaming state setting process of setting the gaming state to the internal medium gaming state if the acquired winning area includes a bonus combination.

(Step S230-3)
The main CPU 200a sets the winning area acquired in step S230-1 above as a stop control number.

(Step S230-5)
The main CPU 200a determines (sets) the winning type based on the winning area acquired in step S230-1 above.

(Step S230-7)
The main CPU 200a executes a symbol code initial setting process to set a symbol code indicating a displayable symbol and a drawing target symbol based on the stop control number set in step S230-3.

(Step S230-9)
The main CPU 200a executes display symbol bit initial value setting processing for setting display symbol bits.

(Step S231)
The main CPU 200a executes an execution flag setting process that sets an execution flag, performs various processes related to the presentation state, processes related to auxiliary presentation, and the like. Note that this execution flag setting process will be described later.

(Step S230-13)
The main CPU 200a sets a production command, which is a command related to an advantageous section, in the transmission buffer.

(Step S230-15)
The main CPU 200a sets a winning information command indicating the winning type in the transmission buffer.

(Step S230-17)
The main CPU 200a checks the one-game timer.

(Step S230-19)
The main CPU 200a sets a pre-rotation command in the transmission buffer indicating that the reels 110a, 110b, and 110c are before rotation.

(Step S230-21)
The main CPU 200a executes an excitation release wait process for waiting for excitation release of the stepping motor 152.

(Step S230-23)
The main CPU 200a determines whether the one-game timer is not 0. As a result, if it is determined that the one-game timer is not 0, the process moves to step S230-23, and if it is determined that the one-game timer is 0, the process moves to step S230-25.

(Step S230-25)
The main CPU 200a executes a reel start process for starting the rotation of the reels 110a, 110b, and 110c. Here, the motor phase of the reels 110a, 110b, and 110c is set to be accelerated to start the rotation of each reel, and the one-game timer is set to a value corresponding to 4.1 seconds.

(Step S230-27)
The main CPU 200a sets a reel start command in the transmission buffer indicating that the rotation of the reels 110a, 110b, and 110c has started.

(Step S240)
The main CPU 200a executes a reel rotation process which is a process while the reels 110a, 110b, and 110c are rotating. Note that this process during rotation of the drum will be described later.

FIG. 29 is a flowchart illustrating the execution flag setting process (S231) in the main control board 200.

(Step S231-1)
The main CPU 200a executes an AT state update process that updates (transitions) the production state based on the next AT flag. Note that the next AT flag indicates the performance state to be set in the next game, and will be set in the following process.

(Step S232 to Step S236)
The main CPU 200a executes a state-specific module execution process that executes a module for each performance state and game section, and ends the execution flag setting process. In addition, in the state-based module execution process, the module (process) corresponding to the transitioned performance state and game section is read from the main ROM 200b and executed. Below, modules related to the features of this embodiment will be explained in detail, and explanations of modules unrelated to the features of this embodiment will be omitted.

FIG. 30 is a flowchart illustrating the non-advantageous section processing (S232) executed in the state-specific module execution processing. The non-advantageous section process is executed when the game section is a non-advantageous section.

(Step S232-1)
The main CPU 200a performs an advantageous section lottery.

(Step S232-3)
The main CPU 200a determines whether or not the advantageous section lottery has been won in step S232-1. As a result, if it is determined that the advantageous section lottery has been won, the process moves to step S232-5, and if it is determined that the advantageous section lottery has not been won, the non-advantageous section processing is ended.

(Step S232-5)
The main CPU 200a turns on the advantageous section flag indicating that the section is an advantageous section, and ends the non-advantageous section processing. As a result, in the advantageous section update process of step S280-7, which will be described later, the section is shifted to an advantageous section.

FIG. 31 is a flowchart illustrating the normal performance state processing (S233) executed in the state-specific module execution processing. The normal performance state process is executed when the performance state is the normal performance state.

(Step S233-1)
The main CPU 200a increments by one a continuous game number counter for counting the number of continuous games. Note that the continuous game number counter is incremented by 1 for each game in the CZ performance state process described below and also in the pullback performance state process (not shown) that is executed when the game is in the pullback performance state. Further, the continuous game number counter is reset when transitioning to the OP performance state or the special specialized zone performance state.

(Step S233-3)
The main CPU 200a executes a reel performance lottery process that determines by lottery whether or not the reel performance can be executed when a predetermined winning type is won. Here, when the winning type "Watermelon", "Chance", "Weak Cherry", and "Strong Cherry" are won in the winning type lottery, if the number of continuous games is 400 or less, Refer to the reel effect lottery table shown in FIG. 18(c), and if the number of consecutive games is greater than 400, refer to the reel effect lottery table shown in FIG. 18(a) to decide whether or not Lock 1 and Lock 2 can be executed. To be determined by lottery. In addition, when the winning type "Replay 3" or "Replay 4" is won in the winning type lottery, if the number of continuous games is 400 or less, the performance state control means 314 controls the reel performance lottery shown in FIG. 18(d). The table is referred to, and if the number of consecutive games is greater than 400, the reel performance lottery table shown in FIG. 18(b) is referred to, and whether or not Lock 3 can be executed is determined by the reel performance lottery.

(Step S233-5)
The main CPU 200a determines whether the execution of lock 3 has been determined in step S233-3, that is, whether lock 3 has been won. As a result, if it is determined that lock 3 has been won, the process moves to step S233-7, and if it is determined that lock 3 has not been won, the process moves to step S233-9.

(Step S233-7)
The main CPU 200a sets the next AT flag to a value corresponding to the special specialized zone production state, and moves the process to step S233-31.

(Step S233-9)
The main CPU 200a determines whether the value of the continuous game number counter is the ceiling game number corresponding to the mode being set. As a result, if it is determined that the value of the continued game number counter is the ceiling number of games, the process moves to step S233-11, and if it is determined that the value of the continued game number counter is not the ceiling number of games, step S233- Processing moves to step 17.

(Step S233-11)
The main CPU 200a determines whether the value of the continuous game number counter is 999 or not. As a result, if it is determined that the value of the continuous game number counter is 999, the process moves to step S233-13, and if it is determined that the value of the continuous game number counter is not 999, the process moves to step S233-15.

(Step S233-13)
The main CPU 200a refers to the transition lottery table shown in FIG. 14 and performs a transition lottery to determine the destination performance state. Here, if the number of consecutive games has exceeded 999 games, a transition to the special specialized zone performance state is determined with a probability of 50%.

(Step S233-15)
If the main CPU 200a has won the transition lottery in step S233-13 above, the main CPU 200a sets the next AT flag to a value corresponding to the special specialized zone production state, and if the transition lottery has not been won, the main CPU 200a sets the transition lottery If not, the next AT flag is set to a value corresponding to the OP effect state, and the process moves to step S233-31.

(Step S233-17)
The main CPU 200a determines whether the internal state is in the ultra-high certainty state. As a result, if it is determined that the state is extremely accurate, the process moves to step S233-21, and if it is determined that the state is not extremely accurate, the process moves to step S233-19.

(Step S233-19)
The main CPU 200a refers to the status up lottery table shown in FIG. 11 and performs a status up lottery based on the winning type determined in the winning type lottery, and if the status up lottery is won, the internal status is changed by one. promote.

(Step S233-21)
The main CPU 200a determines whether the execution of Lock 1 or Lock 2 has been determined in step S233-3, that is, whether Lock 1 or Lock 2 has been won. As a result, if it is determined that lock 1 or lock 2 has been won, the process moves to step S233-23, and if it is determined that lock 1 or lock 2 has not been won, the process moves to step S233-25. Move.

(Step S233-23)
The main CPU 200a rewrites the winning type to "lock 1" if the lock 1 has been won, and to "lock 2" if the lock 2 has been won.

(Step S233-25)
The main CPU 200a selects one of the CZ lottery tables shown in FIGS. 12(a) to 12(d) based on the internal state, refers to the selected CZ lottery table, and selects the winnings determined by the winning type lottery. A CZ lottery is performed based on the type or the winning type rewritten in step S233-23 above.

(Step S233-27)
The main CPU 200a determines whether the CZ lottery has been won in step S233-25. As a result, if it is determined that the player has won the CZ lottery, the process moves to step S233-29, and if it is determined that the player has not won the CZ lottery, the process moves to step S233-31.

(Step S233-29)
The main CPU 200a sets the next AT flag to a value corresponding to the CZ effect state.

(Step S233-31)
The main CPU 200a determines whether execution of the reel performance has been decided in step S233-3, that is, whether any of the reel performances from Lock 1 to Lock 3 has been won. As a result, if it is determined that the reel performance has been won, the process moves to step S233-33, and if it is determined that the reel performance has not been won, the normal performance state processing is ended.

(Step S233-33)
The main CPU 200a executes the reel performance determined in step S233-3, and ends the normal performance state processing.

FIG. 32 is a flowchart illustrating the CZ effect state processing (S234) executed in the state-based module execution processing. CZ performance state processing is executed when the performance state is CZ performance state processing. It should be noted that among the various processes in the CZ performance state process, the same processes as in the normal performance state process are given the same reference numerals, and their explanations will be omitted.

(Step S234-1)
The main CPU 200a performs an AT lottery based on the winning type determined by the winning type lottery.

(Step S234-3)
The main CPU 200a determines whether the AT lottery has been won in step S234-1. As a result, if it is determined that the AT lottery has been won, the process moves to step S234-5, and if it is determined that the AT lottery has not been won, the process moves to step S234-7.

(Step S234-5)
The main CPU 200a sets the next AT flag to a value corresponding to the OP effect state, and moves the process to step S233-31.

(Step S234-7)
The main CPU 200a determines whether it is the final game in the CZ effect state. As a result, if it is determined that it is the final game in the CZ performance state, the process moves to step S234-9, and if it is determined that it is not the final game in the CZ performance state, the process moves to step S233-31.

(Step S234-9)
The main CPU 200a sets the next AT flag to a value corresponding to the normal performance state, and also sets the internal state to one of the normal state, high accuracy state, or super high accuracy state.

FIG. 33 is a flowchart illustrating the non-advantageous standby performance state processing (S235) executed in the state-specific module execution processing. The non-advantageous performance state processing is executed when the performance state is a non-advantageous performance state.

(Step S235-1)
The main CPU 200a determines whether the continuation flag is on. Note that the continuation flag is turned on when transition (continuation) to the normal AT performance state is determined. As a result, if it is determined that the continuation flag is on, the process moves to step S235-9, and if it is determined that the continuation flag is not on, the process moves to step S235-3.

(Step S235-3)
The main CPU 200a performs a continuous lottery by referring to the first continuous lottery table shown in FIG. 16(a).

(Step S235-5)
The main CPU 200a determines whether the continuous lottery has been won. As a result, if it is determined that the continuous lottery has been won, the process moves to step S235-7, and if it is determined that the continuous lottery has not been won, the process moves to step S235-9.

(Step S235-7)
The main CPU 200a turns on the continuation flag.

(Step S235-9)
The main CPU 200a determines whether it is the final game (second game) in the non-advantageous standby performance state. As a result, if it is determined that it is the final game, the process moves to step S235-11, and if it is determined that it is not the final game, the non-advantageous standby performance state process is ended.

(Step S235-11)
The main CPU 200a determines whether the continuation flag is on. As a result, if it is determined that the continuation flag is on, the process moves to step S235-13, and if it is determined that the continuation flag is not on, the process moves to step S235-15.

(Step S235-13)
If the gaming state of the previous game is a non-internal gaming state, the main CPU 200a refers to the mode lottery table at the time of setting change shown in FIG. 13(d), and if the gaming state of the previous game is other than the non-internal gaming state ( (RBB internal medium game state), the mode of the normal performance state to which the mode will be transferred thereafter is determined by mode lottery with reference to the mode lottery table for the non-advantageous standby performance state shown in FIG. 13(b). .

(Step S235-15)
The main CPU 200a sets the next AT flag to a value corresponding to the continuous performance state, and ends the non-advantageous standby performance state processing.

FIG. 34 is a flowchart illustrating the advantageous standby performance state processing (S236) executed in the state-specific module execution processing. The advantageous performance state processing is executed when the performance state is an advantageous performance state. It should be noted that among the processes in the advantageous performance state processing, the same processes as the non-advantageous performance state processing are given the same reference numerals, and the explanation thereof will be omitted.

(Step S236-1)
The main CPU 200a refers to the mode lottery table for the advantageous standby performance state shown in FIG. 13(c), and determines the mode of the normal performance state to which the mode is to be transferred thereafter by mode lottery. Here, mode D is definitely determined.

FIG. 35 is a flowchart illustrating processing during rotation of the drum (S240) in the main control board 200.

(Step S240-1)
The main CPU 200a sets the stop indicator output bit OFF (output image) to turn off (extinguish) the bit corresponding to the indicators (not shown) of the stop switches 120a, 120b, and 120c. Here, the stop indicator output bit is composed of a 3-bit bit string, and each bit is associated with the emission color of the three stop switches 120a, 120b, and 120c, and is represented by blue = 1 and red = 0. be done.

(Step S240-3)
The main CPU 200a executes output port image setting processing to update the output image for the bits set in step S240-1 above.

(Step S240-5)
The main CPU 200a executes error confirmation processing to confirm the detection results of various errors.

(Step S240-7)
The main CPU 200a refers to the index flag and obtains the indexes of the rotating reels 110a, 110b, and 110c. Note that the index flag is set only after the reels 110a, 110b, and 110c reach a constant rotation speed.In other words, the index flag is set when the reels 110a, 110b, and 110c are rotated at a constant speed. It also shows that the speed has been reached.

(Step S240-9)
The main CPU 200a determines whether the index flags of all the reels 110a, 110b, and 110c have been detected. As a result, if it is determined that all index flags have not been detected, the process moves to step S240-1, and if it is determined that all index flags have been detected, the process moves to step S240-11.

(Step S240-11)
The main CPU 200a obtains stop reel bits indicating the reels 110a, 110b, and 110c that have stopped or started to stop. Here, the stop reel bit is composed of a bit string of 3 bits, each bit is associated with one of the three reels 110a, 110b, and 110c, and the constant speed state = 1, acceleration state, and deceleration state. Alternatively, the stopped state is represented by 0.

(Step S240-13)
The main CPU 200a stores the stop drum bit acquired in step S240-11 above as a drum rotating flag.

(Step S240-15)
The main CPU 200a sets the stop indicator output bit on (output image) to turn on (turn off) the bit corresponding to the indicators (not shown) of the stop switches 120a, 120b, and 120c.

(Step S240-17)
The main CPU 200a acquires an image of input port 0, and executes operation target bit extraction processing for extracting operation target bits from the acquired image. Here, the bits to be manipulated are composed of a 3-bit bit string, and each bit is associated with one of the three stop switches 120a, 120b, and 120c, and the bit being manipulated = 1 and not being manipulated. =0.

(Step S240-19)
The main CPU 200a calculates the logical product of the rotation drum flag acquired in step S240-13 and the operation target bit extracted in step S240-17. Here, if the reel 110 is rotating and the stop switch 120 corresponding to the reel is operated, that is, if the operated stop switch 120 corresponds to the reel 110 that is effectively rotating. , the logical product is 1.

(Step S240-21)
The main CPU 200a determines whether the logical product calculated in step S240-19 is 0, that is, whether the stop switch 120 corresponding to the rotating reel 110 has been operated. As a result, if it is determined that the stop switch 120 corresponding to the rotating reel 110 is not operated, the process moves to step S240-3, and the stop switch 120 corresponding to the rotating reel 110 is not operated. If it is determined that it is, the process moves to step S240-23.

(Step S240-23)
The main CPU 200a obtains an output image including the stop indicator output bit, and calculates a logical product between the obtained output image and the logical product calculated in step S240-19. Here, when the operated stop switch 120 is lit in red, the AND bit becomes 0, and when the operated stop switch 120 is lit in blue, the AND bit becomes 1.

(Step S240-25)
The main CPU 200a determines whether the logical product calculated in step S240-23 is 0, that is, whether the operated stop switch 120 is lit in red. As a result, if it is determined that the operated stop switch 120 is lit red, the process moves to step S240-1, and if it is determined that the operated stop switch 120 is not lit red, then step S240- The process moves to step 27.

(Step S240-27)
The main CPU 200a determines whether or not the operated stop switch 120 is valid. As a result, if it is determined that the operated stop switch 120 is not valid, the process moves to step S240-1, and if it is determined that the operated stop switch 120 is valid, the process moves to step S240-29. Move. Note that here, it is determined whether or not only one stop switch 120 has been operated. If it is determined that the number of operated stop switches 120 is one, the process moves to step S240-29, and if it is determined that the number of operated stop switches 120 is not one, that is, two or more. Then, the process moves to step S240-1.

(Step S240-29)
The main CPU 200a executes a stop control reel setting process to obtain various parameters for stopping the reel 110 corresponding to the operated stop switch 120.

(Step S240-31)
The main CPU 200a prohibits interrupts.

(Step S240-33)
The main CPU 200a executes a press reference position acquisition process that derives the symbol number of the symbol located on the active line A as the press reference position.

(Step S240-35)
The main CPU 200a executes a sliding piece number acquisition process that determines the number of sliding pieces on the reel 110.

(Step S250)
The main CPU 200a executes a reel stop process to stop the reel 110 corresponding to the operated stop switch 120. Note that this rotation drum stop processing will be described later.

FIG. 36 is a flowchart illustrating the rotation drum stop process (S250) in the main control board 200.

(Step S250-1)
The main CPU 200a obtains the press reference position derived in step S240-35 above.

(Step S250-3)
The main CPU 200a calculates the stop request number by correcting the number of sliding frames determined in step S240-37 above with respect to the press reference position obtained in step S250-1 above.

(Step S250-5)
The main CPU 200a sets a stop request flag (sets it to 1). The stop request flag is a flag for requesting a program running in parallel to stop the target reel 110. By setting the stop request flag to 1, the symbol corresponding to the stop request number is enabled. It becomes possible to stop on line A. The stop request flag and the above-mentioned stop request number are read by a program running in parallel, and the reel 110 is stopped. Note that when the stop processing is completed, the stop request flag is reset to 0 (OFF) by the program.

(Step S250-7)
The main CPU 200a allows interrupts.

(Step S250-9)
The main CPU 200a sets a stop information command indicating the order in which the reels 110 are stopped in the transmission buffer.

(Step S250-11)
The main CPU 200a sets the stop indicator output bit OFF (output image) to turn off (extinguish) the bit corresponding to the indicator (not shown) of the stop switch 120.

(Step S250-13)
The main CPU 200a executes output port image setting processing to update the output image for the bits set in step S250-11 above.

(Step S250-15)
The main CPU 200a executes display symbol bit setting processing for setting display symbol bits.

(Step S250-17)
The main CPU 200a executes next cylinder setting preprocessing to stop the next reel 110.

(Step S250-19)
The main CPU 200a determines whether the stopping process for all reels 110 has been completed. As a result, if it is determined that the stop processing of all reels 110 has not been completed, the process moves to step S240, and if it is determined that the stop processing of all reels 110 has been completed, the process proceeds to step S250-21. Transfer processing.

(Step S250-21)
The main CPU 200a determines whether the stop request flag is on for any reel 110, that is, whether all reels 110 have been stopped. As a result, if it is determined that all the reels 110 have not been stopped, the process moves to step S250-21, and if it is determined that all the reels 110 have stopped, the process moves to step S250-23.

(Step S250-23)
The main CPU 200a executes error confirmation processing to confirm the detection results of various errors.

(Step S250-25)
The main CPU 200a executes an operation target bit extraction process that extracts information about the operation target bit.

(Step S250-27)
The main CPU 200a determines whether the stop switch 120 is pressed based on the operation target bit acquired in step S250-25 above. As a result, if it is determined that the stop switch 120 is pressed down, the process moves to step S250-23, and if it is determined that the stop switch 120 is not pressed down, the process moves to step S260.

(Step S260)
The main CPU 200a executes a display determination process to determine the winning winning combination. Note that this display determination process will be described later.

FIG. 37 is a flowchart illustrating the display determination process (S260) in the main control board 200.

(Step S260-1)
The main CPU 200a clears the buffer of the main payout display section 132.

(Step S260-3)
The main CPU 200a determines whether a display determination abnormality has occurred based on whether or not the symbol combination displayed on the active line A matches the symbol combination that is permitted to be displayed on the active line A. Execute the detection process.

(Step S260-5)
The main CPU 200a sets an error code "EE" indicating a display determination abnormality (error).

(Step S260-7)
The main CPU 200a determines whether the display determination is abnormal based on the determination result in step S260-3. As a result, if it is determined that the display determination is abnormal, the process moves to step S112, and if it is determined that the display determination is not abnormal, the process moves to step S260-9.

(Step S260-9)
The main CPU 200a executes display symbol identification generation processing to determine the winning winning combination based on the symbol combinations stopped (displayed) on the active line A.

(Step S260-11)
The main CPU 200a sets 0 as the initial value of the number of coins to be paid out.

(Step S260-13)
The main CPU 200a determines whether a small winning combination has been won. As a result, if it is determined that a small winning combination has been won, the process moves to step S260-15, and if it is determined that a small winning combination has not been won, the process moves to step S260-35.

(Step S260-15)
The main CPU 200a turns on a winning flag indicating that a small winning combination has been won.

(Step S260-17)
The main CPU 200a executes a payout number setting process for setting a payout number according to the winning small winning combination.

(Step S260-19)
The main CPU 200a determines whether it is an advantageous section. As a result, if it is determined that it is not an advantageous section, the process moves to step S270, and if it is determined that it is an advantageous section, the process moves to step S260-21.

(Step S260-21)
The main CPU 200a obtains the value of the advantageous section MY counter that counts the net increase in the number of sheets during the advantageous section.

(Step S260-23)
The main CPU 200a adds the number of coins to be paid out to the value of the advantageous section MY counter acquired in step S260-23.

(Step S260-25)
The main CPU 200a obtains the number of coins inserted in the game.

(Step S260-27)
The main CPU 200a subtracts the number of inserted sheets from the value added in step S260-23.

(Step S260-29)
The main CPU 200a determines whether the subtraction result in step S260-27 is not negative. As a result, if it is determined that the subtraction result is not negative, the process moves to step S260-33, and if it is determined that the subtraction result is negative, the process moves to step S260-31.

(Step S260-31)
The main CPU 200a clears the value of the advantageous section MY counter (sets it to 0).

(Step S260-33)
The main CPU 200a updates the value of the advantageous section MY counter to the value subtracted in step S260-27 or the value cleared in step S260-31.

(Step S260-35)
The main CPU 200a determines whether or not the replay combination has won. As a result, if it is determined that the replay combination has not won, the process moves to step S270, and if it is determined that the replay combination has won, the process moves to step S260-37.

(Step S260-37)
The main CPU 200a sets the number of coins to be put in to the number of coins to be paid out.

(Step S260-39)
The main CPU 200a turns on the replay flag.

(Step S260-41)
The main CPU 200a sets the number of automatically inserted sheets.

(Step S270)
The main CPU 200a executes a payout process for paying out medals. Note that this payout process will be described later.

FIG. 38 is a flowchart illustrating the payout process (S270) in the main control board 200.

(Step S270-1)
The main CPU 200a acquires the re-gaming operation flag.

(Step S270-3)
The main CPU 200a sets a payout start command in the transmission buffer indicating that the payout of medals has started.

(Step S270-5)
The main CPU 200a determines whether or not the replay combination has won based on the replay active flag acquired in step S270-1. As a result, if it is determined that the replay combination has won, the process moves to step S270-41, and if it is determined that the replay combination has not won, the process moves to step S270-7.

(Step S270-7)
The main CPU 200a executes a main display display process to display 0 on the main payout display section 132.

(Step S270-9)
The main CPU 200a determines that there is no payout (the number of coins to be paid out is 0). As a result, if it is determined that there is no payout, the process moves to step S270-35, and if it is determined that there is a payout, the process moves to step S270-11.

(Step S270-11)
The main CPU 200a determines whether the number of stored sheets is 50 or more. As a result, if it is determined that the stored number is 50 or more, the process moves to step S270-13, and if it is determined that the stored number is not 50 or more, the process moves to step S270-15.

(Step S270-13)
The main CPU 200a executes a medal payout device control process to pay out one medal from the medal payout device 142, and moves the process to step S270-23.

(Step S270-15)
The main CPU 200a sets a payout start interval timer.

(Step S270-17)
The main CPU 200a determines whether the payout start timer is not 0, that is, whether it is the first payout. As a result, if it is determined that it is the first payout time, the process moves to step S270-21, and if it is determined that it is not the first payout time, the process moves to step S270-19.

(Step S270-19)
The main CPU 200a executes a timer wait process of waiting until the payout start interval timer becomes 0.

(Step S270-21)
The main CPU 200a increments the number of stored sheets by one.

(Step S270-23)
The main CPU 200a sets a payout execution command indicating that one medal has been paid out in the transmission buffer.

(Step S270-25)
The main CPU 200a executes main display pre-display processing for displaying the number of coins that have already been paid out on the main payout display section 132.

(Step S270-27)
The main CPU 200a determines whether the game is in a bonus game state. As a result, if it is determined that the bonus game state is not present, the process advances to step S270-31, and if it is determined that the bonus game state is present, the process advances to step S270-29.

(Step S270-29)
The main CPU 200a increments the number of medals obtained during bonus operation, which is the number of medals paid out in the bonus game state, by one.

(Step S270-31)
The main CPU 200a determines whether the payout of the number of medals to be paid out has not been completed. As a result, if it is determined that the payout has not been completed, the process moves to step S270-11, and if it is determined that the payout has finished, the process moves to step S270-33.

(Step S270-33)
The main CPU 200a executes a payout end process to end the payout of medals.

(Step S270-35)
The main CPU 200a determines whether an over error has been detected. As a result, if it is determined that no over error has been detected, the process moves to step S270-41, and if it is determined that an over error has been detected, the process moves to step S270-37.

(Step S270-37)
The main CPU 200a sets an error code "E5" indicating an over error.

(Step S270-39)
The main CPU 200a displays an error, requests a warning sound, and executes error wait processing for waiting for error recovery.

(Step S270-41)
The main CPU 200a sets a payout end command indicating that the payout of medals has ended in the transmission buffer.

(Step S280)
The main CPU 200a executes a game transition process that performs a game state transition, a process for managing an advantageous section, and the like. Note that this game transfer process will be described later.

FIG. 39 is a flowchart illustrating the game transfer process (S280) in the main control board 200.

(Step S280-1)
The main CPU 200a acquires the replay active flag, and turns on or off a bit corresponding to a replay indicator (not shown) indicating that the next game is a replay based on the acquired replay active flag. For this purpose, the stop indicator output bit off (output image) is set, and replay indicator control processing is executed to update the output bit of the set output image.

(Step S280-3)
When a bonus combination is won, the main CPU 200a executes an accessory activation symbol display process that sets various parameters for controlling the bonus game state.

(Step S281)
The main CPU 200a executes a state-specific module execution process that executes a module for each production state and section state. In the state-specific module execution process, the module (process) corresponding to the performance state being transitioned to is read from the main ROM 200b and executed. Below, modules related to the features of this embodiment will be explained in detail, and explanations of modules unrelated to the features of this embodiment will be omitted.

(Step S280-5)
The main CPU 200a executes a bonus operation termination process to shift the gaming state to a non-internal gaming state when the number of coins acquired during bonus operation reaches a predetermined number in the bonus gaming state.

(Step S280-7)
The main CPU 200a executes advantageous section update processing for managing advantageous sections.

(Step S280-9)
The main CPU 200a determines whether the next game is in an AT performance state. As a result, if it is determined that the next game is not in the AT effect state, the process moves to step S280-15, and if it is determined that the next game is in the AT effect state, the process moves to step S280-11.

(Step S280-11)
The main CPU 200a determines whether the game is in a bonus game state. As a result, if it is determined that the bonus game state is not present, the process moves to step S280-15, and if it is determined that the bonus game state is present, the process moves to step S280-13.

(Step S280-13)
The main CPU 200a sets an advantageous lamp flag to turn on the section indicator 160.

(Step S280-15)
The main CPU 200a executes a production command setting process that sets a production command, which is a command related to an advantageous section, in a transmission buffer.

(Step S280-17)
The main CPU 200a sets a game end command indicating that one game has ended in the transmission buffer.

(Step S280-19)
The main CPU 200a executes terminal board signal output processing for outputting external signals.

(Step S280-21)
The main CPU 200a determines whether the performance wait timer set when ending the advantageous section in step S280-7 is not 0. As a result, if it is determined that the presentation wait timer is not 0, the process moves to step S280-21, and if it is determined that the presentation wait timer is 0, the process moves to step S280-23.

(Step S280-23)
The main CPU 200a sets a gaming status command indicating the gaming status in the transmission buffer.

(Step S280-25)
The main CPU 200a sets a game start command indicating the start of the next game in the transmission buffer, and moves the process to step S200.

FIG. 40 is a flowchart illustrating the normal AT performance state processing (S281) executed in the state-specific module execution processing. The normal AT performance state processing is executed when the performance state is the normal AT performance state.

(Step S281-1)
The main CPU 200a determines whether it is the final game in the normal AT performance state based on the net increase in the number of coins in the normal AT performance state. As a result, if it is determined that this is the final game in the normal AT production state, the process moves to step S281-3, and if it is determined that it is not the final game in the normal AT production state, the normal AT production state processing is ended. .

(Step S281-3)
The main CPU 200a performs the continuous lottery by referring to the continuous lottery table shown in FIGS. 16(a) and 16(b).

(Step S281-5)
The main CPU 200a determines whether the continuous lottery has been won. As a result, if it is determined that the continuous lottery has been won, the process moves to step S281-7, and if it is determined that the continuous lottery has not been won, the process moves to step S281-9.

(Step S281-7)
The main CPU 200a turns on the continuation flag and moves the process to step S281-17.

(Step S281-9)
The main CPU 200a determines whether the value of the advantageous section MY counter is less than 400. As a result, if it is determined that the value of the advantageous section MY counter is less than 400, the process moves to step S281-11, and if it is determined that the value of the advantageous section MY counter is not less than 400, the process proceeds to step S281-15. Transfer processing.

(Step S281-11)
The main CPU 200a performs an advantageous continuation lottery by referring to the advantageous continuation lottery table shown in FIG. 16(c).

(Step S281-13)
The main CPU 200a determines whether or not the advantageous continuation lottery has been won. As a result, if it is determined that the advantageous continuation lottery has been won, the process moves to step S281-17, and if it is determined that the advantageous continuation lottery has not been won, the process moves to step S281-15.

(Step S281-15)
The main CPU 200a sets the next AT flag to a value corresponding to the non-advantageous standby performance state, and also sets the flag for setting the gaming section to the non-advantageous period in step S280-7, and processes the normal AT performance state. end.

(Step S281-17)
The main CPU 200a sets the next AT flag to a value corresponding to the advantageous standby effect state, and ends the normal AT effect state processing.

One game is executed through a series of processes from step S200 to step S280. Thereafter, steps S200 to S280 will be repeated.

Next, the power-off saving process and timer interrupt process in the main control board 200 will be described.

(Evacuation process when the main control board 200 is powered off)
FIG. 41 is a flowchart illustrating a power-off save process in the main control board 200. The main CPU 200a monitors the power-off detection circuit, and when the power supply voltage falls below a predetermined value, interrupts and executes a power-off save process.

(Step S300-1)
When the power-off notice signal is input, the main CPU 200a saves the register.

(Step S300-3)
The main CPU 200a checks the power-off warning signal.

(Step S300-5)
The main CPU 200a determines whether a power-off notice signal is detected. As a result, if it is determined that a power-off notice signal has been detected, the process moves to step S300-11, and if it is determined that a power-off notice signal has not been detected, the process moves to step S300-7. .

(Step S300-7)
The main CPU 200a restores the register.

(Step S300-9)
The main CPU 200a performs processing to permit interrupts, and ends the power-off save processing.

(Step S300-11)
The main CPU 200a executes output port clear processing to stop output from the output port.

(Step S300-13)
The main CPU 200a executes a save process for another area when the power is turned off.

(Step S300-15)
The main CPU 200a executes RAM protect setting processing necessary to prohibit access to the main RAM 300c.

(Step S300-17)
The main CPU 200a sets a predetermined number of times the power outage detection signal has been detected in the counter value of the loop counter in order to set the power outage occurrence monitoring time.

(Step S300-19)
The main CPU 200a subtracts 1 from the value of the loop counter set in step S300-17.

(Step S300-21)
The main CPU 200a determines whether the counter value of the loop counter is not zero. As a result, if it is determined that the counter value is not 0, the process moves to step S300-19, and if it is determined that the counter value is 0, the process moves to the above-described CPU initialization process (step S1000).

Note that if a power outage actually occurs, the operation of the slot machine 100 is stopped while the steps S300-19 to S300-21 are looped.

(Timer interrupt processing of main control board 200)
FIG. 42 is a flowchart illustrating timer interrupt processing in the main control board 200. The main control board 200 is provided with a reset clock pulse generation circuit that generates a clock pulse at every predetermined period (1.49 milliseconds in the simultaneous running reference example, hereinafter referred to as "1.49ms"). Then, when a clock pulse is generated by the reset clock pulse generation circuit, an interrupt is generated and the following timer interrupt processing is executed.

(Step S400-1)
The main CPU 200a saves the register.

(Step S400-3)
The main CPU 200a clears the interrupt flag.

(Step S400-5)
The main CPU 200a reads various input port images and executes port input processing to accurately obtain the latest switch status.

(Step S400-7)
The main CPU 200a outputs the set output image to the output port, and displays the main credit display section 130, main payout display section 132, input number display, start display, stop switch 120a, 120b, and 120c display, and replay display. Dynamic port output processing is executed to control the lighting of the section indicator 160.

(Step S400-9)
The main CPU 200a updates the timer interrupt phase. Note that the timer interrupt phase is one of 0 to 3, and here, when the timer interrupt phase is 0, 1, or 2, 1 is added, and when the timer interrupt phase is 3, it is added to 0. Be changed.

(Step S400-11)
The main CPU 200a performs sub-command transmission processing to transmit the command stored in the transmission buffer to the sub-control board 202.

(Step S400-13)
The main CPU 200a executes stepping motor control processing to control the stepping motor 152.

(Step S400-15)
The main CPU 200a executes an output port image output process to output an output image to the medal payout device 142.

(Step S400-17)
The main CPU 200a executes random number update processing to update various random numbers.

(Step S400-19)
The main CPU 200a executes fraud monitoring processing to detect errors in order to output external signals (external signals 4 and 5) corresponding to the errors to the outside.

(Step S400-21)
The main CPU 200a executes a module (subroutine) corresponding to the timer interrupt processing phase updated in step S400-9. Here, the timer interrupt processing phase is set to one of 0 to 3, and one module is provided corresponding to each of the timer interrupt processing phases 0 to 3 (total of 4). The two modules will be executed once every four times (every 5.96 ms) of timer interrupt processing. For example, a module that executes time monitoring processing for subtracting various timers is associated with one timer interrupt processing phase.

(Step S400-23)
The main CPU 200a executes test signal output processing to output a test signal to the outside.

(Step S400-25)
The main CPU 200a reads various input port images and executes port input processing to accurately obtain the latest switch status.

(Step S400-27)
The main CPU 200a restores the register.

(Step S400-29)
The main CPU 300a allows the interrupt and ends the timer interrupt processing.

<Configuration around the CPU of the main control board>
FIG. 43 is a diagram for explaining electrical connections around the main CPU 200a. Main CPU 200a includes a CPU core 700 and a bus controller 702. The CPU core 700 controls the bus controller 702 through a bus control signal (Bus Cont) output from the BC terminal, reads data from the main ROM 200b, main RAM 200c, or input/output section 704, or writes data to the main RAM 200c. Write. Note that here, as the main CPU 200a, a microprocessor based on the Z80 series CPU sold by LETech is used.

For example, when reading data from the main ROM 200b, the main RAM 200c, or the input/output unit 704, the bus controller 702 outputs a 16-bit address (A[16]) signal, and the main ROM 200b, Identify either the main RAM 200c or the input/output unit 704, control the read (RD) signal, and read the data (D[8]) signal from the main ROM 200b, the main RAM 200c, or the input/output unit 704. . Furthermore, when writing data to the main RAM 200c or the input/output section 704, the bus controller 702 outputs an address (A[16]) signal and a data (D[8]) signal, and writes the data to the main RAM 200c through the decoders 706b and 706c. , or the input/output unit 704, and controls the write (WR) signal to write the data (D[8]) signal to the main RAM 200c or the input/output unit 704.

Here, as will be described later, the address space of the input/output unit 704 is integrated with the address spaces of the main ROM 200b and the main RAM 200c. Therefore, conventionally, a memory request (MREQ) terminal and an I/O request (IORQ) terminal for outputting a signal for specifying whether to access memory or I/O are not provided. By reassigning these two terminals to arbitrary other signals, the degree of freedom in program development can be increased.

The CPU core 700 also has an interrupt/wait (INT/WAIT) signal that triggers the start of interrupt processing, a non-maskable interrupt (NMI) signal that allows interrupt processing to be executed with the highest priority, and a bus signal that is set to high impedance. External signals such as a transitionable bus request (BUSREQ) signal are also input.

FIG. 44 is a block diagram showing the internal configuration of CPU core 700. CPU core 700 includes an external input unit 710, a state control unit 712, a central control unit 714, a register unit 716, and an arithmetic logic unit (ALU) 718. External input unit 710 receives an external signal and outputs control information based on the external signal to state control unit 712 and central control unit 714.

The state control unit 712 determines the operating state of the CPU core 700 by managing and transitioning internal states (RESET, instruction fetch, instruction decoder, calculation, memory load, memory store, HALT, etc.), and also determines the operating state of the CPU core 700 based on the internal state. control information is output to central control unit 714.

The central control unit 714 extracts an operation code (instruction) from the input data (DI[8]) input via the bus controller 702, and controls the ALU 718 based on the command decoded by the instruction decoder. Further, the central control unit 714 obtains necessary information from each register of the register unit 716 and updates each register using the decoded command.

The register unit 716 includes selector ports 722a, 722b, and 722c, an input bank selector 724, a first register bank 726, a second register bank 728, an output bank selector 730, an address port 732, and an individual register 734. The individual registers 734 include a 16-bit program counter (PC) that indicates the address of the program to be executed next, an 8-bit interrupt (I) register used in interrupt mode, and an 8-bit interrupt (I) register that counts opcode fetch cycles. It includes a bit refresh (R) register and an 8-bit interrupt enable (IFF) register that controls interrupt enable/disable.

In addition, the register unit 716 includes a random number generator for obtaining various random numbers (jackpot determination random number, winning symbol random number, reach group determination random number, reach mode determination random number, fluctuation pattern random number, hit determination random number) related to the big winning lottery. Random values associated with a device (not shown) and latched via input ports (FE73h to FE9Ch) are obtained.

The random number generator operates on a system clock (a clock obtained by dividing an external input by two) and generates random numbers less than a predetermined maximum value. The random number generator is a random number generator that can set the maximum value of random numbers.As a maximum value setting random number generator, it has 4 channels of random number generation that can set a maximum value of 16 bits, and a maximum value of 8 bits. Eight channels of possible random number generation are available. Here, for the 16-bit maximum value setting random number generator, the random number update cycle can be selected within the range of 32 to 47 clocks, and the maximum value setting range can be set within the range of 256 to 65,535. In addition, for the 8-bit maximum value setting random number generator, the random number update cycle can be selected in the range of 16 to 31 clocks, and the maximum value setting range can be set in the range of 16 to 255 for 4 channels, and for the other 4 channels. It can be set in the range of 64 to 255. In addition, as a maximum value fixed random number generator, which is a random number generator with a fixed maximum value, it has 4 channels of random number generation that can set a maximum value of 16 bits, and a random number generator that can set a maximum value of 8 bits. 8 channels are prepared. Here, in the 16-bit maximum value fixed random number generator, the random number update period is fixed to 1 clock, and the maximum value is fixed to 65535. Further, in the 8-bit fixed maximum value random number generator, the random number update period is fixed to 1 clock, and the maximum value is fixed to 255.

In addition, if there are insufficient types of random numbers, the random number obtained from the hardware random number generator (random number generator) is multiplied by a predetermined number in the program, and other random numbers are generated by dividing. Random number generator) is also possible.

FIG. 45 is a diagram illustrating the configuration of the register. Both the first register bank 726 and the second register bank 728 include 8-bit registers (Q, U, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY, SP) are provided. Further, the registers of the first register bank 726 and the second register bank 728 include front registers and back registers. The main CPU 200a can only access the front register of the register bank indicated by the register bank designation register RB in the F register, and cannot access the back register.

Among the registers shown in FIG. 45, the Q register is an 8-bit dedicated register with extended specifications for gaming machines. This Q register is fixed at F0h and is used for accessing the main RAM 200c from F000h to F0FFh. The U register is an 8-bit dedicated register with extended specifications for gaming machines. The U register is fixed at FEh and is used to access the built-in devices (timer, random number generator, external input/output circuit, etc.) connected to the input/output section 704 of FE00h to FEFFh.The A register is used for arithmetic processing and data transfer. The F register is an 8-bit flag register that holds various operation results.As shown in FIG. 45, each bit of the F register is the most significant bit (MSB: S is a sign flag that is set to 1 when the operation result is negative, and Z is a sign flag that is set to 1 when all bits are 0 as a result of the operation. TZ is a zero flag (first zero flag) that is set to 1, and TZ is an extended specification for gaming machines that is set to 1 (value changes) when all bits are 0 by executing a data transfer instruction (LD; load). This is a specific bit flag (second zero flag), and is sometimes called a teaset flag. H is a half-carry flag that the programmer cannot interact with, and RB is a flag that indicates the current register bank (first register bank 726 = 0, first register bank 726 = 0, 2 register bank 728 = 1), P/V is a parity overflow flag, N is an addition/subtraction flag that the programmer cannot interact with, and C is a register bank monitor that indicates whether a carry or borrow occurs as a result of the operation. This is a carry flag that is set to 1 at times.The F register constitutes a pair register AF with the A register.

Furthermore, the B register, C register, D register, E register, H register, and L register are 8-bit general-purpose registers, and each constitutes a 16-bit pair register BC, DE, and HL whose combinations are determined in advance. . The IX register and IY register are 16-bit dedicated registers for index addressing. The SP (stack pointer) register is 16 bits and stores an address that becomes a stack pointer. Q' register, A' register, F' register, B' register, C' register, D' register, E' register, H' register, L' register, IX' register, IY' register are Q register, A register. , F register, B register, C register, D register, E register, H register, L register, IX register, and IY register, which are back registers whose data (contents) can be exchanged by an exchange command with the front registers, and the A' register. and F' registers form a pair register AF', B' and C' registers form a pair register BC', D' and E' registers form a pair register DE', and H' and L registers form a pair register AF'. 'Construct a pair register HL' with registers. The back register and the front register can be used by selecting and swapping either register with the front register using a swap command or the like. On the other hand, register U and register SP are single registers without back registers. In this way, the back register functions as a stack area for the front register when an interrupt process occurs.

By the way, as described above, in the main control board 200, the main CPU 200a controls the progress of the game in cooperation with the main RAM 200c based on the program stored in the main ROM 200b. Programs for executing these functional units are arranged in predetermined areas (used areas) of the main ROM 200b and main RAM 200c.

FIG. 46 is an explanatory diagram showing a memory map. The main ROM 200b is assigned a memory space of 0000h to 3FFFh (12 kbytes), the main RAM 200c is assigned a memory space of F000h to F3FFh (1 kbyte), and the input/output unit 704 is assigned a memory space of FE00h to FEFFh (256 bytes). Memory space is allocated. Note that the instruction code of the program is written in assembler language. Here, the program is composed of instruction codes, and can be read by a computer and cooperate with data and a work area to realize a predetermined process.

A usable area is allocated to the memory space from 0000h to 1DF3h of the main ROM 200b. The usage area is an area for storing programs and data for executing game control processing that controls the progress of the game. Specifically, an initialization means 300, a bet means 302, a winning type lottery means 304, a reel control means 306, a determination means 308, and a payout control are stored in a memory space (control area) limited to 0000h to 11FFh (4.5 kbyte). The command code of the program for executing the game control process for controlling the progress of the game by functioning the means 310, the game state control means 312, the production state control means 314, and the command transmission means 316 is stored, Data used for the game control processing program is stored in a memory space (data area) limited to .0 kbyte). Further, a comment area is allocated to the memory space from 1E00h to 1FFFh, and a program management area is allocated to the memory space from 3FC0h to 3FFFh. Further, a separate area (unused area) is allocated to the memory space from 2000h to 3FBFh. The separate area is an area for storing programs and data that are not specified to be stored in the used area, as will be described later. Specifically, the memory space from 2000h to 3FBFh contains instruction codes and program data for programs that perform part or all of gaming machine test processing and security-related processing that do not affect the progress of the game. Stored. The test process for gaming machines is the test process for the slot machine 400 described in the connection specifications for reel-type gaming machine test machines (fourth edition). Security-related processing is processing for identifying abnormal conditions for the purpose of preventing fraud by third parties and discovering defects, and includes, for example, the above-mentioned backup flag determination and checksum execution. Note that there is no limit to the storage capacity of the separate area, and in the example of FIG. 46, it can be freely allocated to storage areas other than the used area, comment area, and program management area.

As described above, the main CPU 200a may perform not only game control processing but also gaming machine test processing and security related processing. However, the storage capacity of the used area is predetermined, and for example, as shown in FIG. 46, the control area is limited to 4.5 kbytes and the data area is limited to 3.0 kbytes. Therefore, if programs and data for not only gaming control processing but also testing processing for gaming machines and security-related processing are allocated to the usage area, the storage area for performing gaming control processing will be limited accordingly. Here, the program (used program) and data for executing the game control process must be stored in the usage area, but it must not affect the progress of the game other than the game control process (not directly related). Programs (separate programs) and data for executing processes (gaming machine test processes, security-related processes, etc.) can be stored in both the used area and the separate area. Therefore, at least part of the programs and data for executing backup flag determination processing and checksum execution processing, which correspond to security-related processing, are stored in a storage area different from the used area (other than the used area). It is written in a separate area that is part of my work.

In this way, if there is a mixture of processing performed in the used area (here, gaming control processing) and processing that does not necessarily need to be performed in the used area (here, security-related processing), gaming control processing To store programs (used programs) and data for executing in the used area, and execute processes that do not have to be performed in the used area and do not affect the progress of the game other than game control processing (security-related processing) It is desirable to store programs (separate programs) and data in separate areas. By dividing the storage area into a plurality of areas in this way, there is an extra storage area (capacity) in the used area for the program moved to another area. Therefore, it becomes possible to allocate the usage area to the game control process (usage program) accordingly.

However, even when the storage area is divided into a used area and a separate area as described above, the fairness of the gaming machine must be ensured. Therefore, the following conditions (1) to (6) are defined in order to ensure the fairness of the gaming machine and to appropriately divide the roles between the usage area and the separate area.

Condition (1): Programs placed in a separate area are used for the purpose of outputting signals necessary for testing gaming machines (gaming machine test processing) and preventing fraud (security-related processing), and are not intended to harm the fairness of gaming. (no damage). Condition (2): The control area and data area, which are separate from the used area, must be placed in clearly separated areas. Condition (3): The program placed in a separate area (separate program) is statically called and executed from the program in the used area (use program). In addition, the call destination address must be clearly stated in the program list. Condition (4): Programs placed in separate areas should be modularized for each function, and when called, the contents of all registers used in the used area should be protected. Condition (5): RAM in each area can only be accessed from the used area or from another area, and cannot be updated. Condition (6): It is not possible to call a subroutine in the control area of the used area from the control area of another area. Note that since a subroutine for performing interrupt processing is provided in the used area, it is necessary to disable interrupts when using a control area in another area. In addition, in order to properly perform the gaming control process, the time from disabling interrupts to canceling the disabling of interrupts must be within the interval of interrupt processing in the gaming control process (for example, 1.49 msec). Must be. Therefore, when calling a subroutine that uses a control area in another area, the total time required for one call is set to be within the interval of the interrupt process of the game control process.

Further, a usable area is allocated to the memory space F000h to F1FFh of the main RAM 200c. Specifically, the memory space from F000h to F13Fh is assigned a work area for the game control processing, and is used for managing variables such as timers, counters, and flags. A stack area for the game control process is allocated to the memory space F1C0h to F1FFh. Further, a separate area is allocated to the memory space of F200h to F3FFh of the main RAM 200c. Specifically, the memory spaces F210h to F22Fh are allocated work areas for some or all of the security-related processes, and are used for managing variables such as timers, counters, and flags. A stack area for some or all of the security-related processes is allocated to the memory spaces F230h to F246h.

Furthermore, an input/output unit 704 is allocated to the memory space of FE00h to FEFFh. Conventionally, in order to access the device corresponding to the input/output unit 704, a 256-byte I/O space was provided independent of the memory space. In contrast, in this embodiment, the MREQ and IORQ signals are eliminated, and the memory and input/output unit 704 are accessed in common by the RD and WR signals. Further, a U register is provided as hardware for specifying an upper 8-bit address for accessing a device connected to the input/output unit 704, and the 8-bit upper address is specified in advance. As a result, the I/O space that was provided independently from the memory space is integrated into the memory space and becomes one address space, and when an IN instruction or an OUT instruction is executed, the input/output unit 704 assigned to the memory space On the other hand, the upper 8 bits are specified by the U register, and the lower 8 bits can be accessed using the lower 8 bits specified by the operands of the IN and OUT instructions.

In this embodiment, the LDQ instruction uses the Q register to access memory space (mainly data area, work area), and the IN and OUT instructions use the U register to access devices (timers, random number generators, external input/output It becomes possible to write programs to access I/O of circuits, etc.). This configuration makes it easier to understand the program at the time of design. In addition, memory and I/O, which were previously accessed by specifying a 16-bit address, can now be accessed using a lower 8-bit operand, and the program capacity can be compressed. Furthermore, by having multiple upper specification registers such as the Q register, Q' register, and U register, the number of replacements due to reuse of upper registers is reduced compared to when there is only one upper register, further reducing program capacity. be able to.

In the above example, the IN instruction and the OUT instruction accessed the memory space corresponding to the I/O space, but the IN instruction and the OUT instruction may also directly access the memory space. For example, when accessing three 256-byte areas on memory, specify the upper 8 bits of each in the Q register, Q' register, and U register, and use the LDQ instruction, IN instruction, and OUT instruction to access each area. This can be achieved by accessing.

Hereinafter, specific instruction codes (command groups) for realizing each of the above-mentioned processes (modules) will be explained. Here, the general-purpose lottery process and the variable initialization process will be specifically explained.

(General-purpose lottery processing)
General-purpose lottery processing is performed by a COM_PRE module that performs general-purpose setting processing, a COM_CHK module that executes return address confirmation processing, a RAD_CHK module that calls the COM_CHK module, and a COM_LOT module that executes specific processing related to general-purpose lottery related to the balls put out. carried out by. Among these, the COM_PRE module is a general-purpose module. A general-purpose module is a subroutine of the same processing used to execute a program, and indicates a module that is particularly frequently called by other modules. A general-purpose module is often placed near the lowest address 0000H on the memory map shown in FIG. 46. This is because by placing a frequently called general-purpose module near 0000H, it can be called using not only the command "CALL" used for calling but also another command "RST". Note that an example will be described in which the COM_PRE module is placed at 0028H on the memory map.

Here, the command "RST" is a low numerical address near 0000H in the memory map, and is one of multiple addresses (0008H, 0010H, 0018H, 0020H, 0028H, 0030H, 0038H, 0040H) separated by 8 bytes. This is a command that can be called. The command "RST" has the same execution cycle as the normal command "CALL" used for calling, which is "4", but the command size of the normal command "CALL" is "3", while the command "RST" The command size of is "1". Therefore, by using the command "RST", the program can be shortened.

The main CPU 200a reads a program from the main ROM 200b, executes the read program, calls the COM_PRE module as a subroutine in any process, and executes the COM_PRE module, RAD_CHK module, COM_CHK module, and COM_LOT module. In this way, the general-purpose lottery process is executed.

FIG. 47 is a flowchart showing specific processing of the COM_PRE module, RAD_CHK module, COM_CHK module, and COM_LOT module. The numerical values of step S in this figure will be used only in the explanation of this figure.

When the main CPU 200a calls the COM_PRE module as a subroutine as shown in FIG. 47(a), it temporarily restores the stack pointer value to the DE register (S1), and immediately saves the contents of the DE register to the stack area (S2). . In this way, the value of the stack pointer, that is, the return address (current return address) of the original routine that called the subroutine can be held in the DE register while maintaining the state of the stack area. Then, the main CPU 200a sets the address of the general-purpose lottery offset selection table (the initial value of the return address to be compared) in the HL register (S3), and moves to the RAD_CHK module (S4).

In the RAD_CHK module, the main CPU 200a calls the COM_CHK module, which is a common module for acquiring a reference address, as shown in FIG. 47(b) (S5). In the COM_CHK module, the main CPU 200a compares the current return address with the value of the HL register (return address to be compared) as shown in FIG. The HL register is incremented by 2 to set a reference address (S7). Here, based on the comparison result in step S6, it is determined whether the current return address matches the value of the HL register (S8), and if they do not match (NO in S8), the return address to be compared is determined. The HL register is incremented by 2 in order to set (S9), and the process returns to step S6, where the comparison process is repeated until the current return address and the value of the HL register match. Also, if the current return address matches the value of the HL register (YES in S8), the reference address is obtained (S10), the COM_CHK module is terminated, and the routine returns to the routine one level higher (RAD_CHK module). (S11).

When the main CPU 200a moves from the RAD_CHK module to the COM_LOT module shown in FIG. 47(d), it executes specific processing related to general-purpose lottery based on the value specified by the reference address, and returns to the routine that called the COM_PRE module. Return (S12).

FIG. 48 is an explanatory diagram for explaining an example of commands for realizing the COM_PRE module, RAD_CHK module, COM_CHK module, and COM_LOT module. Of these, FIG. 48(a) shows a command group of the COM_PRE module, FIG. 48(b) shows a command group of the RAD_CHK module and COM_LOT module, and FIG. 48(c) shows a command group of the COM_CHK module. . The flowchart shown in FIG. 47 is realized, for example, by the program shown in FIG. 48.

The start position of the COM_PRE module is set to 0028H by the command "ORG 0028H" in the first line of FIG. 48(a). The index “COM_PRE:” on the second line indicates the start address of the COM_PRE module. The data saved in the stack area is returned to the DE register by the command "POP DE" on the third line. The command on the third line corresponds to step S1 in FIG. 47(a). The command "PUSH DE" on the fourth line saves the value of the DE register to the stack area. The command on the fourth line corresponds to step S2 in FIG. 47(a). In this way, the return address (current return address) of the original routine that called the subroutine is held in the DE register. By the command "LD HL, T_SEL_CLO" on the fifth line, the address of the general-purpose lottery offset selection table (the initial value of the return address to be compared) is stored in the HL register. The command on the fifth line corresponds to step S3 in FIG. 47(a). The command "JP RAD_CHK" on the sixth line moves to the index "RAD_CHK:" indicating the start address of the RAD_CHK module. The command on the sixth line corresponds to step S4 in FIG. 47(a).

Note that the reason for moving from the COM_PRE module to the RAD_CHK module here is as follows. In other words, the general-purpose module called by the command "RST" has a limit on its number and the area it occupies (for example, the number is 8 and the area is 8H), and in order to use it effectively, the command of the general-purpose module must be Groups must be kept within 8H. In this way, the general-purpose module executes only the minimum necessary commands and moves to other areas to perform the remaining processing. Here, the COM_PRE module is once called by the command "RST", and moved to the RAD_CHK module by the command "JP RAD_CHK", and the remaining processes necessary for the general-purpose lottery process are executed in the processes after the RAD_CHK module.

The index "RAD_CHK:" in the first line of FIG. 48(b) indicates the start address of the RAD_CHK module. The command "CALLF COM_CHK" on the second line calls the COM_CHK module as a subroutine. The command on the second line corresponds to step S5 in FIG. 47(b). The index “COM_LOT:” on the third line indicates the start address of the COM_LOT module. Then, specific processing regarding the general-purpose lottery is executed, and the command "RET" on the fourth line ends the COM_LOT module and returns to the routine that called the COM_PRE module. The command on the fourth line corresponds to step S12 in FIG. 47(d).

The index “COM_CHK:” in the first line of FIG. 48(c) indicates the start address of the COM_CHK module. The command "CP (HL), DE" on the second line compares the value stored in the address indicated by the HL register (return address to be compared) and the value stored in the DE register (current return address). compare.

FIG. 49 is an explanatory diagram for explaining the processing of the command "CP (HL), DE". Assume that the COM_PRE module shown in FIG. 48(a) is called by the command "RST COM_PRE" on the first line in the process shown in FIG. 49(a). Then, the current return address becomes the address of the next command. Therefore, at the time when the command "CP (HL), DE" on the second line of FIG. 48(c) is executed, the command following the command "RST COM_PRE" on the first line of FIG. 49(a) is stored in the DE register. address has been set.

On the other hand, in the general-purpose lottery offset table shown in FIG. 49(b), a plurality of combinations of return addresses (2 bytes) and reference addresses (2 bytes) to be compared are consecutively arranged every 4 bytes. Therefore, the address of the index "T_SEL_CLO:" is initially held in the HL register at the time when the command "CP (HL), DE" on the second line of FIG. 48(c) is executed. Here, when the command "CP (HL), DE" is executed, the value stored in the address ("T_SEL_CLO") indicated in the HL register, that is, "@ADT_HED_FLZ" (return address to be compared) and the DE register , that is, the address of the next command (current return address) after the command "RST COM_PRE" in the first line of FIG. 49(a). Here, "@ADT_HED_FLZ", which is the value stored in the address ("T_SEL_CLO") indicated in the HL register, is determined by the definition "@ADT_HED_FLZ EQU $" in the second line of FIG. 49(a). ), the address of the next command after the command "RST COM_PRE" on the first line is copied. Therefore, in this example, (value stored at the address indicated in the HL register) = (value of the DE register), and as a result of executing the command "CP (HL), DE", the zero flag will be set to 1. . The command on the second line of FIG. 48(c) corresponds to step S6 of FIG. 47(c).

Returning to FIG. 48(c), the command "INC HL" on the third line adds 1 to the value of the HL register. Furthermore, the command "INC HL" on the fourth line further adds 1 to the value of the HL register. Thus, the HL register is incremented by two. As can be understood with reference to FIG. 49(b), this is done by changing the return address to be compared in the even numbered row (for example, the second row) to the reference address in the odd numbered row (for example, the third row). Become. The commands on the third and fourth lines in FIG. 48(c) correspond to step S7 in FIG. 47(c).

If the result of the command “CP (HL), DE” on the second line is zero flag = 1 (Z) by the command “JR Z, COM_CHK01” on the fifth line in FIG. 48(c), the index on the ninth line Move to “COM_CHK01:”. For example, according to the example in FIG. 49, (“@ADT_HED_FLZ” which is the value stored in the address (“T_SEL_CLO”) indicated in the HL register) = (the current return value which is the value of the DE register). , the zero flag becomes 1 from the first time, and the index moves to "COM_CHK01:". The command on the fifth line corresponds to step S8 in FIG. 47(c).

Suppose that the result of the command "JR Z, COM_CHK01" on the 5th line in FIG. ), the command "INC HL" on the 6th line adds 1 to the value of the HL register. Furthermore, the command "INC HL" on the seventh line further adds 1 to the value of the HL register. Thus, the HL register is incremented by two. As can be understood with reference to FIG. 49(b), this involves changing the reference address in the odd-numbered row (for example, the 3rd row) to the return address to be compared in the even-numbered row (for example, the 4th row); That is, the comparison target is changed to the next combination of the return address (2 bytes) and reference address (2 bytes) to be compared. Note that, for example, 50 next combinations of return addresses and reference addresses to be compared are prepared. The command "JR COM_CHK" on the 8th line in FIG. 48(c) moves to the index "COM_CHK:" on the 1st line. The commands on the 6th to 8th lines correspond to step S9 in FIG. 47(c).

On the other hand, if the result of the command "JR Z, COM_CHK01" on the 5th line in FIG. ” reads (loads) the 2-byte length value (reference address) stored at the address indicated by the HL register into the DE register, and adds 2 to the value of the HL register. Then, the reference address read out to the DE register by the command "LD HL, DE" on the 11th line is set in the HL register. In this way, the reference address ("T_HED_FLZ" in the example of FIG. 49) can be set in the HL register. The commands on the 10th and 11th lines correspond to step S10 in FIG. 47(c). Then, the command "RET" on the 12th line ends the COM_CHK module and returns to the routine one step above. The command on the 12th line corresponds to step S11 in FIG. 47(c).

(variable initialization process)
Variable initialization processing is performed by the COM_PRE2 module that performs general-purpose setting processing, the COM_CHK module that performs return address confirmation processing, the RAD_CHK2 module that calls the COM_CHK module, and the TABLSET module that performs table content setting preprocessing. Such variable initialization processing is, for example, the setting value switching data table setting processing S120-5 of the setting value switching processing shown in FIG. 13, the error weight processing S210-11 of the gaming medal insertion processing 210 shown in FIG. 17, etc. , called by various modules. Also, in the variable initialization process, the COM_PRE2 module is a general-purpose module like the COM_PRE module. Note that an example will be described in which the COM_PRE2 module is placed at 0030H on the memory map.

The main CPU 200a reads a program from the main ROM 200b, executes the read program, calls the COM_PRE2 module as a subroutine in any process, and executes the COM_PRE2 module, RAD_CHK2 module, COM_CHK module, and TABLSET module. Here, in this way, predetermined values (initial values) are set in the variables of the main RAM 200c.

FIG. 50 is a flowchart showing specific processing of the COM_PRE2 module, RAD_CHK2 module, COM_CHK module, and TABLSET module. The numerical values of step S in this figure will be used only in the explanation of this figure.

When the main CPU 200a calls the COM_PRE2 module as a subroutine as shown in FIG. 50(a), it temporarily restores the stack pointer value to the DE register (S1), and immediately saves the contents of the DE register to the stack area (S2). . In this way, the value of the stack pointer, that is, the return address (current return address) of the original routine that called the subroutine can be held in the DE register while maintaining the state of the stack area. Then, the main CPU 200a sets the address of the general-purpose lottery offset selection table 2 (the initial value of the return address to be compared) in the HL register (S3), and moves to the RAD_CHK2 module (S4).

In the RAD_CHK2 module, the main CPU 200a calls the COM_CHK module, which is a common module for acquiring a reference address, as shown in FIG. 50(b) (S5). In the COM_CHK module, the main CPU 200a performs steps S6 to S11 as shown in FIG. 50(c) to obtain a reference address that is the address of a table that will be referenced later by the TABLSET module. Since such processing has already been explained as steps S6 to S11 in FIG. 47(c), detailed explanation thereof will be omitted here. When the reference address is obtained, the COM_CHK module is terminated and the routine returns to the routine one step above (RAD_CHK2 module).

In the TABLSET module, the main CPU 200a reads the 1-byte value stored at the address indicated by the HL register into the B register, as shown in FIG. 50(d) (S12). This 1-byte value indicates the number of data. Next, the main CPU 200a stores the data at the address specified by adding "2" to the HL register to the address specified by the value stored at the address shown by adding "1" to the HL register. The next address to be transferred is set by adding "2" to the value of the HL register (S13). Next, the main CPU 200a decrements (subtracts by "1") the value of the B register, and determines whether the decremented result is 0 (S14). Here, if the decremented result is not 0 (NO in S14), the process from step S13 is repeated, and if the decremented result is 0 (YES in S14), the corresponding TABLSET module is terminated and Return to the routine (S15).

FIG. 51 is an explanatory diagram for explaining an example of commands for realizing the COM_PRE2 module, RAD_CHK2 module, COM_CHK module, and TABLSET module. Of these, FIG. 51(a) shows a command group of the COM_PRE2 module, FIG. 51(b) shows a command group of the RAD_CHK2 module and TABLSET module, and FIG. 51(c) shows a command group of the COM_CHK module. , FIG. 51(d) shows the arrangement of 1-byte data groups in the program data of the main ROM 200b, and FIG. 51(e) shows the arrangement of 1-byte data groups in the work area of the main RAM 200c. The flowchart shown in FIG. 50 is realized, for example, by the program shown in FIG. 51.

The start position of the COM_PRE2 module is set to 0030H by the command "ORG 0030H" in the first line of FIG. 51(a). The index “COM_PRE2:” on the second line indicates the start address of the COM_PRE2 module. The data saved in the stack area is restored to the DE register by the command "POP DE" on the third line. The command on the third line corresponds to step S1 in FIG. 50(a). The command "PUSH DE" on the fourth line saves the value of the DE register to the stack area. The command on the fourth line corresponds to step S2 in FIG. 50(a). In this way, the return address (current return address) of the original routine that called the subroutine is held in the DE register. By the command "LD HL, T_SEL_CLO_2" on the fifth line, the address of the general-purpose lottery offset selection table 2 (the initial value of the return address to be compared) is stored in the HL register. The command on the fifth line corresponds to step S3 in FIG. 50(a). The command "JP RAD_CHK2" on the sixth line moves to the index "RAD_CHK2:" indicating the start address of the RAD_CHK2 module. The command on the sixth line corresponds to step S4 in FIG. 50(a).

The reason for moving from the COM_PRE2 module to the RAD_CHK2 module here is the same as the reason for moving from the COM_PRE module to the RAD_CHK module described above. Here, the COM_PRE2 module is called once with the command "RST", the command "JP RAD_CHK2" is used to move to the RAD_CHK2 module, and the remaining processing necessary for variable initialization is executed in the RAD_CHK2 module.

The index "RAD_CHK2:" in the first line of FIG. 51(b) indicates the start address of the RAD_CHK2 module. The command "CALLF COM_CHK" on the second line calls the COM_CHK module shown in FIG. 51(c) as a subroutine, and sets a reference address (for example, "T_ERR_RCV") in the HL register. Since such a COM_CHK module has already been explained using FIG. 48(c), detailed explanation thereof will be omitted here. The command on the second line corresponds to step S5 in FIG. 50(b).

The index “TABLSET:” in the third line of FIG. 51(b) indicates the start address of the TABLSET module. The command "PUSH BC" on the fourth line saves the value of the BC register to the stack area. Interrupts are prohibited by the command "DI" on the fifth line.

The 1-byte value stored at the address indicated by the HL register is read into the B register by the command "LD B, (HL)" on the 6th line of FIG. 51(b). At this time, a reference address (for example, "T_ERR_RCV") is set in the HL register by the COM_CHK module. Therefore, the 1-byte value "(T_ERR_RCV_-T_ERR_RCV)/2" in the second line of FIG. 51(d) is read to the B register as the data number (transfer repetition number). Note that "T_ERR_RCV_" is the address following the last address of the 1-byte data group that is the transfer source, and T_ERR_RCV is the first address of the 1-byte data group that is the transfer source, so the value of T_ERR_RCV_ - T_ERR_RCV (indicating the number of data The value of 1-byte value) is the total number of bytes of the 1-byte value, and by dividing that value by 2, which is the number of combinations of address and value, the number of data is derived. In the example of FIG. 51(d), the number of data is 9/2=4. The command on the sixth line corresponds to step S12 in FIG. 50(d).

The index “TABLSET01:” in the seventh line of FIG. 51(b) indicates the start address of the repetitive process. The command "INLD AC, (HL)" on the 8th line and the command "LDQ (C), A" on the 9th line specify the value stored at the address indicated by adding "1" to the HL register. The value stored in the address indicated by adding "2" to the HL register is stored in the address to be transferred, and "2" is added to the value of the HL register to set the next address to be transferred. The commands on the 8th and 9th lines correspond to step S13 in FIG. 50(d).

For example, if the HL register has the value of the address "T_ERR_RCV", the lower 1 byte value of the 2-byte variable "_ERR_NUM" in the third line of FIG. 51(d) is stored in the C register, and The value "0" in the third line is stored in the A register.

In addition, the command "LDQ (C), A" on the 9th line of FIG. , is a command to store the value of the A register.

For example, the value of the C register, that is, the value of the lower 1 byte of "_ERR_NUM" is set as the lower 1 byte of the address, and the value of the A register, that is, the value of "0" is stored in that address.

Here, in FIGS. 51(d) and 51(e), the variable "_ERR_NUM" indicates the error number, the variable "_CRE_TMR" indicates the credit button detection timer, and the variable "_CRE_FLG" indicates the credit button detection flag. , and the variable "_SNS_OLD" indicates the previous state of the medal passing sensor bit.

Next, the value of the B register is decremented (subtracted by 1) by the command "DJNZ TABLSET01" on the 10th line of FIG. 51(b), and if the decremented result is not 0, it moves to the address "TABLSET01" , if the decremented result is 0, the process moves to the command next to the command in question. Here, the number of data is "4", so if the process from "TABLSET01" is repeated four times, the value of the B register becomes 0. The command on the 10th line corresponds to step S14 in FIG. 50(d).

Interruption is permitted by the command "EI" on the 11th line of FIG. 51(b). The command "POP BC" on the 12th line causes the data saved in the stack area to be returned to the BC register. Then, the command "RET" on the 13th line returns to the routine one stage higher. The command on the 13th line corresponds to step S15 in FIG. 50(d).

(Commonization of general-purpose lottery processing and variable initialization processing)
As described above, the general-purpose lottery process and the variable initialization process share and call the COM_CHK module that executes the return address confirmation process. Therefore, there is no need to prepare a COM_CHK module for each of the general-purpose lottery process and the variable initialization process, and the capacity of the main ROM 200b can be reduced accordingly.

However, between the general-purpose lottery process and the variable initialization process, the module that specifically performs the process after acquiring the reference address is different depending on the COM_CHK module (COM_LOT module, TABLSET module). Therefore, as described above, the general-purpose lottery process and the variable initialization process are performed independently, and a common COM_CHK module is called during the process. Specifically, in the general-purpose lottery process, a common COM_CHK module is called in the RAD_CHK module in a flow that reliably moves to the COM_LOT module via the COM_PRE module and the RAD_CHK module. On the other hand, in the variable initialization process, the common COM_CHK module was called in the RAD_CHK2 module in order to ensure a transition to the TABLSET module via the COM_PRE2 module and the RAD_CHK2 module. In other words, two general-purpose modules, the COM_PRE module and the COM_PRE2 module, were prepared in order to independently execute the COM_LOT module and the TABLSET module.

Here, further reduction in the capacity of the main ROM 200b will be considered. For example, the reference address to be acquired by the common COM_CHK module differs between the general-purpose lottery process and the variable initialization process. Therefore, depending on the position of the reference address, it can be determined whether the process is a general-purpose lottery process or a variable initialization process. Here, the migration destination is determined to be the COM_LOT module or the TABLSET module, depending on the "reference address" resulting from the execution of the common COM_CHK module. This eliminates the need to go through the COM_PRE module or COM_PRE2 module in advance. Therefore, not only the COM_CHK module, but also the COM_PRE module and the RAD_CHK module can be shared. In this way, it is possible to further reduce the capacity of the main ROM 200b. Note that here, the RAD_CHK module and the COM_CHK module are integrated into a RAD_CHK module. Further, the COM_PRE module and the RAD_CHK module are collectively referred to as a first module.

FIG. 52 is a flowchart showing other processing of the COM_PRE module, RAD_CHK module, COM_LOT module, and TABLSET module. The numerical values of step S in this figure will be used only in the explanation of this figure.

As shown in FIG. 52(a), when the main CPU 200a calls the COM_PRE module (first module), which is a common and general-purpose module as a subroutine, it temporarily restores the stack pointer value to the DE register (S1), and immediately The contents of are saved in the stack area (S2). In this way, the value of the stack pointer, that is, the return address (current return address) of the original routine that called the subroutine can be held in the DE register while maintaining the state of the stack area. Then, the main CPU 200a sets the address of the general-purpose lottery offset selection table (the initial value of the return address to be compared) in the HL register (S3), and moves to the RAD_CHK module (S4).

The main CPU 200a compares the current return address and the value of the HL register (return address to be compared) in the RAD_CHK module (first module), which is a common module, as shown in FIG. 52(b) (S5), The HL register is incremented by 2 to set the reference address (S6). Here, based on the comparison result in step S5, it is determined whether the current return address matches the value of the HL register (S7), and if they do not match (NO in S7), the return address to be compared is determined. The HL register is incremented by 2 in order to set (S8), and the process returns to step S5, where the comparison process is repeated until the current return address and the value of the HL register match. Furthermore, if the current return address matches the value of the HL register (YES in S7), a reference address is acquired (S9). In this way, the reference address (specific address) can be extracted based on the return address of the program that called the COM_PRE module.

Next, the main CPU 200a subtracts a predetermined boundary address from the address in the table (S10). In this embodiment, an aggregate of multiple combinations of return addresses and reference addresses to be compared is used for general lottery processing, and a collection of multiple combinations of return addresses and reference addresses to be compared is used for variable initialization processing. Separate the two aggregates from the juxtaposed aggregates, and set the address of one to be larger than the address of the other. Here, an aggregate of multiple combinations of return addresses and reference addresses to be compared used for general-purpose lottery processing is a collection of multiple combinations of return addresses and reference addresses to be compared used for variable initialization processing. The address is set to be larger than the aggregate. In addition, the boundary address is a collection of multiple combinations of return addresses and reference addresses to be compared, used for general-purpose lottery processing, and a combination of return addresses and reference addresses to be compared, used for variable initialization processing. This is an address located at the boundary to separate two aggregates from a plurality of aggregates arranged side by side. Therefore, for the combination of return address and reference address to be compared used in general-purpose lottery processing, the result of subtracting a predetermined boundary address from the table address is positive or 0 (the specific address is equal to or higher than the boundary address), and the variable Regarding the combination of return address and reference address to be compared used in the initialization process, the result of subtracting a predetermined boundary address from the address in the table is negative (the specific address is less than the boundary address).

The main CPU 200a obtains a reference address in order to restore the subtracted HL register (S11), as shown in FIG. 52(b). If the subtraction result in step S10 is negative (YES in S12), the main CPU 200a moves to the TABLSET module (third module), and if the subtraction result is positive or 0 (NO in S12), the main CPU 200a moves to the COM_LOT module (third module). 2 module).

When the main CPU 200a moves from the RAD_CHK module to the COM_LOT module shown in FIG. The process returns to the called routine (S13).

When the main CPU 200a moves from the RAD_CHK module to the TABLSET module, it reads the 1-byte value stored at the address indicated by the HL register into the B register as shown in FIG. 52(d) (S14). This 1-byte value indicates the number of data. Next, the main CPU 200a stores the data at the address specified by adding "2" to the HL register to the address specified by the value stored at the address shown by adding "1" to the HL register. The next address to be transferred is set by adding "2" to the value of the HL register (S15). Next, the main CPU 200a decrements (subtracts by "1") the value of the B register, and determines whether the decremented result is 0 (S16). Here, if the decremented result is not 0 (NO in S16), the process from step S15 is repeated, and if the decremented result is 0 (YES in S16), the corresponding TABLSET module is terminated and the Return to the routine (S17). In this way, variable initialization processing is executed based on the value specified by the reference address (specific address).

FIG. 53 is an explanatory diagram for explaining an example of commands for realizing the COM_PRE module, RAD_CHK module, COM_LOT module, and TABLSET module. Of these, FIG. 53(a) shows a command group of the COM_PRE module, FIG. 53(b) shows a command group of the RAD_CHK module and COM_LOT module, and FIG. 53(c) shows a command group of the TABLSET module. . The flowchart shown in FIG. 52 is realized, for example, by the program shown in FIG. 53.

The start position of the COM_PRE module is set to 0028H by the command "ORG 0028H" in the first line of FIG. 53(a). The index “COM_PRE:” on the second line indicates the start address of the COM_PRE module. The data saved in the stack area is returned to the DE register by the command "POP DE" on the third line. The command on the third line corresponds to step S1 in FIG. 52(a). The command "PUSH DE" on the fourth line saves the value of the DE register to the stack area. The command on the fourth line corresponds to step S2 in FIG. 52(a). In this way, the return address (current return address) of the original routine that called the subroutine is held in the DE register. By the command "LD HL, T_SEL_CLO" on the fifth line, the address of the general-purpose lottery offset selection table (the initial value of the return address to be compared) is stored in the HL register. The command on the fifth line corresponds to step S3 in FIG. 52(a). The command "JP RAD_CHK" on the sixth line moves to the index "RAD_CHK:" indicating the start address of the RAD_CHK module. The command on the sixth line corresponds to step S4 in FIG. 52(a).

The index “RAD_CHK:” in the first line of FIG. 53(b) indicates the start address of the RAD_CHK module. The command "CP (HL), DE" on the second line compares the value stored in the address indicated by the HL register (return address to be compared) and the value stored in the DE register (current return address). compare.

FIG. 54 is an explanatory diagram for explaining the arrangement of variables in memory. In the general-purpose lottery offset selection table shown in FIG. 54(a), a plurality of combinations of return addresses and reference addresses to be compared are consecutively arranged every 4 bytes. Therefore, the address of the index "T_SEL_CLO:" is initially held in the HL register at the time when the command "CP (HL), DE" on the second line of FIG. 53(b) is executed. Here, when the command "CP (HL), DE" is executed, the value stored at the address ("T_SEL_CLO") indicated in the HL register, that is, "@ADT_SET_EPL" (the return address to be compared), and the value stored in the DE register (current return address). The command on the second line of FIG. 53(b) corresponds to step S5 of FIG. 52(b).

Returning to FIG. 53(b), the command "INC HL" on the third line adds 1 to the value of the HL register. Furthermore, the command "INC HL" on the fourth line further adds 1 to the value of the HL register. Thus, the HL register is incremented by two. As shown in FIG. 54(a), this results in changing the return address to be compared in the even numbered row (for example, the second row) to the reference address in the odd numbered row (for example, the third row). The commands on the third and fourth lines in FIG. 53(b) correspond to step S6 in FIG. 52(b).

If the zero flag is 1 (Z) by the command "JR Z, RAD_CHK01" on the 5th line of FIG. 53(b), it moves to the index "RAD_CHK01:" on the 9th line. For example, according to the example in FIG. 54, (“@ADT_SET_EPL” which is the value stored in the address (“T_SEL_CLO”) indicated in the HL register) = (the current return value which is the value of the DE register). , the zero flag becomes 1 from the first time, and the index moves to "RAD_CHK01:". The command on the fifth line of FIG. 53(b) corresponds to step S7 of FIG. 52(b).

If the execution result of the command "JR Z, COM_CHK01" on the 5th line of FIG. 53(b) is not zero flag = 1, and the command "JR Z, COM_CHK01" is not moved, then 6 of FIG. 53(b) The command "INC HL" on the line adds 1 to the value of the HL register. Furthermore, the command "INC HL" on the seventh line further adds 1 to the value of the HL register. Thus, the HL register is incremented by two. As shown in FIG. 54(a), this involves changing the reference address in the odd numbered row (e.g., the third row) to the return address to be compared in the even numbered row (e.g., the fourth row). The target is changed to the next combination of the return address and reference address to be compared. Note that, for example, 100 next combinations of return addresses and reference addresses to be compared are prepared. The command "JR RAD_CHK" on the 8th line moves to the index "RAD_CHK:" on the 1st line. The commands on the 6th to 8th lines correspond to step S8 in FIG. 52(b).

On the other hand, if the execution result of the command "JR Z, COM_CHK01" on the 5th line in FIG. 53(b) is zero flag = 1, the command "LDIN DE, (HL )" reads (loads) the 2-byte length value (reference address) stored at the address indicated by the HL register into the DE register, and adds 2 to the value of the HL register. Then, the reference address read out to the DE register by the command "LD HL, DE" on the 11th line is set in the HL register. In this way, the reference address ("T_SET_EPL" in the example of FIG. 54) can be set in the HL register. The commands on the 10th and 11th lines correspond to step S9 in FIG. 52(b).

By the command "SUB HL, @END_TBL_SET" on the 12th line of FIG. 53(b), a predetermined boundary address is subtracted from the address of the reference table set in the HL register. As mentioned above, here, if the result of subtracting the predetermined boundary address from the table address is positive or 0, that table address corresponds to general-purpose lottery processing, and the predetermined boundary address is subtracted from the table address. If the result of subtracting the boundary address is negative, this means that the table address corresponds to variable initialization processing. The command on the 12th line corresponds to step S10 in FIG. 52(b). The reference address read out to the DE register by the command "LD HL, DE" on the 13th line is set in the HL register again. In this way, the reference address ("T_SET_EPL" in the example of FIG. 54) can be restored to the HL register. The command on the 13th line corresponds to step S11 in FIG. 52(b). If the carry flag (c) is 1 by the command "JR C, TABLSET" on the 14th line of FIG. 53(b), that is, if the result of subtracting the predetermined boundary address from the table address is negative, Move to TABLSET. On the other hand, if the carry flag (c) is not 1, the process moves to the next process (index "COM_LOT:"). The command on the 14th line corresponds to step S12 in FIG. 52(b).

Here, as mentioned above, we will use a set of multiple combinations of return addresses and reference addresses to be compared, used for general-purpose lottery processing, and a set of return addresses and reference addresses to be compared, used for variable initialization processing. The two aggregates, the aggregate in which a plurality of combinations are arranged side by side, are separated, and one address is set to be larger than the other. Therefore, depending on whether the result of subtracting a predetermined boundary address from the address in the table is positive or negative, that is, whether the address has a smaller value than the boundary address, the general lottery process or the variable initialization process is determined. It is branching out.

The index “COM_LOT:” on the 15th line of FIG. 53(b) indicates the start address of the COM_LOT module. Then, specific processing regarding the general-purpose lottery is executed based on the value specified by the reference address (specific address), and the command "RET" on the 16th line terminates the COM_LOT module and calls the COM_PRE module. Return to The command on the 15th line corresponds to step S13 in FIG. 52(c).

The index “TABLSET:” in the first line of FIG. 53(c) indicates the start address of the TABLSET module. The command "PUSH BC" on the second line saves the value of the BC register to the stack area. Interrupts are prohibited by the command "DI" on the fifth line.

The 1-byte value stored at the address indicated by the HL register is read into the B register by the command "LD B, (HL)" in the fourth line of FIG. 53(c). At this time, a reference address (for example, "T_SET_EPL") is set in the HL register by the RAD_CHK module. Therefore, the 1-byte value "(T_SET_EPL_-T_SET_EPL)/2" in the second line of FIG. 54(b) is read into the B register as the data number (transfer repetition number). Note that "T_SET_EPL_" is the address next to the last address of the 1-byte data group that is the transfer source, and T_SET_EPL is the first address of the 1-byte data group that is the transfer source, so the value of T_SET_EPL_ - T_SET_EPL (indicating the number of data 1-byte value) is the total number of bytes of the 1-byte value, and by dividing that value by 2, which is the number of combinations of addresses and values, the number of data is derived. In the example of FIG. 54(b), the number of data is 9/2=4. The command on the fourth line corresponds to step S14 in FIG. 52(d).

The index “TABLSET01:” in the fifth line of FIG. 53(c) indicates the start address of the repetitive process. The command “INLD AC, (HL)” on the 6th line and the command “LDQ (C), A” on the 7th line specify the value stored at the address indicated by adding “1” to the HL register. The value stored in the address indicated by adding "2" to the HL register is stored in the address to be transferred, and "2" is added to the value of the HL register to set the next address to be transferred. The commands on the 6th and 7th lines correspond to step S15 in FIG. 52(d).

For example, if the HL register has the value of the address "T_SET_EPL", the lower 1 byte value of the 2-byte variable "_AT__NXT" in the third line of FIG. 54(b) is stored in the C register, and The value “@AT__MOD_EPS” in the third line is stored in the A register.

In addition, the command "LDQ (C), A" on the 7th line of FIG. , is a command to store the value of the A register.

For example, the value of the C register, that is, the value of the lower 1 byte of "_AT__NXT" is set as the lower 1 byte of the address, and the value of the A register, that is, the value of "@AT__MOD_EPS" is stored in that address.

Next, the value of the B register is decremented (subtracted by "1") by the command "DJNZ TABLSET01" on the 8th line of FIG. , if the decremented result is 0, the process moves to the command next to the command in question. Here, the number of data is "4", so if the process from "TABLSET01" is repeated four times, the value of the B register becomes 0. The command on the eighth line corresponds to step S16 in FIG. 52(d).

Interruption is permitted by the command "EI" on the 9th line of FIG. 53(c). The data saved in the stack area is returned to the BC register by the command "POP BC" on the 10th line. Then, the command "RET" on the 11th line returns to the routine one level higher. The command on the 11th line corresponds to step S17 in FIG. 52(d). In this way, variable initialization processing is executed based on the value specified by the reference address (specific address).

In this way, by integrating the general-purpose lottery process shown in FIG. 48 and the variable initialization process shown in FIG. 51, the capacity of the main ROM 200b can be further reduced as shown in FIG. Specifically, in the general-purpose lottery process of FIG. 48, as shown by the broken line, the second line command "CALLF COM_CHK" (2 bytes) in the RAD_CHK module of FIG. 48(b) and the COM_CHK module of FIG. 48(c) The command "RET" (1 byte) on the 12th line can be deleted, and the total number of bytes can be reduced by 3 bytes. Furthermore, in the variable initialization process in FIG. 51, the entire COM_PRE2 module in FIG. 51(a) can be deleted, as indicated by the broken line. Then, the command "POP DE" (1 byte) on the 3rd line, the command "PUSH DE" (1 byte) on the 4th line, the command "LD HL, T_SEL_CLO_2" (3 bytes) on the 5th line, and the 6th line The second command “JP RAD_CHK2” (3 bytes) can be deleted. Also, like the general-purpose lottery process, the command "CALLF COM_CHK" (2 bytes) on the second line in the RAD_CHK2 module in FIG. 51(b) can also be deleted. Therefore, the total number of bytes can be reduced by 10 bytes.

On the other hand, when general-purpose lottery processing and variable initialization processing are integrated, as shown by the broken line, the commands "SUB HL, @END_TBL_SET" (3 bytes), 13 on the 12th line in the RAD_CHK module in FIG. The command "LD HL, DE" (2 bytes) on the 14th line and the command "JRC, TABLSET" (2 bytes) on the 14th line are added, increasing the total number of bytes by 7 bytes. Therefore, by integrating the general-purpose lottery process shown in FIG. 48 and the variable initialization process shown in FIG. 51 as shown in FIG. 53, 13 bytes are reduced and 7 bytes are increased, resulting in a total reduction of 6 bytes. In the case of the main CPU 200a shown in FIGS. 43 to 46, the command size of the command "SUB HL, @END_TBL_SET" on the 12th line in the RAD_CHK module in FIG. 53(b) is 2 bytes, so the total reduction is 7 bytes. can. In this way, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

Although preferred embodiments of the present invention have been described above with reference to the accompanying drawings, it goes without saying that the present invention is not limited to these embodiments. It is clear that those skilled in the art can come up with various changes and modifications within the scope of the claims, and it is understood that these naturally fall within the technical scope of the present invention. be done.

For example, in the embodiment described above, the COM_PRE module and the RAD_CHK module were mentioned as the first module, the COM_LOT module was mentioned as the second module, and the TABLSET module was mentioned as the third module. However, this is not the only case; for example, the first module may be a single RAD_CHK module (excluding the COM_PRE module), or the second module may be used as a TABLSET module and the third module by reversing the magnitude relationship of the addresses with respect to the boundary address. It may also be a COM_LOT module. In addition, various combinations of modules are possible.

Further, in the embodiment described above, the specific address is used as a reference address, and if the reference address is equal to or greater than the boundary address, the transition is made to the COM_LOT module (second module), and if the reference address is less than the boundary address, the transition is made to the TABLSET module. (The third module) was explained using an example. However, this is not the only case; if a specific address is set as the "return address to be compared" and the return address to be compared is equal to or greater than the boundary address, the process moves to the COM_LOT module (second module), and the return address to be compared is is less than the boundary address, the process may proceed to the TABLSET module (third module). For example, in the example of FIG. 54(a), the command "DEFW @ADT_HED_FLZ" on the 6th line is set as the boundary address. At this time, if the return address to be compared is, for example, "@ADT_SET_EPL", the return address to be compared is less than the boundary address, so the process moves to the TABLSET module (third module), and the return address to be compared is, for example, " @ADT_HED_FLZ”, the return address to be compared is greater than or equal to the boundary address, so the process moves to the COM_LOT module (second module).

Furthermore, in the embodiment described above, the main control board 200 and the sub-control board 202 are arranged to share the functional parts for playing the game, but the functional parts of the main control board 200 are transferred to the sub-control board 202. The functional parts of the sub-control board 202 may be arranged on the main control board 200, or all the functional parts can be arranged on one control board.

Further, in the above-described embodiment, the game is played using medals as the gaming value, but the gaming value may be electrical information (so-called medalless). In this case, when a winning combination is won, the amount of value corresponding to the winning combination may be given to the player in the form of electrical information.

Further, each process performed by the main control board 200 and the sub-control board 202 described above does not necessarily need to be performed in chronological order according to the order described in the flowchart, and may include processing in parallel or by a subroutine.

100 Slot machine (gaming machine)
200 Main control board 200a Main CPU
200b main ROM
200c main RAM
202 Sub control board 202a Sub CPU
202b Sub ROM
202c sub RAM

Claims (1)

a winning type lottery means for determining one of the plurality of winning types by lottery;
Reel control means for controlling the rotation of a plurality of reels each having a plurality of types of symbols arranged on the basis of the operation of a start switch, and for controlling the rotation of each reel corresponding to the operated stop switch in accordance with the operation of a stop switch; ,
a non-internal gaming state; a gaming state control means for causing the non-internal gaming state to transition to one of a plurality of types of gaming states, including an internal medium gaming state that is entered by winning a winning type including a bonus combination in the non-internal gaming state;
Performance state control means for determining either an advantageous section, which is a game section in which auxiliary presentations to assist in winning a specific role can be performed, and a non-advantageous section, which is a game section other than the advantageous section. and,
Equipped with
The winning type lottery means, in the non-internal gaming state, selects a specific winning combination in which a first minor role whose payout is less than a specified number, a second minor role whose payout is less than a specified number, and a bonus role overlap. The type may be determined,
The specific winning type is such that the first operation mode of first stopping the first reel is set as the winning condition of the first small winning combination, and the second reel different from the first reel is A second operation mode of stopping is set as a winning condition for the second small role,
The winning type lottery means may determine a selected winning type in which a correct winning combination with a payout of a specified number or more and an incorrect winning combination with a payout of less than a specified number overlap,
In the selected winning type, the first operation mode is not set as a winning condition for the correct combination, but is set as a winning condition for the incorrect combination;
The incorrect winning combination includes the first small winning combination but does not include the second small winning combination,
The winning type lottery means may determine a special winning type that is a winning type that cannot be drawn to transfer to the advantageous area in the non-advantageous area and includes a replay combination,
A gaming machine in which the replay winning combination and the first small winning combination have the same symbols corresponding to the first reel .

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