JP7479913B2 - Gaming Machines - Google Patents

Description

The present invention relates to an amusement machine.

In general, in gaming machines (pachinko machines), a game ball is launched toward a game area in a game board by a player operating a handle, and a lottery for a special symbol is executed on the condition that the game ball that flows down the game area enters a start hole. Then, the special symbol is displayed variably on the special symbol display, and the special symbol determined by the lottery is displayed as a frozen special symbol, thereby notifying the player of the lottery result. At this time, when a specific special symbol indicating a jackpot is displayed as a frozen special symbol on the special symbol display, a big prize game that is more advantageous to the player than normal play begins. In this big prize game, the attacker device opens and closes a predetermined number of times, allowing the game ball to enter the big prize hole, and the player can receive many prize balls.

When a gaming machine is turned on, a wait time of, for example, two seconds is provided to wait for a stable supply of power (for example, Patent Document 1).

Japanese Patent No. 6210388

In recent years, the mechanisms of the presentation devices controlled by the sub-control board in gaming machines have become more complex, and it has been considered to lengthen the wait time on the main control board in order to wait for the presentation devices to be initialized.

However, simply lengthening the wait time posed the problem of increasing the possibility of cheating during the wait time.

In view of these problems, the present invention aims to provide a gaming machine that can improve security against fraudulent activities.

In order to solve the above problems, the gaming machine of the present invention is a gaming machine that includes a CPU, a ROM storing a program used by the CPU, and a RAM that holds variables updated by the program, on a specified board used to progress through the game, and the CPU reads out from the ROM the program that is executed when the power is turned on, executes loop processing using a plurality of commands based on the program, and executes a command that outputs an external signal during the loop processing.

If the CPU has output the external signal when the final loop process ends, the CPU may clear the external signal by a specified timer interrupt process.

The present invention makes it possible to improve security against fraudulent activities.

1 is an oblique view of a gaming machine showing the door in the open state in the simultaneous rotation reference example. FIG. 2 is a front view of a gaming machine relating to a simultaneous rotation reference example. A diagram explaining the second large prize slot in the simultaneous spinning reference example. A block diagram showing the internal configuration of a control means for controlling the progress of a game in the simultaneous rotation reference example. 13 is an address map of a memory area used by a main CPU according to a reference example of simultaneous rotation. This is a diagram explaining the random number judgment table for determining a jackpot at low probability in the simultaneous spin reference example. This is a diagram explaining the random number judgment table for determining a jackpot at high probability in the simultaneous spin reference example. A diagram explaining a winning pattern random number determination table and a small winning pattern random number determination table for a simultaneous spin reference example. A diagram explaining a reach group determination random number judgment table for the simultaneous rotation reference example. A figure explaining a reach mode determination random number judgment table for the simultaneous rotation reference example. A figure explaining a variation pattern random number determination table for a simultaneous rotation reference example. FIG. 13 is a diagram illustrating a variable time determination table according to a simultaneous rotation reference example. A diagram explaining the game state and variable time for the simultaneous spin reference example. This is the first diagram explaining the special electric role operation ram set table for the simultaneous rotation reference example. This is the second diagram explaining the special electric role operation ram set table for the simultaneous rotation reference example. A diagram explaining a game status setting table for a simultaneous rotation reference example. A diagram explaining a random number judgment table for determining a win in the simultaneous rotation reference example. 1A is a diagram explaining a normal pattern change time data table for a simultaneous rotation reference example, and FIG. 1B is a diagram explaining an opening/closing control pattern table for a simultaneous rotation reference example. A figure explaining the transition of game states in accordance with the original gameplay of the simultaneous spin reference example. A figure explaining the transition of game states when play is not performed properly in the simultaneous spin reference example. A figure explaining the gaming machine status flag for the simultaneous spin reference example. 11 is a first flowchart illustrating a CPU initialization process in a main control board according to a simultaneous rotation reference example. 13 is a second flowchart illustrating the CPU initialization process in the main control board according to the simultaneous rotation reference example. 13 is a flowchart illustrating a sub-command group set process in a main control board according to a simultaneous rotation reference example. 13 is a flowchart illustrating a power-off evacuation process in a main control board according to a simultaneous rotation reference example. 13 is a flowchart illustrating timer interrupt processing in a main control board in a simultaneous rotation reference example. 13 is a flowchart illustrating setting-related processing in a main control board according to a simultaneous rotation reference example. 13 is a flowchart illustrating a switch management process in a main control board according to a simultaneous rotation reference example. 13 is a flowchart illustrating a gate passing process in a main control board according to a simultaneous rotation reference example. 13 is a flowchart explaining the first starting port passing process in the main control board in the simultaneous rotation reference example. 13 is a flowchart explaining the second starting port passing process in the main control board in the simultaneous rotation reference example. A flowchart explaining the special pattern random number acquisition process in the main control board for the simultaneous rotation reference example. 13 is a flowchart illustrating the acquisition time performance determination process in the main control board for the simultaneous rotation reference example. A flowchart explaining the large prize opening passing processing in the main control board for the simultaneous rotation reference example. A figure explaining the special game management phase and the special electric device game management phase in the simultaneous spinning reference example. 13 is a flowchart explaining the special game management processing in the main control board for the simultaneous rotation reference example. A flowchart explaining the special pattern change waiting process in the main control board for the simultaneous rotation reference example. 13 is a flowchart explaining the special pattern winning determination process in the main control board for the simultaneous rotation reference example. 13 is a flowchart explaining the special pattern variable number determination process in the main control board for the simultaneous rotation reference example. 13 is a flowchart illustrating the number of times cutoff management processing in the main control board in the simultaneous rotation reference example. A flowchart explaining the processing during special pattern changes in the main control board for the simultaneous rotation reference example. 13 is a flowchart explaining the forced pattern stop processing in the main control board for the simultaneous rotation reference example. 13 is a flowchart explaining the special pattern stop pattern display processing in the main control board for the simultaneous rotation reference example. 13 is a flowchart explaining the special electric device play management processing in the main control board for the simultaneous rotation reference example. A flowchart explaining the processing before opening the large prize opening in the main control board for the simultaneous rotation reference example. A flowchart explaining the large prize opening/closing switching process in the main control board for the simultaneous rotation reference example. A flowchart explaining the large prize opening control processing in the main control board for the simultaneous rotation reference example. A flowchart explaining the large prize opening closure activation process in the main control board for the simultaneous rotation reference example. A flowchart explaining the large prize opening end wait processing in the main control board for the simultaneous rotation reference example. A diagram explaining the normal game management phase related to the simultaneous rotation reference example. 13 is a flowchart explaining the normal game management processing in the main control board for the simultaneous rotation reference example. A flowchart explaining the normal pattern change waiting process in the main control board for the simultaneous rotation reference example. A flowchart explaining the processing during normal pattern fluctuations on the main control board in the simultaneous rotation reference example. A flowchart explaining the normal pattern stop pattern display processing in the main control board for the simultaneous rotation reference example. This is a flowchart explaining the processing before opening of the winning opening of a normal electric device in the main control board for the simultaneous rotation reference example. This is a flowchart explaining the normal electric gimmick prize opening/closing switching process in the main control board for the simultaneous rotation reference example. This is a flowchart explaining the control processing for opening the winning port of a normal electric device in the main control board for the simultaneous rotation reference example. This is a flowchart explaining the normal electric device winning opening closure validity processing in the main control board for the simultaneous rotation reference example. This is a flowchart explaining the normal electric gimmick winning slot end wait processing in the main control board for the simultaneous rotation reference example. This is a diagram illustrating an example of a variable presentation of a no-reach variable pattern related to a reference presentation example. This is a diagram illustrating an example of a normal reach fluctuation pattern fluctuation presentation related to a presentation reference example. This is a diagram illustrating an example of a change in the development reach change pattern when a miss occurs in accordance with a reference example of the performance. This is a diagram illustrating an example of a change presentation of a development reach change pattern at the time of a jackpot, which is related to a reference presentation example. This is a diagram illustrating an example of a variable presentation when the reach development presentation relating to the presentation reference example is executed twice. 13 is a diagram illustrating an example of a pseudo-continuous reach fluctuation pattern fluctuation presentation relating to a presentation reference example. FIG. A diagram explaining a variable performance decision table related to a performance reference example. A figure explaining an example of a hold display presentation related to a reference presentation example. 1A is a diagram explaining a final hold display pattern determination table relating to a reference example of presentation, and FIG. 1B is a diagram explaining a previous hold display pattern determination table relating to a reference example of presentation. 13 is a flowchart explaining the sub-CPU initialization process in the sub-control board for the reference example performance. 13 is a flowchart explaining sub-timer interrupt processing in a sub-control board for a reference example of a performance. 13 is a flowchart explaining the pre-reading designation command reception processing in the sub-control board for the reference example performance. 13 is a flowchart explaining the variable command receiving processing in the sub-control board for the reference example performance. FIG. 1 is an external view for explaining a schematic mechanical configuration of a slot machine. 1 is an external view of the slot machine with the front door open, illustrating the general mechanical configuration of the slot machine. FIG. 1 is a diagram illustrating the arrangement of symbols on the reels and the winning lines. FIG. 2 is a block diagram showing a schematic electrical configuration of the slot machine. FIG. 13 is an explanatory diagram for explaining a winning combination. FIG. 13 is a diagram showing a winning type lottery table. FIG. 13 is a diagram showing a winning type lottery table. FIG. 11 is an explanatory diagram for explaining the transition of a game state. FIG. 11 is an explanatory diagram for explaining the transition of the presentation state. 11 is a flowchart illustrating a CPU initialization process in a main control board. 11 is a flowchart illustrating a cold start process in a main control board. 13 is a flowchart illustrating an error stop process in the main control board. 13 is a flowchart illustrating a setting value switching process in a main control board. 11 is a flowchart illustrating an initialization start process in the main control board. 13 is a flowchart illustrating a state restoration process in a main control board. 13 is a flowchart explaining game start processing on the main control board. 13 is a flowchart explaining the game medal insertion processing on the main control board. 13 is a flowchart illustrating an internal lottery process in the main control board. 13 is a flowchart illustrating a pattern code setting process in the main control board. 13 is a flowchart explaining the processing performed during reel rotation on the main control board. 13 is a flowchart explaining the reel stop processing in the main control board. 13 is a flowchart illustrating a display determination process in a main control board. 13 is a flowchart explaining the payout process in the main control board. 13 is a flowchart explaining game transition processing on the main control board. 11 is a flowchart illustrating a save process in the main control board when power is turned off. 11 is a flowchart illustrating a timer interrupt process in a main control board. FIG. 2 is a diagram for explaining electrical connections around a main CPU. FIG. 2 is a block diagram showing the internal configuration of a CPU core. FIG. 2 is a diagram illustrating a configuration of a register. FIG. 2 is an explanatory diagram showing a memory map. 11 is a flowchart showing an initialization start process. FIG. 11 is an explanatory diagram for explaining an example of commands for implementing a STARTUP module and an E_RMCLR module. 13 is a flowchart showing another example of the initialization start process. FIG. 13 is an explanatory diagram for explaining another example of the command for implementing the STARTUP module and the E_RMCLR module. 13 is a flowchart showing a setting value switching process. FIG. 11 is an explanatory diagram for explaining an example of commands for implementing a RANKSET module and an E_RMCLR module. 13 is a flowchart showing another example of the setting value switching process. FIG. 13 is an explanatory diagram for explaining another example of the command for realizing the RANKSET module and the E_RMCLR module. FIG. 11 is an explanatory diagram for explaining a test signal output process. FIG. 11 is an explanatory diagram for explaining a test signal output process. FIG. 11 is an explanatory diagram for explaining a test signal output process. FIG. 11 is an explanatory diagram for explaining a test signal output process. FIG. 11 is an explanatory diagram for explaining a test signal output process. FIG. 11 is an explanatory diagram for explaining a test signal output process. FIG. 11 is an explanatory diagram for explaining a test signal output process. FIG. 11 is an explanatory diagram for explaining a test signal output process. FIG. 11 is an explanatory diagram for explaining a test signal output process. FIG. 1 is a diagram illustrating a signal input to an input port. FIG. 11 is an explanatory diagram for explaining an edge check process. FIG. 11 is an explanatory diagram for explaining an edge clearing process. FIG. 2 is an explanatory diagram for explaining a RECOVER module. FIG. 11 is an explanatory diagram illustrating another example of the edge check process. FIG. 13 is an explanatory diagram for explaining another example of the EDGECHK module. FIG. 11 is an explanatory diagram for explaining another example of the EDGECLR module and the RECOVER module. 10 is a flowchart illustrating another example of the CPU initialization process. FIG. 11 is an explanatory diagram for explaining an INITIAL module. FIG. 1 is a diagram comparing input port 1 and output port 2.

The preferred embodiment of the present invention will be described in detail below with reference to the attached drawings. The dimensions, materials, and other specific values shown in the embodiment are merely examples to facilitate understanding of the invention, and do not limit the present invention unless otherwise specified. In this specification and drawings, elements having substantially the same functions and configurations are given the same reference numerals to avoid duplicated explanations, and elements not directly related to the present invention are not illustrated.

In this embodiment of the present invention, a pachinko machine and a slot machine are given as examples of gaming machines, in that order, and then the specific processing is described in detail.

<Pachinko machine>
In order to facilitate understanding of the embodiments of the present invention, first, as a simultaneous rotation reference example, the mechanical and electrical configurations of the so-called simultaneous rotation machine and the specific processing on each board are explained. Then, as a performance reference example, specific performances that can be executed by the simultaneous rotation machine and specific processing related to the performance are explained. After that, as an embodiment of the present invention, the configurations that are different from each reference example are specifically explained.

<Simultaneous rotation example>
1 is a perspective view of a gaming machine 100 according to a simultaneous rotation reference example, showing a state in which the door is open. As shown in the figure, the gaming machine 100 includes an outer frame 102 having an enclosed space formed by four sides assembled into a substantially rectangular shape, a middle frame 104 attached to the outer frame 102 by a hinge mechanism so as to be freely opened and closed, and a front frame 106 attached to the middle frame 104 by a hinge mechanism so as to be freely opened and closed.

The middle frame 104, like the outer frame 102, has four sides arranged in a roughly rectangular shape to form an enclosed space, and the game board 108 is held in this enclosed space. The front frame 106 also holds a glass or resin transparent plate 110. When the middle frame 104 and the front frame 106 are closed against the outer frame 102, the game board 108 and the transparent plate 110 face each other roughly parallel, maintaining a predetermined distance between them, and the game board 108 can be seen through the transparent plate 110 from the front side of the gaming machine 100.

Figure 2 is a front view of a gaming machine 100 relating to a simultaneous rotation reference example. As shown in this figure, an operating handle 112 that protrudes toward the front side of the gaming machine 100 is provided at the bottom of the front frame 106. This operating handle 112 is provided so that it can be rotated by the player, and when the player rotates the operating handle 112 to perform a firing operation, a gaming ball is fired by a firing mechanism (not shown) with a strength according to the rotation angle of the operating handle 112. The gaming ball fired in this way rises between rails 114a, 114b provided on the gaming board 108 and is guided to the playing area 116.

The play area 116 is a space formed between the play board 108 and the transparent plate 110, and is an area in which the play balls can flow down or roll. The play board 108 is provided with numerous nails and windmills (not shown), and the play balls guided to the play area 116 collide with the nails and windmills, causing them to flow down and roll in irregular directions.

The play area 116 has a first play area 116a and a second play area 116b, in which the degree of entry of the play balls differs according to the launch strength of the launch mechanism, allowing the player to hit different game balls. The first play area 116a is located on the left side of the play area 116 as seen by a player facing the gaming machine 100, and the second play area 116b is located on the right side of the play area 116 as seen by a player facing the gaming machine 100. Since the rails 114a and 114b are on the left side of the play area 116, game balls launched by the launch mechanism with a launch strength less than a predetermined strength will enter the first play area 116a, and game balls launched with a launch strength equal to or greater than the predetermined strength will enter the second play area 116b.

The game area 116 is also provided with a general prize entry port 118 through which game balls can enter, a first fixed start port 120A, a first variable start port 120B, a second start port 122, and a general action port 125. When a game ball enters the general prize entry port 118, the first fixed start port 120A, the first variable start port 120B, the second start port 122, or the general action port 125, a predetermined prize ball is paid out to the player. In the following, the first fixed start port 120A and the first variable start port 120B are collectively referred to as the first start port 120.

As will be described in more detail later, a first starting area is provided within the first starting hole 120, and a second starting area is provided within the second starting hole 122. When a game ball enters the first starting hole 120 or the second starting hole 122 and enters the first starting area or the second starting area, a lottery is held to determine one of a number of special patterns that have been set up in advance. Each special pattern is associated with the possibility of executing a big prize game or a small prize game that is advantageous to the player. Therefore, when a game ball enters the first starting hole 120 or the second starting hole 122, the player not only acquires a predetermined prize ball, but also acquires the opportunity to acquire the right to receive various game benefits.

The first fixed starting port 120A, the second starting port 122 and the normal operating port 125 are configured as fixed starting ports that are always open to allow game balls to enter. On the other hand, the first variable starting port 120B is provided with a movable piece 120b that can be opened and closed, and is configured as a variable starting port in which the ease with which game balls can enter the first variable starting port 120B changes depending on the state of this movable piece 120b. Specifically, the movable piece 120b is normally maintained in a closed state, and during this time it is difficult or impossible for game balls to enter the first variable starting port 120B.

In response to this, when a game ball passes through the gate 124 provided in the game area 116 (second game area 116b) or enters the normal symbol operation port 125, a lottery for a normal symbol, which will be described later, is held, and if a winning symbol is selected in this lottery, the movable piece 120b is controlled to an open state for a predetermined time. When the movable piece 120b is in an open state, it becomes possible for the game ball to enter the first variable start port 120B. In this way, the movable piece 120b functions as a movable member (start variable winning device) that transitions between an open state that allows the game ball to enter the first variable start port 120B, and a closed state that makes it more difficult or impossible for the game ball to enter the first variable start port 120B than in the open state.

The first fixed starting port 120A is located at a position where only game balls flowing down the first game area 116a can enter, and the first variable starting port 120B and the second starting port 122 are located at a position where only game balls flowing down the second game area 116b can enter. The first fixed starting port 120A may be used to allow game balls flowing down the second game area 116b to enter, but in this case, it is desirable to place it at a position where game balls flowing down the first game area 116a can enter more easily than game balls flowing down the second game area 116b.

Similarly, the first variable starting port 120B and the second starting port 122 may be entered by game balls flowing down the first game area 116a, but in this case, it is desirable to arrange them in a position where game balls flowing down the second game area 116b can enter more easily than game balls flowing down the first game area 116a. In any case, it is desirable that the first fixed starting port 120A is arranged in a position where at least game balls flowing down the first game area 116a can enter, and the first variable starting port 120B and the second starting port 122 are arranged in a position where at least game balls flowing down the second game area 116b can enter.

Furthermore, the second game area 116b is provided with a first large prize opening 126 and a second large prize opening 128. The first large prize opening 126 and the second large prize opening 128 are positioned so that only game balls flowing down the second game area 116b can enter the opening. However, the first large prize opening 126 and the second large prize opening 128 may be positioned so that any game balls flowing down the first game area 116a and the second game area 116b can enter the opening.

The first large prize opening 126 is provided with an opening/closing door 126b that can be opened and closed. Normally, the opening/closing door 126b closes the first large prize opening 126, making it impossible for game balls to enter the first large prize opening 126. Specifically, when the opening/closing door 126b is closed, it is flush with the surface of the game board 108, and game balls flow down in front of the first large prize opening 126. In contrast, when the aforementioned big prize game is played, the opening/closing door 126b opens and functions as a tray that guides game balls to the first large prize opening 126, making it possible for game balls to enter the first large prize opening 126. Then, when a game ball enters the first large prize opening 126, a predetermined number of prize balls are paid out to the player.

The second large prize opening 128 is provided below the first large prize opening 126 in the second game area 116b. The second large prize opening 128 is equipped with a movable piece 128b, which is normally maintained in a closed state. In contrast, when a small prize game, which will be described later, is played, the movable piece 128b is controlled to an open state, allowing a game ball to enter the second large prize opening 128. In the following, the first large prize opening 126 and the second large prize opening 128 are collectively referred to simply as the large prize openings.

Figure 3 is a diagram illustrating the second large prize opening 128 in the simultaneous spin reference example. A structure 129 protruding from the front side of the game board 108 is provided in the second game area 116b. This structure 129 is surrounded on all four sides in the left-right and front-back directions of the gaming machine 100, as well as on the bottom side, and has an opening formed at the top. The opening formed at the top of this structure 129 becomes the second large prize opening 128. A movable piece 128b is provided at the top of the structure 129, and normally, as shown in Figure 3(a), the movable piece 128b is maintained in a closed state that closes the second large prize opening 128.

The movable piece 128b protrudes into the game area 116 where the game balls roll and flow down, facing above the game machine 100. Therefore, when the movable piece 128b is maintained in a closed state, the game balls flowing down the game area 116 (second game area 116b) fall onto the movable piece 128b. Here, the structure 129 has a base that is approximately parallel to the horizontal direction, and the right side of the game machine 100 is slightly longer in the height direction than the left side. Therefore, the second large winning opening 128 is slightly lower on the left side of the game machine 100 than the right side, and the movable piece 128b maintained in a closed state is inclined so that the left side of the game machine 100 is slightly lower than the right side. Therefore, when the movable piece 128b is in the closed state, the game ball that falls onto the movable piece 128b will roll slowly from right to left on the movable piece 128b, as shown by the arrow in Figure 3 (a).

When a small win game, which will be described later, is executed, the movable piece 128b transitions to an open state that opens the second large winning opening 128. Here, the movable piece 128b transitions from a closed state to an open state by sliding toward the rear side of the game board 108, as shown in FIG. 3(b). As a result, when transitioning from the closed state to the open state, the game ball rolling on the movable piece 128b falls under its own weight into the second large winning opening 128.

In this way, in the simultaneous rotation reference example, the movable piece 128b is slightly tilted to ensure a long time for the game ball to roll on the movable piece 128b. Then, the movable piece 128b transitions from a closed state to an open state, leading the game ball rolling on the movable piece 128b into the second large winning opening 128. With the above configuration, even if the time for which the movable piece 128b is kept in the open state is set to be short, a predetermined number of game balls can be led into the second large winning opening 128. In other words, the time for which the movable piece 128b is kept in the open state, which is necessary to allow a predetermined number of game balls to enter the second large winning opening 128, can be shortened. In addition, a hole that communicates with the back side of the game board 108 is formed on the back side of the structure 129, and the game balls that enter the second large winning opening 128 are discharged to the back side of the game board 108. When a game ball enters the second large prize opening 128, a certain number of prize balls are paid out to the player.

Here, the configuration of the second large winning opening 128 has been described, but the first variable starting opening 120B has the same configuration as the second large winning opening 128. That is, the movable piece 120b of the first variable starting opening 120B protrudes from the front side of the game board 108 in the closed state, and the game ball rolls on the movable piece 120b. And, when the movable piece 120b is in the open state, the movable piece 120b slides to the rear side of the game board 108, and the game ball can enter the first variable starting opening 120B. However, as shown in FIG. 2, the right side of the movable piece 128b is higher than the left side when viewed from the front of the gaming machine 100, whereas the left side of the movable piece 120b is higher than the right side when viewed from the front of the gaming machine 100.

Now, the board configuration of the second game area 116b will be described in detail. In the simultaneous spin reference example, the second start hole 122 and the gate 124 are arranged in parallel at the top of the second game area 116b. All game balls guided to the second game area 116b either enter the second start hole 122 or pass through the gate 124 and flow downward. In the simultaneous spin reference example, one game ball is paid out as a prize ball for each game ball that enters the second start hole 122.

When a game ball enters the second starting port 122, one game ball is paid out as a prize ball, and a lottery is held to determine whether a big prize game or a small prize game will be played. In addition, when the game ball passes through the gate 124, a lottery is held to determine whether the first variable starting port 120B (movable piece 120b) will be opened.

Directly below the second starting hole 122 and the gate 124 is a first large prize opening 126. When the first large prize opening 126 is open, it is positioned so that all game balls that pass through the gate 124 and flow downward enter the first large prize opening 126. In the simultaneous spin reference example, the first large prize opening 126 is only opened during the big prize game. In other words, the first large prize opening 126 can be said to be a large prize opening exclusively for the big prize game. When a game ball enters the first large prize opening 126 during the big prize game, a predetermined number of game balls (2 or more in number, 15 in this case) are paid out as prize balls for each game ball that enters.

A first variable start opening 120B is provided below the first large prize opening 126. In addition, an outlet 131 is provided between the first large prize opening 126 and the first variable start opening 120B. The outlet 131 is the entrance to a passage for discharging game balls from the game area 116, and even if a game ball enters the outlet 131, no prize balls will be paid out.

In the second game area 116b, nails are arranged so that most (e.g., 90% or more) of the game balls that flow down below the first large winning opening 126 fall onto the movable piece 120b. In addition, these nails guide a portion (e.g., 1% to 10%) of the game balls that flow down below the first large winning opening 126 to the outlet 131.

When the first variable start opening 120B is in a closed state, the game ball rolls on the movable piece 120b. If the movable piece 120b opens while the game ball is rolling on the movable piece 120b, all the game balls on the movable piece 120b are guided into the first variable start opening 120B. When a game ball enters the first variable start opening 120B, one game ball is paid out as a prize ball for each game ball that enters, and a lottery is held to determine whether or not a big prize game or a small prize game will be played.

Gaming balls that do not enter the first variable start opening 120B fall from above the movable piece 120b to the right side when viewed from the front of the gaming machine 100. Below the first variable start opening 120B, the second large prize opening 128 is provided, and most of the gaming balls that fall from above the movable piece 120b roll on the movable piece 128b of the second large prize opening 128. Due to the inclination of the movable piece 128b, the gaming balls on the movable piece 128b slowly roll from the right side to the left side when viewed from the front of the gaming machine 100.

In the simultaneous spin reference example, which will be described in more detail later, the second large prize opening 128 is only opened during small prize play. In other words, the second large prize opening 128 can be said to be a large prize opening exclusively for small prize play. When the movable piece 128b opens while a game ball is rolling on it, all game balls on the movable piece 128b are guided into the second large prize opening 128. When a game ball enters the second large prize opening 128 during a small prize play, a predetermined number of game balls (2 or more in number, 15 in this case) are paid out as prize balls for each game ball that enters.

The normal ball operation port 125 is provided to the lower left of the second large winning port 128. Here, nails are arranged in the second game area 116b so that almost all game balls that fall downward from above the second large winning port 128 enter the normal ball operation port 125. In the simultaneous spin reference example, the normal ball operation port 125 constitutes a "specific winning port" from which one game ball is paid out as a prize ball for each game ball that enters. In addition, when a game ball enters the normal ball operation port 125, a lottery is held to determine whether or not the first variable start port 120B (movable piece 120b) is opened, just as when a game ball passes through the gate 124.

At the bottom of the game area 116, there is a discharge port 130 that discharges game balls that do not enter the general winning hole 118, the first starting hole 120, the second starting hole 122, the general operation hole 125, or the big winning hole from the game area 116 to the back side of the game board 108.

The gaming machine 100 is equipped with a performance display device 200 consisting of a liquid crystal display device, a performance prop device 202 consisting of a movable device, a performance lighting device 204 consisting of lamps that can be controlled to various lighting modes and emission colors, a sound output device 206 consisting of a speaker, and a performance operation device 208 that accepts operations by the player, as performance devices that perform performances while the game is in progress.

The effect display device 200 is equipped with a main effect display section 200a consisting of an image display section that displays images, and this main effect display section 200a is arranged in the approximate center of the game board 108 so that it can be seen from the front side of the gaming machine 100. As shown in the figure, this main effect display section 200a executes various effects, such as the display of three effect patterns 210a, 210b, and 210c in a variable manner.

The performance device 202 is located in front of the main performance display unit 200a, and is usually separated into multiple components and stored at the origin position on the back side of the game board 108 so that it cannot be seen by the player. Then, when the actuator is driven to move each component to a movable position in front of the main performance display unit 200a during the changing display of the performance patterns 210a, 210b, 210c, the components combine in front of the main performance display unit 200a, giving the player a sense of anticipation of a big win.

The lighting device 204 is provided on the prop device 202, the game board 108, etc., and is controlled to light up in various ways in accordance with the images displayed on the main display unit 200a.

The audio output device 206 is provided at the top of the front frame 106 or at the bottom of the outer frame 102, and outputs various sounds toward the front of the gaming machine 100 in accordance with the images displayed on the main performance display section 200a.

The effect operation device 208 is composed of buttons that are pressed by the player, and is located in approximately the center of the gaming machine 100 in the width direction, and below the transparent plate 110. This effect operation device 208 is activated in accordance with the images displayed on the main effect display section 200a, and when a player's operation is received within the effective operation time, various effects are executed according to the operation.

The reference symbol 132 in the figure indicates an upper tray to which prize balls paid out from the gaming machine 100 and gaming balls loaned from the gaming ball loaning device are guided. When the upper tray 132 is full of gaming balls, the gaming balls are guided to the lower tray 134. A ball ejection hole (not shown) is formed in the bottom surface of the lower tray 134 to eject gaming balls from the lower tray 134. This ball ejection hole is normally closed by an opening/closing plate (not shown), but by pressing down on the ball ejection knob 134a, the opening/closing plate slides together with the ball ejection knob 134a, making it possible to eject gaming balls from the ball ejection hole to below the lower tray 134.

The game board 108 is provided with a first special symbol display 160, a second special symbol display 162, a first special symbol reserved display 164, a second special symbol reserved display 166, a normal symbol display 168, a normal symbol reserved display 170, and a right hit notification display 172, located outside the game area 116 and in a position visible to the player. Each of these displays 160-172 is a device for displaying various game-related situations, and will be described in detail below.

(Internal configuration of control means)
FIG. 4 is a block diagram showing the internal configuration of a control means for controlling the progress of a game in the simultaneous spin reference example.

The main control board 300 controls the basic operations of the game. This main control board 300 is equipped with a main CPU 300a, a main ROM 300b, and a main RAM 300c. The main CPU 300a reads out the programs stored in the main ROM 300b and performs arithmetic processing based on input signals from each detection switch and timer, and also directly controls each device and display, or sends commands to other boards depending on the results of the arithmetic processing. The main RAM 300c functions as a work area for data during arithmetic processing by the main CPU 300a.

The main control board 300 includes a general winning hole detection switch 118s for detecting when a game ball has entered the general winning hole 118, a first fixed starting hole detection switch 120As for detecting when a game ball has entered the first fixed starting hole 120A, a first variable starting hole detection switch 120Bs for detecting when a game ball has entered the first variable starting hole 120B, a second starting hole detection switch 122s for detecting when a game ball has entered the second starting hole 122, and a second starting hole detection switch 122s for detecting when a game ball has passed through the gate 124. A gate detection switch 124s that detects when a ball has passed the gate, a normal operation port detection switch 125s that detects when a game ball has entered the normal operation port 125, a first large prize opening detection switch 126s that detects when a game ball has entered the first large prize opening 126, and a second large prize opening detection switch 128s that detects when a game ball has entered the second large prize opening 128 are connected, and detection signals are input from each of these detection switches to the main control board 300.

The main control board 300 is also connected to a normal electric device solenoid 120c that operates the movable piece 120b of the first variable start opening 120B, a first large prize opening solenoid 126c that operates the opening and closing door 126b that opens and closes the first large prize opening 126, and a second large prize opening solenoid 128c that operates the movable piece 128b that opens and closes the second large prize opening 128. The main control board 300 controls the opening and closing of the first variable start opening 120B, the first large prize opening 126, and the second large prize opening 128.

Furthermore, the first special pattern display 160, the second special pattern display 162, the first special pattern reserved display 164, the second special pattern reserved display 166, the normal pattern display 168, the normal pattern reserved display 170, and the right hit notification display 172 are connected to the main control board 300, and the display of each of these displays is controlled by the main control board 300.

Furthermore, a setting change switch 180s is provided on the back of the game board 108. The setting change switch 180s is configured to be accessible with a dedicated key. When the setting change switch 180s is turned on, the setting value can be changed and confirmed. As will be described in detail later, in the gaming machine 100 of the simultaneous rotation reference example, one of six setting values with different degrees of advantage is stored as a registered setting value in the setting value buffer, and the game progresses according to the stored registered setting value. Note that, although it is assumed here that there are six setting values, there may be only two setting values, a high setting and a low setting, or there may be multiple other settings. Furthermore, a setting value is not essential, and the degree of advantage does not have to be changed.

A RAM clear button is provided on the back of the game board 108 so that it can be pressed, and pressing this RAM clear button is detected by the RAM clear switch 182s. The RAM clear switch 182s is connected to the main control board 300, and a RAM clear operation signal is input from the RAM clear switch 182s to the main control board 300. If a RAM clear operation signal is input from the RAM clear switch 182s when the power is turned on, the main CPU 300a clears the main RAM 300c.

In addition, a performance display monitor 184 is provided on the back of the game board 108. The main control board 300 displays the registered setting values and base ratios on the performance display monitor 184.

The gaming machine 100 of the simultaneous spin reference example is broadly divided into special games that are started mainly by a game ball entering the first start port 120 or the second start port 122, and regular games that are started by a game ball passing through the gate 124 or entering the regular operation port 125. The main ROM 300b of the main control board 300 stores various programs for progressing the special games and regular games, as well as data and tables required for various games.

The main control board 300 is also connected to a payout control board 310 and a sub-control board 330. The payout control board 310 controls the launching of game balls and the payout of prize balls. This payout control board 310 also has a CPU, ROM, and RAM, and is connected to the main control board 300 so that it can communicate in both directions. A game information output terminal board 312 is connected to this payout control board 310, and various information on the progress of the game output from the main control board 300 is output to the hall computer of the gaming facility via the payout control board 310 and the game information output terminal board 312.

The payout control board 310 is also connected to a payout motor 314 for paying out the game balls stored in the storage section to the player as prize balls. The payout control board 310 controls the payout motor 314 based on a payout number designation command sent from the main control board 300 to control it so that a specified number of prize balls are paid out to the player. At this time, the number of paid out game balls is detected by a payout ball count switch 316s, and it is possible to know whether the prize balls to be paid out have been paid out to the player.

In addition, a tray full detection switch 318s that detects the full state of the lower tray 134 is connected to the payout control board 310. This tray full detection switch 318s is provided in a passage that guides the game balls paid out as prize balls to the lower tray 134, and a game ball detection signal is input to the payout control board 310.

When the lower tray 134 is filled to capacity with more than a predetermined amount of game balls, game balls become trapped in the passageway leading to the lower tray 134, and game ball detection signals are continuously input from the full tray detection switch 318s to the payout control board 310. If the game ball detection signals are continuously input for a predetermined period of time, the payout control board 310 determines that the lower tray 134 is full, and sends a full tray command to the main control board 300. On the other hand, if the continuous input of the game ball detection signals stops after sending the full tray command, it determines that the full tray state has been released, and sends a full tray release command to the main control board 300.

The payout control board 310 is also provided with a launch control circuit 320 that controls the launch of game balls. The payout control board 310 is connected to a touch sensor 112s that is provided on the operating handle 112 and detects when the player touches the operating handle 112, and an operation volume 112a that detects the operating angle of the operating handle 112. When signals are input from the touch sensor 112s and the operation volume 112a, the launch control circuit 320 controls the energization of a launch solenoid 112c provided on the game ball launching device to launch the game balls.

The sub-control board 330 mainly controls each presentation during play, standby, etc. This sub-control board 330 is equipped with a sub-CPU 330a, a sub-ROM 330b, and a sub-RAM 330c, and is connected to the main control board 300 so that it can communicate in one direction from the main control board 300 to the sub-control board 330. The sub-CPU 330a reads out the programs stored in the sub-ROM 330b and performs calculation processing based on commands sent from the main control board 300 and input signals from a timer, and also controls the execution of the presentation. At this time, the sub-RAM 330c functions as a work area for data during calculation processing by the sub-CPU 330a.

Specifically, in the sub-control board 330, the sub-CPU 330a, sub-ROM 330b, and sub-RAM 330c work together to function as a sub-main, image control unit, prop control unit, lighting control unit, and sound control unit. The sub-main determines the content of the performance to be executed in response to various input commands, and manages and coordinates the execution of the performance. The image control unit performs image display control to display images on the main performance display unit 200a. The sub-ROM 330b stores a large amount of image data such as designs, backgrounds, and subtitles to be displayed on the main performance display unit 200a, and the image control unit reads the image data from the sub-ROM 330b to a VRAM (not shown) to control the image display on the main performance display unit 200a.

The prop control unit drives actuators in accordance with the performance management by the sub-main, and controls the movement of the prop device 202. The lighting control unit controls the lighting of the performance lighting device 204. The audio control unit controls the audio output to output audio from the audio output device 206. Sub-ROM 330b stores a large amount of audio data, such as audio and music, that is output from the audio output device 206, and the audio control unit reads out the audio data from sub-ROM 330b and controls the audio output of the audio output device 206.

Furthermore, the sub-control board 330 executes a predetermined performance when an operation detection signal is input from the performance operation device detection switch 208s, which detects that the performance operation device 208 has been pressed or rotated.

A power supply board (not shown) is connected to each board, and power is supplied to each board from a commercial power source via the power supply board. The power supply board is also provided with a backup power supply consisting of a capacitor.

Figure 5 is an address map of the memory area used by the main CPU 300a in the simultaneous rotation reference example. Note that in Figure 5, addresses are shown in hexadecimal, with "H" indicating hexadecimal. As shown in Figure 5, the memory area used by the main CPU 300a includes the memory area (0000H to 2FFFH) allocated to the main ROM 300b and the memory area (F000H to F3FFH) allocated to the main RAM 300c.

The memory area of the main ROM 300b is divided into a used area (0000H to 1BF3H) that stores programs and data for controlling the progress of the game, and a non-used area (2000H to 2BFFH) that stores programs and data for executing processes for performing tests stipulated by gaming machine regulations and processes for displaying the performance display monitor 184 (including processes for calculating the base ratio to be displayed on the performance display monitor 184).

The used area of the main ROM 300b includes a program area (0000H-0A89H) in which programs for controlling the progress of the game are stored, an unused area (0A8AH-11FFH), and a data area (1200H-1BF3H) in which data other than programs are stored. Note that the used area does not necessarily have to include the unused area (0A8AH-0FFFH).

The unused area of the main ROM 300b includes a program area (2000H to 27FFH) that stores programs for executing processes for performing tests stipulated by gaming machine regulations and processes for displaying the performance display monitor 184, and a data area (2800H to 2BFFH) that stores data other than these programs.

In addition to the used area and unused area, the memory area of main ROM 300b also includes an unused area (1A7BH-1DFFH), a ROM comment area (1E00H-1EFFH) in which arbitrary data such as the program title and version is stored, an unused area (1F00H-1FFFH), an unused area (2C00H-2FBFH), and a program management area (2FC0H-2FFFH) in which information necessary for main CPU 300a to execute a program is stored.

The memory area of the main RAM 300c is divided into a used area (F000H to F1FFH) that is temporarily used when a program for controlling the progress of the game is being executed, and a non-used area (F210H to F228H) that is an area other than the used area and is temporarily used when a program for processing tests stipulated by the gaming machine regulations or processing for displaying the performance display monitor 184 is being executed.

The used area of the main RAM 300c includes a work area (F000H-F12AH) that is temporarily used when a program for controlling the progress of the game is being executed, an unused area (F12BH-F1D7H), and a stack area (F1D8H-F1FFH) where data is temporarily saved while a program for controlling the progress of the game is being executed. Note that the used area does not have to include the unused area (F12BH-F1D7H).

The unused area of the main RAM 300c includes a work area (F210H to F21FH) that is temporarily used when programs are being executed for processing tests stipulated by gaming machine regulations and processing for displaying the performance display monitor 184, and a stack area (F220H to F228H) that temporarily stores data when these programs are being executed.

In addition to the used area and unused area, the memory area of main RAM 300c also includes an unused area (F200H to F20FH) and an unused area (F229H to F3FFH).

In this way, main ROM 300b and main RAM 300c are provided with separate areas: a used area used to control the progress of the game, and a non-used area used to execute processes for performing tests stipulated by gaming machine regulations and processes for controlling the display of the performance display monitor 184.

The main RAM 300c has a 16-byte unused area (F200H-F20FH) between the used area and the unused area. This unused area (F200H-F20FH) is set as a boundary area that separates the used area and the unused area, making the boundary between the used area and the unused area clear, preventing the unused area from being used when a program for controlling the progress of the game is being executed, and preventing the used area from being used when a program for processing tests stipulated by the gaming machine regulations or processing for controlling the display of the performance display monitor 184 is being executed.

The unused area between the used area and the unused area only needs to be at least 1 byte, and from the viewpoint of preventing fraud, it is preferable that it be 4 bytes or more, and more preferably set to 16 bytes or more. Furthermore, writing and reading of data into the unused area is prohibited, but from the viewpoint of preventing fraud, it may be cleared at a specified time.

In addition, the memory space from FE00h to FEFFh is assigned to an input/output unit. This input/output unit will be described in detail later.

Next, we will explain how to play the simultaneous spin reference example gaming machine 100, along with the various tables stored in the main ROM 300b.

As mentioned above, the gaming machine 100 of the simultaneous spin reference example has two types of games, special game and normal game, progressing in parallel. The special game progresses in either a low probability game state or a high probability game state, while the normal game progresses in either a non-time-saving game state, a medium time-saving game state, or a time-saving game state.

Details of each game state will be described later, but the low probability game state is a game state in which the probability of acquiring the right to play the big prize game in which the big prize opening is opened is set low, and the high probability game state is a game state in which the probability of acquiring the right to play the big prize game is set high. In addition, the non-time-saving game state is a game state in which the movable piece 120b is less likely to be in the open state and the game ball is less likely to enter the first variable start opening 120B, and the intermediate time-saving game state is a game state in which the movable piece 120b is more likely to be in the open state than the non-time-saving game state and the game ball is more likely to enter the first variable start opening 120B. In addition, the time-saving game state is a game state in which the movable piece 120b is even more likely to be in the open state than the intermediate time-saving game state and the game ball is most likely to enter the first variable start opening 120B. In addition, in the time-saving game mode, if game balls continue to be shot toward the second game area 116b during play, the game balls are set to decrease slightly or not at all.

As described above, since the special game and the normal game proceed simultaneously in parallel, in the simultaneous spin reference example, the game state is a combination of a low probability game state or a high probability game state with either a non-time-saving game state, a medium time-saving game state, or a time-saving game state. In the following, for ease of understanding, the game states related to the special game, i.e., the low probability game state and the high probability game state, may be referred to as special game states, and the game states related to the normal game, i.e., the non-time-saving game state, the medium time-saving game state, and the time-saving game state, may be referred to as normal game states. The initial state of the gaming machine 100 is set to the low probability game state and the non-time-saving game state.

When a player operates the operating handle 112 to launch a game ball into the game area 116, and the game ball flowing down the game area 116 enters the first start port 120 or the second start port 122, a lottery (hereinafter referred to as the "big prize lottery") is held to determine whether or not the player will be awarded a game profit. In this big prize lottery, if a big win is won, a big prize opening is opened and a big prize game is executed in which the game ball can enter the big prize opening, and the game state after the big prize game ends is set to one of the game states described above. The big prize lottery method is explained below.

As will be described in more detail later, when a game ball enters the first start hole 120 or the second start hole 122, various random number values related to the big role lottery (jackpot determining random number, winning symbol random number, reach group determining random number, reach mode determining random number, variable pattern random number) are obtained, and each of these random number values is stored in the special symbol reserve memory area of the main RAM 300c. In the following, the various random numbers stored in the special symbol reserve memory area when a game ball enters the first start hole 120 are collectively referred to as special 1 reserve, and the various random numbers stored in the special symbol reserve memory area when a game ball enters the second start hole 122 are collectively referred to as special 2 reserve.

The special chart reservation memory area of the main RAM 300c includes a first special chart reservation memory area and a second special chart reservation memory area. The first special chart reservation memory area and the second special chart reservation memory area each have four memory sections (first to fourth memory sections). When a game ball enters the first starting hole 120, the special 1 reservation is stored in order starting from the first memory section of the first special chart reservation memory area, and when a game ball enters the second starting hole 122, the special 2 reservation is stored in order starting from the first memory section of the second special chart reservation memory area.

For example, when a game ball enters the first starting hole 120, if no reserve is stored in any of the first to fourth memory sections of the first special chart reserve memory area, a special 1 reserve is stored in the first memory section. Also, for example, if a game ball enters the first starting hole 120 while a special 1 reserve is stored in the first to third memory sections, the special 1 reserve is stored in the fourth memory section. Also, when a game ball enters the second starting hole 122, similar to the above, a special 2 reserve is stored in the memory section with the smallest number (ordinal number) among the first to fourth memory sections of the second special chart reserve memory area where a special 2 reserve is not stored.

However, the number of special 1 reservations (X1) and the number of special 2 reservations (X2) that can be stored in the first special chart reservation memory area and the second special chart reservation memory area are each set to four. Therefore, for example, if four special 1 reservations are already stored in the first special chart reservation memory area when a game ball enters the first starting hole 120, no new special 1 reservations will be stored by the game ball entering the first starting hole 120. Similarly, if four special 2 reservations are already stored in the second special chart reservation memory area when a game ball enters the second starting hole 122, no new special 2 reservations will be stored by the game ball entering the second starting hole 122.

Figure 6 is a diagram explaining the low probability jackpot determination random number judgment table for the simultaneous spin reference example. When a game ball enters the first start hole 120 or the second start hole 122, one jackpot determination random number is obtained from the range of 0 to 65535. Then, when the big win lottery starts, that is, according to the game state when the jackpot determination is made, a jackpot determination random number judgment table is selected, and the big win lottery is performed using the selected jackpot determination random number judgment table and the obtained jackpot determination random number.

When starting the big prize lottery for special 1 reserve and special 2 reserve in a low probability game state, the low probability jackpot determination random number judgment table is referenced. Here, in the simultaneous spin reference example, six setting values with different degrees of advantage are provided, and a low probability jackpot determination random number judgment table is provided for each setting value. During play, the setting value is set to one of the six levels, and the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table corresponding to the currently set setting value (registered setting value stored in the setting value buffer).

When the game is in a low probability game state and the setting value is set to 1 (registered setting value = 1), the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table a shown in FIG. 6 (a). According to this low probability jackpot determination random number judgment table a, if the jackpot determination random number is between 10001 and 10218, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/300.6, and the probability of a small jackpot is approximately 1/3.45.

When the game is in a low probability game state and the setting value is set to 2 (registered setting value = 2), the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table b shown in Figure 6 (b). According to this low probability jackpot determination random number judgment table b, if the jackpot determination random number is between 10001 and 10225, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/291.2, and the probability of a small jackpot is approximately 1/3.45.

When the game is in a low probability game state and the setting value is set to 3 (registered setting value = 3), the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table c shown in Figure 6 (c). According to this low probability jackpot determination random number judgment table c, if the jackpot determination random number is between 10001 and 10232, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/282.4, and the probability of a small jackpot is approximately 1/3.45.

When the game is in a low probability game state and the setting value is set to 4 (registered setting value = 4), the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table d shown in Figure 6 (d). According to this low probability jackpot determination random number judgment table d, if the jackpot determination random number is between 10001 and 10239, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/274.2, and the probability of a small jackpot is approximately 1/3.45.

When the game is in a low probability game state and the setting value is set to 5 (registered setting value = 5), the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table e shown in Figure 6 (e). According to this low probability jackpot determination random number judgment table e, if the jackpot determination random number is between 10001 and 10246, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/266.4, and the probability of a small jackpot is approximately 1/3.45.

When the game is in a low probability game state and the setting value is set to 6 (registered setting value = 6), the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table f shown in FIG. 6 (f). According to this low probability jackpot determination random number judgment table f, if the jackpot determination random number is between 10001 and 10253, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/259.0, and the probability of a small jackpot is approximately 1/3.45.

Figure 7 is a diagram explaining the random number judgment table for determining a high probability jackpot in the simultaneous spin reference example. When starting a lottery for a big prize for special 1 reserve and special 2 reserve in a high probability game state, the random number judgment table for determining a high probability jackpot is referenced. The random number judgment table for determining a high probability jackpot is also set for each setting value, just like the random number judgment table for determining a low probability jackpot.

When the game is in a high probability game state and the setting value is set to 1 (registered setting value = 1), the big prize lottery is performed by referring to the high probability jackpot determination random number judgment table a shown in FIG. 7 (a). According to this high probability jackpot determination random number judgment table a, if the jackpot determination random number is between 10001 and 10620, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/105.7, and the probability of a small jackpot is approximately 1/3.45.

Similarly, when the game is in a high probability game state and the setting value is set to 2 to 6 (registered setting value = 2 to 6), the big prize lottery is performed by referring to high probability jackpot determination random number judgment tables b to f shown in Figures 7 (b) to (f). According to these high probability jackpot determination random number judgment tables b to f, a jackpot is determined to have occurred when the jackpot determination random number is the value shown. Therefore, when the setting value is 2 to 6, the jackpot probability is approximately 1/102.4 to 1/91.0, respectively, and the small jackpot probability is approximately 1/3.45.

As described above, the big prize lottery is held according to the registered setting value. At this time, the probability of winning a big prize differs according to the registered setting value, and it is easier to win a big prize when the registered setting value is large than when it is small. Note that here, even if the registered setting value differs, the probability of winning a small prize does not change, but the probability of winning a small prize may be different for each registered setting value. Also, a small prize is not required, and only either a big prize or a miss may be determined in the big prize lottery.

In addition, here, the probability of winning a jackpot in both the low-probability game state and the high-probability game state is set to differ depending on the registered setting value, but it is also possible to set it so that only the probability of winning a jackpot in either the low-probability game state or the high-probability game state differs depending on the registered setting value.

Figure 8 is a diagram explaining the winning symbol random number determination table and the small winning symbol random number determination table for the simultaneous spin reference example. When a game ball enters the first start hole 120 or the second start hole 122, one winning symbol random number within the range of 0 to 99 is obtained. Then, when a "big win" determination result is derived by the above-mentioned big role lottery, the type of special symbol is determined based on the obtained winning symbol random number and the winning symbol random number determination table. At this time, if the "big win" is won by the special 1 reservation, the winning pattern random number judgment table a for special 1 is selected as shown in FIG. 8(a), if the "big win" is won by the special 2 reservation, the winning pattern random number judgment table b for special 2 is selected as shown in FIG. 8(b), if the "small win" is won by the special 1 reservation, the small win pattern random number judgment table a for special 1 is selected as shown in FIG. 8(c), and if the "small win" is won by the special 2 reservation, the small win pattern random number judgment table b for special 2 is selected as shown in FIG. 8(d). In the following, the special pattern determined by the winning pattern random number, that is, the special pattern determined when the judgment result of the big win is obtained, is called the big win pattern, the special pattern determined when the judgment result of the small win is obtained is called the small win pattern, and the special pattern determined when the judgment result of the loss is obtained is called the loss pattern.

According to the special 1 winning symbol random number determination table a shown in FIG. 8(a) and the special 2 winning symbol random number determination table b shown in FIG. 8(b), a big winning symbol (special symbols A to J) is determined as a special symbol according to the value of the acquired winning symbol random number, as shown in the figure. Also, according to the special 1 small winning symbol random number determination table a shown in FIG. 8(c) and the special 2 small winning symbol random number determination table b shown in FIG. 8(d), a small winning symbol (special symbols Z1 to Z6) is determined as a special symbol according to the value of the acquired winning symbol random number, as shown in the figure.

When the result of the big prize lottery is a "miss", if the result is derived by special 1 reservation, special pattern X is determined as the missing pattern without drawing a lottery, and when the result is derived by special 2 reservation, special pattern Y is determined as the missing pattern without drawing a lottery. In other words, the winning pattern random number determination table is referenced only when the result of the big prize lottery is a "big prize", and is not referenced when the result of the big prize lottery is a "miss" or a "small prize". In addition, the small prize pattern random number determination table is referenced only when the result of the big prize lottery is a "small prize", and is not referenced when the result of the big prize lottery is a "big prize" or a "miss". In addition, the special patterns Z1 to Z6, which are the small prize patterns, are collectively referred to simply as special pattern Z.

Figure 9 is a diagram illustrating a reach group determination random number judgment table for the simultaneous spin reference example. A plurality of reach group determination random number judgment tables are provided, and a preset table is selected according to the reserved type, reserved number, game status, etc. When a game ball enters the first start hole 120 or the second start hole 122, one reach group determination random number is obtained from the range of 0 to 10006. As described above, when the big role lottery result is derived, a process is performed to determine a variable presentation pattern that notifies the big role lottery result. In the simultaneous spin reference example, when the big role lottery result is a "miss", in determining the variable presentation pattern, first, the group type is determined by the reach group determination random number and the reach group determination random number judgment table.

For example, when the game state is set to the normal state, which will be described in detail later, if a "miss" big role lottery result is derived based on the special 1 reservation, and the number of reserved special 1s (hereinafter simply referred to as the "reserved number") at the time of the big role lottery is 0, the reach group determination random number judgment table 1 is selected as shown in FIG. 9(a). Similarly, when the game state is set to the normal state, if a "miss" big role lottery result is derived based on the special 1 reservation, and the number of reserved special roles at the time of the big role lottery is 1 to 2, the reach group determination random number judgment table 2 is selected as shown in FIG. 9(b), and if the number of reserved special roles is 3, the reach group determination random number judgment table 3 is selected as shown in FIG. 9(c). In FIG. 9, the group x written in the group type column indicates an arbitrary group number. Therefore, various group numbers are determined as the group type depending on the acquired reach group determination random number and the type of reach group determination random number judgment table to be referenced.

Note that, here, we have explained the reach group determination random number judgment table that is referenced when a "miss" major role lottery result is derived based on the special 1 reserved in the normal state, but many other reach group determination random number judgment tables are stored in the main ROM 300b.

If the result of the big prize lottery is a "big prize" or a "small prize", the group type is not determined when deciding the variable presentation pattern. In other words, the reach group determination random number judgment table is only referenced when the result of the big prize lottery is a "miss", and is not referenced when the result of the big prize lottery is a "big prize" or a "small prize".

Figure 10 is a diagram explaining the reach mode determination random number judgment table for the simultaneous spin reference example. This reach mode determination random number judgment table is broadly divided into a miss reach mode determination random number judgment table that is selected when the big role lottery result is a "miss", a big win reach mode determination random number judgment table that is selected when the big role lottery result is a "big win", and a small win reach mode determination random number judgment table that is selected when the big role lottery result is a "small win". The miss reach mode determination random number judgment table is provided for each group type determined as described above, and the big win reach mode determination random number judgment table and the small win reach mode determination random number judgment table are provided for each game state and hold type.

In addition, each reach mode determination random number judgment table is also provided for each game state and type of pattern. Here, an example of a reach mode determination random number judgment table for group x when it is a miss, which is referenced in a specific game state and type of pattern, is shown in FIG. 10(a), an example of a reach mode determination random number judgment table for a special 1 big win is shown in FIG. 10(b), an example of a reach mode determination random number judgment table for a special 2 big win is shown in FIG. 10(c), an example of a reach mode determination random number judgment table for a special 1 small win is shown in FIG. 10(d), and an example of a reach mode determination random number judgment table for a special 2 small win is shown in FIG. 10(e).

When a game ball enters the first start hole 120 or the second start hole 122, one reach mode determination random number is obtained from the range of 0 to 250. If the result of the big role lottery is a "miss," as shown in FIG. 10(a), a reach mode determination random number judgment table at the time of a miss corresponding to the group type determined by the group type lottery is selected, and a variable mode number is determined based on the selected reach mode determination random number judgment table at the time of a miss and the reach mode determination random number. If the result of the big role lottery is a "jackpot," as shown in FIG. 10(b) and (c), a reach mode determination random number judgment table at the time of a jackpot win corresponding to the game state at the time of the jackpot win and the read-out reserve type is selected, and a variable mode number is determined based on the selected reach mode determination random number judgment table at the time of a jackpot win and the reach mode determination random number.

Furthermore, if the result of the big prize lottery is a "small win," as shown in Figures 10(d) and (e), a random number judgment table for determining the reach mode at the time of the small win corresponding to the game state at the time of the small win and the hold type that was read out is selected, and a variable mode number is determined based on the selected random number judgment table for determining the reach mode at the time of the small win and the reach mode determination random number.

In addition, in each reach mode determination random number judgment table, the reach mode determination random number is associated with a fluctuation pattern random number judgment table described later along with the fluctuation mode number, and the fluctuation pattern random number judgment table is determined at the same time as the fluctuation mode number is determined. In FIG. 10, the table x written in the fluctuation pattern random number judgment table column indicates an arbitrary table number. Therefore, the fluctuation mode number and the table number of the fluctuation pattern random number judgment table are determined according to the acquired reach group determination random number and the type of reach mode determination random number judgment table to be referenced. In the simultaneous rotation reference example, the fluctuation mode number and the fluctuation pattern number described later are set in hexadecimal. In the following, "H" is added to indicate hexadecimal numbers, but ○○H written in FIG. 10 to FIG. 12 indicates an arbitrary value expressed in hexadecimal numbers.

As described above, if the result of the big role lottery is a "miss," the group type is first determined by the reach group determination random number judgment table and reach group determination random number shown in Figure 9. Then, depending on the determined group type and game status, the fluctuation mode number and fluctuation pattern random number judgment table are determined by the reach mode determination random number judgment table at the time of a miss and the reach mode determination random number shown in Figure 10 (a).

On the other hand, if the result of the big prize lottery is a "big win" or a "small win," the system will refer to the big win reach mode determination random number judgment table shown in Figure 10, which corresponds to the determined big win or small win pattern (type of special pattern), the game state when the big win or small win is won, and use the reach mode determination random number to determine the fluctuation mode number and fluctuation pattern random number judgment table.

Figure 11 is a diagram explaining a fluctuation pattern random number judgment table for a simultaneous rotation reference example. Here, fluctuation pattern random number judgment table x for a specific table number x is shown, but in addition to this, many other fluctuation pattern random number judgment tables are provided for each table number.

When a game ball enters the first starting hole 120 or the second starting hole 122, one fluctuation pattern random number is obtained from the range of 0 to 238. Then, based on the fluctuation pattern random number determination table determined at the same time as the above fluctuation mode number and the obtained fluctuation pattern random number, the fluctuation pattern number is determined as shown in the figure.

In this way, when the big prize lottery is held, the change mode number and change pattern number are determined according to the big prize lottery result, the determined symbol type, the game status, the number of reserved balls, the reserved ball type, etc. These change mode numbers and change pattern numbers specify the change presentation pattern, and each of them is associated with the mode and time of the change presentation.

Figure 12 is a diagram illustrating a variation time determination table for the simultaneous rotation reference example. Once the variation mode number is determined as described above, variation time 1 is determined according to the variation time 1 determination table shown in Figure 12 (a). According to this variation time 1 determination table, variation time 1 is associated with each variation mode number, and the corresponding variation time 1 is determined according to the determined variation mode number.

Once the fluctuation pattern number is determined as described above, the fluctuation time 2 is determined according to the fluctuation time 2 determination table shown in FIG. 12(b). According to this fluctuation time 2 determination table, a fluctuation time 2 is associated with each fluctuation pattern number, and the corresponding fluctuation time 2 is determined according to the determined fluctuation pattern number. The total time of the fluctuation times 1 and 2 determined in this way is the time of the fluctuation performance that notifies the result of the big role lottery, that is, the fluctuation time. This fluctuation time is the time until the determined special pattern is stopped and displayed on the first special pattern display device 160 or the second special pattern display device 162.

As will be described in more detail below, when a special pattern is determined based on the special 1 reservation and the change mode number and change pattern number, i.e., the change time, are determined, the change of the pattern is displayed on the first special pattern display 160 for the determined change time, and when the change time has elapsed, the determined special pattern is displayed stationary on the first special pattern display 160. Also, when a special pattern is determined based on the special 2 reservation and the change pattern number, i.e., the change time, are determined, the change of the pattern is displayed on the second special pattern display 162 for the determined change time, and when the change time has elapsed, the determined special pattern is displayed stationary on the second special pattern display 162. At this time, when a losing symbol is stopped and displayed on the first special symbol display 160, a loss is confirmed as a result of the big role lottery, and the big role lottery based on the next special 1 reservation can be executed, and when a losing symbol is stopped and displayed on the second special symbol display 162, a loss is confirmed as a result of the big role lottery, and the big role lottery based on the next special 2 reservation can be executed. On the other hand, when a big win symbol is stopped and displayed on the first special symbol display 160 or the second special symbol display 162, a big win is confirmed as a result of the big role lottery, and a big role game is executed, and when a small win symbol is stopped and displayed on the first special symbol display 160 or the second special symbol display 162, a small win is confirmed as a result of the big role lottery, and a small win game is executed.

In this way, the change time stipulates the time for which the pattern on the first special pattern display device 160 or the second special pattern display device 162 changes and displays, in other words, the time until the result of the big prize lottery is determined.

When the fluctuation mode number is determined in the above manner, a fluctuation mode command corresponding to the determined fluctuation mode number is sent to the sub-control board 330, and when the fluctuation pattern number is determined, a fluctuation pattern command corresponding to the determined fluctuation pattern number is sent to the sub-control board 330. In the sub-control board 330, the first half of the fluctuation performance is mainly determined based on the received fluctuation mode command, and the second half of the fluctuation performance is mainly determined based on the received fluctuation pattern command, but the details will be described later. Note that, below, the fluctuation mode number and the fluctuation pattern number are collectively referred to as fluctuation information, and the fluctuation mode command and the fluctuation pattern command are collectively referred to as fluctuation commands.

Figure 13 is a diagram explaining the game states and variable times in the simultaneous spin reference example. As described above, the special game state and the normal game state are combined to form one game state, and the progress of the game is controlled according to the game state being set. As already explained, there are two types of special game states, a low probability game state and a high probability game state, which differ in the probability of winning a jackpot. In addition, there are three types of normal game states, a non-time-saving game state, a medium time-saving game state, and a time-saving game state, which differ in the ease (ball-scoring frequency) of entering the first variable start hole 120B.

Here, in normal play, the ease with which a game ball can enter the first variable start port 120B is determined by three factors: winning probability, fluctuation time, and opening time. As will be described in detail later, in normal play, when a game ball passes through the gate 124 or enters the normal play operation port 125, a normal play reserve is stored. Then, based on the stored normal play reserve, a normal play lottery is held to determine whether or not to open the movable piece 120b. The result of this normal play lottery is determined after a predetermined fluctuation time has elapsed. When a win is determined as a result of the normal play lottery, the movable piece 120b is opened. At this time, the winning probability in the normal play lottery, the fluctuation time, and the opening time when opening the movable piece 120b are each set for each normal play state.

In the simultaneous spin reference example, as shown in FIG. 13(a), six types of game states are provided by combining special game states and normal game states. The initial state of the gaming machine 100 is a low probability game state and a non-time-saving game state. In the non-time-saving game state, the probability of winning in the normal drawing is low, the fluctuation time is long, and the opening time of the movable piece 120b is short. In the simultaneous spin reference example, a game state that combines a low probability game state and a non-time-saving game state is called a normal state.

In the simultaneous spin reference example, the game state may be set to a high probability game state and a non-time-saving game state, and the game state that combines these two is called the most advantageous state. This most advantageous state is the most advantageous of the six game states, and is set so that if the game balls are fired appropriately, the number of game balls will gradually increase during play, even if a jackpot is not won.

In addition, in the simultaneous spin reference example, the game may be set to a low probability game state and a time-saving game state. In the time-saving game state, the probability of winning in the regular drawing is high, the fluctuation time is short, and the opening time of the movable piece 120b is long. In the following, a game state that combines the low probability game state and the time-saving game state is called a low probability time-saving state.

In addition, in the simultaneous spin reference example, the game state may be set to a high probability game state and a time-saving game state. In the following, a game state in which a high probability game state and a time-saving game state are combined is referred to as a high probability time-saving state or a high probability precursor state. The high probability time-saving state and the high probability precursor state will be described in more detail later.

In the simultaneous spin reference example, the game may be set to a high probability game state and a medium time-saving game state. In the medium time-saving game state, the probability of winning in the normal drawing is higher than in the non-time-saving game state and lower than in the time-saving game state, the fluctuation time is short, and the opening time of the movable piece 120b is long. This game state can be set when an unforeseen event occurs, such as when the game ball is not launched appropriately. Hereinafter, a game state that combines a high probability game state and a medium time-saving game state is called a penalty state.

In addition, a presentation mode corresponding to the game state set on the main control board 300 is set on the sub-control board 330. The presentation mode specifies the background image and BGM displayed on the main presentation display section 200a, and the content of the presentation differs for each presentation mode. In other words, the player can identify the current game state by the presentation mode.

As described above, in the simultaneous spin reference example, six game states are provided. As described above, the change mode number and change pattern number, i.e., the change time, are determined according to the game state when the big role lottery is performed, the reserved type, the number of changes in that game state, and the type of pattern.

Here, in the gaming machine 100, an actual variable target is set for each gaming state. The actual variable target indicates the type of reserve for which the big prize lottery should be held, and for each gaming state, either the special 1 reserve or the special 2 reserve is set as the actual variable target. In the normal state, the special 1 reserve is set as the actual variable target. Also, in the normal state, since the normal gaming state is a non-time-saving gaming state, the first variable start port 120B is rarely opened. Therefore, in the normal state, the player needs to shoot the gaming ball toward the first gaming area 116a in order to make the gaming ball enter the first fixed start port 120A.

In the normal state, the special 1 reserved ball, which is the actual variable, is used to draw a big prize, and when a losing symbol or a small winning symbol is determined, the variable time is determined within a range of 3 to 100 seconds. Also, in the normal state, the special 1 reserved ball is used to draw a big prize, and when a winning symbol is determined, the variable time is determined within a range of 40 to 100 seconds.

On the other hand, in the normal state, when a big prize lottery is held based on the special 2 reserve, which is not actually subject to fluctuation, the fluctuation time is always set to 10 minutes regardless of the determined symbol type. In this way, by setting the fluctuation time to a long time such as 10 minutes, in the normal state, even if the player puts the game ball into the second starting hole 122, the opportunity to hold a big prize lottery based on the special 2 reserve becomes extremely low.

To be more specific, the second start hole 122 is provided in the second play area 116b, and is configured as a fixed start hole that game balls can always enter. Furthermore, due to the playability of the gaming machine 100, the second start hole 122 is located in a position where game balls can enter more easily than the first start hole 120. Therefore, if the fluctuation time for the special 2 reservation is set to a short time in the normal state, the player will be given more opportunities than necessary to win the big prize lottery. Therefore, in accordance with the original playability in the normal state, the fluctuation time is set to a long time, such as 10 minutes, in order to appropriately launch game balls toward the first play area 116a.

In the most advantageous state, the special 2 reserve is set as the actual variable. Therefore, in the most advantageous state, the player needs to shoot the game ball toward the second game area 116b in order to make the game ball enter the second starting hole 122. In the most advantageous state, when a big role lottery is performed by the special 1 reserve, which is not an actual variable, the variable time is always set to 10 seconds regardless of the determined pattern type. Note that the effect on playability is smaller when a big role lottery is performed by the special 1 reserve, which is not an actual variable, in the most advantageous state than when a big role lottery is performed by the special 2 reserve, which is not an actual variable, in the normal state. Therefore, in the most advantageous state, the variable time when a big role lottery is performed by the special 1 reserve, which is not an actual variable, is set to a short time of 10 seconds.

In the most advantageous state, a lottery for a big prize is held by the special 2 reserved symbol, which is the actual variable target, and when a losing symbol or a small winning symbol is determined, the variable time is determined within a range of 1 to 3 seconds. Also, in the most advantageous state, a lottery for a big prize is held by the special 2 reserved symbol, and when a big winning symbol is determined, the variable time is determined within a range of 3 to 10 seconds.

In both the low-probability time-saving state and the high-probability time-saving state, the special 1 reservation is set as the actual variable target. In addition, in the low-probability time-saving state and the high-probability time-saving state, the normal game state is set as the time-saving game state, and the first variable start port 120B is frequently controlled to the open state. Therefore, in these two game states, the player needs to launch the game ball toward the second game area 116b to make the game ball enter the first variable start port 120B. In both of these game states, the same variable pattern random number judgment table is selected, but these two game states have in common that the normal game state is a time-saving game state. In other words, when the normal game state is a time-saving game state, a big role lottery is performed by the special 1 reservation, which is the actual variable target, and when a losing pattern or a small winning pattern is determined, a variable time of 1 second is always determined. Also, in the low probability time-saving state or high probability time-saving state, a lottery for a big role is held by special 1 reservation, and when a big win pattern is determined, the fluctuation time is always set to 30 seconds.

In the high probability premonition state, the special 1 reserve is set as the actual variable target. Also, in the high probability premonition state, the normal game state is set as the time-saving game state, and the first variable start port 120B is frequently controlled to the open state. Therefore, in the high probability premonition state, the player needs to shoot the game ball toward the second game area 116b to make the game ball enter the first variable start port 120B. In the high probability premonition state, a big role lottery is performed using the special 1 reserve, which is the actual variable target, and when a losing pattern or a small winning pattern is determined, the variable time is determined within the range of 3 to 10 seconds. Also, in the high probability premonition state, a big role lottery is performed using the special 1 reserve, and when a big winning pattern is determined, the variable time is always determined to be 30 seconds.

On the other hand, in the low probability time-saving state, high probability time-saving state, and high probability premonition state, i.e., when the normal game state is a time-saving game state, if a big role lottery is held by a special 2 reserve that is not actually subject to change, the change time is always set to 10 minutes regardless of the type of pattern that is determined.

In the penalty state, the special 1 reserved ball is set as the actual variable object. Also, in the penalty state, the normal game state is set as the medium time shortening game state, and the first variable start port 120B is controlled to be in the open state at a certain frequency. Therefore, in the penalty state, the player needs to shoot the game ball toward the second game area 116b in order to make the game ball enter the first variable start port 120B. In the penalty state, a big role lottery is performed by the special 1 reserved ball, which is the actual variable object, and when a losing symbol or a small winning symbol is determined, the variable time is determined within a range of 3 to 100 seconds. Also, in the penalty state, a big role lottery is performed by the special 1 reserved ball, and when a big winning symbol is determined, the variable time is determined within a range of 40 to 100 seconds.

On the other hand, in a penalty state, if a big prize lottery is held by a special 2 reserve that is not actually subject to change, the change time is always set to 10 minutes, regardless of the type of symbol that is determined.

As described above, an actual change target is set for each game state, and when a big role lottery is held based on a reserved type that is an actual change target, the longest change time is 100 seconds. On the other hand, when a big role lottery is held based on a reserved type that is not an actual change target, the change time is approximately 10 minutes, so that games that go against the original gameplay are not played.

In the simultaneous spin reference example, a case is described in which the average fluctuation time of the high-probability time-saving state is shorter than the average fluctuation time of the high-probability precursor state, but the average fluctuation time of the high-probability time-saving state may be longer than the average fluctuation time of the high-probability precursor state. In other words, the average fluctuation time of the high-probability time-saving state and the average fluctuation time of the high-probability precursor state may be different.

Figure 14 is a first diagram explaining the special electric role operation ram set table relating to the simultaneous rotation reference example, and Figure 15 is a second diagram explaining the special electric role operation ram set table relating to the simultaneous rotation reference example. The special electric role operation ram set table stores various data for controlling the big role game or the small win game, and during the big role game and the small win game, the first big win port solenoid 126c or the second big win port solenoid 128c is controlled to be energized by referring to the special electric role operation ram set table. In reality, a plurality of special electric role operation ram set tables are provided for each type of special pattern (big win pattern and small win pattern), and the corresponding table is set at the start of the big role game or the small win game according to the type of special pattern determined, but here, for convenience of explanation, the control data of the special pattern is shown for each type of pattern.

As shown in FIG. 14, the big prize game consists of multiple rounds of play in which the big prize opening is opened and closed a predetermined number of times, while the small prize game consists of only one round of play. According to this special electric device operation ram set table, the opening time (waiting time until the first round of play begins), the maximum number of times the special electric device operates (the number of rounds of play executed during one big win play or small win play), the number of times the special electric device opens and closes (the number of times the large prize opening is opened during one round), the solenoid energization time (the energization time of the first large prize opening solenoid 126c or the second large prize opening solenoid 128c for each number of times the large prize opening is opened, i.e., the opening time of one large prize opening), the specified number (the maximum number of times a large prize opening can be won in one round of play), the effective time for closing the large prize opening (the closing time of the large prize opening between rounds of play, i.e., the interval time), and the ending time (the waiting time from the end of the last round of play until the normal special play (the variable display of the patterns described later) is resumed) are stored in advance as control data for each type of special pattern as shown in the figure.

If a jackpot is won by the special 1 reservation and the special symbols A, B, or D are determined as the jackpot symbol, a big prize game consisting of four rounds of play is executed. In this big prize game, the first big prize opening 126 is opened only once each in the first to fourth rounds of play. In each round of play, the first big prize opening 126 is opened for a maximum of 29.0 seconds, and when a specified number of game balls enter during this time or the maximum opening time (29.0 seconds) has elapsed, the first big prize opening 126 is closed and one round of play ends.

In addition, if a jackpot is won by the special 1 reservation and the special symbols C and E are determined as the jackpot symbols, a jackpot game consisting of 10 rounds of play is executed. In these jackpot games, the first jackpot opening 126 is opened only once each in the first to tenth rounds of play. In each round of play, the first jackpot opening 126 is opened for a maximum of 29.0 seconds, and when a specified number of game balls enter during this time or the maximum opening time (29.0 seconds) has elapsed, the first jackpot opening 126 is closed and one round of play ends.

In addition, if a small prize is won by the special 1 reservation and the special symbols Z1 to Z3 are determined as the small prize symbol, a small prize game consisting of one round of play is executed. In this small prize game, the second large prize opening 128 is opened once for 0.1 seconds during one round of play.

As shown in FIG. 15, if a jackpot is won by the special 2 reserve and the special symbols F, G, or I are determined as the jackpot symbol, a big prize game consisting of four rounds of play is executed. In this big prize game, the first big prize opening 126 is opened only once each in the first to fourth rounds of play. In each round of play, the first big prize opening 126 is opened for a maximum of 29.0 seconds, and when a specified number of game balls enter during this time or the maximum opening time (29.0 seconds) has elapsed, the first big prize opening 126 is closed and one round of play ends.

In addition, if a jackpot is won by the special 2 reserve and the special symbols H and J are determined as the jackpot symbols, a jackpot game consisting of 10 rounds of play is executed. In this jackpot game, the first jackpot opening 126 is opened only once each in the first to tenth rounds of play. In each round of play, the first jackpot opening 126 is opened for a maximum of 29.0 seconds, and when a specified number of game balls enter during this time or the maximum opening time (29.0 seconds) has elapsed, the first jackpot opening 126 is closed and one round of play ends.

In addition, if a small prize is won by the special 2 reservation and the special symbols Z4 to Z6 are determined as the small prize symbol, a small prize game consisting of one round of play is executed. Here, in the small prize game when the special symbol Z4 is determined as the small prize symbol, the second large prize opening 128 is opened twice for 0.1 seconds in one round of play. The interval time during the round, which is the pause time between the two openings of the second large prize opening 128, is set to 1.78 seconds. Since the game balls are shot at intervals of 0.6 seconds at the shortest, the probability that the game balls will enter the second large prize opening 128 during this small prize game is low, considering the opening time of the second large prize opening 128 and the shooting interval of the game balls.

However, in the simultaneous spinning reference example, the structure is such that game balls tend to remain on the movable piece 128b that keeps the second large prize opening 128 in a closed state, and when the movable piece 128b transitions to an open state, the game balls remaining on the movable piece 128b are guided into the second large prize opening 128. Therefore, when the second large prize opening 128 is opened twice for 0.1 seconds, an average of 2 to 3 game balls enter the second large prize opening 128.

In addition, in a small prize game in which the special symbol Z5 is determined as the small prize symbol, the second large prize opening 128 is opened 0.1 seconds x 3 times in one round of play. In this case, the interval time during the round is set to 0.84 seconds. In this small prize game, an average of 3 to 4 game balls enter the second large prize opening 128.

Furthermore, in a small prize game in which the special pattern Z6 is determined as the small prize pattern, the second large prize opening 128 is opened 0.1 seconds x 12 times in one round of play. In this case, the interval time during the round is set to 0.84 seconds. In this small prize game, by continuing to shoot game balls toward the second game area 116b, it is possible to almost certainly cause a specified number of game balls (e.g. 10 balls) to enter the second large prize opening 128.

In addition, during the design stage of the gaming machine 100, it is necessary to strictly manage and adjust the firing prize ball ratio, which is the ratio between the number of game balls fired and the number of prize balls paid out. For this reason, in the simultaneous spin reference example, special pattern Z4 is provided, which opens twice for 0.1 seconds in a small win game, and special pattern Z5 is provided, which opens three times for 0.1 seconds in a small win game, and the firing prize ball ratio can be easily adjusted and changed simply by changing the selection ratio of these.

Figure 16 is a diagram illustrating a game state setting table for setting the game state after the end of the big prize game in the simultaneous spin reference example. In the simultaneous spin reference example, when the big prize game is executed, the game state setting table is referenced and the game state after the big prize game ends is set according to the game state at the time of winning the big prize, the reserved type, and the type of special pattern (big prize pattern).

If the game state at the time of winning the jackpot is the normal state or the penalty state, when the jackpot is won by the special 1 reservation, which is the actual variable target, the game state after the big prize game is set according to the type of the jackpot pattern. Specifically, if the special pattern A is determined as the jackpot pattern, it is set to a low probability time-saving state (the special game state is a low probability game state, and the normal game state is a time-saving game state). At this time, the number of times the time-saving game state continues (hereinafter referred to as the "time-saving number of times") is set to 100. This means that the time-saving game state continues until the big prize lottery is performed 100 times. However, the above-mentioned time-saving number of times indicates the maximum number of times that it continues in the time-saving game state of 1, and if a jackpot is won before the above-mentioned number of times of continuation is reached, the game state will be set again. Therefore, if the time-saving game state is set after the big win game ends, and a lottery result other than a jackpot is drawn 100 times without a jackpot result being drawn in the time-saving game state, the game state will change to a non-time-saving game state (normal state).

In addition, if special patterns B or D are determined as the jackpot pattern, the machine will be set to a high-probability time-saving state (the special game state is a high-probability game state, and the normal game state is a time-saving game state). At this time, "next" is set as the high-probability number of times, and the high-probability game state will continue until the next jackpot is won. In addition, "next" is set as the number of time-saving times, and the time-saving game state will continue until the next jackpot is won. Therefore, if special patterns B or D are determined, the high-probability time-saving state will continue after the big win game until the next jackpot is won.

In addition, if special patterns C or E are determined as the jackpot pattern, the game will be set to a high probability precursor state (the special game state is a high probability game state, and the normal game state is a time-saving game state). At this time, "next time" is set as the high probability number of times, and the time-saving number of times is set to 100. If special patterns C or E are determined, the high probability game state will continue until the next jackpot is won, while the time-saving game state will end after 100 times. Therefore, if special patterns C or E are determined, after the big prize game, the game state will transition to the most advantageous state when the results of the big prize lottery have been derived 100 times.

In addition, if the game state at the time of winning the jackpot is the normal state or the penalty state, if the jackpot is won by the special 2 reserve, which is not actually subject to change, the game state after the big win is set as follows. That is, if special pattern F is determined as the jackpot pattern, it is set to the normal state (special game state is a low probability game state, normal game state is a non-time-saving game state). In addition, if special patterns G to J are determined as the jackpot pattern, it is set to the penalty state (special game state is a high probability game state, normal game state is a medium time-saving game state). At this time, the number of high probability wins and the number of time-saving wins are both set to "next time".

In addition, if the game state at the time of winning the jackpot is the most advantageous state, when the jackpot is won by a special 1 reserve that is not actually subject to change, the game state after the big win is set as follows. That is, if special pattern A is determined as the jackpot pattern, it is set to a low probability time-saving state (the special game state is a low probability game state, and the normal game state is a time-saving game state). At this time, the number of time-saving times is set to 100. In addition, if special patterns B to E are determined as the jackpot pattern, the game state after the big win is set to the same as the normal state and penalty state.

On the other hand, if the game state at the time of winning the jackpot is the most advantageous state, when a jackpot is won by the special 2 reserve, which is essentially subject to change, the game state after the big win is set as follows. That is, if the special pattern F is determined as the jackpot pattern, it is set to a low-probability time-saving state (the special game state is a low-probability game state, and the normal game state is a time-saving game state). At this time, the number of time-saving times is set to 100. Also, if the special pattern G or I is determined as the jackpot pattern, it is set to a high-probability time-saving state (the special game state is a high-probability game state, and the normal game state is a time-saving game state). At this time, the high-probability number of times and the number of time-saving times are set to "next time".

In addition, if the special symbols H or J are determined as the jackpot symbols, the high probability premonition state is set (the special game state is a high probability game state, and the normal game state is a time-saving game state). At this time, the number of high probability times is set to "next time," and the number of time-saving times is set to 100.

In addition, if the game state at the time of winning the jackpot is a low probability time-saving state, a high probability time-saving state, or a high probability premonition state, in other words, if the normal game state is a time-saving game state, the game state after the big win is set to the same as the normal state or the penalty state.

Figure 17 is a diagram explaining a winning decision random number judgment table for the simultaneous spin reference example. When the game ball flowing down the game area 116 passes through the gate 124 or enters the normal symbol operating port 125, a normal symbol judgment process (hereinafter referred to as "normal symbol lottery") is performed, which corresponds to whether or not to control the flow of electricity to the movable piece 120b of the first variable start port 120B.

As will be described in detail later, when a game ball passes through gate 124 or enters normal map operation port 125, one winning determination random number is obtained from the range of 0 to 99, and this random number value is stored in the normal map reserve memory area of main RAM 300c, up to a maximum of four. In other words, the normal map reserve memory area has four memory sections for saving winning determination random numbers. Therefore, if a game ball passes through gate 124 or enters normal map operation port 125 with winning determination random numbers stored in all four memory sections of the normal map reserve memory area, no winning determination random number will be stored based on the passage of the game ball. In the following, the winning determination random number stored in the normal map reserve memory area when a game ball passes through gate 124 or enters normal map operation port 125 is referred to as a normal map reserve.

When the normal game state is a non-time-saving game state and a normal symbol lottery is started, the non-time-saving game state winning random number judgment table is referenced as shown in FIG. 17(a). According to this non-time-saving game state winning random number judgment table, if the winning random number is 0, a winning symbol is determined as the type of normal symbol, and if the winning random number is 1 to 99, a losing symbol is determined as the type of normal symbol. Therefore, the probability of a winning symbol being determined in a non-time-saving game state, that is, the probability of winning, is 1/100. As will be described in detail later, when a winning symbol is determined in this normal symbol lottery, the movable piece 120b of the first variable start opening 120B is controlled to the open state, and when a losing symbol is determined, the movable piece 120b of the first variable start opening 120B is maintained in the closed state.

When starting the normal symbol lottery in the intermediate time-saving play state, the winning symbol determination random number judgment table for the intermediate time-saving play state is referenced, as shown in FIG. 17(b). According to this winning symbol determination random number judgment table for the intermediate time-saving play state, if the winning symbol determination random number is between 0 and 49, a winning symbol is determined as the type of normal symbol, and if the winning symbol determination random number is between 50 and 99, a losing symbol is determined as the type of normal symbol. Therefore, the probability of a winning symbol being determined in the intermediate time-saving play state, i.e., the probability of winning, is 50/100.

In addition, when starting the regular symbol lottery in the time-saving play state, the time-saving play state win determination random number judgment table is referenced, as shown in FIG. 17(c). According to this time-saving play state win determination random number judgment table, if the win determination random number is 0-98, a winning symbol is determined as the type of regular symbol, and if the win determination random number is 99, a losing symbol is determined as the type of regular symbol. Therefore, the probability of a winning symbol being determined in the time-saving play state, i.e., the probability of winning, is 99/100.

18(a) is a diagram explaining the normal symbol variation time data table relating to the simultaneous spin reference example, and FIG. 18(b) is a diagram explaining the opening/closing control pattern table relating to the simultaneous spin reference example. As described above, when the normal symbol lottery is performed, the variation time of the normal symbol is determined. The normal symbol variation time data table is referenced when determining the variation time of the normal symbol when a winning symbol or a losing symbol is determined by the normal symbol lottery. According to this normal symbol variation time data table, when the game state is set to a non-time-saving game state or a medium time-saving game state, the variation time is determined to be 10 seconds, and when the game state is set to a time-saving game state, the variation time is determined to be 1 second. When the variation time is determined in this way, the normal symbol display 168 is displayed (blinking) for the determined time. Then, when a winning symbol is determined, the normal symbol display 168 is turned on, and when a losing symbol is determined, the normal symbol display 168 is turned off.

When the winning symbol is determined by the normal symbol lottery and the normal symbol display 168 is lit, the movable piece 120b of the first variable start port 120B is controlled to energize by referring to the opening/closing control pattern table, as shown in FIG. 18(b). Note that, in reality, an opening/closing control pattern table is provided for each game state, and the corresponding table is set when the normal electric role solenoid 120c starts energizing, depending on the game state when the normal symbol is determined.

Once the winning pattern is determined, the first variable starting port 120B is controlled to open and close by referring to the opening and closing control pattern table, as shown in Figure 18 (b). According to this opening/closing control pattern table, the time before normal power opening (waiting time until the first variable start port 120B starts opening), the maximum number of normal electric role opening/closing switching times (number of times the first variable start port 120B is opened), the solenoid energization time (the energization time of the normal electric role solenoid 120c for each number of times the first variable start port 120B is opened, i.e., the opening time of the first variable start port 120B once), the specified number (the maximum number of winnings that can be won into the first variable start port 120B during the full opening of the first variable start port 120B), the normal power closing effective time (the closing time between each opening of the first variable start port 120B, i.e., the pause time), the normal power effective state time (waiting time from the end of the last opening of the first variable start port 120B), and the normal power end wait time (waiting time until the variable display of the normal pattern described later is resumed after the normal power effective state time has elapsed) are stored in advance for each game state as shown in the figure as control data for the first variable start port 120B.

In this way, by setting the winning probability of the normal symbol, the variable time and the opening time, as shown in the lower part of Figure 18 (b), the fired prize ball ratio (the ratio of the number of prize balls that enter the first variable start port 120B, the second start port 122, the normal symbol operating port 125 and the large prize entry port and are paid out to the player relative to the number of game balls fired into the game area 116) is the number of fired balls:number of prize balls = 100:20 in the non-time-saving game state, the number of fired balls:number of prize balls = 100:40 in the intermediate time-saving game state, and the number of fired balls:number of prize balls = 100:99 in the time-saving game state.

The opening and closing conditions of the first variable start port 120B stipulate three elements: the probability of winning a normal symbol, the time for which the normal symbol is displayed in a variable manner, and the opening time of the first variable start port 120B. In other words, by combining the three elements of the probability of winning a normal symbol, the time for which the normal symbol is displayed in a variable manner, and the opening time of the first variable start port 120B, it is possible to set the frequency of game balls entering the first variable start port 120B and the ratio of prize balls fired in each of the non-time-saving game state, intermediate time-saving game state, and time-saving game state. In any case, the combination of the three elements shown here is merely one example, and it is sufficient to combine the three elements so that the ratio of prize balls fired is higher in the time-saving game state than in the non-time-saving game state.

Figure 19 is a diagram explaining the transition of game states according to the original gameplay of the simultaneous spin reference example. With the above configuration, the game machine 100 realizes the following gameplay. Note that here, the case where the registration setting value is set to "1" is explained. First, in the initial state of the game machine 100, it is set to the normal state shown in Figure 19 (a). In the normal state, the actual variable target is set to special 1 reservation, so the player launches the game ball toward the first game area 116a to make the game ball enter the first fixed start hole 120A. Since the first game area 116a is located on the left side of the game board 108, the player will perform what is called a "left shot" in the normal state.

When a game ball enters the first fixed starting hole 120A, the special 1 reserve is stored in the first special chart reserve memory area. The special 1 reserves stored in the first special chart reserve memory area are read out sequentially when the starting conditions are met, and a big prize lottery is held based on the read special 1 reserves. At this time, the probability of winning a big prize is set to approximately 1/300.6. Under normal conditions, the game is played with the aim of winning a big prize in the big prize lottery based on this special 1 reserve. Note that the prize ball ratio when a game ball is fired toward the first game area 116a is set to 100:20, and the game balls will decrease during play.

In the normal state, if a jackpot is won in the big prize lottery using the special 1 reservation, a big prize game is executed. In this big prize game, the first big prize opening 126 is opened and a round game is executed four or ten times, allowing the player to win four or ten rounds of prize balls. If a jackpot is won using the special 1 reservation, one of the special patterns A to E is determined as the jackpot pattern.

In the normal state, if the jackpot symbol stopped and displayed on the first special symbol display 160 is special symbol A, the game state after the big win will be the low-probability time-saving state shown in FIG. 19(b). When a jackpot is won with special 1 reserved, there is a 30% probability that special symbol A will be determined as the jackpot symbol. Therefore, when a jackpot is won in the normal state, there is a 30% probability that the game state will transition to the low-probability time-saving state. In the low-probability time-saving state, the actual variable target is set to special 1 reserved, but since the normal game state is the time-saving game state, the player will hit the ball to the right, aiming at the second game area 116b, in order to get the game ball to enter the first variable start hole 120B.

In other words, in this low-probability time-saving state, just like in the normal state, the player plays with the goal of winning the jackpot in the big prize lottery based on the special 1 reserve. In the low-probability time-saving state, the probability of winning the jackpot is approximately 1/300.6, but since the normal game state is a time-saving game state, the movable piece 120b frequently opens. Therefore, the ratio of fired prize balls is 100:99, and the player can aim for a jackpot while reducing the consumption of game balls.

When the game transitions to the low probability time-saving state, the number of time-saving times is set to 100, and if no jackpot is won in the 100 big prize draws, the game state will transition back to the normal state (time-saving time ...

In addition, in the normal state, if the jackpot pattern displayed on the first special pattern display 160 is the special pattern B or D, the game state after the big win will be the high probability time-saving state shown in FIG. 19(c). When a jackpot is won with the special 1 reserved, there is a 35% probability that the special pattern B or D will be determined as the jackpot pattern. Therefore, when a jackpot is won in the normal state, there is a 35% probability that the game state will transition to the high probability time-saving state. In the high probability time-saving state, the actual variable target is set to the special 1 reserved, but since the normal game state is the time-saving game state, the player will hit the ball to the right, aiming at the second game area 116b, in order to get the game ball into the first variable start hole 120B.

In other words, in this high-probability time-saving state, just like in the normal state, the player plays with the goal of winning the jackpot in the lottery for the big prize based on the special 1 reservation. In the high-probability time-saving state, the probability of winning the jackpot is approximately 1/105.7, and since the normal game state is a time-saving game state, the movable piece 120b frequently opens. Therefore, the ratio of fired prize balls is 100:99, and the player can play the lottery for the big prize while reducing the consumption of game balls. Therefore, in the high-probability time-saving state, it can be said that the next jackpot is essentially guaranteed to be won.

In addition, in the normal state, if the jackpot pattern displayed on the first special pattern display 160 is the special pattern C or E, the game state after the big win game will be the high probability premonition state shown in FIG. 19(d). When a jackpot is won with the special 1 reserved, there is a 35% probability that the special patterns C or E will be determined as the jackpot pattern. Therefore, when a jackpot is won in the normal state, there is a 35% probability that the game state will transition to the high probability premonition state. In the high probability premonition state, the actual variable target is set to the special 1 reserved, but since the normal game state is the time-saving game state, the player will hit the ball to the right, aiming at the second game area 116b, in order to get the game ball to enter the first variable start hole 120B.

When the special symbols C or E are selected, the game is set to a high probability premonition state and the time-saving count is set to 100. When the number of changes after the big win reaches 100, the time-saving game state ends and the normal game state becomes a non-time-saving game state. As a result, the game state transitions to the most advantageous state shown in FIG. 19(e) due to the time-saving end. As will be described in detail later, in the most advantageous state, the number of game balls can be increased simply by continuing to fire game balls toward the second game area 116b. Therefore, in the high probability premonition state, the objective of the game is not to win a jackpot, but to end the time-saving state without winning a jackpot.

According to the special 1 reserve that is the actual variable target in the high probability premonition state, high probability time-saving state, and low probability time-saving state described above, when a jackpot is won, special patterns A to E are determined as the jackpot pattern. When special pattern A is determined, four rounds of play are executed in the big prize game, and the game state after the big prize game becomes the low probability time-saving state shown in FIG. 19(b). Also, when special patterns B or D are determined, four or ten rounds of play are executed in the big prize game, and the game state after the big prize game becomes the high probability time-saving state. Also, when special patterns C or E are determined, four or ten rounds of play are executed in the big prize game, and the game state after the big prize game becomes the high probability premonition state.

In the most advantageous state, when a game ball enters the second starting hole 122, the special 2 reserve is stored in the second special chart reserve memory area. The special 2 reserves stored in the second special chart reserve memory area are read out sequentially when the starting conditions are met, and a lottery for a big prize is held based on the read special 2 reserves. At this time, the probability of winning a big prize is set to approximately 1/105.7, and the probability of winning a small prize is set to approximately 1/3.45. In the most advantageous state, the main objective of the game is to win a small prize in the lottery for a big prize based on this special 2 reserve.

Specifically, when a game ball is shot into the second game area 116b, the ratio of prize balls paid out by the game ball entering the second start hole 122 to the number of shot balls is set to about 100:60 to 80. In the most advantageous state, the probability of winning a small prize in the large role lottery by the special 2 reservation is about 1/3.45, so small prize games are frequently played. Here, when a small prize is won by the special 2 reservation, small prize patterns Z4 to Z6 are determined. As described above, in a small prize game when the small prize pattern Z4 is stopped and displayed on the second special pattern display 162, an average of 2 to 3 game balls enter the second large prize hole 128. In a small prize game when the small prize pattern Z5 is stopped and displayed on the second special pattern display 162, an average of 3 to 4 game balls enter the second large prize hole 128. Furthermore, in a small win game in which the small win symbol Z6 is stopped and displayed on the second special symbol display 162, approximately the specified number of game balls enter the second large prize opening 128.

When a game ball enters the second large prize opening 128, for example, 15 prize balls are paid out for each game ball that enters. As a result, in the most advantageous state, the fired prize ball ratio, which is the ratio of the number of all prize balls to the number of fired balls, is 100:120, and the number of game balls can be increased simply by continuing to fire game balls toward the second game area 116b.

In addition, in this most advantageous state, the normal game state is a non-time-saving game state, and the movable piece 120b is almost never in the open state. Also, in the most advantageous state, the special game state is a high probability game state, and since the probability of winning a jackpot in the most advantageous state is approximately 1 in 105.7, in the most advantageous state, it can be said that the next jackpot is essentially guaranteed to be won.

According to the special 2 reserve that is the actual variable target in this most advantageous state, when a jackpot is won, special symbols F to J are determined as the jackpot symbol. When special symbol F is determined, four rounds of play are executed in the big prize game, and the game state after the big prize game becomes a low-probability time-saving state as shown in FIG. 19(b). When special symbols G or I are determined, four or ten rounds of play are executed in the big prize game, and the game state after the big prize game becomes a high-probability time-saving state. When special symbols H or J are determined, four or ten rounds of play are executed in the big prize game, and the game state after the big prize game becomes a high-probability precursor state.

The most advantageous state is much more advantageous than other game states, so the main objective of playing on the gaming machine 100 is to transition the game state to the most advantageous state. As described above, the game first starts in the normal state, but there is no immediate transition from this normal state to the most advantageous state. Therefore, the transition route to the most advantageous state on the gaming machine 100 is the transition route that transitions to the most advantageous state via the high probability precursor state.

Furthermore, in the simultaneous spin reference example, aside from the time-saving feature escaping in the high probability premonition state, the condition for transitioning from the high probability premonition state to the most advantageous state is set to be the winning of a specific small win symbol. Specifically, when a small win is won by the special 1 reserve, which is the actual variable subject in the high probability premonition state, the small win symbol is determined to be special symbol Z1 with a probability of 1%, special symbol Z2 with a probability of 69%, and special symbol Z3 with a probability of 30% (see Figure 8 (c)).

At this time, if the special pattern Z1 is determined as the small win pattern, the time-saving game state ends with the end of the small win game, and as a result, the game state transitions to the most advantageous state.

In this way, the player transitions to the most advantageous state upon winning a specific small jackpot, which creates a constant sense of expectation and tension for the player, compared to a situation where the most advantageous state is reached only when the number of fluctuations reaches a specified number (100 times).

In addition, in the high probability premonition state, high probability time-saving state, and low probability time-saving state, there is a probability of about 1 in 3.45 of winning a small jackpot. Therefore, in the high probability premonition state, high probability time-saving state, and low probability time-saving state, small jackpot play is frequently executed, just like in the most advantageous state. However, in the high probability premonition state, high probability time-saving state, and low probability time-saving state, the normal play state is a time-saving play state. Also, as will be described in detail later, the normal play state is maintained in the time-saving play state even during a small jackpot play. Therefore, although the second large prize winning port 128 is opened during a small jackpot play, the first variable start port 120B is also opened during this time.

As described above, the first variable start port 120B is located above the second large winning port 128, and in the time-saving game state, the opening time of the first variable start port 120B is much longer than the opening time of the second large winning port 128. Therefore, in the high probability premonition state, high probability time-saving state, and low probability time-saving state, most of the game balls flowing down the second game area 116b enter the first variable start port 120B, and almost no game balls enter the second large winning port 128. As a result, in the high probability premonition state, high probability time-saving state, and low probability time-saving state, unlike the most advantageous state, the game balls will gradually decrease even if a right hit is made during play.

As described above, when the game progresses according to the actual variable object in accordance with the original gameplay, if a jackpot is won, the game state after the big win is set to either a low-probability time-saving state, a high-probability time-saving state, or a high-probability premonition state. The high-probability time-saving state and the high-probability premonition state have in common that the special game state is a high-probability game state, and the normal game state is a time-saving game state. On the other hand, the high-probability time-saving state continues until the next jackpot is won, whereas the high-probability premonition state differs in that the game state transitions to the most advantageous state when a specific small jackpot (special pattern Z1) is won or the time-saving state ends.

Also, in the high-probability time-saving state, the fluctuation time for small wins and misses is set to 1 second, whereas in the high-probability premonition state, the fluctuation time for small wins and misses is set within the range of 3 to 10 seconds (see Figure 13 (b)). In other words, the average fluctuation time in the high-probability time-saving state is set shorter than the average fluctuation time in the high-probability premonition state.

Therefore, in the high probability time-saving state, the time of change during small wins and misses is relatively short, so that the actual change target can be consumed at high speed until a big win is won. Although detailed explanation is omitted, during the change time of the special pattern, the change display of the performance patterns 210a, 210b, and 210c is performed on the sub-control board 330. In the high probability time-saving state, the change display of the performance patterns 210a, 210b, and 210c also becomes relatively short. Therefore, in the high probability time-saving state, as long as the special 1 reservation continues to be stored, the special 1 reservation (the change display of the performance patterns 210a, 210b, and 210c) continues to be consumed at high speed, so that the time until a big win can be shortened, and the player can play until the next big win without feeling (reducing) stress.

On the other hand, in the high probability premonition state, the fluctuation time during small wins and misses is relatively long, but the sub-control board 330 performs a presentation to see whether or not the most advantageous state will be entered. Therefore, the player can play while hoping that the most advantageous state will be entered.

In this way, in the high-probability time-saving state, even if a specific small jackpot (special pattern Z1) is won, there will be no transition to the most advantageous state, but by setting the average fluctuation time to a short value, the time until the next big jackpot is won can be shortened, reducing stress for the player. Also, in the high-probability precursor state, the average fluctuation time is set to be longer than in the high-probability time-saving state, but during that fluctuation time, it is possible to perform a presentation as to whether or not the most advantageous state will be entered, creating a sense of expectation and tension for the player.

As described above, a high-probability time-saving state and a high-probability precursor state are provided, which have in common that the special game state is a high-probability game state and the normal game state is a time-saving game state, and by making the average fluctuation time of the high-probability time-saving state shorter than the average fluctuation time of the high-probability precursor state, new gameplay can be provided.

Figure 20 is a diagram explaining the transition of the game state when the game is not played properly in the simultaneous spin reference example. As described above, in the gaming machine 100, the display of the changing patterns on the first special pattern display 160 and the display of the changing patterns on the second special pattern display 162 are performed simultaneously in parallel. At this time, if a large role lottery is performed based on a reservation other than the actual change target, and there is a possibility that the player may suffer a disadvantage as a result, the change time is set to a long time such as 10 minutes. However, after a large role lottery is performed based on a reservation other than the actual change target, for example, if the game is interrupted, a large win based on a reservation other than the actual change target may be confirmed. In this case, the game state will transition as shown in Figure 20.

The main processing of the main control board 300 to achieve the above gameplay characteristics is explained below.

Figure 21 is a diagram explaining the gaming machine status flag for the simultaneous spin reference example. In the main control board 300, the gaming machine status flag manages whether or not the game can proceed. The gaming machine status flag is set to one of six flag values from 00H to 05H. A flag value of 00H for the gaming machine status flag indicates a playable state. When the gaming machine status flag is 00H, the game is controlled to proceed, and when the gaming machine status flag is other than 00H, the game is stopped.

The flag value of the gaming machine status flag = 01H indicates a setting change state, and when the gaming machine status flag is 01H, the registered setting value can be changed. The flag value of the gaming machine status flag = 02H indicates a setting confirmation state, and when the gaming machine status flag is 02H, the registered setting value can be confirmed by displaying it on the performance display monitor 184, for example. The flag value of the gaming machine status flag = 03H indicates a setting abnormal state, and when the gaming machine status flag is 03H, the registered setting value is considered abnormal and play is stopped. The flag value of the gaming machine status flag = 04H indicates a RAM abnormal state, and when the gaming machine status flag is 04H, play is stopped. The flag value of the gaming machine status flag = 05H indicates a checksum abnormal state, and when the gaming machine status flag is 05H, play is stopped. When the power is turned on, the gaming machine status flag is set to one of the flag values, and processing according to the gaming machine status flag is performed.

(CPU Initialization Processing of Main Control Board 300)
FIG. 22 is a first flowchart explaining the CPU initialization processing in the main control board 300 relating to the simultaneous rotation reference example, and FIG. 23 is a second flowchart explaining the CPU initialization processing in the main control board 300 relating to the simultaneous rotation reference example.

When power is supplied from the power supply board, a system reset occurs in the main CPU 300a, and the main CPU 300a performs the following CPU initialization process (S100).

(Step S100-1)
When the power is turned on, the main CPU 300a reads a startup program from the main ROM 300b as an initial setting process, and also performs setting processes required for executing various processes.

(Step S100-3)
The main CPU 300a sets a wait processing time in a timer counter.

(Step S100-5)
The main CPU 300a judges whether a power-off warning signal has been detected. The main control board 300 is provided with a power-off detection circuit, which outputs a power-off warning signal when the power supply voltage falls below a predetermined value. If a power-off warning signal has been detected, the process proceeds to step S100-3, and if a power-off warning signal has not been detected, the process proceeds to step S100-7.

(Step S100-7)
The main CPU 300a judges whether the wait time set in step S100-3 has elapsed or not. If it is judged that the wait time has elapsed, the process proceeds to step S100-9, and if it is judged that the wait time has not elapsed, the process proceeds to step S100-5.

(Step S100-9)
The main CPU 300a executes the processes required to permit access to the main RAM 300c.

(Step S100-11)
The main CPU 300a loads the flag value of the gaming machine status flag before the power is turned off into the D register.

(Step S100-13)
The main CPU 300a calculates the checksum and determines whether the calculated checksum matches the checksum saved when the power was turned off (is normal) and whether the backup flag is normal. If it is determined that the backup flag and the checksum are normal, the process proceeds to step S100-15, and if it is determined that either one or both are not normal, the process proceeds to step S100-25.

(Step S100-15)
The main CPU 300a sets an address that does not include a setting value or a gaming machine status flag as the first address to be cleared in the main RAM 300c.

(Step S100-17)
The main CPU 300a judges whether a RAM clear operation signal has been input from the RAM clear switch 182s (whether the RAM clear button has been pressed down). If it is judged that a RAM clear operation signal has been input, the process proceeds to step S100-31, and if it is judged that a RAM clear operation signal has not been input, the process proceeds to step S100-19.

(Step S100-19)
The main CPU 300a judges whether the flag value of the gaming machine status flag loaded in step S100-11 is 00H (playable state), the setting change switch 180s is on, and the middle frame 104 is open. If it is judged that all three conditions are met, the process proceeds to step S100-21, and if it is judged that any one of the three conditions is not met, the process proceeds to step S100-23.

(Step S100-21)
The main CPU 300a sets the gaming machine status flag to 02H (setting confirmation status). That is, when the power is normally turned on in a state where the middle frame 104 is open, the setting change switch 180s is on, and the RAM clear button is not pressed, the gaming machine enters the setting confirmation status.

(Step S100-23)
The main CPU 300a executes an initialization process to clear the areas of the main RAM 300c subsequent to the top address set in step S100-15 that are to be cleared when the power is restored, and then proceeds to step S100-49.

(Step S100-25)
The main CPU 300a sets 05H (checksum abnormal state) in the D register.

(Step S100-27)
The main CPU 300a performs an outside area read/write check process for checking and clearing the read/write memory in the unused area.

(Step S100-29)
The main CPU 300a sets an address including a setting value and a gaming machine status flag as the first address to be cleared in the main RAM 300c.

(Step S100-31)
The main CPU 300a checks and clears the read/write memory of the used area.

(Step S100-33)
The main CPU 300a judges whether the check result of the read/write memory in the above step S100-31 is normal or not. If it is judged as normal, the process proceeds to step S100-37, and if it is judged as not normal, the process proceeds to step S100-35.

(Step S100-35)
The main CPU 300a sets 04H (RAM abnormal state) in the D register, and moves the process to step S100-45.

(Step S100-37)
The main CPU 300a judges whether 02H (setting confirmation state) is set in the D register. If it is judged that 02H is set, the process proceeds to step S100-39, and if it is judged that 02H is not set, the process proceeds to step S100-41.

(Step S100-39)
The main CPU 300a sets the D register to 00H (playable state).

(Step S100-41)
The main CPU 300a judges whether the setting change conditions are satisfied. If it is judged that the setting change conditions are satisfied, the process proceeds to step S100-43, and if it is judged that the setting change conditions are not satisfied, the process proceeds to step S100-45. Note that the setting change conditions here include at least that the setting change switch 180s is turned on, that the middle frame 104 is open, and that a RAM clear operation signal is input from the RAM clear switch 182s.

(Step S100-43)
The main CPU 300a sets the D register to 01H (setting changed state).

(Step S100-45)
The main CPU 300a saves the value set in the D register in the gaming machine status flag.

(Step S100-47)
The main CPU 300a executes an initialization process for clearing the items in the main RAM 300c that are to be cleared when the RAM is cleared, and moves the process to step S100-49.

(Step S100-49)
The main CPU 300a performs a transmission process (storing the RAM clear designation command in a transmission buffer) of a payout command (RAM clear designation command) to inform the payout control board 310 that the main RAM 300c has been cleared.

(Step S100-51)
The main CPU 300a loads the gaming machine status flag.

(Step S100-53)
The main CPU 300a judges whether the gaming machine status flag loaded in step S100-51 is 00H (playable state). If it is judged to be 00H, the process proceeds to step S110, and if it is judged not to be 00H, the process proceeds to step S100-55.

(Step S110)
The main CPU 300a performs a sub-command group set process, which will be described later.

(Step S100-55)
The main CPU 300 a performs a sub-command group set process for transmitting a predetermined command to the sub-control board 330 .

(Step S100-57)
The main CPU 300a sets the timer interrupt period.

(Step S100-59)
The main CPU 300a performs processing to disable interrupts.

(Step S100-61)
The main CPU 300a updates the initial value update random number for the winning symbol random number. The initial value update random number for the winning symbol random number is for determining the initial value and the end value of the winning symbol random number. In other words, when the winning symbol random number goes through one cycle from the initial value update random number for the winning symbol random number to the initial value update random number for the winning symbol random number - 1 by the updating process of the winning symbol random number described later, the winning symbol random number is updated to the initial value update random number for the winning symbol random number at that time.

(Step S100-63)
The main CPU 300a analyzes the received data (main commands) received from the payout control board 310 and executes various processes according to the received data.

(Step S100-65)
The main CPU 300 a performs processing to transmit the sub-commands stored in the transmission buffer to the sub-control board 330 .

(Step S100-67)
The main CPU 300a performs processing to permit an interrupt.

(Step S100-69)
The main CPU 300a updates the reach group determination random number, the reach mode determination random number, and the change pattern random number, and thereafter repeats the process from step S100-59. Note that, hereinafter, the reach group determination random number, the reach mode determination random number, and the change pattern random number for determining the change presentation pattern are collectively referred to as the change presentation random number.

Figure 24 is a flowchart explaining the sub-command group set process (S110) in the main control board 300 in the simultaneous rotation reference example.

(Step S110-1)
The main CPU 300a loads the flag value of the gaming machine status flag.

(Step S110-3)
The main CPU 300 a performs a sub-command group setting process for transmitting a predetermined command to the sub-control board 330 .

(Step S110-5)
The main CPU 300a performs a model command setting process to set a model command indicating model information of the gaming machine 100 in a transmission buffer.

(Step S110-7)
The main CPU 300a performs a setting value designation command setting process for setting a setting value designation command indicating a registered setting value in a transmission buffer.

(Step S110-9)
The main CPU 300a performs a special chart 1 reservation designation command setting process that sets a special chart 1 reservation designation command indicating the special chart 1 reservation number in a transmission buffer.

(Step S110-11)
The main CPU 300a performs a special chart 2 reservation designation command setting process that sets a special chart 2 reservation designation command indicating the special chart 2 reservation number in a transmission buffer.

(Step S110-13)
The main CPU 300a performs a count command setting process for setting a count command indicating the remaining number of times in the time-shortened gaming state in a transmission buffer.

(Step S110-15)
The main CPU 300a performs a variation pattern selection state designation command setting process that sets a variation pattern selection state designation command indicating the variation pattern selection state in a transmission buffer.

(Step S110-17)
The main CPU 300a performs a special game phase designation command setting process for setting a special game phase designation command indicating a special game management phase in a transmission buffer. The special game management phase will be described later.

(Step S110-19)
The main CPU 300a judges whether the special game management phase is in a special symbol change waiting state. If it is judged that the special symbol change waiting state is in effect, the process proceeds to step S110-21, and if it is judged that the special symbol change waiting state is not in effect, the sub-command group set process is terminated.

(Step S110-21)
The main CPU 300a sets the customer waiting designation command in the transmission buffer, and ends the sub-command group setting process.

Next, we will explain the interrupt processing in the main control board 300. Here, we will explain the power-off evacuation processing (XINT interrupt processing) and timer interrupt processing.

(Power off save process of main control board 300 (XINT interrupt process))
25 is a flow chart for explaining the power-off save process (XINT interrupt process) in the main control board 300 according to the simultaneous rotation reference example. The main CPU 300a monitors the power-off detection circuit, and when the power supply voltage falls below a predetermined value, it interrupts the CPU initialization process and executes the power-off save process.

(Step S300-1)
When the power-off warning signal is input, the main CPU 300a saves the registers.

(Step S300-3)
The main CPU 300a checks the power-off warning signal.

(Step S300-5)
The main CPU 300a judges whether a power-off warning signal has been detected. If it is judged that a power-off warning signal has been detected, the process proceeds to step S300-11. If it is judged that a power-off warning signal has not been detected, the process proceeds to step S300-7.

(Step S300-7)
The main CPU 300a restores the register.

(Step S300-9)
The main CPU 300a performs processing to permit an interrupt, and ends the power-off save processing.

(Step S300-11)
The main CPU 300a executes an output port clear process to stop the output of the output port.

(Step S300-13)
The main CPU 300a executes a checksum setting process that calculates and stores a checksum.

(Step S300-15)
The main CPU 300a executes a RAM protect setting process required to prohibit access to the main RAM 300c.

(Step S300-17)
In order to set the power interruption occurrence monitoring time, the main CPU 300a sets the counter value of a loop counter to a predetermined number of times the power interruption detection signal has been detected.

(Step S300-19)
The main CPU 300a checks the power-off warning signal.

(Step S300-21)
The main CPU 300a judges whether a power-off warning signal has been detected. If it is judged that a power-off warning signal has been detected, the process proceeds to step S300-17. If it is judged that a power-off warning signal has not been detected, the process proceeds to step S300-23.

(Step S300-23)
The main CPU 300a subtracts 1 from the value of the loop counter set in step S300-17.

(Step S300-25)
The main CPU 300a judges whether the counter value of the loop counter is 0. If it is judged that the counter value is not 0, the process proceeds to step S300-19, and if it is judged that the counter value is 0, the process proceeds to the above-mentioned CPU initialization process (step S100).

If a power outage actually occurs, operation of the gaming machine 100 will stop while steps S300-17 to S300-25 are looping.

(Timer interrupt processing of main control board 300)
26 is a flow chart for explaining the timer interrupt process in the main control board 300 according to the simultaneous rotation reference example. The main control board 300 is provided with a reset clock pulse generating circuit that generates a clock pulse every predetermined period (4 milliseconds in the simultaneous rotation reference example, hereinafter referred to as "4 ms"). When a clock pulse is generated by the reset clock pulse generating circuit, the CPU initialization process (step S100) is interrupted and the following timer interrupt process is executed.

(Step S400-1)
The main CPU 300a saves the registers.

(Step S400-3)
The main CPU 300a performs processing to permit an interrupt.

(Step S400-5)
The main CPU 300a outputs the common data set in the common output buffer to the output port, and executes dynamic port output processing which controls the lighting of the first special pattern display 160, the second special pattern display 162, the first special pattern reserved indicator 164, the second special pattern reserved indicator 166, the normal pattern display 168, the normal pattern reserved indicator 170, the right hit notification indicator 172, and the performance display monitor 184.

(Step S400-7)
The main CPU 300a reads various types of input port information and executes a port input process to accurately obtain the latest switch states.

(Step S400-9)
The main CPU 300a loads the flag value of the gaming machine status flag.

(Step S400-11)
The main CPU 300a judges whether the flag value loaded in step S400-9 is 00H (playable state). If it is judged to be 00H, the process proceeds to step S400-15, and if it is judged not to be 00H, the process proceeds to step S400-13.

(Step S400-13)
The main CPU 300a judges whether the flag value loaded in step S400-9 is equal to or greater than 03H (abnormal setting). If it is judged to be equal to or greater than 03H, the process proceeds to step S400-29. If it is judged to be equal to or greater than 03H, the process proceeds to step S450.

(Step S450)
The main CPU 300a executes a setting-related process, and moves the process to step S400-29. The setting-related process will be described later.

(Step S400-15)
The main CPU 300a performs a timer update process to update various timer counters. Here, unless otherwise specified, the timer counters are decremented every time the timer interrupt process of the main control board 300 is performed, and the decrement stops when the timer counters reach 0.

(Step S400-17)
The main CPU 300a executes an update process for the initial value update random number for the winning symbol random number, similar to step S100-61 described above.

(Step S400-19)
The main CPU 300a performs a process of updating the winning symbol random number. Specifically, the random number counter is updated by adding 1, and if the result of the addition exceeds the maximum value of the random number range, the random number counter is reset to 0, and if the random number counter has completed one cycle, the random number is updated from the value of the initial value update random number for the winning symbol random number at that time.

Although a detailed explanation will be omitted, in the simultaneous spin reference example, the jackpot determination random number and the win determination random number use hardware random numbers updated by a hardware random number generation unit built into the main control board 300. The hardware random number generation unit updates both the jackpot determination random number and the win determination random number according to certain rules, automatically changing the random number sequence each time the random number sequence goes through one cycle, and changing the start value each time the system is reset.

(Step S500)
The main CPU 300a executes a switch management process to determine whether or not a signal has been input from the first fixed start hole detection switch 120As, the first variable start hole detection switch 120Bs, the second start hole detection switch 122s, the gate detection switch 124s, the normal operation hole detection switch 125s, the first large prize hole detection switch 126s, and the second large prize hole detection switch 128s. Details of this switch management process will be described later.

(Step S600)
The main CPU 300a executes a special game management process for controlling the progress of the variable display of the special symbols based on the special 2 reservation in the special game. The details of this special game management process will be described later.

(Step S600)
The main CPU 300a executes a special game management process for controlling the progress of the variable display of the special symbol based on the special 1 reservation in the special game. Here, the same program (module) as the special game management process for controlling the progress of the variable display of the special symbol based on the special 2 reservation is read out, and the special game management process for controlling the progress of the variable display of the special symbol based on the special 1 reservation is executed.

(Step S700)
The main CPU 300a executes a special electric accessory game management process for controlling the progress of the big prize game and the small prize game in the special game. The details of this special electric accessory game management process will be described later.

(Step S800)
The main CPU 300a executes a normal game management process for controlling the progress of the normal game. The details of this normal game management process will be described later.

(Step S400-21)
The main CPU 300a executes an error management process for determining various errors and making settings according to the error determination results.

(Step S400-23)
The main CPU 300a checks the general prize hole detection switch 118s, the first start hole detection switch 120s, the second start hole detection switch 122s, the first large prize hole detection switch 126s, and the second large prize hole detection switch 128s, and executes prize hole switch processing to increment the corresponding counters for prize ball control, etc.

(Step S400-25)
The main CPU 300a executes a payout control management process to create and transmit a payout command based on the counter value of the counter for controlling the winning balls set in the above step S400-23.

(Step S400-27)
The main CPU 300a executes a launch position designation management process for transmitting a launch position designation command to the sub-control board 330, which designates the launch position of the game ball, i.e., whether the game ball is to be launched into the first game area 116a or the second game area 116b.

(Step S400-29)
The main CPU 300a executes an external information management process for setting output data for external information to be output from the game information output terminal board 312 to the outside.

(Step S400-31)
The main CPU 300a executes an LED display setting process which sets display data for controlling the lighting of various indicators (LEDs), such as the first special pattern display 160, the second special pattern display 162, the first special pattern reserved indicator 164, the second special pattern reserved indicator 166, the normal pattern display 168, the normal pattern reserved indicator 170, and the right hit notification indicator 172, in an output buffer corresponding to each common.

(Step S400-33)
The main CPU 300a executes a solenoid output image synthesis process to synthesize the solenoid output images of the normal electric role solenoid 120c, the first large prize opening solenoid 126c, and the second large prize opening solenoid 128c, and store them in an output port buffer.

(Step S400-35)
The main CPU 300a executes a port output process for outputting the values of the common output buffers stored in the respective output port buffers to the output ports.

(Step S400-37)
The main CPU 300a performs processing to disable interrupts.

(Step S400-39)
The main CPU 300a uses the unused area of the main RAM 300c to perform processing for calculating a base ratio to be displayed on the performance display monitor 184, and executes a performance display monitor control processing for setting common data for displaying the calculated base ratio on the performance display monitor 184 in a common output buffer. In the performance display monitor control processing, the base ratio is calculated for each predetermined period. Here, the performance display monitor 184 may switch between displaying the base ratio for the current period and the base ratio for the previous period at predetermined time intervals. Also, the base ratio displayed on the performance display monitor 184 may be switched in response to a predetermined operation.

(Step S400-41)
The main CPU 300a restores the registers and ends the timer interrupt process.

Figure 27 is a flowchart explaining the setting-related process (S450) for the simultaneous rotation reference example.

(Step S450-1)
The main CPU 300a judges whether the flag value of the gaming machine state flag is 01H (setting change state). If it is judged to be 01H, the process proceeds to step S450-3, and if it is judged not to be 01H, the process proceeds to step S450-15.

(Step S450-3)
The main CPU 300a loads the registered setting values stored in the setting value buffer into a predetermined processing area.

(Step S450-5)
The main CPU 300a judges whether the RAM clear switch 182s has been pressed (whether a RAM clear operation signal has been input). If it is judged that the RAM clear switch 182s has been pressed, the process proceeds to step S450-7, and if it is judged that the RAM clear switch 182s has not been pressed, the process proceeds to step S450-9.

(Step S450-7)
The main CPU 300a adds 1 to the setting value of the processing area.

(Step S450-9)
The main CPU 300a judges whether the setting value of the processing area is in the range of 1 to 6. As a result, if it is judged that the setting value is in the range of 1 to 6, the process proceeds to step S450-13, and if it is judged that the setting value is not in the range of 1 to 6, the process proceeds to step S450-11.

(Step S450-11)
The main CPU 300a sets the setting value of the processing area to 1.

(Step S450-13)
The main CPU 300a sets the setting value of the processing area in the setting value buffer.

(Step S450-15)
The main CPU 300a judges whether the setting change switch 180s is on. If it is judged that the setting change switch 180s is on, the setting-related process is terminated, and if it is judged that the setting change switch 180s is not on, the process proceeds to step S450-17.

(Step S450-17)
The main CPU 300a sets a setting-related end designation command, which indicates the end of the setting-related processing, in the transmission buffer.

(Step S110)
The main CPU 300a executes the sub-command group set process of Fig. 24. That is, when the setting related process is executed, at the end of the process, the model command, the setting value designation command, the special chart 1 reservation designation command, the special chart 2 reservation designation command, the number of times command, the variation pattern selection state designation command, the special chart phase designation command, and the customer waiting designation command are transmitted to the sub-control board 330.

(Step S450-19)
The main CPU 300a sets the gaming machine state flag to 00H (playable state), and ends the setting-related processing.

As described above, according to the simultaneous rotation reference example, when the power is turned on normally with the middle frame 104 open, the setting change switch 180s on, and the RAM clear button pressed, the gaming machine status flag is set to 01H (setting change state) in the CPU initialization process (Figure 22). After that, the timer interrupt process is executed, but because the gaming machine status flag is set to 01H (setting change state), all processes related to the progress of the game (steps S400-15 to S400-27 in Figure 26) are stopped, and setting-related processes are executed.

The setting-related process is executed repeatedly while the setting change switch 180s is on, and during this setting-related process, pressing the RAM clear button is accepted as a setting change operation for the registered setting value. In other words, during the setting change process (S450-1 to S450-13) that accepts setting change operations, the registered setting value stored in the setting value buffer is switched to one of multiple setting values in response to the setting change operation.

When the setting change switch 180s is switched off while the gaming machine status flag is set to 01H (setting change state), the setting change process ends and the gaming machine status flag is set to 00H (playable state). This makes it possible to execute processes related to the progress of the game, starting with the next timer interrupt process.

Here, in the setting-related processing of the simultaneous rotation reference example, after the RAM clear button is pressed, i.e., after the acceptance of the setting change operation of the registered setting value has ended, a setting value designation command corresponding to the registered setting value is sent to the sub-control board 330 in the sub-command group set processing. On the other hand, while the setting change operation is being accepted, the setting value designation command is not sent to the sub-control board 330. In this way, while the setting change operation is being accepted, the setting value designation command is not sent, and when the acceptance of the setting change operation has ended and the game transitions to a state in which it is possible to proceed, the setting value designation command is sent, thereby reducing the risk of the registered setting value being obtained illegally.

In addition, in the simultaneous rotation reference example, multiple flag values including at least 01H (setting change state) are switched. Then, when the gaming machine state flag is set to 01H (setting change state), setting-related processing can be executed, and the progress of the game is stopped. In this way, since setting-related processing is not executed while the game is in progress, setting value designation commands are not sent while the game is in progress, and the risk of registered setting values being illegally obtained is reduced.

Next, among the timer interrupt processes described above, the switch management process in step S500, the special game management process in step S600, the special electric role game game management process in step S700, and the regular game management process in step S800 will be described in detail.

Figure 28 is a flowchart explaining the switch management process (step S500) in the main control board 300 in the simultaneous rotation reference example.

(Step S500-1)
The main CPU 300a judges whether the gate detection switch is ON, that is, whether the game ball has passed through the gate 124 and the detection signal from the gate detection switch 124s has been turned ON. If it is judged that the gate detection switch is ON, the process proceeds to step S510, and if it is judged that the gate detection switch is not ON, the process proceeds to step S500-7.

(Step S510)
The main CPU 300a executes a gate passing process based on the passage of the gaming ball through the gate 124. The gate passing process will be described in detail later.

(Step S500-3)
The main CPU 300a judges whether the normal operation port detection switch is ON, that is, whether a game ball has entered the normal operation port 125 and the detection signal from the normal operation port detection switch 125s has been turned ON. If it is judged that the normal operation port detection switch is ON, the process proceeds to step S510, and if it is judged that the normal operation port detection switch is not ON, the process proceeds to step S500-5.

(Step S510)
The main CPU 300a executes gate passing processing based on the entry of a game ball into the normal operation port 125.

(Step S500-5)
The main CPU 300a judges whether the first fixed start hole detection switch is ON, that is, whether a game ball has entered the first fixed start hole 120A and a detection signal has been input from the first fixed start hole detection switch 120As. If it is judged that the first fixed start hole detection switch is ON, the process proceeds to step S520, and if it is judged that the first fixed start hole detection switch is not ON, the process proceeds to step S500-7.

(Step S520)
The main CPU 300a executes a first start hole passing process based on the entry of the game ball into the first fixed start hole 120A. The first start hole passing process will be described in detail later.

(Step S500-7)
The main CPU 300a judges whether the first variable start hole detection switch is ON, that is, whether a game ball has entered the first variable start hole 120B and a detection signal has been input from the first variable start hole detection switch 120Bs. If it is determined that the first variable start hole detection switch is ON, the process proceeds to step S520, and if it is determined that the first variable start hole detection switch is not ON, the process proceeds to step S500-11.

(Step S520)
The main CPU 300a executes a first start hole passing process based on the entry of the gaming ball into the first variable start hole 120B. The first start hole passing process will be described in detail later.

(Step S500-9)
The main CPU 300a determines whether the game ball has entered the first variable start opening 120B properly, and if it determines that the game ball has not entered properly, executes a normal electric device winning confirmation process to send a normal electric illegal winning error occurrence command to the sub-control board 330, indicating that the game ball has entered the first variable start opening 120B illegally.

(Step S500-11)
The main CPU 300a judges whether the second start hole detection switch is ON, that is, whether a game ball has entered the second start hole 122 and a detection signal has been input from the second start hole detection switch 122s. If it is determined that the second start hole detection switch is ON, the process proceeds to step S530, and if it is determined that the second start hole detection switch is not ON, the process proceeds to step S500-13.

(Step S530)
The main CPU 300a executes a second start hole passing process based on the entry of the gaming ball into the second start hole 122. The second start hole passing process will be described in detail later.

(Step S500-13)
The main CPU 300a judges whether the time has come when the large prize opening detection switch is detected as being on, that is, whether a game ball has entered the first large prize opening 126 or the second large prize opening 128 and a detection signal has been input from the first large prize opening detection switch 126s or the second large prize opening detection switch 128s. If it is determined that the time has come when the large prize opening detection switch is detected as being on, the process proceeds to step S540, and if it is determined that the time has not come when the large prize opening detection switch is detected as being on, the switch management process is terminated.

(Step S540)
The main CPU 300a judges whether the game ball has entered the first large prize opening 126 or the second large prize opening 128 properly, and if it judges that the game ball has entered properly, it executes a large prize opening passing process for transmitting a large prize opening entry command, which indicates that the game ball has entered the first large prize opening 126 or the second large prize opening 128, to the sub-control board 330. The details of this large prize opening passing process will be described later.

Figure 29 is a flowchart explaining the gate passage process (step S510) in the main control board 300 in the simultaneous rotation reference example.

(Step S510-1)
The main CPU 300a loads the winning determination random number updated by the hardware random number generator.

(Step S510-3)
The main CPU 300a judges whether the counter value of the normal pattern reserved ball counter is equal to or greater than the maximum value, that is, whether the counter value of the normal pattern reserved ball counter is equal to or greater than 4. If it is judged that the counter value of the normal pattern reserved ball counter is equal to or greater than the maximum value, the gate passing process is terminated, and if it is judged that the normal pattern reserved ball counter is not equal to or greater than the maximum value, the process proceeds to step S510-5.

(Step S510-5)
The main CPU 300a updates the counter value of the normal symbol reserved ball count counter to a value obtained by adding "1" to the current counter value.

(Step S510-7)
The main CPU 300a determines which of the four memory sections in the general reserve memory area is to be the target memory section in which to save the acquired winning determination random number.

(Step S510-9)
The main CPU 300a saves the winning determination random number obtained in the above step S510-1 in the target memory calculated in the above step S510-7.

(Step S510-11)
The main CPU 300a sets a regular map reservation designation command indicating the number of regular map reservations stored in the regular map reservation memory area in the transmission buffer, and terminates the gate passing process.

Figure 30 is a flow chart explaining the first starting port passing process (step S520) in the main control board 300 in the simultaneous rotation reference example.

(Step S520-1)
The main CPU 300a sets "00H" as the special symbol identification value. The special symbol identification value is used to identify whether the reserved type is special 1 reserved or special 2 reserved, and the special symbol identification value (00H) indicates special 1 reserved, and the special symbol identification value (01H) indicates special 2 reserved.

(Step S520-3)
The main CPU 300a sets the address of the reserved ball count counter for special pattern 1.

(Step S535)
The main CPU 300a executes the special symbol random number acquisition process and ends the first start hole passing process. This special symbol random number acquisition process is executed using a module common to the second start hole passing process (step S530). Therefore, the details of the special symbol random number acquisition process will be explained after the explanation of the second start hole passing process.

Figure 31 is a flow chart explaining the second starting port passing process (step S530) in the main control board 300 in the simultaneous rotation reference example.

(Step S530-1)
The main CPU 300a sets "01H" as the special symbol identification value.

(Step S530-3)
The main CPU 300a sets the address of the special pattern 2 reserved ball count counter.

(Step S535)
The main CPU 300a executes the special pattern random number acquisition process described later, and ends the second starting port passing process.

Figure 32 is a flow chart explaining the special symbol random number acquisition process (step S535) in the main control board 300 relating to the simultaneous rotation reference example. This special symbol random number acquisition process is executed using a common module in the first start port passing process (step S520) and the second start port passing process (step S530) described above.

(Step S535-1)
The main CPU 300a loads the special symbol identification value set in step S520-1 or step S530-1.

(Step S535-3)
The main CPU 300a loads the number of reserved balls for the target special symbol. Here, if the special symbol identification value loaded in the above step S535-1 is "00H", the counter value of the reserved ball counter for the special symbol 1, i.e., the reserved number for special 1, is loaded. Also, if the special symbol identification value loaded in the above step S535-1 is "01H", the counter value of the reserved ball counter for the special symbol 2, i.e., the reserved number for special 2, is loaded.

(Step S535-5)
The main CPU 300a loads the jackpot determination random number updated by the hardware random number generating unit.

(Step S535-7)
The main CPU 300a judges whether the number of reserved balls for the target special symbol loaded in step S535-3 is equal to or greater than the upper limit. If it is judged to be equal to or greater than the upper limit, the main CPU 300a ends the special symbol random number acquisition process. If it is judged to be equal to or greater than the upper limit, the process proceeds to step S535-9.

(Step S535-9)
The main CPU 300a updates the counter value of the target special pattern reserved ball count counter to a value obtained by adding "1" to the current counter value.

(Step S535-11)
The main CPU 300a calculates the target memory section among the memory sections of the special chart reserved memory area into which the acquired jackpot determination random number is to be saved.

(Step S535-13)
The main CPU 300a obtains the jackpot determination random number loaded in step S535-5, the winning symbol random number updated in step S400-19, and the variation pattern random number updated in step S100-69, and stores them in the target memory section calculated in step S535-11.

(Step S535-15)
The main CPU 300a loads the counter values of the special pattern 1 reserved ball count counter and the special pattern 2 reserved ball count counter.

(Step S535-17)
The main CPU 300a sets the special reserved command in the transmission buffer based on the counter value loaded in step S535-15. Here, the special reserved command is set based on the counter value (special reserved number of special 1) of the special reserved ball number counter, and the special reserved command is set based on the counter value (special reserved number of special 2) of the special reserved ball number counter. As a result, the special reserved number of special 1 and the special reserved number of special 2 are transmitted to the sub-control board 330 every time the special reserved number of special 1 or special reserved number of special 2 is stored.

(Step S536)
The main CPU 300a performs the acquisition time performance determination process and ends the special symbol random number acquisition process. In this acquisition time performance determination process, the result of the big role lottery and the variable pattern number are provisionally determined, and a pre-reading designation command according to the provisional determination result is transmitted to the sub-control board 330. This acquisition time performance determination process will be described with reference to FIG.

Figure 33 is a flowchart explaining the performance determination process (step S536) at the time of acquisition in the main control board 300 in the simultaneous rotation reference example.

(Step S536-1)
The main CPU 300a selects a corresponding jackpot determination random number judgment table based on the currently set value. Specifically, the main CPU 300a selects a corresponding jackpot determination random number judgment table based on the current game state and the currently set value. Then, the main CPU 300a performs a provisional special symbol win judgment process to provisionally judge whether the winning combination is a jackpot, a small win, or a miss, based on the selected table and the jackpot determination random number stored in the target memory unit in step S535-13.

(Step S536-3)
The main CPU 300a executes a special symbol provisional determination process for provisionally determining a special symbol. Here, if the result of the provisional big role lottery in the above step S536-1 (the result derived by the special symbol provisional win determination process) is a big win or a small win, the winning symbol random number, the winning type (whether it is a big win or a small win), and the reserved type stored in the target memory in the above step S535-13 are loaded, the corresponding winning symbol random number determination table is selected to extract the special symbol determination data, and the extracted special symbol determination data (type of big win symbol or small win symbol) is saved. Also, if the result of the provisional big role lottery in the above step S536-1 is a loss, a predetermined special symbol determination data for a loss (type of loss symbol) is saved.

(Step S536-5)
The main CPU 300a sets in the transmission buffer a look-ahead symbol type designation command (look-ahead designation command) corresponding to the special symbol determination data saved in step S536-3.

(Step S536-7)
The main CPU 300a judges whether the result derived by the special symbol winning provisional judgment process in the above step S536-1 is a big win or a small win. If it is judged to be a big win or a small win, the process proceeds to step S536-9, and if it is judged not to be a big win or a small win (miss), the process proceeds to step S536-11.

(Step S536-9)
The main CPU 300a sets the random number judgment table for determining the reach mode at the big win (see Figures 10(b) and (c)) or the random number judgment table for determining the reach mode at the small win (see Figures 10(d) and (e)), and transfers the process to step S536-19.

(Step S536-11)
The main CPU 300a loads the reach group determination random number stored in the target memory section in step S535-13.

(Step S536-13)
The main CPU 300a judges whether the reach group determination random number loaded in step S536-11 is a fixed value (9000 or more). Here, the group type is determined by referring to the reach group determination random number judgment table, and this reach group determination random number judgment table is selected according to the number of reserved items stored. At this time, the reach group determination random number is acquired from a range of 0 to 10006, and if the value of the reach group determination random number is 9000 or more, the same reach group determination random number judgment table is selected regardless of the number of reserved items, and if the value of the reach group determination random number is less than 9000, a different reach group determination random number judgment table is selected depending on the number of reserved items. Hereinafter, the value of the reach group determination random number in the range of 0 to 8999, where a different reach group determination random number judgment table is selected depending on the number of reserved items, is referred to as an indefinite value, and the value in the range of 9000 to 10006, where the same reach group determination random number judgment table is selected regardless of the number of reserved items, is referred to as a fixed value. If it is determined that the reach group determination random number loaded in step S536-11 above is a fixed value (9000 or more), processing is transferred to step S536-15, and if it is determined that the reach group determination random number loaded in step S536-11 above is not a fixed value (9000 or more), processing is transferred to step S536-27.

(Step S536-15)
The main CPU 300a sets a reach group determination random number judgment table (see FIG. 9). Note that, although there are multiple types of reach group determination random number judgment tables provided according to the reserved number, here, a table to be used when the reserved number is 0 is selected. Then, a reach group (group type) is provisionally determined based on the set reach group determination random number judgment table and the reach group determination random number stored in the target memory unit in step S535-13.

(Step S536-17)
The main CPU 300a sets the miss-time reach mode determination random number judgment table (see FIG. 10(a)) corresponding to the group type provisionally determined in step S536-15, and moves the process to step S536-19.

(Step S536-19)
The main CPU 300a provisionally determines a variation mode number based on the reach mode determination random number judgment table set in the above step S536-9 or step S536-17 and the reach mode determination random number stored in the target memory unit in the above step S535-13. Here, a variation pattern random number judgment table is provisionally determined together with the variation mode number.

(Step S536-21)
The main CPU 300a sets in the transmission buffer a read-ahead designation fluctuation mode command (read-ahead designation command) corresponding to the fluctuation mode number tentatively determined in step S536-19.

(Step S536-23)
The main CPU 300a provisionally determines a fluctuation pattern number based on the fluctuation pattern random number determination table provisionally determined in the above step S536-19 and the fluctuation pattern random number stored in the target memory unit in the above step S535-13.

(Step S536-25)
The main CPU 300a sets in the transmission buffer a look-ahead specified variable pattern command (look-ahead specification command) corresponding to the variable pattern number provisionally determined in step S536-23 above, and terminates the performance determination process at the time of acquisition.

(Step S536-27)
The main CPU 300a sets in the transmission buffer an indefinite value command (look-ahead specified variable mode command and look-ahead specified variable pattern command = 7FH) indicating that the group type, i.e., the variable presentation pattern, will change depending on the number of holds when the holds are read out for the holds newly stored in the target memory unit, and terminates the presentation determination process at the time of acquisition.

Figure 34 is a flowchart explaining the large prize opening passage process (step S540) in the main control board 300 in the simultaneous rotation reference example.

(Step S540-1)
When the main CPU 300a determines in step S500-13 that the big prize opening detection switch is ON, it loads a special electric accessory game management phase, which will be described later in detail. Note that, as will be described later in detail, the special electric accessory game management phase indicates the stage of the execution process of the big prize game or the small prize game, that is, the progress of the big prize game or the small prize game, and is updated according to the stage of the execution process of the big prize game or the small prize game.

(Step S540-3)
The main CPU 300a judges whether the special electric role game management phase loaded in the above step S540-1 indicates a stage of execution processing of the large prize opening pre-processing or higher. The special electric role game management phase has nine stages from 00H to 08H, of which 01H to 08H correspond to the stage of execution processing of the large prize opening pre-processing or higher. Since the large role game or the small prize game is executed when the special electric role game management phase is 01H to 08H, here, it is judged whether the large role game or the small prize game is currently being played. If it is judged that the special electric role game management phase indicates a stage of execution processing of the large prize opening pre-processing or higher, the process proceeds to step S540-5, and if it is judged that the special electric role game management phase does not indicate a stage of execution processing of the large prize opening pre-processing or higher, the process proceeds to step S540-7.

(Step S540-5)
The main CPU 300a sets a large prize opening ball entry command, indicating that the game ball has properly entered the first large prize opening 126 or the second large prize opening 128, in the transmission buffer, and ends the large prize opening passage process.

(Step S540-7)
The main CPU 300a determines that the entry of the game ball into the first large prize opening 126 or the second large prize opening 128 is inappropriate, executes a prescribed error process, and terminates the large prize opening passage process.

Figure 35 is a diagram explaining the special game management phase in the simultaneous spin reference example. As already explained, in the simultaneous spin reference example, a special game triggered by the entry of a game ball into the first start port 120 or the second start port 122, and a normal game triggered by the passage of a game ball through the gate 124 or the entry of a game ball into the normal operation port 125 proceed simultaneously in parallel. The processing related to the special game is executed stepwise and repeatedly, and the main control board 300 manages each processing related to such special games by the special game management phase and the special electric device game management phase.

As shown in FIG. 35, the main ROM 300b stores a number of special game control modules for controlling the execution of the display of changing special symbols in special games, and each of these special game control modules is associated with a special game management phase. Specifically, when the special game management phase is "00H", a module for executing "special symbol change waiting process" is called, when the special game management phase is "01H", a module for executing "special symbol changing process" is called, and when the special game management phase is "02H", a module for executing "special symbol stop symbol display process" is called.

In addition, the main ROM 300b stores a plurality of special electric role control modules for controlling the execution of the big prize game and the small prize game among the special games, and each of these special electric role control modules is associated with a special electric role game management phase. Specifically, when the special electric role game management phase is "01H" or "05H", a module for executing "large prize opening pre-processing" is called, when the special electric role game management phase is "02H" or "06H", a module for executing "large prize opening control processing" is called, when the special electric role game management phase is "03H" or "07H", a module for executing "large prize opening closing valid processing" is called, and when the special electric role game management phase is "04H" or "08H", a module for executing "large prize opening end wait processing" is called. In addition, when the special electric role play management phase is "00H", none of the special electric role play control modules are called.

Figure 36 is a flowchart explaining the special game management process (step S600) in the main control board 300 in the simultaneous rotation reference example.

(Step S600-1)
The main CPU 300a loads the special electric role play management phase.

(Step S600-3)
The main CPU 300a judges whether the special electric role game management phase loaded in the above step S600-1 is other than "00H". That is, here, it judges whether the big role game or the small role game is currently being played. If it is judged that the special electric role game management phase is other than "00H", the special game management process is terminated, and if it is judged that the special electric role game management phase is not other than "00H", the process proceeds to step S600-5.

(Step S600-5)
The main CPU 300a loads a special game special symbol determination flag. The special game special symbol determination flag is for determining whether the reserved type to be the target of the special game management process is special 1 reserved or special 2 reserved, and the special game special symbol determination flag (00H) indicates special 1 reserved, and the special game special symbol determination flag (01H) indicates special 2 reserved.

(Step S600-7)
The main CPU 300a inverts the special game special symbol determination flag loaded in the above step S600-5. Here, if the special game special symbol determination flag is "00H", it is inverted to "01H", and if the special game special symbol determination flag is "01H", it is inverted to "00H". Since the initial value of the special game special symbol determination flag is set to "00H", in the first special game management process S600 of the two special game management processes S600 shown in FIG. 26, the special game special symbol determination flag is set to "01H" and the subsequent process is executed for the special 2 reservation, and in the second special game management process S600, the special game special symbol determination flag is set to "00H" and the subsequent process is executed for the special 1 reservation. In other words, the special 2 reservation is processed preferentially.

(Step S600-9)
The main CPU 300a saves the special game special symbol determination flag that was inverted in step S600-7.

(Step S600-11)
The main CPU 300a loads the special game management phase.

(Step S600-13)
The main CPU 300a selects the special game control module corresponding to the special game management phase loaded in step S600-11.

(Step S600-15)
The main CPU 300a calls the special game control module selected in step S600-13 and starts processing.

(Step S600-17)
The main CPU 300a loads a special game timer that manages the control time of the special game, and ends the special game management process.

Figure 37 is a flowchart explaining the special symbol change waiting process in the main control board 300 in the simultaneous spin reference example. This special symbol change waiting process is executed when the special game management phase is "00H".

(Step S610-1)
The main CPU 300a judges whether the number of reserved balls with special symbols in the reserved balls (special 1 reserved or special 2 reserved, hereinafter referred to as the target reserved balls) that are the subject of the special game management process is 1 or more. If it is judged that the number of reserved balls with special symbols is 1 or more, the process proceeds to step S610-3, and if it is judged that the number of reserved balls with special symbols is not 1 or more, the process of waiting for the change of the special symbols is terminated.

(Step S610-3)
The main CPU 300a judges whether a special symbol (hereinafter referred to as a non-target special symbol) based on a reserve that is not the target of the special game management process (special reserve 2 or special reserve 1, hereinafter referred to as a non-target reserve) is being determined. If it is determined that a non-target special symbol is being determined, the process proceeds to step S610-5, and if it is determined that a special symbol based on a non-target special symbol is not being determined, the process proceeds to step S610-9.

(Step S610-5)
The main CPU 300a judges whether the non-target special symbol is a big win symbol. If it is judged to be a big win symbol, the process of waiting for the special symbol change is terminated. If it is judged not to be a big win symbol, the process proceeds to step S610-7.

(Step S610-7)
The main CPU 300a judges whether the non-target special symbol is a small win symbol. If it is judged to be a small win symbol, the main CPU 300a ends the special symbol variation waiting process, and if it is judged not to be a small win symbol, the process proceeds to step S610-9.

(Step S610-9)
The main CPU 300a transfers the target reservation stored in the first to fourth storage sections of the special symbol reservation storage area corresponding to the target reservation in a block to a storage section with a smaller ordinal number by one. Specifically, the target reservation stored in the second to fourth storage sections is transferred to the first to third storage sections. The main RAM 300c is also provided with a 0th storage section to be processed, and the target reservation stored in the 1st storage section is block transferred to the 0th storage section. In addition, in this special symbol storage area shift process, the counter value of the target special symbol reservation ball number counter corresponding to the target reservation is subtracted by "1", and a reservation subtraction designation command indicating that the target reservation has been subtracted by "1" is set in the transmission buffer.

(Step S611)
The main CPU 300a executes a special symbol winning determination process for performing a lottery for a big win. This special symbol winning determination process will be described later.

(Step S610-11)
The main CPU 300a executes a special symbol determination process to determine a special symbol. Here, if the result of the big role lottery in the step S611 is a big win or a small win, the winning symbol random number and reserved type transferred to the 0th memory unit are loaded, the corresponding winning symbol random number determination table or small win symbol random number determination table is selected to extract special symbol determination data, and the extracted special symbol determination data (type of big win symbol) is saved. Also, if the result of the big role lottery in the step S611 is a loss, the special symbol determination data for loss is saved. Then, after the special symbol determination data is saved, a symbol type designation command corresponding to the special symbol determination data is set in the transmission buffer.

(Step S610-13)
The main CPU 300a saves the special symbol stop symbol number corresponding to the special symbol determination data extracted in step S610-11. The first special symbol display 160 and the second special symbol display 162 are each composed of 7 segments, and each segment constituting the 7 segments is associated with a number (counter value). The special symbol stop symbol number determined here indicates the number (counter value) of the segment that will finally be lit up.

(Step S612)
The main CPU 300a executes a special symbol variable number determination process for determining a variable mode number and a variable pattern number. The details of this special symbol variable number determination process will be described later.

(Step S610-15)
The main CPU 300a loads the fluctuation mode number and the fluctuation pattern number determined in step S612, and refers to the fluctuation time determination table to determine the fluctuation time 1 and the fluctuation time 2. Then, the total time of the determined fluctuation times 1 and 2 is set in the special symbol fluctuation timer.

(Step S610-17)
The main CPU 300a judges whether the result of the big prize lottery is a big prize or not, and if it is a big prize, loads the special symbol judgment data saved in the above step S610-11 and checks the type of the big prize symbol. Then, referring to the game state setting table and the current game state, it judges the game state, the high probability number of times, and the time-saving number of times to be set after the big prize game ends, and saves the judgment results in the special symbol probability state reserve flag, the time-saving state reserve flag, the high probability number cut reserve counter, and the time-saving number cut reserve counter. Note that if a losing symbol is saved, the process proceeds to the next process without executing the process.

(Step S610-19)
The main CPU 300a executes a process of setting a special symbol display counter in order to start the variable display of the special symbol in the first special symbol display 160 or the second special symbol display 162. A counter value is associated with each segment of the 7-segment that constitutes the first special symbol display 160 and the second special symbol display 162, and the segment corresponding to the counter value set in the special symbol display counter is controlled to light up. Here, the counter value corresponding to the segment to be lit at the start of the variable display of the special symbol is set in the special symbol display counter. Note that the special symbol display counter is provided separately as a special symbol 1 display counter corresponding to the first special symbol display 160 and a special symbol 2 display counter corresponding to the second special symbol display 162, and here, a counter value is set in the counter corresponding to the reserved type.

(Step S613)
The main CPU 300a executes a number-of-plays management process. Here, a process for ending the time-limited gaming state according to the number of times of fluctuation is performed. This number-of-plays management process will be described later.

(Step S610-21)
The main CPU 300a sets in the transmission buffer a number command indicating the number of times remaining (actual remaining number of times) until the high probability number of times and the time-saving number of times reach 0.

(Step S610-23)
The main CPU 300a sets in the transmission buffer a game state change designation command indicating the game state at the start of the variable display of the special symbol.

(Step S610-25)
The main CPU 300a updates the special game management phase to "01H" and ends the special symbol change waiting process.

Figure 38 is a flowchart explaining the special symbol winning determination process (S611) for the simultaneous spin reference example.

(Step S611-1)
The main CPU 300a loads the special symbol probability state flag.

(Step S611-3)
The main CPU 300a loads the registered setting values in the setting value buffer.

(Step S611-5)
The main CPU 300a judges whether the registered setting value loaded in step S611-3 is within the normal range. If it is judged to be within the normal range, the process proceeds to step S611-11. If it is judged to be not within the normal range, the process proceeds to step S611-7.

(Step S611-7)
The main CPU 300a sets the gaming machine status flag to 03H (abnormal setting status).

(Step S611-9)
The main CPU 300a sets the setting abnormal state command (sub-command) in the transmission buffer and ends the special symbol winning determination process. When this setting abnormal state command is transmitted to the sub-control board 330, a notification that a setting abnormality has occurred is issued.

(Step S611-11)
The main CPU 300a refers to the big win determination random number judgment table corresponding to the information loaded in the above steps S611-1 and S611-3, and sets the lower and upper limits for determining whether a big win or a small win has occurred.

(Step S611-13)
The main CPU 300a compares the jackpot determination random number transferred to the 0th memory unit with the above-mentioned lower limit value and upper limit value, and performs a determination process (big prize lottery) to determine whether a jackpot or small jackpot has been won.

(Step S611-15)
The main CPU 300a judges whether the non-target special symbol is a big win symbol. If it is judged to be a big win symbol, the process proceeds to step S611-17. If it is judged not to be a big win symbol, the process proceeds to step S611-21.

(Step S611-17)
The main CPU 300a judges whether the result of the big role lottery in the step S611-13 is a small win or a miss. If it is judged to be a small win or a miss, the process proceeds to step S611-21, and if it is not a small win or a miss, the process proceeds to step S611-19.

(Step S611-19)
The main CPU 300a changes the result of the big role lottery in the above step S611-13 to a loss.

(Step S611-21)
The main CPU 300a sets the result of the determination process in the above step S611-13 or the result changed in the above step S611-19 as determination information, and ends the special symbol winning determination process.

Figure 39 is a flowchart explaining the special pattern variable number determination process (step S612) in the main control board 300 for the simultaneous rotation reference example.

(Step S612-1)
The main CPU 300a judges whether the result of the big prize lottery in the step S611 is a big win or a small win. If it is judged to be a big win or a small win, the process proceeds to step S612-3, and if it is judged to be neither a big win nor a small win (a miss), the process proceeds to step S612-5.

(Step S612-3)
The main CPU 300a sets a reach mode determination random number judgment table corresponding to the current game state and reserved type.

(Step S612-5)
When the hold type of the read-out hold is special 2 hold, the main CPU 300a checks the counter value of the special pattern 2 hold ball count counter, and when the hold type of the read-out hold is special 1 hold, the main CPU 300a checks the counter value of the special pattern 1 hold ball count counter.

(Step S612-7)
The main CPU 300a sets the corresponding reach group determination random number judgment table based on the current game state, the reserved number and reserved type confirmed in the above step S612-5, and determines the reach group (group type) based on the set reach group determination random number judgment table and the reach group determination random number transferred to the 0th memory unit in the above step S610-9.

(Step S612-9)
The main CPU 300a sets a random number judgment table for determining a losing reach mode corresponding to the group type determined in step S612-7.

(Step S612-11)
The main CPU 300a determines a variation mode number based on the reach mode determination random number judgment table set in the above step S612-3 or step S612-9 and the reach mode determination random number transferred to the 0th memory unit in the above step S610-9. Here, a variation pattern random number judgment table is also determined together with the variation mode number.

(Step S612-13)
The main CPU 300a sets in the transmission buffer a fluctuation mode command corresponding to the fluctuation mode number determined in step S612-11 above.

(Step S612-15)
The main CPU 300a determines a fluctuation pattern number based on the fluctuation pattern random number determination table determined in the above step S612-11 and the fluctuation pattern random number transferred to the 0th memory unit in the above step S610-9.

(Step S612-17)
The main CPU 300a sets the variation pattern command corresponding to the variation pattern number determined in step S612-15 above in the transmission buffer, and ends the special pattern variation number determination process.

Figure 40 is a flowchart explaining the cutoff number management process (step S613) in the main control board 300 in the simultaneous rotation reference example.

(Step S613-1)
The main CPU 300a judges whether the time-saving count, i.e., the counter value of the time-saving count cut-off counter, is greater than 0. As a result, if it is judged that the time-saving count is greater than 0, the process proceeds to step S613-3, and if it is judged that the time-saving count is 0, the time-cut-off management process is terminated.

(Step S613-3)
The main CPU 300a decrements the time-saving cut counter.

(Step S613-5)
In the above step S613-3, the main CPU 300a judges whether the counter value (time-saving count) has been updated to 0. As a result, if it is judged that the time-saving count is 0, the process proceeds to step S613-7, and if it is judged that the time-saving count is not 0, the process for managing the number of times the game has been cut is terminated.

(Step S613-7)
The main CPU 300a sets the time-saving state flag to set the normal game state to a non-time-saving game state. As a result, after the normal game state is set to the time-saving game state, the normal game state is changed to the non-time-saving game state at the start of the change when the change count reaches the time-saving count (here, 50 or 100 times). For example, if it is set to the high probability premonition state, it is set to the most advantageous state.

(Step S613-9)
The main CPU 300a turns on the time-saving end flag and ends the number-of-times-cut management process.

Figure 41 is a flowchart explaining the processing during special pattern change on the main control board 300 in the simultaneous rotation reference example.

(Step S620-1)
The main CPU 300a judges whether the interruption flag is on. In addition, although details will be described later, in the simultaneous rotation reference example, a small winning pattern may be displayed in a stopped state on the second special pattern display 162 during the variable display of the pattern on the first special pattern display 160. In this case, when the small winning pattern is displayed in a stopped state on the second special pattern display 162, a small winning game is executed, during which the subtraction of the variable time of the special pattern on the first special pattern display 160 is suspended, and after the small winning game ends, the variable display of the pattern on the first special pattern display 160 is resumed. The interruption flag is turned on if the variable display of the pattern is being performed on the first special pattern display 160 when the small winning pattern is displayed in a stopped state on the second special pattern display 162. Here, if it is determined that the interruption flag is on, the special pattern variable process is terminated, and if it is determined that the interruption flag is not on, the process is moved to step S620-3.

(Step S620-3)
The main CPU 300a executes a process of updating the special symbol variation base counter. The special symbol variation base counter is set to a counter value that completes one revolution in a predetermined cycle (e.g., 100 ms). Specifically, when the counter value of the special symbol variation base counter is "0", a predetermined counter value (e.g., 25) is set, and when the counter value is "1" or more, the counter value is updated to a value obtained by subtracting "1" from the current counter value.

(Step S620-5)
The main CPU 300a judges whether the counter value of the special symbol variation base counter updated in step S620-3 is "0". If the counter value is "0", the process proceeds to step S620-7. If the counter value is not "0", the process proceeds to step S620-11.

(Step S620-7)
The main CPU 300a performs a special symbol fluctuation timer update process to subtract a predetermined value from the timer value of the special symbol fluctuation timer set in the above step S610-15.

(Step S620-9)
The main CPU 300a judges whether the timer value of the special symbol fluctuation timer updated in the above step S620-7 is "0". If the timer value is "0", the process proceeds to step S620-17, and if the timer value is not "0", the process proceeds to step S620-11.

(Step S620-11)
The main CPU 300a updates the special symbol display timer that measures the lighting time of each of the 7-segment segments that make up the first special symbol display device 160 and the second special symbol display device 162. Specifically, if the timer value of the special symbol display timer is "0", a predetermined timer value is set, and if the timer value is "1" or greater, the timer value is updated to a value obtained by subtracting "1" from the current timer value.

(Step S620-13)
The main CPU 300a judges whether the timer value of the special symbol display timer is "0". If it judges that the timer value of the special symbol display timer is "0", the process proceeds to step S620-15, and if it judges that the timer value of the special symbol display timer is not "0", the process during the special symbol variation is terminated.

(Step S620-15)
The main CPU 300a updates the counter value of the special symbol display symbol counter to be updated, and ends the special symbol variation process. As a result, each segment constituting the 7-segment display is sequentially lit at predetermined time intervals.

(Step S620-17)
The main CPU 300a judges whether the non-target special symbols are being displayed variably. If it is judged that the non-target special symbols are being displayed variably, the process proceeds to step S621. If it is judged that the non-target special symbols are not being displayed variably, the process proceeds to step S620-19.

(Step S621)
The main CPU 300a executes a symbol forcible stop process, which will be described later with reference to FIG.

(Step S620-19)
The main CPU 300a updates the special game management phase to "02H".

(Step S620-21)
The main CPU 300a saves the special symbol stop symbol number (counter value) determined in step S610-13 in the target special symbol display symbol counter. As a result, the determined special symbol is stopped and displayed on the first special symbol display device 160 or the second special symbol display device 162.

(Step S620-23)
The main CPU 300a sets in the transmission buffer a special symbol stop designation command indicating that a special symbol has been stopped and displayed on the first special symbol display device 160 or the second special symbol display device 162.

(Step S620-25)
The main CPU 300a sets the special pattern variation stop time, which is the time for which the special pattern is stopped and displayed, in the special game timer, and ends the special pattern variation process.

Figure 42 is a flowchart explaining the forced pattern stop process (step S621) in the main control board 300 in the simultaneous rotation reference example.

(Step S621-1)
The main CPU 300a judges whether the currently displayed special symbol is a small win symbol. If it is judged to be a small win symbol, the process proceeds to step S621-3. If it is judged not to be a small win symbol, the process proceeds to step S621-11.

(Step S621-3)
The main CPU 300a judges whether the special game special symbol determination flag is 00H, that is, whether the small win symbol is stopped and displayed on the first special symbol display 160. If it is judged that the special game special symbol determination flag is 00H, the process proceeds to step S621-11, and if it is judged that the special game special symbol determination flag is not 00H, the process proceeds to step S621-5.

(Step S621-5)
The main CPU 300a judges whether the special symbol being changed (the other) is a big win symbol. If it is judged to be a big win symbol, the process proceeds to step S621-11. If it is judged not to be a big win symbol, the process proceeds to step S621-7.

(Step S621-7)
The main CPU 300a turns on the interruption flag.

(Step S621-9)
The main CPU 300a executes a variation interruption process to interrupt the variable display of the special symbols, and ends the symbol forced stop process. Here, the main CPU 300a executes a process to temporarily save the remaining time of the variation time and information related to the special symbols in a predetermined memory area.

(Step S621-11)
The main CPU 300a forcibly stops the losing pattern on the first special pattern display 160 or the second special pattern display 162 on which the pattern is being displayed in a changing manner, and performs processing to turn on a special stop flag for the changing time to forcibly end the remaining changing time, and then ends the forced pattern stop processing.

When the small win symbol is displayed as a stopped symbol on the first special symbol display 160 by the above process, a losing symbol is forcibly displayed as a stopped symbol on the second special symbol display 162. Also, when a small win symbol is displayed as a stopped symbol on the second special symbol display 162, if a big win symbol is being displayed as a stopped symbol on the first special symbol display 160 during a variable display in which the big win symbol is finally displayed as a stopped symbol on the first special symbol display 160, a losing symbol is forcibly displayed as a stopped symbol on the first special symbol display 160. On the other hand, when a small win symbol is displayed as a stopped symbol on the second special symbol display 162, if a small win symbol or a losing symbol is being displayed as a stopped symbol on the first special symbol display 160 during a variable display in which the small win symbol or a losing symbol is finally displayed as a stopped symbol on the first special symbol display 160, the variable display on the first special symbol display 160 is temporarily interrupted.

Figure 43 is a flowchart explaining the special symbol stop symbol display process on the main control board 300 in the simultaneous rotation reference example.

(Step S630-1)
The main CPU 300a judges whether the timer value of the special game timer set in the above step S620-25 is "0". If it is judged that the timer value of the special game timer is not "0", the main CPU 300a ends the special symbol stop symbol display process, and if it is judged that the timer value of the special game timer is "0", the process proceeds to step S630-3.

(Step S630-3)
The main CPU 300a judges whether the variable time special stop flag is on. If it is judged that the variable time special stop flag is on, the process proceeds to step S630-5, and if it is judged that the variable time special stop flag is not on, the process for displaying the special symbol stop symbol is terminated.

(Step S630-5)
The main CPU 300a checks the result of the big role lottery.

(Step S630-7)
The main CPU 300a judges whether the result of the big role lottery is a miss. If it is judged to be a miss, the process proceeds to step S630-27, and if it is judged not to be a miss, the process proceeds to step S630-9.

(Step S630-9)
The main CPU 300a performs a game state update process to update the game state. Here, if the special symbol currently being stopped is a big win symbol, the game state is set to the initial state, and if the special symbol currently being stopped is a small win symbol, the game state proceeds directly to the next process.

(Step S630-11)
The main CPU 300a sets data in the special electric accessory operation RAM set table according to the type of the determined special symbol. Note that the main CPU 300a turns off the variable time special stop flag if it is on.

(Step S630-13)
The main CPU 300a performs a process for setting the maximum number of times that the special electric device operates. Specifically, the data set in step S630-11 is referenced, and a predetermined number (counter value corresponding to the type of special symbol=number of rounds) is set as a counter value in the maximum number of times that the special electric device operates. The maximum number of times that the special electric device operates indicates the number of rounds that can be executed in the big role game that is about to start. Meanwhile, the main RAM 300c is provided with a counter for the number of consecutive times that the special electric device operates, and the current number of rounds is managed by adding "1" to the counter value of the counter for the number of consecutive times that the special electric device operates at the start of each round game. Here, a process for resetting (updating to "0") the counter value of the counter for the number of consecutive times that the special electric device operates is also executed with the start of the big role game.

(Step S630-15)
The main CPU 300a refers to the data set in step S630-11 and saves a predetermined opening time as a timer value in the special electric role play timer.

(Step S630-17)
The main CPU 300a sets an opening designation command in the transmission buffer to transmit the start of the big prize game to the sub-control board 330.

(Step S630-19)
The main CPU 300a updates the special electric role game management phase to "01H" when starting a big win game, and updates the special electric role game management phase to "05H" when starting a small win game.

(Step S630-21)
The main CPU 300a updates the special game management phase to "00H".

(Step S630-23)
The main CPU 300a judges whether the special electric role game management phase updated in the above step S630-19 is "01H", that is, whether a jackpot has been reached. If it is judged that the special electric role game management phase is "01H", the process proceeds to step S630-25, and if it is judged that the special electric role game management phase is not "01H", the process proceeds to step S630-27.

(Step S630-25)
The main CPU 300a performs a jackpot signal output start process for outputting a jackpot signal from the game information output terminal board 312, and ends the special symbol stop symbol display process. This process causes a jackpot signal to be output with the start of the big win game (opening). Note that although multiple signals are provided to be output from the game information output terminal board 312, only a specific jackpot signal will be described here.

(Step S630-27)
The main CPU 300a sets in the transmission buffer a game state confirmation command at the time of special symbol determination, which indicates the game state when the special symbol is determined.

(Step S630-29)
The main CPU 300a judges whether the time-saving end flag is on. As described above, the time-saving end flag is turned on in step S613-9 in FIG. 40 at the start of the fluctuation when changing from the time-saving game state to the non-time-saving game state. That is, the time-saving end flag is turned on here when the normal game state is changed from the time-saving game state to the non-time-saving game state due to the time-saving exit at the start of the 50th or 100th fluctuation in the high probability premonition state. That is, here, the time-saving end flag is judged to be on only when the fluctuation at the time of the time-saving exit ends. If it is judged that the time-saving end flag is on, the process moves to step S630-31, and if it is judged that the time-saving end flag is not on, the process moves to step S630-35.

(Step S630-31)
The main CPU 300a performs a jackpot signal output stop process for stopping the jackpot signal output from the game information output terminal board 312. That is, the jackpot signal is output during a big win game or a time-saving game state.

(Step S630-33)
The main CPU 300a turns off the time-saving end flag.

(Step S630-35)
The main CPU 300a updates the special game management phase to "00H" and ends the special symbol stop symbol display process.

Figure 44 is a flowchart explaining the special electric role play management process (step S700) in the main control board 300 in the simultaneous rotation reference example.

(Step S700-1)
The main CPU 300a loads the special electric role play management phase.

(Step S700-3)
The main CPU 300a judges whether the special electric role game management phase loaded in the above step S700-1 is "00H". That is, here, it is judged whether the big role game or the small role game is currently being played. If it is judged that the special electric role game management phase is "00H", the special electric role game management process is terminated, and if it is judged that the special electric role game management phase is not "00H", the process proceeds to step S700-5.

(Step S700-5)
The main CPU 300a selects the special electric role game control module corresponding to the special electric role game management phase loaded in the above step S700-1.

(Step S700-7)
The main CPU 300a calls the special electric role game control module selected in step S700-5 and starts processing.

(Step S700-9)
The main CPU 300a loads a special electric feature game timer that manages the control time of the special electric feature game, and ends the special electric feature game management process.

Figure 45 is a flow chart explaining the processing before the opening of the large prize opening in the main control board 300 in the simultaneous rotation reference example. This processing before the opening of the large prize opening is executed when the special electric role play management phase is "01H" or "05H".

(Step S710-1)
The main CPU 300a judges whether the timer value of the special electric feature game timer set in the above step S630-15 is not "0". If it judges that the timer value of the special electric feature game timer is not "0", it ends the pre-opening process of the big prize opening, and if it judges that the timer value of the special electric feature game timer is "0", it moves the process to step S710-3.

(Step S710-3)
The main CPU 300a updates the counter value of the special electric device continuous operation number counter to a value obtained by adding "1" to the current counter value.

(Step S710-5)
The main CPU 300a sets in the transmission buffer a command to specify opening of the large prize opening to transmit the start of opening of the large prize opening (start of a round of play) to the sub-control board 330.

(Step S711)
The main CPU 300a executes a special prize opening/closing switching process, which will be described later.

(Step S710-7)
The main CPU 300a updates the special electric device play management phase to a value obtained by adding 01H to the current value ("02H" or "06H"), and ends the pre-opening process for the large prize opening.

Figure 46 is a flowchart explaining the large prize opening/closing switching process (S711) in the main control board 300 in the simultaneous rotation reference example.

(Step S711-1)
The main CPU 300a judges whether the counter value of the special electric device opening/closing switching counter is the upper limit of the special electric device opening/closing switching count (the number of times the special winning hole is opened and closed during one round of play). If it is judged that the counter value is the upper limit, the main CPU 300a ends the special winning hole opening/closing switching process, and if it is judged that the counter value is not the upper limit, the process proceeds to step S711-3.

(Step S711-3)
The main CPU 300a refers to the data in the special electric device operation RAM set table and extracts solenoid control data for controlling the energization of the first large prize opening solenoid 126c and the second large prize opening solenoid 128c, and timer data which is the energization time or de-energization time, based on the counter value of the special electric device opening/closing switching count counter.

(Step S711-5)
The main CPU 300a executes a large prize opening solenoid energization control process to start or stop energization of the first large prize opening solenoid 126c or the second large prize opening solenoid 128c based on the solenoid control data extracted in step S711-3. By executing this large prize opening solenoid energization control process, the start or stop of energization of the first large prize opening solenoid 126c or the second large prize opening solenoid 128c is controlled in steps S400-33 and S400-35.

(Step S711-7)
The main CPU 300a saves the timer value based on the timer data extracted in step S711-3 in the special electric accessory timer. The timer value saved in the special electric accessory timer here is the maximum opening time of the big prize opening once.

(Step S711-9)
The main CPU 300a judges whether the first large prize opening solenoid 126c or the second large prize opening solenoid 128c is in the energization start state, that is, whether the control process to start energization of the first large prize opening solenoid 126c or the second large prize opening solenoid 128c has been performed in the above step S711-5. If it is judged to be in the energization start state, the process proceeds to step S711-11, and if it is judged not to be in the energization start state, the large prize opening opening open/close switching process is terminated.

(Step S711-11)
The main CPU 300a updates the counter value of the special electric device opening/closing switching count counter to a value obtained by adding "1" to the current counter value, and ends the large prize opening opening/closing switching process.

Figure 47 is a flowchart explaining the large prize opening control process in the main control board 300 in the simultaneous spin reference example. This large prize opening control process is executed when the special electric role play management phase is "02H" or "06H".

(Step S720-1)
The main CPU 300a judges whether the timer value of the special electric feature game timer saved in the above step S711-7 is 0. If it is judged that the timer value of the special electric feature game timer is not 0, the process proceeds to step S720-5, and if it is judged that the timer value of the special electric feature game timer is 0, the process proceeds to step S720-3.

(Step S720-3)
The main CPU 300a judges whether the counter value of the special electric role opening/closing switching counter is the upper limit value of the special electric role opening/closing switching count. If it is judged that the counter value is the upper limit value, the process proceeds to step S720-7, and if it is judged that the counter value is not the upper limit value, the process proceeds to step S711.

(Step S711)
In the above step S720-3, if it is determined that the counter value of the special electric role opening/closing switching count counter is not the upper limit value of the special electric role opening/closing switching count, the main CPU 300a executes the processing of the above step S711.

(Step S720-5)
The main CPU 300a judges whether the counter value of the large prize opening winning ball counter updated in the above step S500-9 has reached a specified number, that is, whether the number of game balls equal to the maximum number of winnings in one round has entered the large prize opening. If it is determined that the specified number has not been reached, the main CPU 300a ends the large prize opening opening opening control process, and if it is determined that the specified number has been reached, the process proceeds to step S720-7.

(Step S720-7)
The main CPU 300a executes a large prize opening closing process required to close the large prize opening by stopping the energization of the first large prize opening solenoid 126c or the second large prize opening solenoid 128c. As a result, the large prize opening becomes closed.

(Step S720-9)
The main CPU 300a saves the effective time (interval time) for closing the large prize opening in the special electric device play timer.

(Step S720-11)
The main CPU 300a updates the special electric role play management phase to a value obtained by adding 01H to the current value ("03H" or "07H").

(Step S720-13)
The main CPU 300a sets a special prize opening closure command, indicating that the special prize opening has been closed, in the transmission buffer, and ends the special prize opening opening control process.

Figure 48 is a flow chart explaining the large prize opening closure validity process in the main control board 300 in the simultaneous spin reference example. This large prize opening closure validity process is executed when the special electric role play management phase is "03H" or "07H".

(Step S730-1)
The main CPU 300a judges whether the timer value of the special electric feature game timer saved in the above step S720-9 is 0. If it is judged that the timer value of the special electric feature game timer is not 0, the main CPU 300a ends the large prize opening closure valid processing, and if it is judged that the timer value of the special electric feature game timer is 0, the main CPU 300a proceeds to step S730-3.

(Step S730-3)
The main CPU 300a judges whether the counter value of the special electric device continuous operation counter matches the counter value of the special electric device maximum operation counter, that is, whether a preset number of rounds of play have been completed. If it is judged that the counter value of the special electric device continuous operation counter matches the counter value of the special electric device maximum operation counter, the process proceeds to step S730-9, and if it is judged that they do not match, the process proceeds to step S730-5.

(Step S730-5)
The main CPU 300a updates the special electric accessory game management phase to "01H". In addition, when the special electric accessory game management phase is 07H, that is, during the control of the small win game, the number of rounds of the small win game is "1", so that the result is always YES in the above step S730-3, and the process does not proceed to the step.

(Step S730-7)
The main CPU 300a saves the predetermined special prize opening closing time in the special game timer and ends the special prize opening closing validity process, thereby starting the next round of games.

(Step S730-9)
The main CPU 300a executes an ending time setting process for saving the ending time in a special electric role play timer.

(Step S730-11)
The main CPU 300a updates the special electric role play management phase to a value obtained by adding 01H to the current value ("04H" or "08H").

(Step S730-13)
The main CPU 300a sets an ending designation command indicating the start of the ending in the transmission buffer, and ends the large prize opening closure activation process.

Figure 49 is a flow chart explaining the large prize opening end wait process in the main control board 300 in the simultaneous rotation reference example. This large prize opening end wait process is executed when the special electric role play management phase is "04H" or "08H".

(Step S740-1)
The main CPU 300a judges whether the timer value of the special electric feature game timer saved in the above step S730-9 is not "0". As a result, if it is judged that the timer value of the special electric feature game timer is not "0", the main CPU 300a ends the large prize opening end wait process, and if it is judged that the timer value of the special electric feature game timer is "0", the process proceeds to step S740-3.

(Step S740-3)
The main CPU 300a judges whether the special electric role game management phase is "08H", that is, whether the small win game has ended. If it is judged that the special electric role game management phase is "08H", the process proceeds to step S740-11, and if it is judged that the special electric role game management phase is not "08H", the process proceeds to step S740-5.

(Step S740-5)
The main CPU 300a executes a state setting process to set the game state after the big win game ends. Here, the game state, the number of high probability games, and the number of time-saving games set in the preliminary area in the above step S610-17 are loaded, and the settings of each flag and the counter value are set as the game state after the big win game.

(Step S740-7)
In step S740-5, the main CPU 300a judges whether the normal game state has been set to the non-time-saving game state. If it is judged that the normal game state has been set to the non-time-saving game state, the process proceeds to step S740-9. If it is judged that the normal game state has not been set to the non-time-saving game state, the process proceeds to step S740-21.

(Step S740-9)
The main CPU 300a performs a big win signal output stop process to stop the big win signal output from the game information output terminal board 312. That is, when the most advantageous state is set after the big win game, the output of the big win signal is stopped when the big win game ends.

(Step S740-11)
The main CPU 300a judges whether the current game state is a high probability premonition state (high probability game state and time-saving game state). If it is judged to be a high probability premonition state, the process proceeds to step S740-13, and if it is judged not to be a high probability premonition state, the process proceeds to step S740-21.

(Step S740-13)
The main CPU 300a judges whether the stopped small winning symbol is the special symbol Z1. If it is judged to be the special symbol Z1, the process proceeds to step S740-15. If it is judged not to be the special symbol Z1, the process proceeds to step S740-21.

(Step S740-15)
The main CPU 300a sets the time-saving state flag to change the normal game state to a non-time-saving game state. As a result, when the special symbol Z1 is determined in the high probability premonition state, the game state is changed to the most advantageous state at the end of the small win game.

(Step S740-17)
The main CPU 300a performs a counter reset process to reset the time-saving number counter.

(Step S740-19)
The main CPU 300a performs a big win signal output stop process to stop the big win signal output from the game information output terminal board 312. That is, when the special symbol Z1 is won and the most advantageous state is set after the small win game, the output of the big win signal is stopped when the small win game ends.

(Step S740-21)
The main CPU 300a sets in the transmission buffer a game state change designation command for transmitting the game state to be set after the big win game ends.

(Step S740-23)
The main CPU 300a sets a number command corresponding to the number of high probability times and the number of time reduction times in a transmission buffer.

(Step S740-25)
The main CPU 300a updates the special electric role play management phase to "00H" and ends the waiting process for the end of the special winning slot. As a result, if the special 1 reserve or special 2 reserve is stored, the variable display of the symbols will be resumed.

Figure 50 is a diagram explaining the normal game management phase in the simultaneous play reference example. As already explained, in the simultaneous play reference example, the processing related to the normal game, which is triggered by the passage of the game ball through the gate 124 or the entry of the game ball into the normal play opening 125, is executed step by step and repeatedly, and the main control board 300 manages each processing related to such normal games by the normal game management phase.

As shown in FIG. 50, the main ROM 300b stores multiple normal game control modules for controlling the execution of normal games, and each of these normal game control modules is associated with a normal game management phase. Specifically, when the normal game management phase is "00H", a module for executing "normal symbol change waiting process" is called, when the normal game management phase is "01H", a module for executing "normal symbol change process" is called, when the normal game management phase is "02H", a module for executing "normal symbol stop symbol display process" is called, when the normal game management phase is "03H", a module for executing "normal electric role winning opening pre-processing" is called, when the normal game management phase is "04H", a module for executing "normal electric role winning opening opening control process" is called, when the normal game management phase is "05H", a module for executing "normal electric role winning opening closing valid process" is called, when the normal game management phase is "06H", a module for executing "normal electric role winning opening end wait process" is called.

Figure 51 is a flowchart explaining the normal game management process (step S800) in the main control board 300 in the simultaneous rotation reference example.

(Step S800-1)
The main CPU 300a loads the normal game management phase.

(Step S800-3)
The main CPU 300a selects the normal game control module corresponding to the normal game management phase loaded in step S800-1.

(Step S800-5)
The main CPU 300a calls the normal game control module selected in step S800-3 above and starts processing.

(Step S800-7)
The main CPU 300a loads a normal game timer that manages the control time of the normal game.

Figure 52 is a flowchart explaining the normal symbol change waiting process in the main control board 300 in the simultaneous rotation reference example. This normal symbol change waiting process is executed when the normal game management phase is "00H".

(Step S810-1)
The main CPU 300a loads the counter value of the normal symbol reserved ball number counter and judges whether the counter value is "0", that is, whether the normal symbol reserved is "0". If it is judged that the counter value is "0", the normal symbol change waiting process is terminated, and if it is judged that the counter value is not "0", the process proceeds to step S810-3.

(Step S810-3)
The main CPU 300a transfers the regular reserved balls (win-determining random numbers) stored in the first to fourth storage sections of the regular reserved ball storage area in blocks to the storage section with the next smaller ordinal number. Specifically, the regular reserved balls stored in the second to fourth storage sections are transferred to the first to third storage sections. The main RAM 300c is also provided with a 0th storage section to be processed, and the regular reserved balls stored in the 1st storage section are transferred to the 0th storage section. In addition, in this regular pattern storage area shift process, the counter value of the regular pattern reserved ball count counter is decremented by "1," and a regular reserved reduction command indicating that the regular reserved balls have been decremented by "1" is set in the transmission buffer.

(Step S810-5)
The main CPU 300a loads the winning determination random number transferred to the 0th memory unit, selects a winning determination random number judgment table corresponding to the current game state, performs a regular symbol lottery, and executes a regular symbol winning determination process that stores the lottery result.

(Step S810-7)
The main CPU 300a saves the normal symbol stop symbol number corresponding to the result of the normal symbol lottery in step S810-5. In the simultaneous spin reference example, the normal symbol display 168 is composed of one LED lamp, and in the case of a win, the normal symbol display 168 is turned on, and in the case of a loss, the normal symbol display 168 is turned off. The normal symbol stop symbol number determined here indicates whether or not the normal symbol display 168 is ultimately turned on. For example, in the case of a win, "0" is determined as the normal symbol stop symbol number, and in the case of a loss, "1" is determined as the normal symbol stop symbol number.

(Step S810-9)
The main CPU 300a checks the current game state, and selects and sets the corresponding normal symbol variation time data table.

(Step S810-11)
The main CPU 300a determines the normal symbol variation time based on the winning determination random number transferred to the 0th memory unit in step S810-3 and the normal symbol variation time data table set in step S810-9.

(Step S810-13)
The main CPU 300a saves the normal symbol variation time determined in the above step S810-11 in the normal game timer.

(Step S810-15)
The main CPU 300a executes a process of setting a normal pattern display pattern counter in order to start the variable display of normal patterns in the normal pattern display 168. When the counter value is set to, for example, "0" in the normal pattern display pattern counter, the normal pattern display 168 is controlled to be turned on, and when the counter value is set to "1", the normal pattern display 168 is controlled to be turned off. Here, a predetermined counter value is set in the normal pattern display pattern counter at the start of the variable display of normal patterns.

(Step S810-17)
The main CPU 300a sets a regular map reservation designation command indicating the number of regular map reservations stored in the regular map reservation memory area in a transmission buffer.

(Step S810-19)
The main CPU 300a sets a normal pattern designation command in the transmission buffer based on the normal pattern stopping pattern number determined in step S810-7 above, i.e., the pattern type (winning pattern or losing pattern) determined by the normal pattern winning judgment process.

(Step S810-21)
The main CPU 300a updates the normal game management phase to "01H" and ends the normal pattern change waiting process.

Figure 53 is a flowchart explaining the processing during normal symbol fluctuation in the main control board 300 in the simultaneous rotation reference example. This processing during normal symbol fluctuation is executed when the normal game management phase is "01H".

(Step S820-1)
The main CPU 300a judges whether the timer value of the normal game timer saved in step S810-13 is "0". If the timer value is "0", the process proceeds to step S820-9. If the timer value is not "0", the process proceeds to step S820-3.

(Step S820-3)
The main CPU 300a updates the normal symbol display timer that measures the light-on and light-off times of the normal symbol display 168. Specifically, if the timer value of the normal symbol display timer is "0", a predetermined timer value is set, and if the timer value is "1" or more, the timer value is updated to a value obtained by subtracting "1" from the current timer value.

(Step S820-5)
The main CPU 300a judges whether the timer value of the normal symbol display timer is "0". As a result, if it is judged that the timer value of the normal symbol display timer is "0", the process proceeds to step S820-7, and if it is judged that the timer value of the normal symbol display timer is not "0", the process during the normal symbol variation is terminated.

(Step S820-7)
The main CPU 300a updates the counter value of the normal symbol display symbol counter. Here, if the counter value of the normal symbol display symbol counter is a counter value indicating that the normal symbol display 168 is turned off, it is updated to a counter value indicating that the normal symbol display 168 is turned on, and if the counter value is a counter value indicating that the normal symbol display 168 is turned on, it is updated to a counter value indicating that the normal symbol display 168 is turned off, and the normal symbol variation process is terminated. As a result, the normal symbol display 168 is turned on and off (blinks) at predetermined intervals over the normal symbol variation time.

(Step S820-9)
The main CPU 300a saves the normal symbol stop symbol number (counter value) determined in step S810-7 in the normal symbol display symbol counter. As a result, the normal symbol display 168 is finally controlled to be turned on or off, and the result of the normal symbol lottery is announced.

(Step S820-11)
The main CPU 300a sets a normal pattern variation stop time, which is the time for stopping and displaying the normal pattern, in a normal game timer.

(Step S820-13)
The main CPU 300a sets a normal symbol stop command, which indicates that the stopped display of normal symbols has begun, in the transmission buffer.

(Step S820-15)
The main CPU 300a updates the normal game management phase to "02H" and ends the normal pattern variation processing.

Figure 54 is a flowchart explaining the normal symbol stop symbol display process in the main control board 300 in the simultaneous rotation reference example. This normal symbol stop symbol display process is executed when the normal game management phase is "02H".

(Step S830-1)
The main CPU 300a judges whether the timer value of the normal game timer set in the above step S820-11 is not "0". As a result, if it is judged that the timer value of the normal game timer is not "0", the normal symbol stop symbol display process is terminated, and if it is judged that the timer value of the normal game timer is "0", the process proceeds to step S830-3.

(Step S830-3)
The main CPU 300a checks the result of the regular drawing.

(Step S830-5)
The main CPU 300a judges whether the result of the regular drawing is a win or not. If it is judged to be a win, the process proceeds to step S830-9, and if it is judged to be a no win (no win), the process proceeds to step S830-7.

(Step S830-7)
The main CPU 300a updates the normal game management phase to "00H" and ends the normal stop symbol display process. This ends the normal game management process based on one normal symbol reservation, and if a normal symbol reservation is stored, processing is performed to start the variable display of the next reserved normal symbol.

(Step S830-9)
The main CPU 300a refers to the data in the opening/closing control pattern table, and saves the time before normal power opening in the normal game timer as a timer value.

(Step S830-11)
The main CPU 300a updates the normal game management phase to "03H" and ends the normal symbol stop symbol display process. This starts the opening and closing control of the first variable start opening 120B.

Figure 55 is a flow chart explaining the processing before the opening of the winning opening of the normal electric device in the main control board 300 in the simultaneous rotation reference example. This processing before the opening of the winning opening of the normal electric device is executed when the normal game management phase is "03H".

(Step S840-1)
The main CPU 300a judges whether the timer value of the normal game timer set in the above step S830-9 is "0". As a result, if it is judged that the timer value of the normal game timer is not "0", the normal electric role winning opening pre-opening process is terminated, and if it is judged that the timer value of the normal game timer is "0", the process proceeds to step S841.

(Step S841)
The main CPU 300a executes a normal electric device prize opening opening/closing switching process, which will be described later.

(Step S840-3)
The main CPU 300a updates the normal game management phase to "04H" and ends the processing before opening the normal electric device winning opening.

Figure 56 is a flowchart explaining the normal electric role winning opening/closing switching process in the main control board 300 for the simultaneous rotation reference example.

(Step S841-1)
The main CPU 300a judges whether the counter value of the normal electric role opening/closing switching counter is the upper limit value of the normal electric role opening/closing switching count (the number of times the movable piece 120b of the first variable start port 120B is opened and closed during one opening/closing control). If it is judged that the counter value is the upper limit value, the normal electric role winning port opening/closing switching process is terminated, and if it is judged that the counter value is not the upper limit value, the process proceeds to step S841-3.

(Step S841-3)
The main CPU 300a refers to the data in the opening/closing control pattern table and extracts solenoid control data (energization control data or energization stop control data) for controlling the energization of the normal electric role solenoid 120c based on the counter value of the normal electric role opening/closing switching count counter, and timer data which is the energization time (solenoid energization time) or energization stop time (normal electric closing effective time = pause time) of the normal electric role solenoid 120c.

(Step S841-5)
The main CPU 300a executes a normal electric role solenoid energization control process to start energizing the normal electric role solenoid 120c or to stop energizing the normal electric role solenoid 120c based on the solenoid control data extracted in the above step S841-3. By executing this normal electric role solenoid energization control process, the normal electric role solenoid 120c is controlled to start or stop energizing in the above step S400-33 and step S400-35.

(Step S841-7)
The main CPU 300a saves the timer value based on the timer data extracted in step S841-3 in the normal game timer. The timer value saved in the normal game timer here is the maximum opening time of the first variable start port 120B once.

(Step S841-9)
The main CPU 300a judges whether the normal electric role solenoid 120c is in the energization start state, that is, whether the control process to start energization of the normal electric role solenoid 120c has been performed in the above step S841-5. As a result, if it is judged to be in the energization start state, the process proceeds to step S841-11, and if it is judged not to be in the energization start state, the normal electric role winning port opening/closing switching process is terminated.

(Step S841-11)
The main CPU 300a updates the counter value of the normal electric role opening/closing switching count counter to a value obtained by adding "1" to the current counter value.

Figure 57 is a flowchart explaining the normal electric device prize opening control process in the main control board 300 for the simultaneous rotation reference example. This normal electric device prize opening control process is executed when the normal game management phase is "04H".

(Step S850-1)
The main CPU 300a judges whether the timer value of the normal game timer saved in the above step S841-7 is not "0". As a result, if it is judged that the timer value of the normal game timer is not "0", the process proceeds to step S850-5, and if it is judged that the timer value of the normal game timer is "0", the process proceeds to step S850-3.

(Step S850-3)
The main CPU 300a judges whether the counter value of the normal electric role opening/closing switching counter is the upper limit value of the normal electric role opening/closing switching count. If it is judged that the counter value is the upper limit value, the process proceeds to step S850-7, and if it is judged that the counter value is not the upper limit value, the process proceeds to step S841.

(Step S841)
In the above step S850-3, if it is determined that the counter value of the normal electric role opening/closing switching count counter is not the upper limit value of the normal electric role opening/closing switching count, the main CPU 300a executes the processing of the above step S841.

(Step S850-5)
The main CPU 300a judges whether the counter value of the normal electric device winning ball counter updated in the above step S530-9 has reached a specified number, that is, whether the first variable start opening 120B has received the same number of game balls as the maximum number of winning balls during one opening/closing control. If it is determined that the specified number has not been reached, the normal electric device winning opening opening control process is terminated, and if it is determined that the specified number has been reached, the process proceeds to step S850-7.

(Step S850-7)
The main CPU 300a executes a normal electric role closing process required to stop the power supply to the normal electric role solenoid 120c and close the first variable start port 120B. This causes the first variable start port 120B to be in a closed state.

(Step S850-9)
The main CPU 300a saves the normal power effective state time in the normal game timer.

(Step S850-11)
The main CPU 300a updates the normal game management phase to "05H" and ends the normal electric device winning port opening control process.

Figure 58 is a flow chart explaining the normal electric device prize opening closure enable processing in the main control board 300 relating to the simultaneous rotation reference example. This normal electric device prize opening closure enable processing is executed when the normal game management phase is "05H".

(Step S860-1)
The main CPU 300a judges whether the timer value of the normal game timer saved in the above step S850-9 is not "0". As a result, if it is judged that the timer value of the normal game timer is not "0", the normal electric role winning port closure valid processing is terminated, and if it is judged that the timer value of the normal game timer is "0", the processing proceeds to step S860-3.

(Step S860-3)
The main CPU 300a saves the normal power end wait time in the normal game timer.

(Step S860-5)
The main CPU 300a updates the normal game management phase to "06H" and ends the normal electric role winning hole closure validation processing.

Figure 59 is a flow chart explaining the normal electric role winning slot end wait process in the main control board 300 in the simultaneous rotation reference example. This normal electric role winning slot end wait process is executed when the normal game management phase is "06H".

(Step S870-1)
The main CPU 300a judges whether the timer value of the normal game timer saved in the above step S860-3 is not "0". As a result, if it is judged that the timer value of the normal game timer is not "0", the normal electric role winning port end wait process is terminated, and if it is judged that the timer value of the normal game timer is "0", the process proceeds to step S870-3.

(Step S870-3)
The main CPU 300a updates the normal game management phase to "00H" and ends the normal electric role winning port end wait process. As a result, if a normal symbol reservation is stored, the variable display of the normal symbol will be resumed. Next, as a reference example of the performance, specific performances that can be executed in the above-mentioned one-type gaming machine, one-type two-type gaming machine, and simultaneous spinning machine and specific processing related to the performance will be described.

<Example of performance>
FIG. 60 is a diagram for explaining an example of a variation performance of a no-reach variation pattern according to a reference performance example. As described above, when a big role lottery is performed in the main control board 300, a variation performance is performed to notify the result of the big role lottery during the variation display of the special symbol, that is, during the variation time of the special symbol. In this variation performance, various background images are displayed in the main performance display section 200a, and the performance symbols 210a, 210b, and 210c are displayed superimposed on the background images. During the variation performance, sound is output from the audio output device 206 in accordance with the image displayed in the main performance display section 200a, and the performance lighting device 204 is controlled to light up, and the performance role device 202 is controlled to move, but detailed explanations are omitted here.

The variable performances in the reference performance examples are broadly divided into a no-reach variable pattern and a reach variable pattern. In the variable performance of the no-reach variable pattern, a background image (not shown) is displayed on the main performance display unit 200a, and the performance patterns 210a, 210b, and 210c are displayed in a variable manner superimposed on this background image. For example, as shown in FIG. 60(a), the performance patterns 210a, 210b, and 210c are displayed stationary in a combination that indicates that the big role lottery result was a miss. In this state, when a new special pattern is displayed, as the display of the special pattern starts, the three performance patterns 210a, 210b, and 210c start to display (scroll) as shown in FIG. 60(b). Note that the downward white arrow in the figure indicates that the performance patterns 210a, 210b, and 210c are displayed scrolling in the vertical direction.

Then, as shown in FIG. 60(c), first, the effect pattern 210a is displayed as a stopped pattern, and then, as shown in FIG. 60(d), the effect pattern 210c, which is different from the effect pattern 210a, is displayed as a stopped pattern. Then, at approximately the same timing as the special pattern stops being displayed as a stopped pattern on the first special pattern display device 160 or the second special pattern display device 162 after the variable display of the special pattern, the effect pattern 210b is displayed as a stopped pattern, as shown in FIG. 60(e), and the result of the big prize lottery is notified to the player based on the final stopped display state of the three effect patterns 210a, 210b, and 210c at this time.

Figure 61 is a diagram for explaining an example of a normal reach fluctuation pattern fluctuation performance according to a performance reference example. In the performance reference example, the reach fluctuation pattern is broadly divided into a normal reach fluctuation pattern, an advanced reach fluctuation pattern, and a pseudo-continuous reach fluctuation pattern. In the normal reach fluctuation pattern fluctuation performance, similar to the non-reach fluctuation pattern fluctuation performance, the fluctuation display of the performance patterns 210a, 210b, and 210c begins with the start of the fluctuation display of the special pattern, and as shown in Figure 61 (a), the performance pattern 210a is first displayed frozen. After that, as shown in Figure 61 (b), the performance pattern 210c, which is the same as the performance pattern 210a, is displayed frozen.

In this way, when the same performance symbols 210a, 210c are displayed in a reach state in the main performance display section 200a, as shown in FIG. 61(c), "reach" is displayed superimposed on the performance symbols 210a, 210c in the main performance display section 200a. Note that there are multiple types of reach states, and the same performance symbols 210a, 210c with any of the numbers "1" to "9" written on them are displayed in a stopped state. After that, as shown in FIG. 61(d), the shape of the performance symbols 210a, 210c is changed from that before the reach state and the variable display continues. Then, as shown in FIG. 61(e), finally, a performance symbol 210b different from the performance symbols 210a, 210c is displayed in a stopped state, and the player is notified that the result of the big role lottery was a miss.

Figure 62 is a diagram for explaining an example of the variation presentation of the development reach variation pattern at the time of a miss according to the performance reference example, and Figure 63 is a diagram for explaining an example of the variation presentation of the development reach variation pattern at the time of a big win according to the performance reference example. As shown in Figures 62(a)-(d) and 63(a)-(d), the variation presentation of the development reach variation pattern is similar to the variation presentation of the normal reach variation pattern, in which the performance patterns 210a and 210c are displayed in a reach state in the main performance display section 200a, and then a reach development presentation in which a predetermined development image (video) is played and displayed is executed. In this reach development presentation, for example, as shown in Figures 62(e) and 63(e), a mission is displayed on the main performance display section 200a, and as shown in Figures 62(f), (g) and 63(f), (g), an image toward the achievement of the mission is displayed.

Here, the development images for reach development effects are broadly divided into miss patterns and big win patterns, and in the development image for the miss pattern, as shown in FIG. 62(h), an image indicating failure of the mission is finally displayed, and then, as shown in FIG. 62(i), the performance patterns 210a, 210b, and 210c are displayed in a stopped combination to indicate a miss. On the other hand, in the development image for the big win pattern, as shown in FIG. 63(h), an image indicating success of the mission is finally displayed, and then, as shown in FIG. 63(i), the performance patterns 210a, 210b, and 210c are displayed in a stopped combination to indicate a big win.

The reach development effects include, for example, mission effects in which development images of mission challenges are displayed, and battle effects in which development images of friendly characters and enemy characters battling each other are displayed, as described above. The mission effects have multiple execution patterns with different mission contents, and the battle effects have multiple execution patterns with different characters appearing and fighting methods. As described above, the execution patterns of the mission effects are broadly divided into big win patterns in which the mission is accomplished and failure patterns in which the mission is failed, and the execution patterns of the battle effects are similarly broadly divided into big win patterns in which the friendly character triumphs over the enemy character and failure patterns in which the friendly character is defeated by the enemy character.

The big win pattern and the losing pattern are composed of the same content until the end of the performance, and differ in whether the friendly character ultimately wins or loses, or whether the mission is accomplished or not. Therefore, during the reach development performance, the player cannot distinguish the result of the big role lottery until the end of the variable performance, which gives the player a sense of expectation of a big win.

The big win pattern is selected only if the big win lottery result is a big win, and the miss pattern is selected only if the big win lottery result is a miss. However, the reach development effect may be executed twice in one variable performance, in which case the first reach development effect is executed in a miss pattern, and the second reach development effect is executed in either a miss pattern or a big win pattern. The flow of the performance when the reach development effect is executed twice in one variable performance is explained below.

Figure 64 is a diagram illustrating an example of a variable performance when the reach development performance relating to the reference performance example is executed twice. For example, after performance patterns 210a, 210c are displayed in a reach state, a mission performance is executed as shown in Figures 64(a) and (b). Up to this point, there is no difference from the case where the reach development performance is executed only once in one variable performance, but immediately after it is notified that the mission has not been completed, "REACH UP" is displayed on the main performance display section 200a as shown in Figure 64(c).

Then, as shown in FIG. 64(d), the main performance display section 200a displays a battle performance development image, and the second reach development performance starts. This battle performance development image shows a battle between an ally character and an enemy character, and when a jackpot is won, as shown in FIG. 64(e), the ally character finally wins against the enemy character, and as shown in FIG. 64(f), the performance symbols 210a, 210b, and 210c are displayed in a stopped combination to indicate a jackpot. On the other hand, when a loss occurs, as shown in FIG. 64(g), the ally character finally loses to the enemy character, and as shown in FIG. 64(h), the performance symbols 210a, 210b, and 210c are displayed in a stopped combination to indicate a loss.

Figure 65 is a diagram for explaining an example of the pseudo-successive reach fluctuation pattern fluctuation performance according to the performance reference example. As shown in Figure 65 (a), when the display of the fluctuation of the performance patterns 210a, 210b, and 210c starts, the performance patterns 210a, 210b, and 210c are temporarily stopped and displayed in one of multiple types of pseudo patterns that have been set up in advance, as shown in Figure 65 (b). In this pseudo pattern, for example, the same performance patterns 210a and 210b and the performance pattern 210c with a number "2" larger than these performance patterns 210a and 210b are temporarily stopped and displayed.

When the performance symbols 210a, 210b, and 210c are temporarily stopped in a pseudo mode, the display of the changing performance symbols 210a, 210b, and 210c is resumed, as shown in FIG. 65(c). In other words, the pseudo mode can be said to indicate a re-changing display of the performance symbols 210a, 210b, and 210c. After that, the performance symbols 210a, 210b, and 210c are temporarily stopped again in a pseudo mode, as shown in FIG. 65(d).

Then, as shown in FIG. 65(e), when the display of the varying effect symbols 210a, 210b, and 210c resumes, as shown in FIG. 65(f), the effect symbols 210a and 210c are displayed in a reach state, and thereafter, as shown in FIG. 65(g)-(i), the reach development effect is executed in the same manner as the developed reach variation pattern, and the result of the big prize lottery is notified to the player.

In this way, the pseudo-continuous reach fluctuation pattern's fluctuation performance differs from that of the developed reach fluctuation pattern in the content until the performance patterns 210a, 210c reach the state, and after the state is reached, the fluctuation performance proceeds in the same way as the developed reach fluctuation pattern.

In addition, in the pseudo-continuous reach fluctuation pattern, a plurality of fluctuation display patterns of the performance symbols 210a, 210b, and 210c until the reach state is reached are provided, and the number of tentative stop displays of the performance symbols 210a, 210b, and 210c, in other words, the number of times that the performance symbols 210a, 210b, and 210c are displayed, differs for each fluctuation display pattern. This fluctuation display pattern is determined by the fluctuation mode command, and the selection ratio of the fluctuation mode command when the jackpot is won and when it is lost is set so that the more the number of tentative stop displays (fluctuation displays) of the performance symbols 210a, 210b, and 210c, the higher the possibility (hereinafter referred to as "reliability") that a jackpot will ultimately be announced.

Specifically, if the result of the big role lottery is a big win, the selection ratio of the variable mode command with a large number of variable display counts is set higher than the selection ratio of the variable mode command with a small number of variable display counts, and if the result of the big role lottery is a loss, the selection ratio of the variable mode command with a small number of variable display counts is set higher than the selection ratio of the variable mode command with a large number of variable display counts.

In addition, the main control board 300 is set so that the reliability of the pseudo-successive reach fluctuation pattern is higher than the reliability of the extended reach fluctuation pattern. Therefore, the reliability is indicated by the number of tentative stop displays (fluctuating displays) of the performance symbols 210a, 210b, and 210c, and the player will watch the progress of the performance while hoping for more tentative stop displays (fluctuating displays) of the performance symbols 210a, 210b, and 210c.

The execution pattern of the above-mentioned variable performance is determined and controlled by the sub-control board 330 based on the variable command determined by the main control board 300. In other words, it can be said that the execution pattern of the variable performance is determined in cooperation between the main control board 300 and the sub-control board 330.

Figure 66 is a diagram explaining the variable performance determination table related to the performance reference example, in which Figure 66 (a) shows the first half variable performance determination table, and Figure 66 (b) shows the second half variable performance determination table. As described above, when the main control board 300 performs a big role lottery, a variable command is determined based on the result of the big role lottery, and each determined command is sent to the sub-control board 330. When the sub-control board 330 receives a variable mode command, it obtains a performance random number of 1 from the range of 0 to 249, and refers to the first half variable performance determination table to determine the execution pattern of the first half variable performance based on the obtained performance random number and the received variable mode command. Also, when it receives a variable pattern command, it obtains a performance random number of 1 from the range of 0 to 249, and refers to the second half variable performance determination table to determine the execution pattern of the second half variable performance based on the obtained performance random number and the received variable pattern command. Note that Figure 66 shows only a part of the first half variable performance determination table and the second half variable performance determination table.

As shown in FIG. 66, according to the first half variable performance decision table, a selection ratio for the execution pattern of the first half variable performance is set for each variable mode number (variation mode command), and according to the second half variable performance decision table, a selection ratio for the execution pattern of the second half variable performance is set for each variable pattern number (variation pattern command). Then, one variable performance is executed by combining and executing the execution patterns of the first and second half variable performances that have been determined.

The no-reach fluctuation pattern fluctuation performance is executed when "none" is determined as the execution pattern of the first half, indicating that the first half fluctuation performance is not executed, and "normal miss 1", "normal miss 2", "special miss 1", or "special miss 2" corresponding to the no-reach fluctuation pattern is determined as the execution pattern of the second half. For example, when a fluctuation mode command corresponding to the fluctuation mode number "01H", indicating that the first half fluctuation performance is not executed, is received, the sub-control board 330 always determines "none" as the execution pattern of the first half. In addition, at this time, the selection ratio is set in the second half fluctuation performance determination table so that only one of "normal miss 1", "normal miss 2", "special miss 1", or "special miss 2" is determined as the fluctuation pattern command that can be received at the same time. Therefore, by determining "none" as the execution pattern of the first half and determining "normal miss 1", "normal miss 2", "special miss 1", or "special miss 2" as the execution pattern of the second half, the execution pattern of the fluctuation performance is determined to be the no-reach fluctuation pattern described above.

On the other hand, the reach fluctuation pattern fluctuation performance is executed when a pattern other than "none" is determined as the execution pattern for the first half, and one of the reach development performances (shown as developments 1 to 5 in the figure) is determined as the execution pattern for the second half. In other words, when the reach fluctuation pattern fluctuation performance is executed in the main performance display unit 200a, a fluctuation mode command corresponding to a fluctuation mode number other than the fluctuation mode number = 01H is always received, and a fluctuation pattern command corresponding to a fluctuation pattern number that determines one of developments 1 to 5 is received.

Here, in FIG. 66(a), "Normal Reach 1" and "Normal Reach 2" in the execution pattern of the first half respectively indicate the background image and the variable display pattern of the performance symbols 210a, 210b, 210c displayed on the main performance display section 200a until the performance symbols 210a, 210b, 210c reach the reach state, or more specifically, until the reach development performance begins, among the variable performances of the normal reach variable pattern. These image patterns are designed in advance to match the variable display time of the special symbol associated with the variable mode number, and for example, when "Normal Reach 1" is determined, the images shown in FIG. 61(a)-(d) will be displayed on the main performance display section 200a.

In addition, in FIG. 66(a), "pseudo 2a" and the like in the execution pattern in the first half indicate the display pattern of the main change performance image displayed on the main performance display unit 200a until the reach development performance starts, among the change performances of the pseudo continuous reach change pattern, that is, the execution pattern of the pattern display performance in which the performance patterns 210a, 210b, and 210c are displayed changeably. For example, "pseudo 2a" indicates that the pseudo continuous reach change pattern of "pseudo 2" in which the change display number of the performance patterns 210a, 210b, and 210c is two, and the main change performance image is display pattern a. Also, "pseudo 3b" indicates that the pseudo continuous reach change pattern of "pseudo 3" in which the change display number of the performance patterns 210a, 210b, and 210c is three, and the main change performance image is display pattern b.

In the first half variation presentation decision table and second half variation presentation decision table shown in FIG. 66, the selection ratio is set so that the variation presentation of the no-reach variation pattern and the normal reach variation pattern is executed only when the result of the big role lottery is a miss. Also, the developed reach variation pattern and the pseudo-continuous reach variation pattern are determined both when there is a miss and when there is a jackpot, but the selection ratio of the developed reach variation pattern is set higher when there is a miss and lower when there is a jackpot than the pseudo-continuous reach variation pattern. In this way, by setting the selection ratio when there is a miss and when there is a jackpot, the pseudo-continuous reach variation pattern is set to have a higher reliability than the developed reach variation pattern.

Furthermore, within the pseudo-sequential reach fluctuation pattern, the more the number of pseudos, the higher the selection rate for a big win and the lower the selection rate for a miss, so that the more the number of pseudos, the higher the reliability.

As described above, the general flow of the variable performance is determined by the variable performance determination table, but at the start of the variable performance, the possibility of executing various element performances that make up the variable performance and the execution pattern are further determined based on the variable mode command or the variable pattern command. Here, element performance refers to all performances that make up the variable performance, such as the variable display of performance patterns 210a, 210b, and 210c on the main performance display unit 200a, the development image displayed on the main performance display unit 200a in the reach development performance, and even the performance that moves the performance role device 202, as described above. In the embodiment, preview performances (suggested performances) are executed at various times during the variable performance as element performances that make up the variable performance.

This preview performance is a performance in which a predetermined image is displayed on the main performance display unit 200a and the performance role device 202 is moved at a predetermined timing when the fluctuation performance starts, when the fluctuation patterns 210a, 210b, 210c are displayed again in the fluctuation performance of the pseudo continuous reach fluctuation pattern, and even during the reach development performance, and the possibility of execution and the execution pattern are determined for each preview performance. Each preview performance has multiple types of execution patterns, and for each of the multiple types of execution patterns, a selection ratio is set for each fluctuation pattern command or fluctuation mode command, in other words, for each possibility of winning the jackpot, and an expected value is set for each execution pattern based on this selection ratio.

As explained above, when the sub-control board 330 receives a variation command, it determines the execution pattern of the variation performance, whether each element performance can be executed, and the execution pattern, and the variation performance is executed while the special pattern is being displayed. In this way, the variation performance is executed once for each special pattern variable display, but in the embodiment, a performance spanning multiple special pattern variable displays is also executed.

Figure 67 is a diagram for explaining an example of a reserved display effect according to the reference example. A reserved display area 211 is provided at the bottom of the main effect display section 200a. Although not shown in Figures 60 to 65, the reserved display area 211 is always displayed on the main effect display section 200a even during variable effects and while waiting for a game. During variable effects, a reserved display effect is performed in this reserved display area 211. In the reserved display effect, the reserved display 212a indicating the reserved item read out to the processing area (zeroth memory section) during the big role lottery, the first reserved display 212b, the second reserved display 212c, the third reserved display 212d, and the fourth reserved display 212e indicating the reserved items stored in the first memory section to the fourth memory section of the first special chart reserved memory area, respectively, are displayed in the reserved display area 211. In the following, the reserved display 212a and the first reserved display 212b to the fourth reserved display 212e are collectively referred to as reserved display 212.

For example, when the special symbol is being displayed in a variable manner and four special 1 reserved symbols are stored in the main RAM 300c, the reserved symbol 212a and the first reserved symbol 212b to the fourth reserved symbol 212e, a total of five reserved symbols 212, are displayed in the reserved symbol display area 211 as shown in FIG. 67(a). Then, when the display of the special symbol is terminated from this state, the special 1 reserved symbol stored in the first memory unit is read into the processing area (the 0th memory unit) and a large role lottery is performed, and the reserved symbol shift processing of the main RAM 300c is executed, the reserved symbol 212a is erased and the first reserved symbol 212b to the fourth reserved symbol 212e are moved one position to the left as shown in FIG. 67(b). Furthermore, when the next special 1 reserved symbol is read from this state, each reserved symbol 212 is further moved as shown in FIG. 67(c). In this way, the reserved symbol display is a display that notifies the player of the number of special 1 reserved symbols stored in the main RAM 300c.

In addition, multiple display patterns of the reserved display 212 are provided, and the display color is different for each display pattern. In the main control board 300, when a reserved is stored, the acquisition time performance determination process (step S536) is executed, and a look-ahead designation command indicating the variable information to be determined when the newly stored reserved is read out to the 0th storage unit is sent to the sub-control board 330. When the sub-control board 330 receives the look-ahead designation command, it determines the display pattern of the reserved display 212 corresponding to the newly stored reserved based on the received command. At this time, the selection ratio of each display pattern is set for each look-ahead designation command, that is, for each variable information to be determined when the newly stored reserved is read out in the big role lottery. In other words, since the selection ratio of each display pattern is set according to the possibility of winning a jackpot and the execution pattern of the variable performance, the display pattern of the reserved display 212 suggests the reliability (expected value) of the jackpot.

Figure 68 (a) is a diagram explaining the final pending display pattern determination table, and Figure 68 (b) is a diagram explaining the previous pending display pattern determination table. As described above, in the acquisition time performance determination process in the main control board 300, a look-ahead designation command indicating the variation mode number and variation pattern number to be determined when the newly stored pending is read out is sent to the sub-control board 330. In other words, the look-ahead designation command is a command that transmits the variation mode number and variation pattern number to be determined when the pending is read out to the sub-control board 330. According to the final pending display pattern determination table, the selection ratio of the display pattern of the pending display 212 is set for each look-ahead designation command (variation pattern number), and when a look-ahead designation command is received, the final display pattern of the pending display 212, i.e., the final display pattern of the pending display 212a, is determined.

According to the final hold display pattern determination table shown in FIG. 68(a), one of eight display patterns is determined: "default (white)", "flashing", "blue", "yellow", "green", "black", "red", and "premium (rainbow)". Then, once the final display pattern of the hold display 212a is determined, the display pattern of the hold display 212 displayed before that is determined by referring to the previous hold display pattern determination table shown in FIG. 68(b). According to this previous hold display pattern determination table, a selection ratio of the display pattern of the hold display 212 to be displayed before the moving display is set for each display pattern of the hold display 212.

For example, when a hold is stored in the second memory section of the first special chart hold memory area in the main control board 300, the final display pattern of the hold display 212a is determined by referring to the final hold display pattern determination table. In this case, the display pattern of the first hold display 212b is then determined by referring to the previous hold display pattern determination table. At this time, the display pattern of the first hold display 212b is determined based on the previously determined final display pattern of the hold display 212a. For example, if the final display pattern of the hold display 212a is "blue," then according to the previous hold display pattern determination table, the display pattern of the first hold display 212b is determined to be "blinking" with a probability of 200/250, and "blue" with a probability of 50/250.

Once the display pattern of the first hold display 212b is determined in this manner, the display pattern of the second hold display 212c is then determined based on the previously determined display pattern of the first hold display 212b, again by referring to the previous hold display pattern determination table.

As described above, when a hold is stored, first the final display pattern of the hold display 212a is determined, and then the display pattern of the first hold display 212b is determined based on the determined final display pattern of the hold display 212a, and so on, in a manner that works backwards in the display order to determine the display patterns. Note that, according to the previous hold display pattern determination table, the selection ratio is set so that only a display pattern that is the same as the previously determined hold display 212 display pattern or one with a low reliability is determined.

As described above, in the hold display presentation, multiple display patterns are provided for the hold display 212, each of which has a different expected value for the award of a predetermined gaming profit. From the time the hold display 212 is first displayed on the main presentation display section 200a until it is finally erased, the hold display 212 may be displayed in one display pattern, or the display pattern may change during the display period.

In the reference example, the timing when the display pattern of the hold display 212 changes can be broadly divided into when the newly stored special hold 1 (hereinafter also referred to as the target hold) is moved to the first hold display 212b to the third hold display 212d, and when the target change display related to the target hold is in progress.

Next, we will explain the processing in the sub-control board 330 to execute the above-mentioned variable performance. Note that, in the following, we will omit explanations of the processing in the sub-control board 330 that is not related to the variable performance.

(Sub-CPU Initialization Processing of the Sub-Control Board 330)
FIG. 69 is a flowchart explaining the sub-CPU initialization process (S1000) of the sub-control board 330 relating to the reference example of performance.

(Step S1000-1)
When the power is turned on, the sub-CPU 330a reads a CPU initialization processing program from the sub-ROM 330b, and initializes and sets flags and the like stored in the sub-RAM 330c.

(Step S1000-3)
Next, the sub-CPU 330a performs a process of updating each effect random number, and thereafter repeats the process of step S1000-3 until an interrupt process is performed. Note that multiple types of effect random numbers are provided, and here, each effect random number is updated asynchronously.

(Sub-timer interrupt processing of the sub-control board 330)
70 is a flow chart for explaining the sub timer interrupt process (S1100) of the sub control board 330 according to the reference example. The sub control board 330 is provided with a reset clock pulse generating circuit (not shown) that generates a clock pulse at a predetermined cycle (30 times per second). When the reset clock pulse generating circuit generates a clock pulse, the sub CPU 330a reads a timer interrupt process program and starts the sub timer interrupt process.

(Step S1100-1)
The sub CPU 330a saves the registers.

(Step S1100-3)
The sub-CPU 330a performs processing for permitting an interrupt.

(Step S1100-5)
The sub-CPU 330a performs update processing of various timer counters used in the sub-control board 330. Here, unless otherwise specified, the various timer counters are decremented by 1 each time the sub-timer interrupt processing of the sub-control board 330 is performed, and the decrement stops when the counter reaches 0.

(Step S1200)
The sub-CPU 330a analyzes the command stored in the receive buffer of the sub-RAM 330c, and performs various processes according to the received command. When a command is transmitted from the main control board 300, the sub-control board 330 performs a command reception interrupt process, and the command transmitted from the main control board 300 is stored in the receive buffer. Here, the command stored in the receive buffer is analyzed by the command reception interrupt process.

(Step S1100-7)
The sub-CPU 330a performs a time schedule management process that refers to a time table and executes a process corresponding to the time stored in the time table. Here, based on the timer data set in the time table, various flags are turned on or off, or commands are sent to each performance device, thereby controlling the execution of each performance, including the variable performance and the major role performance.

(Step S1100-9)
The sub-CPU 330a restores the registers and ends the sub-timer interrupt process.

Figure 71 is a flowchart explaining the look-ahead designation command reception process for the reference performance example that is executed when a look-ahead designation command is received, part of the command analysis process. As described above, the look-ahead designation command (look-ahead designation variable pattern command) is set in the main control board 300 in the performance determination process at the time of acquisition (steps S536-21, S536-25, and S536-27 in Figure 33), and then transmitted to the sub-control board 330 by the sub-command transmission process (step S100-65 in Figure 23).

(Step S1210-1)
The sub-CPU 330a first analyzes the received read-ahead designation command.

(Step S1210-3)
The sub-CPU 330a stores the advance judgment information based on the analysis result of the above step S1210-1. The sub-RAM 330c of the sub-control board 330 is provided with a first advance judgment information storage unit corresponding to the first special chart reserved storage area of the main control board 300, and a second advance judgment information storage unit corresponding to the second special chart reserved storage area. The first advance judgment information storage unit has four storage units, the first storage unit to the fourth storage unit. The first storage unit to the fourth storage unit of the first advance judgment information storage unit correspond to the first storage unit to the fourth storage unit of the first special chart reserved storage area, respectively. Similarly, the second advance judgment information storage unit has four storage units, the first storage unit to the fourth storage unit, and the first storage unit to the fourth storage unit of the second advance judgment information storage unit correspond to the first storage unit to the fourth storage unit of the second special chart reserved storage area, respectively. Here, the pre-determination information is stored in the memory section corresponding to the memory section in which the newly reserved item is stored, among the first memory section to the fourth memory section of the first special chart reservation memory area or the second special chart reservation memory area of the main control board 300.

(Step S1210-5)
The sub-CPU 330a performs a final hold display pattern determination process to determine the final display pattern of the hold display 212. Here, based on the received look-ahead designation command, the final hold display pattern determination table (FIG. 68(a)) is referenced, and the final display pattern of the hold display 212a is determined and stored.

(Step S1210-7)
The sub-CPU 330a derives the number of times to determine the display pattern of the reserved display 212, i.e., the change timing of the reserved display 212, based on the storage unit in which the reserved is stored, and determines the display pattern of the reserved display 212 by referring to the previous reserved display pattern determination table (FIG. 68(b)) for the derived number of times. Then, the display pattern information of the reserved display 212 thus determined is stored in a predetermined storage unit, and the process proceeds to step S1210-9.

(Step S1210-9)
Based on the determinations in steps S1210-5 and S1210-7, the sub-CPU 330a performs a hold display start process to start displaying the hold display 212, and ends the read-ahead designation command reception process. As a result, when the hold is stored, the display of the corresponding hold display 212 is started.

Figure 72 is a flowchart explaining the variable command receiving process executed when a variable command is received, which is part of the command analysis process for the reference example. As described above, the variable command is set in the special symbol variable number determination process (steps S612-13, S612-17 in Figure 39) in the main control board 300, and then transmitted to the sub-control board 330 by the sub-command transmission process (step S100-65 in Figure 23).

(Step S1220-1)
When a variation command is received, the sub-CPU 330a first analyzes and stores the received variation pattern command.

(Step S1220-3)
The sub-CPU 330a acquires the performance random number (0 to 249) updated in the above step S1000-3, and determines and stores the execution pattern of the variable performance in the latter half based on the acquired performance random number and the analysis result in the above step S1220-1.

(Step S1220-5)
The sub-CPU 330a analyzes and stores the received variation mode command.

(Step S1220-7)
The sub-CPU 330a acquires the performance random number (0 to 249) updated in the above step S1000-3, and determines and stores the execution pattern of the variable performance for the first half based on the acquired performance random number and the analysis result in the above step S1220-5.

(Step S1220-9)
The sub-CPU 330a obtains the performance random number (0 to 249) updated in step S1000-3 for each preview performance, and based on the obtained performance random number and the analysis results in steps S1220-1 and S1220-5, refers to each preview performance decision table to determine whether or not to execute each preview performance and the execution pattern, and stores the same.

(Step S1220-11)
The sub-CPU 330a executes a shift process to shift the pre-determination information stored in the pre-determination information storage unit. Here, when starting a variable performance based on the special 1 reservation, the pre-determination information stored in the fourth storage unit to the second storage unit of the first pre-determination information storage unit is shifted to the third storage unit to the first storage unit of the first pre-determination information storage unit, respectively, and when starting a variable performance based on the special 2 reservation, the pre-determination information stored in the fourth storage unit to the second storage unit of the second pre-determination information storage unit is shifted to the third storage unit to the first storage unit of the second pre-determination information storage unit, respectively.

(Step S1220-13)
The sub-CPU 330a performs a reservation display shift process to move and display the reservation display 212. In addition, here, when the display pattern of the reservation display 212 is to be changed, execution data for changing the display pattern at a predetermined timing is set.

(Step S1220-15)
The sub-CPU 330a sets the timer data of the time table based on the decision of each step above, and ends the variable command receiving process. Based on the time table set here, in the above step S1100-7, the process of displaying the image for the variable performance on the main performance display unit 200a, the sound output process, the lighting control process of the performance lighting device 204, and other performance execution control are performed.

<Slot Machine 400>
73 and 74, a slot machine 400 as a gaming machine is provided with a housing 402 with an open front, and an upper front door 404 and a lower front door 406 which are rotatably arranged vertically side by side at one end of the front of the housing 402. A colorless and transparent symbol display window 408 made of a glass plate, a transparent resin plate or the like is provided at approximately the center of the lower part of the upper front door 404, and three reels 410 (left reel 410a, center reel 410b, right reel 410c) are provided at positions corresponding to the symbol display window 408 in the housing 402 so as to be rotatable independently of each other. As shown in the pattern arrangement in Figure 75 (a), multiple types of patterns are arranged in each of 20 equal areas on the outer peripheral surfaces of the left reel 410a, center reel 410b, and right reel 410c, and the player can view a total of nine patterns, three consecutive patterns located on the top, middle, and bottom rows of the left reel 410a, center reel 410b, and right reel 410c, through the pattern display window 408.

An operation unit installation stand 412 is formed on the top of the front lower door 406, and is provided with a medal insertion unit 414, a bet switch 416, a start switch 418, a stop switch 420, a performance switch 422, and the like. The medal insertion unit 414 accepts medals inserted as game value through a medal insertion port 414a. The bet switch 416 inserts (bet) a specified number of medals required for one game from among the medals electrically stored inside the slot machine 400 (hereinafter simply referred to as credits).

The start switch 418 is, for example, a lever that can detect tilting operation, and detects the start operation of the game by the player. The stop switches 420 (stop switch 420a, stop switch 420b, stop switch 420c) are provided corresponding to the left reel 410a, the center reel 410b, and the right reel 410c, respectively, and detect the stop operation by the player. Note that when the stop switch 420 can be stopped, the first stop is when the player operates one of the stop switches 420a, 420b, and 420c to stop, and after the first stop, the second stop is when the player operates one of the two stop switches 420 that have not been stopped, and after the second stop, the third stop is when the player operates the last remaining stop switch 420 to stop. The effect switch 422 is, for example, a push switch and a jog dial switch arranged around it so that it can rotate freely, and detects the push operation and rotation operation by the player.

A liquid crystal display unit 424 that displays various images associated with the performance is provided approximately in the center of the top of the upper front door 404. Performance lamps 426, for example consisting of high-brightness light-emitting diodes (LEDs), are provided at the top and left and right of the upper front door 404. Speakers 428 that provide auditory performances using sound effects, musical tones, etc. are provided at the left and right positions of the liquid crystal display unit 424 on the back surface of the upper front door 404 and at the left and right positions on the back surface of the lower front door 406.

The operation unit installation stand 412 is provided with a main credit display unit 430 and a main payout display unit 432. In addition, a sub-credit display unit 434 and a sub-payout display unit 436 are provided between the symbol display window 408 and the operation unit installation stand 412. The main credit display unit 430 and the sub-credit display unit 434 display the number of medals credited (number of credits), and the main payout display unit 432 and the sub-payout display unit 436 display the number of medals paid out.

Below the reels 410 in the housing 402, a medal payout device (medal hopper) 442 is provided for paying out medals from a medal discharge port 440a. In addition, at the lower front part of the front lower door 406, a receiving tray 440 is provided for storing medals paid out from the medal discharge port 440a. Also, a power switch 444 is provided inside the housing 402. The power switch 444 is operated by an administrator who manages the slot machine 400, and is used to switch between two states: a power-off state and a power-on state.

In addition, inside the housing 402, a setting key and a setting change switch (collectively referred to as a setting value setting means) (not shown) are provided on the main control board 500 described later. In the slot machine 400, when a predetermined key (operation key) is inserted into the setting key and turned from the OFF position to the ON position, and the power is turned on via the power switch 444, the slot machine 400 transitions to a setting change mode, and the setting value can be changed (also simply referred to as a setting change). The setting value indicates the degree of advantage (machine odds) of the player in stages, and is expressed in six stages, for example, from 1 to 6. In general, the setting value is set so that the higher the numerical value of the setting value, the higher the degree of advantage in the game as a whole (the higher the expected number of coins to be won). Then, each time the setting change switch is pressed in a state in which the setting can be changed, the setting value is incremented by one, and the setting value is changed to one of the six setting values, for example, and when the start switch 418 is operated, the setting value is confirmed, and the setting key is returned to its original position (OFF position), ending the setting change mode and enabling play. Note that settings can only be changed for a certain period of time after the power switch 444 is operated to turn on the power.

In the slot machine 400, when a game can be started and a specified number of medals are bet, the active line A is activated and the operation of the start switch 418 is activated. Here, the bet includes the case where the medals credited through the operation of the bet switch 416 are inserted, the case where the medals are inserted through the medal insertion section 414, and the case where the medals are automatically inserted based on the replay role displayed on the active line A, which will be described in detail later. The active line A is a line for determining the winning of the winning role, and in this embodiment, there is one line. As shown in FIG. 75(b), the active line A is set to a line connecting the positions corresponding to the symbols stopped in the middle row of the left reel 410a, the middle row of the middle reel 410b, and the top row of the right reel 410c among the nine symbols (three reels x three rows: top, middle, and bottom) facing the symbol display window 408. Invalid lines are lines other than the valid line A that are not used to determine whether a winning combination has been won, and which display other symbol combinations that make it easier to determine the winning combination when it is difficult to determine the winning combination based on the symbol combination displayed on the valid line A alone. In this embodiment, the five invalid lines B1, B2, B3, C1, and C2 shown in FIG. 75(b) are assumed.

When the player operates the start switch 418, the game begins, the left reel 410a, the center reel 410b, and the right reel 410c are spun, and a lottery for a winning type is executed. After that, the left reel 410a, the center reel 410b, and the right reel 410c are stopped according to the operation of the stop switches 420a, 420b, and 420c. Then, if a winning combination that can receive a medal payout is won based on the result of the lottery for a winning type and the combination of the symbols displayed on the active line A, the medal is paid out. If a winning combination that can receive a medal payout is not won or if a winning type that can receive a medal payout is won but not won, the game ends when the left reel 410a, the center reel 410b, and the right reel 410c all stop.

In this embodiment, the above-mentioned one game refers to a game from when a medal is inserted through the medal insertion section 414, when a credited medal is inserted through the operation of the bet switch 416, or when a medal is automatically inserted based on a replay role being displayed on the active line A, until the left reel 410a, middle reel 410b, and right reel 410c are controlled to rotate and a winning type lottery is executed in response to the player's operation of the start switch 418, and the left reel 410a, middle reel 410b, and right reel 410c corresponding to the operated stop switch 420a, 420b, 420c are controlled to stop in response to the result of the winning type lottery and the player's operation of the multiple stop switches 420a, 420b, and 420c, and if a winning role that may be awarded with a medal is won, the medal is paid out. In addition, if a player does not win a prize type that can receive a medal payout, or if a player wins but does not win a prize, one game ends when the left reel 410a, center reel 410b, and right reel 410c all come to a halt. However, the start of one game may be interpreted as the player operating the start switch 418 instead of the insertion of a medal or winning a replay role. The number of times such a game is repeated is defined as the number of games.

Figure 76 is a block diagram showing the schematic electrical configuration of the slot machine 400. As shown in Figure 76, the slot machine 400 is provided with a control board including a main control board 500 (main control unit) that controls the progress of the game, and a sub-control board 502 (sub-control unit) that controls the presentation according to the progress of the game. In addition, the transmission of electrical signals between the main control board 500 and the sub-control board 502 is limited to one direction only, from the main control board 500 to the sub-control board 502, from the viewpoint of preventing fraud, etc.

(Main control board 500)
The main control board 500 has semiconductor integrated circuits including a main CPU 500a which is a central processing unit, a main ROM 500b in which programs and the like are stored, and a main RAM 500c which functions as a work area, and generally controls the entire slot machine 400. Note that even if the power is cut off, the main RAM 500c retains data without erasing it, unless a setting change is made and the RAM is cleared.

The main control board 500 also has functional units such as an initialization means 600, a betting means 602, a winning type selection means 604, a reel control means 606, a determination means 608, a payout control means 610, a game status control means 612, a presentation status control means 614, and a command transmission means 616, which function when the main CPU 500a cooperates with the main RAM 500c based on a program stored in the main ROM 500b.

The main control board 500 receives various detection signals from the medal insertion detection unit 414b, which detects the insertion of medals into the medal insertion slot 414a, the bet switch 416, the start switch 418, and the stop switches 420a, 420b, and 420c, and the main CPU 500a executes various processes based on the received detection signals.

The initialization means 600 executes initialization processing on the main control board 500. The betting means 602 bets medals to be used in the game. The winning type selection means 604 performs a winning type selection based on the operation of the start switch 418, as will be described in detail later, to determine whether or not a winning role has been won, and more specifically, whether or not a winning type that includes a winning role has been won.

The reel control means 606 controls the rotation of the left reel 410a, middle reel 410b, and right reel 410c in response to the operation of the start switch 418, and controls the stopping of the corresponding left reel 410a, middle reel 410b, and right reel 410c in response to the operation of the stop switches 420a, 420b, and 420c corresponding to the rotating left reel 410a, middle reel 410b, and right reel 410c, respectively. In addition, the reel control means 606 may extend the time from enabling the operation of the stop switches 420a, 420b, 420c in the previous game to enabling the operation of the stop switches 420a, 420b, 420c by the player to display the lottery result of the winning type lottery (disabled by completing the operation of the stop switches 420a, 420b, 420c in the previous game) to a specified time in response to the operation of the start switch 418, and during that time, perform a reel effect (freeze effect) in which the reels 410a, 410b, 410c are rotated in various ways. The reel effect can be realized by not enabling any switch that should be enabled for a specified time, suspending a process that should be executed for a specified time, or not transmitting or receiving a signal of any switch that should be transmitted or received for a specified time.

The reel drive control unit 450 is also connected to the main control board 500. This reel drive control unit 450 drives the stepping motor 452 based on the rotation start signal for the left reel 410a, center reel 410b, and right reel 410c sent from the reel control means 606 in response to the operation signal of the start switch 418. The reel drive control unit 450 also stops the driving of the stepping motor 452 based on the stop signal for each of the left reel 410a, center reel 410b, and right reel 410c and the detection signal of the rotation position detection circuit 454 sent from the reel control means 606 in response to the operation signal of the stop switch 420.

The determination means 608 determines whether or not a symbol combination corresponding to a winning role has been displayed on the pay line A. Here, the display of a symbol combination corresponding to a winning role on the pay line A may simply be referred to as winning. The payout control means 610 pays out medals in the number (value amount) corresponding to the winning role based on the fact that a symbol combination corresponding to a winning role has been displayed on the pay line A (winning). In addition, the medal payout device 442 is connected to the main control board 500, and the payout control means 610 dispenses medals while counting the number of medals paid out.

The game state control means 612 refers to the result of the winning type lottery and the judgment result of the judgment means 608, and transitions the game state to one of multiple game states. The presentation state control means 614 refers to the result of the winning type lottery, the judgment result of the judgment means 608, and transition information of the game state, and transitions the presentation state to one of multiple presentation states.

The command transmission means 616 sequentially determines game-related commands associated with the operation of the betting means 602, the winning type selection means 604, the reel control means 606, the determination means 608, the payout control means 610, the game state control means 612, the presentation state control means 614, etc., and sequentially transmits the determined commands to the sub-control board 502.

The main control board 500 is also provided with a random number generator (random number generating means) 500d. The random number generator 500d sequentially increments the count value, loops it within a predetermined numerical range, and extracts the count value at a predetermined point in time to obtain a random number. The random number generated by the random number generator 500d of the main control board 500 (hereinafter referred to as the winning type lottery random number) is used to determine the gaming benefit to be awarded to the player, for example, the winning type by the winning type lottery means 604.

(Sub-control board 502)
Similarly to the main control board 500, the sub-control board 502 has various semiconductor integrated circuits including a sub-CPU 502a which is a central processing unit, a sub-ROM 502b which stores programs and the like, and a sub-RAM 502c which functions as a work area, and controls the performance, in particular, based on commands from the main control board 500. Similarly to the main RAM 500c, the sub-RAM 502c is also connected to a backup power supply (not shown), so that data is retained without being erased even if the power supply is cut off. Similarly to the main control board 500, the sub-control board 502 is also provided with a random number generator (random number generating means) 502d, and the random numbers generated by the random number generator 502d (hereinafter referred to as performance lottery random numbers) are mainly used to determine the mode of the performance.

In addition, the sub-control board 502 has functional units such as an initialization determination means 630, a command receiving means 632, and a performance control means 634, which function in cooperation with the sub-RAM 502c based on the program stored in the sub-ROM 502b.

The initialization determination means 630 executes the initialization process in the sub-control board 502. The command receiving means 632 receives commands from other control boards such as the main control board 500, and processes the commands. The performance control means 634 receives a detection signal from the performance switch 422, and determines the performance of the game performed by each device of the liquid crystal display unit 424, the speaker 428, and the performance lamp 426 based on the received command. Specifically, the performance control means 634 determines image data to be displayed on the liquid crystal display unit 424, lighting data for the performance through lighting devices such as the performance lamp 426, the sub-credit display unit 434, and the sub-payout display unit 436, and determines audio data constituting the sound to be output from the speaker 428. Then, the performance control means 634 executes the performance of the determined game. In addition, the performance also includes auxiliary performance. The auxiliary effect is an effect that notifies the player of the correct operation mode of the stop switches 420a, 420b, and 420c, which is the winning condition for the correct role, when a selected winning type in which a correct role (specific role) and an incorrect role overlap in a winning type lottery is won. This auxiliary effect allows the player to easily display the symbol combination corresponding to the correct role on the pay line A. The performance state in which this auxiliary effect is executed is called an AT (assist time) performance state. In addition, a so-called ART game state in which the AT performance state and an RT (replay time) game state, in which the probability of winning a replay role is high, are carried out in parallel, may also be used.

In the following, notification means managed by boards other than the main control board 500, including the sub-control board 502, such as the LCD display unit 424, performance lamps 426, speaker 428, sub-credit display unit 434, and sub-payout display unit 436, may be referred to as other notification means. In contrast, notification means managed by the main control board 500, such as the main credit display unit 430 and main payout display unit 432, may be referred to as main notification means (instruction monitor). In addition, the main notification means and other notification means capable of executing auxiliary performances may be collectively referred to as auxiliary performance execution means. The performance state control means 614 causes the auxiliary performance execution means to execute the auxiliary performance in the AT performance state.

(Table used in main control board 500)
FIG. 77 is an explanatory diagram for explaining a winning combination, and FIG. 78 and FIG. 79 are explanatory diagrams for explaining a winning type selection table.

As described in detail below, the slot machine 400 has multiple game states and presentation states, and the game states and presentation states are changed according to the progress of the game. In the main control board 500, multiple winning type lottery tables and the like corresponding to the game states managed and controlled by the game state control means 612 are stored in the main ROM 500b. The winning type lottery means 604 extracts the corresponding winning type lottery table from the main ROM 500b according to the current setting value (which indicates the easiness of obtaining a game profit in stages) stored in the main RAM 500c and the current game state, and determines which winning type in the winning type lottery table corresponds to the winning type lottery random number obtained according to the operation signal of the start switch 418 based on the extracted winning type lottery table.

Here, the winning roles that make up the winning types extracted in the winning type lottery table include a replay role, a small role, and a bonus role. A replay role is a role that allows the player to play again without placing a new medal bet when a symbol combination corresponding to the replay role is displayed on the active line A. A small role is a role that allows the player to receive a predetermined number of medals according to the symbol combination when a symbol combination corresponding to the small role is displayed on the active line A. A bonus role is a role that allows the game state managed by the game state control means 612 to transition to a bonus game state (a game state during RBB operation described later) when a symbol combination corresponding to the bonus role is displayed on the active line A.

As shown in FIG. 77, the winning roles in this embodiment include replay roles "Replay 1" to "Replay 7". In addition, the winning roles "Small Role 1" to "Small Role 39" are provided as small roles. In addition, the winning role "RBB" is provided as a bonus role. In FIG. 77, one or more symbols constituting each winning role are associated with the left reel 410a, the center reel 410b, and the right reel 410c.

Here, in this embodiment, when the stop switch 420 is operated by the player, if the symbols constituting the symbol combination corresponding to a possible winning combination are on the active line A, the reel control means 606 performs stop control so that the symbols stop on the active line A. Also, when the stop switch 420 is operated, if the symbols constituting the symbol combination corresponding to a possible winning combination are not on the active line A but are within a range equivalent to four symbol frames in the opposite direction to the rotation direction of the reel 410 (pulling-in range), the reel control means 606 performs stop control so that the number of separated symbols becomes the number of sliding frames, and the symbols constituting the symbol combination corresponding to the winning combination are pulled onto the active line A and then stopped after maintaining rotation for the number of sliding frames. In addition, when there are multiple symbols corresponding to winning combinations that can win prizes on the reel 410 and all of them are within the reel-in range of the reel 410, it is determined which symbol to reel in to the pay line A according to a predetermined priority order, and the stop control is performed so that the prioritized symbol is stopped after maintaining rotation for the number of sliding frames so as to reel in the winning line A. In addition, when the stop switch 420 is pressed, if a symbol constituting a symbol combination corresponding to a winning combination other than a winning combination that can win prizes is on the winning line A, the reel control means 606 also executes a so-called kicking process in parallel to prevent the symbol from stopping on the winning line A. In addition, as described later, when an operation mode (operation order or operation timing) is set as a winning condition for a winning combination included in a winning type, the reel control means 606 controls the stop so that the symbol combination corresponding to the winning combination can be displayed on the winning line A according to the operation mode of the player.

For example, the symbols constituting the symbol combinations corresponding to the winning roles "Replay 1" to "Replay 4", "Small Role 1" to "Small Role 6", and "Small Role 35" to "Small Role 39" are arranged on each reel 410 so that they can always be displayed on the pay line A by the above-mentioned stop control. Such a winning role may be expressed as PB=1. On the other hand, for example, the symbols constituting the symbol combinations corresponding to the winning roles "Replay 5" to "Replay 7", "Small Role 7" to "Small Role 34", and "RBB" are not always arranged on each reel 410 so that they can always be displayed on the pay line A by the above-mentioned stop control, so so-called missed wins may occur. Such a winning role may be expressed as PB≠1.

As shown in Figures 78 and 79, the winning type lottery table divides multiple winning areas, and the winning types that are the subject of the lottery vary depending on each game state, and the presence or absence of non-winning (missing) varies. In Figures 78 and 79, the winning areas (winning types) assigned to each game state (non-internal game state (non-internal), game state while inside RBB (while inside RBB), game state while RBB is operating (RBB operating)) are represented by "◎" or "○", but in reality, a winning type lottery table corresponding to each of the multiple game states is stored in the main ROM 500b. Note that "◎" indicates a winning type that allows the lottery of an advantageous zone for which a lottery for moving to an advantageous zone can be held, and "○" indicates a winning type that does not allow the lottery of moving to an advantageous zone for which a lottery for moving to an advantageous zone cannot be held.

In the winning type lottery table, each partitioned winning area is associated with a predetermined number of entries (winning range value), which is a numerical value indicating the winning range, and a winning type. The total number of entries in all winning areas assigned to each game state is the total number of winning type lottery random numbers (65536). Therefore, the probability of each winning type being determined is the value obtained by dividing the number of entries associated with the winning area by the total number of winning type lottery random numbers. The winning type lottery means 604 sequentially obtains the number of entries from the multiple winning areas in the winning type lottery table starting with the highest number based on the game state at that time, subtracts the number of entries from the winning type lottery random number, and if the value after subtraction is less than 0, the winning type associated with the winning area at that time is the lottery result of the winning type lottery. Also, if the number of entries in all winning areas 1 or more are subtracted from the winning type lottery random number and the value after subtraction is 0 or more, the winning type "miss" of winning area 0 is the lottery result of the winning type lottery.

Here, we will add some details about the winning role "RBB" that constitutes the winning type "RBB". The specified first-class special role RB is a role that increases the number of combinations of symbols related to winning for each specified number, or increases the probability of the condition device related to winning for each specified number activating, and is activated in a predetermined case and can continue to operate until the result of the game is obtained not more than 12 times. Here, the condition device is a device whose operation is a necessary condition for the display of a combination of symbols related to winning, replay, the operation of a role, or the operation of a role continuous operation device, and is activated when a winning type lottery (a lottery by a computer performed in the gaming machine) is won, that is, it means a winning flag. And the role continuous operation device related to the first-class special role that constitutes the winning type "RBB" (winning role "RBB") is a device that can continuously operate the first-class special role RB, and is activated when a specific combination of symbols is displayed and ends its operation in a predetermined case.

According to the winning type lottery table in FIG. 78, for example, winning area 0 is associated with the winning type "miss", and when this winning type is won, the symbol combination corresponding to any of the winning roles shown in FIG. 77 will not be displayed on the active line A, and no medals will be paid out. However, as described below, if the RBB internal winning flag is carried over to the next game, winning the winning type "miss" makes it possible to display the symbol combination corresponding to the winning role "RBB" on the active line A.

In addition, winning area 1 is associated with a winning type "small win ALL" which includes overlapping winning roles "small win 1" to "small win 39", winning area 2 is associated with a winning type "1 coin ALLA" which includes overlapping winning roles "small win 11" to "small win 39", and winning area 3 is associated with a winning type "1 coin ALLB" which includes overlapping winning roles "small win 12" to "small win 27". In addition, winning area 4 is associated with a winning type "1 choice 1" which includes the overlapping winning roles "small role 12" and "small role 20", winning area 5 is associated with a winning type "1 choice 2" which includes the overlapping winning roles "small role 13" and "small role 21", winning area 6 is associated with a winning type "1 choice 3" which includes the overlapping winning roles "small role 14" and "small role 22", and winning area 7 is associated with a winning type "1 choice 4" which includes the overlapping winning roles "small role 15" and "small role 23". In addition, the winning area 8 is associated with a winning type "weak cherry" which includes the overlapping winning roles "small role 35" and "small role 36", the winning area 9 is associated with a winning type "strong cherry" which includes the overlapping winning roles "small role 37" to "small role 39", the winning area 10 is associated with a winning type "watermelon A" which includes the overlapping winning roles "small role 7", "small role 8", and "small role 11", the winning area 11 is associated with a winning type "watermelon B" which includes the overlapping winning roles "small role 7" to "small role 10", and the winning area 12 is associated with a winning type "strong bell" which includes the overlapping winning roles "small role 1", "small role 3", and "small role 5". In addition, winning area 13 is associated with a winning type "common bell A" that includes the winning roles "small role 1" to "small role 6" in overlapping fashion, and winning area 14 is associated with a winning type "common bell B" that includes the winning roles "small role 1" to "small role 6" and "small role 11" in overlapping fashion.

In addition, winning regions 15 to 26 are associated with selected winning types (winning types "Batting Order Bell 1A" to "Batting Order Bell 6A" and "Batting Order Bell 1B" to "Batting Order Bell 6B") that overlap correct roles with a payout of 11 coins (winning roles "Small Role 1" to "Small Role 6") and incorrect roles with a payout of 1 coin (winning roles "Small Role 12" to "Small Role 34").

According to the winning type selection table in FIG. 79, winning areas 27 to 39 are associated with winning types "Symbol Replay A1" to "Symbol Replay A7" and "Symbol Replay B1" to "Symbol Replay B6", which include overlapping winning roles "Replay 1" to "Replay 7". Furthermore, winning area 40 is associated with the winning type "Normal Replay", which includes overlapping winning roles "Replay 1" and "Replay 2".

In addition, winning regions 41 to 46 are associated with winning types "RBB1" to "RBB6" that include the winning combination "RBB" alone or in combination with other minor combinations.

When a winning type that includes multiple overlapping winning combinations is won, the winning conditions for which symbol combination corresponding to each winning combination is preferentially displayed on the pay line A are set, for example, the order in which the stop switches 420a, 420b, and 420c are operated.

In the following description, the operation of the stop switches 420a, 420b, and 420c that stop the reels in the order of left reel 410a, center reel 410b, and right reel 410c is referred to as "batting order 1", the operation of the stop switches 420a, 420b, and 420c that stop the reels in the order of left reel 410a, right reel 410c, and center reel 410b is referred to as "batting order 2", and the operation of the stop switches 420a, 420b, and 420c that stop the reels in the order of center reel 410b, left reel 410a, and right reel 410c is referred to as "batting order 3". " The operation of the stop switches 420a, 420b, 420c that stop the reels in the order of center reel 410b, right reel 410c, and left reel 410a is "batting order 4", the operation of the stop switches 420a, 420b, 420c that stop the reels in the order of right reel 410c, left reel 410a, and center reel 410b is "batting order 5", and the operation of the stop switches 420a, 420b, 420c that stop the reels in the order of right reel 410c, center reel 410b, and left reel 410a is "batting order 6".

For example, in a non-internal game state, when the winning type "batting order bell 1A" in the winning area 15 is won and an operation is performed according to the correct operation mode (batting order 1), the stop control is performed so that the symbol combination corresponding to the winning role "small role 1", which is a correct role with a payout of 11 coins, is preferentially displayed on the valid line A. Also, when an operation is performed according to batting order 2, the stop control is performed so that the symbol combination corresponding to the winning role "small role 28", which is an incorrect role with a payout of 1 coin, is preferentially displayed on the valid line A. When an operation is performed according to batting orders 3 and 4, the stop control is performed so that the symbol combination corresponding to the winning role "small role 12", which is an incorrect role with a payout of 1 coin, is preferentially displayed on the valid line A with a probability of 1/4. When an operation is performed according to batting orders 5 and 6, the stop control is performed so that the symbol combination corresponding to the winning role "small role 16", which is an incorrect role with a payout of 1 coin, is preferentially displayed on the valid line A with a probability of 1/4.

The probability of winning (number of pieces placed) for each winning type in winning areas 15-26 is set to be equal. Since players usually cannot know which winning type they have won, providing winning areas 15-26 as described above makes it difficult for correct combinations to win. Also, as described above, even if stop switches 420a, 420b, 420c are operated in a hitting order that prioritizes the display of incorrect combinations, it is not necessarily possible to display the symbol combination corresponding to the incorrect combination on the pay line A, so depending on the manner of operation, a miss may occur (PB ≠ 1).

When any of the above winning types is won, the internal winning flag corresponding to the winning type is established (ON), and the stop control of each reel 410 is performed according to the establishment status of the internal winning flag. At this time, if a winning type including a small role is won, but the symbol combination corresponding to the winning role cannot be displayed on the active line A during the game, the internal winning flag is turned OFF after the game ends. In other words, the right to win a small role is limited only to the game in which the winning type including a small role is won, and the right cannot be carried over to the next game. On the other hand, when a winning type including the winning role "RBB" is won, the RBB internal winning flag is established (ON), and the RBB internal winning flag is carried over across games until the symbol combination corresponding to the winning role "RBB" is displayed on the active line A. In addition, when an internal win flag corresponding to a win type that includes a replay role is established, a symbol combination corresponding to one of the replay roles included in that win type is always displayed on the active line A, and after the processing required to play the next game without requiring a medal is performed, the internal win flag is turned OFF.

(Game state transition)
Here, the transition of the game state will be explained using FIG. 80. Here, a plurality of game states are prepared, such as a non-internal game state, an internal RBB game state, and an RBB operation game state. As described later, each game state is transitioned according to the winning of a bonus role, winning (operation), and ending.

The non-internal game state is a game state that corresponds to the initial state among multiple game states. In such a non-internal game state, the probability of winning a replay role is set to approximately 1/7.3. In addition, in the non-internal game state, the winning role "RBB" is determined with a predetermined probability (for example, approximately 1/30).

The game state control means 612 transitions the game state in response to the winning combination "RBB". For example, in a game in which the winning combination "RBB" is won, when a symbol combination corresponding to the winning combination "RBB" is displayed on the active line A, the game state control means 612 transitions the game state to a game state in which RBB is active (1).

In the RBB-activated game state, the probability of winning a replay role is set to 0. In this RBB-activated game state, the possible winning types are set as "small role ALL" in the winning area 1, and "1-piece ALLA" and "1-piece ALLB" in the winning areas 2 and 3. When the "small role ALL" winning type is won, a symbol combination corresponding to one of the winning roles "small role 1" to "small role 39" is displayed on the active line A, and when the "1-piece ALL" winning type is won, the game is stopped and controlled so that a symbol combination corresponding to one of the winning roles "small role 11" to "small role 39" is displayed on the active line A. Here, the expected number of coins per unit of play in the RBB-activated game state is lowered by the configuration of the small roles.

When the conditions for terminating the RBB-operated game state are met, i.e., when the number of coins won reaches a predetermined number, the game state control means 612 transitions the game state to a non-internal game state (2).

On the other hand, in a game in which the winning combination "RBB" is won, if the symbol combination corresponding to the winning combination "RBB" cannot be displayed on the active line A, the game state control means 612 transitions the game state to an RBB internal game state (special game state) (3).

In the RBB internal game state, the probability of winning a replay role is set to approximately 1/5.9. Also, in the RBB internal game state, the winning type "miss" cannot be won. In other words, if the symbol combination corresponding to the winning role "RBB" cannot be displayed on the active line A in the winning game of the winning role "RBB", the symbol combination corresponding to the winning role "RBB" cannot be displayed on the active line A after that, since the minor role and the replay role are controlled to stop on the active line A in priority to the winning role "RBB". Therefore, once the game state transitions to the RBB internal game state, the RBB internal game state is maintained without any transition of the game state. Here, while maintaining such an RBB internal game state, the AT performance state is realized in the RBB internal game state.

Here, in the RBB internal game state, multiple types of correct roles are won without overlapping with each other, so the chances of winning a correct role can be increased, and as a result, for example, by performing an auxiliary performance in the AT performance state in the RBB internal game state, medals can be easily won. On the other hand, in the RBB operation game state, multiple types of correct roles are won in overlapping, so there are fewer chances of winning a correct role, and therefore there are fewer chances of winning a correct role than in the AT performance state in other game states, making it difficult for the player to increase the medals he owns. Therefore, it is possible to realize a specification (accelerator RBB) in which the RBB operation game state is inferior to the RBB internal game state in terms of medal winning performance, while having the function of the RBB operation game state in which the winning role related to winning is higher than in the RBB internal game state.

(Transition of performance state)
81 is an explanatory diagram for explaining the transition of the presentation state. Below, the presentation state (non-AT presentation state, AT presentation state) that is transitioned by the presentation state control means 614 in the main control board 500 will be described in detail. In addition, the following will explain the case where the game state is the game state inside the RBB.

Here, in order to comprehensively and uniformly determine whether or not the game state with high medal acquisition performance is biased, a game area that has a performance related to the instruction function, that is, a game area that is advantageous to the player, including a game area that executes an auxiliary performance (instruction function), is defined as an advantageous area (specific area). Note that the advantageous area is a game area in which instruction information may be sent to a peripheral board such as the sub-control board 502 only when the instruction content is displayed on the main notification means, for example, so that the main control board 500 can identify the instruction content when the auxiliary performance is activated as a result of a lottery or the like related to the activation of the auxiliary performance on the main control board 500. In addition, a game area different from the advantageous area is defined as a non-advantageous area. Therefore, multiple performance states (non-AT performance state, AT performance state) belong to either the advantageous area or the non-advantageous area, which are game areas. In this embodiment, almost all performance states belong to the advantageous area, and a non-advantageous area is realized in some performance states of the non-AT performance state (here, the non-advantageous performance state).

In addition, in the advantageous zone, among the winning modes in which the correct combination would be missed without the auxiliary effect, in the selected winning type in which the payout for the correct combination is the maximum (here, 11 coins), when an auxiliary effect that assists in winning the correct combination (an auxiliary effect that can obtain the maximum payout number) is performed, this must be notified, for example, by lighting up the zone indicator 460.

In addition, in non-advantageous zones, the probability of winning a type of win can be made different for each setting value, but the probability of deciding to transition to a presentation state with auxiliary effects (AT presentation state) for the same winning type must not be made different for each setting value. On the other hand, in advantageous zones, both the probability of winning a type of win and the probability of deciding to transition (or add) to a presentation state with auxiliary effects (AT presentation state) for the same winning type can be made different for each setting value.

Therefore, the presentation state control means 614 manages the transition of the presentation state, as well as the transition between the non-advantageous zone and the advantageous zone. Regardless of this management, the advantageous zone is forcibly terminated when the following termination conditions are met. For example, the zone is forcibly terminated when the value counted in the advantageous zone reaches a predetermined value (for example, the number of games played during the zone (number of games played) reaches 1,500 games, or the number of coins won (net increase in number of coins) exceeds 2,400). In either case, the presentation state control means 614 resets all information updated in the advantageous zone (all variables that affect the performance related to the instruction function) by transitioning from the advantageous zone to the non-advantageous zone.

(Non-AT performance state, AT performance state)
In the non-AT performance state, the frequency of execution of the auxiliary performance is much lower than in the AT performance state, and the auxiliary performance is almost not performed, so the number of medals that can be acquired is limited. Here, six performance states are provided as the non-AT performance state, such as a normal performance state, a non-advantageous performance state, a preparation performance state, a first interval performance state, a continuous lottery performance state, and a second interval performance state.

In the AT performance state, by having the auxiliary performance execution means execute the auxiliary performance when all selected winning types are won, it is possible to win many medals while reducing medal consumption. Therefore, by transitioning to the AT performance state, the player can play more advantageously than in a non-AT performance state. Here, a pseudo bonus performance state is provided as the AT performance state. Each performance state (normal performance state, pseudo bonus performance state, non-advantageous performance state, preparation performance state, first interval performance state, continuous lottery performance state, second interval performance state) will be explained individually below.

(Each performance state)
The normal presentation state is a presentation state corresponding to the initial state among a plurality of presentation states. The presentation state control means 614 performs an AT lottery in the normal presentation state. The AT lottery is a lottery that determines the transition to the AT presentation state, and the presentation state control means 614 performs an AT lottery with a different probability for each winning type determined by the winning type lottery. Then, when the AT lottery is won, the presentation state control means 614 transitions the presentation state to a pseudo bonus presentation state, which is an AT presentation state, after a predetermined number of premonition games have elapsed (1). Also, when a predetermined ceiling condition (for example, a predetermined number of games played consecutively in the normal presentation state) is satisfied in the normal presentation state without transitioning to the pseudo bonus presentation state (so-called reaching the ceiling), the presentation state control means 614 transitions the presentation state to a pseudo bonus presentation state (1).

In the pseudo bonus presentation state, the auxiliary presentation is executed until a predetermined end condition (for example, the number of games played reaches a predetermined number of games) is met, and the player can obtain, for example, 3.5 expected coins in the pseudo bonus presentation state. In the pseudo bonus presentation state, two end conditions are mainly prepared. For example, if the end condition is that the number of games played reaches a predetermined number of games, two stages are set as the predetermined number of games, 30 and 80, and one of them is determined by lottery. In the pseudo bonus presentation state, the more games played, the more gaming profits the player will obtain. Therefore, the player will want the predetermined number of games to be 80 rather than 30. However, even if 30 is determined as the predetermined number of games, a promotion lottery is also held to increase the predetermined number of games of the auxiliary presentation from 30 to 80 during the number of games. Note that, in this example, the condition for ending the pseudo bonus presentation state is that the number of plays played reaches a predetermined number of plays, but instead, the number of times the auxiliary presentation that can win the maximum payout number reaches a predetermined number, or the number of coins won (net increase in number of coins) reaches a predetermined number.

In the pseudo-bonus presentation state, when a predetermined end condition is satisfied, the presentation state control means 614 may transition the presentation state to a non-advantageous presentation state (2). At this time, the presentation state control means 614 transitions the advantageous section to a non-advantageous section and resets all information updated in the advantageous section. For example, if the previous pseudo-bonus presentation state was the first pseudo-bonus presentation state, that is, if it is a pseudo-bonus presentation state immediately after transition from a normal presentation state, the presentation state control means 614 transitions the presentation state to a non-advantageous presentation state and transitions the advantageous section to a non-advantageous section. Also, if the previous pseudo-bonus presentation state was a pseudo-bonus presentation state that is a multiple of three (3rd, 6th, ...) without passing through the normal presentation state, the presentation state control means 614 transitions the advantageous section to a non-advantageous section and transitions the advantageous section to a non-advantageous section.

Then, the presentation state control means 614 draws a lottery for a transition to the advantageous zone with a high probability (for example, 1/2), and after the number play is completed, returns to the advantageous zone and transitions the presentation state to the preparation presentation state (3). This is to avoid the pseudo bonus presentation state being forcibly terminated when the value counted in the advantageous zone reaches a predetermined value.

On the other hand, if the previous pseudo-bonus presentation state is not the first time, or is not a pseudo-bonus presentation state that is a multiple of three and does not pass through a normal presentation state, the presentation state control means 614 transitions the presentation state directly to the preparation presentation state without transitioning to a non-advantageous presentation state (4). This is to avoid the forced termination of the pseudo-bonus presentation state due to the value counted in the advantageous zone reaching a predetermined value, while also preventing the advantageous zone from being terminated unnecessarily.

In the preparation performance state, the performance state control means 614 draws a lottery for transition to the first interval performance state with a high probability (e.g., 1/2), and transitions the performance state to the first interval performance state based on the decision to transition to the first interval performance state (5).

The first interval presentation state continues until a predetermined end condition (for example, 40 plays are played) is met, during which time a lottery is held to continue the pseudo bonus presentation state. Unlike the pseudo bonus presentation state, the first interval presentation state has a smaller expected number of coins per unit play, and may even be a negative value. In this embodiment, if a favorable zone is won in a non-favorable zone, the presentation state is set to always become the first interval presentation state. Therefore, after the pseudo bonus presentation state ends, the presentation state will transition to the first interval presentation state even if the favorable zone continues or, as described above, if the zone transitions to a non-favorable zone. Then, when a predetermined end condition in the first interval presentation state is met, the presentation state control means 614 transitions the presentation state to a continuation lottery presentation state (6).

The continuation lottery presentation state continues until a predetermined end condition (e.g., five plays are played) is met, and finally, the result of the lottery to continue the pseudo bonus presentation state in the first interval presentation state is announced. Unlike the pseudo bonus presentation state, the continuation lottery presentation state also has a small expected number of coins to be won per unit play in such a state, and may even be a negative value. If a transition (continuation) to the pseudo bonus presentation state has been determined in the first interval presentation state, the presentation state control means 614 transitions the presentation state to the pseudo bonus presentation state (7), and if a transition to the pseudo bonus presentation state has not been determined, the presentation state control means 614 returns the presentation state to the normal presentation state (8).

In this way, in this embodiment, once the pseudo bonus presentation state is entered, the player can accumulate medals by repeating the transition from the pseudo bonus presentation state → preparation presentation state → first interval presentation state → continuation selection presentation state, unless the player misses the continuation selection selection state.

In addition, in the preparation performance state, the performance state control means 614 draws a lottery for transition to the second interval performance state in addition to drawing a lottery for transition to the first interval performance state. However, the probability of transition to the second interval performance state (e.g., 1/20) is set smaller than the probability of transition to the first interval performance state (e.g., 1/2). In the preparation performance state, if a transition to the second interval performance state is determined before a transition to the first interval performance state is determined, the performance state control means 614 transitions the performance state to the second interval performance state based on the decision to transition to the second interval performance state (9). Note that, although an example of drawing a lottery for transition to the second interval performance state in the preparation performance state is given here, a lottery for transition to the second interval performance state may also be drawn in a non-advantageous performance state in a similar manner.

The second interval presentation state, like the first interval presentation state, continues until a predetermined end condition (e.g., 40 plays are played) is met, during which time a lottery is held to continue the pseudo bonus presentation state. Like the first interval presentation state, the second interval presentation state differs from the pseudo bonus presentation state in that the expected number of coins to be won per unit of play is small, and may even be a negative value.

However, the pseudo bonus presentation state is determined with a higher probability in the second interval presentation state than in the first interval presentation state. For example, in the first interval presentation state, the pseudo bonus presentation state is determined every 1/58 of a game for 40 games (50% chance of winning), and in the second interval presentation state, the pseudo bonus presentation state is determined every 1/25 of a game for 40 games (80% chance of winning). Then, when a predetermined termination condition is met, the presentation state control means 614 transitions the presentation state to a continuous lottery presentation state (10). Once the transition to the second interval presentation state is determined, thereafter, there will be no transition to a non-advantageous presentation state, preparation presentation state, or first interval presentation state until the continuous lottery presentation state is missed, and the pseudo bonus presentation state will only transition to the second interval presentation state (11). Therefore, the player can always receive a continuation lottery with a high probability. In addition, once a transition to the second interval presentation state is determined, even if a transition to the pseudo bonus presentation state is not determined in the continuous lottery presentation state, the presentation state control means 614 immediately transitions the presentation state to a non-advantageous presentation state without returning the presentation state to the normal presentation state (12). Therefore, if a transition to the pseudo bonus presentation state is not determined in the continuous lottery presentation state, the transition from the pseudo bonus presentation state to the preparation presentation state to the first interval presentation state to the continuous lottery presentation state can be repeated until the continuation lottery for the continuous lottery presentation state is missed again. In this way, once a transition to the second interval presentation state is made, the transition from the pseudo bonus presentation state to the second interval presentation state to the continuous lottery presentation state can be repeated with a high probability, and further, even if a transition to the pseudo bonus presentation state is not determined in the continuous lottery presentation state, the transition from the pseudo bonus presentation state to the preparation presentation state to the first interval presentation state to the continuous lottery presentation state can at least be repeated again, so that the player can accumulate more medals. In other words, the second interval presentation state can be said to be a more advantageous state than the first interval presentation state.

As described above, when transitioning from the pseudo bonus presentation state to the second interval presentation state, the presentation state control means 614 does not transition to a non-advantageous zone, unlike the transition to the first interval presentation state. In this embodiment, if the pseudo bonus presentation state is the initial pseudo bonus presentation state, the presentation state control means 614 does not transition to the second interval presentation state, but transitions the advantageous zone to a non-advantageous zone once, and always transitions to the first interval presentation state. In this way, the advantageous zone is reset once. Therefore, even if the advantageous zone is not reset when transitioning to the second interval presentation state, the pseudo bonus presentation state that passes through the second interval presentation state will not end in a short period due to the limitation of the advantageous zone, and the player can obtain many medals by looping the pseudo bonus presentation state → second interval presentation state → continuous lottery presentation state.

The specific processing on the main control board 500 and the sub-control board 502 is explained below based on the flowchart.

(CPU Initialization Processing of Main Control Board 500)
82 is a flowchart explaining the CPU initialization process in the main control board 500. When power is supplied from the power supply board, a system reset occurs in the main CPU 500a, and the main CPU 500a performs the following CPU initialization process (S2000).

(Step S2000-1)
When the power is turned on, the main CPU 500a reads a startup program from the main ROM 500b as an initial setting process, and performs setting processes necessary for executing various processes.

(Step S2000-3)
The main CPU 500a sets a wait processing time in a timer counter.

(Step S2000-5)
The main CPU 500a judges whether a power-off warning signal has been detected. The main control board 500 is provided with a power-off detection circuit, which outputs a power-off warning signal when the power supply voltage falls below a predetermined value. If a power-off warning signal has been detected, the process proceeds to step S2000-3, and if a power-off warning signal has not been detected, the process proceeds to step S2000-7.

(Step S2000-7)
The main CPU 500a judges whether the wait processing time set in step S2000-3 has elapsed or not. If it is judged that the wait processing time has elapsed, the process proceeds to step S2000-9, and if it is judged that the wait time has not elapsed, the process proceeds to step S2000-5.

(Step S2000-9)
The main CPU 500a executes the processes required to permit access to the main RAM 500c.

(Step S2000-11)
The main CPU 500a executes a checksum confirmation process. Here, the main CPU 500a calculates a checksum and judges whether the calculated checksum does not match the checksum saved at the time of power off (is abnormal) and whether the backup is abnormal. If the main CPU 500a judges that either or both of the backup and the checksum are abnormal, it turns on the backup abnormality flag, and if it judges that neither the backup nor the checksum are abnormal, it turns off the backup abnormality flag.

(Step S2000-13)
The main CPU 500a determines whether the backup abnormality flag is on. If it is determined that the backup abnormality flag is on, the process proceeds to step S2010, and if it is determined that the backup abnormality flag is not on, the process proceeds to step S2020.

(Step S2010)
The main CPU 500a executes a cold start process, which will be described later.

(Step S2020)
The main CPU 500a executes a setting value switching process for switching the setting value, which will be described later.

(Step S2030)
The main CPU 500a executes a state restoration process to restore the state immediately before the power was turned off, as will be described later.

Figure 83 is a flowchart explaining the cold start processing (S2010) in the main control board 500.

(Step S2010-1)
The main CPU 500a clears the used area in the main RAM 500c and executes a used area RAM check process to detect any abnormalities in the used area.

(Step S2010-3)
The main CPU 500a clears the separate area (unused area) in the main RAM 500c and executes a separate area RAM check process to detect an abnormality in the separate area. If an abnormality is detected in the separate area in the separate area RAM check process, the main CPU 500a turns on a RAM read/write error flag.

(Step S2010-5)
The main CPU 500a sets an error code "EA" indicating an abnormality in the main RAM 500c.

(Step S2010-7)
The main CPU 500a judges whether an abnormality has been detected in the above step S2010-1. If it is judged that an abnormality has been detected in the above step S2010-1, the process proceeds to step S2011, and if it is judged that an abnormality has not been detected in the above step S2010-1, the process proceeds to step S2010-9.

(Step S2010-9)
The main CPU 500a acquires a RAM read/write error flag that is turned on when an abnormality is detected in step S2010-3.

(Step S2010-11)
The main CPU 500a judges whether the RAM read/write error flag is on. If it is judged that the RAM read/write error flag is on, the process proceeds to step S2011, and if it is judged that the RAM read/write error flag is not on, the process proceeds to step S2020.

(Step S2020)
The main CPU 500a executes a setting value switching process for switching the setting value, which will be described later.

(Step S2010-13)
The main CPU 500a sets an error code "E7" indicating a backup error.

(Step S2011)
The main CPU 500a executes an error stop process for stopping the progress of the game due to an error, which will be described later.

Figure 84 is a flowchart explaining the error stop processing (S2011) in the main control board 500.

(Step S2011-1)
The main CPU 500a sets an initial stack pointer value as the address of the stack pointer.

(Step S2011-3)
The main CPU 500a executes an error setting process for displaying an error and setting an alarm sound.

(Step S2011-5)
The main CPU 500a sets the external signal 1-3 output bit OFF, which turns off the output image of the bits corresponding to the external signals 1-3.

(Step S2011-7)
The main CPU 500a executes an output port image set process to update the output image for the bit set in step S2011-5.

(Step S2011-9)
The main CPU 500a goes into a permanent loop, which stops the progress of the game.

Figure 85 is a flowchart explaining the setting value switching process (S2020) in the main control board 500.

(Step S2020-1)
The main CPU 500a acquires a signal from the input port 1, and judges whether the setting value switching condition is satisfied based on the acquired signal from the input port 1. As a result, if it is judged that the setting value switching condition is not satisfied, the setting value switching process is terminated, and if it is judged that the setting value switching condition is satisfied, the process proceeds to step S2020-3. Here, the signal from the input port 1 includes a signal indicating whether the front upper door 404 and the front lower door 406 are opened or not, and a signal indicating whether the setting key is turned on or not. Here, it is judged that the setting value switching condition is satisfied when a signal indicating that the front upper door 404 and the front lower door 406 are opened and a signal indicating that the setting key is turned on are acquired.

(Step S2020-3)
The main CPU 500a executes a RAM clear process to clear areas in the main RAM 500c that should be cleared when the settings are changed.

(Step S2020-5)
The main CPU 500a executes a table content setting process for transferring the table data of the setting value switching data table to the main RAM 500c.

(Step S2020-7)
The main CPU 500a sets in the transmission buffer a setting change start command, which indicates the start of changing the setting value.

(Step S2020-9)
The main CPU 500a executes an edge check process to detect the falling edge (on edge) of the signal at the input port.

(Step S2020-11)
The main CPU 500a obtains setting value data indicating the current setting value.

(Step S2020-13)
The main CPU 500a judges whether the on-edge of the setting change switch has been detected in the above step S2020-9. If it is judged that the on-edge of the setting change switch has not been detected, the process proceeds to step S2020-17, and if it is judged that the on-edge of the setting change switch has been detected, the process proceeds to step S2020-15.

(Step S2020-15)
The main CPU 500a increments the setting value data by one.

(Step S2020-17)
The main CPU 500a judges whether the set value data is within the range (1 to 6) that can be set as a set value. If it is judged that the set value data is within the range, the process proceeds to step S2020-21, and if it is judged that the set value data is not within the range, the process proceeds to step S2020-19.

(Step S2020-19)
The main CPU 500a sets the setting value data to 0.

(Step S2020-21)
The main CPU 500a updates the setting value data to the value incremented or set in step S2020-15 or step S2020-19.

(Step S2020-23)
The main CPU 500 a executes a display data conversion process for displaying the set value in the main credit display section 430 .

(Step S2020-25)
The main CPU 500a judges whether the on-edge of the setting change switch is detected. If it is judged that the on-edge of the setting change switch is not detected, the process proceeds to step S2020-31, and if it is judged that the on-edge of the setting change switch is detected, the process proceeds to step S2020-27.

(Step S2020-27)
The main CPU 500a judges whether the setting change switch is on. If it is judged that the setting change switch is on, the process proceeds to step S2020-27, and if it is judged that the setting change switch is not on, the process proceeds to step S2020-29.

(Step S2020-29)
The main CPU 500a sets a setting value change switch interval timer.

(Step S2020-31)
The main CPU 500a executes a timer wait process to wait until the setting change switch interval timer counts down to 0.

(Step S2020-33)
The main CPU 500a judges whether it has detected an on-edge of the start switch 418. As a result, if it is judged that an on-edge of the start switch 418 has not been detected, the process proceeds to step S2020-9, and if it is judged that an on-edge of the start switch 418 has been detected, the process proceeds to step S2020-35.

(Step S2020-35)
The main CPU 500a judges whether the setting key is OFF. If it is judged that the setting key is OFF, the process proceeds to step S2020-35, and if it is judged that the setting key is not OFF, the process proceeds to step S2020-37.

(Step S2020-37)
The main CPU 500a judges whether the setting key is on. If it is judged that the setting key is on, the process proceeds to step S2020-37, and if it is judged that the setting key is not on, the process proceeds to step S2021.

(Step S2021)
The main CPU 500a executes an initialization start process to start the initialization start, which will be described later.

Figure 86 is a flowchart explaining the initialization start process (S2021) in the main control board 500.

(Step S2021-1)
The main CPU 500a sets in the transmission buffer a setting change end command indicating that the change of the setting value has been completed.

(Step S2021-3)
The main CPU 500a sets in the transmission buffer a setting change state command indicating the state when the setting value change is completed.

(Step S2021-5)
The main CPU 500a sets a wait timer at the start of initialization.

(Step S2021-7)
The main CPU 500a executes a timer wait process to wait until the wait timer reaches 0 at the start of initialization.

(Step S2021-9)
The main CPU 500a executes a setting change RAM clear process to clear a separate area of the main RAM 500c.

(Step S2021-11)
The main CPU 500a executes a RAM clear process to clear areas in the main RAM 500c that should be cleared when the settings are changed.

(Step S2021-13)
The main CPU 500a sets a game status command indicating the current game status in a transmission buffer.

(Step S2100)
The main CPU 500a executes a game start process to start a game, which will be described later.

Figure 87 is a flowchart explaining the state restoration process (S2030) in the main control board 500.

(Step S2030-1)
The main CPU 500a restores the stack pointer.

(Step S2030-3)
The main CPU 500a executes an unused area clearing process to clear unused areas in the main RAM 500c.

(Step S2030-5)
The main CPU 500a clears the stack pointer storage buffer.

(Step S2030-7)
The main CPU 500a sets (ON) the post-power-off recovery flag.

(Step S2030-9)
The main CPU 500a executes a port input process to update the image of the input port.

(Step S2030-11)
The main CPU 500a executes an operation target bit extraction process for extracting information on the operation target bit based on the image of the input port updated in step S2030-9.

(Step S2030-13)
The main CPU 500a sets the operation target bit extracted in step S2030-11 as the operation target bit of the previous state.

(Step S2030-15)
The main CPU 500a acquires the motor phases of the reels 410a, 410b, and 410c. Here, the motor phase is set as the state of the reels 410a, 410b, and 410c. The motor phase indicates the operation state of the reels 410a, 410b, and 410c, i.e., accelerating, rotating steadily, stopped, and waiting. Specifically, a variable of 1 byte (storage unit) assigned to the motor phase changes to a value such as accelerating = 3, rotating steadily = 2, stopped = 1, and waiting = 0 according to the operation state of the stepping motor 452.

(Step S2030-17)
The main CPU 500a determines whether any of the reels 410a, 410b, 410c are rotating steadily or accelerating based on the motor phase acquired in step S2030-15. If it is determined that any of the reels 410a, 410b, 410c are not rotating steadily or accelerating, the process proceeds to step S2030-21, and if it is determined that any of the reels 410a, 410b, 410c are rotating steadily or accelerating, the process proceeds to step S2030-19.

(Step S2030-19)
The main CPU 500a executes a rotation error process that performs settings when an error is detected in the reels 410a, 410b, and 410c.

(Step S2030-21)
The main CPU 500a restores the saved register group.

(Step S2030-23)
The main CPU 500a then permits the interrupt and ends the state restoration process, thereby restoring the main CPU 500a to the state it was in immediately before the power was turned off.

Figure 88 is a flowchart explaining the game start processing (S2100) on the main control board 500.

(Step S2100-1)
The main CPU 500a executes a re-play state identification signal output setting process for outputting a re-play state identification signal indicating whether or not a re-play is being performed.

(Step S2100-3)
The main CPU 500a sets an inserted number indicator output bit OFF to turn off (light off) the bit corresponding to the inserted number indicator that displays the number of inserted medals (number of bets).

(Step S2100-5)
The main CPU 500a executes an output port image set process to update the output image for the bit set in step S2100-3.

(Step S2100-7)
The main CPU 500a sets a game start wait timer.

(Step S2100-9)
The main CPU 500a executes a timer wait process to wait until the game start wait timer counts down to 0.

(Step S2100-11)
The main CPU 500a executes a one-game RAM clear process to clear an area in the main RAM 500c that should be cleared for each game.

(Step S2100-13)
The main CPU 500a executes a bonus signal setting process for setting a bonus signal.

(Step S2100-15)
The main CPU 500a executes an edge clear process to clear edge information of the input port image.

(Step S2200)
The main CPU 500a executes a medal insertion process for receiving insertion of medals, which will be described later.

Figure 89 is a flowchart explaining the medal insertion process (S2200) on the main control board 500.

(Step S2200-1)
The main CPU 500a executes an error checking process to check the detection results of various errors.

(Step S2200-3)
The main CPU 500a executes an edge check process to detect the falling edge (on edge) of the signal at the input port.

(Step S2200-5)
The main CPU 500a acquires a door open error detection flag that is set to 1 when the front upper door 404 or the front lower door 406 is open.

(Step S2200-7)
The main CPU 500a judges whether the front upper door 404 and the front lower door 406 are closed based on the door open error detection flag acquired in the above step S2200-5. If it is judged that the front upper door 404 and the front lower door 406 are closed, the process proceeds to step S2200-17, and if it is judged that at least one of the front upper door 404 and the front lower door 406 is not closed, the process proceeds to step S2200-9.

(Step S2200-9)
The main CPU 500a sets an error code "E8" which indicates that at least one of the front upper door 404 or the front lower door 406 is open.

(Step S2200-11)
The main CPU 500a executes an error wait process to display an error, request an alarm sound, and wait for recovery from the error.

(Step S2200-13)
The main CPU 500a executes a setting value confirmation process to confirm the setting value.

(Step S2200-15)
The main CPU 500a executes an edge clear process to clear edge information of the input port image.

(Step S2200-17)
When a credit switch (not shown) for paying back accumulated (credited) medals is pressed, the main CPU 500a executes a credit button check process for paying back the accumulated medals.

(Step S2200-19)
The main CPU 500a executes a process related to the medal insertion button for betting medals. Here, when the bet switch 416 is pressed, the reserved (credited) medals are bet up to a specified number, and the number of reserved medals is subtracted by the number of medals bet. Also, when medals are inserted through the medal insertion slot 414a, medals are bet up to a specified number, and if more medals are inserted than the specified number, the number of medals is added to the number of reserved medals.

(Step S2200-21)
The main CPU 500a executes a medal acquisition process to check whether the number of inserted medals is a specified number.

(Step S2200-23)
The main CPU 500a judges whether the number of inserted coins is equal to the specified number based on the result of the check in step S2200-21. If the number of inserted coins is equal to the specified number, the process proceeds to step S2200-1. If the number of inserted coins is equal to the specified number, the process proceeds to step S2200-25.

(Step S2200-25)
The main CPU 500a sets a start indicator output bit for turning on (illuminating) a start indicator (not shown) which indicates whether or not the operation of the start switch 418 has been validated.

(Step S2200-27)
The main CPU 500a judges whether or not it has detected a falling edge (pressing) of the start switch 418. As a result, if it is judged that the falling edge of the start switch 418 has not been detected, the process proceeds to step S2200-1, and if it is judged that the falling edge of the start switch 418 has been detected, the process proceeds to step S2200-29.

(Step S2200-29)
The main CPU 500a clears the main payout display section buffer to clear the display of the main payout display section 432.

(Step S2200-31)
The main CPU 500a executes a re-play state identification signal clearing process for clearing the re-play state identification signal.

(Step S2200-33)
The main CPU 500a executes blocker blocking pre-processing to turn off (extinguish) the start indicator.

(Step S2200-35)
The main CPU 500a sets a lever press command, which indicates that the start switch 418 has been pressed, in the transmission buffer.

(Step S2300)
The main CPU 500a executes an internal lottery process for carrying out a lottery for determining the type of winning. This internal lottery process will be described later.

Figure 90 is a flowchart explaining the internal lottery process (S2300) in the main control board 500.

(Step S2300-1)
The main CPU 500a acquires the setting value data.

(Step S2300-3)
The main CPU 500a sets an error code "EC" indicating an abnormal setting error.

(Step S2300-5)
The main CPU 500a judges whether the setting value data acquired in step S2300-1 is abnormal. If it is judged that the setting value data is abnormal, the process proceeds to step S2011, and if it is judged that the setting value data is not abnormal, the process proceeds to step S2300-7.

(Step S2300-7)
The main CPU 500a obtains the winning type lottery random number updated by the random number generator 500d.

(Step S2300-9)
The main CPU 500a executes a state offset acquisition process to acquire an offset value related to a game state.

(Step S2300-11)
The main CPU 500a sets the address of the internal lottery area definition table (winning type lottery table).

(Step S2300-13)
The main CPU 500a adds the offset value acquired in step S2300-9 to the address set in step S2300-11, and sets the value indicated by the address as the initial value of the winning area. Here, the first winning area in the winning type lottery table for the current game state is set as the initial value.

(Step S2300-15)
The main CPU 500a acquires lottery data, which is a numerical value indicating the winning range of the winning area, and executes a lottery data acquisition process to shift the winning area by one.

(Step S2300-17)
The main CPU 500a determines whether or not to hold a prize type lottery. If it determines that a prize type lottery will not be held, the process proceeds to step S2300-21. If it determines that a prize type lottery will be held, the process proceeds to step S2300-19.

(Step S2300-19)
The main CPU 500a subtracts the lottery data from the random number value.

(Step S2300-21)
The main CPU 500a judges whether the subtraction result in step S2300-19 is negative, i.e., whether the winning area has been won by the winning type lottery. If it is judged that the winning type lottery has been won, the process proceeds to step S2400, and if it is judged that the winning type lottery has not been won, the process proceeds to step S2300-23.

(Step S2300-23)
The main CPU 500a judges whether the winning type lottery has ended. If it is judged that the winning type lottery has not ended, the process proceeds to step S2300-15, and if it is judged that the winning type lottery has ended, the process proceeds to step S2300-25.

(Step S2300-25)
The main CPU 500a clears the trigger role type.

(Step S2400)
The main CPU 500a executes a symbol code setting process for setting a symbol code based on the winning area and the game state. This symbol code setting process will be described later.

Figure 91 is a flowchart explaining the pattern code setting process (S2400) on the main control board 500.

(Step S2400-1)
The main CPU 500a acquires the winning area acquired in step S2300, and executes a game state setting process to set the game state to an internal game state if the acquired winning area includes a bonus role.

(Step S2400-3)
The main CPU 500a sets the winning area acquired in step S2400-1 as the stop control number.

(Step S2400-5)
The main CPU 500a determines (sets) the type of win based on the win area acquired in step S2400-1.

(Step S2400-7)
The main CPU 500a executes a symbol code initial setting process for setting symbol codes indicating symbols that can be displayed and symbols to be drawn in, based on the stop control number set in step S2400-3.

(Step S2400-9)
The main CPU 500a executes a display symbol bit initial value setting process to set a display symbol bit.

(Step S2400-11)
The main CPU 500a executes an execution flag setting process, which performs various processes related to the performance state, and processes related to auxiliary performance.

(Step S2400-13)
The main CPU 500a sets a presentation command, which is a command related to the advantageous zone, in the transmission buffer.

(Step S2400-15)
The main CPU 500a sets a winning information command indicating the type of winning in the transmission buffer.

(Step S2400-17)
The main CPU 500a checks the one-game timer.

(Step S2400-19)
The main CPU 500a sets a pre-reel spin command, which indicates that the reels 410a, 410b, and 410c have not yet spun, in the transmission buffer.

(Step S2400-21)
The main CPU 500a executes an excitation release waiting process for waiting for the excitation release of the stepping motor 452.

(Step S2400-23)
The main CPU 500a judges whether the 1-game timer is not 0. As a result, if it is judged that the 1-game timer is not 0, the process proceeds to step S2400-23, and if it is judged that the 1-game timer is 0, the process proceeds to step S2400-25.

(Step S2400-25)
The main CPU 500a executes a reel start process for starting the rotation of the reels 410a, 410b, and 410c. Here, the motor phases of the reels 410a, 410b, and 410c are set to accelerating to start the rotation of each reel, and the one-game timer is set to a value equivalent to 4.1 seconds.

(Step S2400-27)
The main CPU 500a sets a reel start command, which indicates that the reels 410a, 410b, and 410c have started to rotate, in the transmission buffer.

(Step S2500)
The main CPU 500a executes a process during the rotation of the reels 410a, 410b, and 410c. This process will be described later.

Figure 92 is a flowchart explaining the processing during reel rotation (S2500) in the main control board 500.

(Step S2500-1)
The main CPU 500a sets the stop indicator output bit off (output image) to turn off (turn off) the bit corresponding to the indicator (not shown) of the stop switches 420a, 420b, 420c. Here, the stop indicator output bit is composed of a bit string of 3 bits, each bit corresponding to the light emission color of the three stop switches 420a, 420b, 420c, respectively, and is represented by blue=1 and red=0.

(Step S2500-3)
The main CPU 500a executes an output port image set process to update the output image for the bit set in step S2500-1 above.

(Step S2500-5)
The main CPU 500a executes an error checking process to check the detection results of various errors.

(Step S2500-7)
The main CPU 500a refers to the index flag and obtains the index of the spinning reels 410a, 410b, and 410c. Note that the index flag is set only after the reels 410a, 410b, and 410c have reached a constant rotation speed. In other words, the fact that the index flag is set indicates that the reels 410a, 410b, and 410c have reached a constant rotation speed.

(Step S2500-9)
The main CPU 500a judges whether all index flags of the reels 410a, 410b, and 410c have been detected. If it is determined that all index flags have not been detected, the process proceeds to step S2500-1. If it is determined that all index flags have been detected, the process proceeds to step S2500-11.

(Step S2500-11)
The main CPU 500a acquires the stopped reel bit indicating the reels 410a, 410b, and 410c that have stopped or are starting to stop. Here, the stopped reel bit is composed of a 3-bit bit string, and each bit corresponds to one of the three reels 410a, 410b, and 410c, and is represented as a constant speed state = 1, and an accelerating state, decelerating state, or stopped state = 0.

(Step S2500-13)
The main CPU 500a stores the stopped reel bit acquired in step S2500-11 above as a reel rotation in progress flag.

(Step S2500-15)
The main CPU 500a sets a stop indicator output bit on (output image) to turn on (turn off) the bit corresponding to the indicator (not shown) of the stop switches 420a, 420b, 420c.

(Step S2500-17)
The main CPU 500a acquires an image of the input port 0, and executes an operation target bit extraction process to extract an operation target bit from the acquired image. Here, the operation target bit is composed of a bit string of 3 bits, each bit corresponding to one of the three stop switches 420a, 420b, 420c, and is represented as 1 if it is operated and 0 if it is not operated.

(Step S2500-19)
The main CPU 500a calculates the logical product of the reel spinning flag acquired in step S2500-13 and the bit to be operated extracted in step S2500-17. If the reel 410 is spinning and the stop switch 420 corresponding to that reel is operated, that is, if the operated stop switch 420 corresponds to the reel 410 that is spinning effectively, the logical product will be 1.

(Step S2500-21)
The main CPU 500a determines whether the logical product calculated in step S2500-19 is 0, i.e., whether the stop switch 420 corresponding to the spinning reel 410 has not been operated. If it is determined that the stop switch 420 corresponding to the spinning reel 410 has not been operated, the process proceeds to step S2500-3, and if it is determined that the stop switch 420 corresponding to the spinning reel 410 has been operated, the process proceeds to step S2500-23.

(Step S2500-23)
The main CPU 500a obtains an output image including the stop indicator output bit, and calculates the logical product of the obtained output image and the logical product calculated in the above step S2500-19. Here, if the operated stop switch 420 is lit in red, the bit of the logical product becomes 0, and if the operated stop switch 420 is lit in blue, the bit of the logical product becomes 1.

(Step S2500-25)
The main CPU 500a judges whether the logical product calculated in the above step S2500-23 is 0, that is, whether the operated stop switch 420 is lit in red. If it is judged that the operated stop switch 420 is lit in red, the process proceeds to step S2500-1, and if it is judged that the operated stop switch 420 is not lit in red, the process proceeds to step S2500-27.

(Step S2500-27)
The main CPU 500a judges whether the operated stop switch 420 is valid. As a result, if it is judged that the operated stop switch 420 is not valid, the process proceeds to step S2500-1, and if it is judged that the operated stop switch 420 is valid, the process proceeds to step S2500-29. Note that here, it is judged whether or not one stop switch 420 is operated. Then, if it is judged that one stop switch 420 is operated, the process proceeds to step S2500-29, and if it is judged that not one stop switch 420 is operated, that is, that two or more stop switches 420 are operated, the process proceeds to step S2500-1.

(Step S2500-29)
The main CPU 500a executes a stop control reel setting process to acquire various parameters for stopping the reel 410 corresponding to the operated stop switch 420.

(Step S2500-31)
The main CPU 500a disables interrupts.

(Step S2500-33)
The main CPU 500a executes a touch reference position acquisition process to derive the symbol number of the symbol located on the pay line A as the touch reference position.

(Step S2500-35)
The main CPU 500a executes a sliding frame number acquisition process for determining the number of sliding frames on the reel 410.

(Step S2600)
The main CPU 500a executes a reel stop process for stopping the reel 410 corresponding to the operated stop switch 420. This reel stop process will be described later.

Figure 93 is a flowchart explaining the reel stop processing (S2600) in the main control board 500.

(Step S2600-1)
The main CPU 500a obtains the pressed reference position derived in step S2500-35 above.

(Step S2600-3)
The main CPU 500a calculates a stop request number by correcting the number of sliding symbols determined in step S2500-37 above with respect to the pressed reference position acquired in step S2600-1 above.

(Step S2600-5)
The main CPU 500a sets a stop request flag (sets it to 1). The stop request flag is a flag for requesting a program operating in parallel to perform a stop process for the target reel 410, and by setting the stop request flag to 1, it becomes possible to stop the symbol corresponding to the stop request number on the activated line A. The stop request flag and the stop request number are read out by a program operating in parallel, and the reel 410 is stopped. When the stop process is completed, the stop request flag is reset to 0 (OFF) by that program.

(Step S2600-7)
The main CPU 500a permits interrupts.

(Step S2600-9)
The main CPU 500a sets a stop information command indicating the stopping order of the reels 410 in the transmission buffer.

(Step S2600-11)
The main CPU 500a sets the stop indicator output bit off (output image) to turn off (turn off) the bit corresponding to the indicator (not shown) of the stop switch 420.

(Step S2600-13)
The main CPU 500a executes an output port image set process to update the output image for the bit set in step S2600-11.

(Step S2600-15)
The main CPU 500a executes a display symbol bit setting process to set a display symbol bit.

(Step S2600-17)
The main CPU 500a executes a next cylinder setting pre-processing for stopping the next reel 410.

(Step S2600-19)
The main CPU 500a judges whether or not the stop processing has been completed for all of the reels 410. As a result, if it is judged that the stop processing has not been completed for all of the reels 410, the process proceeds to step S2500, and if it is judged that the stop processing has been completed for all of the reels 410, the process proceeds to step S2600-21.

(Step S2600-21)
The main CPU 500a determines whether the stop request flag is on for any of the reels 410, i.e., whether all of the reels 410 have stopped. If it is determined that all of the reels 410 have not stopped, the process proceeds to step S2600-21, and if it is determined that all of the reels 410 have stopped, the process proceeds to step S2600-23.

(Step S2600-23)
The main CPU 500a executes an error checking process to check the detection results of various errors.

(Step S2600-25)
The main CPU 500a executes an operation target bit extraction process for extracting information on operation target bits.

(Step S2600-27)
The main CPU 500a judges whether the stop switch 420 is pressed based on the operation target bit acquired in the above step S2600-25. If it is judged that the stop switch 420 is pressed, the process proceeds to step S2600-23, and if it is judged that the stop switch 420 is not pressed, the process proceeds to step S2700.

(Step S2700)
The main CPU 500a executes a display determination process for determining the winning combination that has been achieved. This display determination process will be described later.

Figure 94 is a flowchart explaining the display determination process (S2700) in the main control board 500.

(Step S2700-1)
The main CPU 500a clears the buffer of the main payout display section 432.

(Step S2700-3)
The main CPU 500a executes a display judgment abnormality detection process to determine whether a display judgment abnormality has occurred based on whether or not the pattern combination displayed on the active line A matches the pattern combination permitted to be displayed on the active line A.

(Step S2700-5)
The main CPU 500a sets an error code "EE" which indicates a display determination abnormality (error).

(Step S2700-7)
The main CPU 500a judges whether or not there is a display judgment abnormality based on the judgment result of the above step S2700-3. As a result, if it is judged that there is a display judgment abnormality, the process proceeds to step S2011, and if it is judged that there is no display judgment abnormality, the process proceeds to step S2700-9.

(Step S2700-9)
The main CPU 500a executes a display symbol identification generation process for determining a winning combination based on the symbol combination stopped (displayed) on the pay line A.

(Step S2700-11)
The main CPU 500a sets the initial value of the payout number to 0.

(Step S2700-13)
The main CPU 500a judges whether or not a small win has been won. If it is judged that a small win has been won, the process proceeds to step S2700-15. If it is judged that a small win has not been won, the process proceeds to step S2700-35.

(Step S2700-15)
The main CPU 500a turns on a winning flag indicating that a small winning combination has been achieved.

(Step S2700-17)
The main CPU 500a executes a payout number setting process for setting the payout number according to the small winning combination.

(Step S2700-19)
The main CPU 500a judges whether the time is within an advantageous zone. If it is judged that the time is within an advantageous zone, the process proceeds to step S2800. If it is judged that the time is within an advantageous zone, the process proceeds to step S2700-21.

(Step S2700-21)
The main CPU 500a obtains the value of the favorable zone MY counter, which counts the net increase in the number of coins during the favorable zone.

(Step S2700-23)
The main CPU 500a adds the number of payout coins to the value of the advantageous zone MY counter obtained in step S2700-23 above.

(Step S2700-25)
The main CPU 500a acquires the number of coins inserted for the game.

(Step S2700-27)
The main CPU 500a subtracts the number of inserted coins from the value added in step S2700-23.

(Step S2700-29)
The main CPU 500a judges whether the result of the subtraction in the above step S2700-27 is negative. If it is judged that the result of the subtraction is not negative, the process proceeds to step S2700-33, and if it is judged that the result of the subtraction is negative, the process proceeds to step S2700-31.

(Step S2700-31)
The main CPU 500a clears the value of the advantageous zone MY counter (sets it to 0).

(Step S2700-33)
The main CPU 500a updates the value of the favorable zone MY counter to the value subtracted in step S2700-27 or the value cleared in step S2700-31.

(Step S2700-35)
The main CPU 500a judges whether or not the replay role has been won. If it is judged that the replay role has not been won, the process proceeds to step S2800. If it is judged that the replay role has been won, the process proceeds to step S2700-37.

(Step S2700-37)
The main CPU 500a sets the number of coins inserted as the number of coins to be paid out.

(Step S2700-39)
The main CPU 500a turns on the re-play operation flag.

(Step S2700-41)
The main CPU 500a sets the number of coins to be automatically inserted.

(Step S2800)
The main CPU 500a executes a payout process for paying out medals, which will be described later.

Figure 95 is a flowchart explaining the payout process (S2800) in the main control board 500.

(Step S2800-1)
The main CPU 500a acquires a re-play operation flag.

(Step S2800-3)
The main CPU 500a sets in the transmission buffer a payout start command indicating that the payout of medals has started.

(Step S2800-5)
The main CPU 500a judges whether or not a replay has been won based on the replay operation flag acquired in step S2800-1. If it is judged that a replay has been won, the process proceeds to step S2800-41. If it is judged that a replay has not been won, the process proceeds to step S2800-7.

(Step S2800-7)
The main CPU 500a executes a main display display process to display 0 on the main payout display section 432.

(Step S2800-9)
The main CPU 500a determines whether or not a payout has been made (the number of payout coins is 0). If it determines that no payout has been made, the process proceeds to step S2800-35. If it determines that a payout has been made, the process proceeds to step S2800-11.

(Step S2800-11)
The main CPU 500a judges whether the number of stored sheets is 50 or more. If it is judged that the number of stored sheets is 50 or more, the process proceeds to step S2800-13, and if it is judged that the number of stored sheets is not 50 or more, the process proceeds to step S2800-15.

(Step S2800-13)
The main CPU 500a executes a medal payout device control process to cause the medal payout device 442 to pay out one medal, and then moves to step S2800-23.

(Step S2800-15)
The main CPU 500a sets a payout start interval timer.

(Step S2800-17)
The main CPU 500a judges whether the payout start timer is not 0, i.e., whether it is the first payout time. If it is judged that it is the first payout time, the process proceeds to step S2800-21, and if it is judged that it is not the first payout time, the process proceeds to step S2800-19.

(Step S2800-19)
The main CPU 500a executes a timer wait process to wait until the payout start interval timer counts down to 0.

(Step S2800-21)
The main CPU 500a increments the number of stored coins by one.

(Step S2800-23)
The main CPU 500a sets in the transmission buffer a payout execution command indicating that one medal has been paid out.

(Step S2800-25)
The main CPU 500a executes a main display pre-display process for displaying the number of coins already paid out on the main payout display section 432.

(Step S2800-27)
The main CPU 500a judges whether or not the bonus game state is in effect. If it is judged that the bonus game state is not in effect, the process proceeds to step S2800-31. If it is judged that the bonus game state is in effect, the process proceeds to step S2800-29.

(Step S2800-29)
The main CPU 500a increments by one the number of medals acquired during bonus operation, which is the number of medals paid out in the bonus game state.

(Step S2800-31)
The main CPU 500a judges whether or not the payout of the payout number of medals has been completed. If it is judged that the payout has not been completed, the process proceeds to step S2800-11, and if it is judged that the payout has been completed, the process proceeds to step S2800-33.

(Step S2800-33)
The main CPU 500a executes a payout end process to end the payout of medals.

(Step S2800-35)
The main CPU 500a judges whether an over error has been detected. If it is judged that an over error has not been detected, the process proceeds to step S2800-41, and if it is judged that an over error has been detected, the process proceeds to step S2800-37.

(Step S2800-37)
The main CPU 500a sets an error code "E5" indicating an over error.

(Step S2800-39)
The main CPU 500a executes an error wait process to display an error, request an alarm sound, and wait for recovery from the error.

(Step S2800-41)
The main CPU 500a sets in the transmission buffer a payout end command indicating that the payout of medals has been completed.

(Step S2900)
The main CPU 500a executes a game transition process for transitioning the game state, managing advantageous zones, etc. This game transition process will be described later.

Figure 96 is a flowchart explaining the game transition process (S2900) on the main control board 500.

(Step S2900-1)
The main CPU 500a acquires a replay operation flag, and based on the acquired replay operation flag, executes a replay display control process which sets a stop display output bit off (output image) to turn on or off a bit corresponding to a replay display (not shown) indicating that the next play is a replay, and updates the output bit of the set output image.

(Step S2900-3)
When a bonus combination is won, the main CPU 500a executes a combination operation symbol display process for setting various parameters for controlling the bonus game state.

(Step S2900-5)
When the number of coins acquired during the bonus operation reaches a predetermined number in the bonus game state, the main CPU 500a executes a bonus operation end process for shifting the game state to a non-internal game state.

(Step S2900-7)
The main CPU 500a executes advantageous zone update processing to manage advantageous zones.

(Step S2900-9)
The main CPU 500a judges whether the next game is in an AT presentation state. If it is judged that the next game is not in an AT presentation state, the process proceeds to step S2900-15. If it is judged that the next game is in an AT presentation state, the process proceeds to step S2900-11.

(Step S2900-11)
The main CPU 500a judges whether or not the bonus game state is in effect. If it is judged that the bonus game state is not in effect, the process proceeds to step S2900-15. If it is judged that the bonus game state is in effect, the process proceeds to step S2900-13.

(Step S2900-13)
The main CPU 500a sets the advantageous lamp flag on to turn on the section indicator 460.

(Step S2900-15)
The main CPU 500a executes a performance command setting process that sets a performance command, which is a command related to the advantageous zone, in a transmission buffer.

(Step S2900-17)
The main CPU 500a sets a game end command, which indicates that one game has ended, in the transmission buffer.

(Step S2900-19)
The main CPU 500a executes a terminal board signal output process for outputting an external signal.

(Step S2900-21)
The main CPU 500a judges whether the effect wait timer, which is set when the advantageous zone is ended in the above step S2900-7, is 0. As a result, if it is judged that the effect wait timer is not 0, the process proceeds to step S2900-21, and if it is judged that the effect wait timer is 0, the process proceeds to step S2900-23.

(Step S2900-23)
The main CPU 500a sets a game status command indicating the game status in a transmission buffer.

(Step S2900-25)
The main CPU 500a sets a game start command indicating the start of the next game in the transmission buffer, and transfers the process to step S2100.

One game is executed through a series of processes from step S2100 to step S2900. After that, steps S2100 to S2900 are repeated.

Next, we will explain the power-off evacuation process and timer interrupt process on the main control board 500.

(Evacuation process when power is turned off for the main control board 500)
97 is a flow chart explaining the power-off save processing in the main control board 500. The main CPU 500a monitors the power-off detection circuit, and when the power supply voltage falls below a predetermined value, it interrupts and executes the power-off save processing.

(Step S3000-1)
When the power-off warning signal is input, the main CPU 500a saves the registers.

(Step S3000-3)
The main CPU 500a checks the power-off warning signal.

(Step S3000-5)
The main CPU 500a judges whether a power-off warning signal has been detected. If it is judged that a power-off warning signal has been detected, the process proceeds to step S3000-11. If it is judged that a power-off warning signal has not been detected, the process proceeds to step S3000-7.

(Step S3000-7)
The main CPU 500a restores the registers.

(Step S3000-9)
The main CPU 500a performs processing to permit an interrupt, and ends the power-off save processing.

(Step S3000-11)
The main CPU 500a executes an output port clear process to stop the output of the output port.

(Step S3000-13)
The main CPU 500a executes a save process for another area when power is turned off.

(Step S3000-15)
The main CPU 500a executes a RAM protect setting process required to prohibit access to the main RAM 300c.

(Step S3000-17)
In order to set the power interruption occurrence monitoring time, the main CPU 500a sets the counter value of a loop counter to a predetermined number of times the power interruption detection signal has been detected.

(Step S3000-19)
The main CPU 500a decrements the value of the loop counter set in step S3000-17 by one.

(Step S3000-21)
The main CPU 500a judges whether the counter value of the loop counter is 0. If it is judged that the counter value is not 0, the process proceeds to step S3000-19, and if it is judged that the counter value is 0, the process proceeds to the above-mentioned CPU initialization process (step S1000).

If a power outage actually occurs, operation of the slot machine 400 will stop while steps S3000-19 to S3000-21 are being looped.

(Timer interrupt processing of main control board 500)
98 is a flow chart for explaining the timer interrupt process in the main control board 500. The main control board 500 is provided with a reset clock pulse generating circuit that generates a clock pulse every predetermined period (1.49 milliseconds in the simultaneous rotation reference example, hereinafter referred to as "1.49 ms"). When a clock pulse is generated by the reset clock pulse generating circuit, an interrupt occurs and the following timer interrupt process is executed.

(Step S3100-1)
The main CPU 500a saves the registers.

(Step S3100-3)
The main CPU 500a clears the interrupt flag.

(Step S3100-5)
The main CPU 500a reads various input port images and executes port input processing to accurately obtain the latest switch states.

(Step S3100-7)
The main CPU 500a outputs the set output image to the output port and executes a dynamic port output process which controls the lighting of the main credit display section 430, the main payout display section 432, the number of inserted coins indicator, the start indicator, the indicators of the stop switches 420a, 420b, 420c, the replay indicator, and the section indicator 460.

(Step S3100-9)
The main CPU 500a updates the timer interrupt phase. The timer interrupt phase can be any of 0 to 3. In this example, if the timer interrupt phase is 0, 1, or 2, 1 is added, and if the timer interrupt phase is 3, it is changed to 0.

(Step S3100-11)
The main CPU 500 a performs a sub-command transmission process to transmit the commands stored in the transmission buffer to the sub-control board 502 .

(Step S3100-13)
The main CPU 500 a executes a stepping motor control process for controlling the stepping motor 452 .

(Step S3100-15)
The main CPU 500 a executes an output port image output process that outputs an output image to be output to the medal payout device 442 .

(Step S3100-17)
The main CPU 500a executes a random number update process to update various random numbers.

(Step S3100-19)
The main CPU 500a executes fraud monitoring processing to detect errors in order to output external signals (external signals 4 and 5) corresponding to the errors to the outside.

(Step S3100-21)
The main CPU 500a executes a module (subroutine) corresponding to the timer interrupt processing phase updated in step S3100-9. Here, the timer interrupt processing phase is set to any one of 0 to 3, and one module is provided corresponding to each of the timer interrupt processing phases 0 to 3 (four in total), so that one module is executed once every four timer interrupt processing times (every 5.96 ms). For example, a module that executes a time monitoring process that subtracts from various timers is associated with one timer interrupt processing phase.

(Step S3100-23)
The main CPU 500a executes a test signal output process for outputting a test signal to the outside.

(Step S3100-25)
The main CPU 500a reads various input port images and executes port input processing to accurately obtain the latest switch states.

(Step S3100-27)
The main CPU 500a restores the registers.

(Step S3100-29)
The main CPU 300a permits the interrupt and ends the timer interrupt process.

In addition, in the above-described embodiment, the main control board 500 and the sub-control board 502 are arranged to share the functional parts for progressing the game, but the functional parts of the main control board 500 may be arranged on the sub-control board 502, or the functional parts of the sub-control board 502 may be arranged on the main control board 500, or all the functional parts may be arranged together on a single control board.

In addition, in the above-described embodiment, only one type of AT presentation state is provided, but multiple types of AT presentation states may be provided, such as a specialized zone for adding the number of continuous plays in the AT presentation state.

In the above embodiment, the game is played using medals as the game value, but the game value may be electrical information (it may be so-called medalless). In this case, when a winning combination is achieved, the amount of value corresponding to the winning combination may be given to the player in the form of electrical information.

Furthermore, each process performed by the main control board 500 and the sub-control board 502 described above does not necessarily have to be performed in chronological order according to the order described in the flowchart, and may include parallel or subroutine processing.

Furthermore, each process performed by the main control board 500 and the sub-control board 502 described above does not necessarily have to be performed in chronological order according to the order described in the flowchart, and may include parallel or subroutine processing.

<Main control board CPU peripheral configuration>
99 is a diagram for explaining electrical connections around the main CPU 300a. The main CPU 300a includes a CPU core 700 and a bus controller 702. The CPU core 700 controls the bus controller 702 through a bus control signal (Bus Cont) output from the BC terminal, and reads data from the main ROM 300b, the main RAM 300c, or the input/output unit 704, or writes data to the main RAM 300c. Here, a microprocessor based on a Z80 series CPU and sold by LETech is used as the CPU 300a. Here, the main CPU 300a, main ROM 300b, and main RAM 300c of a pachinko machine are described, but it goes without saying that they can be replaced with the main CPU 500a, main ROM 500b, and main RAM 500c of a slot machine 400.

For example, when reading data from main ROM 300b, main RAM 300c, or input/output unit 704, the bus controller 702 outputs a 16-bit address (A[16]) signal, identifies either main ROM 300b, main RAM 300c, or input/output unit 704 through decoders 706a, 706b, 706c, and controls the read (RD) signal to read a data (D[8]) signal from main ROM 300b, main RAM 300c, or input/output unit 704. Furthermore, when writing data to the main RAM 300c or the input/output unit 704, the bus controller 702 outputs an address (A[16]) signal and a data (D[8]) signal, and identifies either the main RAM 300c or the input/output unit 704 via the decoders 706b and 706c, and controls the write (WR) signal to write the data (D[8]) signal to the main RAM 300c or the input/output unit 704.

As described below, the address space of the input/output unit 704 is integrated with the address spaces of the main ROM 300b and the main RAM 300c. Therefore, unlike the conventional technology, there is no memory request (MREQ) terminal or I/O request (IORQ) terminal that outputs a signal to specify whether to access memory or I/O. By reassigning these two terminals to any other signal, the degree of freedom in program development can be increased.

The CPU core 700 also receives external signals such as an interrupt/wait (INT/WAIT) signal that triggers the start of interrupt processing, a non-maskable interrupt (NMI) signal that allows interrupt processing to be executed with the highest priority, and a bus request (BUSREQ) signal that can transition a bus signal to high impedance.

Figure 100 is a block diagram showing the internal configuration of a CPU core 700. The CPU core 700 includes an external input unit 710, a state control unit 712, a central control unit 714, a register unit 716, and an arithmetic logic unit (ALU) 718. The external input unit 710 receives an external signal and outputs control information based on the external signal to the state control unit 712 and the central control unit 714.

The state control unit 712 manages and transitions the internal states (RESET, instruction fetch, instruction decoder, operation, memory load, memory store, HALT, etc.) to determine the operating state of the CPU core 700, and outputs control information based on the internal states to the central control unit 714.

The central control unit 714 extracts an opcode (instruction) from the input data (DI[8]) input via the bus controller 702, and controls the ALU 718 based on the command decoded by the instruction decoder. The central control unit 714 also obtains necessary information from each register of the register unit 716 and updates each register based on the decoded command.

The register unit 716 includes selector ports 722a, 722b, and 722c, an input bank selector 724, a first register bank 726, a second register bank 728, an output bank selector 730, an address port 732, and individual registers 734. The individual registers 734 include a 16-bit program counter (PC) that indicates the address of the program to be executed next, an 8-bit interrupt (I) register that is used in interrupt mode, an 8-bit refresh (R) register that counts opcode fetch cycles, and an 8-bit interrupt enable (IFF) register that controls whether interrupts are enabled or disabled.

The register unit 716 is also associated with a random number generator (not shown) for obtaining various random number values related to the big prize lottery (jackpot determining random number, winning symbol random number, reach group determining random number, reach mode determining random number, variation pattern random number, winning random number), and the random number values latched via the input ports (FE73h to FE9Ch) are obtained.

The random number generator operates on the system clock (a clock obtained by dividing the external input by two) and generates random numbers less than a predetermined maximum value. The random number generator is a maximum value setting random number generator that can set the maximum value of the random number, and is provided with four channels for generating random numbers that can generate 16-bit maximum values and eight channels for generating random numbers that can generate 8-bit maximum values. Here, the 16-bit maximum value setting random number generator allows the random number update period to be selected from the range of 32 to 47 clocks, and the maximum value setting range can be set from 256 to 65535. The 8-bit maximum value setting random number generator allows the random number update period to be selected from the range of 16 to 31 clocks, and the maximum value setting range can be set from 16 to 255 in four channels and from 64 to 255 in the other four channels. The maximum value setting random number generator is a random number generator with a fixed maximum value, and is provided with four channels for generating random numbers that can generate 16-bit maximum values and eight channels for generating random numbers that can generate 8-bit maximum values. Here, the 16-bit fixed maximum random number generator has a random number update period of 1 clock and a maximum value fixed at 65535. Also, the 8-bit fixed maximum random number generator has a random number update period of 1 clock and a maximum value fixed at 255.

If there are not enough types of random numbers, it is also possible to generate other random numbers (software random number generator) by multiplying or dividing the random number value obtained from the hardware random number generator (random number generator) by a specified number within the program.

Figure 101 is a diagram explaining the register configuration. Both the first register bank 726 and the second register bank 728 are provided with 8-bit registers (Q, U, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY, SP). The registers in the first register bank 726 and the second register bank 728 are divided into front registers and back registers. The CPUs 300a and 500a can only access the front registers of the register bank indicated by the register bank designation register RB in the F register, and cannot access the back registers.

Of the registers shown in FIG. 101, the Q register is an 8-bit dedicated register with expansion specifications for gaming machines. This Q register is fixed at F0h, and is used to access the main RAM 300c from F000h to F0FFh. The U register is an 8-bit dedicated register with expansion specifications for gaming machines. This U register is fixed at FEh, and is used to access built-in devices (timers, random number generators, external input/output circuits, etc.) connected to the input/output unit 704 from FE00h to FEFFh. The A register is an 8-bit accumulator used for arithmetic processing and data transfer. The F register is an 8-bit flag register that holds various calculation results. Here, each bit of the F register is arranged from the most significant bit (MSB: Most Significant Bit) to the least significant bit (LSB: Least Significant Bit) as shown in FIG. 101. Bit), S is a sign flag that is set to 1 when the result of the operation is negative, Z is a zero flag (first zero flag) that is set to 1 when all bits are 0 as a result of the operation, TZ is a specific bit flag (second zero flag) of the gaming machine expansion specification that is set to 1 (value changes) when all bits are 0 by executing a data transfer instruction (LD; load), and is sometimes called a TZ flag. H is a half carry flag that cannot be controlled by the programmer, RB is a register bank monitor that indicates the current register bank (first register bank 726 = 0, second register bank 728 = 1), P/V is a parity overflow flag, N is an addition/subtraction flag that cannot be controlled by the programmer, and C is a carry flag that is set to 1 when a carry or borrow occurs as a result of the operation. The F register and the A register form a pair register AF.

The B, C, D, E, H, and L registers are 8-bit general-purpose registers that form 16-bit pair registers BC, DE, and HL, each with a predefined combination. The IX and IY registers are 16-bit dedicated registers for index addressing. The SP (stack pointer) register is 16 bits and stores the address that serves as the stack pointer. The Q', A', F', B', C', D', E', H', L', IX', and IY' registers are back registers whose data (contents) can be exchanged with the front registers Q, A, F, B, C, D, E, H, L, IX, and IY by an exchange command. The A' and F' registers form a pair register AF', the B' and C' registers form a pair register BC', the D' and E' registers form a pair register DE', and the H' and L' registers form a pair register HL'. The back registers can be used by selecting and exchanging one of them with the front register by an exchange command or the like. On the other hand, the U and SP registers are single registers that do not have back registers. In this way, the back registers function as a stack area for the front registers when an interrupt process occurs.

As described above, in the main control boards 300 and 500, the main CPU 300a controls the progress of the game in cooperation with the main RAM 300c based on the programs stored in the main ROM 300b. The programs for executing these functional parts are stored in designated areas (usage areas) of the main ROM 300b and the main RAM 300c.

Figure 102 is an explanatory diagram showing a memory map. Note that the memory map in a pachinko machine has already been explained using Figure 5, so here, the memory map of the slot machine 400 will be explained. The main ROM 500b is assigned a memory space of 0000h to 3FFFh (12 kbytes), the main RAM 500c is assigned a memory space of F000h to F3FFh (1 kbyte), and the input/output unit 704 is assigned a memory space of FE00h to FEFFh (256 bytes). Note that the instruction codes of the program are written in assembler language. Here, a program is composed of instruction codes, and is read by a computer to realize a specified process in cooperation with data and a work area.

A usage area is allocated to the memory space from 0000h to 1DF3h of the main ROM 500b. The usage area is an area for storing programs and data for executing game control processing that controls the progress of the game. Specifically, the memory space (control area) limited to 0000h to 11FFh (4.5 kbytes) stores instruction codes for a program for executing game control processing that controls the progress of the game by operating the initialization means 600, betting means 602, winning type lottery means 604, reel control means 606, judgment means 608, payout control means 610, game status control means 612, presentation status control means 614, and command transmission means 616, and the memory space (data area) limited to 1200h to 1DF3h (3.0 kbytes) stores data used in the game control processing program. In addition, a comment area is assigned to the memory space from 1E00h to 1FFFh, and a program management area is assigned to the memory space from 3FC0h to 3FFFh. In addition, another area (unused area) is assigned to the memory space from 2000h to 3FBFh. The other area is an area for storing programs and data that are not specified to be stored in the used area, as described later. Specifically, the memory space from 2000h to 3FBFh stores instruction codes and program data of programs that perform part or all of the gaming machine test processing and security-related processing that do not affect the progress of the game. The gaming machine test processing is a test processing of the slot machine 400 described in the Connection Specifications (4th Edition) of the Test Machine for Slot Machines. The security-related processing is a process for identifying an abnormal state for the purpose of preventing fraud by a third party and discovering defects, and includes, for example, the determination of the backup flag and the execution of a checksum as described above. There is no limit to the storage capacity of the separate areas, and in the example of Figure 102, they can be freely assigned to storage areas other than the usage area, comment area, and program management area.

As described above, the main CPU 500a may perform not only game control processing, but also game machine test processing and security-related processing. However, the storage capacity of the usage area is predetermined; for example, as shown in FIG. 102, the control area is limited to 4.5 kbytes, and the data area is limited to 3.0 kbytes. Therefore, if not only game control processing but also programs and data for game machine test processing and security-related processing are placed in the usage area, the storage area for performing game control processing will be limited accordingly. Here, programs (usage programs) and data for executing game control processing must be stored in the usage area, but programs (separate programs) and data for executing processing (game machine test processing, security-related processing, etc.) that does not affect (is not directly related to) the progress of the game other than game control processing can be stored in either the usage area or the separate area. Therefore, at least a part of the programs and data for executing the backup flag determination processing and checksum execution processing, which are processing corresponding to security-related processing, are described in a separate area that is a part of a storage area different from the usage area (other than the usage area).

In this way, when there is a mixture of processing that is performed in the use area (here, game control processing) and processing that does not necessarily have to be performed in the use area (here, security-related processing), it is desirable to store the program (use program) and data for executing the game control processing in the use area, and store the program (separate program) and data for executing processing (security-related processing) that does not have to be performed in the use area and does not affect the progress of the game other than the game control processing in a separate area. By dividing the memory area into multiple areas in this way, there is more space in the memory area (capacity) of the use area for the programs that have been moved to the separate area. This makes it possible to allocate that much of the use area to the game control processing (use program).

However, even if the memory area is divided into a usage area and a separate area as described above, the fairness of the gaming machine must be guaranteed. Therefore, in order to ensure the fairness of the gaming machine while appropriately dividing the roles between the usage area and the separate area, the following conditions (1) to (6) are stipulated.

Condition (1): The programs to be placed in the separate area are used for the purpose of outputting signals required for testing the gaming machine (gaming machine test processing) and preventing fraud (security-related processing), and do not impair (or impair) the fairness of the game. Condition (2): The control area and data area of the use area and the separate area are placed in areas that are explicitly distinguished from each other. Condition (3): The programs to be placed in the separate area (separate programs) are executed after being statically called from the program in the use area (use program). In addition, the call destination address is clearly stated in the program list at that time. Condition (4): The programs to be placed in the separate area are modularized by function, and when called, the contents of all registers used in the use area are protected. Condition (5): Access to the RAM in each area from the use area or the separate area is only possible for reference, and cannot be updated. Condition (6): It is not possible to call a subroutine in the control area of the use area from the control area of the separate area. Since a subroutine that performs interrupt processing is provided in the use area, it becomes necessary to prohibit interrupts when using the control area of the separate area. In order to properly execute the game control process, the time from when the interrupt is prohibited to when it is released must be within the interval of the interrupt process in the game control process (e.g., 1.49 msec). Therefore, when calling a subroutine that uses a control area in another area, the total time required for that one call is set to be within the interval of the interrupt process in the game control process.

In addition, the memory space from F000h to F1FFh in the main RAM 500c is allocated as a usage area. Specifically, the memory space from F000h to F13Fh is allocated as a work area for the game control process, and is used to manage variables such as timers, counters, and flags. The memory space from F1C0h to F1FFh is allocated as a stack area for the game control process. In addition, another area is allocated to the memory space from F200h to F3FFh in the main RAM 500c. Specifically, the memory space from F210h to F22Fh is allocated as a work area for some or all of the security-related processes, and is used to manage variables such as timers, counters, and flags. The memory space from F230h to F246h is allocated as a stack area for some or all of the security-related processes.

Also, the input/output unit 704 is assigned to the memory space from FE00h to FEFFh. Conventionally, a 256-byte I/O space was provided independent of the memory space to access the device corresponding to the input/output unit 704. In contrast, in this embodiment, the MREQ and IORQ signals are eliminated, and access to the memory and the input/output unit 704 is performed by a common RD and WR signal. Also, a U register is provided as hardware to specify the upper 8 bits of the address to access the device connected to the input/output unit 704, and the upper 8 bits of the address are specified in advance here. As a result, the I/O space that was provided independently of the memory space is integrated into the memory space to form a single address space, and when the IN command or the OUT command is executed, the input/output unit 704 assigned to the memory space can be accessed by specifying the upper 8 bits with the U register and the lower 8 bits with the lower 8 bits specified by the operand of the IN command or the OUT command.

In this embodiment, a program can be written so that the LDQ instruction uses the Q register to access memory space (mainly data areas and work areas), and the IN and OUT instructions use the U register to access I/O of devices (timers, random number generators, external input/output circuits, etc.). This configuration makes it easier to understand the program at the time of design. Also, memory and I/O, which were previously accessed by specifying 16-bit addresses, can now be accessed by lower 8-bit operands, thereby compressing program capacity. Furthermore, by having multiple upper specification registers, the Q register, Q' register, and U register, the number of times that upper registers need to be replaced due to reuse is reduced compared to when there is only one upper register, further compressing program capacity.

In the above example, the memory space corresponding to the I/O space was accessed with the IN and OUT instructions, but the memory space may also be accessed directly with the IN and OUT instructions. For example, when accessing three 256-byte areas in memory, this can be achieved by specifying the upper 8 bits of each in the Q register, Q' register, and U register, and then accessing each area with the LDQ instruction and the IN and OUT instructions.

The specific instruction codes (command groups) required to implement each of the above-mentioned processes (modules) are explained below.

(Initialization start process)
FIG. 103 is a flow chart showing the initialization start process. The main CPU 500a in the slot machine 400 reads the program in the use area from the main ROM 500b and executes the read program. Then, by executing the STARTUP module, the initialization start process (S2021) in FIG. 86 is executed, and in the STARTUP module, the E_RMCLR module in another area is called as a subroutine, and the setting change RAM clear process shown in step S2021-9 in FIG. 86 is executed. The numerical values of step S in this figure are used only in the explanation of this figure.

As shown in FIG. 103(a), the main CPU 500a sets in the transmission buffer a setting change end command indicating that the setting value change has ended (S2021-1), sets in the transmission buffer a setting change state command indicating the state when the setting value change has ended (S2021-3), sets the initialization start wait timer (S2021-5), and executes timer wait processing to wait until the initialization start wait timer reaches 0 (S2021-7). Interrupts are permitted in steps S2021-1, S2021-3, S2021-5, and S2021-7.

Next, the main CPU 500a executes a RAM clear process at the time of setting change to clear another area of the main RAM 500c (S2021-9), and executes a RAM clear process at the time of setting change to clear the used area in the main RAM 500c that is to be cleared (S2021-11).

Here, the E_RMCLR module called in step S2021-9 is located in a separate area, so according to the rules, interrupts must be prohibited when it is called. In addition, both steps S2021-9 and S2021-11 are processes that clear memory values sequentially (step S2021-9 clears a separate area, and step S2021-11 clears the area in use), so interrupts must be prohibited. This is because if a timer interrupt occurs while the memory is being cleared, some of the memory will have been cleared and the subsequent memory will not have been cleared, so if the value of the memory that has not been cleared is referenced, the process may not operate normally. In addition, there may be cases where the value of the memory that has been cleared is overwritten. Therefore, in such steps S2021-9 and S2021-11, neither timer interrupts nor power interrupts are allowed. Therefore, interrupts are prohibited at least before step S2021-9, in which interrupts are not allowed, is started, and the prohibition of interrupts is released (allowed) after step S2021-11, in which interrupts are not allowed, is completed.

Then, the main CPU 500a sets a game status command indicating the current game status in the transmission buffer (S2021-13). In this step S2021-13, interrupts are permitted.

When the E_RMCLR module is called in step S2021-9, the main CPU 500a sets the top address of the other area of the main RAM 500c (S1), clears the value of the main RAM 500c (S2), sets the next address of the main RAM 500c (S3), and checks the set address of the main RAM 500c (S4), as shown in FIG. 103(b). The main CPU 500a then determines whether or not clearing of the other area of the main RAM 500c is complete based on the address of the main RAM 500c (S5). If clearing of the other area of the main RAM 500c is not complete (YES in S5), the process from step S2 is repeated, and if clearing of the other area of the main RAM 500c is complete (NO in S5), the E_RMCLR module is terminated and the process returns to the routine one step above (S6).

The E_RMCLR module is designed to meet all of the above conditions (1) to (6) in order to ensure the fairness of the gaming machine while properly dividing roles between the used area and the other area. Therefore, not only are interrupts prohibited when the E_RMCLR module is called, but the values of the general-purpose registers (A register, B register, C register, D register, E register, H register, L register, F register) are also saved.

Figure 104 is an explanatory diagram for explaining an example of commands for implementing the STARTUP module and the E_RMCLR module. Of these, Figure 104(a) shows a group of commands for a portion of the STARTUP module (steps S2021-9 to S2021-13), and Figure 104(b) shows a group of commands for the E_RMCLR module. The flowchart shown in Figure 103 is implemented, for example, by the program shown in Figure 104.

The indicator "STARTUP:" on the first line of Figure 104 (a) indicates the starting address of the STARTUP module. The command "DI" on the second line disables interrupts. This interrupt disable command is written in the usage area because it must be executed at least before calling the E_RMCLR module in another area. The command "CALL E_RMCLR" on the third line calls the E_RMCLR module as a subroutine. These commands on the second and third lines correspond to step S2021-9 in Figure 103 (a).

When the E_RMCLR module is called in step S2021-9, the command group in FIG. 104(b) is executed. The index "E_RMCLR:" on the first line of FIG. 104(b) indicates the starting address of the E_RMCLR module. The command "EX AF, AF'" on the second line swaps the value of pair register AF with the value of pair register AF', which is a back register, and saves the value of pair register AF. The command "EXX" on the third line swaps the values of pair registers BC, DE, and HL with the values of pair registers BC', DE', and HL', which are back registers, and saves the values of pair registers BC, DE, and HL. In this way, the values of the general-purpose registers (A register, B register, C register, D register, E register, H register, L register, F register) are saved.

The command "LD HL, @EXT_RWM_TOP" on the fourth line of FIG. 104(b) reads the fixed value "@EXT_RWM_TOP", i.e., F210H, which is the top address of another area of main RAM 500c, into the HL register. This command on the fourth line corresponds to step S1 in FIG. 103(b). The command "XOR A" on the fifth line calculates the exclusive OR of the values in the A register and stores the result in the A register. Therefore, regardless of the value of the A register before the calculation, 0 (zero) is stored in the A register. The index "E_RMCLR01:" on the sixth line indicates the destination address of the command "JR NZ, E_RMCLR01" described later. The command "LD (HL), A" on the seventh line stores the value of the A register, i.e., 0, in the address indicated by the HL register. The command on the seventh line corresponds to step S2 in FIG. 103(b). The command on the eighth line "INC HL" adds 1 to the value of the HL register. The command on the eighth line corresponds to step S3 in FIG. 103. The command on the ninth line "CP HL, @FIL_RMC_END" compares the value of the HL register with a fixed value "@FIL_RMC_END" that indicates the final address to be cleared when changing settings in another area. That is, the zero flag is not set (zero flag = 0) until the value of the HL register matches the fixed value "@FIL_RMC_END", and when they match, the zero flag is set (zero flag = 1). The command on the ninth line corresponds to step S4 in FIG. 104. If the zero flag is not set (if it is 0), the command on the tenth line "JR NZ, E_RMCLR01" moves to E_RMCLR01. The command on line 10 corresponds to step S5 in Figure 103(a).

The command "EXX" on line 11 of FIG. 104(b) swaps the values of pair registers BC, DE, and HL with the values of pair registers BC', DE', and HL', which are backed up registers, and restores the values of pair registers BC, DE, and HL. The command "EX AF, AF'" on line 12 swaps the value of pair register AF with the value of pair register AF', which is a backed up register, and restores the value of pair register AF. Then, the command "RET" on line 13 returns to the routine one level above. This command on line 13 corresponds to step S6 in FIG. 103(b). In this way, it becomes possible to clear another area of main RAM 500c in another area.

Returning to the used area, the command "LD B, @FIL_RNK_SET" on line 4 of Figure 104 (a) reads the fixed value "@FIL_RNK_SET", i.e., the file size of the buffer, into the B register. The fixed value "@FIL_RNK_SET" is expressed as F200H-_CRE_CNT-256=501 (bytes). Here, "_CRE_CNT" indicates the address of the stored number, which indicates the start address of the buffer to be cleared. The command "LDQ DE, LOW _CRE_CNT" on line 5 sets the value of the Q register to the upper byte of the address, and the value of the lower byte of the address "_CRE_CNT" to the lower byte of the address, and reads the 2-byte value stored at that address (the address of the stored number, which indicates the start address of the buffer to be cleared) into the DE register. Then, the command "RST MEMFILL" on lines 6 and 7 calls the MEMFILL module as a subroutine.

The MEMFILL module is a general-purpose module that is a subroutine of the same process used in executing a program, and is called frequently from other modules. Upon entry into the MEMFILL module, the B register stores the file size to be cleared, and the DE register stores the start address of the file to be cleared. Starting from that start address, a buffer (memory) equivalent to the file size is cleared, up to a maximum of 256 bytes.

As described above, the command "RST MEMFILL" is executed twice on lines 6 and 7 because the target is 501 bytes, which is greater than 256 bytes. First, the command "RST MEMFILL" on line 6 clears 245 (501-256) bytes from the buffer starting at address "_CRE_CNT", and the command "RST MEMFILL" on line 7 clears the remaining 256 bytes from the next address. Note that the command "RST MEMFILL" on line 6 sets the value of the B register to 0, but in the MEMFILL module, if the value of the B register is 0, the file size starts calculation as 256, so a total of 501 bytes can be cleared. The commands on lines 4 to 7 correspond to step S2021-11 in FIG. 103(a).

Interrupts are permitted by the command "EI" on line 8 of FIG. 104(a). In this way, in steps S2021-9 and S2021-11, both timer interrupts and power interruption interrupts are prohibited, while interrupts are permitted in subsequent processing. Then, after returning from the subroutine, a command to permit interrupts is executed.

The command "LDQ (LOW _WIN_DAT + 1), 00111111B" on line 9 of Fig. 104(a) sets the value of the Q register to the upper byte of the address, and the value obtained by adding 1 to the lower byte of the address "_WIN_DAT" to the lower byte of the address, and stores the fixed value 00111111B in that address. The command "CALLF GMCMDST" on line 10 calls the GMCMDST module which executes the game status command set process.

Here, by placing the E_RMCLR module, which clears another area of the main RAM 500c, in a separate area rather than in the used area, there is a margin in the memory area (capacity) of the used area for the E_RMCLR module. Therefore, it is possible to allocate that amount of the used area to game control processing (used programs). Here, further reductions in memory area in the used area are considered.

Figure 105 is a flowchart showing another example of the initialization start process. Here, the process of Figure 103 (a) is changed to that shown in Figure 105.

As shown in FIG. 105, the main CPU 500a sets in the transmission buffer a setting change end command indicating that the setting value change has ended (S2021-1), sets in the transmission buffer a setting change state command indicating the state when the setting value change has ended (S2021-3), sets an initialization start wait timer (S2021-5), and executes a timer wait process to wait until the initialization start wait timer reaches 0 (S2021-7). Interrupts are permitted in steps S2021-1, S2021-3, S2021-5, and S2021-7.

The main CPU 500a then executes a RAM clear process to clear the used area in the main RAM 500c that is to be cleared when the setting is changed (S2021-11), and then executes a RAM clear process at the time of setting change to clear another area in the main RAM 500c (S2021-9).Then, the main CPU 500a sets a game status command indicating the current game status in the transmission buffer (S2021-13).

In FIG. 105, like FIG. 103(a), neither timer interrupts nor power interrupts are allowed in steps S2021-11 and S2021-9. Therefore, interrupts are prohibited at least before step S2021-11, in which interrupts are not allowed, is started, and the prohibition of interrupts is released (allowed) after step S2021-9, in which interrupts are not allowed, is completed. However, unlike FIG. 103(a), in FIG. 105, step S2021-9 is executed and the E_RMCLR module is called just before releasing the prohibition of interrupts. In this way, the position (area) where the command "EI" is executed can be changed, as shown below.

Figure 106 is an explanatory diagram for explaining another example of commands for realizing the STARTUP module and the E_RMCLR module. Of these, Figure 106(a) shows a group of commands for some of the STARTUP module (steps S2021-11, S2021-9, and S2021-13), and Figure 106(b) shows a group of commands for the E_RMCLR module. The flowchart shown in Figure 105 is realized, for example, by the program shown in Figure 106. Here, a description of the processes that are substantially the same as those in Figure 104 will be omitted, and only the processes that differ from those in Figure 104 will be described.

In the example of Fig. 104(a), the command "CALL E_RMCLR" is executed immediately after interrupts are prohibited by the command "DI" on line 2. In the example of Fig. 106(a), the command "CALL E_RMCLR" is executed not immediately after interrupts are prohibited by the command "DI", but immediately before executing the command "LDQ (LOW_WIN_DAT+1), 00111111B" on line 9, which allows interrupts. In other words, with interrupts prohibited by the command "DI", multiple commands that do not allow interrupts, shown on lines 4 to 8 of Fig. 106(a), are executed, and the last command of the multiple commands that do not allow interrupts, which corresponds to line 8, calls a subroutine in another area by the command "CALL E_RMCLR". Here, the multiple commands that do not allow interrupts include at least a command that does not allow interrupts placed at the end of the command group, and the command group also includes a command that allows interrupts that corresponds to preparation for executing a command that does not allow interrupts (e.g., setting a register).

In the example of Fig. 104(a), the command "EI" is executed immediately before executing the command "LDQ (LOW_WIN_DAT+1), 00111111B" on line 9, which allows interrupts, but in the example of Fig. 106, as shown in Fig. 106(b), the command "EI" (interrupt permission command) is executed before (one command before) executing the command "RET" on line 14 in the E_RMCLR module, which is a subroutine. Therefore, after returning from the subroutine, the state is immediately set to interrupt permission, and then the command to allow interrupts can be executed.

Due to the specifications of the Z80-series CPU, even if the command "EI" is executed when an interrupt is requested, the interrupt will not occur until the instruction following the command "EI" is executed. In other words, even if the command "EI" is executed before the command "RET" to return from the subroutine E_RMCLR module, the interrupt will be properly permitted after the command "RET" is executed. Therefore, even if the command "EI" is written within a subroutine in a different area, the interrupt will be permitted in the area used after returning from the subroutine.

In FIG. 104, the process is executed in the order of command "DI" → memory clearing process in another area (step S2021-9) → memory clearing process in the used area (step S2021-11) → command "EI". In contrast, in FIG. 106, the process is executed in the order of command "DI" → memory clearing process in the used area (step S2021-11) → memory clearing process in another area (step S2021-9) → command "EI" in the E_RMCLR module. By doing this, instead of adding command "EI" to the 13th line of FIG. 106(b) for the command group in FIG. 104(b), it is possible to delete command "EI" written on the 8th line of FIG. 104(a). Since command "EI" has a command size of 1 byte, 1 byte of capacity in the used area can be secured instead of occupying 1 byte of capacity in the other area. In this way, it is possible to secure the capacity of the used area, which is relatively tight, while occupying the capacity of the other area, which is relatively generous.

(Setting value switching process)
As in the above-described initialization start process, the capacity of the used area can be secured in the setting value switching process.

Figure 107 is a flow chart showing the setting value switching process. The main CPU 500a reads the program in the usage area from the main ROM 500b and executes the read program. Then, by executing the RANKSET module, the setting value switching process (S2020) shown in Figure 85 is executed, and in the RANKSET module, the E_RMCLR module in another area is called as a subroutine, thereby executing the RAM clear process shown in step S2020-3 in Figure 85.

As shown in FIG. 107, the main CPU 500a determines whether the setting value switching condition is met (S2020-1), and if it determines that the setting value switching condition is not met (YES in S2020-1), it ends the setting value switching process, and if it determines that the setting value switching condition is met (NO in S2020-1), it proceeds to step S2020-3. In step S2020-1, interrupts are permitted.

Then, the main CPU 500a executes a setting change RAM clear process to clear another area of the main RAM 500c (S2020-3A), and executes a RAM clear process to clear the used area in the main RAM 500c that is to be cleared when the setting is changed (S2020-3B). As can be understood by referring to FIG. 107, in step S2020-3, specifically, two processes, setting change RAM clear process S2020-3A and RAM clear process S2020-3B, are executed in that order. In addition, the processing of the E_RMCLR module called in the setting change RAM clear process S2020-3A has already been explained using FIG. 103(b), so a duplicate explanation will be omitted here.

The E_RMCLR module called in step S2020-3A is located in a separate area, just like the initialization start process, so according to the rules, interrupts must be prohibited when it is called. Also, both step S2020-3A and step S2020-3B are processes that clear memory values sequentially (step S2020-3A clears a separate area, and step S2020-3B clears the area in use), so interrupts must be prohibited. Therefore, neither timer interrupts nor power interrupts are allowed in these steps S2020-3A and S2020-3B. Therefore, interrupts are prohibited at least before step S2020-3A, in which interrupts are not allowed, is started, and the prohibition of interrupts is released (allowed) after step S2020-3B, in which interrupts are not allowed, is completed.

Then, the main CPU 500a performs a data table setting process when switching the setting value (S2020-5), sets a setting change start command (S2020-7), ..., determines whether the setting key is on (S2020-37), and transfers processing to the initialization start process S2021 shown in FIG. 86. Interrupts are permitted in steps S2020-5 to S2020-37.

Figure 108 is an explanatory diagram for explaining an example of commands for realizing the RANKSET module and the E_RMCLR module. Of these, Figure 108(a) shows a group of commands for some of the RANKSET module (steps S2020-3A, S2020-3B, S2020-5, and S2020-7), and Figure 108(b) shows a group of commands for the E_RMCLR module. The flowchart shown in Figure 107 is realized, for example, by the program shown in Figure 108.

The index "RANKSET:" on the first line of FIG. 108(a) indicates the starting address of the RANKSET module. The command "CALL E_RMCLR" on the second line calls the E_RMCLR module as a subroutine. This command on the second line corresponds to step S2020-3A in FIG. 107. Note that it is necessary to execute an interrupt disable command at least before calling the E_RMCLR module in another area. However, the RANKSET module is executed as part of the CPU initialization process S2000, and interrupts are not yet enabled when the RANKSET module is started. Therefore, when the RANKSET module in another area is called, interrupts are already disabled, so there is no need to execute the command "DI" as in FIG. 104(a).

When the E_RMCLR module is called in step S2020-3A, the command group in FIG. 108(b) is executed. The index "E_RMCLR:" on the first line of FIG. 108(b) indicates the starting address of the E_RMCLR module. The command "EX AF, AF'" on the second line swaps the value of pair register AF with the value of pair register AF', which is a back register, and saves the value of pair register AF. The command "EXX" on the third line swaps the values of pair registers BC, DE, and HL with the values of pair registers BC', DE', and HL', which are back registers, and saves the values of pair registers BC, DE, and HL. In this way, the values of the general-purpose registers (A register, B register, C register, D register, E register, H register, L register, F register) are saved.

The command "LD HL, @EXT_RWM_TOP" on line 4 of FIG. 108(b) reads the fixed value "@EXT_RWM_TOP", i.e., F210H, which is the top address of another area of main RAM 500c, into the HL register. The command "XOR A" on line 5 calculates the exclusive OR of the values in the A register and stores the result in the A register. Therefore, regardless of the value of the A register before the calculation, 0 (zero) is stored in the A register. The index "E_RMCLR01:" on line 6 indicates the destination address of the command "JR NZ, E_RMCLR01" described later. The command "LD (HL), A" on line 7 stores the value of the A register, i.e., 0, in the address indicated by the HL register. The command "INC HL" on line 8 adds 1 to the value of the HL register. The command on line 9, "CP HL, @FIL_RMC_END," compares the value of the HL register with the fixed value "@FIL_RMC_END," which indicates the final address to be cleared when a setting is changed in another area. In other words, the zero flag is not set (zero flag = 0) until the value of the HL register matches the fixed value "@FIL_RMC_END," and when they match, the zero flag is set (zero flag = 1). The command on line 10, "JR NZ, E_RMCLR01," moves to E_RMCLR01 if the zero flag is not set (if it is 0).

The command "EXX" on line 11 of Figure 108(b) swaps the values of pair registers BC, DE, and HL with the values of back-register pair registers BC', DE', and HL', and restores the values of pair registers BC, DE, and HL. The command "EX AF, AF" on line 12 swaps the value of pair register AF with the value of back-register pair register AF', and restores the value of pair register AF. Then, the command "RET" on line 13 returns to the routine one level above. In this way, it becomes possible to clear another area of main RAM 500c in another area.

Returning to the used area, the command "LD B, @FIL_RNK_SET" on the third line of Figure 108 (a) reads the fixed value "@FIL_RNK_SET", i.e., the file size of the buffer, into the B register. As explained in Figure 104 (a), the fixed value "@FIL_RNK_SET" is expressed as F200H-_CRE_CNT-256=501. Here, "_CRE_CNT" indicates the address of the stored number, which indicates the start address of the buffer to be cleared. The command "LDQ DE, LOW _CRE_CNT" on the fourth line makes the value of the Q register the upper byte of the address, and the value of the lower byte of the address "_CRE_CNT" the lower byte of the address, and reads the 2-byte value stored at that address (the address of the stored number, which indicates the start address of the buffer to be cleared) into the DE register. The MEMFILL module is then called as a subroutine by the command "RST MEMFILL" on lines 5 and 6. As described above, the command "RST MEMFILL" is executed twice on lines 5 and 6 because the target is 501 bytes, which is greater than 256 bytes, as explained using FIG. 104(a). The commands on lines 3 to 6 correspond to step S2020-3B in FIG. 107.

The command "LD HL, T_RNK_SET" on line 7 of Figure 108(a) sets the first address "T_RNK_SET" of the 1-byte data group that is the transfer source in the HL register. The command "RST TABLESET" on line 8 calls the TABLESET module as a subroutine. The TABLESET module is a general-purpose module that sets a specified value (initial value) to the variables in main RAM 500c. In this way, the specified value is set to the variables in main RAM 500c. The commands on lines 7 and 8 correspond to step S2020-5 in Figure 107.

Note that, when steps S2020-3A and S2020-3B, which should prohibit interrupts, are completed, the command "EI" should be executed to permit interrupts. However, the commands "DI" and "EI" are used in the TABLESET module. That is, since the command "EI" is executed in the TABLESET module, the command "EI" is not executed (not written) after the completion of steps S2020-3A and S2020-3B, which should prohibit interrupts, and the interrupt prohibition state is maintained until the command "RST TABLESET" on line 8 is executed, and the command "EI" executed in the TABLESET module is effectively used to permit interrupts. In this way, the command "EI" that should be written after the command "RST MEMFILL" on line 6 of FIG. 108(a) can be omitted.

The command "LD DE, @CMD_RNK_INI" on line 9 of Figure 108(a) sets the fixed value "@CMD_RNK_INI" in the DE register. Specifically, the fixed value ECH (subcommand message 1) is set in the D register, and the lower byte of "_CMD_CHK" (subcommand message 2) is set in the E register. The command "RST SBCMDST" on line 10 calls the SBCMDST module as a subroutine. The SBCMDST module is a general-purpose module that sets subcommands. In this way, the subcommand is set. The commands on lines 9 and 10 correspond to step S2020-7 in Figure 107.

Here, by placing the E_RMCLR module, which clears another area of the main RAM 500c, in a separate area, there is a surplus in the memory area (capacity) of the used area for the programs that have been moved to the separate area. This makes it possible to allocate that much of the used area to game control processing (used programs). Here, we consider further reductions in memory area in the used area.

Figure 109 is a flowchart showing another example of the setting value switching process. Here, the process of Figure 107 is changed to that shown in Figure 109.

As shown in FIG. 109, the main CPU 500a determines whether the setting value switching condition is met (S2020-1), and if it determines that the setting value switching condition is not met, it ends the setting value switching process, and if it determines that the setting value switching condition is met, it moves the process to step S2020-3B. In step S2020-1, interrupts are permitted.

Then, the main CPU 500a executes a RAM clear process to clear the used area in the main RAM 500c that is to be cleared when the settings are changed (S2020-3B), and executes a RAM clear process at the time of setting change to clear another area in the main RAM 500c (S2020-3A).The main CPU 500a then executes a data table set process at the time of setting value switching (S2020-5), sets a setting change start command (S2020-7), ..., determines whether the setting key is on (S2020-37), and moves the process to the initialization start process S2021 shown in FIG. 86.

In FIG. 109, like FIG. 107, neither timer interrupts nor power interrupts are allowed in steps S2020-3B and S2020-3A. Therefore, interrupts are prohibited at least before step S2020-3B, in which interrupts are not allowed, is started, and the prohibition of interrupts is released (allowed) after step S2020-3A, in which interrupts are not allowed, is completed. However, unlike FIG. 107, in FIG. 109, step S2020-3A is executed and the E_RMCLR module is called just before releasing the prohibition of interrupts. In this way, the position (area) where the command "EI" is executed can be changed, as shown below.

Figure 110 is an explanatory diagram for explaining another example of commands for realizing the RANKSET module and the E_RMCLR module. Of these, Figure 110(a) shows a group of commands for some of the RANKSET module (steps S2020-3B, S2020-3A, S2020-5, and S2020-7), and Figure 110(b) shows a group of commands for the E_RMCLR module. The flowchart shown in Figure 109 is realized, for example, by the program shown in Figure 110. Here, a description of the processes that are substantially the same as those in Figure 108 will be omitted, and only the processes that differ from those in Figure 108 will be described.

In the example of FIG. 108(a), the command "CALL E_RMCLR" which should prohibit interrupts was executed relatively early in the RANKSET module. In the example of FIG. 110(a), the command "CALL E_RMCLR" is executed not before the RANKSET module, but just before executing the command "LD HL, T_RNK_SET" on line 8 which allows interrupts. In other words, with interrupts already prohibited, multiple commands which do not allow interrupts, as shown on lines 3 to 7 of FIG. 110(a), are executed, and the last command of the multiple commands which do not allow interrupts, the command "CALL E_RMCLR", calls a subroutine in another area.

In the example of Figure 108(a), the command "EI" is executed in the TABLESET module called by the command "RST TABLET" on line 8, which allows interrupts, but in the example of Figure 110, as shown in Figure 110(b), the command "EI" (interrupt permission command) is executed immediately before executing the command "RET" on line 14 in the E_RMCLR module, which is a subroutine. Therefore, after returning from the subroutine, the state is immediately set to interrupt permission, and the command to allow interrupts can be executed.

As explained using FIG. 106, due to the specifications of the Z80 series CPU, even if the command "EI" is executed when an interrupt is requested, the interrupt will not occur until the instruction following the command "EI" is executed. In other words, even if the command "EI" is executed before the command "RET" to return from the E_RMCLR module, which is a subroutine, the interrupt will be properly permitted after the command "RET" is executed. Therefore, even if the command "EI" is written within a subroutine in a different area, the interrupt will be permitted in the area used after returning from the subroutine.

In FIG. 108, the process is executed in the following order: memory clearing process in another area (step S2020-3A) → memory clearing process in the used area (step S2020-3B) → execution of command "EI" in the TABLESET module. In contrast, in FIG. 110, the process is executed in the following order: memory clearing process in the used area (step S2020-3B) → memory clearing process in another area (step S2020-3A) → execution of command "EI" in the E_RMCLR module. This provides the following effect. In other words, in the command group in FIG. 108(b), in order to avoid duplicate execution of command "EI", it was necessary to maintain the interrupt disabled state until command "EI" was executed in the TABLESET module, but in the example in FIG. 110(a), it is possible to permit interrupts at an appropriate timing, such as immediately after the end of command "CALL E_RMCLR", which should prohibit interrupts.

<Test signal>
In the slot machine 400, the lamps displayed by the main control board 500 include the main credit display section 430, the main payout display section 432, the section indicator 460, and the operation mode indicator lamps 462 (inserted coin number indicator, start possible indicator, replay indicator, and insert possible indicator). Of these, the main credit display section 430, the main payout display section 432, and the section indicator 460 must be provided due to the specifications, but the inserted coin number indicator, start possible indicator, replay indicator, and insert possible indicator, which are the operation mode indicator lamps 462, do not necessarily need to be provided, or may be displayed instead by the liquid crystal display section 424 displayed by the sub-control board 502. Therefore, it is considered to not install the inserted coin number indicator, start possible indicator, replay indicator, and insert possible indicator.

In this way, if the number of inserted coins indicator, start enable indicator, replay indicator, and insert enable indicator are not provided, there is no need to generate the display signals (number of inserted coins signal, start enable signal, replay signal, insert enable signal) to turn them on or off. However, in the test process for slot machine 400 described in the Connection Specifications for Test Machines for Slot Machines (4th Edition), it is necessary to output test signals (number of inserted coins signal, start enable signal, replay signal, insert enable signal) that are synonymous with the display signals (number of inserted coins signal, start enable signal, replay signal, insert enable signal). However, if test signals are generated randomly in the usage area, they will occupy the usage area, unnecessarily increasing its capacity.

Therefore, by utilizing a separate area, the capacity of the area used is not increased, and even if a number of coins inserted indicator, start possible indicator, replay indicator, and input possible indicator are not provided and display signals for displaying these are not generated, test signals (number of coins inserted signal, start possible signal, replay signal, input possible signal) are appropriately output based on a signal different from the display signal.

Here, the test processing for the gaming machine can be executed in a separate area. Therefore, the E_EXOUT module written in the separate area executes the test signal output processing that outputs the test signal. By doing this, there is a surplus in the memory area (capacity) of the used area for the programs that have been moved to the separate area. Therefore, it becomes possible to allocate that much of the used area to the gaming control processing (programs used).

Of the indication signals (number of coins inserted signal, start possible signal, replay signal, insert possible signal) for turning on or off the number of coins inserted indicator, start possible indicator, replay indicator, and insert possible indicator, the "number of coins inserted signal" is not subject to the test signal. Therefore, the number of coins inserted signal will not be generated here.

The "start possible signal" is handled by providing a one-byte flag (hereafter referred to as the start possible flag (_STA_FLG)) in the used area of the main RAM 500c. For example, without referencing the display signal, the start possible flag is turned on and off instead of turning on and off the start possible indicator in the medal insertion process (MEDALIN module) or the blocker blocking pre-processing (PRE_BLK module). Then, the E_EXOUT module references the start possible flag from another area and outputs it as a test signal.

For the "replay signal", a replay active flag (_REP_FLG), which is different from the display signal, is referenced. However, the replay active flag is cleared when the motor phase is accelerating during one game, i.e., when the reels 410a, 410b, 410c start to rotate, and the replay signal cannot be maintained for one game, so it cannot be used as a test signal. Therefore, at the start of a game (for example, when the start switch 418 is operated), the contents of the replay active flag are copied to a replay signal output flag (_EC_RPGG) in another area of the main RAM 500c. The replay signal output flag maintained in another area of the main RAM 500c is then referenced from the other area and output as a test signal.

The "insertion possible signal" does not refer to the display signal, and the period during which the blocker is open is regarded as the period during which medals can be inserted. Then, the blocker output signal stored in the usage area of the main RAM 500c is referenced from a separate area and output as a test signal.

Figures 111 to 119 are explanatory diagrams for explaining the test signal output process. The numerical values of step S in these figures will only be used in the explanation of each figure. Note that duplicate explanations of processes that have already been explained in the above embodiment will be omitted.

In the medal insertion process S2200 shown in FIG. 111, compared to the medal insertion process S2200 shown in FIG. 89, instead of setting the start indicator output bit (S2200-25), a start possible flag is set (S2200-25N). In this way, in the MEDALIN module that executes the medal insertion process S2200, when the number of medals inserted reaches a specified number, the start possible flag is set (S2200-25N) on the condition that the start switch 418 has not been operated.

When the MEDALIN module is called, the commands in Figure 112 are executed. The index "MEDALIN:" on the first line of Figure 112 indicates the starting address of the MEDALIN module. The command "LDQ (LOW _STA_FLG), @TRUE" on the second line sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "_STA_FLG" as the lower byte of the address, and stores a fixed value @TRUE (-1 (FFH) in this case) in that address. In this way, the start possible signal (start possible flag) can be turned on when the start possible indicator lights up.

Here, the reason why the variable (start possible flag) is set in the used area rather than placing the variable in a separate area of main RAM 500c is as follows. Namely, if the start possible flag is set in a separate area, a subroutine from the separate area must be called, which would actually increase the command size in the used area. For example, the command "DI" would increase by one byte for each module. Also, even if an attempt is made to reference a variable in the used area from a separate area, a start possible signal cannot be generated because there is no variable indicating start possible.

The MDL_SNS module is also called by the command "CALL MDL_SNS" on the third line of FIG. 112, which corresponds to the game medal detection-related process S2200-18.

In the game medal detection related process shown in FIG. 113(a), medal detection and blocker opening and closing processes are performed. Here, the main CPU 500a subtracts the number of medals stored from the value obtained by subtracting the number of medals inserted from the maximum number of medals that can be inserted (S1), as shown in FIG. 113(a), and judges whether the subtraction result is 0 (zero) or not, that is, whether any more medals can be inserted (S2). As a result, if it is determined that medals can still be inserted (NO in S2), it checks the number of medals that can be inserted by subtracting the number of medals inserted from the maximum number of medals (S3), and judges whether the subtraction result is 0 (zero) or not, that is, whether the number of medals that can be inserted is one or not (S4). As a result, if it is determined that the number of medals that can be inserted is not one (NO in S4), it sets an output bit corresponding to the blocker (S5). Also, if the result of subtracting the number of stored medals is 0 (zero), that is, if it is determined that no more medals can be inserted (YES in S2), and if it is determined that there is only one medal left to be inserted (YES in S4), it is determined whether the blocker is blocked (S6). As a result, if the blocker is not blocked (NO in S6), the output bit corresponding to the blocker is reset (S7), and a blocker blocking process is performed to turn off the start possible signal (start possible flag) (S8).

The game medal detection-related process in FIG. 113(a) is realized by the command group of the MDL_SNS module shown in FIG. 113(b). The index "MDL_SNS:" on the first line of FIG. 113(b) indicates the starting address of the MDL_SNS module. The command "SUB B" on the second line subtracts the value of the B register (the number of medals stored) from the value of the A register (the value obtained by subtracting the number of medals inserted from the maximum number of medals). This command on the second line corresponds to step S1 in FIG. 113(a). The command "JR Z, BLKSHUT" on the third line moves to BLKSHUT (line 6) if the zero flag (Z) is 1. This command on the third line corresponds to step S2 in FIG. 113(a). The command "DEC L" on the third line subtracts the value of the L register (the number of medals inserted) from the value of the A register (the maximum number of medals). The command on the fourth line corresponds to step S3 in FIG. 113(a). The command on the fifth line "JR Z, BLKSHUT" moves to BLKSHUT (line 7) if the zero flag (Z) is 1. The command on the fifth line "SETQ @BLK_SIG_POS, (LOW _OUT_PT4)" sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "_OUT_PT4" to the lower byte of the address, and sets (sets) the bit (e.g., bit 3) indicated by @BLK_SIG_POS in the value stored at that address to 1. The command on the sixth line corresponds to step S5 in FIG. 113(a). In this way, the blocker can be opened through the image value of output port 4. In addition, depending on the change in the image value of output port 4, the start possible signal can be turned on when the start possible indicator goes off, as described below.

The indicator "BLKSHUT:" on line 7 of Figure 113(b) indicates the destination of lines 3 and 5. The command "BITQ @BLK_SIG_POS, (LOW _OUT_PT4)" on line 8 sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of address "_OUT_PT4" to the lower byte of the address, and determines the bit (e.g. bit 3) indicated by @BLK_SIG_POS in the value stored at that address. The command "RET Z" on line 9 ends the MDL_SNS module and returns to the module above if the zero flag is set. The commands on lines 8 and 9 correspond to step S6 in Figure 113(a). The command "RESQ @BLK_SIG_POS, (LOW _OUT_PT4)" on the 10th line sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "_OUT_PT4" to the lower byte of the address, and sets (resets) the bit (e.g., bit 3) indicated by @BLK_SIG_POS in the value stored at that address to 0. This command on the 10th line corresponds to step S7 in FIG. 113(a). In this way, the blocker can be closed through the image value of the output port 4. Also, in response to the change in the image value of the output port 4, as described later, the turn-on enable signal can be turned off at the timing when the start enable indicator is turned off. The command "CLRQ (LOW _STA_FLG)" on the 11th line sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "_STA_FLG" to the lower byte of the address, and stores 0 (zero) in that address. The command on line 11 corresponds to step S8 in FIG. 113(a). In this way, the start possible signal (start possible flag) can be turned off when the start possible indicator goes out.

The PRE_BLK module is also called by the command "CALLF PRE_BLK" on the fourth line of FIG. 112, which corresponds to the blocker blocking pre-processing S2200-33 shown in FIG. 111.

In the blocker blocking pre-processing shown in FIG. 114(a), instead of setting the output bit of the start possible indicator, the start possible flag is cleared. When the PRE_BLK module that executes the blocker blocking pre-processing is called, the command group in FIG. 114(b) is executed. The index "PRE_BLK:" on the first line of FIG. 114(b) indicates the starting address of the PRE_BLK module. The command "CLRQ (LOW _STA_FLG)" on the second line sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "_STA_FLG" to the lower byte of the address, and stores 0 (zero) in that address. In this way, the start possible signal (start possible flag) can be turned off when the start possible indicator goes out.

Similar to the medal insertion process S2200, the PRE_BLK module is also called in the error setting process S2011-3 shown in FIG. 84 and the credit button check process S2200-17 shown in FIG. 89.

In the error setting process shown in FIG. 115(a), the PRE_BLK module, which executes the blocker blocking pre-processing described above, is called. When the SET_ERR module, which executes the error setting process, is called, the commands in FIG. 115(b) are executed. The index "SET_ERR:" on the first line of FIG. 115(b) indicates the starting address of the SET_ERR module. The PRE_BLK module is called by the command "CALLF PRE_BLK" on the second line. In this way, the start possible signal (start possible flag) can be turned off when the start possible indicator goes out.

In the credit button check process shown in FIG. 116(a), the PRE_BLK module which executes the blocker blocking pre-processing is called. When the CANCELM module which executes the credit button check process is called, the command group in FIG. 116(b) is executed. The index "CANCELM:" on the first line of FIG. 116(b) indicates the starting address of the CANCELM module. The PRE_BLK module is called by the command "CALLF PRE_BLK" on the second line. In this way, the start possible signal (start possible flag) can be turned off when the start possible indicator goes out.

In the bonus signal setting process S2100-13 in the game start process S2100 shown in FIG. 88, the E_SGSET module in another area is called, and the bonus signal and advantageous zone signal are set. Here, the main CPU 500a acquires the replay operation flag (S1) as shown in FIG. 117(a), and sets the replay signal output flag by the acquired replay operation flag (S2). The game medal detection related process in FIG. 117(a) is realized by the command group of the E_SGSET module shown in FIG. 117(b). The index "E_SGSET:" in the first line of FIG. 117(b) indicates the top address of the E_SGSET module. The command "LD A, (_REP_FLG)" in the second line stores the replay operation flag (_REP_FLG) in the A register. Such a command in the second line corresponds to step S1 in FIG. 117(a). The command on the third line, "LD (_EX_RPFG), A," sets the variable replay signal output flag (_EX_RPFG) to the value of the A register, i.e., the replay in progress flag (_REP_FRG). This command on the third line corresponds to step S2 in FIG. 117(a).

Here, the replay operation flag (_REP_FRG) is set each time the game start process S2100 shown in FIG. 88 is executed. This means that the replay operation flag is only updated when the game starts. In this way, even if the motor phase is accelerating, that is, the replay operation flag (_REP_FRG) is cleared when the reels 410a, 410b, and 410c start to rotate, the replay signal can be maintained by the replay signal output flag (_EX_RPFG) until the game start process S2100 is next executed, that is, until one game is completed.

In the timer interrupt processing S3100 shown in FIG. 118(a), interrupt processing is performed every 1.49 msec. When the TMR_IPT module that realizes the timer interrupt processing is called, the test signal output processing S3100-23 is executed. The index "TMR_IPT:" on the first line of FIG. 118(b) indicates the starting address of the TMR_IPT module. The command "CALL E_EXOUT" on the second line calls the E_EXOUT module. In this way, a test signal can be set each time the timer interrupt processing S3100 is executed.

In the test signal output process shown in FIG. 119(a), a test signal is output. Here, the main CPU 500a acquires a start possible flag (S1), acquires an output port 4 image (S2), acquires a replay signal output flag (S3), acquires an output port 3 image (S4), and outputs a test signal to output port 8 (S5), as shown in FIG. 119(a).

The test signal output process in FIG. 119(a) is realized by a group of commands of the E_EXOUT module in another area shown in FIG. 119(b). The index "E_EXOUT:" on the first line of FIG. 119(b) indicates the start address of the E_EXOUT module. The command "LD A, (_STA_FLG)" on the second line stores the value of the start enable flag stored in the address indicated by "_STA_FLG" set in FIG. 111 to FIG. 116 in the A register. The command "AND @STA_SIG_BIT" on the third line masks the start enable flag, leaving the result of the start enable flag only in the bit indicated by "@STA_SIG_BIT" (e.g. bit 5). The commands on the second and third lines correspond to step S1 in FIG. 119(a). In this way, the "start enable signal" can be set.

The command "LD B, A" on line 4 of FIG. 119(b) copies the value of the A register to the B register, which serves as a working register for overlapping signals. The command "LD A, (_OUT_PT4)" on line 5 stores the image value of output port 4 stored at the address indicated by "_OUT_PT4" in FIG. 113 in the A register. The command "JBIT Z, @BLK_SIG_POS, A, E_EXOUT01" on line 6 determines whether the bit indicated by "@BLK_SIG_POS" in the A register (image value of output port 4) (e.g., bit 3) is zero or not. If the bit indicated by "@BLK_SIG_POS" is zero, i.e., if the blocker is blocked, it is moved to E_EXOUT01, and if it is not zero, it proceeds directly to the next process. The command on line 7, "SET @INS_SIG_POS, B," sets the bit defined by "@INS_SIG_POS" (for example, bit 6) in the value of the B register. The index "E_EXOUT01:" on line 8 indicates the destination of the command on line 6, "JBIT Z, @BLK_SIG_POS, A, E_EXOUT01." These commands on lines 5 to 8 correspond to step S2 in Figure 119(a). In this way, the "injectable signal" can be set.

The command "LD A, (_EX_RPFG)" on line 9 of Figure 119(b) stores the value of the replay signal output flag stored at the address indicated by "_EX_RPFG" set in Figure 117 in the A register. The command "JR TZ, E_EXOUT02" on line 10 moves the value of the A register to E_EXOUT02 if it is 0, i.e., if the replay signal output flag (_EX_RPFG) is not set, and if it is not zero, proceeds directly to the next process. The command "SET @REP_SIG_POS, B" on line 11 sets the bit defined by "@REP_SIG_POS" (e.g. bit 7) in the value of the B register. The index "E_EXOUT02:" on line 12 indicates the destination of the command "JR TZ, E_EXOUT02" on line 10. The commands on lines 9 to 12 correspond to step S3 in Figure 119(a). In this way, the "replay signal" can be set.

The command "LD A, (_OUT_PT3)" on line 13 of FIG. 119(b) stores the image value of output port 3 stored at the address indicated by "_OUT_PT3" in the A register. The command "AND 00001111B" on line 14 masks the upper 4 bits of the image value of output port 3 stored in the A register. The command "OR B" on line 15 calculates the logical sum of the value of the A register (the masked image value of output port 3) and the value of the B register aggregated up to line 12, and stores the result in the A register. These commands on lines 13 to 15 correspond to step S4 in FIG. 119(a). Then, the command "OUT (@OUT_PRT_8), A" on line 16 outputs the value of the A register to the image value of output port 8 stored at the address indicated by "@OUT_PRT_8". In this way, the start possible signal (bit 5), replay signal (bit 7), and input possible signal (bit 6) can be output as test signals.

Here, the test signal output process that outputs the test signal is executed by the E_EXOUT module written in a separate area, so there is a surplus in the memory area (capacity) of the used area for the programs that have been moved to the separate area. Therefore, it becomes possible to allocate that amount of the used area to the game control process (used programs).

In this way, it is possible to output a test signal appropriately without increasing the capacity of the used area, even if an insert number indicator, start possible indicator, replay indicator, or insert possible indicator is not provided.

Note that, in the above example, the start possible signal is described by manipulating a start possible flag in the use area without referring to the display signal that turns on or off the start possible indicator, and a test signal is generated based on the start possible flag in a separate area. However, not only the start possible signal, but also the replay signal and the input possible signal may be configured to manipulate a flag in the use area without referring to the display signal that turns on or off the indicator, and a test signal may be generated based on the flag in a separate area.

In addition, although an example has been described in which a test signal is not generated for the number of coins inserted signal among the display signals (number of coins inserted signal, start possible signal, replay signal, and insert possible signal), a test signal may also be generated for the number of coins inserted signal.

<Edge information>
FIG. 120 is a diagram for explaining signals input to the input ports. In the slot machine 400, input ports 0 to 2 and output ports 0 to 8 are provided as the input/output unit 704. Various signals are input to the main CPU 500a via the input ports 0 to 2. In addition, the main CPU 500a outputs various signals via the output ports 0 to 8. As shown in FIG. 120, the input ports 0 to 2 are each composed of 8 bits (1 byte). Similarly, the output ports 0 to 8 are each composed of 8 bits (1 byte). Note that, since the signals input to the input ports 0 to 2 are input as negative logic, 0 is input to the input ports 0 to 2 when the signal is on, and 1 is input to the input ports 0 to 2 when the signal is off.

The signal of the stop switch 420a (stop switch 1 signal) is input to bit 0 of input port 0. The signal of the stop switch 420b (stop switch 2 signal) is input to bit 1 of input port 0. The signal of the stop switch 420c (stop switch 3 signal) is input to bit 2 of input port 0. The signal of the fourth stop switch 420 (stop switch 4 signal) in the case where there are four stop switches 420 is input to bit 3 of input port 0. The signal of the start switch 418 (start switch signal) is input to bit 5 of input port 0. The signal of the bet switch 416 (MAX switch signal) is input to bit 6 of input port 0. The signal of the one-coin bet switch (not shown) for betting one medal (one-coin insertion switch signal) is input to bit 7 of input port 0.

A signal (medal passing sensor 1 signal) of the first medal passing sensor that detects the passage of a medal inserted through the medal insertion port 414a is input to bit 0 of input port 1. A signal (medal passing sensor 2 signal) of the second medal passing sensor that detects the passage of a medal inserted through the medal insertion port 414a is input to bit 1 of input port 1. A signal (medal passing sensor signal) of the insertion detection sensor that detects that a medal has been inserted into the medal insertion port 414a is input to bit 2 of input port 1. A signal (door opening switch signal) of the door opening switch that turns on when at least one of the front upper door 404 and the front lower door 406 is opened is input to bit 3 of input port 1. A signal (setting key switch signal) of the setting key switch is input to bit 4 of input port 1. A signal (overflow sensor signal) of the overflow sensor that detects the overflow of the medal payout device 442 is input to bit 5 of input port 1. A signal (credit button signal) of the credit button for paying out credited medals is input to bit 6 of input port 1. Bit 7 of input port 1 receives a signal from the payout sensor (payout sensor signal) that detects medals paid out from the medal payout device 442.

The signal of the first reel index sensor (first reel index sensor signal) that detects the index of the left reel 410a is input to bit 0 of the input port 2. The signal of the second reel index sensor (second reel index sensor signal) that detects the index of the center reel 410b is input to bit 1 of the input port 2. The signal of the third reel index sensor (third reel index sensor signal) that detects the index of the right reel 410c is input to bit 2 of the input port 2. The signal of the fourth reel index sensor (fourth reel index sensor signal) that detects the index of the fourth reel 410 when there are four reels 410 is input to bit 3 of the input port 2. The signal of the R chute sensor (R chute sensor signal) that detects medals passing through the R chute that connects the medal insertion port 414a and the medal payout device 442 is input to bit 4 of the input port 2. A power cut warning signal is input to bit 5 of the input port 2. Bit 6 of input port 2 receives a signal from an error reset switch (error reset switch signal) that is installed inside the housing 402 (inside the lower front door 406) and is operated to reset an error. Bit 7 of input port 2 is a spare port, and does not receive any signal (it is unused).

In this way, a maximum of 24 signals can be input to the main CPU 500a via input ports 0 to 2. The main CPU 500a then executes edge check processing in the error wait processing of steps S2020-9 (Figure 85), S2200-3 (Figure 89), and S2200-11 to generate an edge information image (8 edge information) based on the image (8 signals) input to input port 0.

Of the edge information images generated in the edge check process, the edge information of the setting change switch signal input to bit 7 of input port 0 is used in steps S2020-13 and S2020-25 (Fig. 85). The edge information of the start switch signal input to bit 4 of input port 0 is used in steps S2020-33 (Fig. 85) and S2200-27 (Fig. 89). The edge information of the MAX switch signal input to bit 5 of input port 0 and the edge information of the one-piece-in switch signal input to bit 6 of input port 0 are used in step S2200-19 (Fig. 89).

The main CPU 500a also executes edge clear processing to clear the edge information image in steps S2100-15 (FIG. 88) and S2200-15 (FIG. 89). Furthermore, the main CPU 500a updates the previously acquired image of input port 0 (previous image) in the state restoration processing in step S2030.

Figure 121 is an explanatory diagram for explaining the edge check process. The numerical values of step S in this figure will be used only in the explanation of this figure.

In edge check processing, as shown in FIG. 121(a), the main CPU 500a acquires an image of input port 0 (S1), acquires and updates the previous image (S2), checks (generates) the edge information image (S3), sets the edge information image in the C register (S4), and returns to the routine one level above (S5).

The edge check process in FIG. 121(a) is realized by the commands of the EDGECHK module shown in FIG. 121(b). The index "EDGECHK:" on the first line of FIG. 121(b) indicates the starting address of the EDGECHK module. The command "LDQ A, (LOW _IN0_NEW)" on the second line sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "_IN0_NEW" to the lower byte of the address, and reads the value indicated at that address (image of input port 0, current image) into the A register. This command on the second line corresponds to step S1 in FIG. 121(a).

The command on line 3, "LDQ HL, LOW _IN0_OLD," sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "_IN0_OLD" to the lower byte of the address, and stores that address in the HL register. The command on line 4, "LD C, (HL)," reads the value (previous image) stored at the address indicated by the HL register into the C register. The command on line 5, "LD (HL), A," stores the value of the A register at the address indicated by the HL register. These commands on lines 3 to 5 correspond to step S2 in FIG. 121(a).

The command "XOR A, C" on line 6 calculates the exclusive OR of the value of the A register (image of input port 0) and the value of the C register (previous image), and stores the result in the A register. Here, only bits that differ between the image of input port 0 and the previous image become 1 due to the exclusive OR. The command "AND A, C" on line 7 calculates the logical product of the value of the A register and the value of the C register, and stores the result in the A register. Here, only bits that have switched from off (1) to on (0) become 1 due to the logical product of the 1 (off) before the switch and the 1 obtained by the exclusive OR, and bits that have switched from on (0) to off (1) do not become 1. These commands on lines 6 and 7 correspond to step S3 in FIG. 121(a).

The command "LD C, A" on line 8 stores the value of the A register in the C register. This command on line 8 corresponds to step S4 in FIG. 121(a). The command "RET" on line 9 returns to the routine one level above. This command on line 9 corresponds to step S5 in FIG. 121(a). In this way, the edge information image is updated (stored in the C register) based on the image of input port 0.

Figure 122 is an explanatory diagram for explaining edge clear processing. The numerical values of step S in this figure will be used only in the explanation of this figure.

In edge clear processing, the main CPU 500a clears the edge information image stored in the C register (S1) as shown in FIG. 122(a) and returns to the routine one level above (S2).

The edge clear process in FIG. 122(a) is realized by the commands of the EDGECLR module shown in FIG. 122(b). The index "EDGECLR:" on the first line of FIG. 122(b) indicates the start address of the EDGECLR module. The command "XOR A, A" on the second line calculates the exclusive OR of the values in the A register and stores the result in the A register. Therefore, regardless of the value of the A register before the calculation, 0 (zero) is stored in the A register. The command "LD C, A" on the third line stores the value of the A register (0) in the C register. These commands on the second and third lines correspond to step S1 in FIG. 122(a). The command "RET" on the fourth line returns to the routine one level above. This command on the fourth line corresponds to step S2 in FIG. 122(a). In this way, the edge information stored in the C register is cleared.

Figure 123 is an explanatory diagram for explaining the RECOVER module. The index "RECOVER:" on the first line of Figure 123 indicates the starting address of the RECOVER module. The command "CALLF LD_PORT" on the second line reads out the LD_PORT module. In the LD_PORT module, the image of input port 0 is stored in the A register. The command "LDQ (LOW _IN0_OLD), A" on the third line sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "_IN0_OLD" as the lower byte of the address, and stores the value of the A register (previous image) at that address.

In the slot machine 400, in addition to input port 0, edge information of signals input to input port 1 and input port 2 may be obtained. For example, in addition to the start switch signal input to bit 4 of input port 0, the MAX switch signal input to bit 5 of input port 0, the one-coin switch signal input to bit 6 of input port 0, and the setting change switch signal input to bit 7 of input port 0, edge information of the credit button signal input to bit 6 of input port 1 and the error release switch signal input to bit 6 of input port 2 may be obtained. In such a case, if the EDGECHK module shown in FIG. 121(b), the EDGECLR module shown in FIG. 122(b), and the RECOVER module shown in FIG. 123 are created for each input port, the capacity will increase.

Therefore, in another example of edge check processing, only the bits of the signals that obtain edge information are collected from the signals input to multiple input ports to generate a single image (1-byte image), thereby consolidating the edge information of the signals input to multiple input ports into a single (1-byte) edge information image.

Figure 124 is an explanatory diagram explaining another example of edge check processing. In another example of edge check processing, as shown in Figure 124 (a), the main CPU 500a acquires an image of input port 0 (S1) and masks the lower 4 bytes (S2). Then, the main CPU 500a acquires an image of input port 1 and determines whether the signal of bit 6 is not 0 (S3). If bit 6 of the image of input port 1 is 0 (NO in S3), the main CPU 500a sets bit 0 of the image masked in step S2 to 0 (S4). After that, the main CPU 500a acquires an image of input port 2 and determines whether bit 6 is not 0 (S5). If bit 6 of the image of input port 2 is 0 (NO in S5), the main CPU 500a sets bit 1 of the image updated in step S4 to 0 (S6).

Then, the main CPU 500a acquires and updates the previous image (S7), checks (generates) the edge information image (S8), sets the edge information image in the C register (S9), and returns to the routine one step above (S10). In this way, as shown in FIG. 124(b), a 1-byte edge information image can be generated in which the edge information (credit button edge information) of the signal at bit 6 of input port 1 is assigned to bit 0, the edge information (error release switch edge information) of the signal at bit 6 of input port 2 is assigned to bit 1, and the edge information (start switch edge information, MAX switch edge information, one-coin insertion switch edge information, setting change switch edge information) of the signal at bits 4 to 7 of input port 0 are assigned to bits 4 to 7, respectively.

Figure 125 is an explanatory diagram for explaining another example of the EDGECHK module. The edge check process in Figure 124(a) is realized by the command group of the EDGECHK module shown in Figure 125. The index "EDGECHK:" on the first line of Figure 125 indicates the starting address of the EDGECHK module. The command "LDQ A, (LOW _IN0_NEW)" on the second line sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "_IN0_NEW" as the lower byte of the address, and reads the value indicated by that address (image of input port 0) into the A register. The command on the first line corresponds to step S1 in Figure 124(a). The command "OR A, 00001111B" on the third line masks the lower 4 bits of the image value of input port 0 stored in the A register (sets it to 1). As mentioned above, the input port is negative logic, so the logical OR with 1 becomes the mask. The command on the third line corresponds to step S2 in Figure 124 (a).

The "JBITQ NZ, @CAN_SWI_POS, (LOW _IN1_NEW), EDGECHK01" on the fourth line sets the value of the Q register as the most significant byte of the address, and the value of the least significant byte of the address "_IN1_NEW" as the most significant byte of the address. If the bit (bit 6) indicated by the value "@CAN_SWI_POS" in the value indicated at that address (image of input port 1) is not 0, then it moves to the address indicated by the index "EDGECHK01", and if it is 0, then it moves directly to the next process. This process on the fourth line corresponds to step S3 in FIG. 124(a).

The "RES @CAN_EDG_POS, A" on the fifth line sets the bit (bit 0) of the A register value indicated by the value "@CAN_EDG_POS, A" to 0. This processing on the fifth line corresponds to step S4 in FIG. 124(a).

The index "EDGECHK01:" on the sixth line indicates the destination address of the above command "JBITQ NZ, @CAN_SWI_POS, (LOW_IN1_NEW), EDGECHK01".

The "JBITQ NZ, @ERS_SWI_POS, (LOW _IN2_NEW), EDGECHK02" on line 7 sets the value of the Q register to the upper byte of the address, and the value of the lower byte of the address "_IN2_NEW" to the lower byte of the address. If the bit (bit 6) indicated by the value "@ERS_SWI_POS" in the value indicated at that address (image of input port 2) is not 0, then it moves to the address indicated by the index "EDGECHK02", and if it is zero, it moves directly to the next process. This process on line 7 corresponds to step S5 in Figure 124 (a).

The "RES @ERS_EDG_POS, A" on line 8 sets the bit (bit 1) indicated by the value "@ERS_EDG_POS, A" in the A register to 0. This causes the current image to be stored in the A register. The processing on line 8 corresponds to step S6 in FIG. 124(a).

The index "EDGECHK02:" on the 9th line indicates the destination address of the above command "JBITQ NZ, @ERS_SWI_POS, (LOW_IN2_NEW), EDGECHK02".

The command on line 10, "LDQ HL, LOW _INI_OLD," sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "_INI_OLD" to the lower byte of the address, and stores that address in the HL register. The command on line 11, "LD C, (HL)," reads the value (previous image) stored at the address indicated by the HL register into the C register. The command on line 12, "LD (HL), A," stores the value of the A register at the address indicated by the HL register. These commands on lines 10 to 12 correspond to step S7 in FIG. 124(a).

The command "XOR A, C" on line 13 calculates the exclusive OR of the value in the A register and the value in the C register (previous image), and stores the result in the A register. The command "AND A, C" on line 14 calculates the logical AND of the value in the A register and the value in the C register, and stores the result in the A register. These commands on lines 13 and 14 correspond to step S8 in Figure 124 (a).

The command "LD C, A" on line 15 stores the value of the A register in the C register. This command on line 15 corresponds to step S9 in FIG. 124(a). The command "RET" on line 16 returns to the routine one level above. This command on line 16 corresponds to step S10 in FIG. 124(a).

Figure 126 is an explanatory diagram for explaining another example of the EDGECLR module and the RECOVER module. Here, the module in Figure 122(b) is modified as shown in Figure 126(a). Here, the explanation of the processing that is substantially the same as in Figure 122(b) is omitted, and only the processing that differs from Figure 122(b) is explained.

The EDGECHK module is called by the command "CALLF EDGECHK" on the second line of Figure 126 (a). In the EDGECHK module, the edge information image is stored in the C register.

The module in FIG. 123 is modified as shown in FIG. 126(b). Here, we will omit the explanation of the processes that are essentially the same as those in FIG. 123, and only explain the processes that differ from those in FIG. 123.

The EDGECHK module is called by the command "CALLF EDGECHK" on the second line of Figure 126 (b). In the EDGECHK module, the command on line 12 sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "_INI_OLD" as the lower byte of the address, and stores the previous image at that address.

In this way, images are acquired from multiple input ports, and a portion of the acquired images (signals with a specified bit number) are collected to generate a single image (current image, previous image, edge information image). This eliminates the need to generate an image for each input port, and also eliminates the need to provide a module for generating the images, resulting in more space in the memory area (capacity) of the used area. This makes it possible to allocate that much of the used area to game control processing (programs used).

<Extended startup wait time>
When the main CPU 500a is powered on, it executes the above-mentioned CPU initialization process (FIG. 82). In the CPU initialization process, a value equivalent to 3 seconds is set as the wait processing time in step S2000-3, and it is determined in step S2000-7 whether the wait processing time has elapsed. This wait processing time is set in order to wait for a stable supply of power and to wait for initialization processing of the performance devices such as the liquid crystal display unit 424, the performance lamp 426, and the performance props (not shown) controlled by the sub-control board 502.

In recent years, however, the number of presentation devices controlled by the sub-control board 502, such as the LCD display unit 424, presentation lamps 426, and presentation props (not shown), has increased, and the mechanisms have become more complex, so that the initialization process for these presentation devices is taking longer.

As a result, it is possible to extend the wait processing time from 3 seconds to, for example, 10.5 seconds. However, if the wait processing time is extended to 10.5 seconds, the front upper door 404 or the front lower door 406 will be opened during that time, increasing the possibility of fraudulent activity (so-called cheating).

Therefore, by determining whether or not at least one of the front upper door 404 and the front lower door 406 has been opened before the wait processing time has elapsed, and outputting an external signal if at least one of the front upper door 404 and the front lower door 406 has been opened, security against fraudulent activity is improved.

Figure 127 is a flowchart explaining another example of CPU initialization processing. The numerical values of steps S in this figure will be used only in the explanation of this figure. Also, the CPU initialization processing shown in Figure 127 is a replacement for steps S2000-3 to S2000-7 in the CPU initialization processing shown in Figure 82, and is otherwise similar to the CPU initialization processing shown in Figure 82.

In the CPU initialization process shown in FIG. 127, the main CPU 500a sets the number of repetitions to 105 (S1). Then, the main CPU 500a acquires an image of the input port 1 (S2) and outputs an image of the output port 2 (door opening signal) (S3). After that, the main CPU 500a sets 45713 as the wait processing timer (S4) and acquires the power-off warning signal (input port 2) (S5). Then, the main CPU 500a determines whether the power-off warning signal is on (S6), and if the power-off warning signal is on (YES in S6), the process returns to step S1, and if the power-off warning signal is not on (NO in S6), the wait processing timer is decremented by 1 (S7). After that, the main CPU 500a determines whether the wait processing timer is 0 (S8), and if the wait processing time is not 0 (NO in S8), the process returns to step S5, and if the wait processing timer is 0 (YES in S8), the repeat count is decremented by 1 (S9). The main CPU 500a then determines whether the number of repetitions is 0 (S10), and if the number of repetitions is not 0 (NO in S10), returns the process to step S2, and if the number of repetitions is 0 (YES in S10), executes the process from step S2000-9 onwards in FIG. 82.

When the number of repetitions is 1, the image of output port 2 output in step S3 is cleared in step S3100-21 (Figure 98) in the timer interrupt process.

Figure 128 is an explanatory diagram explaining the INITIAL module. The CPU initialization process in Figure 127 is realized by the command group of the INITIAL module shown in Figure 128. The index "INITIAL:" on the first line of Figure 128 indicates the start address of the INITIAL module. The index "INITIAL02:" on the second line indicates the destination address of the command "JBIT Z, @PWF_SIG_POS, A, INITIAL02" described later.

The command "LD B, 105" on the third line stores the value "105" in the B register. This command on the third line corresponds to step S1 in FIG. 127. The index "INITIAL03:" on the fourth line indicates the destination address of the command "DJNZ INITIAL03" described later.

The command "IN A, (@IN_PRT_1)" on line 5 reads the value of the address indicated by the value "@IN_PRT_1" (image of input port 1) into the A register. This command on line 5 corresponds to step S2 in FIG. 127. The command "CPL" on line 6 inverts the bits in the value of the A register. The command "AND A, @DOR_SWI_BIT" on line 7 calculates the logical product of the value of the A register and the value "@DOR_SWI_BIT" (00001000B), and stores the result in the A register. Here, all bits in the image of input port 1 are set to 0 except for the door open signal based on the door open switch signal at bit 3. The command "OUT (@DOR_PRT_2), A" on line 8 outputs the value of the A register to the address indicated by the value "@DOR_PRT_2" (output port 2). The commands on lines 5 to 8 correspond to step S3 in Figure 127.

The "LD DE, 45713" command on the 9th line stores the value "45713" in the DE register. This command on the 9th line corresponds to step S4 in FIG. 127. The index "INITIAL04:" on the 10th line indicates the destination address for the command "JR NTZ, INITIAL04" described below.

The command "IN A, (@IN_PRT_2)" on line 11 reads the value of the address indicated by the value "@IN_PRT_2" (image of input port 2) into the A register. This command on line 11 corresponds to step S5 in FIG. 127.

The command on line 12, "JBIT Z, @PWF_SIG_POS, A, INITIAL02," determines whether the bit (bit 5) indicated by the value "@PWF_SIG_POS" in the A register (image of input port 2) is 0. If the bit indicated by "@PWF_SIG_POS" is 0, that is, if the power-off warning signal is on, it moves to INITIAL02, and if it is not 0, it moves directly to the next process. This command on line 12 corresponds to step S6 in FIG. 127.

The command "DEC DE" on line 13 decrements (subtracts) the value of the DE register by 1. When the value of the DE register becomes 0, the second zero flag is set and becomes 1. This command on line 13 corresponds to step S7 in Figure 127. The command on line 14, "JR NTZ, INITIAL04", moves to INITIAL04 if the second zero flag is not set, and moves directly to the next process if the second zero flag is set. This command on line 14 corresponds to step 8 in Figure 127.

The command "@DJNZ INITIAL03" on line 15 decrements (subtracts) the value of the B register by 1, and if the value of the B register is not 0, it moves to INITIAL03, and if the value of the B register is 0, it moves directly to the next process. This command on line 15 corresponds to steps S9 and S10 in Figure 127.

Here, the main control board 500 is equipped with a 32 MHz crystal oscillator, and the main CPU 500a switches the clock on/off when the signal output from the crystal oscillator changes from off to on. Therefore, the main CPU 500a clocks 16 million times per second (defining the operating timing).

And each command has a state number, i.e., the number of clocks required to execute that command. In the example of FIG. 128, the number of states for the command on the third line is 7, the number of states for the command on the fifth line is 11, the number of states for the command on the sixth line is 4, the number of states for the command on the seventh line is 7, the number of states for the command on the eighth line is 11, the number of states for the command on the ninth line is 10, the number of states for the command on the eleventh line is 11, the number of states for the command on the twelfth line is 12, the number of states for the command on the thirteenth line is 4, the number of states for the command on the fourteenth line is 8/7, and the number of states for the command on the fifteenth line is 8/7. Note that the number of states for the commands on the fourteenth and fifteenth lines is 8 if a branch (jump) occurs, and 7 if no branching occurs.

When the INITIAL module shown in Figure 128 is executed, 7 states, or 7 clocks, pass for the command on line 3. Then, 11 + 4 + 7 + 11 + 10 = 43 states, or 43 clocks, pass for the commands on lines 5 to 9.

The commands on lines 11 to 14 will be executed 45713 times (a loop process will be executed), with the number of states being 11+12+4+8=35 states for the 1st to 45712th iterations, and 11+12+4+7=34 states for the 45713th iteration. In other words, when the commands on lines 11 to 14 are repeated 45713 times, the number of states will be 35 x 45712 + 34 = 1599954 states. The time it takes the main CPU 500a to execute the process for 1599954 states will be approximately 100 ms (1599954/16000000 seconds).

Then, after 1,599,954 clock cycles have elapsed, the command on line 15 is executed without branching due to the command on line 14, and the value of the B register (number of iterations) is decremented by 1.

The number of repetitions is 105, but for the 1st to 104th repetitions, the number of states for the commands on lines 5 to 15 is 43 + 1599954 + 8 = 1600005, and for the 105th repetition, the number of states for the commands on lines 5 to 15 is 43 + 1599954 + 7 = 1600004. Therefore, the total number of states for the module in Figure 128 is 7 + 1600005 x 104 + 1600004 = 168000531. And since the main CPU 500a ticks the clock 16 million times per second, the time that elapses when the module in Figure 128 is executed is 168000531/16000000 = 10.5000331875 seconds. In other words, the wait processing time is approximately 10.5 seconds.

In addition, regulations stipulate that the door open signal must be output continuously for at least 50 ms, so in order to execute the command on line 8 again after executing it, the commands on lines 11 to 14 must be executed 45,713 times. In other words, approximately 100 ms will pass before the door open signal is updated.

As a result, in the slot machine 400, the door open signal can be output continuously for approximately 100 ms during the CPU initialization process, thereby satisfying the rules. In addition, security against fraudulent activity can be improved by extending the wait processing time.

In addition, while the INITIAL module shown in FIG. 128 is being executed, access to the main RAM 300c is prohibited. Therefore, the image (door open signal) of output port 2 is output without using the main RAM 300c.

Figure 129 is a diagram comparing input port 1 and output port 2. As shown in Figure 129, based on the door opening switch signal of bit 3 of input port 1, an external signal 4 (door opening signal) of bit 3 of output port 2 is output. Here, the bit number at which the door opening switch signal (predetermined signal) is input in input port 1 and the bit number at which the door opening signal based on the door opening switch signal is output in output port 2 are both set to the same as bit 3. As a result, the door opening signal can be output without the need for shift processing, etc., by simply inverting the bit and outputting the door opening switch signal of bit 3 of input port 1. This creates a surplus in the storage area (capacity) of the usage area. Therefore, it is possible to allocate that much of the usage area to game control processing (usage program).

Note that, although the case where a door open signal is output as the specified signal has been described here, the specified signal may be another signal. Furthermore, the bit number at which the specified signal is input in the input port and the bit number at which a signal based on the specified signal is output in the output port may be set to be the same.

Although the preferred embodiment of the present invention has been described above with reference to the attached drawings, it goes without saying that the present invention is not limited to such an embodiment. It is clear that a person skilled in the art can come up with various modified or revised examples within the scope of the claims, and it is understood that these also naturally fall within the technical scope of the present invention.

100 Gaming machine 300, 500 Main control board 300a, 500a Main CPU
300b, 500b Main ROM
300c, 500c Main RAM
330, 502 Sub-control board 330a, 502a Sub-CPU
330b, 502b Sub ROM
330c, 502c, Sub RAM
400 Slot Machine

Claims (2)

A gaming machine comprising a CPU, a ROM storing a program used by the CPU, and a RAM for holding variables updated by the program, on a predetermined board used for the progress of a game,
The CPU includes:
Reading from the ROM the program to be executed when power is turned on;
Based on the program,
Execute loop processing with multiple commands,
A gaming machine that executes a command to output an external signal in the loop processing. The CPU includes:
2. The gaming machine according to claim 1, wherein if the external signal has been output when the final loop process is completed, the external signal is cleared by a predetermined timer interrupt process.

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