JP7410902B2 - gaming machine - Google Patents

Description

TECHNICAL FIELD The present invention relates to a gaming machine that uses a lottery to determine whether or not to award a gaming benefit to a player.

In general, in a gaming machine (pachinko machine), a game ball is launched toward a gaming area within the gaming board by the player's handle operation, and a special condition is set in which the gaming ball that flows down the gaming area enters the starting port. A lottery regarding the symbols is executed. Then, on the special symbol display, the special symbol is displayed in a variable manner, and furthermore, the special symbol determined by the lottery is stopped and displayed, thereby notifying the player of the lottery result.

At this time, when a specific special symbol indicating a jackpot is stopped and displayed on the special symbol display, a big prize game that is more advantageous to the player than a normal game is started. In this big prize game, the attacker device opens and closes a predetermined number of times, allowing game balls to enter the big prize opening, allowing the player to receive a payout of many prize balls.

In such gaming machines, it is desirable to effectively utilize the limited storage area in the memory in order to enhance the gameplay. For example, a technique is known in which management values are associated with control information in a data set table to effectively use memory (for example, Patent Document 1).

Japanese Patent Application Publication No. 2016-214339

In a game machine, a program related to game control processing that controls the progress of the game must be placed in the usable area (4.5 kbyte control area + 3.0 kbyte data area) in the ROM of the main control board.

However, as game information becomes more complex in accordance with the variety of games, there is a risk that the use area, particularly the control area, will be squeezed.

In view of such problems, an object of the present invention is to provide a gaming machine that can secure the capacity of a control area for performing game control processing.

In order to solve the above problems, the present invention provides a processor, a storage means for storing data, a predetermined device, and a random number generation unit that generates random numbers on a predetermined board used for playing the game. In the gaming machine, the random number generation unit includes a maximum value fixed random number generator in which the maximum value of the random number is fixed, and a maximum value setting random number generator in which the maximum value of the random number can be set, and the random number generation unit includes a maximum value setting random number generator in which the maximum value of the random number can be set. A random number generated by the maximum value fixed random number generator or the maximum value setting random number generator is used as the random number, and the storage means and the device are respectively allocated to different address ranges on the memory space, and the In the same program, the processor may access the device by a command based on a memory mapped I/O method for accessing the storage means, and may also access the device using an I/O mapped command for accessing the device. The device may be accessed by a command based on an I/O method.

According to the present invention, it is possible to secure the capacity of a control area for performing game control processing.

It is a perspective view of a game machine showing a state in which a door according to a simultaneous rotation reference example is opened. It is a front view of a gaming machine according to a simultaneous spinning reference example. It is a figure explaining the 2nd big prize winning hole concerning a simultaneous spin reference example. It is a block diagram showing the internal configuration of a control means for controlling the progress of a game according to a simultaneous play reference example. It is an address map of the memory area used by the main CPU according to the simultaneous rotation reference example. It is a figure explaining the low probability jackpot determination random number determination table according to the simultaneous rotation reference example. It is a diagram explaining a random number determination table for determining a jackpot at high accuracy according to a simultaneous rotation reference example. It is a figure explaining a winning pattern random number determination table and a small winning pattern random number determination table according to a simultaneous rotation reference example. It is a figure explaining the reach group determination random number determination table based on a simultaneous rotation reference example. It is a figure explaining the reach mode determination random number determination table based on a simultaneous rotation reference example. It is a figure explaining the variation pattern random number determination table based on a simultaneous rotation reference example. It is a figure explaining the variable time determination table based on a simultaneous rotation reference example. It is a figure explaining the game state and fluctuation time concerning a simultaneous play reference example. It is the 1st figure explaining the special electric accessory operation ram set table concerning a simultaneous rotation reference example. It is the 2nd figure explaining the special electric accessory operation ram set table concerning a simultaneous rotation reference example. It is a figure explaining the game state setting table concerning a simultaneous rotation reference example. It is a figure explaining a winning decision random number judgment table concerning a simultaneous rotation reference example. (a) is a diagram explaining a normal symbol fluctuation time data table according to a simultaneous rotation reference example, and (b) is a diagram explaining an opening/closing control pattern table according to a simultaneous rotation reference example. It is a figure explaining the transition of the game state in accordance with the original game nature according to the simultaneous play reference example. It is a diagram explaining the transition of the game state when the game is not played properly according to the simultaneous play reference example. It is a figure explaining the gaming machine state flag concerning a simultaneous rotation reference example. It is a 1st flowchart explaining the CPU initialization process in the main control board based on a simultaneous rotation reference example. It is a 2nd flowchart explaining the CPU initialization process in the main control board based on a simultaneous rotation reference example. 12 is a flowchart illustrating sub-command group set processing in the main control board according to a simultaneous execution reference example. 12 is a flowchart illustrating a power-off evacuation process in the main control board according to a simultaneous rotation reference example. 12 is a flowchart illustrating timer interrupt processing in a main control board according to a simultaneous running reference example. 12 is a flowchart illustrating setting-related processing in the main control board according to a simultaneous rotation reference example. 12 is a flowchart illustrating switch management processing in a main control board according to a simultaneous rotation reference example. It is a flowchart explaining the gate passing process in the main control board based on a simultaneous rotation reference example. It is a flowchart explaining the 1st starting port passage process in the main control board based on a simultaneous rotation reference example. It is a flowchart explaining the 2nd starting port passage process in the main control board based on a simultaneous rotation reference example. It is a flowchart explaining the special symbol random number acquisition process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the effect determination process at the time of acquisition in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the big winning a prize opening passage process in the main control board according to the simultaneous rotation reference example. It is a diagram explaining a special game management phase and a special electric accessory game management phase according to a simultaneous play reference example. It is a flowchart explaining the special game management process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the special symbol change waiting process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the special symbol hit determination process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the special symbol variation number determination process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the number cut management process in the main control board according to a simultaneous rotation reference example. It is a flowchart explaining the process during special symbol fluctuation in the main control board according to the simultaneous rotation reference example. It is a flow chart explaining pattern forced stop processing in the main control board concerning a simultaneous rotation reference example. It is a flowchart explaining the special symbol stop symbol display processing in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the special electric accessory game management process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the big prize opening pre-opening process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the big prize opening opening/closing switching process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the big prize opening control process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the big prize opening closing effective processing in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the big winning a prize opening end wait process in the main control board according to the simultaneous rotation reference example. It is a diagram explaining a normal game management phase according to a simultaneous play reference example. It is a flowchart explaining the normal game management process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the normal symbol change waiting process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the process during normal symbol fluctuation in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the normal symbol stop symbol display processing on the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the normal electric accessory prize opening pre-opening process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the normal electric accessory prize opening opening/closing switching process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the normal electric accessory prize opening control process in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the normal electric accessory prize winning opening closing effective processing in the main control board according to the simultaneous rotation reference example. It is a flowchart explaining the normal electric accessory winning a prize opening end wait process in the main control board according to the simultaneous rotation reference example. It is a figure explaining an example of the fluctuation performance of the non-reach fluctuation pattern concerning a performance reference example. It is a figure explaining an example of the fluctuation performance of the normal reach fluctuation pattern concerning a performance reference example. It is a figure explaining an example of the fluctuation performance of the developed reach fluctuation pattern at the time of loss according to the performance reference example. It is a figure explaining an example of the fluctuation performance of the developed reach fluctuation pattern at the time of a jackpot according to the performance reference example. It is a figure explaining an example of the fluctuating performance when the reach development performance concerning a performance reference example is performed twice. It is a figure explaining an example of the fluctuation performance of the pseudo continuous reach fluctuation pattern concerning a performance reference example. It is a figure explaining the variable production decision table concerning a production reference example. It is a figure explaining an example of the hold display performance concerning a performance reference example. (a) is a diagram explaining the final pending display pattern determination table according to the production reference example, and (b) is a diagram explaining the previous suspension display pattern determination table according to the production reference example. It is a flowchart explaining sub CPU initialization processing in a sub control board concerning a performance reference example. It is a flowchart explaining the sub-timer interruption process in the sub-control board based on a performance reference example. It is a flowchart explaining the prefetch designation command reception process in the sub-control board based on a performance reference example. It is a flowchart explaining the fluctuation command reception process in the sub-control board concerning a performance reference example. FIG. 2 is an external view for explaining a schematic mechanical configuration of a slot machine. FIG. 2 is an external view of the slot machine with the front door opened for explaining the general mechanical configuration of the slot machine. It is a figure explaining the pattern arrangement of a reel, and an active line. 1 is a block diagram showing a schematic electrical configuration of a slot machine. FIG. It is an explanatory diagram for explaining a winning combination. It is a figure showing a winning type lottery table. It is a figure showing a winning type lottery table. It is an explanatory diagram for explaining transition of a game state. FIG. 3 is an explanatory diagram for explaining the transition of performance states. 3 is a flowchart illustrating CPU initialization processing in the main control board. It is a flowchart explaining cold start processing in a main control board. 3 is a flowchart illustrating error stop processing in the main control board. 3 is a flowchart illustrating a setting value switching process in the main control board. 3 is a flowchart illustrating initialization start processing in the main control board. 3 is a flowchart illustrating state recovery processing in the main control board. It is a flowchart explaining game start processing in the main control board. It is a flowchart explaining the game medal insertion process in the main control board. It is a flowchart explaining internal lottery processing in a main control board. It is a flowchart explaining the pattern code setting process in the main control board. It is a flowchart explaining processing during rotation of a drum in a main control board. It is a flow chart explaining rotation drum stop processing in a main control board. 3 is a flowchart illustrating display determination processing in the main control board. It is a flow chart explaining payout processing in a main control board. It is a flowchart explaining game transfer processing in the main control board. 3 is a flowchart illustrating a power-off save process in the main control board. 3 is a flowchart illustrating timer interrupt processing in the main control board. FIG. 3 is a diagram for explaining electrical connections around a main CPU. FIG. 2 is a block diagram showing the internal configuration of a CPU core. FIG. 2 is a diagram illustrating the configuration of a register. FIG. 2 is an explanatory diagram showing a memory map. FIG. 3 is an explanatory diagram showing the appearance of the main control board. FIG. 3 is an explanatory diagram for explaining a display mode of a ratio display section. It is a flowchart which shows the 1st calculation example of accessory ratio. FIG. 3 is an explanatory diagram for explaining a first calculation example using only 8-bit MUL instructions. 7 is a flowchart showing specific processing for realizing the first calculation example. FIG. 7 is a diagram showing an example of a specific command for realizing the first calculation example. FIG. 7 is an explanatory diagram for explaining a second calculation example using a 16-bit multiplier. 7 is a flowchart showing specific processing for realizing a second calculation example. FIG. 7 is a diagram showing an example of a specific command for realizing a second calculation example. FIG. 7 is a diagram showing an example of a specific command for realizing the first calculation example. FIG. 7 is an explanatory diagram for explaining a third calculation example using repeated subtraction of a number multiplied by a power of 2; 12 is a flowchart showing specific processing for realizing a third calculation example. FIG. 7 is a diagram showing an example of a specific command for realizing a third calculation example. 12 is a flowchart showing specific processing for realizing a fourth calculation example. FIG. 12 is a diagram showing an example of a specific command for realizing a fourth calculation example. 12 is a flowchart showing specific processing for realizing a fifth calculation example. FIG. 12 is a diagram showing an example of a specific command for realizing a fifth calculation example. 12 is a flowchart showing specific processing for realizing a sixth calculation example. FIG. 12 is a diagram showing an example of a specific command for realizing a sixth calculation example. 3 is a flowchart showing specific processing of the BYTESEL module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a BYTESEL module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a BYTESEL module. FIG. 7 is an explanatory diagram for explaining another example of commands for implementing the BYTESEL module. FIG. 7 is an explanatory diagram for explaining still another example of commands for implementing the BYTESEL module. 3 is a flowchart showing specific processing of the WORDSEL module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a WORDSEL module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a WORDSEL module. FIG. 7 is an explanatory diagram for explaining another example of commands for realizing the WORDSEL module. FIG. 7 is an explanatory diagram for explaining still another example of commands for implementing the WORDSEL module. It is an explanatory diagram for explaining a CAL_MOD module. It is an explanatory diagram for explaining a HID_JUG module. 3 is a flowchart showing specific processing of the RAMSET module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing a RAMSET module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing a RAMSET module. FIG. 7 is an explanatory diagram for explaining another example of commands for realizing the RAMSET module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a TABLSET module. FIG. 7 is an explanatory diagram for explaining another example of commands for realizing the TABLSET module. 3 is a flowchart showing specific processing of the BYTEDEC module. FIG. 3 is an explanatory diagram for explaining a decrement mode and settings of a zero flag and a carry flag in the BYTEDEC module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a BYTEDEC module. FIG. 7 is an explanatory diagram for explaining another example of commands for implementing the BYTEDEC module. FIG. 2 is an explanatory diagram for explaining a RAM_DEC module. 3 is a flowchart showing specific processing of the WORDDEC module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a WORDDEC module. FIG. 7 is an explanatory diagram for explaining another example of commands for implementing the WORDDEC module. FIG. 3 is an explanatory diagram for explaining an example of a process of returning from a subroutine. FIG. 2 is an explanatory diagram for explaining a PY_CMDA module. It is an explanatory diagram for explaining a GAT_PAS module. It is an explanatory diagram for explaining a TDN_PAS module. FIG. 2 is an explanatory diagram for explaining an FD_OPN module. It is an explanatory diagram for explaining a TZ_STA module. It is an explanatory diagram for explaining a TZ_RGET module. It is an explanatory diagram for explaining a TRSVSEL module. FIG. 2 is an explanatory diagram for explaining a TDOVCHK module. It is an explanatory diagram for explaining a BER_CHK module. It is an explanatory diagram for explaining a TEF_SEL module. It is an explanatory diagram for explaining a SET_RIG module. It is an explanatory diagram for explaining a PRE_LOT module. It is an explanatory diagram for explaining a REG_LOT module. It is an explanatory diagram for explaining a BIG_SLT module. It is an explanatory diagram for explaining a NAV_SET module. 3 is a flowchart showing specific processing of the TOK_PRC module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing a TOK_PRC module. It is a flowchart showing specific processing of the TEF_SEL module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing a TEF_SEL module. 3 is a flowchart showing specific processing of the SWI_PRC module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing a SWI_PRC module. 3 is a flowchart showing specific processing of the CPUINIT module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a CPU INIT module. It is an explanatory diagram for explaining a TMR_IPT module. It is a flowchart showing specific processing of the FZ_SPN module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing the FZ_SPN module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a CPU INIT module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing an EXE_SET module. It is a flowchart showing specific processing of the HPT_GRP module. (a) and (b) are explanatory diagrams for explaining an example of a command for realizing the HPT_GRP module, and (c) is an explanatory diagram for explaining an example of a reach group determination random number determination table. be. It is an explanatory diagram for explaining an E_ILGER module. It is an explanatory diagram for explaining an E_LEVOT module. It is a flowchart showing specific processing of the SBC_OUT module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing an SBC_OUT module. FIG. 7 is an explanatory diagram for explaining an example of another command for realizing the SBC_OUT module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing the FZ_OPN module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing a TD_OPN module. FIG. 3 is an explanatory diagram for explaining an example of a command for implementing an HSY_PRC module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing an FDN_CHK module. FIG. 3 is an explanatory diagram for explaining an example of a command for implementing the FZ_STP module. FIG. 2 is a block diagram for explaining the configuration of a random number generator. FIG. 3 is a diagram illustrating a combination of random number generators. 3 is a flowchart showing specific processing of the SMC_ROT module. FIG. 3 is an explanatory diagram for explaining an example of commands for implementing the SMC_ROT module. FIG. 7 is an explanatory diagram for explaining another example of commands for implementing the SMC_ROT module. 3 is a flowchart showing specific processing of an INITIAL module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing an INITIAL module. FIG. 7 is an explanatory diagram for explaining another example of commands for realizing an INITIAL module. FIG. 2 is an explanatory diagram for explaining a RANKSET module. FIG. 2 is an explanatory diagram for explaining a PWRFAIL module. FIG. 2 is an explanatory diagram for explaining a DYM_OUT module. 12 is a flowchart showing specific processing of the IPT_PD module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing an IPT_PD module. FIG. 7 is an explanatory diagram for explaining another example of commands for implementing the IPT_PD module. FIG. 2 is an explanatory diagram for explaining a DYNMOUT module. It is an explanatory diagram for explaining an EXT_PRC module. 3 is a flowchart showing specific processing of the STOPDCT module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a STOPDCT module. FIG. 7 is an explanatory diagram for explaining another example of commands for implementing the STOPDCT module. It is a flowchart showing specific processing of the E_SETTM module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing an E_SETTM module. FIG. 7 is an explanatory diagram for explaining another example of commands for realizing the E_SETTM module. FIG. 2 is an explanatory diagram for explaining a DYM_OUT module. FIG. 2 is an explanatory diagram for explaining a DYM_OUT module. It is a flowchart showing specific processing of the E_SETTM module. FIG. 7 is an explanatory diagram for explaining still another example of commands for implementing the E_SETTM module. 3 is a flowchart showing specific processing of the RAM_INC module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a RAM_INC module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a RAM_INC module. FIG. 7 is an explanatory diagram for explaining another example of commands for implementing the RAM_INC module. FIG. 7 is an explanatory diagram for explaining another example of commands for implementing the RAM_INC module. 3 is a flowchart showing specific processing of the TABLSET module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a TABLSET module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing a TABLSET module. FIG. 7 is an explanatory diagram for explaining another example of commands for realizing the TABLSET module. 12 is a flowchart showing specific processing of the IPT_PC module. FIG. 2 is an explanatory diagram for explaining an example of a command for realizing an IPT_PC module. 3 is a flowchart showing specific processing of the CMDPROC module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing a CMDPROC module. It is a flowchart showing specific processing of the SET_PLS module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing a SET_PLS module. It is a flowchart showing specific processing of the OTM_ATK module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing an OTM_ATK module. FIG. 3 is an explanatory diagram for explaining an example of a command for realizing a KRS_JDG module. FIG. 7 is an explanatory diagram for explaining another example of commands for realizing the KRS_JDG module. 7 is a diagram showing an example of a command for setting a value in a Q' register. FIG. 7 is a diagram showing an example of a command for setting a value in a Q' register. FIG. 7 is a diagram showing an example of a command for setting a value in a Q' register. FIG. 7 is a diagram showing an example of a command for setting a value in a Q' register. FIG. FIG. 3 is a diagram for explaining transitions of register banks and register groups. FIG. 2 is an explanatory diagram for explaining how an access method is used. 3 is a flowchart for explaining an example of subcommand transmission processing. FIG. 7 is a diagram showing an example of a specific command for realizing subcommand transmission processing. FIG. 7 is a diagram showing an example of other commands for realizing subcommand transmission processing. FIG. 3 is a diagram showing part of a command group for implementing CPU initialization processing. FIG. 3 is a diagram showing a table referenced in CPU initialization processing. FIG. 7 is a diagram illustrating another example of a part of a command group for implementing CPU initialization processing. FIG. 7 is a diagram showing another example of a table referenced in CPU initialization processing. FIG. 7 is a diagram illustrating another example of a part of a command group for implementing CPU initialization processing. FIG. 2 is an explanatory diagram showing addresses of output ports. FIG. 7 is a diagram showing a part of a command group for realizing a power-off save process. FIG. 7 is a diagram illustrating another example of a part of a command group for realizing a power-off save process.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The dimensions, materials, and other specific numerical values shown in these embodiments are merely illustrative to facilitate understanding of the invention, and do not limit the invention unless otherwise specified. In this specification and the drawings, elements with substantially the same functions and configurations are given the same reference numerals to omit redundant explanation, and elements not directly related to the present invention are omitted from illustration. do.

In the embodiment of the present invention, a pachinko machine and a slot machine are illustrated in that order as gaming machines, and then specific processing will be explained in detail.

<Pachinko machine>
In order to facilitate understanding of the embodiments of the present invention, first, as a reference example of simultaneous rotation, the mechanical configuration and electrical configuration of a so-called simultaneous rotation machine, and specific processing on each board will be explained. Then, as a reference example of a performance, a specific performance that can be executed in the simultaneous spinning machine and a specific process related to the performance will be explained. Thereafter, configurations different from those of each reference example will be specifically explained as examples of the present invention.

<Simultaneous rotation reference example>
FIG. 1 is a perspective view of a gaming machine 100 according to a simultaneous rotation reference example, and shows a state in which the door is opened. As shown in the figure, the gaming machine 100 includes an outer frame 102 in which a surrounding space is formed by four sides arranged in a substantially rectangular shape, an inner frame 104 attached to the outer frame 102 so as to be openable and closable by a hinge mechanism, and The front frame 106 is attached to the middle frame 104 by a hinge mechanism so as to be openable and closable.

Similar to the outer frame 102, the inner frame 104 has a surrounding space formed by four sides arranged in a substantially rectangular shape, and a game board 108 is held in this surrounding space. Further, the front frame 106 holds a transparent plate 110 made of glass or resin. When the middle frame 104 and the front frame 106 are closed with respect to the outer frame 102, the game board 108 and the transparent plate 110 face each other substantially parallel to each other while maintaining a predetermined distance, and are viewed from the front side of the game machine 100. , the game board 108 becomes visible through the transparent plate 110.

FIG. 2 is a front view of the gaming machine 100 according to a reference example of simultaneous play. As shown in this figure, an operating handle 112 that protrudes toward the front side of the gaming machine 100 is provided at the lower part of the front frame 106. This operation handle 112 is provided so that the player can rotate it, and when the player rotates the operation handle 112 to perform a firing operation, the operation handle 112 has a strength corresponding to the rotation angle of the operation handle 112, and when the player performs a firing operation, the operation handle 112 has a strength corresponding to the rotation angle of the operation handle 112. A game ball is fired by the firing mechanism. The game ball launched in this manner ascends between the rails 114a and 114b provided on the game board 108 and is guided to the game area 116.

The game area 116 is a space formed between the game board 108 and the transparent plate 110, and is an area where the game balls can flow down or roll. The game board 108 is provided with a large number of nails and windmills (not shown), and the game ball guided into the game area 116 collides with the nails and windmills, causing it to flow down and roll in irregular directions. I have to.

The game area 116 includes a first game area 116a and a second game area 116b, in which the degree of entry of game balls is different depending on the firing strength of the firing mechanism, and game balls can be shot separately. The first gaming area 116a is located on the left side of the gaming area 116 when viewed from the player facing the gaming machine 100, and the second gaming area 116b is located on the left side of the gaming area 116 when viewed from the player facing the gaming machine 100. It is located on the right side. Since the rails 114a and 114b are on the left side of the game area 116, game balls fired by the firing mechanism with a firing strength lower than the predetermined strength enter the first game area 116a and are fired with a firing strength equal to or higher than the predetermined strength. The game ball that has been played enters the second game area 116b.

In addition, the gaming area 116 is provided with a general prize opening 118 into which game balls can enter, a first fixed starting opening 120A, a first variable starting opening 120B, a second starting opening 122, and a normal figure operating opening 125. , When a game ball enters these general prize opening 118, first fixed starting opening 120A, first variable starting opening 120B, second starting opening 122, and normal pattern operation opening 125, a predetermined prize ball is paid out to the player. It will be done. In addition, below, 120 A of 1st fixed starting ports and the 1st variable starting port 120B are named generically, and are called the 1st starting port 120.

As will be described in detail later, a first starting region is provided within the first starting port 120, and a second starting region is provided within the second starting port 122. Then, when the game ball enters the first starting port 120 or the second starting port 122 and enters the first starting area or the second starting area, one of the plurality of special symbols provided in advance is selected. A lottery is held to determine the No. 1 special symbol. Each special symbol is associated with whether or not a large winning game or a small winning game that is advantageous to the player can be executed. Therefore, when a game ball enters the first starting port 120 or the second starting port 122, the player not only obtains a predetermined prize ball but also has the opportunity to obtain the right to receive various gaming benefits. becomes.

Further, the first fixed starting port 120A, the second starting port 122, and the standard operating port 125 are constituted by fixed starting ports that are open to allow game balls to enter at all times. On the other hand, the first variable starting port 120B is provided with a movable piece 120b that can be opened and closed, and the ease with which the game ball enters the first variable starting port 120B changes depending on the state of the movable piece 120b. Consists of a variable starting port. Specifically, the movable piece 120b is normally maintained in a closed state, and during this time, it becomes difficult or impossible for the game ball to enter the first variable starting port 120B.

On the other hand, when a game ball passes through the gate 124 provided in the game area 116 (second game area 116b) or when a game ball enters the normal pattern operation opening 125, a lottery of normal symbols to be described later is performed. If a winner is won in this lottery, the movable piece 120b is controlled to be in the open state for a predetermined period of time. When the movable piece 120b is in the open state, a game ball can enter the first variable starting port 120B. In this way, the movable piece 120b has an open state that allows a game ball to enter the first variable starting port 120B, and an open state in which it is more difficult to enter the game ball into the first variable starting port 120B than in the open state. Otherwise, it functions as a movable member (variable start winning device) that transitions to the closed state, which is impossible.

Note that the first fixed starting port 120A allows only game balls flowing down the first gaming area 116a to enter, and the first variable starting port 120B and the second starting port 122 allow entry of game balls flowing down the second gaming area 116b. It is placed in a position where only the ball can enter. Note that a game ball flowing down the second game area 116b may enter the first fixed starting port 120A, but in this case, the game ball flowing down the first game area 116a is It is desirable to arrange the game area 116b at a position where it is easier for the ball to enter than the game ball flowing down.

Similarly, a game ball flowing down the first game area 116a may enter the first variable starting port 120B and the second starting port 122, but in this case, a game ball flowing down the second game area 116b may enter the first variable starting port 120B and the second variable starting port 122. It is desirable that the ball be placed in a position where it is easier for the ball to enter the first game area 116a than the game ball flowing down. In any case, the first fixed starting port 120A is arranged at a position where at least a game ball flowing down the first gaming area 116a can enter, and the first variable starting port 120B and the second starting port 122 are arranged at least in a position where a game ball flowing down the first gaming area 116a can enter. 2. It is preferable that the game ball flowing down the game area 116b be placed at a position where the ball can enter.

Furthermore, a first big winning hole 126 and a second big winning hole 128 are provided in the second gaming area 116b. The first big winning hole 126 and the second big winning hole 128 are arranged at positions where only game balls flowing down the second gaming area 116b can enter. However, the first big winning hole 126 and the second big winning hole 128 may be arranged so that any game balls flowing down the first gaming area 116a and the second gaming area 116b can enter.

The first big prize opening 126 is provided with an opening/closing door 126b that can be opened and closed. Normally, the opening/closing door 126b closes the first big winning opening 126 to prevent game balls from entering the first big winning opening 126. The ball has become impossible. Specifically, in the closed state, the opening/closing door 126b is flush with the board surface of the game board 108, and the game ball flows down in front of the first big prize opening 126. On the other hand, when the above-mentioned big prize game is executed, the opening/closing door 126b is opened and functions as a tray that guides the game ball to the first big winning hole 126, and the game ball enters the first big winning hole 126. The ball becomes possible. Then, when a game ball enters the first big prize opening 126, a predetermined prize ball is paid out to the player.

The second big winning hole 128 is provided below the first big winning hole 126 in the second gaming area 116b. The second big prize opening 128 includes a movable piece 128b, and the movable piece 128b is normally maintained in a closed state. On the other hand, when a small winning game to be described later is executed, the movable piece 128b is controlled to be in an open state, and the game ball can enter the second big prize opening 128. In addition, below, the 1st big winning hole 126 and the 2nd big winning hole 128 are collectively simply called a big winning hole.

FIG. 3 is a diagram illustrating the second grand prize opening 128 according to a simultaneous spinning reference example. A structure 129 that protrudes toward the front side of the game board 108 is provided in the second game area 116b. This structure 129 is surrounded by the four sides located in the left-right direction and the front-back direction of the gaming machine 100, as well as the bottom, and has an opening formed in the upper part. The opening formed in the upper part of this structure 129 becomes the second big prize opening 128. A movable piece 128b is provided at the top of the structure 129, and normally, as shown in FIG. .

The movable piece 128b faces above the gaming machine 100 and protrudes into the gaming area 116 where the gaming ball rolls and flows down. Therefore, when the movable piece 128b is maintained in the closed state, the game ball flowing down the game area 116 (second game area 116b) will fall onto the movable piece 128b. Here, the base of the structure 129 is substantially parallel to the horizontal direction, and the right side of the gaming machine 100 is slightly longer in the height direction than the left side. Therefore, the second big prize opening 128 is positioned so that the left side of the gaming machine 100 is slightly lower than the right side, and the movable piece 128b maintained in the closed state is positioned so that the left side of the gaming machine 100 is slightly lower than the right side. is inclined to. Therefore, when the movable piece 128b is in the closed state, the game ball that has fallen onto the movable piece 128b slowly rolls from the right to the left on the movable piece 128b, as shown by the arrow in FIG. 3(a). It will move.

Then, when a small winning game to be described later is executed, the movable piece 128b shifts to the open state in which the second big prize opening 128 is opened. Here, the movable piece 128b changes from the closed state to the open state by sliding toward the back side of the game board 108, as shown in FIG. 3(b). As a result, when changing from the closed state to the open state, the game ball rolling on the movable piece 128b falls into the second grand prize opening 128 under its own weight.

In this manner, in the simultaneous rotation reference example, the movable piece 128b is slightly inclined to ensure a long time for the game ball to roll on the movable piece 128b. Then, when the movable piece 128b changes from the closed state to the open state, the game ball rolling on the movable piece 128b is guided into the second grand prize opening 128. With the above configuration, even if the time for maintaining the movable piece 128b in the open state is set slightly, a predetermined number of game balls can be guided into the second big prize opening 128. In other words, the time required to maintain the movable piece 128b in the open state, which is necessary to allow a predetermined number of game balls to enter the second big prize opening 128, can be shortened. Note that a hole communicating with the back side of the game board 108 is formed on the back side of the structure 129, and the game ball that enters the second grand prize opening 128 is discharged to the back side of the game board 108. . Then, when a game ball enters the second big prize opening 128, a predetermined prize ball is paid out to the player.

In addition, although the structure of the 2nd big winning a prize opening 128 was demonstrated here, the 1st variable starting opening 120B is also the same structure as the 2nd big winning a prize opening 128. That is, the movable piece 120b of the first variable starting port 120B protrudes to the front side of the game board 108 in the closed state, and the game ball rolls on the movable piece 120b. In the open state of the movable piece 120b, the movable piece 120b slides toward the back side of the game board 108, allowing the game ball to enter the first variable starting port 120B. However, as shown in FIG. 2, the right side of the movable piece 128b is higher than the left side when the gaming machine 100 is viewed from the front, whereas the left side of the movable piece 120b is on the right side when the gaming machine 100 is viewed from the front. located higher than.

Here, the board structure of the second game area 116b will be described in detail. In the simultaneous rotation reference example, the second starting port 122 and the gate 124 are arranged in parallel at the top of the second game area 116b. All the game balls guided to the second game area 116b either enter the second starting port 122 or pass through the gate 124 and flow downward. In the simultaneous rotation reference example, the second starting port 122 pays out one game ball as a prize ball for each game ball that enters.

When a game ball enters the second starting port 122, one game ball is paid out as a prize ball, and a lottery is held to determine whether or not to execute a big winning game or a small winning game. Further, when the game ball passes through the gate 124, a lottery is held to determine whether or not the first variable starting port 120B (movable piece 120b) is to be opened.

Directly below the second starting opening 122 and the gate 124, a first big winning opening 126 is provided. When the first big prize opening 126 is in the open state, all of the game balls that have passed through the gate 124 and flowed down are arranged so as to enter the first big prize opening 126. In the simultaneous spinning reference example, the first big prize opening 126 is opened only in the big prize game. In other words, the first big winning hole 126 can be said to be a big winning hole exclusively for big prize games. When a game ball enters the first big prize opening 126 during a big prize game, a predetermined number of two or more (15 in this case) game balls are paid out as prize balls for each game ball that enters. .

A first variable starting opening 120B is provided below the first big winning opening 126. In addition, an out port 131 is provided between the first big winning port 126 and the first variable starting port 120B. The out port 131 is the entrance of a passage for discharging game balls from the gaming area 116, and even if a game ball enters the out port 131, no prize ball is paid out.

Nails are arranged in the second game area 116b so that most (for example, 90% or more) of the game balls that have flowed down from the first big prize opening 126 fall onto the movable piece 120b. In addition, a part (for example, 1% to 10%) of the game balls that have flowed downward from the first big prize opening 126 are guided to the out opening 131 by these nails.

When the first variable starting port 120B is in the closed state, the game ball rolls on the movable piece 120b. When the movable piece 120b is opened while the game balls are rolling on the movable piece 120b, all the game balls on the movable piece 120b are guided into the first variable starting port 120B. When a game ball enters the first variable starting port 120B, one game ball is paid out as a prize ball for each game ball that enters, and it is also determined whether or not to execute a big prize game or a small winning game. A lottery will be held.

Game balls that have not entered the first variable starting port 120B fall from above the movable piece 120b to the right side of the gaming machine 100 when viewed from the front. A second big winning opening 128 is provided below the first variable starting opening 120B, and most of the game balls that fall from above the movable piece 120b roll on the movable piece 128b of the second big winning opening 128. do. The game ball on the movable piece 128b slowly rolls from the right side to the left side when the gaming machine 100 is viewed from the front due to the inclination of the movable piece 128b.

Although details will be described later, in the simultaneous spin reference example, the second large prize opening 128 is opened only in the small winning game. In other words, the second big winning hole 128 can be said to be a big winning hole exclusively for small winning games. When the movable piece 128b is opened while the game balls are rolling on the movable piece 128b, all the game balls on the movable piece 128b are guided into the second big prize opening 128. When a game ball enters the second large prize opening 128 during a small winning game, a predetermined number of two or more (15 in this case) game balls are paid out as prize balls for each game ball that enters. It will be done.

A normal figure operation opening 125 is provided at the lower left of the second big prize opening 128. Here, nails are arranged in the second game area 116b so that almost all of the game balls that fall downward from above the second big prize opening 128 enter the normal pattern operation opening 125. In the simultaneous rotation reference example, the common figure operation opening 125 constitutes a "specific winning opening" in which one game ball is paid out as a prize ball for each game ball that enters. Furthermore, when a game ball enters the normal pattern operating port 125, it is determined whether or not to open the first variable starting port 120B (movable piece 120b), similarly to when the game ball passes through the gate 124. A lottery will be held.

In addition, at the bottom of the gaming area 116, there are game balls that did not enter any of the general prize opening 118, first starting opening 120, second starting opening 122, normal figure operation opening 125, and big winning opening. A discharge port 130 is provided for discharging the water from the game area 116 to the back side of the game board 108.

The gaming machine 100 includes an effect display device 200 consisting of a liquid crystal display device, an effect accessory device 202 consisting of a movable device, and an effect display device 200 that performs effects while the game is in progress, etc., and an effect display device 202 consisting of a movable device, which is controlled in various lighting modes and emitting colors. A production lighting device 204 consisting of a lamp, an audio output device 206 consisting of a speaker, and a production operation device 208 that receives operations from a player are provided.

The effect display device 200 includes a main effect display section 200a consisting of an image display section that displays an image, and this main effect display section 200a is visible from the front side of the gaming machine 100 at approximately the center of the game board 108. It is arranged as possible. Various effects will be executed on this main effect display section 200a, such as three effect symbols 210a, 210b, and 210c being displayed in a variable manner as shown in the figure.

The performance accessory device 202 is placed in front of the main performance display section 200a, and is usually retracted in a state where it is divided into a plurality of components at the origin position on the back side of the game board 108, so that the player can It is no longer visible. Then, when each component moves to a movable position in front of the main effect display section 200a by driving the actuator while the above-mentioned effect symbols 210a, 210b, 210c are being displayed in a variable manner, the front surface of the main effect display section 200a Each component unites to give the player a feeling of anticipation of a jackpot.

The effect lighting device 204 is provided in the effect accessory device 202, the game board 108, etc., and is controlled to be lit in various ways according to the image etc. displayed on the main effect display section 200a.

The audio output device 206 is provided at the upper position of the front frame 106 or the lowermost position of the outer frame 102, and outputs various sounds toward the front side of the gaming machine 100 in accordance with the image displayed on the main effect display section 200a. Output audio.

The production operation device 208 is composed of a button that accepts a pressing operation by a player, and is provided at a substantially central position in the width direction of the gaming machine 100 and at a position below the transparent plate 110. This effect operation device 208 is activated according to the image displayed on the main effect display section 200a, and when it receives an operation from the player within the operation effective time, various operations are performed according to the operation. The performance is executed.

In addition, the reference numeral 132 in the figure is an upper tray into which the prize balls paid out from the gaming machine 100 and the game balls lent out from the game ball rental device are guided, and when the upper tray 132 is full of game balls, the game balls are It will be guided to the lower tray 134. Further, a ball removal hole (not shown) for ejecting game balls from the lower tray 134 is formed in the bottom surface of the lower tray 134. This ball removal hole is normally closed by an opening/closing plate (not shown), but by pressing down the ball removal knob 134a, the opening/closing plate slides together with the ball removal knob 134a, and the ball removal hole is closed. It is possible to discharge game balls from below the lower tray 134.

In addition, on the game board 108, a first special symbol display 160, a second special symbol display 162, and a first special symbol reserved are located outside the gaming area 116 and in a position that is visible to the player. A display 164, a second special symbol reservation display 166, a normal symbol display 168, a regular symbol reservation display 170, and a right hit notification display 172 are provided. Each of these displays 160 to 172 is a device for displaying various situations related to the game, and details thereof will be described later.

(Internal configuration of control means)
FIG. 4 is a block diagram showing the internal configuration of a control means for controlling the progress of a game according to a simultaneous play reference example.

The main control board 300 controls the basic operations of the game. This main control board 300 includes a main CPU 300a, a main ROM 300b, and a main RAM 300c. The main CPU 300a reads the program stored in the main ROM 300b and performs arithmetic processing based on input signals from each detection switch and timer, and also directly controls each device and display, or uses the results of the arithmetic processing. Send commands to other boards accordingly. The main RAM 300c functions as a data work area during arithmetic processing by the main CPU 300a.

The main control board 300 includes a general winning hole detection switch 118s that detects that a game ball has entered the general winning hole 118, and a first fixed start port that detects that a game ball has entered the first fixed starting port 120A. A starting port detection switch 120As, a first variable starting port detection switch 120Bs that detects that a game ball has entered the first variable starting port 120B, and a second variable starting port detection switch 120Bs that detects that a game ball has entered the second starting port 122. A starting port detection switch 122s, a gate detection switch 124s that detects that a game ball has passed through the gate 124, a normal pattern operation port detection switch 125s that detects that a game ball has entered the normal pattern operation port 125, and a first large A first big winning hole detection switch 126s that detects that a game ball has entered the winning hole 126, and a second big winning hole detection switch 128s that detects that a game ball has entered the second big winning hole 128 are connected. Detection signals are input to the main control board 300 from each of these detection switches.

In addition, the main control board 300 includes a normal electric accessory solenoid 120c that operates the movable piece 120b of the first variable starting opening 120B, and a first big prize opening that operates the opening/closing door 126b that opens and closes the first big prize opening 126. The solenoid 126c and the second large winning opening solenoid 128c that operates the movable piece 128b that opens and closes the second large winning opening 128 are connected, and the main control board 300 controls the first variable starting opening 120B and the first large winning opening. The opening and closing of the winning opening 126 and the second big winning opening 128 is controlled.

Furthermore, the main control board 300 includes a first special symbol display 160, a second special symbol display 162, a first special symbol reservation display 164, a second special symbol reservation display 166, a normal symbol display 168, and a normal symbol display 168. A symbol holding display 170 and a right hit notification display 172 are connected, and the main control board 300 controls the display of each of these displays.

Furthermore, a setting change switch 180s is provided on the back side of the game board 108. The setting change switch 180s is configured to be accessible by a dedicated key. On the condition that the setting change switch 180s is turned on, it is possible to change and confirm the setting value. Although details will be described later, in the gaming machine 100 of the simultaneous playback reference example, any of the six levels of setting values with different degrees of advantage is stored as a registered setting value in the setting value buffer, and the game machine 100 is set according to the stored registered setting value. The game progresses. Here, it is assumed that the setting value is in six stages, but the setting value may be provided in only two stages, high setting and low setting, or may be provided in other plural stages. Furthermore, the set value is not essential, and the degree of advantage does not need to be changed.

Further, a RAM clear button is provided on the back side of the game board 108 so that it can be pressed down, and the pressing operation of this RAM clear button is detected by the RAM clear switch 182s. The RAM clear switch 182s is connected to the main control board 300, and a RAM clear operation signal is input to the main control board 300 from the RAM clear switch 182s. If a RAM clear operation signal is input from the RAM clear switch 182s when the power is turned on, the main CPU 300a clears the main RAM 300c.

Furthermore, a performance display monitor 184 is provided on the back side of the game board 108. The main control board 300 displays registered setting values and base ratios on the performance display monitor 184.

In addition, the game machine 100 of the simultaneous play reference example mainly plays a special game that is started by the entry of the game ball into the first starting port 120 or the second starting port 122, and the passing of the game ball into the gate 124, or , and a normal game that is started by the entry of a game ball into the normal pattern operating port 125. The main ROM 300b of the main control board 300 stores various programs for playing special games and normal games, as well as data and tables necessary for various games.

Further, a payout control board 310 and a sub-control board 330 are connected to the main control board 300. The payout control board 310 performs control for shooting game balls and control for paying out prize balls. This payout control board 310 also includes a CPU, ROM, and RAM, and is connected to the main control board 300 so as to be able to communicate in both directions. A game information output terminal board 312 is connected to this payout control board 310, and various information regarding game progress outputted from the main control board 300 is transmitted via the payout control board 310 and the game information output terminal board 312. , and will be output to the hall computer of the game parlor.

Further, a payout motor 314 is connected to the payout control board 310 for paying out the game balls stored in the storage section as prize balls to the player. The payout control board 310 controls the payout motor 314 based on the payout number designation command transmitted from the main control board 300 to pay out predetermined prize balls to the player. At this time, the number of game balls that have been paid out is detected by the paid-out ball counting switch 316s, so that it can be ascertained whether the prize balls that should be paid out have been paid out to the player.

Further, a tray full detection switch 318s that detects the full state of the lower tray 134 is connected to the payout control board 310. This tray full detection switch 318s is provided in a passage that guides game balls paid out as prize balls to the lower tray 134, and a game ball detection signal is input to the payout control board 310.

When a predetermined amount or more of game balls are stored in the lower tray 134 and the game ball becomes full, the game balls stay in the passage toward the lower tray 134 and are sent from the tray full detection switch 318s toward the payout control board 310. , game ball detection signals are continuously input. When the game ball detection signal is continuously input for a predetermined period of time, the payout control board 310 determines that the lower tray 134 is full, and sends a full tray command to the main control board 300. On the other hand, if the continuous input of the game ball detection signal is interrupted after transmitting the full plate command, it is determined that the full state has been canceled, and a full plate release command is sent to the main control board 300.

Further, the payout control board 310 is provided with a launch control circuit 320 that controls the launch of game balls. A touch sensor 112s that is provided on the operating handle 112 and detects that the player has touched the operating handle 112, and an operating volume 112a that detects the operating angle of the operating handle 112 are connected to the payout control board 310. ing. Then, when a signal is input from the touch sensor 112s and the operation volume 112a, the firing control circuit 320 controls to energize the firing solenoid 112c provided in the game ball firing device to fire the game ball.

The sub-control board 330 mainly controls various effects such as during gaming and on standby. The sub-control board 330 includes a sub-CPU 330a, a sub-ROM 330b, and a sub-RAM 330c, and is connected to the main control board 300 so as to be able to communicate in one direction from the main control board 300 to the sub-control board 330. . The sub CPU 330a reads out the program stored in the sub ROM 330b based on commands transmitted from the main control board 300, input signals from the timer, etc., performs arithmetic processing, and controls execution of effects. At this time, the sub-RAM 330c functions as a data work area during arithmetic processing by the sub-CPU 330a.

Specifically, in the sub-control board 330, the sub-CPU 330a, sub-ROM 330b, and sub-RAM 330c work together to function as a sub-main, an image control section, an accessory control section, a lighting control section, and an audio control section. The sub-main determines the content of the performance to be executed in response to various input commands, and manages and supervises the execution of the performance. The image control section performs image display control to display an image on the main effect display section 200a. The sub ROM 330b stores a large amount of image data such as symbols, backgrounds, and subtitles to be displayed on the main performance display section 200a, and the image control section reads out the image data from the sub ROM 330b to a VRAM (not shown) and Controls image display on the effect display section 200a.

Further, the accessory control unit drives the actuator in accordance with the performance management by the sub-main, and controls the movement of the performance accessory device 202. The lighting control unit controls lighting of the performance lighting device 204. The audio control unit also performs audio output control to cause the audio output device 206 to output audio. The sub ROM 330b stores a large amount of audio data such as voices and songs output from the audio output device 206, and the audio control unit reads out the audio data from the sub ROM 330b and controls the audio output of the audio output device 206. do.

Furthermore, the sub-control board 330 executes a predetermined effect when an operation detection signal is input from the effect operation device detection switch 208s that detects that the effect operation device 208 is pressed or rotated.

Note that a power supply board (not shown) is connected to each board, and power is supplied to each board from a commercial power source via the power supply board. Further, the power supply board is provided with a backup power supply consisting of a capacitor.

FIG. 5 is an address map of the memory area used by the main CPU 300a according to the simultaneous operation reference example. Note that in FIG. 5, addresses are shown in hexadecimal numbers, and "H" indicates that they are hexadecimal numbers. As shown in FIG. 5, the memory area used by the main CPU 300a includes a memory area (0000H to 2FFFH) allocated to the main ROM 300b and a memory area (F000H to F3FFH) allocated to the main RAM 300c.

The memory area of the main ROM 300b includes a used area (0000H to 1BF3H) for storing programs and data for controlling the progress of the game, and an area other than the used area for processing for performing tests stipulated by gaming machine regulations. and an unused area (2000H to 2BFFH) for storing programs and data for executing processing for displaying the performance display monitor 184 (including processing for calculating the base ratio to be displayed on the performance display monitor 184). and is provided.

The used areas of the main ROM 300b include a program area (0000H to 0A89H) where programs for controlling the progress of the game are stored, an unused area (0A8AH to 11FFH), and a data area (1200H) where data other than programs are stored. ~1BF3H) are provided. Note that the used area may not include unused areas (0A8AH to 0FFFH).

The unused area of the main ROM 300b includes a program area (2000H to 27FFH) in which programs for executing tests specified by gaming machine regulations and programs for displaying the performance display monitor 184 are stored; A data area (2800H to 2BFFH) is provided in which data other than these programs is stored.

In addition to the used and unused areas, the memory area of the main ROM 300b also includes an unused area (1A7BH to 1DFFH) and a ROM comment area (1E00H to 1EFFH) where arbitrary data such as program titles and versions are stored. ), an unused area (1F00H to 1FFFH), an unused area (2C00H to 2FBFH), and a program management area (2FC0H to 2FFFH) in which information necessary for the main CPU 300a to execute a program is stored.

The memory area of the main RAM 300c consists of a used area (F000H to F1FFH) that is used temporarily when a program for controlling the progress of the game is being executed, and an area other than the used area, which is specified by gaming machine regulations. An unused area (F210H to F228H) is provided that is used temporarily when a program for performing a specified test or for displaying the performance display monitor 184 is executed.

The used areas of the main RAM 300c include a work area (F000H to F12AH) used temporarily when a program for controlling the progress of the game is being executed, an unused area (F12BH to F1D7H), and a work area (F12BH to F1D7H) used to control the progress of the game. A stack area (F1D8H to F1FFH) is provided for temporarily saving data during execution of a control program. Note that the used area may not include unused areas (F12BH to F1D7H).

The unused area of the main RAM 300c has a work area (F210H -F21FH), and a stack area (F220H to F228H) for temporarily saving data while these programs are being executed.

Furthermore, in addition to the used area and the unused area, the memory area of the main RAM 300c includes an unused area (F200H to F20FH) and an unused area (F229H to F3FFH).

In this way, the main ROM 300b and the main RAM 300c have areas used for controlling the progress of the game, processing for conducting tests specified by gaming machine regulations, and processing for controlling the display of the performance display monitor 184. An unused area used for executing the process is provided separately.

In the main RAM 300c, a 16-byte unused area (F200H to F20FH) is provided between the used area and the unused area. This unused area (F200H to F20FH) is set as a boundary area that separates the used area and the unused area, and the boundary between the used area and the unused area is clear, and the program for controlling the progress of the game is When the program is executed, an unused area is used, and when the program is executed for the process to perform the test specified by the gaming machine regulations or the process to control the display of the performance display monitor 184. Prevents the used area from being used.

Note that the unused area provided between the used area and the unused area should be at least 1 byte or more, and from the perspective of fraud prevention, it is preferably 4 bytes or more, and it is set to 16 bytes or more. It is more desirable. Although data writing and reading are prohibited in the unused area, it may be cleared at a predetermined timing to prevent fraud.

Furthermore, an input/output section is allocated to the memory space from FE00h to FFFFh. The input/output section will be described in detail later.

Next, a game in the gaming machine 100 as a reference example of simultaneous play will be explained together with various tables stored in the main ROM 300b.

As described above, in the gaming machine 100 of the simultaneous play reference example, two types of games, a special game and a normal game, are played in parallel. In the special game, the game progresses in either the low probability game state or the high probability game state, and in the normal game, the game progresses in the game state of the non-time saving game state, the medium time saving game state, or the time saving game state. The game progresses.

The details of each gaming state will be described later, but a low probability gaming state is a gaming state in which the probability of acquiring the right to execute a big prize game that opens a big prize opening is set low, and a high probability gaming state This is a gaming state in which the probability of acquiring the right to execute a big prize game is set high. In addition, the non-time-saving gaming state is a gaming state in which the movable piece 120b is difficult to open and the game ball is difficult to enter the first variable starting port 120B, and the medium-time-saving gaming state is a non-time-saving gaming state. This is a game state in which the movable piece 120b is more likely to be in the open state than in the state, and the game ball is more likely to enter the first variable starting port 120B. In addition, the time-saving game state is a game state in which the movable piece 120b is more likely to be in the open state than the medium-time-saving game state, and the game ball is most likely to enter the first variable starting opening 120B. In addition, in the time-saving game state, when the game balls continue to be fired toward the second game area 116b during the game, the game balls are set so that the number of game balls decreases slightly or the number of game balls does not decrease at all. .

As mentioned above, the special game and the normal game proceed simultaneously, so in the simultaneous play reference example, the low probability game state or high probability game state, the non-time saving game state, the medium time saving game state, the time saving game A gaming state is a combination of any of the states. Below, for ease of understanding, the gaming states related to special games, that is, the low probability gaming states and the high probability gaming states, will be referred to as special gaming states, and the gaming states related to normal games, that is, non-time saving gaming states, medium The time-saving gaming state and the time-saving gaming state are sometimes called the normal gaming state. The initial state of the gaming machine 100 is set to a low probability gaming state and a non-time saving gaming state.

When the player operates the operation handle 112 to launch a game ball into the game area 116, and when the game ball flowing down the game area 116 enters the first starting port 120 or the second starting port 122, the player is prompted to play the game. A lottery is held to determine whether or not to award a profit (hereinafter referred to as a "major lottery"). In this big winning lottery, if you win a jackpot, the big winning opening will be opened and a big winning game will be executed in which you can enter the game ball into the big winning opening, and the game state after the big winning game is over. is set to one of the gaming states listed above. Below, the major prize lottery method will be explained.

Although details will be described later, when a game ball enters the first starting port 120 or the second starting port 122, various random numbers related to the big prize lottery (jackpot determining random number, winning symbol random number, reach group determining random number, reach A mode determination random number, a fluctuation pattern random number) are acquired, and each of these random numbers is stored in the special figure reservation storage area of the main RAM 300c. Hereinafter, various random numbers stored in the special figure holding storage area when a game ball enters the first starting port 120 will be collectively referred to as special 1 holding, and when a game ball enters the second starting port 122 The various random numbers stored in the special figure reservation storage area are collectively called special 2 reservation.

The special figure reservation storage area of the main RAM 300c includes a first special figure reservation storage area and a second special figure reservation storage area. The first special figure reservation storage area and the second special figure reservation storage area each have four storage units (first to fourth storage units). When a game ball enters the first starting port 120, the special 1 reservation is stored in order from the first storage part of the first special symbol reservation storage area, and when a game ball enters the second starting port 122, the special 2 reservations are stored in order from the first storage part of the second special figure reservation storage area.

For example, when a game ball enters the first starting port 120, if no reservation is stored in any of the first to fourth storage sections of the first special symbol reservation storage area, the first storage section Memorize special 1 reservation. Further, for example, if a game ball enters the first starting port 120 with the special 1 hold stored in the first to third storage units, the special 1 hold is stored in the fourth storage unit. Remember. Also, when a game ball enters the second starting port 122, the special 2 reservation is stored in the first to fourth storage sections of the second special symbol reservation storage area in the same manner as described above. The special 2 hold is stored in the storage unit with the smallest number (ordinal number) that is not listed.

However, the number of special 1 reservations (X1) and the number of special 2 reservations (X2) that can be stored in the first special symbol reservation storage area and the second special symbol reservation storage area are each set to four. Therefore, for example, when a game ball enters the first starting port 120, if four special 1 reservations are already stored in the first special symbol reservation storage area, the game ball enters the first starting port 120. Special 1 pending is not newly memorized due to the entry of the game ball. Similarly, when a game ball enters the second starting port 122, if four special 2 reservations are already stored in the second special figure reservation storage area, the game to the second starting port 122 is Special 2 suspension will not be newly memorized due to the ball entering the ball.

FIG. 6 is a diagram illustrating a low probability jackpot determination random number determination table according to a simultaneous play reference example. When a game ball enters the first starting port 120 or the second starting port 122, one jackpot determination random number is obtained from within the range of 0 to 65535. Then, when starting the big prize lottery, that is, when determining a jackpot, a jackpot determination random number determination table is selected according to the gaming state, and based on the selected jackpot determination random number determination table and the acquired jackpot determination random number. A major lottery will be held.

In the low-probability game state, when starting the big winning lottery for special 1 pending and special 2 pending, the low probability jackpot determination random number determination table is referred to. Here, in the simultaneous rotation reference example, there are six levels of setting values with different degrees of advantage, and a low probability jackpot determination random number determination table is provided for each setting value. During the game, the setting value is set to one of six levels, and the random number judgment for determining a jackpot when the probability is low corresponds to the currently set setting value (registered setting value stored in the setting value buffer). A lottery is held with reference to the table.

In the low probability gaming state, when the setting value is set to 1 (registered setting value = 1), the large winning lottery is performed with reference to the low probability jackpot determination random number determination table a shown in FIG. 6(a). will be held. According to this low probability jackpot determination random number determination table a, when the jackpot determination random number is between 10001 and 10218, it is determined to be a jackpot, when the jackpot determination random number is between 20001 and 38996, it is determined to be a small hit, and other If it is a jackpot determination random number, it is determined that it is a loss. Therefore, the jackpot probability in this case is about 1/300.6, and the small win probability is about 1/3.45.

In the low probability gaming state, when the setting value is set to 2 (registered setting value = 2), the large winning lottery is performed with reference to the low probability jackpot determination random number determination table b shown in FIG. 6(b). will be held. According to this low-probability jackpot decision random number determination table b, when the jackpot decision random number is between 10001 and 10225, it is determined to be a jackpot, when the jackpot decision random number is between 20001 and 38996, it is determined as a small hit, and other If it is a jackpot determination random number, it is determined that it is a loss. Therefore, the jackpot probability in this case is about 1/291.2, and the small win probability is about 1/3.45.

In the low probability gaming state, when the setting value is set to 3 (registered setting value = 3), the large winning lottery is performed with reference to the low probability jackpot determination random number determination table c shown in FIG. 6(c). will be held. According to this low-probability jackpot determination random number determination table c, when the jackpot determination random number is between 10001 and 10232, it is determined to be a jackpot, when the jackpot determination random number is between 20001 and 38996, it is determined to be a small hit, and other If it is a jackpot determination random number, it is determined that it is a loss. Therefore, the jackpot probability in this case is about 1/282.4, and the small win probability is about 1/3.45.

In the low probability gaming state, when the setting value is set to 4 (registered setting value = 4), the large winning lottery is performed with reference to the low probability jackpot determination random number determination table d shown in FIG. 6(d). will be held. According to this low-probability jackpot determination random number determination table d, when the jackpot determination random number is between 10001 and 10239, it is determined to be a jackpot, when the jackpot determination random number is between 20001 and 38996, it is determined to be a small hit, and other If it is a jackpot determination random number, it is determined that it is a loss. Therefore, the jackpot probability in this case is about 1/274.2, and the small win probability is about 1/3.45.

In the low probability gaming state, when the setting value is set to 5 (registered setting value = 5), the large winning lottery is performed with reference to the low probability jackpot determination random number determination table e shown in FIG. 6(e). will be held. According to this low-probability jackpot decision random number determination table e, when the jackpot decision random number is between 10001 and 10246, it is determined to be a jackpot, when the jackpot decision random number is between 20001 and 38996, it is determined as a small hit, and other If it is a jackpot determination random number, it is determined that it is a loss. Therefore, the jackpot probability in this case is about 1/266.4, and the small win probability is about 1/3.45.

In the low probability gaming state, when the setting value is set to 6 (registered setting value = 6), the large winning lottery is performed with reference to the low probability jackpot determination random number determination table f shown in FIG. 6(f). will be held. According to this low-probability jackpot decision random number determination table f, when the jackpot decision random number is between 10001 and 10253, it is determined to be a jackpot, when the jackpot decision random number is between 20001 and 38996, it is determined as a small hit, and other If it is a jackpot determination random number, it is determined that it is a loss. Therefore, the jackpot probability in this case is about 1/259.0, and the small win probability is about 1/3.45.

FIG. 7 is a diagram illustrating a random number determination table for determining a jackpot at high probability according to a reference example of simultaneous play. In the high-probability gaming state, when starting the big winning lottery for special 1 pending and special 2 pending, the high probability jackpot determination random number determination table is referred to. The high probability jackpot determination random number determination table is also provided for each set value, similar to the low probability jackpot determination random number determination table.

In the high probability gaming state, when the setting value is set to 1 (registered setting value = 1), the large winning lottery is performed with reference to the high probability jackpot determination random number determination table a shown in FIG. 7(a). will be held. According to this high probability jackpot determination random number determination table a, when the jackpot determination random number is between 10001 and 10620, it is determined that it is a jackpot, when the jackpot determination random number is between 20001 and 38996, it is determined that it is a small hit, and other If it is a jackpot determination random number, it is determined that it is a loss. Therefore, the jackpot probability in this case is about 1/105.7, and the small win probability is about 1/3.45.

Similarly, in the high probability gaming state, when the setting value is set to 2 to 6 (registered setting value = 2 to 6), the high probability jackpot shown in Fig. 7(b) to (f) A major prize lottery is performed with reference to the determined random number determination tables b to f. According to these high-probability jackpot determination random number determination tables b to f, a jackpot is determined when the respective jackpot determination random numbers are the values shown. Therefore, when the setting value is 2 to 6, the jackpot probability is about 1/102.4 to 1/91.0, and the small win probability is about 1/3.45.

As described above, the major prize lottery is performed according to the registered setting values. At this time, the probability of winning the jackpot differs depending on the registered setting value, and it is easier to win the jackpot when the registered setting value is large than when it is small. Note that here, even if the registered setting values are different, the probability of winning a small hit does not change, but the probability of winning a small winning may be changed for each registered setting value. Moreover, a small win is not essential, and only either a jackpot or a loss may be determined in the large prize lottery.

In addition, here, the probability of winning a jackpot in both the low-probability gaming state and the high-probability gaming state is different depending on the registered setting value, but the probability of winning a jackpot in either the low-probability gaming state or the high-probability gaming state is Only the probability of winning may differ depending on the registered setting value.

FIG. 8 is a diagram illustrating a winning symbol random number determination table and a small winning symbol random number determination table according to a simultaneous rotation reference example. When a game ball enters the first starting port 120 or the second starting port 122, one winning symbol random number is obtained from within the range of 0 to 99. Then, when a determination result of "big hit" is derived from the above-mentioned big winning lottery, the type of special symbol is determined based on the acquired winning symbol random number and the winning symbol random number determination table. At this time, if you win a "jackpot" by holding special 1, as shown in Figure 8 (a), the winning symbol random number determination table a for special 1 is selected, and if you win a "jackpot" by holding special 2 In this case, as shown in FIG. 8(b), the winning symbol random number determination table b for special 2 is selected, and if a "small win" is won by holding special 1, as shown in FIG. 8(c). , when the special 1 small winning symbol random number determination table a is selected and the "small hit" is won by holding the special 2, as shown in FIG. 8(d), the special 2 small winning symbol random number determination table a is selected. b is selected. Below, the special symbol determined by the winning symbol random number, that is, the special symbol determined when a jackpot determination result is obtained, is called a jackpot symbol, and the special symbol is determined when a small hit determination result is obtained. A special symbol is called a small hit symbol, and a special symbol determined when a loss determination result is obtained is called a loss symbol.

According to the special 1 winning symbol random number determination table a shown in FIG. 8(a) and the special 2 winning symbol random number determination table b shown in FIG. 8(b), depending on the value of the acquired winning symbol random number, As shown in the figure, jackpot symbols (special symbols A to J) are determined as special symbols. In addition, according to the special 1 small winning symbol random number determination table a shown in FIG. 8(c) and the special 2 small winning symbol random number determination table b shown in FIG. 8(d), the value of the acquired winning symbol random number Accordingly, as shown in the figure, small winning symbols (special symbols Z1 to Z6) are determined as special symbols.

In addition, when the big winning lottery result is a "loss" and the lottery result is derived by special 1 reservation, special symbol X is determined as a losing symbol without performing a lottery, and the lottery result is special 2 When the special symbol Y is derived by holding, the special symbol Y is determined as a losing symbol without performing a lottery. In other words, the winning symbol random number determination table is referred to only when the major prize lottery result is a "big hit", and is not referred to when the major prize lottery result is a "loss" or a "small win". Further, the small winning symbol random number determination table is referred to only when the large winning lottery result is a "small winning", and is not referred to when the large winning lottery result is a "big winning" or "loss". In addition, special symbols Z1 to Z6, which are small winning symbols, are collectively referred to simply as special symbol Z.

FIG. 9 is a diagram illustrating a reach group determination random number determination table according to a simultaneous rotation reference example. A plurality of reach group determination random number determination tables are provided, and a preset table is selected depending on the reservation type, the number of reservations, the gaming state, etc. When a game ball enters the first starting port 120 or the second starting port 122, one reach group determining random number is obtained from within the range of 0 to 10006. As described above, when the major prize lottery result is derived, a process is performed to determine a variable performance pattern for notifying the major prize lottery result. In the simultaneous spinning reference example, when the big winning lottery result is a "lose", in determining the variable production pattern, the group type is first determined based on the reach group determination random number and the reach group determination random number determination table.

For example, if the gaming state is set to the normal state, which will be described in detail later, and a "lose" major prize lottery result is derived based on the special 1 pending, the special 1 pending is suspended when performing the major prize lottery. If the number (hereinafter simply referred to as "pending number") is 0, reach group determination random number determination table 1 is selected as shown in FIG. 9(a). Similarly, when the normal state is set, if a "losing" major prize lottery result is derived based on special 1 reservation, if the number of reserved prizes when performing the major prize lottery is 1 to 2, As shown in FIG. 9(b), if reach group determination random number determination table 2 is selected and the number of reservations is 3, reach group determination random number determination table 3 is selected as shown in FIG. 9(c). Ru. Note that in FIG. 9, the group x listed in the group type column indicates an arbitrary group number. Therefore, various group numbers will be determined as the group type depending on the acquired reach group determination random number and the type of reach group determination random number determination table to be referred to.

Here, we have explained the reach group determination random number determination table that is referred to when a "losing" big winning lottery result is derived based on special 1 pending in the normal state, but the main ROM 300b also contains A large number of reach group determination random number determination tables are also stored.

In addition, when the big winning lottery result is a "big hit" or a "small win", the group type is not determined when determining the variable performance pattern. In other words, the reach group determination random number determination table is referred to only when the big prize lottery result is a "lose", and is not referred to when the major prize lottery result is a "big win" or a "small win".

FIG. 10 is a diagram illustrating a reach mode determination random number determination table according to a simultaneous rotation reference example. This reach mode determination random number determination table is a loss reach mode determination random number determination table that is selected when the major prize lottery result is a "loss", and a jackpot determination table that is selected when the major prize lottery result is a "jackpot". It is roughly divided into a ready-to-win mode determination random number determination table and a small-win ready-to-win mode determination random number determination table that is selected when the large winning lottery result is a "small win." In addition, the reach mode determination random number determination table at the time of a loss is provided for each group type determined as described above, and the reach mode determination random number determination table at the time of a jackpot and the reach mode determination random number determination table at the time of a small win are provided depending on the gaming state. , are provided for each reservation type.

Each reach mode determination random number determination table is also provided for each gaming state and symbol type. Here, an example of the reach mode determination random number determination table at the time of loss for group x that is referred to in a predetermined gaming state and symbol type is shown in FIG. FIG. 10(b) shows an example of the random number determination table for determining the reach mode at the time of the special 2 jackpot, and FIG. 10(d) shows an example of the random number determination table for determining the reach mode at the time of the special 1 small win. An example of the random number determination table for determining reach mode at the time of special 2 small hit is shown in FIG. 10(e).

When a game ball enters the first starting port 120 or the second starting port 122, one reach mode determining random number is obtained from within the range of 0 to 250. If the result of the above-mentioned big winning lottery is a "lose", as shown in FIG. A determination table is selected, and a variable mode number is determined based on the selected reach mode determination random number determination table in case of loss and the reach mode determination random number. In addition, if the result of the above-mentioned big winning lottery is a "jackpot", as shown in FIGS. A jackpot reach mode determination random number determination table is selected, and a variable mode number is determined based on the selected jackpot reach mode determination random number determination table and the reach mode determination random number.

Furthermore, if the result of the above-mentioned major lottery is a "small win", as shown in FIGS. A small hit reach mode determination random number determination table corresponding to is selected, and a variable mode number is determined based on the selected small win reach mode determination random number determination table and the reach mode determination random number.

In addition, in each reach mode determination random number determination table, the fluctuation pattern random number determination table described below is associated with the reach mode determination random number together with the fluctuation mode number, and at the same time as the fluctuation mode number is determined, the fluctuation pattern A random number determination table is determined. In addition, in FIG. 10, table x described in the column of variation pattern random number determination table indicates an arbitrary table number. Therefore, the fluctuation mode number and the table number of the fluctuation pattern random number determination table are determined according to the acquired reach group determination random number and the type of reach mode determination random number determination table to be referred to. In addition, in the simultaneous rotation reference example, the variation mode number and the variation pattern number, which will be described later, are set in hexadecimal numbers. In the following, when indicating a hexadecimal number, "H" is attached, but in FIGS. 10 to 12, ○○H is written to indicate an arbitrary value indicated in hexadecimal.

As described above, when the winning lottery result is a "lose", the group type is first determined based on the reach group determination random number determination table and the reach group determination random numbers shown in FIG. Then, according to the determined group type and gaming state, a variable mode number and a variable pattern random number determination table are determined based on the reach mode determination random number determination table in case of loss and the reach mode determination random number shown in FIG. 10(a).

On the other hand, if the big winning lottery result is a "big hit" or "small win", the determined jackpot symbol or small win symbol (type of special symbol), the gaming state at the time of winning the jackpot or the small win, etc. With reference to the corresponding jackpot reach mode determination random number determination table shown in FIG. 10, the fluctuation mode number and fluctuation pattern random number determination table will be determined using the reach mode determination random number.

FIG. 11 is a diagram illustrating a variation pattern random number determination table according to a simultaneous rotation reference example. Here, a fluctuation pattern random number determination table x for a predetermined table number x is shown, but many other fluctuation pattern random number determination tables are provided for each table number.

When a game ball enters the first starting port 120 or the second starting port 122, one fluctuation pattern random number is obtained from within the range of 0 to 238. Then, the variation pattern number is determined as shown in the figure based on the variation pattern random number determination table determined at the same time as the variation mode number and the obtained variation pattern random number.

In this way, when a major prize lottery is performed, a variable mode number and a variable pattern number are determined according to the major prize lottery result, the determined symbol type, the gaming state, the number of reservations, the reservation type, etc. These variable mode numbers and variable pattern numbers specify variable effect patterns, and are associated with the mode and time of the variable effect, respectively.

FIG. 12 is a diagram illustrating a variable time determination table according to a reference example of simultaneous rotation. As described above, once the variation mode number is determined, the variation time 1 is determined according to the variation time 1 determination table shown in FIG. 12(a). According to this variation time 1 determination table, variation time 1 is associated with each variation mode number, and the corresponding variation time 1 is determined according to the determined variation mode number.

Furthermore, as described above, when the variation pattern number is determined, the variation time 2 is determined according to the variation time 2 determination table shown in FIG. 12(b). According to this variation time 2 determination table, a variation time 2 is associated with each variation pattern number, and the corresponding variation time 2 is determined according to the determined variation pattern number. The total time of the fluctuation times 1 and 2 determined in this way becomes the time of the fluctuation performance for notifying the result of the big prize lottery, that is, the fluctuation time. This variation time is the time until the determined special symbol is stopped and displayed on the first special symbol display 160 or the second special symbol display 162.

As will be described in detail later, when a special symbol is determined based on the special 1 hold, and a variation mode number and a variation pattern number, that is, a variation time, the first special symbol is displayed for the determined variation time. A variable display of symbols is performed on the device 160, and when a variable time has elapsed, the determined special symbol is stopped and displayed on the first special symbol display 160. In addition, when a special symbol is determined based on the special 2 hold and a variation pattern number, that is, a variation time is determined, the variation display of the symbol is displayed on the second special symbol display 162 over the determined variation time. When the variable time has elapsed, the determined special symbol is stopped and displayed on the second special symbol display 162. At this time, the losing symbol is stopped and displayed on the first special symbol display 160, so that the losing symbol is confirmed as a result of the big prize lottery, and the next major prize lottery based on special 1 reservation can be executed, and the losing symbol is the second special symbol. By being stopped and displayed on the special symbol display 162, a loss is confirmed as a result of the major prize lottery, and the next major prize lottery based on the special 2 hold can be executed. On the other hand, when the jackpot symbol is stopped and displayed on the first special symbol display 160 or the second special symbol display 162, the jackpot is confirmed as a result of the big prize lottery, the big prize game is executed, and the small prize symbol is displayed on the first special symbol display 160. When it is stopped and displayed on the symbol display 160 or the second special symbol display 162, a small win is determined as a result of the large winning lottery, and a small win game is executed.

In this way, the fluctuation time defines the time for fluctuating display of the symbols on the first special symbol display 160 or the second special symbol display 162, in other words, the time until the result of the big prize lottery is determined. Become.

When the fluctuation mode number is determined as described above, a fluctuation mode command corresponding to the determined fluctuation mode number is transmitted to the sub control board 330, and when the fluctuation pattern number is determined, the fluctuation mode command corresponding to the determined fluctuation mode number is transmitted to the sub control board 330. A variable pattern command corresponding to the pattern number is transmitted to the sub control board 330. In the sub-control board 330, based on the received variation mode command, the first half of the variation effect is mainly determined, and the second half of the variation production is mainly determined based on the received variation pattern command. The details will be described later. Note that hereinafter, the variation mode number and the variation pattern number may be collectively referred to as variation information, and the variation mode command and the variation pattern command may be collectively referred to as variation command.

FIG. 13 is a diagram illustrating the gaming state and variable time according to a reference example of simultaneous play. As described above, the special gaming state and the normal gaming state are combined to form one gaming state, and the progress of the game is controlled according to the gaming state being set. As already explained, there are two types of special gaming states: a low probability gaming state and a high probability gaming state, which have different jackpot winning probabilities. In addition, the normal game state has three types: a non-time-saving game state, a medium-time-saving game state, and a time-saving game state, which differ in the ease of entry of game balls into the first variable starting port 120B (entering frequency). It is being

Here, in the normal game, the ease with which a game ball enters the first variable starting port 120B is determined by three factors: winning probability, variable time, and opening time. Although details will be described later, in a normal game, when a game ball passes through the gate 124 or when a game ball enters the normal pattern operation opening 125, the normal pattern holding state is stored. Then, based on the stored standard pattern reservation, a standard pattern lottery is performed to determine whether or not to release the movable piece 120b. The result of this general drawing lottery is determined after a predetermined variable time has elapsed. When a winning result is determined as a result of the general drawing lottery, the movable piece 120b is released. At this time, the probability of winning in the normal drawing lottery, the variable time, and the opening time when the movable piece 120b is opened are set for each normal game state.

In the simultaneous play reference example, as shown in FIG. 13(a), six types of game states are provided by combinations of the special game state and the normal game state. The initial state of the gaming machine 100 is a low probability gaming state and a non-time saving gaming state. In addition, in the non-time-saving gaming state, the winning probability in the general lottery is low, the fluctuation time is long, and the opening time of the movable piece 120b is short. In the simultaneous play reference example, a gaming state in which a low probability gaming state and a non-time-saving gaming state are combined is called a normal state.

In addition, in the simultaneous play reference example, a high probability gaming state and a non-time saving gaming state may be set, and a gaming state in which both are combined is called the most dominant state. This most advantageous state has the highest degree of advantage among the six gaming states, and if you shoot the game balls properly, the number of game balls will gradually increase during the game even if you do not win the jackpot. It is set to go.

In addition, in the simultaneous play reference example, the low probability game state and the time saving game state may be set. In addition, in the time-saving game state, the winning probability in the general lottery is high, the fluctuation time is short, and the open time of the movable piece 120b is long. Below, a gaming state in which a low probability gaming state and a time saving gaming state are combined will be referred to as a low probability time saving state.

In addition, in the simultaneous play reference example, the high probability game state and the time saving game state may be set. Hereinafter, a gaming state in which a high probability gaming state and a time saving gaming state are combined will be referred to as a high probability time saving state or a high probability precursor state. Note that the highly accurate time saving state and the highly accurate precursor state will be described in detail later.

In addition, in the simultaneous play reference example, the high probability game state and the medium time saving game state may be set. In addition, in the medium time-saving game state, the probability of winning in the general lottery is higher than in the non-time-saving game state and lower than in the time-saving game state, the fluctuation time is short, and the open time of the movable piece 120b is long. This gaming state can be set when an unexpected situation occurs, such as when the game ball is not launched properly. Hereinafter, a gaming state in which a high probability gaming state and a medium time saving gaming state are combined will be referred to as a penalty state.

In addition, in the sub-control board 330, a production mode corresponding to the gaming state set in the main control board 300 is set. The performance mode defines the background image, BGM, etc. displayed on the main performance display section 200a, and the content of the performance differs depending on the performance mode. In other words, the player can identify the current gaming state based on the presentation mode.

As mentioned above, in the simultaneous play reference example, six game states are provided. Then, as mentioned above, the fluctuation mode number and fluctuation pattern number, that is, the fluctuation time, are determined according to the gaming state when the big prize lottery is held, the reservation type, the number of fluctuations in the gaming state, and the symbol type. Ru.

Here, in the gaming machine 100, a substantial variable target is set for each gaming state. The actual variable object originally indicates the type of reservation for which the major prize lottery should be performed, and either special 1 reservation or special 2 reservation is set as the actual fluctuation object for each gaming state. Under normal conditions, special 1 reservation is set as subject to real fluctuation. Further, in the normal state, since the normal gaming state is a non-time-saving gaming state, the first variable starting port 120B is hardly opened. Therefore, in the normal state, the player needs to launch the game ball toward the first game area 116a in order to cause the game ball to enter the first fixed starting port 120A.

In the normal state, a big winning lottery is carried out with special 1 reservation, which is actually subject to fluctuation, and when a losing symbol or a small winning symbol is determined, the fluctuation time is determined within the range of 3 to 100 seconds. In addition, in the normal state, when a big winning lottery is carried out with Toku 1 pending and a jackpot symbol is determined, a variable time is determined within the range of 40 to 100 seconds.

On the other hand, in the normal state, when a major prize lottery is carried out by special 2 reservation, which is not subject to actual fluctuation, the fluctuation time is always determined to be 10 minutes, regardless of the determined symbol type. In this way, by setting the variable time to a long time such as 10 minutes, in the normal state, even if the player enters the game ball into the second starting port 122, the big winning lottery based on special 2 reservation will not be possible. Opportunities for execution become extremely rare.

Specifically, the second starting port 122 is provided in the second gaming area 116b, and the second starting port 122 is configured as a fixed starting port into which a game ball can always enter. Further, due to the playability of the gaming machine 100, the second starting port 122 is arranged at a position where a game ball enters more easily than the first starting port 120. Therefore, if the variation time related to special 2 pending is made short in the normal state, the player will be given more chances to win the big prize lottery than necessary. Therefore, in accordance with the original gameplay in the normal state, the variable time is set to a long time such as 10 minutes in order to appropriately launch the game ball toward the first game area 116a.

In the most advantageous state, special 2 reservation is set as subject to real fluctuation. Therefore, in the most advantageous state, the player needs to launch the game ball toward the second game area 116b in order to cause the game ball to enter the second starting port 122. In the most advantageous state, when a major prize lottery is carried out by special 1 reservation, which is not actually subject to variation, the variation time is always determined to be 10 seconds, regardless of the determined symbol type. Furthermore, in the case where a major prize lottery is held using Toku 1 reservation, which is not subject to actual fluctuation in the most advantageous state, the game quality is improved compared to when a major prize lottery is performed by Toku 2 reservation, which is not subject to actual fluctuation in the normal state. The impact is small. Therefore, in the most advantageous state, the fluctuation time when a major prize lottery is performed due to special 1 reservation, which is not subject to actual fluctuation, is set as short as 10 seconds.

In the most advantageous state, a major prize lottery is carried out using special 2 hold, which is actually subject to fluctuation, and when a losing symbol or a small winning symbol is determined, the fluctuation time is determined within the range of 1 second to 3 seconds. In addition, in the most advantageous state, a big winning lottery is performed by special 2 reservation, and when a jackpot symbol is determined, the fluctuation time is determined within the range of 3 seconds to 10 seconds.

In both the low-probability time-saving state and the high-probability time-saving state, special 1 reservation is set to be subject to actual fluctuation. In addition, in the low-accuracy time-saving state and the high-accuracy time-saving state, the normal game state is set to the time-saving game state, and the first variable starting port 120B is frequently controlled to be in the open state. Therefore, in these two gaming states, the player needs to launch the game ball toward the second game area 116b in order to cause the game ball to enter the first variable starting port 120B. In these two gaming states, the same variable pattern random number determination table is selected, but these two gaming states have in common that the normal gaming state is a time-saving gaming state. In other words, when the normal gaming state is the time-saving gaming state, when a big winning lottery is held with special 1 reservation, which is subject to actual fluctuation, and a losing symbol or a small winning symbol is determined, the fluctuation time of 1 second is always determined. Ru. In addition, in the case of a low probability time saving state and a high probability time saving state, when a big winning lottery is carried out by special 1 reservation and a jackpot symbol is determined, the variable time is always determined to be 30 seconds.

In the high certainty precursor state, special 1 suspension is set as subject to real fluctuation. In addition, in the high certainty precursor state, the normal game state is set to the time-saving game state, and the first variable starting port 120B is frequently controlled to be in the open state. Therefore, in the high probability precursor state, the player needs to launch the game ball toward the second game area 116b in order to cause the game ball to enter the first variable starting port 120B. In the high probability precursor state, a big winning lottery is carried out by special 1 reservation which is a real variable target, and when a losing symbol or a small winning symbol is determined, a variable time is determined within the range of 3 seconds to 10 seconds. In addition, in the high certainty precursor state, when a big winning lottery is performed with special 1 pending and a jackpot symbol is determined, the fluctuation time is always determined to be 30 seconds.

On the other hand, in a low-probability time-saving state, a high-probability time-saving state, and a high-probability portent state, that is, when the normal gaming state is a time-saving gaming state, if a big prize lottery is held by special 2 reservation, which is not subject to actual fluctuation, Regardless of the determined symbol type, the variation time is always determined to be 10 minutes.

In the penalty state, special 1 suspension is set to be subject to actual fluctuation. Further, in the penalty state, the normal game state is set to the medium time saving game state, and the first variable starting port 120B is controlled to be open at a constant frequency. Therefore, in the penalty state, the player needs to launch the game ball toward the second game area 116b in order to cause the game ball to enter the first variable starting port 120B. In the penalty state, a big winning lottery is carried out using special 1 hold, which is actually subject to fluctuation, and when a losing symbol or a small winning symbol is determined, the fluctuation time is determined within the range of 3 to 100 seconds. In addition, in the penalty state, when a big prize lottery is carried out by holding special 1 and a jackpot symbol is determined, a variable time is determined within the range of 40 to 100 seconds.

On the other hand, in the penalty state, if a major prize lottery is carried out by special 2 reservation which is not actually subject to variation, the variation time is always determined to be 10 minutes, regardless of the determined symbol type.

As described above, a real variable target is set for each gaming state, and when a major prize lottery is performed based on the reservation type as a real variable target, the longest variable time is 100 seconds. On the other hand, when a major prize lottery is performed based on a reservation type that is not subject to actual fluctuation, the fluctuation time is approximately 10 minutes, and a game that is contrary to the original gameplay is prevented from being played.

In addition, in the simultaneous rotation reference example, we will explain the case where the average fluctuation time of the high-accuracy time-saving state is shorter than the average fluctuation time of the high-accuracy precursor state, but the average fluctuation time of the high-accuracy time-saving state is It may be longer than the average fluctuation time of the precursor state. In other words, the average of the fluctuation times of the highly reliable time saving state and the average of the fluctuation times of the highly reliable precursor state may be different.

FIG. 14 is a first diagram illustrating a special electric accessory operation ram set table according to a simultaneous rotation reference example, and FIG. 15 is a first diagram illustrating a special electric accessory operation ram set table according to a simultaneous rotation reference example. It is a figure of 2. In addition, the special electric accessory actuation ram set table stores various data for controlling the big prize game or the small winning game, and during the big prize game or the small winning game, the special electric accessory actuating ram set table With reference to the table, the first big winning hole solenoid 126c or the second big winning hole solenoid 128c is controlled to be energized. In addition, in reality, there are multiple special electric accessory activation ram set tables for each type of special symbol (big winning symbol and small winning symbol), and the corresponding table is used as a major prize depending on the determined type of special symbol. Although it is set at the start of a game or a small winning game, here, for convenience of explanation, special symbol control data is shown for each symbol type.

As shown in FIG. 14, the big winning game consists of a plurality of round games in which the big prize opening is opened and closed a predetermined number of times, and the small winning game is a round game that is executed only once. According to this special electric accessory activation ram set table, the opening time (waiting time until the first round game starts), the maximum number of special electric accessory activations (performed during one big prize game or small winning game) (number of round games to be played), number of special electric accessory opening/closing switches (number of openings of the grand prize opening during one round), solenoid energization time (first grand prize opening solenoid 126c or second grand prize opening for each number of openings of the grand prize opening) The energization time of the grand prize opening solenoid 128c, that is, the opening time of one grand prize opening), the specified number (the maximum possible number of prizes to the grand prize opening in one round game), the effective time for closing the grand prize opening (round Closing time of the big prize opening between games, that is, interval time), ending time (waiting time from the end of the last round game until the normal special game (variable symbol display described below) is resumed) However, as control data, each type of special symbol is stored in advance as shown in the figure.

Incidentally, when a jackpot is won by special 1 reservation and special symbols A, B, and D are determined as jackpot symbols, a big prize game consisting of four round games is executed. In this big winning game, each of the first big prize openings 126 is opened only once in the first to fourth round games. In each round game, the first big prize opening 126 is opened for a maximum of 29.0 seconds, and if a specified number of game balls enter the ball during this time, or the maximum opening time (29.0 seconds) has elapsed, the first prize opening 126 is opened for a maximum of 29.0 seconds. One big prize opening 126 is closed and one round game ends.

Further, when a jackpot is won by special 1 reservation and special symbols C and E are determined as jackpot symbols, a big prize game consisting of 10 round games is executed. In these big winning games, the first big prize opening 126 is opened only once in each of the 1st to 10th round games. In each round game, the first big prize opening 126 is opened for a maximum of 29.0 seconds, and if a specified number of game balls enter the ball during this time, or the maximum opening time (29.0 seconds) has elapsed, the first prize opening 126 is opened for a maximum of 29.0 seconds. One big prize opening 126 is closed and one round game ends.

Further, when a small win is won due to special 1 retention and special symbols Z1 to Z3 are determined as the small win symbols, a small win game consisting of one round game is executed. In this small winning game, the second big prize opening 128 is opened once for 0.1 seconds in one round game.

In addition, as shown in FIG. 15, if a jackpot is won by special 2 hold and special symbols F, G, and I are determined as jackpot symbols, a big prize game consisting of four round games is executed. Ru. In this big winning game, each of the first big prize openings 126 is opened only once in the first to fourth round games. In each round game, the first big prize opening 126 is opened for a maximum of 29.0 seconds, and if a specified number of game balls enter the ball during this time, or the maximum opening time (29.0 seconds) has elapsed, the first prize opening 126 is opened for a maximum of 29.0 seconds. One big prize opening 126 is closed and one round game ends.

Further, when a jackpot is won by special 2 holding and special symbols H and J are determined as jackpot symbols, a big prize game consisting of 10 round games is executed. In this big prize game, each of the first big prize openings 126 is opened only once in the first to tenth round games. In each round game, the first big prize opening 126 is opened for a maximum of 29.0 seconds, and if a specified number of game balls enter the ball during this time, or the maximum opening time (29.0 seconds) has elapsed, the first prize opening 126 is opened for a maximum of 29.0 seconds. One big prize opening 126 is closed and one round game ends.

Further, even when a small hit is won due to special 2 reservation and special symbols Z4 to Z6 are determined as the small winning symbols, a small winning game consisting of one round game is executed. Here, in the small winning game when the special symbol Z4 is determined as the small winning symbol, the second large prize opening 128 is opened twice for 0.1 seconds in one round game. Note that the in-round interval time, which is the pause time between opening the second big prize opening 128 twice, is set to 1.78 seconds. Since the game balls are fired at intervals of 0.6 seconds at the shortest, considering the opening time of the second big prize opening 128 and the firing interval of the game balls, the game ball will win the second big prize during this small winning game. The probability of the ball hitting the opening 128 is low.

However, in the simultaneous play reference example, the game balls tend to stay on the movable piece 128b that maintains the second big prize opening 128 in the closed state, and when the movable piece 128b changes to the open state, the movable The game balls staying on the piece 128b are guided into the second big prize opening 128. Therefore, by opening the second grand prize opening 128 twice for 0.1 seconds, two to three game balls will enter the second grand prize opening 128 on average.

In addition, in a small winning game where the special symbol Z5 is determined as the small winning symbol, the second large prize opening 128 is opened 0.1 seconds x 3 times in one round game. Note that the in-round interval time in this case is set to 0.84 seconds. In this small winning game, three to four game balls enter the second big prize opening 128 on average.

Further, in a small winning game in which the special symbol Z6 is determined as the small winning symbol, the second large prize opening 128 is opened 0.1 seconds x 12 times in one round game. Note that the in-round interval time in this case is set to 0.84 seconds. In this small winning game, by continuing to fire game balls toward the second game area 116b, it is almost certain that a specified number (for example, 10) of game balls enter the second big prize opening 128. can.

In addition, at the design stage of the gaming machine 100, it is necessary to strictly manage and adjust the firing prize ball ratio, which is the ratio between the number of game balls fired and the number of paid prize balls. Therefore, in the simultaneous rotation reference example, a special symbol Z4 is provided in which the opening for 0.1 seconds is made twice in the small winning game, and a special symbol Z5 is provided in which the opening is made for 0.1 seconds three times in the small winning game, By simply changing these selection ratios, the firing prize ball ratio can be easily adjusted and changed.

FIG. 16 is a diagram illustrating a game state setting table for setting the game state after the end of the big prize game according to the simultaneous play reference example. In the simultaneous play reference example, when a big prize game is executed, the game state setting table is referred to according to the game state at the time of winning the jackpot, the reservation type, and the type of special symbol (jackpot symbol), and after the big prize game ends. Set the gaming state of.

When the game state at the time of winning a jackpot is a normal state or a penalty state, when winning a jackpot due to special 1 reservation which is subject to actual fluctuation, the game state after the jackpot game is set according to the type of the jackpot symbol. Specifically, when the special symbol A is determined as the jackpot symbol, a low probability time saving state is set (the special gaming state is a low probability gaming state, and the normal gaming state is a time saving gaming state). At this time, the number of times the time-saving game state continues (hereinafter referred to as "time-saving number") is set to 100 times. This means that the time-saving gaming state continues until the major prize lottery is performed 100 times. However, the above-mentioned number of time-savings indicates the maximum number of continuations in the time-saving gaming state of 1, and if you win a jackpot before reaching the number of continuations mentioned above, the gaming state will be set again. It happens. Therefore, when the time-saving gaming state is set after the end of the big prize game, if a jackpot lottery result is not derived in the time-saving gaming state and lottery results other than the jackpot are derived 100 times, the non-time-saving gaming state is set. The gaming state will be changed to (normal state).

Further, when special symbols B and D are determined as jackpot symbols, a high probability time saving state is set (the special gaming state is a high probability gaming state, and the normal gaming state is a time saving gaming state). At this time, "next time" is set as the high probability number of times, and the high probability gaming state continues until the next jackpot is won. In addition, "next time" is set as the number of time saving times, and the time saving gaming state continues until the next jackpot is won. Therefore, when the special symbols B and D are determined, the highly accurate time-saving state continues after the big prize game until the next jackpot is won.

Further, when special symbols C and E are determined as jackpot symbols, a high probability precursor state is set (the special game state is a high probability game state, and the normal game state is a time saving game state). At this time, "next time" is set as the high accuracy number of times, and the time saving number of times is set to 100 times. When special symbols C and E are determined, the high probability game state continues until the next jackpot is won, while the time-saving game state ends after 100 times. Therefore, when special symbols C and E are determined, the gaming state will shift to the most advantageous state after the big prize game and when the result of the big prize lottery has been derived 100 times.

Further, if the gaming state at the time of winning the jackpot is the normal state or the penalty state, if the jackpot is won by special 2 reservation which is not subject to actual fluctuation, the gaming state after the jackpot game is set as follows. That is, when the special symbol F is determined as a jackpot symbol, the normal state is set (the special gaming state is a low probability gaming state, and the normal gaming state is a non-time saving gaming state). Further, when special symbols G to J are determined as jackpot symbols, a penalty state is set (the special game state is a high probability game state, and the normal game state is a medium time saving game state). At this time, both the high-accuracy count and the time-saving count are set to "next time."

Further, if the gaming state at the time of winning the jackpot is the most advantageous state, if the jackpot is won by special 1 reservation, which is not subject to actual fluctuation, the gaming state after winning the jackpot is set as follows. That is, when the special symbol A is determined as a jackpot symbol, a low probability time saving state is set (the special gaming state is a low probability gaming state, and the normal gaming state is a time saving gaming state). At this time, the number of time saving times is set to 100 times. Further, when the special symbols B to E are determined as the jackpot symbols, the game state after the big prize game is set in the same way as the normal state and the penalty state.

On the other hand, if the gaming state at the time of winning the jackpot is the most advantageous state, when winning the jackpot due to special 2 reservation which is subject to actual fluctuation, the gaming state after winning the jackpot game is set as follows. That is, when the special symbol F is determined as a jackpot symbol, a low probability time saving state is set (the special gaming state is a low probability gaming state and the normal gaming state is a time saving gaming state). At this time, the number of time saving times is set to 100 times. Further, when special symbols G and I are determined as jackpot symbols, a high probability time saving state is set (the special game state is a high probability game state and the normal game state is a time saving game state). At this time, the high-accuracy count and the time-saving count are set to "next time."

Further, when special symbols H and J are determined as jackpot symbols, a high probability precursor state (the special game state is a high probability game state, and the normal game state is a time-saving game state) is set. At this time, the high accuracy number of times is set to "next time" and the time saving number of times is set to 100 times.

In addition, if the gaming state at the time of winning a jackpot is a low probability time saving state, a high probability time saving state, or a high probability premonitory state, that is, if the normal gaming state is the time saving gaming state, the gaming state after the big winning game is the normal state. and penalty status.

FIG. 17 is a diagram illustrating a winning determination random number determination table according to a simultaneous play reference example. When a game ball flowing down the game area 116 passes through the gate 124 or enters the normal operating port 125, it is associated with whether or not to control the energization of the movable piece 120b of the first variable starting port 120B. A normal symbol determination process (hereinafter referred to as "normal symbol lottery") is performed.

Although the details will be described later, when the game ball passes through the gate 124 or enters the normal pattern operation port 125, one winning determination random number is obtained from within the range of 0 to 99, and this random number is Numerical values are stored in the general figure reservation storage area of the main RAM 300c, with an upper limit of four. In other words, the common pattern holding storage area includes four storage sections for saving winning determination random numbers. Therefore, when the game ball passes through the gate 124 or enters the normal pattern operation opening 125 with the determined random number stored in all four storage units of the normal pattern holding storage area, the game ball No winning random numbers are stored based on the passage of the ball. Hereinafter, the winning determination random number stored in the normal pattern holding storage area when a game ball passes through the gate 124 or enters the normal pattern operation opening 125 will be referred to as normal pattern holding.

When starting the regular lottery when the normal gaming state is the non-time-saving gaming state, the winning determination random number determination table for the non-time-saving gaming state is referred to, as shown in FIG. 17(a). According to this winning random number determination table for non-time-saving gaming state, when the winning random number is 0, a winning symbol is determined as the type of normal symbol, and when the winning random number is 1 to 99, A losing symbol is determined as the type of normal symbol. Therefore, the probability that a winning symbol is determined in the non-time-saving gaming state, that is, the winning probability is 1/100. As will be described in detail later, when a winning symbol is determined in this general lottery, the movable piece 120b of the first variable starting port 120B is controlled to be in the open state, and when a losing symbol is determined, the first variable starting port is opened. The movable piece 120b of the mouth 120B is maintained in the closed state.

In addition, when starting the regular lottery in the medium time saving game state, as shown in FIG. 17(b), the winning determination random number determination table for the medium time saving game state is referred to. According to this winning random number determination table for the medium time saving game state, when the winning random number is between 0 and 49, a winning symbol is determined as a type of normal symbol, and when the winning random number is between 50 and 99. Then, a losing symbol is determined as the type of normal symbol. Therefore, the probability that a winning symbol is determined in the medium time saving gaming state, that is, the winning probability is 50/100.

Further, when starting the regular lottery in the time-saving gaming state, as shown in FIG. 17(c), the winning determination random number determination table for the time-saving gaming state is referred to. According to this winning random number determination table for the time-saving gaming state, when the winning random number is 0 to 98, a winning symbol is determined as the type of normal symbol, and when the winning random number is 99, the winning symbol is determined as a normal symbol. A losing symbol is determined as the symbol type. Therefore, the probability that a winning symbol is determined in the time-saving gaming state, that is, the winning probability is 99/100.

FIG. 18(a) is a diagram illustrating a normal symbol fluctuation time data table according to a simultaneous rotation reference example, and FIG. 18(b) is a diagram illustrating an opening/closing control pattern table according to a simultaneous rotation reference example. As described above, when the ordinary symbol lottery is performed, the fluctuation time of the ordinary symbol is determined. The normal symbol fluctuation time data table is referred to when determining the fluctuation time of the normal symbol when a winning symbol or a losing symbol is determined by the regular symbol lottery. According to this normal symbol variation time data table, when the gaming state is set to the non-time saving gaming state and the medium time saving gaming state, the variation time is determined to be 10 seconds, and when the gaming state is set to the time saving gaming state. If so, the variation time is determined to be 1 second. When the variable time is determined in this manner, the normal symbol display 168 is displayed in a variable manner (blinking display) over the determined time. Then, when a winning symbol is determined, the normal symbol display 168 lights up, and when a losing symbol is determined, the normal symbol display 168 is turned off.

Then, when the winning symbol is determined by the ordinary symbol lottery and the ordinary symbol display 168 lights up, the movable piece 120b of the first variable starting port 120B performs opening/closing control as shown in FIG. 18(b). The energization is controlled by referring to the pattern table. In fact, the opening/closing control pattern table is provided for each gaming state, and depending on the gaming state when the normal symbol is determined, the corresponding table is set when the energization of the normal electric accessory solenoid 120c starts. .

When the winning symbol is determined, as shown in FIG. 18(b), the opening/closing control of the first variable starting port 120B is performed with reference to the opening/closing control pattern table. According to this opening/closing control pattern table, the time before normal electric opening (the waiting time until opening of the first variable starting port 120B starts), the maximum number of switching times for normal electric accessories (opening of the first variable starting port 120B), number of times), solenoid energization time (the energization time of the normal electric accessory solenoid 120c for each number of times the first variable starting port 120B is opened, that is, the opening time of the first variable starting port 120B once), the specified number (the first variable maximum number of prizes that can be won in the first variable starting port 120B while the starting port 120B is fully open), normal power closing effective time (closing time between each opening of the first variable starting port 120B, that is, rest time), normal power Valid state time (wait time from the end of the last opening of the first variable starting port 120B), normal power end wait time (wait until the normal symbol fluctuation display, which will be described later, is resumed after the normal power valid state time has elapsed) time) is stored in advance as control data for the first variable starting port 120B for each gaming state as shown in the figure.

In this way, by setting the winning probability of the normal symbol, the variable time, and the opening time, as shown in the lower part of FIG. The ratio of the number of prize balls paid out to the player when game balls enter the first variable starting port 120B, the second starting port 122, the normal pattern operating port 125, and the big winning port) is the number of balls fired in the non-time saving gaming state. : Number of prize balls = 100:20, number of fired balls: number of prize balls = 100:40 in the medium time saving game state, number of fired balls: number of prize balls = 100:99 in the time saving game state.

The opening/closing conditions of the first variable starting port 120B define three elements: the winning probability of the normal symbol, the time of variable display of the normal symbol, and the opening time of the first variable starting port 120B. In other words, by combining the three elements of the winning probability of the normal symbol, the time of variable display of the normal symbol, and the opening time of the first variable starting port 120B, in each of the non-time-saving gaming state, the intermediate time-saving gaming state, and the time-saving gaming state, It is possible to set the frequency of game balls entering the first variable starting port 120B and the firing prize ball ratio. In any case, the combination of the three elements shown here is just an example, and if you combine the three elements so that the firing prize ball ratio is higher in the time-saving game state than in the non-time-saving game state, good.

FIG. 19 is a diagram illustrating the transition of the gaming state according to the original gaming nature according to the simultaneous play reference example. With the above configuration, the gaming machine 100 realizes the following gaming experience. Note that here, a case will be described in which the registration setting value is set to "1". First, in the initial state of the gaming machine 100, it is set to the normal state shown in FIG. 19(a). In the normal state, since the actual variable target is set to special 1 pending, the player shoots the game ball toward the first game area 116a in order to enter the game ball into the first fixed starting port 120A. Since the first game area 116a is located on the left side of the game board 108, the player will play what is called "left-handed play" in the normal state.

When a game ball enters the first fixed starting port 120A, special 1 reservation is stored in the first special figure reservation storage area. The special 1 reservations stored in the first special symbol reservation storage area are sequentially read out when the starting condition is met, and a big prize lottery is performed based on the read special 1 reservations. At this time, the probability of winning the jackpot is set to approximately 1/300.6. In the normal state, a game is played with the aim of winning a jackpot in the big winning lottery based on this special 1 reservation. Note that the firing prize ball ratio when the game balls are fired toward the first game area 116a is set to 100:20, and the number of game balls will decrease during the game.

Then, in the normal state, when a jackpot is won in the big winning lottery by special 1 reservation, the big winning game is executed. In this big winning game, a round game in which the first big prize opening 126 is opened is executed 4 or 10 times, and the player can win prize balls for 4 or 10 rounds. When a jackpot is won due to special 1 retention, one of the special symbols A to E is determined as the jackpot symbol.

In the normal state, when the jackpot symbol stopped and displayed on the first special symbol display 160 is the special symbol A, the gaming state after the big winning game becomes a low probability time saving state shown in FIG. 19(b). When winning a jackpot with special 1 pending, the probability that special symbol A will be determined as the jackpot symbol is 30%. Therefore, if the player wins a jackpot in the normal state, there is a 30% probability that the gaming state will shift to the low probability time saving state. In the low-probability time-saving state, the actual variable target is set to special 1 pending, but since the normal gaming state is the time-saving gaming state, the player enters the first variable start opening 120B with the game ball. 2. The player will hit the ball to the right aiming at the 2 game area 116b.

That is, in this low-probability time-saving state, as in the normal state, a game is played with the aim of winning a jackpot in the big winning lottery based on special 1 reservation. Note that in the low-probability time-saving state, the probability of winning a jackpot is about 1/300.6, but since the normal game state is the time-saving game state, the movable piece 120b is frequently in the open state. Therefore, the firing prize ball ratio is 100:99, and the player can aim for a jackpot while reducing consumption of game balls.

In addition, when shifting to the low probability time saving state, the number of time saving times is set to 100, and if the jackpot is not won in the 100 big winning lottery, the gaming state will change to the normal state again (time saving exit) ).

In addition, in the normal state, if the jackpot symbols stopped and displayed on the first special symbol display 160 are special symbols B and D, the gaming state after the big prize game is the high accuracy time saving shown in FIG. 19(c). state. When winning a jackpot with special 1 pending, the probability that special symbols B and D will be determined as jackpot symbols is 35%. Therefore, if the player wins a jackpot in the normal state, there is a 35% probability that the gaming state will shift to the high-accuracy time-saving state. In the high-accuracy time-saving state, the actual variable target is set to special 1 pending, but since the normal gaming state is the time-saving gaming state, the player enters the game ball into the first variable starting port 120B. 2. The player will hit the ball to the right aiming at the 2 game area 116b.

That is, in this high probability time saving state, as in the normal state, a game is played with the aim of winning a jackpot in the big winning lottery based on special 1 reservation. In addition, in the high-accuracy time-saving state, the probability of winning a jackpot is about 1/105.7, and since the normal game state is the time-saving game state, the movable piece 120b is frequently opened. Therefore, the firing prize ball ratio is 100:99, and the player can perform the big winning lottery while reducing the consumption of game balls. Therefore, in the high probability time saving state, it can be said that the winning of the next jackpot is virtually guaranteed.

In addition, in the normal state, if the jackpot symbols stopped and displayed on the first special symbol display 160 are special symbols C and E, the gaming state after the big winning game is a high probability precursor as shown in FIG. 19(d). state. When winning a jackpot with special 1 pending, the probability that special symbols C and E will be determined as jackpot symbols is 35%. Therefore, if the player wins a jackpot in the normal state, there is a 35% probability that the gaming state will shift to the high-predictability precursor state. In the high certainty precursor state, the actual variable target is set to special 1 pending, but since the normal gaming state is the time saving gaming state, the player enters the first variable starting port 120B with the first variable. 2. The player will hit the ball to the right aiming at the 2 game area 116b.

When the special symbols C and E are determined, a highly accurate precursor state is set and the time saving number is set to 100 times. At this time, when the number of fluctuations after the big prize game reaches 100, the time-saving game state ends and the normal game state becomes a non-time-saving game state. As a result, due to the time saving, the gaming state shifts to the most advantageous state shown in FIG. 19(e). As will be described in detail later, in the most dominant state, the number of game balls can be increased by simply continuing to shoot the game balls toward the second game area 116b. Therefore, in the high probability precursor state, the purpose of the game is not to win the jackpot, but to save time without winning the jackpot.

According to the above-mentioned special 1 suspension of real fluctuation objects in the high probability precursor state, high probability time saving state, and low probability time saving state, when a jackpot is won, special symbols A to E are determined as jackpot symbols. When the special symbol A is determined, four round games are executed in the big prize game, and the game state after the big prize game becomes a low probability time saving state shown in FIG. 19(b). Further, when special symbols B and D are determined, 4 or 10 round games are executed in the big prize game, and the gaming state after the big prize game becomes a high-accuracy time-saving state. Further, when the special symbols C and E are determined, four or ten round games are executed in the big prize game, and the game state after the big prize game becomes a high probability precursor state.

In the most dominant state, when a game ball enters the second starting port 122, special 2 reservation is stored in the second special figure reservation storage area. The special 2 reservations stored in the second special symbol reservation storage area are sequentially read out when the starting condition is met, and a big prize lottery is performed based on the read special 2 reservations. At this time, the winning probability of the jackpot is set to about 1/105.7, and the winning probability of the small winning is set to about 1/3.45. In the most advantageous state, the main purpose of the game is to win the small prize in the major prize lottery based on this special 2 reservation.

Specifically, when game balls are fired into the second game area 116b, the ratio of prize balls paid out by entering the game balls into the second starting port 122 to the number of fired balls is 100:60 to 80. It is set to about. In the most advantageous state, small winning games are frequently played because the probability of winning a small winning is about 1/3.45 in the special lottery with special 2 reservation. Here, if a small hit is won due to special 2 reservation, small winning symbols Z4 to Z6 are determined. As described above, in the small winning game when the small winning symbol Z4 is stopped and displayed on the second special symbol display 162, an average of 2 to 3 game balls enter the second large prize opening 128. In the small winning game when the small winning symbol Z5 is stopped and displayed on the second special symbol display 162, an average of 3 to 4 game balls enter the second large prize opening 128. Furthermore, in the small winning game when the small winning symbol Z6 is stopped and displayed on the second special symbol display 162, almost a specified number of game balls enter the second large winning hole 128.

When a game ball enters the second large winning hole 128, for example, 15 prize balls are paid out for each game ball that enters. As a result, in the most dominant state, the firing prize ball ratio, which is the ratio of the number of all prize balls to the number of firing balls, is 100:120, and by simply continuing to fire the game balls toward the second game area 116b, the game ball can be increased.

In addition, in this most dominant state, the normal game state has become a non-time-saving game state, and the movable piece 120b is almost never in the open state. In addition, in the most advantageous state, the special gaming state is a high probability game state, and the probability of winning a jackpot in the most advantageous state is about 1/105.7, so in the most advantageous state, the next It can be said that winning the jackpot is guaranteed.

According to the special 2 reservation of the real variable object in this most dominant state, when a jackpot is won, special symbols F to J are determined as jackpot symbols. When the special symbol F is determined, four round games are executed in the big prize game, and the game state after the big prize game becomes a low probability time saving state shown in FIG. 19(b). Further, when the special symbols G and I are determined, 4 or 10 round games are executed in the big prize game, and the gaming state after the big prize game becomes a high-accuracy time-saving state. Further, when the special symbols H and J are determined, 4 or 10 round games are executed in the big prize game, and the game state after the big prize game becomes a high probability precursor state.

Since the most advantageous state has an extremely high degree of advantage compared to other gaming states, the main purpose of the game in the gaming machine 100 is to shift the gaming state to the most advantageous state. As mentioned above, the game is first started in the normal state, but the normal state does not shift to the most advantageous state all at once. Therefore, the transition route of transitioning to the most dominant state via the high probability precursor state is the transition route to the most dominant state in gaming machine 100.

Furthermore, in the simultaneous spinning reference example, apart from the time-saving exit in the high-precision precursor state, winning a specific small winning symbol is set as a transition condition from the high-precision precursor state to the most advantageous state. Specifically, if you win a small hit with special 1 reservation, which is a real fluctuation target in a high probability precursor state, the special symbol Z1 will be 1%, the special symbol Z2 will be 69%, and the special symbol Z3 will be 30% as the small winning symbol. % probability (see FIG. 8(c)).

At this time, when the special symbol Z1 is determined as the small winning symbol, the time saving game state ends with the end of the small winning game, and as a result, the gaming state shifts to the most advantageous state.

In this way, since the player moves to the most advantageous state upon winning a specific small win, the player is This always creates a sense of anticipation and tension.

In addition, in the above-mentioned high probability precursor state, high probability time saving state, and low probability time saving state, the probability of winning a small win is about 1/3.45. Therefore, even in the high probability precursor state, the high probability time saving state, and the low probability time saving state, small winning games are frequently executed as in the most advantageous state. However, in the high probability precursor state, the high probability time saving state, and the low probability time saving state, the normal gaming state is the time saving gaming state. Further, as will be described in detail later, the normal game state is maintained in the time-saving game state even during the small winning game. Therefore, although the second large prize opening 128 is opened during the small winning game, the first variable starting opening 120B is also opened during this time.

As described above, the first variable starting opening 120B is provided above the second big winning opening 128, and in the time-saving gaming state, the opening time of the first variable starting opening 120B is longer than the second big winning opening. It is much longer than the opening time of the mouth 128. Therefore, in the high-accuracy precursor state, the high-accuracy time-saving state, and the low-accuracy time-saving state, most of the game balls flowing down the second gaming area 116b enter the first variable starting opening 120B and enter the second big prize opening 128. Game balls almost never enter the ball. As a result, in the high-accuracy precursor state, the high-accuracy time-saving state, and the low-accuracy time-saving state, unlike the most dominant state, the number of game balls will gradually decrease even if you hit right during the game.

As mentioned above, when the game progresses with the real variable object in accordance with the original gameplay, if you win a jackpot, the gaming state after the big winning game will be a low probability time saving state, a high probability time saving state, a high probability premonitory state. Set to either. The high-probability time-saving state and the high-probability portent state have in common that the special game state is a high-probability game state, and the normal game state is a time-saving game state. On the other hand, the high-accuracy time-saving state continues until the next jackpot is won, whereas the high-accuracy precursor state is when the game is stopped by winning a specific small win (special symbol Z1) or exiting the time-saving state. The difference is that the state is shifted to the most dominant state.

In addition, in the high accuracy time saving state, the fluctuation time for small hits and losses is set to 1 second, whereas in the high accuracy precursor state, the fluctuation time for small wins and losses is set to 3 to 10 seconds. The difference is that it is set within the range (see FIG. 13(b)). That is, the average of the fluctuation times in the high certainty time saving state is set to be shorter than the average fluctuation time in the high certainty precursor state.

Therefore, in the high-accuracy time-saving state, since the fluctuation time at the time of a small win and a loss is relatively short, it is possible to digest the actual fluctuation targets at a high speed until winning the jackpot. Although a detailed explanation will be omitted, during the special symbol variation time, the effect symbols 210a, 210b, and 210c are displayed in a variable manner on the sub-control board 330. In the highly accurate time saving state, the variable display of the performance symbols 210a, 210b, and 210c also becomes relatively short. Therefore, in the high-accuracy time-saving state, as long as the special 1 reservation continues to be memorized, the special 1 reservation (fluctuating display of production symbols 210a, 210b, and 210c) will continue to be consumed at a high speed, and the time until winning the jackpot will be reduced. This allows the player to play the game until the next jackpot without feeling (reduced) stress.

On the other hand, in the highly accurate precursor state, the fluctuation time at the time of a small hit and a loss is relatively long, but the sub-control board 330 performs an effect as to whether or not the state will shift to the most advantageous state. Therefore, the player can play the game while expecting that the state will shift to the most advantageous state.

In this way, in the high-accuracy time-saving state, even if you win a specific small hit (special symbol Z1), it will not shift to the most advantageous state, but by setting the average fluctuation time short, the next big hit It is possible to shorten the time it takes to win a game and reduce stress on the player. In addition, in the high-accuracy precursor state, the average fluctuation time is set longer than in the high-accuracy time-saving state, but the fluctuation time can be used to determine whether or not to move to the most advantageous state, and the game This can give people a sense of anticipation and tension.

As described above, there are a high-probability time-saving state and a high-probability portent state in which the special game state is a high-probability game state and the normal game state is a time-saving game state, and changes in the high-probability time-saving state are provided. By making the average time shorter than the average fluctuating time of the high-predictability precursor state, new gaming features can be provided.

FIG. 20 is a diagram illustrating the transition of the game state when the game is not played properly according to the simultaneous play reference example. As described above, in the gaming machine 100, the variable display of symbols on the first special symbol display 160 and the variable display of symbols on the second special symbol display 162 are performed simultaneously and in parallel. At this time, in the case where there is a possibility that the player will be disadvantaged as a result of a big winning lottery being held due to suspension of items other than those subject to actual fluctuation, the fluctuation time is set to a long time such as 10 minutes. However, after the big winning lottery is held due to reservations other than the actual fluctuation targets, for example, as a result of interrupting the game, a jackpot due to reservations other than the actual fluctuation targets may be confirmed. In this case, the gaming state will change as shown in FIG. 20.

Below, the main processing of the main control board 300 for realizing the above-mentioned gaming properties will be explained.

FIG. 21 is a diagram illustrating a gaming machine status flag according to a reference example of simultaneous play. In the main control board 300, whether or not the game can be played is managed by a gaming machine status flag. The gaming machine status flag is set to one of six flag values from 00H to 05H. The flag value of the gaming machine status flag = 00H indicates a gaming enabled state, and when the gaming machine status flag is 00H, the progress of the game is controlled, and when the gaming machine status flag is other than 00H, the game is stopped. will be stopped.

The flag value of the gaming machine state flag=01H indicates a setting change state, and when the gaming machine state flag is 01H, the registered setting value can be changed. The flag value of the gaming machine status flag = 02H indicates the setting confirmation status, and when the gaming machine status flag is 02H, the registered setting value is displayed on the performance display monitor 184, etc. It becomes possible to confirm. The flag value of the gaming machine status flag=03H indicates an abnormal setting state, and when the gaming machine status flag is 03H, the registered setting value is considered abnormal and the game is stopped. The flag value of the gaming machine status flag=04H indicates a RAM abnormal state, and when the gaming machine status flag is 04H, the game is stopped. The flag value of the gaming machine status flag=05H indicates a checksum abnormal state, and when the gaming machine status flag is 05H, the game is stopped. When the power is turned on, the gaming machine status flag is set to one of the flag values, and processing according to the gaming machine status flag is performed.

(CPU initialization process of main control board 300)
FIG. 22 is a first flowchart illustrating the CPU initialization process in the main control board 300 according to the simultaneous running reference example, and FIG. 23 is a first flowchart illustrating the CPU initialization process in the main control board 300 according to the simultaneous running reference example. FIG.

When power is supplied from the power supply board, a system reset occurs in the main CPU 300a, and the main CPU 300a performs the following CPU initialization process (S100).

(Step S100-1)
When the main CPU 300a is powered on, the main CPU 300a reads a startup program from the main ROM 300b as an initial setting process and performs setting processes necessary to execute various processes.

(Step S100-3)
The main CPU 300a sets a wait processing time in a timer counter.

(Step S100-5)
The main CPU 300a determines whether a power-off notice signal is detected. Note that the main control board 300 is provided with a power-off detection circuit, and when the power supply voltage falls below a predetermined value, a power-off warning signal is output from the power-off detection circuit. If a power cutoff notice signal is detected, the process moves to step S100-3, and if a power cutoff notice signal is not detected, the process moves to step S100-7.

(Step S100-7)
The main CPU 300a determines whether the wait time set in step S100-3 above has elapsed. As a result, if it is determined that the wait time has elapsed, the process moves to step S100-9, and if it is determined that the wait time has not elapsed, the process moves to step S100-5.

(Step S100-9)
Main CPU 300a executes necessary processing to permit access to main RAM 300c.

(Step S100-11)
The main CPU 300a loads the flag value of the gaming machine status flag before power-off into the D register.

(Step S100-13)
The main CPU 300a calculates a checksum, and determines whether the calculated checksum matches (is normal) the checksum saved when the power is turned off, and whether the backup flag is normal. As a result, if it is determined that the backup flag and the checksum are normal, the process moves to step S100-15, and if it is determined that either one or both are not normal, the process moves to step S100-25. .

(Step S100-15)
The main CPU 300a sets an address that does not include the set value and gaming machine status flag as the start address of the main RAM 300c to be cleared.

(Step S100-17)
The main CPU 300a determines whether a RAM clear operation signal is input from the RAM clear switch 182s (whether the RAM clear button is pressed). As a result, if it is determined that the RAM clear operation signal is input, the process moves to step S100-31, and if it is determined that the RAM clear operation signal is not input, the process moves to step S100-19. .

(Step S100-19)
The main CPU 300a checks whether the flag value of the gaming machine status flag loaded in step S100-11 is 00H (playable state), the setting change switch 180s is on, and the middle frame 104 is open. judge. As a result, if it is determined that all three conditions are satisfied, the process moves to step S100-21, and if it is determined that even one of the three conditions is not satisfied, the process moves to step S100-23.

(Step S100-21)
The main CPU 300a sets the gaming machine status flag to 02H (setting confirmation status). That is, if the power is turned on normally with the middle frame 104 open, the setting change switch 180s turned on, and the RAM clear button not pressed, the setting confirmation state is entered.

(Step S100-23)
The main CPU 300a executes an initialization process to clear the area of the main RAM 300c after the start address set in step S100-15, which is to be cleared when the power is restored, and moves the process to step S100-49.

(Step S100-25)
The main CPU 300a sets 05H (checksum abnormal state) in the D register.

(Step S100-27)
The main CPU 300a performs an out-of-area read/write check process that checks and clears the read/write memory in the out-of-use area.

(Step S100-29)
The main CPU 300a sets an address including the setting value and the gaming machine status flag to the top address of the main RAM 300c to be cleared.

(Step S100-31)
The main CPU 300a checks and clears the read/write memory of the used area.

(Step S100-33)
The main CPU 300a determines whether the check result of the read/write memory in step S100-31 is normal. As a result, if it is determined that it is normal, the process moves to step S100-37, and if it is determined that it is not normal, the process moves to step S100-35.

(Step S100-35)
The main CPU 300a sets 04H (RAM abnormal state) in the D register, and moves the process to step S100-45.

(Step S100-37)
The main CPU 300a determines whether 02H (setting confirmation state) is set in the D register. As a result, if it is determined that 02H is set, the process moves to step S100-39, and if it is determined that 02H is not set, the process moves to step S100-41.

(Step S100-39)
The main CPU 300a sets 00H (game ready state) in the D register.

(Step S100-41)
The main CPU 300a determines whether the setting change conditions are satisfied. As a result, if it is determined that the setting change conditions are satisfied, the process moves to step S100-43, and if it is determined that the setting change conditions are not satisfied, the process moves to step S100-45. Here, the setting change conditions include at least that the setting change switch 180s is turned on, that the middle frame 104 is open, and that a RAM clear operation signal is input from the RAM clear switch 182s. included.

(Step S100-43)
The main CPU 300a sets 01H (setting change state) in the D register.

(Step S100-45)
The main CPU 300a saves the value set in the D register to the gaming machine status flag.

(Step S100-47)
The main CPU 300a executes an initialization process to clear the items to be cleared when clearing the RAM in the main RAM 300c, and moves the process to step S100-49.

(Step S100-49)
The main CPU 300a performs processing for transmitting a payout command (RAM clear designation command) (stores the RAM clear designation command in a transmission buffer) for transmitting to the payout control board 310 that the main RAM 300c has been cleared.

(Step S100-51)
The main CPU 300a loads the gaming machine status flag.

(Step S100-53)
The main CPU 300a determines whether the gaming machine status flag loaded in step S100-51 is 00H (playable status). As a result, if it is determined that it is 00H, the process moves to step S110, and if it is determined that it is not 00H, the process moves to step S100-55.

(Step S110)
The main CPU 300a performs subcommand group setting processing. Note that this subcommand group set processing will be described later.

(Step S100-55)
The main CPU 300a performs a sub-command group setting process for transmitting a predetermined command to the sub-control board 330.

(Step S100-57)
The main CPU 300a sets the cycle of timer interrupts.

(Step S100-59)
The main CPU 300a performs processing to prohibit interrupts.

(Step S100-61)
The main CPU 300a updates the initial value update random number for the winning symbol random number. In addition, the initial value update random number for the winning pattern random number is for determining the initial value and end value of the winning pattern random number. In other words, when the winning pattern random number goes through one round from the initial value update random number for the winning pattern random number to -1 the initial value update random number for the winning pattern random number by the updating process of the winning pattern random number described later, the winning pattern random number at that time It will be updated to the initial value update random number for the winning symbol random number.

(Step S100-63)
The main CPU 300a analyzes the received data (main command) received from the payout control board 310, and executes various processes according to the received data.

(Step S100-65)
The main CPU 300a performs processing for transmitting sub-commands stored in the transmission buffer to the sub-control board 330.

(Step S100-67)
The main CPU 300a performs processing to permit interrupts.

(Step S100-69)
The main CPU 300a updates the reach group determination random number, the reach mode determination random number, and the fluctuation pattern random number, and thereafter repeats the process from step S100-59. In addition, below, the reach group determination random number, the reach mode determination random number, and the fluctuation pattern random number for determining the fluctuation performance pattern are collectively referred to as the random number for fluctuation performance.

FIG. 24 is a flowchart illustrating subcommand group setting processing (S110) in the main control board 300 according to the simultaneous execution reference example.

(Step S110-1)
The main CPU 300a loads the flag value of the gaming machine status flag.

(Step S110-3)
The main CPU 300a performs a sub-command group setting process for transmitting a predetermined command to the sub-control board 330.

(Step S110-5)
The main CPU 300a performs a model command setting process to set a model command indicating model information of the gaming machine 100 in the transmission buffer.

(Step S110-7)
The main CPU 300a performs a setting value designation command setting process of setting a setting value designation command indicating a registered setting value in a transmission buffer.

(Step S110-9)
The main CPU 300a performs a special figure 1 reservation designation command setting process that sets a special figure 1 reservation designation command indicating the number of special 1 reservations in the transmission buffer.

(Step S110-11)
The main CPU 300a performs a special figure 2 reservation designation command setting process that sets a special figure 2 reservation designation command indicating the number of special 2 reservations in the transmission buffer.

(Step S110-13)
The main CPU 300a performs a number command setting process to set a number command indicating the remaining number of times in the time saving gaming state in the transmission buffer.

(Step S110-15)
The main CPU 300a performs a variation pattern selection state designation command setting process that sets a variation pattern selection state designation command indicating a variation pattern selection state in the transmission buffer.

(Step S110-17)
The main CPU 300a performs a special figure phase designation command setting process that sets a special figure phase designation command indicating a special game management phase in the transmission buffer. The special game management phase will be described later.

(Step S110-19)
The main CPU 300a determines whether the special game management phase is in a special symbol change waiting state. As a result, if it is determined that it is in the special symbol change waiting state, the process moves to step S110-21, and if it is determined that it is not in the special symbol change waiting state, the subcommand group set process is ended.

(Step S110-21)
The main CPU 300a sets the customer waiting designation command in the transmission buffer, and ends the subcommand group setting process.

Next, interrupt processing in the main control board 300 will be explained. Here, the power-off saving process (XINT interrupt process) and timer interrupt process will be explained.

(Evacuation processing at power-off of main control board 300 (XINT interrupt processing))
FIG. 25 is a flowchart illustrating the power-off saving process (XINT interrupt process) in the main control board 300 according to the simultaneous operation reference example. The main CPU 300a monitors the power-off detection circuit, and when the power supply voltage falls below a predetermined value, interrupts the CPU initialization process and executes the power-off save process.

(Step S300-1)
When the power-off notice signal is input, the main CPU 300a saves the register.

(Step S300-3)
The main CPU 300a checks the power-off notice signal.

(Step S300-5)
The main CPU 300a determines whether a power-off notice signal is detected. As a result, if it is determined that a power-off notice signal has been detected, the process moves to step S300-11, and if it is determined that a power-off notice signal has not been detected, the process moves to step S300-7. .

(Step S300-7)
The main CPU 300a restores the register.

(Step S300-9)
The main CPU 300a performs processing to permit interrupts, and ends the power-off save processing.

(Step S300-11)
The main CPU 300a executes output port clear processing to stop output from the output port.

(Step S300-13)
The main CPU 300a executes checksum setting processing to calculate and save a checksum.

(Step S300-15)
The main CPU 300a executes RAM protect setting processing necessary to prohibit access to the main RAM 300c.

(Step S300-17)
The main CPU 300a sets a predetermined number of times the power outage detection signal has been detected to the counter value of the loop counter in order to set the power outage occurrence monitoring time.

(Step S300-19)
The main CPU 300a checks the power-off notice signal.

(Step S300-21)
The main CPU 300a determines whether a power-off notice signal is detected. As a result, if it is determined that a power-off notice signal has been detected, the process moves to step S300-17, and if it is determined that a power-off notice signal has not been detected, the process moves to step S300-23. .

(Step S300-23)
The main CPU 300a subtracts 1 from the value of the loop counter set in step S300-17 above.

(Step S300-25)
The main CPU 300a determines whether the counter value of the loop counter is not zero. As a result, if it is determined that the counter value is not 0, the process moves to step S300-19, and if it is determined that the counter value is 0, the process moves to the above-described CPU initialization process (step S100).

Note that if the power is actually cut off, the operation of the gaming machine 100 is stopped while the steps S300-17 to S300-25 are looped.

(Timer interrupt processing of main control board 300)
FIG. 26 is a flowchart illustrating timer interrupt processing in the main control board 300 according to the simultaneous operation reference example. The main control board 300 is provided with a reset clock pulse generation circuit that generates a clock pulse every predetermined period (4 milliseconds in the simultaneous running reference example, hereinafter referred to as "4ms"). When a clock pulse is generated by the reset clock pulse generation circuit, the CPU initialization process (step S100) is interrupted and the following timer interrupt process is executed.

(Step S400-1)
The main CPU 300a saves the register.

(Step S400-3)
The main CPU 300a performs processing to permit interrupts.

(Step S400-5)
The main CPU 300a outputs the common data set in the common output buffer to the output port, and outputs the first special symbol display 160, the second special symbol display 162, the first special symbol reservation display 164, and the second special symbol reservation. Dynamic port output processing is executed to control the lighting of the display 166, normal symbol display 168, normal symbol pending display 170, right hit notification display 172, and performance display monitor 184.

(Step S400-7)
The main CPU 300a reads various input port information and executes port input processing to accurately obtain the latest switch status.

(Step S400-9)
The main CPU 300a loads the flag value of the gaming machine status flag.

(Step S400-11)
The main CPU 300a determines whether the flag value loaded in step S400-9 is 00H (playable state). As a result, if it is determined that it is 00H, the process moves to step S400-15, and if it is determined that it is not 00H, the process moves to step S400-13.

(Step S400-13)
The main CPU 300a determines whether the flag value loaded in step S400-9 above is equal to or greater than 03H (setting abnormal state). As a result, if it is determined that it is 03H or more, the process moves to step S400-29, and if it is determined that it is not 03H or more, the process moves to step S450.

(Step S450)
The main CPU 300a executes setting-related processing and moves the processing to step S400-29. Note that the setting-related processing will be described later.

(Step S400-15)
The main CPU 300a performs timer update processing to update various timer counters. Here, unless otherwise specified, the various timer counters are decremented each time the main control board 300 performs timer interrupt processing, and when they reach 0, they stop decrementing.

(Step S400-17)
The main CPU 300a executes the process of updating the initial value update random number for the winning symbol random number, as in step S100-61 above.

(Step S400-19)
The main CPU 300a performs a process of updating the winning symbol random number. Specifically, the random number counter is incremented by 1 and updated, and if the added result exceeds the maximum value of the random number range, the random number counter is reset to 0, and when the random number counter has completed one cycle, the current Update the random number from the initial value update random number for winning symbol random number.

Although detailed explanation will be omitted, in the simultaneous rotation reference example, the jackpot determination random number and the hit determination random number use hardware random numbers that are updated by a hardware random number generation section built into the main control board 300. The hardware random number generator updates both the jackpot determination random number and the winning determination random number according to certain rules, automatically changes the random number sequence every time the random number sequence goes around, and updates the starting value every time the system is reset. It is changing.

(Step S500)
The main CPU 300a includes a first fixed starting opening detection switch 120As, a first variable starting opening detection switch 120Bs, a second starting opening detection switch 122s, a gate detection switch 124s, a regular figure operation opening detection switch 125s, and a first big winning opening detection switch. 126s, a switch management process is executed to determine whether or not a signal is input from the second big winning opening detection switch 128s. Note that details of this switch management processing will be described later.

(Step S600)
The main CPU 300a executes a special game management process for controlling the progress of the variable display of special symbols based on the special 2 hold of the special game. The details of this special game management process will be described later.

(Step S600)
The main CPU 300a executes a special game management process for controlling the progress of the variable display of special symbols based on special 1 suspension of the special games. In addition, here, the same program (module) as the special game management process for controlling the progress of the variable display of special symbols based on special 2 reservation is read out, and the same program (module) as the special game management process for controlling the progress of the variable display of special symbols based on special 1 reservation is read out. Special game management processing for control will be executed.

(Step S700)
The main CPU 300a executes special electric accessory game management processing for controlling the progress of the big winning game and the small winning game in the special game. The details of this special electric accessory game management process will be described later.

(Step S800)
The main CPU 300a executes a normal game management process for controlling the progress of the above-mentioned normal game. The details of this normal game management process will be described later.

(Step S400-21)
The main CPU 300a executes error management processing for determining various errors and making settings according to the error determination results.

(Step S400-23)
The main CPU 300a checks the general winning opening detection switch 118s, the first starting opening detection switch 120s, the second starting opening detection switch 122s, the first big winning opening detection switch 126s, and the second big winning opening detection switch 128s, and detects the corresponding The prize opening switch process is executed to increment the counter etc. for prize ball control.

(Step S400-25)
The main CPU 300a executes a payout control management process for creating and transmitting a payout command based on the counter value of the prize ball control counter set in step S400-23 above.

(Step S400-27)
The main CPU 300a is a firing command for transmitting a firing position designation command to the sub control board 330, which instructs the firing position of the game ball, that is, to which of the first game area 116a and the second game area 116b the game ball is to be fired. Execute location specification management processing.

(Step S400-29)
The main CPU 300a executes an external information management process for setting output data for external information to be output from the game information output terminal board 312 to the outside.

(Step S400-31)
The main CPU 300a includes a first special symbol display 160, a second special symbol display 162, a first special symbol pending display 164, a second special symbol pending display 166, a normal symbol display 168, and a normal symbol pending display 170. , executes an LED display setting process in which display data for controlling the lighting of various indicators (LEDs) such as the right-handed hit notification display 172 is set in the output buffer corresponding to each common.

(Step S400-33)
The main CPU 300a synthesizes the solenoid output images of the normal electric accessory solenoid 120c, the first big winning hole solenoid 126c, and the second big winning hole solenoid 128c, and executes a solenoid output image synthesis process for storing the synthesized image in the output port buffer. .

(Step S400-35)
The main CPU 300a executes port output processing for outputting the common output buffer value stored in each output port buffer to the output port.

(Step S400-37)
The main CPU 300a performs processing to prohibit interrupts.

(Step S400-39)
The main CPU 300a uses the unused area of the main RAM 300c to perform processing for calculating a base ratio to be displayed on the performance display monitor 184, and to common data for displaying the calculated base ratio on the performance display monitor 184. Execute performance display monitor control processing to set in the output buffer. Note that in the performance display monitor control process, the base ratio is calculated every predetermined period. Here, the base ratio of the current period and the base ratio of the previous period may be switched and displayed on the performance display monitor 184 at predetermined time intervals. Further, the base ratio displayed on the performance display monitor 184 may be switched in accordance with a predetermined operation.

(Step S400-41)
The main CPU 300a restores the register and ends the timer interrupt processing.

FIG. 27 is a flowchart illustrating the setting-related processing (S450) according to the simultaneous rotation reference example.

(Step S450-1)
The main CPU 300a determines whether the flag value of the gaming machine status flag is 01H (setting change status). As a result, if it is determined that it is 01H, the process moves to step S450-3, and if it is determined that it is not 01H, the process moves to step S450-15.

(Step S450-3)
The main CPU 300a loads the registered setting values stored in the setting value buffer into a predetermined processing area.

(Step S450-5)
The main CPU 300a determines whether the RAM clear switch 182s is pressed (whether a RAM clear operation signal is input). As a result, if it is determined that the RAM clear switch 182s is pressed, the process moves to step S450-7, and if it is determined that the RAM clear switch 182s is not pressed, the process moves to step S450-9. .

(Step S450-7)
The main CPU 300a adds 1 to the setting value of the processing area.

(Step S450-9)
The main CPU 300a determines whether the setting value of the processing area is within the range of 1 to 6. As a result, if it is determined that the set value is within the range of 1 to 6, the process moves to step S450-13, and if it is determined that the set value is not within the range of 1 to 6, the process moves to step S450-11. move.

(Step S450-11)
The main CPU 300a sets the setting value of the processing area to 1.

(Step S450-13)
The main CPU 300a sets the setting value of the processing area in the setting value buffer.

(Step S450-15)
The main CPU 300a determines whether the setting change switch 180s is on. As a result, if it is determined that the setting change switch 180s is turned on, the setting-related process is ended, and if it is determined that the setting change switch 180s is not turned on, the process moves to step S450-17.

(Step S450-17)
The main CPU 300a sets a settings-related end designation command indicating the end of the settings-related process in the transmission buffer.

(Step S110)
The main CPU 300a executes the subcommand group set process shown in FIG. That is, when the setting-related process is executed, at the end, the model command, setting value specification command, special figure 1 hold specification command, special figure 2 hold specification command, number of times command, variation pattern selection state specification command, special figure phase A designation command and a customer waiting designation command are transmitted to the sub-control board 330.

(Step S450-19)
The main CPU 300a sets the gaming machine state flag to 00H (playable state) and ends the setting-related processing.

As described above, according to the simultaneous rotation reference example, when the power is turned on normally with the middle frame 104 opened, the setting change switch 180s turned on, and the RAM clear button pressed, the CPU initializes. In the processing (FIG. 22), 01H (setting change state) is set in the gaming machine state flag. After that, the timer interrupt process is executed, but since the gaming machine status flag is set to 01H (setting change status), all processes related to the progress of the game (steps S400-15 to S400-27 in FIG. 26) are executed. ) is stopped and configuration-related processing is executed.

The setting-related process is repeatedly executed while the setting change switch 180s is on, and during this setting-related process, a press operation of the RAM clear button is accepted as a setting change operation of the registered setting value. That is, during the setting change process (S450-1 to S450-13) that accepts a setting change operation, the registered setting value stored in the setting value buffer is set to one of the setting values in multiple stages according to the setting change operation. can be switched to

Then, when the setting change switch 180s is turned off while the gaming machine status flag is set to 01H (setting change state), the setting change process ends and the gaming machine status flag is set to 00H (playable status). Set. As a result, processing related to the progress of the game can be executed from the next timer interrupt processing.

Here, in the setting-related processing of the simultaneous rotation reference example, after the RAM clear button press operation, that is, the reception of the setting change operation of the registered setting value, is completed, the setting value corresponding to the registered setting value is specified in the subcommand group set processing. The command is sent to sub control board 330. On the other hand, while a setting change operation is being accepted, the setting value designation command is not sent to the sub control board 330. In this way, the setting value specification command is not sent while the setting change operation is being accepted, but the setting value specification command is sent when the setting change operation is finished accepting and the game can proceed. By doing so, it is possible to reduce the risk that registered setting values are obtained illegally.

Further, in the simultaneous rotation reference example, a plurality of flag values including at least 01H (setting change state) are switched. When the gaming machine state flag is set to 01H (setting change state), the setting-related process becomes executable and the progress of the game is stopped. In this way, since no settings-related processing is executed while the game is in progress, no setting value specification commands are sent while the game is in progress, reducing the risk of unauthorized acquisition of registered setting values. be done.

Next, among the timer interrupt processes described above, the switch management process in step S500, the special game management process in step S600, the special electric accessory game management process in step S700, and the normal game management process in step S800 will be explained in detail. .

FIG. 28 is a flowchart illustrating switch management processing (step S500) in the main control board 300 according to the simultaneous operation reference example.

(Step S500-1)
The main CPU 300a determines whether the gate detection switch is being turned on, that is, whether the game ball has passed through the gate 124 and the detection signal from the gate detection switch 124s has been turned on. As a result, if it is determined that the gate detection switch-on is detected, the process moves to step S510, and if it is determined that the gate detection switch-on is not detected, the process moves to step S500-7.

(Step S510)
The main CPU 300a executes a gate passage process based on passage of the game ball to the gate 124. Note that details of this gate passing process will be described later.

(Step S500-3)
The main CPU 300a determines whether the normal game operating port detection switch is on-detected, that is, whether a game ball enters the normal game operating port 125 and the detection signal from the normal game operating port detection switch 125s is turned on. . As a result, if it is determined that the ordinary figure actuation opening detection switch is turned on, the process moves to step S510, and if it is determined that the ordinary figure actuation opening detection switch is not turned on, the process goes to step S500-5. move.

(Step S510)
The main CPU 300a executes a gate passing process based on the entry of the game ball into the normal figure operating port 125.

(Step S500-5)
The main CPU 300a determines whether the first fixed starting port detection switch is turned on, that is, whether a game ball enters the first fixed starting port 120A and a detection signal is input from the first fixed starting port detection switch 120As. judge. As a result, if it is determined that the first fixed starting port detection switch is on, the process moves to step S520, and if it is determined that the first fixed starting port detection switch is not on, the process moves to step S500-7. Processing is transferred to .

(Step S520)
The main CPU 300a executes the first starting port passing process based on the game ball entering the first fixed starting port 120A. Note that details of this first starting port passing process will be described later.

(Step S500-7)
The main CPU 300a determines whether the first variable starting port detection switch is turned on, that is, whether a game ball enters the first variable starting port 120B and a detection signal is input from the first variable starting port detection switch 120Bs. judge. As a result, if it is determined that the first variable starting port detection switch is on, the process moves to step S520, and if it is determined that the first variable starting port detection switch is not on, the process moves to step S500-11. Processing is transferred to .

(Step S520)
The main CPU 300a executes the first starting port passing process based on the entry of the game ball into the first variable starting port 120B. Note that details of this first starting port passing process will be described later.

(Step S500-9)
The main CPU 300a determines whether the game ball has entered the first variable starting port 120B properly, and if it is determined that the game ball has not entered the first variable starting port 120B properly, the main CPU 300a determines whether the game ball has entered the first variable starting port 120B properly. A normal electric accessory winning confirmation process is executed to send a normal electric accessory winning error generation designation command to the sub-control board 330, which indicates that an illegal game ball has entered the variable starting port 120B.

(Step S500-11)
The main CPU 300a determines whether the second starting port detection switch is on-detection, that is, whether a game ball enters the second starting port 122 and a detection signal is input from the second starting port detection switch 122s. As a result, if it is determined that the second starting port detection switch is on, the process moves to step S530, and if it is determined that the second starting port detection switch is not on, the process moves to step S500-13. move.

(Step S530)
The main CPU 300a executes the second starting port passing process based on the game ball entering the second starting port 122. Note that details of this second starting port passage processing will be described later.

(Step S500-13)
The main CPU 300a determines whether the big winning opening detection switch is turned on, that is, when a game ball enters the first big winning opening 126 or the second big winning opening 128 and the first big winning opening detection switch 126s or the second big winning opening detection switch is turned on. It is determined whether a detection signal is input from the big winning opening detection switch 128s. As a result, if it is determined that the big winning opening detection switch is on, the process moves to step S540, and if it is determined that the big winning opening detection switch is not on, the switch management process is ended.

(Step S540)
The main CPU 300a determines whether the game ball has entered properly into the first big winning hole 126 or the second big winning hole 128, and when it is determined that the game ball has entered properly. In this step, a grand prize opening passage process is executed to transmit a grand prize opening entry command indicating the entry of a game ball into the first grand prize opening 126 or the second grand prize opening 128 to the sub-control board 330. The details of this big prize opening passage process will be described later.

FIG. 29 is a flowchart illustrating the gate passing process (step S510) in the main control board 300 according to the simultaneous rotation reference example.

(Step S510-1)
The main CPU 300a loads the winning determination random number updated by the hardware random number generator.

(Step S510-3)
The main CPU 300a determines whether the counter value of the normal symbol reserved ball number counter is greater than or equal to the maximum value, that is, whether the counter value of the normal symbol reserved ball number counter is 4 or more. As a result, if it is determined that the counter value of the normal symbol reserved ball number counter is greater than or equal to the maximum value, the gate passing process is terminated, and if it is determined that the normal symbol reserved ball number counter is not greater than the maximum value, The process moves to step S510-5.

(Step S510-5)
The main CPU 300a updates the counter value of the normal symbol reserved ball number counter to a value obtained by adding "1" to the current counter value.

(Step S510-7)
The main CPU 300a calculates a target storage section in which the acquired winning determination random number is to be saved among the four storage sections of the normal pattern reservation storage area.

(Step S510-9)
The main CPU 300a saves the winning determination random number obtained in the above step S510-1 in the target storage section calculated in the above step S510-7.

(Step S510-11)
The main CPU 300a sets in the transmission buffer a general pattern reservation designation command indicating the general pattern reservation number stored in the general pattern reservation storage area, and ends the gate passing process.

FIG. 30 is a flowchart illustrating the first starting port passing process (step S520) in the main control board 300 according to the simultaneous rotation reference example.

(Step S520-1)
The main CPU 300a sets "00H" as the special symbol identification value. In addition, the special symbol identification value is for identifying whether the reservation type is special 1 reservation or special 2 reservation, and the special symbol identification value (00H) indicates special 1 reservation, and the special symbol identification value (00H) indicates special 1 reservation. 01H) indicates special 2 reservation.

(Step S520-3)
The main CPU 300a sets the address of the special symbol 1 reserved ball counter.

(Step S535)
The main CPU 300a executes a special symbol random number acquisition process, and ends the first starting opening passage process. Note that this special symbol random number acquisition process is executed using a module common to the second starting port passing process (step S530). Therefore, details of the special symbol random number acquisition process will be explained after explaining the second starting opening passage process.

FIG. 31 is a flowchart illustrating the second starting port passing process (step S530) in the main control board 300 according to the simultaneous rotation reference example.

(Step S530-1)
The main CPU 300a sets "01H" as the special symbol identification value.

(Step S530-3)
The main CPU 300a sets the address of the special symbol 2 reserved ball number counter.

(Step S535)
The main CPU 300a executes a special symbol random number acquisition process, which will be described later, and ends the second starting opening passage process.

FIG. 32 is a flowchart illustrating the special symbol random number acquisition process (step S535) in the main control board 300 according to the simultaneous rotation reference example. This special symbol random number acquisition process is executed using a common module in the first starting opening passage process (step S520) and the second starting opening passage process (step S530) described above.

(Step S535-1)
The main CPU 300a loads the special symbol identification value set in step S520-1 or step S530-1.

(Step S535-3)
The main CPU 300a loads the number of target special symbol reserved balls. Here, if the special symbol identification value loaded in step S535-1 is "00H", the counter value of the special symbol 1 reserved ball number counter, that is, the special 1 reserved number is loaded. Further, if the special symbol identification value loaded in step S535-1 is "01H", the counter value of the special symbol 2 reserved ball number counter, that is, the special 2 reserved number is loaded.

(Step S535-5)
The main CPU 300a loads the jackpot determination random number updated by the hardware random number generator.

(Step S535-7)
The main CPU 300a determines whether the target special symbol reserved ball number loaded in step S535-3 is equal to or greater than the upper limit value. As a result, if it is determined that it is greater than or equal to the upper limit value, the special symbol random number acquisition process is ended, and if it is determined that it is not greater than or equal to the upper limit value, the process moves to step S535-9.

(Step S535-9)
The main CPU 300a updates the counter value of the target special symbol reserved ball number counter to a value obtained by adding "1" to the current counter value.

(Step S535-11)
The main CPU 300a calculates a target storage section in which the acquired jackpot determination random number is to be saved among the storage sections of the special figure reservation storage area.

(Step S535-13)
The main CPU 300a acquires the jackpot determination random number loaded in step S535-5 above, the winning symbol random number updated in step S400-19 above, and the fluctuation pattern random number updated in step S100-69 above, and executes the random number in step S535-11 above. Store it in the target storage unit calculated in .

(Step S535-15)
The main CPU 300a loads the counter values of the special symbol 1 reserved ball number counter and the special symbol 2 reserved ball number counter.

(Step S535-17)
The main CPU 300a sets the special figure reservation designation command in the transmission buffer based on the counter value loaded in step S535-15. Here, the special symbol 1 reservation designation command is set based on the counter value of the special symbol 1 reservation ball number counter (special 1 reservation number), and the special symbol 1 reservation designation command is set based on the counter value of the special symbol 2 reservation ball number counter (special 2 reservation number). and set the special map 2 reservation designation command. As a result, the number of special 1 reservations and the number of special 2 reservations are transmitted to the sub-control board 330 every time special 1 reservation or special 2 reservation is stored.

(Step S536)
The main CPU 300a performs the performance determination process at the time of acquisition, and ends the special symbol random number acquisition process. In this performance determination process at the time of acquisition, the result of the major lottery, the fluctuation pattern number, etc. are tentatively determined, and a prefetch designation command according to the result of the tentative determination is transmitted to the sub-control board 330. This performance determination process at the time of acquisition will be explained using FIG. 33.

FIG. 33 is a flowchart illustrating the acquisition performance determination process (step S536) in the main control board 300 according to the simultaneous rotation reference example.

(Step S536-1)
The main CPU 300a selects a corresponding jackpot determination random number determination table based on the setting value being set. Specifically, the corresponding jackpot determination random number determination table is selected based on the current gaming state and the setting value being set. Then, based on the selected table and the jackpot determination random number stored in the target storage section in step S535-13, special symbol hit provisional determination processing is performed to provisionally determine whether it is a jackpot, a small win, or a loss.

(Step S536-3)
The main CPU 300a executes a special symbol temporary determination process for temporarily determining a special symbol. Here, if the result of the provisional major lottery in step S536-1 (the result derived by the special symbol hit provisional determination process) is a jackpot or small win, it is stored in the target storage unit in step S535-13. Load the winning pattern random number, winning type (big hit or small win), and pending type, select the corresponding winning pattern random number judgment table, extract the special pattern judgment data, and extract the extracted special pattern judgment data. (Type of jackpot symbol or small prize symbol). Further, if the result of the tentative major lottery in step S536-1 is a loss, special symbol determination data for a predetermined loss (type of loss symbol) is saved.

(Step S536-5)
The main CPU 300a sets a prefetch symbol type designation command (prefetch designation command) corresponding to the special symbol determination data saved in step S536-3 in the transmission buffer.

(Step S536-7)
The main CPU 300a determines whether the result derived by the temporary special symbol hit determination process in step S536-1 is a big hit or a small hit. As a result, if it is determined that it is a big hit or a small win, the process moves to step S536-9, and if it is determined that it is not a big hit or a small hit (a loss), the process moves to step S536-11.

(Step S536-9)
The main CPU 300a sets the random number determination table for determining the reach mode at the time of a jackpot (see FIGS. 10(b) and (c)) or the random number determination table for determining the reach mode at the time of a small win (see FIGS. 10(d) and (e)), and performs step The process moves to S536-19.

(Step S536-11)
The main CPU 300a loads the reach group determination random number stored in the target storage unit in step S535-13 above.

(Step S536-13)
The main CPU 300a determines whether the reach group determination random number loaded in step S536-11 is a fixed value (9000 or more). Here, the group type is determined with reference to the reach group determination random number determination table, and this reach group determination random number determination table is selected according to the stored number of reservations. At this time, the reach group determination random number is obtained from the range of 0 to 10006, and if the value of the reach group determination random number is 9000 or more, the same reach group determination random number determination table is selected regardless of the number of reservations, and the reach group determination random number is If the value of the group determination random number is less than 9000, a different reach group determination random number determination table is selected depending on the number of reservations. In the following, among the reach group determination random numbers, a value in the range of 0 to 8999, in which different reach group determination random number determination tables are selected depending on the number of reservations, is defined as an undefined value, and the same reach group determination random number determination table is used regardless of the number of reservations. The values in the range 9000 to 10006 from which the table is selected are called fixed values. If it is determined that the reach group determination random number loaded in the above step S536-11 is a fixed value (9000 or more), the process moves to step S536-15, and the reach group determination random number loaded in the above step S536-11 is fixed. If it is determined that it is not a value (9000 or more), the process moves to step S536-27.

(Step S536-15)
The main CPU 300a sets a reach group determination random number determination table (see FIG. 9). Although a plurality of types of reach group determination random number determination tables are provided depending on the number of reservations, here, the table used when the number of reservations is 0 is selected. Then, a reach group (group type) is tentatively determined based on the set reach group determination random number determination table and the reach group determination random number stored in the target storage unit in step S535-13.

(Step S536-17)
The main CPU 300a sets a reach mode determination random number determination table (see FIG. 10(a)) corresponding to the group type tentatively determined in step S536-15, and moves the process to step S536-19.

(Step S536-19)
The main CPU 300a determines the variable mode number based on the reach mode determination random number determination table set in step S536-9 or step S536-17, and the reach mode determination random number stored in the target storage unit in step S535-13. tentatively decided. Also, here, a variation pattern random number determination table is provisionally determined together with the variation mode number.

(Step S536-21)
The main CPU 300a sets a prefetch designation variation mode command (prefetch designation command) corresponding to the variation mode number tentatively determined in step S536-19 above in the transmission buffer.

(Step S536-23)
The main CPU 300a tentatively determines a fluctuation pattern number based on the fluctuation pattern random number determination table tentatively determined in step S536-19 and the fluctuation pattern random number stored in the target storage unit in step S535-13.

(Step S536-25)
The main CPU 300a sets the prefetch designation variation pattern command (prefetch designation command) corresponding to the variation pattern number tentatively determined in step S536-23 in the transmission buffer, and ends the acquisition performance determination process.

(Step S536-27)
The main CPU 300a sends an indefinite value command (preread The designated fluctuation mode command and the pre-read designated fluctuation pattern command (=7FH) are set in the transmission buffer, and the acquisition performance determination process is ended.

FIG. 34 is a flowchart illustrating the big winning opening passage process (step S540) in the main control board 300 according to the simultaneous rotation reference example.

(Step S540-1)
If the main CPU 300a determines in step S500-13 that the big winning opening detection switch is on, it loads a special electric accessory game management phase which will be described in detail later. Although the details will be described later, the special electric accessory game management phase indicates the stage of execution processing of the big prize game or the small winning game, that is, the progress status of the big winning game or the small winning game. It is updated according to the stage of execution processing of the winning game.

(Step S540-3)
The main CPU 300a determines whether the special electric accessory game management phase loaded in the above step S540-1 indicates a stage of execution processing equal to or higher than the grand prize opening pre-processing. In addition, the special electric accessory game management phase is provided with nine stages from 00H to 08H, of which 01H to 08H corresponds to the stage of execution processing beyond the grand prize opening pre-processing. Since the big winning game or the small winning game is executed when the special electric accessory game management phase is from 01H to 08H, here, it is determined whether the big winning game or the small winning game is currently being played. Become. If it is determined that the special electric accessory game management phase indicates a stage of execution processing higher than the grand prize opening pre-processing, the process moves to step S540-5, and the special electric accessory game management phase If it is determined that this does not indicate a stage of execution processing beyond the grand prize opening pre-processing, the process moves to step S540-7.

(Step S540-5)
The main CPU 300a sets a grand prize opening entry ball command indicating that the game ball has properly entered the first grand prize opening 126 or the second grand prize opening 128 in the transmission buffer, and ends the grand prize opening passing process. .

(Step S540-7)
The main CPU 300a determines that the entry of the game ball into the first big winning hole 126 or the second big winning hole 128 is inappropriate, executes a predetermined error process, and ends the big winning hole passing process.

FIG. 35 is a diagram illustrating the special game management phase according to the simultaneous play reference example. As already explained, in the simultaneous rotation reference example, there is a special game triggered by the entry of a game ball into the first starting port 120 or the second starting port 122, and a special game triggered by the passing of a game ball into the gate 124 or the normal pattern operating port. A normal game triggered by the entry of a game ball into the ball 125 proceeds simultaneously and in parallel. Processing related to the special game is executed stepwise and repeatedly, but the main control board 300 manages each processing related to the special game in a special game management phase and a special electric accessory game management phase. .

As shown in FIG. 35, the main ROM 300b stores a plurality of special game control modules for executing and controlling the variable display of special symbols in the special game, and each of these special game control modules A management phase is associated with it. Specifically, when the special game management phase is "00H", a module for executing the "special symbol change waiting process" is called, and when the special game management phase is "01H", A module for executing "special symbol fluctuation processing" is called, and when the special game management phase is "02H", a module for executing "special symbol stop symbol display processing" is called.

In addition, the main ROM 300b stores a plurality of special electric accessory game control modules for controlling the execution of big prize games and small winning games among the special games, and for each of these special electric accessory game control modules, The special electric accessory game management phase is associated with it. Specifically, when the special electric accessory game management phase is “01H” or “05H”, a module for executing “big prize opening opening pre-processing” is called, and the special electric accessory game management phase is called. When the phase is "02H" or "06H", a module for executing "big prize opening control process" is called, and the special electric accessory game management phase is "03H" or "07H". In this case, the module for executing the “big winning opening closing effective process” is called, and if the special electric accessory game management phase is “04H” or “08H”, the “big winning opening ending wait processing” is called. ” is called. Note that when the special electric accessory game management phase is "00H", no special electric accessory game control module is called.

FIG. 36 is a flowchart illustrating the special game management process (step S600) in the main control board 300 according to the simultaneous play reference example.

(Step S600-1)
The main CPU 300a loads the special electric accessory game management phase.

(Step S600-3)
The main CPU 300a determines whether the special electric accessory game management phase loaded in step S600-1 is other than "00H". That is, here, it is determined whether the player is currently playing a large winning game or a small winning game. If it is determined that the special electric accessory game management phase is other than "00H", the special game management process is ended, and if it is determined that the special electric accessory game management phase is not other than "00H", step S600 -5.

(Step S600-5)
The main CPU 300a loads the special game special symbol determination flag. In addition, the special game special symbol determination flag is for determining whether the reservation type targeted for special game management processing is special 1 reservation or special 2 reservation, and the special game special symbol determination flag (00H ) indicates special 1 reservation, and the special game special symbol determination flag (01H) indicates special 2 reservation.

(Step S600-7)
The main CPU 300a inverts the special game special symbol determination flag loaded in step S600-5. Here, when the special game special symbol determination flag is "00H", it is inverted to "01H", and when the special game special symbol determination flag is "01H", it is inverted to "00H". Since the initial value of the special game special symbol determination flag is set to "00H", the special game special symbol determination is performed in the first special game management process S600 of the two special game management processes S600 shown in FIG. The flag is set to "01H", the subsequent processing is executed for special 2 pending, the special game special symbol determination flag is set to "00H" in the second special game management process S600, and the subsequent processing is executed for special 1 pending. be done. In other words, special 2 reservations are processed with priority.

(Step S600-9)
The main CPU 300a saves the special game special symbol determination flag that was inverted in step S600-7.

(Step S600-11)
The main CPU 300a loads the special game management phase.

(Step S600-13)
The main CPU 300a selects the special game control module corresponding to the special game management phase loaded in step S600-11 above.

(Step S600-15)
The main CPU 300a calls the special game control module selected in step S600-13 above to start processing.

(Step S600-17)
The main CPU 300a loads a special game timer that manages the control time of the special game, and ends the special game management process.

FIG. 37 is a flowchart illustrating the special symbol change waiting process in the main control board 300 according to the simultaneous rotation reference example. This special symbol change waiting process is executed when the special game management phase is "00H".

(Step S610-1)
The main CPU 300a determines whether the number of special symbol reserved balls targeted for special game management processing (Special 1 pending or Special 2 pending, hereinafter referred to as target pending) is 1 or more. As a result, if it is determined that the number of special symbol reserved balls is 1 or more, the process moves to step S610-3, and if it is determined that the number of special symbol reserved balls is not 1 or more, the special symbol change waiting process is performed. end.

(Step S610-3)
The main CPU 300a is determining a special symbol (hereinafter referred to as a non-target special symbol) based on a reservation that is not subject to special game management processing (Special 2 reservation or Special 1 reservation, hereinafter referred to as non-target reservation). Determine if there is. As a result, if it is determined that the non-target special symbol is being determined, the process moves to step S610-5, and if it is determined that the special symbol based on the non-target special symbol is not being determined, step S610-9 Processing is moved to .

(Step S610-5)
The main CPU 300a determines whether the non-target special symbol is a jackpot symbol. As a result, if it is determined that it is a jackpot symbol, the special symbol change waiting process is ended, and if it is determined that it is not a jackpot symbol, the process moves to step S610-7.

(Step S610-7)
The main CPU 300a determines whether the non-target special symbol is a small winning symbol. As a result, if it is determined that the symbol is a small winning symbol, the special symbol fluctuation waiting process is ended, and if it is determined that it is not a small winning symbol, the process is moved to step S610-9.

(Step S610-9)
The main CPU 300a block-transfers the target reservations stored in the first to fourth storage units of the special figure reservation storage area corresponding to the target reservations to the storage unit with one ordinal number smaller. Specifically, the pending objects stored in the second to fourth storage units are transferred to the first to third storage units. Further, the main RAM 300c is provided with a 0th storage unit to be processed, and the target pending stored in the first storage unit is block transferred to the 0th storage unit. In addition, in this special symbol storage area shift processing, the counter value of the target special symbol reserved ball number counter corresponding to the target reserved is subtracted by "1", and the pending reduction value indicating that the target reserved has been subtracted by "1" is Sets the specified command in the send buffer.

(Step S611)
The main CPU 300a executes a special symbol winning determination process for performing a major lottery. This special symbol hit determination process will be described later.

(Step S610-11)
The main CPU 300a executes a special symbol determination process for determining a special symbol. Here, if the result of the major lottery in step S611 is a jackpot or a small win, the winning symbol random number and reservation type transferred to the 0th storage section are loaded, and the corresponding winning symbol random number determination table or small winning symbol is loaded. Select the random number determination table, extract special symbol determination data, and save the extracted special symbol determination data (type of jackpot symbol). Moreover, when the result of the big winning lottery in step S611 is a loss, special symbol determination data for a loss is saved. Then, after saving the special symbol determination data, a symbol type designation command corresponding to the special symbol determination data is set in the transmission buffer.

(Step S610-13)
The main CPU 300a saves the special symbol stop symbol number corresponding to the special symbol determination data extracted in step S610-11. Note that the first special symbol display 160 and the second special symbol display 162 are each composed of 7 segments, and a number (counter value) is associated with each segment that constitutes the 7 segments. The special symbol stop symbol number determined here indicates the number (counter value) of the segment that will finally light up.

(Step S612)
The main CPU 300a executes a special symbol variation number determination process that determines a variation mode number and a variation pattern number. Details of this special symbol variation number determination process will be described later.

(Step S610-15)
The main CPU 300a loads the variation mode number and variation pattern number determined in step S612 above, and determines variation time 1 and variation time 2 by referring to the variation time determination table. Then, the total time of the determined fluctuation times 1 and 2 is set in the special symbol fluctuation timer.

(Step S610-17)
The main CPU 300a determines whether or not the result of the big winning lottery is a jackpot. If it is a jackpot, the main CPU 300a loads the special symbol determination data saved in step S610-11 above and checks the type of jackpot symbol. do. Then, with reference to the gaming state setting table and the current gaming state, the gaming state, high accuracy number, and time saving number to be set after the end of the big prize game are determined, and the determination results are used as the special symbol probability state preliminary flag and the time saving state preliminary flag. It is saved in the flag, high-accuracy number-cutting reserve counter, and time-saving number-cutting reserve counter. In addition, if the losing symbol is saved, the process moves to the next process without executing the process.

(Step S610-19)
The main CPU 300a executes a process of setting a special symbol display symbol counter in the first special symbol display 160 or the second special symbol display 162 in order to start variable display of special symbols. A counter value is associated with each of the 7 segments that constitute the first special symbol display 160 and the second special symbol display 162, and the segment corresponding to the counter value set in the special symbol display symbol counter is Lighting is controlled. Here, the counter value corresponding to the segment to be lit at the start of the variable display of the special symbol will be set in the special symbol display symbol counter. The special symbol display symbol counter includes a special symbol 1 display symbol counter corresponding to the first special symbol display 160 and a special symbol 2 display symbol counter corresponding to the second special symbol display 162, which are separately provided. Here, a counter value is set in a counter corresponding to the reservation type.

(Step S613)
The main CPU 300a executes the number-of-times management process. Here, processing is performed to end the time saving gaming state according to the number of fluctuations. This number-of-times management process will be described later.

(Step S610-21)
The main CPU 300a sets a number command indicating the remaining number of times (actual remaining number of times) until the high-accuracy number of times and the time-saving number of times become 0 in the transmission buffer.

(Step S610-23)
The main CPU 300a sets a gaming state change designation command indicating the gaming state at the start of the variable display of special symbols in the transmission buffer.

(Step S610-25)
The main CPU 300a updates the special game management phase to "01H" and ends the special symbol change waiting process.

FIG. 38 is a flowchart illustrating the special symbol hit determination process (S611) according to the simultaneous rotation reference example.

(Step S611-1)
The main CPU 300a loads the special symbol probability state flag.

(Step S611-3)
The main CPU 300a loads the registered setting values in the setting value buffer.

(Step S611-5)
The main CPU 300a determines whether the registered setting value loaded in step S611-3 is within the normal range. As a result, if it is determined that the value is within the normal range, the process moves to step S611-11, and if it is determined that the value is not within the normal range, the process moves to step S611-7.

(Step S611-7)
The main CPU 300a sets the gaming machine state flag to 03H (setting abnormal state).

(Step S611-9)
The main CPU 300a sets the setting abnormal state command (subcommand) in the transmission buffer, and ends the special symbol hit determination process. When this setting abnormal state command is sent to the sub control board 330, a notification to the effect that the setting is abnormal is made.

(Step S611-11)
The main CPU 300a refers to the jackpot determination random number determination table corresponding to the information loaded in steps S611-1 and S611-3, and sets the lower limit value and upper limit value for determining a jackpot or small win, respectively.

(Step S611-13)
The main CPU 300a compares the jackpot determination random number transferred to the 0th storage unit with the above lower limit value and upper limit value, and performs a determination process (major lottery) to determine whether or not a jackpot or small win has been won.

(Step S611-15)
The main CPU 300a determines whether the non-target special symbol is a jackpot symbol. As a result, if it is determined that it is a jackpot symbol, the process moves to step S611-17, and if it is determined that it is not a jackpot symbol, the process moves to step S611-21.

(Step S611-17)
The main CPU 300a determines whether the large winning lottery result in step S611-13 is a small win or a loss. As a result, if it is determined that there is a small hit or a loss, the process moves to step S611-21, and if it is determined that there is no small hit or loss, the process moves to step S611-19.

(Step S611-19)
The main CPU 300a changes the winning lottery result in step S611-13 to a loss.

(Step S611-21)
The main CPU 300a sets the result of the determination process in step S611-13 or the result changed in step S611-19 as determination information, and ends the special symbol hit determination process.

FIG. 39 is a flowchart illustrating the special symbol variation number determination process (step S612) in the main control board 300 according to the simultaneous rotation reference example.

(Step S612-1)
The main CPU 300a determines whether the result of the major lottery in step S611 is a big win or a small win. As a result, if it is determined that it is a jackpot or a small win, the process moves to step S612-3, and if it is determined that it is neither a jackpot nor a small hit (a loss), the process moves to step S612-5. Move.

(Step S612-3)
The main CPU 300a sets a reach mode determination random number determination table corresponding to the current gaming state and reservation type.

(Step S612-5)
The main CPU 300a checks the counter value of the special symbol 2 reserved ball number counter when the read reservation type is special 2 reservation, and when the read reservation reservation type is special 1 reservation, Check the counter value of the special symbol 1 reserved balls counter.

(Step S612-7)
The main CPU 300a sets a corresponding reach group determination random number determination table based on the current gaming state, the number of reservations confirmed in step S612-5, and the reservation type. Then, a reach group (group type) is determined based on the set reach group determination random number determination table and the reach group determination random number transferred to the 0th storage unit in step S610-9.

(Step S612-9)
The main CPU 300a sets a reach mode determination random number determination table in case of loss corresponding to the group type determined in step S612-7.

(Step S612-11)
The main CPU 300a selects the variable mode based on the reach mode determination random number determination table set in step S612-3 or step S612-9 and the reach mode determination random number transferred to the 0th storage unit in step S610-9. Determine the number. In addition, here, together with the variation mode number, a variation pattern random number determination table is determined.

(Step S612-13)
The main CPU 300a sets the variable mode command corresponding to the variable mode number determined in step S612-11 above in the transmission buffer.

(Step S612-15)
The main CPU 300a determines a fluctuation pattern number based on the fluctuation pattern random number determination table determined in step S612-11 above and the fluctuation pattern random number transferred to the 0th storage unit in step S610-9 described above.

(Step S612-17)
The main CPU 300a sets the variation pattern command corresponding to the variation pattern number determined in step S612-15 above in the transmission buffer, and ends the special symbol variation number determination process.

FIG. 40 is a flowchart illustrating the number cut management process (step S613) in the main control board 300 according to the simultaneous rotation reference example.

(Step S613-1)
The main CPU 300a determines whether the number of time reductions, that is, the counter value of the time reduction number cut-off counter is greater than zero. As a result, if it is determined that the number of time reductions is greater than 0, the process moves to step S613-3, and if it is determined that the number of time reductions is 0, the number of time reduction management processing is ended.

(Step S613-3)
The main CPU 300a decrements the time saving counter.

(Step S613-5)
The main CPU 300a determines whether the counter value (time saving number) has been updated to 0 in step S613-3. As a result, if it is determined that the number of time reductions is 0, the process moves to step S613-7, and if it is determined that the number of time reductions is not 0, the number of time reduction management processing is ended.

(Step S613-7)
The main CPU 300a sets a time-saving state flag in order to set the normal gaming state to a non-time-saving gaming state. As a result, after the normal gaming state is set to the time-saving gaming state, the normal gaming state is changed to the non-time-saving gaming state at the start of fluctuation when the number of fluctuations reaches the number of time-savings (in this case, 50 or 100 times). The Rukoto. For example, if the state is set to a high probability precursor state, it will be set to the most dominant state.

(Step S613-9)
The main CPU 300a turns on the time saving end flag and ends the number-of-times-cutting management process.

FIG. 41 is a flowchart illustrating special symbol fluctuation processing in the main control board 300 according to the simultaneous rotation reference example.

(Step S620-1)
The main CPU 300a determines whether the suspended flag is on. Although details will be described later, in the simultaneous rotation reference example, small winning symbols may be stopped and displayed on the second special symbol display 162 while the symbols are being displayed in a fluctuating manner on the first special symbol display 160. In this case, when the small winning symbol is stopped and displayed on the second special symbol display 162, a small winning game is executed, but during this time, the subtraction of the variation time of the special symbol on the first special symbol display 160 is interrupted. After the end of the small winning game, the variable display of symbols on the first special symbol display 160 is restarted. The suspended flag is turned on when the small winning symbols are stopped and displayed on the second special symbol display 162 and the first special symbol display 160 is in the process of displaying the symbols in a fluctuating manner. Here, when it is determined that the suspended flag is on, the special symbol variation process is ended, and when it is determined that the suspended flag is not on, the process moves to step S620-3.

(Step S620-3)
The main CPU 300a executes processing to update the special symbol variation base counter. Note that the counter value of the special symbol variation base counter is set so that it makes one round at a predetermined period (for example, 100 ms). Specifically, when the counter value of the special symbol variation base counter is "0", a predetermined counter value (for example, 25) is set, and when the counter value is "1" or more, The counter value is updated to the value obtained by subtracting "1" from the current counter value.

(Step S620-5)
The main CPU 300a determines whether the counter value of the special symbol variation base counter updated in step S620-3 is "0". As a result, if the counter value is "0", the process moves to step S620-7, and if the counter value is not "0", the process moves to step S620-11.

(Step S620-7)
The main CPU 300a performs a special symbol fluctuation timer update process that subtracts a predetermined value from the timer value of the special symbol fluctuation timer set in step S610-15.

(Step S620-9)
The main CPU 300a determines whether the timer value of the special symbol fluctuation timer updated in step S620-7 is "0". As a result, if the timer value is "0", the process moves to step S620-17, and if the timer value is not "0", the process moves to step S620-11.

(Step S620-11)
The main CPU 300a updates a special symbol display timer that measures the lighting time of each segment of the 7 segments that constitute the first special symbol display 160 and the second special symbol display 162. Specifically, when the timer value of the special symbol display timer is "0", a predetermined timer value is set, and when the timer value is "1" or more, the timer value is set from the current timer value. Update the timer value to the value subtracted by "1".

(Step S620-13)
The main CPU 300a determines whether the timer value of the special symbol display timer is "0". As a result, if it is determined that the timer value of the special symbol display timer is "0", the process moves to step S620-15, and if it is determined that the timer value of the special symbol display timer is not "0", the relevant Finish the special symbol changing process.

(Step S620-15)
The main CPU 300a updates the counter value of the special symbol display symbol counter to be updated, and ends the special symbol fluctuation processing. As a result, each segment constituting the 7 segments is sequentially lit at predetermined time intervals.

(Step S620-17)
The main CPU 300a determines whether the non-target special symbol is being displayed in a variable manner. As a result, if it is determined that the non-target special symbol is being displayed in a variable manner, the process moves to step S621, and if it is determined that the non-target special symbol is not being displayed in a variable manner, the process is transferred to step S620-19.

(Step S621)
The main CPU 300a executes a pattern forced stop process. This pattern forced stop processing will be described later using FIG. 42.

(Step S620-19)
The main CPU 300a updates the special game management phase to "02H".

(Step S620-21)
The main CPU 300a saves the special symbol stop symbol number (counter value) determined in the above step S610-13 in the target special symbol display symbol counter. As a result, the determined special symbol is stopped and displayed on the first special symbol display 160 or the second special symbol display 162.

(Step S620-23)
The main CPU 300a sets a special symbol stop designation command indicating that the special symbol is stopped and displayed on the first special symbol display 160 or the second special symbol display 162 in the transmission buffer.

(Step S620-25)
The main CPU 300a sets the special symbol fluctuation stop time, which is the time during which the special symbols are stopped and displayed, in the special game timer, and ends the special symbol fluctuation processing.

FIG. 42 is a flowchart illustrating the pattern forced stop processing (step S621) in the main control board 300 according to the simultaneous rotation reference example.

(Step S621-1)
The main CPU 300a determines whether the special symbol that is being stopped and displayed is a small winning symbol. As a result, if it is determined that it is a small winning symbol, the process moves to step S621-3, and if it is determined that it is not a small winning symbol, the process moves to step S621-11.

(Step S621-3)
The main CPU 300a determines whether the special game special symbol determination flag is 00H, that is, whether the small winning symbol is stopped and displayed on the first special symbol display 160. As a result, if it is determined that the special game special symbol determination flag is 00H, the process moves to step S621-11, and if it is determined that the special game special symbol determination flag is not 00H, the process advances to step S621-5. move.

(Step S621-5)
The main CPU 300a determines whether the (other) special symbol being displayed in a variable manner is a jackpot symbol. As a result, if it is determined that it is a jackpot symbol, the process moves to step S621-11, and if it is determined that it is not a jackpot symbol, the process moves to step S621-7.

(Step S621-7)
The main CPU 300a turns on the suspending flag.

(Step S621-9)
The main CPU 300a executes a variation interruption process to interrupt the variation display of the special symbols, and ends the symbol forced stop process. Here, processing is performed to temporarily save information regarding the remaining time of the variable time and special symbols to a predetermined storage area.

(Step S621-11)
The main CPU 300a causes the first special symbol display 160 or the second special symbol display 162 on which symbols are displayed to be changed to forcibly stop losing symbols, and also to forcibly terminate the remaining variation time. A process of turning on the stop flag is performed, and the pattern forced stop process is ended.

As a result of the above processing, when the small winning symbol is stopped and displayed on the first special symbol display 160, the losing symbol is forcibly stopped and displayed on the second special symbol display 162. In addition, when the small winning symbol is stopped and displayed on the second special symbol display 162, if the jackpot symbol is being displayed in a fluctuating manner in which it is finally stopped and displayed on the first special symbol display 160, the first special symbol is displayed. A losing symbol is forcibly stopped and displayed on the device 160. On the other hand, when a small winning symbol is stopped and displayed on the second special symbol display 162, if a small winning symbol or a losing symbol is being displayed in a fluctuating manner in which it is finally stopped and displayed on the first special symbol display 160, 1 The variable display on the special symbol display 160 will be temporarily interrupted.

FIG. 43 is a flowchart illustrating special symbol stop symbol display processing in the main control board 300 according to the simultaneous rotation reference example.

(Step S630-1)
The main CPU 300a determines whether the timer value of the special game timer set in step S620-25 is not "0". As a result, if it is determined that the timer value of the special game timer is not "0", the special symbol stop symbol display process is terminated, and if it is determined that the timer value of the special game timer is "0", The process moves to step S630-3.

(Step S630-3)
The main CPU 300a determines whether the variable time special stop flag is on. As a result, if it is determined that the variable time special stop flag is on, the process moves to step S630-5, and if it is determined that the variable time special stop flag is not on, the special symbol stop symbol display process is ended. do.

(Step S630-5)
The main CPU 300a confirms the results of the major lottery.

(Step S630-7)
The main CPU 300a determines whether the result of the major lottery is a loss. As a result, if it is determined that the game is a loss, the process moves to step S630-27, and if it is determined that the game is not a loss, the process moves to step S630-9.

(Step S630-9)
The main CPU 300a performs a game state update process to update the game state. Here, when the special symbol being stopped and displayed is a jackpot symbol, the game state is set to the initial state, and when the special symbol being stopped and displayed is a small winning symbol, the process proceeds directly to the next process.

(Step S630-11)
The main CPU 300a sets data in the special electric accessory actuation ram set table according to the determined type of special symbol. Note that the main CPU 300a turns off the variable time special stop flag when it is on.

(Step S630-13)
The main CPU 300a performs a special electric accessory maximum activation count setting process. Specifically, with reference to the data set in step S630-11 above, a predetermined number (counter value corresponding to the type of special symbol = number of rounds) is set as a counter value in the special electric accessory maximum operation number counter. . In addition, this special electric accessory maximum operation number counter indicates the number of rounds that can be executed in the big prize game that will start from now. On the other hand, the main RAM 300c is provided with a special electric accessory continuous operation number counter, and at the start of each round game, by adding "1" to the counter value of the special electric accessory continuous operation number counter, the current The number of round games is managed. Here, with the start of the big winning game, a process of resetting (updating to "0") the counter value of the special electric accessory continuous operation number counter is also executed.

(Step S630-15)
The main CPU 300a refers to the data set in step S630-11 above and saves a predetermined opening time as a timer value in the special electric accessory game timer.

(Step S630-17)
The main CPU 300a sets an opening designation command for transmitting the start of the big prize game to the sub control board 330 in the transmission buffer.

(Step S630-19)
The main CPU 300a updates the special electric accessory game management phase to "01H" when starting a big prize game, and updates the special electric accessory game management phase to "05H" when starting a small winning game. .

(Step S630-21)
The main CPU 300a updates the special game management phase to "00H".

(Step S630-23)
The main CPU 300a determines whether the special electric accessory game management phase updated in step S630-19 is "01H", that is, whether it is a jackpot. As a result, if it is determined that the special electric accessory game management phase is "01H", the process moves to step S630-25, and if it is determined that the special electric accessory game management phase is not "01H", the process is moved to step S630-25. , the process moves to step S630-27.

(Step S630-25)
The main CPU 300a performs a jackpot signal output start process for outputting a jackpot signal from the game information output terminal board 312, and ends the special symbol stop symbol display process. Through this process, a jackpot signal will be output with the start of the big winning game (opening). Although a plurality of signals are provided to be output from the game information output terminal board 312, only a predetermined jackpot signal will be explained here.

(Step S630-27)
The main CPU 300a sets a game state confirmation designation command when a special symbol is confirmed, which indicates the gaming state when the special symbol is confirmed, in the transmission buffer.

(Step S630-29)
The main CPU 300a determines whether the time saving end flag is on. As described above, the time-saving end flag is turned on in step S613-9 of FIG. 40 at the start of fluctuation when changing from the time-saving gaming state to the non-time-saving gaming state. In other words, if the time saving end flag is on here, at the start of the 50th or 100th change in the high probability precursor state, the normal gaming state changes from the time saving gaming state to the non-time saving gaming state due to the time saving exit. This is the case. In other words, here, it is determined that the time saving end flag is on only when the fluctuation at the time of time saving exit ends. If it is determined that the time saving end flag is on, the process moves to step S630-31, and if it is determined that the time saving end flag is not on, the process moves to step S630-35.

(Step S630-31)
The main CPU 300a performs jackpot signal output stop processing to stop the jackpot signal being output from the game information output terminal board 312. That is, the jackpot signal will be output during the big prize game or during the time saving game state.

(Step S630-33)
The main CPU 300a turns off the time saving end flag.

(Step S630-35)
The main CPU 300a updates the special game management phase to "00H" and ends the special symbol stop symbol display process.

FIG. 44 is a flowchart illustrating the special electric accessory game management process (step S700) in the main control board 300 according to the simultaneous play reference example.

(Step S700-1)
The main CPU 300a loads the special electric accessory game management phase.

(Step S700-3)
The main CPU 300a determines whether the special electric accessory game management phase loaded in step S700-1 is "00H". That is, here, it is determined whether a large winning game or a small winning game is currently being played. If it is determined that the special electric accessory game management phase is "00H", the special electric accessory game management process is ended, and if it is determined that the special electric accessory game management phase is not "00H", step The process moves to S700-5.

(Step S700-5)
The main CPU 300a selects the special electric accessory game control module corresponding to the special electric accessory game management phase loaded in step S700-1 above.

(Step S700-7)
The main CPU 300a calls the special electric accessory game control module selected in step S700-5 above to start processing.

(Step S700-9)
The main CPU 300a loads the special electric accessory game timer that manages the control time of the special electric accessory game, and ends the special electric accessory game management process.

FIG. 45 is a flowchart illustrating the pre-processing for opening the big prize opening in the main control board 300 according to the simultaneous rotation reference example. This big prize opening pre-opening process is executed when the special electric accessory game management phase is "01H" or "05H".

(Step S710-1)
The main CPU 300a determines whether the timer value of the special electric accessory game timer set in step S630-15 and the like is not "0". As a result, if it is determined that the timer value of the special electric accessory game timer is not "0", the corresponding big prize opening pre-opening process is finished, and the timer value of the special electric accessory game timer is "0". If it is determined that this is the case, the process moves to step S710-3.

(Step S710-3)
The main CPU 300a updates the counter value of the special electric accessory continuous operation number counter to a value obtained by adding "1" to the current counter value.

(Step S710-5)
The main CPU 300a sets, in the transmission buffer, a big winning opening designation command for transmitting the opening start of the big winning opening (start of the round game) to the sub control board 330.

(Step S711)
The main CPU 300a executes the big winning opening opening/closing switching process. This big winning hole opening/closing switching process will be described later.

(Step S710-7)
The main CPU 300a updates the special electric accessory game management phase to a value obtained by adding 01H to the current value ("02H" or "06H"), and ends the big prize opening pre-opening process.

FIG. 46 is a flowchart illustrating the big winning opening opening/closing switching process (S711) in the main control board 300 according to the simultaneous rotation reference example.

(Step S711-1)
The main CPU 300a determines whether the counter value of the special electric accessory opening/closing switching number counter is the upper limit of the number of special electric accessory opening/closing switching (the number of opening/closing of the big prize opening during one round game). As a result, when it is determined that the counter value is the upper limit value, the corresponding big winning opening opening/closing switching process is ended, and when it is determined that the counter value is not the upper limit value, the process is moved to step S711-3.

(Step S711-3)
The main CPU 300a refers to the data of the special electric accessory activation ram set table and energizes the first grand prize opening solenoid 126c and the second grand prize opening solenoid 128c based on the counter value of the special electric accessory opening/closing switching counter. Solenoid control data for control and time data indicating energization time or energization stop time are extracted.

(Step S711-5)
The main CPU 300a starts energizing the first big winning hole solenoid 126c or the second big winning hole solenoid 128c based on the solenoid control data extracted in the above step S711-3, or controls the main CPU 300a to start energizing the first big winning hole solenoid 126c or the second big winning hole solenoid 128c, or to stop the energization. Execute the prize opening solenoid energization control process. By executing this big winning hole solenoid energization control process, in step S400-33 and step S400-35, the first big winning hole solenoid 126c or the second big winning hole solenoid 128c is controlled to start or stop energizing. It happens.

(Step S711-7)
The main CPU 300a saves the timer value based on the time data extracted in step S711-3 above in the special electric accessory game timer. In addition, the timer value saved in the special electric accessory game timer here becomes the maximum opening time of one time of the big prize opening.

(Step S711-9)
The main CPU 300a determines whether the first big winning hole solenoid 126c or the second big winning hole solenoid 128c is in the energization start state, that is, in the above step S711-5, the first big winning hole solenoid 126c or the second big winning hole solenoid 128c is activated. It is determined whether control processing to start energization has been performed. As a result, if it is determined that the current is in the energization start state, the process moves to step S711-11, and if it is determined that the energization is not in the energization start state, the big winning opening opening/closing switching process is ended.

(Step S711-11)
The main CPU 300a updates the counter value of the special electric accessory opening/closing switching frequency counter to a value obtained by adding "1" to the current counter value, and ends the big winning opening opening/closing switching process.

FIG. 47 is a flowchart illustrating the big winning opening control process in the main control board 300 according to the simultaneous rotation reference example. This big prize opening control process is executed when the special electric accessory game management phase is "02H" or "06H".

(Step S720-1)
The main CPU 300a determines whether the timer value of the special electric accessory game timer saved in step S711-7 is not "0". As a result, if it is determined that the timer value of the special electric accessory game timer is not "0", the process moves to step S720-5, and it is determined that the timer value of the special electric accessory game timer is "0". If so, the process moves to step S720-3.

(Step S720-3)
The main CPU 300a determines whether the counter value of the special electric accessory opening/closing switching frequency counter is the upper limit value of the special electric accessory opening/closing switching frequency. As a result, if it is determined that the counter value is the upper limit value, the process moves to step S720-7, and if it is determined that the counter value is not the upper limit value, the process moves to step S711.

(Step S711)
In step S720-3 above, if it is determined that the counter value of the special electric accessory opening/closing switching frequency counter is not the upper limit value of the number of switching times of special electric accessory opening/closing, the main CPU 300a executes the process of step S711 above. do.

(Step S720-5)
The main CPU 300a determines whether the counter value of the grand prize opening winning ball number counter updated in step S500-9 has reached the specified number, that is, the number of balls that can be won in the grand prize opening is the same as the maximum possible number of prizes in one round. It is determined whether or not a game ball has entered the ball. As a result, if it is determined that the specified number has not been reached, the big winning opening control process is ended, and if it is determined that the specified number has been reached, the process moves to step S720-7.

(Step S720-7)
The main CPU 300a executes a special winning hole closing process necessary to close the special winning hole by stopping the energization of the first big winning hole solenoid 126c or the second big winning hole solenoid 128c. As a result, the grand prize opening will be closed.

(Step S720-9)
The main CPU 300a saves the big winning opening closing effective time (interval time) in the special electric accessory game timer.

(Step S720-11)
The main CPU 300a updates the special electric accessory game management phase to a value obtained by adding 01H to the current value ("03H" or "07H").

(Step S720-13)
The main CPU 300a sets a big winning opening closing designation command indicating that the big winning opening is closed in the transmission buffer, and ends the big winning opening opening control process.

FIG. 48 is a flowchart illustrating the big winning opening closing effective process in the main control board 300 according to the simultaneous rotation reference example. This big prize opening closing validating process is executed when the special electric accessory game management phase is "03H" or "07H".

(Step S730-1)
The main CPU 300a determines whether the timer value of the special electric accessory game timer saved in step S720-9 is not "0". As a result, if it is determined that the timer value of the special electric accessory game timer is not "0", the corresponding big prize opening closing valid processing is terminated, and if the timer value of the special electric accessory game timer is "0". If determined, the process moves to step S730-3.

(Step S730-3)
The main CPU 300a determines whether the counter value of the special electric accessory continuous operation number counter matches the counter value of the special electric accessory maximum operation number counter, that is, whether the preset number of round games has been completed. . As a result, if it is determined that the counter value of the special electric accessory continuous activation number counter matches the counter value of the special electric accessory maximum activation number counter, the process moves to step S730-9, and if it is determined that they do not match, the process moves to step S730-9. Then, the process moves to step S730-5.

(Step S730-5)
The main CPU 300a updates the special electric accessory game management phase to "01H". Note that when the special electric accessory game management phase is 07H, that is, while the small winning game is being controlled, the number of rounds of the small winning game is "1", so be sure to answer YES in step S730-3 above. is determined, and the process does not proceed to that step.

(Step S730-7)
The main CPU 300a saves the predetermined grand prize opening closing time in the special game timer, and ends the big winning opening closing valid processing. As a result, the next round game will start.

(Step S730-9)
The main CPU 300a executes an ending time setting process to save the ending time in the special electric accessory game timer.

(Step S730-11)
The main CPU 300a updates the special electric accessory game management phase to a value obtained by adding 01H to the current value ("04H" or "08H").

(Step S730-13)
The main CPU 300a sets an ending designation command indicating the start of the ending in the transmission buffer, and ends the big winning opening closing validating process.

FIG. 49 is a flowchart illustrating the big winning opening end wait process in the main control board 300 according to the simultaneous rotation reference example. This big winning opening end wait process is executed when the special electric accessory game management phase is "04H" or "08H".

(Step S740-1)
The main CPU 300a determines whether the timer value of the special electric accessory game timer saved in step S730-9 is not "0". As a result, if it is determined that the timer value of the special electric accessory game timer is not "0", the corresponding big winning opening end wait process is terminated, and the timer value of the special electric accessory game timer is "0". If it is determined that this is the case, the process moves to step S740-3.

(Step S740-3)
The main CPU 300a determines whether the special electric accessory game management phase is "08H", that is, whether the small winning game has ended. As a result, if it is determined that the special electric accessory game management phase is "08H", the process is moved to step S740-11, and if it is determined that the special electric accessory game management phase is not "08H", the process is moved to step S740-11. The process moves to step S740-5.

(Step S740-5)
The main CPU 300a executes a state setting process for setting the gaming state after the end of the big prize game. Here, the gaming state, high accuracy number, and time saving number set in the preliminary area in step S610-17 are loaded, and each flag is set and a counter value is set as the gaming state after the big prize game.

(Step S740-7)
The main CPU 300a determines whether the normal gaming state is set to the non-time-saving gaming state in step S740-5. As a result, if it is determined that the non-time-saving gaming state is set, the process moves to step S740-9, and if it is determined that the non-time-saving gaming state is not set, the process moves to step S740-21.

(Step S740-9)
The main CPU 300a performs jackpot signal output stop processing to stop the jackpot signal being output from the game information output terminal board 312. That is, when the most advantageous state is set after the big prize game, the output of the jackpot signal is stopped at the end of the big prize game.

(Step S740-11)
The main CPU 300a determines whether the current gaming state is a high probability precursor state (high probability gaming state and time saving gaming state). As a result, if it is determined that the state is a highly reliable precursor state, the process moves to step S740-13, and if it is determined that the state is not a highly reliable precursor state, the process moves to step S740-21.

(Step S740-13)
The main CPU 300a determines whether the small winning symbol that is stopped and displayed is the special symbol Z1. As a result, if it is determined that it is the special symbol Z1, the process moves to step S740-15, and if it is determined that it is not the special symbol Z1, the process moves to step S740-21.

(Step S740-15)
The main CPU 300a sets a time-saving state flag in order to change the normal gaming state to a non-time-saving gaming state. As a result, when the special symbol Z1 is determined in a high probability precursor state, the gaming state will be changed to the most advantageous state at the end of the small winning game.

(Step S740-17)
The main CPU 300a performs a counter reset process to reset the time saving number counter.

(Step S740-19)
The main CPU 300a performs jackpot signal output stop processing to stop the jackpot signal being output from the game information output terminal board 312. That is, when the special symbol Z1 is won and the small winning game is set to the most dominant state after the small winning game, the output of the jackpot signal is stopped at the end of the small winning game.

(Step S740-21)
The main CPU 300a sets in the transmission buffer a gaming state change designation command for transmitting the gaming state set after the end of the big prize game.

(Step S740-23)
The main CPU 300a sets number commands corresponding to the high accuracy number and time saving number in the transmission buffer.

(Step S740-25)
The main CPU 300a updates the special electric accessory game management phase to "00H" and ends the big winning opening end wait process. As a result, if special 1 hold or special 2 hold is stored, the fluctuating display of symbols will be restarted.

FIG. 50 is a diagram illustrating the normal game management phase according to the simultaneous play reference example. As already explained, in the simultaneous play reference example, the processing related to the normal game triggered by the passage of the game ball to the gate 124 or the entry of the game ball into the normal pattern operation opening 125 is performed stepwise and repeatedly. However, in the main control board 300, each process related to the normal game is managed by the normal game management phase.

As shown in FIG. 50, the main ROM 300b stores a plurality of normal game control modules for controlling the execution of normal games, and a normal game management phase is associated with each of these normal game control modules. . Specifically, when the normal game management phase is "00H", the module for executing the "normal symbol change waiting process" is called, and when the normal game management phase is "01H", A module for executing "normal symbol fluctuation processing" is called, and if the normal game management phase is "02H", a module for executing "normal symbol stop symbol display processing" is called, When the game management phase is "03H", the module for executing the "normal electric accessory prize opening pre-opening process" is called, and when the normal game management phase is "04H", the "normal When the module for executing the "Electric accessory prize opening control process" is called, and the normal game management phase is "05H", the module for executing the "Ordinary electric accessory prize opening opening control process" is called. is called, and when the normal game management phase is "06H", a module for executing the "normal electric accessory winning opening end wait process" is called.

FIG. 51 is a flowchart illustrating the normal game management process (step S800) in the main control board 300 according to the simultaneous play reference example.

(Step S800-1)
The main CPU 300a loads the normal game management phase.

(Step S800-3)
The main CPU 300a selects the normal game control module corresponding to the normal game management phase loaded in step S800-1 above.

(Step S800-5)
The main CPU 300a calls the normal game control module selected in step S800-3 above to start processing.

(Step S800-7)
The main CPU 300a loads a normal game timer that manages control time for normal games.

FIG. 52 is a flowchart illustrating the normal symbol change waiting process in the main control board 300 according to the simultaneous rotation reference example. This normal symbol change waiting process is executed when the normal game management phase is "00H".

(Step S810-1)
The main CPU 300a loads the counter value of the normal symbol pending ball counter and determines whether the counter value is "0", that is, whether the normal symbol pending is "0". As a result, if it is determined that the counter value is "0", the normal symbol change waiting process is ended, and if it is determined that the counter value is not "0", the process is moved to step S810-3.

(Step S810-3)
The main CPU 300a block-transfers the normal pattern reservations (winning determination random numbers) stored in the first to fourth storage sections of the general pattern reservation storage area to the storage section with one ordinal number smaller. Specifically, the ordinary map reservations stored in the second to fourth storage units are transferred to the first to third storage units. Further, the main RAM 300c is provided with a 0th storage section to be processed, and transfers the general map reservation stored in the first storage section to the 0th storage section. In addition, in this normal symbol storage area shift process, the counter value of the normal symbol reserved ball number counter is subtracted by "1", and a regular symbol pending reduction designation command indicating that the regular symbol pending has been subtracted by "1" is transmitted. Set in buffer.

(Step S810-5)
The main CPU 300a loads the winning determination random number transferred to the 0th storage unit, selects the winning determination random number determination table corresponding to the current gaming state, performs a regular symbol lottery, and stores the lottery result. Execute judgment processing.

(Step S810-7)
The main CPU 300a saves the regular symbol stop symbol number corresponding to the result of the regular symbol lottery in step S810-5. In addition, in the simultaneous rotation reference example, the normal symbol display 168 is composed of one LED lamp, and in the case of a win, the normal symbol display 168 is turned on, and in the case of a loss, the normal symbol display 168 is turned off. let The normal symbol stop symbol number determined here indicates whether or not the normal symbol display 168 will finally be lit. For example, in the case of winning, the normal symbol stop symbol number will be "0". is determined, and in the case of a loss, "1" is determined as the normal symbol stop symbol number.

(Step S810-9)
The main CPU 300a confirms the current gaming state, selects and sets the corresponding normal symbol fluctuation time data table.

(Step S810-11)
The main CPU 300a determines the normal symbol fluctuation time based on the winning determination random number transferred to the 0th storage section in step S810-3 and the normal symbol fluctuation time data table set in step S810-9.

(Step S810-13)
The main CPU 300a saves the normal symbol fluctuation time determined in step S810-11 above in the normal game timer.

(Step S810-15)
The main CPU 300a executes a process of setting a normal symbol display symbol counter in order to start variable display of normal symbols on the normal symbol display 168. For example, if the counter value of this normal symbol display symbol counter is set to "0", the normal symbol display 168 is controlled to light up, and if the counter value is set to "1", the normal symbol display is displayed. The lamp 168 is controlled to be turned off. Here, a predetermined counter value is set to the normal symbol display symbol counter at the start of the variable display of the normal symbols.

(Step S810-17)
The main CPU 300a sets, in the transmission buffer, a general pattern reservation designation command indicating the general pattern reservation number stored in the general pattern reservation storage area.

(Step S810-19)
The main CPU 300a sends a normal symbol designation command to the sending buffer based on the normal symbol stop symbol number determined in step S810-7, that is, the symbol type (winning symbol or losing symbol) determined by the normal symbol hit determination process. Set to .

(Step S810-21)
The main CPU 300a updates the normal game management phase to "01H" and ends the normal symbol change waiting process.

FIG. 53 is a flowchart illustrating the process during normal symbol fluctuation in the main control board 300 according to the simultaneous rotation reference example. This normal symbol variation process is executed when the normal game management phase is "01H".

(Step S820-1)
The main CPU 300a determines whether the timer value of the normal game timer saved in step S810-13 is "0". As a result, if the timer value is "0", the process moves to step S820-9, and if the timer value is not "0", the process moves to step S820-3.

(Step S820-3)
The main CPU 300a updates a normal symbol display timer that measures the lighting time and light-off time of the normal symbol display 168. Specifically, when the timer value of the normal symbol display timer is "0", a predetermined timer value is set, and when the timer value is "1" or more, the timer value is set from the current timer value. Update the timer value to the value subtracted by "1".

(Step S820-5)
The main CPU 300a determines whether the timer value of the normal symbol display timer is "0". As a result, if it is determined that the timer value of the normal symbol display timer is "0", the process moves to step S820-7, and if it is determined that the timer value of the normal symbol display timer is not "0", the corresponding Normal symbol fluctuation processing ends.

(Step S820-7)
The main CPU 300a updates the counter value of the normal symbol display symbol counter. Here, if the counter value of the normal symbol display symbol counter is a counter value that indicates that the light of the normal symbol display 168 is off, it is updated to a counter value that indicates that the light of the symbol display 168 is lit, and the counter value that indicates that the symbol display 168 is lit is updated. If it is, the counter value is updated to indicate extinguishment, and the normal symbol fluctuation processing is terminated. As a result, the normal symbol display 168 repeats lighting and extinguishing (flashing) at predetermined time intervals over the normal symbol variation time.

(Step S820-9)
The main CPU 300a saves the normal symbol stop symbol number (counter value) determined in the above step S810-7 in the normal symbol display symbol counter. As a result, the normal symbol display 168 is finally controlled to turn on or off, and the result of the common symbol lottery is notified.

(Step S820-11)
The main CPU 300a sets the normal symbol fluctuation stop time, which is the time during which the normal symbols are stopped and displayed, in the normal game timer.

(Step S820-13)
The main CPU 300a sets a normal pattern stop designation command in the transmission buffer indicating that the stop display of the normal pattern has started.

(Step S820-15)
The main CPU 300a updates the normal game management phase to "02H" and ends the normal symbol variation process.

FIG. 54 is a flowchart illustrating the normal symbol stop symbol display process in the main control board 300 according to the simultaneous rotation reference example. This normal symbol stop symbol display process is executed when the normal game management phase is "02H".

(Step S830-1)
The main CPU 300a determines whether the timer value of the normal game timer set in step S820-11 is not "0". As a result, if it is determined that the timer value of the normal game timer is not "0", the normal symbol stop symbol display process is terminated, and if it is determined that the timer value of the normal game timer is "0", The process moves to step S830-3.

(Step S830-3)
The main CPU 300a confirms the result of the general lottery.

(Step S830-5)
The main CPU 300a determines whether the result of the general drawing lottery is a win. As a result, if it is determined that the game is a win, the process moves to step S830-9, and if it is determined that it is not a win (a loss), the process moves to step S830-7.

(Step S830-7)
The main CPU 300a updates the normal game management phase to "00H" and ends the normal symbol stop symbol display process. As a result, the normal game management process based on the first normal symbol pending is completed, and if the common symbol pending is stored, the process for starting the fluctuating display of the normal symbol based on the next pending is performed. becomes.

(Step S830-9)
The main CPU 300a refers to the data in the opening/closing control pattern table and saves the time before normal power opening as a timer value in the normal game timer.

(Step S830-11)
The main CPU 300a updates the normal game management phase to "03H" and ends the normal symbol stop symbol display process. As a result, the opening/closing control of the first variable starting port 120B is started.

FIG. 55 is a flowchart illustrating the normal electric accessory prize opening pre-opening process in the main control board 300 according to the simultaneous rotation reference example. This normal electric accessory prize opening pre-opening process is executed when the normal game management phase is "03H".

(Step S840-1)
The main CPU 300a determines whether the timer value of the normal game timer set in step S830-9 is not "0". As a result, if it is determined that the timer value of the normal game timer is not "0", the normal electric accessory prize opening pre-opening process is terminated, and it is determined that the timer value of the normal game timer is "0". If so, the process moves to step S841.

(Step S841)
The main CPU 300a executes a normal electric accessory prize opening opening/closing switching process. This normal electric accessory prize opening opening/closing switching process will be described later.

(Step S840-3)
The main CPU 300a updates the normal game management phase to "04H" and ends the normal electric accessory prize opening pre-opening process.

FIG. 56 is a flowchart illustrating the normal electric accessory prize opening opening/closing switching process in the main control board 300 according to the simultaneous rotation reference example.

(Step S841-1)
The main CPU 300a determines that the counter value of the normal electric accessory opening/closing switching frequency counter is the upper limit of the normal electric accessory opening/closing switching frequency (the number of opening/closing times of the movable piece 120b of the first variable starting port 120B during one opening/closing control). Determine if there is. As a result, if it is determined that the counter value is the upper limit value, the normal electric accessory prize opening opening/closing switching process is terminated, and if it is determined that the counter value is not the upper limit value, the process proceeds to step S841-3. Move.

(Step S841-3)
The main CPU 300a refers to the data in the opening/closing control pattern table and generates solenoid control data (energization control data or energization (stop control data), and time data that is the energization time (solenoid energization time) or energization stop time (normal energization closing effective time = rest time) of the normal electric accessory solenoid 120c.

(Step S841-5)
The main CPU 300a starts energizing the normal electric accessory solenoid 120c or starts energizing the normal electric accessory solenoid 120c based on the solenoid control data extracted in step S841-3, or starts energizing the ordinary electric accessory solenoid 120c. Executes physical solenoid energization control processing. By executing this normal electric accessory solenoid energization control process, the normal electric accessory solenoid 120c is controlled to start or stop energizing in step S400-33 and step S400-35.

(Step S841-7)
The main CPU 300a saves the timer value based on the time data extracted in step S841-3 above in the normal game timer. Note that the timer value saved in the normal game timer here becomes the maximum opening time of the first variable starting port 120B once.

(Step S841-9)
The main CPU 300a determines whether the normal electric accessory solenoid 120c has started energization, that is, whether the control process to start energizing the ordinary electric accessory solenoid 120c has been performed in step S841-5. As a result, if it is determined that the current is in the energization start state, the process moves to step S841-11, and if it is determined that the energization is not in the energization start state, the normal electric accessory prize opening opening/closing switching process is ended.

(Step S841-11)
The main CPU 300a updates the counter value of the normal electric accessory opening/closing switching counter to a value obtained by adding "1" to the current counter value.

FIG. 57 is a flowchart illustrating the normal electric accessory prize opening control process in the main control board 300 according to the simultaneous rotation reference example. This normal electric accessory prize opening control process is executed when the normal game management phase is "04H".

(Step S850-1)
The main CPU 300a determines whether the timer value of the normal game timer saved in step S841-7 is not "0". As a result, if it is determined that the timer value of the normal game timer is not "0", the process moves to step S850-5, and if it is determined that the timer value of the normal game timer is "0", step S850 -3.

(Step S850-3)
The main CPU 300a determines whether the counter value of the normal electric accessory opening/closing switching frequency counter is the upper limit of the number of switching times of the normal electric accessory opening/closing. As a result, if it is determined that the counter value is the upper limit value, the process moves to step S850-7, and if it is determined that the counter value is not the upper limit value, the process moves to step S841.

(Step S841)
In step S850-3 above, if it is determined that the counter value of the normal electric accessory opening/closing switching frequency counter is not the upper limit value of the normal electric accessory opening/closing switching frequency, the main CPU 300a executes the process of step S841 above. do.

(Step S850-5)
The main CPU 300a determines whether the counter value of the normal electric accessory winning ball number counter updated in step S530-9 has reached the specified number, that is, whether the first variable starting port 120B is under one opening/closing control. It is determined whether the same number of game balls as the maximum possible winning number of balls have entered. As a result, if it is determined that the specified number has not been reached, the normal electric accessory prize opening control process is ended, and if it is determined that the specified number has been reached, the process moves to step S850-7.

(Step S850-7)
The main CPU 300a executes a normal electric accessory closing process necessary to stop the energization of the ordinary electric accessory solenoid 120c and close the first variable starting port 120B. As a result, the first variable starting port 120B is brought into a closed state.

(Step S850-9)
The main CPU 300a saves the normal power valid state time in the normal game timer.

(Step S850-11)
The main CPU 300a updates the normal game management phase to "05H" and ends the normal electric accessory prize opening control process.

FIG. 58 is a flowchart illustrating the normal electric accessory prize opening closing effective processing in the main control board 300 according to the simultaneous rotation reference example. This normal electric accessory prize opening effective processing is executed when the normal game management phase is "05H".

(Step S860-1)
The main CPU 300a determines whether the timer value of the normal game timer saved in step S850-9 is not "0". As a result, if it is determined that the timer value of the normal game timer is not "0", the normal electric accessory prize opening closing valid processing is terminated, and it is determined that the timer value of the normal game timer is "0". If so, the process moves to step S860-3.

(Step S860-3)
The main CPU 300a saves the normal power end wait time in the normal game timer.

(Step S860-5)
The main CPU 300a updates the normal game management phase to "06H" and ends the normal electric accessory winning opening closing validating process.

FIG. 59 is a flowchart illustrating the normal electric accessory winning opening end wait process in the main control board 300 according to the simultaneous rotation reference example. This normal electric accessory winning hole end wait process is executed when the normal game management phase is "06H".

(Step S870-1)
The main CPU 300a determines whether the timer value of the normal game timer saved in step S860-3 is not "0". As a result, if it is determined that the timer value of the normal game timer is not "0", the normal electric accessory prize opening end wait process is terminated, and it is determined that the timer value of the normal game timer is "0". If so, the process moves to step S870-3.

(Step S870-3)
The main CPU 300a updates the normal game management phase to "00H" and ends the normal electric accessory winning opening end wait process. As a result, if the normal pattern is stored, the variable display of the normal pattern will be restarted. Next, as reference examples of performances, specific performances that can be executed in the above-mentioned type 1 gaming machines, type 2 gaming machines, and simultaneous spinning machines and specific processes related to the performances will be explained.

<Example of production reference>
FIG. 60 is a diagram illustrating an example of a variation performance of a no-reach variation pattern according to a production reference example. As described above, when the major prize lottery is performed on the main control board 300, a variable performance for notifying the results of the major prize lottery is executed during the variable display of the special symbols, that is, over the period of time when the special symbols are varied. In this variable performance, various background images are displayed on the main performance display section 200a, and performance symbols 210a, 210b, and 210c are displayed superimposed on this background image. Note that during the variable performance, along with the image displayed on the main performance display section 200a, sound is output from the audio output device 206, the performance lighting device 204 is controlled to be lit, and the performance accessory device 202 is turned on. Although the movement is controlled, a detailed explanation will be omitted here.

The variable performance according to the reference example of performance is broadly classified into a no-reach variation pattern and a reach variation pattern. In the fluctuating performance of the non-reach fluctuation pattern, a background image (not shown) is displayed on the main performance display section 200a, and performance symbols 210a, 210b, and 210c are superimposed and variably displayed on this background image. For example, as shown in FIG. 60(a), it is assumed that performance symbols 210a, 210b, and 210c are stopped and displayed in a combination indicating that the winning lottery result is a loss. In this state, when a new special symbol is displayed in a variable manner, three production symbols 210a, 210b, and 210c are displayed in a variable manner as shown in FIG. 60(b). (scroll display). Note that the white arrow pointing downward in the figure indicates that the performance symbols 210a, 210b, and 210c are scrolled in the height direction.

Then, as shown in FIG. 60(c), first, the performance pattern 210a is stopped and displayed, and then, as shown in FIG. 60(d), a performance pattern 210c different from the performance pattern 210a is stopped and displayed. Then, at approximately the same timing when the variable display of the special symbol ends and the special symbol stops being displayed on the first special symbol display 160 or the second special symbol display 162, as shown in FIG. 60(e), , the performance symbols 210b are stopped and displayed, and the player is notified of the big prize lottery result based on the final stop display mode of the three performance symbols 210a, 210b, and 210c at this time.

FIG. 61 is a diagram illustrating an example of a variation production of a normal reach variation pattern according to a production reference example. In the performance reference example, reach variation patterns are broadly classified into normal reach variation patterns, developed reach variation patterns, and pseudo-continuous reach variation patterns. In the variation performance of the normal reach variation pattern, similarly to the variation production of the non-reach variation pattern, the variation display of the production symbols 210a, 210b, and 210c starts with the start of the variation display of the special symbol, and as shown in FIG. 61(a). As shown, the production pattern 210a is first stopped and displayed. Thereafter, as shown in FIG. 61(b), the same effect pattern 210c as the effect pattern 210a is stopped and displayed.

In this way, when the same performance symbols 210a and 210c are displayed in the ready-to-reach mode in which they are stopped and displayed in the main performance display section 200a, as shown in FIG. 61(c), the performance symbols 210a and 210c are "Reach" is displayed superimposed on 210a and 210c. It should be noted that there are a plurality of types of ready-to-reach modes, and the same performance symbols 210a and 210c with numbers "1" to "9" written on them are stopped and displayed. Thereafter, as shown in FIG. 61(d), the variable display is continued with the shapes of the performance symbols 210a and 210c being different from before the ready-to-win mode. Then, as shown in FIG. 61(e), finally, a performance pattern 210b different from the performance patterns 210a and 210c is stopped and displayed, and the player is informed that the result of the big prize lottery is a loss.

FIG. 62 is a diagram illustrating an example of a fluctuating performance of the developed reach fluctuation pattern at the time of a loss according to the performance reference example, and FIG. 63 is a diagram illustrating an example of a fluctuating performance of the developed reach fluctuation pattern at the time of a jackpot according to the performance reference example. FIG. As shown in FIGS. 62(a) to 63(a) to 63(d), the variation effect of the developed reach variation pattern is similar to the variation effect of the normal reach variation pattern, in the main effect display section 200a, The effect patterns 210a and 210c are displayed in a ready-to-reach manner, and then a ready-to-reach development effect is executed in which a predetermined developed image (video) is played back and displayed. In this reach development effect, for example, as shown in FIGS. 62(e) and 63(e), a mission is displayed on the main effect display section 200a, and at the same time, as shown in FIGS. 62(f), (g) and 63(e), As shown in f) and (g), images for accomplishing the mission are displayed.

Here, the developed image for the reach development effect is roughly divided into a losing pattern and a jackpot pattern, and in the developing image of the losing pattern, as shown in FIG. 62(h), the image indicating mission failure is finally Then, as shown in FIG. 62(i), the effect symbols 210a, 210b, and 210c are stopped and displayed in a combination that notifies you of a loss. On the other hand, in the development image of the jackpot pattern, as shown in FIG. 63(h), an image indicating the success of the mission is finally displayed, and then, as shown in FIG. 63(i), the production patterns 210a, 210b, 210c is stopped and displayed in combination to notify a jackpot.

In addition, the reach development production includes, for example, as described above, a mission production in which a development image of the mission challenge is displayed, and a battle production in which a development image in which an ally character and an enemy character compete against each other is displayed. It is being The mission production includes a plurality of execution patterns with different mission contents, and the battle production includes a plurality of execution patterns with different characters appearing and fighting methods. In addition, as mentioned above, the execution patterns of mission performances are broadly divided into the jackpot pattern where the mission is completed and the losing pattern where the mission fails, but the execution pattern of the battle performance is also similar. The game can be roughly divided into a jackpot pattern in which the player wins, and a loss pattern in which the friendly character is defeated by the enemy character.

The jackpot pattern and the loss pattern have the same contents until the final stage of the performance, and differ in terms of whether the ally character wins or loses, or whether the mission is accomplished or not. . Therefore, during the reach development performance, the player cannot identify the result of the big winning lottery until the end of the variable performance, and the player is given a sense of expectation of a jackpot.

Note that the jackpot pattern is selected only when the result of the big winning lottery is a jackpot, and the losing pattern is selected only when the result of the big winning lottery is a loss. However, in one fluctuating performance, the reach development performance may be executed twice. In this case, the first reach development performance is performed with a losing pattern, and the second reach development performance is performed with a losing pattern. Or run in a jackpot pattern. Below, the flow of the performance when the reach development performance is executed twice in one fluctuating performance will be explained.

FIG. 64 is a diagram illustrating an example of a variable performance when the reach development performance according to the performance reference example is executed twice. For example, assume that after the performance symbols 210a and 210c are displayed in a ready-to-win mode, a mission performance is executed as shown in FIGS. 64(a) and 64(b). Up to this point, there is no difference from the case where the reach development effect is executed only once in one variable effect, but immediately after it is announced that the mission could not be achieved, as shown in FIG. 64(c). , "REACH UP" is displayed on the main performance display section 200a.

Thereafter, as shown in FIG. 64(d), the main performance display section 200a displays a development image for battle performance, and the second reach development performance is started. This developed image for battle production is a battle between an ally character and an enemy character, and when a jackpot is won, the ally character ultimately wins against the enemy character, as shown in Figure 64(e). , as shown in FIG. 64(f), effect symbols 210a, 210b, and 210c are stopped and displayed in combination to notify a jackpot. On the other hand, in the event of a loss, as shown in FIG. 64(g), the ally character is ultimately defeated by the enemy character, and as shown in FIG. 64(h), the production symbols 210a, 210b, and 210c notify the loss. The combination will stop and display.

FIG. 65 is a diagram illustrating an example of a variation production of a pseudo continuous reach variation pattern according to a production reference example. As shown in FIG. 65(a), as shown in FIG. 65(a), when the fluctuating display of the pseudo-continuous reach fluctuation pattern starts, the fluctuating effect of the pseudo-continuous reach fluctuation pattern starts, and as shown in FIG. 65(b), 210b and 210c are temporarily stopped and displayed in one of a plurality of predetermined pseudo modes. In this pseudo mode, for example, the same performance symbols 210a and 210b and a performance symbol 210c having a number "2" larger than these performance symbols 210a and 210b are temporarily stopped and displayed.

When the performance symbols 210a, 210b, and 210c are temporarily stopped and displayed in a pseudo mode, the variable display of the performance symbols 210a, 210b, and 210c is restarted, as shown in FIG. 65(c). In other words, it can be said that the pseudo mode shows a re-variable display of the production symbols 210a, 210b, and 210c. Thereafter, as shown in FIG. 65(d), the performance symbols 210a, 210b, and 210c are temporarily stopped and displayed again in a pseudo mode.

Then, as shown in FIG. 65(e), when the variable display of the production symbols 210a, 210b, and 210c is resumed, the production symbols 210a, 210c are displayed in a ready-to-reach manner as shown in FIG. 65(f), Thereafter, as shown in FIGS. 65(g) to (i), a reach development performance is executed in the same way as the developed reach variation pattern, and the result of the big winning lottery is notified to the player.

In this way, the variation performance of the pseudo-continuous reach variation pattern is different from the variation production of the developed reach variation pattern until the production symbols 210a and 210c become the reach mode, and after reaching the reach mode, the variation production of the pseudo continuous reach variation pattern is different from the variation production of the developed reach variation pattern. The variable performance will proceed in the same way as the reach variation pattern.

In addition, in the pseudo-continuous reach variation pattern, there are multiple fluctuating display patterns of the production symbols 210a, 210b, and 210c until reaching the ready state, and for each variation display pattern, the production symbols 210a, 210b, and 210c are temporarily stopped. The number of times of display, in other words, the number of times of variable display of the effect symbols 210a, 210b, and 210c are different. This fluctuating display pattern is determined by the fluctuating mode command. The selection ratio of the variable mode commands at the time of winning a jackpot and at the time of losing is set so that the selection ratio (referred to as "degree") becomes high.

Specifically, if the result of the big winning lottery is a jackpot, the selection ratio of variable mode commands with a large number of variable displays is set higher than the selection ratio of variable mode commands with a small number of variable displays, When the result of the big winning lottery is a loss, the selection ratio of the variable mode command with a small number of variable displays is set higher than the selection ratio of the variable mode command with a large number of variable displays.

Moreover, in the main control board 300, the reliability of the pseudo continuous reach variation pattern is set to be higher than the reliability of the developed reach variation pattern. Therefore, reliability is suggested by the number of temporary stop displays (fluctuating displays) of the performance symbols 210a, 210b, and 210c, and the player can expect that the performance symbols 210a, 210b, and 210c will be temporarily stopped displaying (fluctuating displays) more frequently. We will be watching the direction of the performance while hoping that it will be a success.

The above-described execution pattern of the variation effect is determined and executed by the sub-control board 330 based on the variation command determined by the main control board 300. In other words, it can be said that the execution pattern of the variable performance is determined by the main control board 300 and the sub-control board 330 working together.

FIG. 66 is a diagram illustrating a variable performance determination table according to a reference example of performance. FIG. 66(a) shows a first half variable performance determination table, and FIG. 66(b) shows a second half variable performance determination table. As described above, when the major prize lottery is performed in the main control board 300, a variable command is determined based on the result of the major prize lottery, and each determined command is transmitted to the sub control board 330. When the sub-control board 330 receives the variation mode command, it obtains a production random number of 1 from the range of 0 to 249, and refers to the first half variation production determination table to determine the obtained production random number and the received variation mode command. Based on this, the execution pattern of the first half of the variable performance is determined. In addition, upon receiving the variation pattern command, it obtains a production random number of 1 from the range of 0 to 249, and refers to the latter half variation production determination table, and based on the obtained production random number and the received variation pattern command, Determine the execution pattern for the second half of the variable performance. In addition, in FIG. 66, only a part of the first half variable performance determination table and the second half variable performance determination table are extracted and shown.

As shown in FIG. 66, according to the first half variable effect determination table, the selection ratio for the execution pattern of the first half variable effect is set for each variable mode number (variable mode command), and according to the second half variable effect determination table. For example, for each variation pattern number (variation pattern command), the selection ratio for the execution pattern of the latter half of the variation effect is set. Then, by executing the determined execution patterns of the first half and the second half of the variable performance in combination, one variable performance is executed.

For the fluctuation performance of the no-reach fluctuation pattern, "None" is determined as the first half execution pattern, indicating that the first half fluctuation performance is not executed, and "Normal Loss 1" corresponding to the no-reach fluctuation pattern is determined as the second half execution pattern. , "Normal loss 2", "Special loss 1", and "Special loss 2" are determined. For example, when receiving a variation mode command corresponding to a variation mode number of "01H" indicating that the first half of the variation effect is not executed, the sub control board 330 always determines "None" as the first half execution pattern. At this time, the second half of the variable pattern commands that can be received at the same time is set such that only one of "Normal Loss 1", "Normal Loss 2", "Special Loss 1", and "Special Loss 2" is determined. The selection ratio is set in the variable performance determination table. Therefore, "None" is determined as the execution pattern for the first half, and "Normal loss 1", "Normal loss 2", "Special loss 1", and "Special loss 2" are determined as the execution patterns for the second half. The performance execution pattern will be determined to be the above-mentioned non-reach variable pattern.

On the other hand, for the variation effect of the reach variation pattern, a value other than "none" was determined as the execution pattern for the first half, and one of the reach development effects (indicated by development 1 to 5 in the figure) was determined as the execution pattern for the second half. Executed in case. In other words, in the main performance display section 200a, when a fluctuation performance of a reach fluctuation pattern is executed, a fluctuation mode command corresponding to a fluctuation mode number other than fluctuation mode number = 01H is always received, and the development This means that a variation pattern command corresponding to a variation pattern number determined to be one of 1 to 5 has been received.

Here, in FIG. 66(a), in the first half of the execution pattern, "Normal Reach 1", "Normal Reach 2", etc., the performance symbols 210a, 210b, and 210c are in the reach mode among the fluctuation effects of the normal reach variation pattern, respectively. In more detail, it shows the background image and the fluctuating display pattern of the performance symbols 210a, 210b, and 210c displayed on the main performance display section 200a until the reach development performance is started. These image patterns are designed in advance to match the time of the variable display of the special symbol associated with the variable mode number. For example, when "Normal reach 1" is determined, the images shown in FIGS. The image shown in (d) will be displayed on the main effect display section 200a.

In addition, in FIG. 66(a), "pseudo 2a" etc. in the first half execution pattern are displayed on the main performance display section 200a among the fluctuation performances of the pseudo continuous reach variation pattern until the reach development performance is started. This shows the display pattern of the main variation effect image, that is, the execution pattern of the symbol display effect in which the effect symbols 210a, 210b, and 210c are displayed in a variable manner. For example, "Pseudo 2a" is a pseudo continuous reach variation pattern of "Pseudo 2" in which the number of variation displays of the production symbols 210a, 210b, and 210c is 2 times, and the main variation production image is display pattern a. It shows. In addition, "Pseudo 3b" is a pseudo continuous reach variation pattern of "Pseudo 3" in which the number of variation displays of the production symbols 210a, 210b, and 210c is three times, and the main variation production image is display pattern b. It shows.

In addition, in the first half variation production determination table and the second half variation production determination table shown in FIG. 66, the variation production of the no-reach variation pattern and the normal reach variation pattern is executed only when the result of the big winning lottery is a loss. , the selection ratio has been set. In addition, the developed reach variation pattern and the pseudo-continuous reach variation pattern are determined both when you lose and when you hit the jackpot, but the developed reach variation pattern has a higher selection ratio when you lose than the pseudo-continuous reach variation pattern, and when you hit the jackpot. The selection ratio is set low. In this way, by setting the selection ratio for the time of loss and the time of jackpot, the pseudo-continuous reach variation pattern is set to have higher reliability than the developed reach variation pattern.

Furthermore, among the pseudo continuous reach variation patterns, the higher the number of pseudos, the higher the selection ratio when hitting the jackpot, and the lower the selection ratio when losing. is being done.

As described above, the general flow of the variable effect is determined by the variable effect determination table, but at the start of the variable effect, the various element effects that make up the variable effect are determined based on the variable mode command or the variable pattern command. Execution capability and execution pattern are further determined. Here, the element effects include, for example, as described above, the variable display of the effect patterns 210a, 210b, and 210c on the main effect display section 200a, the development image displayed on the main effect display section 200a in the reach development effect, Furthermore, it refers to all performances that constitute a variable performance, such as a performance that moves the performance accessory device 202. In the embodiment, preview performances (suggestive performances) are executed at various timings during the fluctuation performance as element performances that constitute the fluctuation performance.

This preview performance is performed on the main performance display section 200a at the start of a variable performance, when the performance symbols 210a, 210b, and 210c are displayed again in a variable performance of a pseudo continuous reach variation pattern, and further during a reach development performance. This is a performance in which a predetermined image is displayed on the screen or a performance accessory device 202 is moved at a predetermined timing, and whether or not the performance can be performed and the execution pattern are determined for each preview performance. Each preview performance has multiple types of execution patterns, and for each of the multiple types of execution patterns, a selection ratio is set for each variable pattern command and variable mode command, in other words, for each jackpot winning probability. Expected values are set for each execution pattern depending on the selection ratio.

As explained above, when the sub-control board 330 receives a variation command, the execution pattern of the variation production, whether or not each element production can be executed, and the execution pattern are determined, and the variation production is executed during the variation display of the special symbol. The Rukoto. In this way, the fluctuating performance is performed once for one special symbol fluctuating display, but in the embodiment, a fluctuating performance spanning a plurality of special symbol fluctuating displays is also performed.

FIG. 67 is a diagram illustrating an example of a hold display performance according to a reference example of performance. A hold display area 211 is provided at the bottom of the main performance display section 200a. Although not shown in FIGS. 60 to 65, the hold display area 211 is always displayed on the main performance display section 200a even during variable performance or while waiting for a game. During the variable performance, a hold display effect is performed in this hold display area 211. In the hold display performance, the hold display 212a indicating the hold read out to the processing area (0th storage unit) at the time of the big winning lottery, and stored in the first to fourth storage units of the first special figure hold storage area. A first hold display 212b, a second hold display 212c, a third hold display 212d, and a fourth hold display 212e are displayed in the hold display area 211, respectively indicating the hold being held. Note that, hereinafter, the hold display 212a and the first hold display 212b to the fourth hold display 212e are collectively referred to as the hold display 212.

For example, when the special symbol is being displayed in a variable manner and four special 1 pendings are stored in the main RAM 300c, as shown in FIG. 67(a), the corresponding pending display 212a, the first pending display A total of five pending displays 212, 212b to 4th pending display 212e, are displayed in the pending display area 211. Then, from this state, the variable display of the special symbols is finished, the special 1 pending stored in the first storage section is read out to the processing area (0th storage section), a big prize lottery is carried out, and the main RAM 300c When the hold shift process is executed, as shown in FIG. 67(b), the hold display 212a is erased, and the first hold display 212b to fourth hold display 212e are moved one place to the left. . Furthermore, when the next special 1 hold is read out from this state, each hold display 212 is further moved and displayed as shown in FIG. 67(c). In this way, the hold display performance is a performance that notifies the player of the number of Special 1 holds stored in the main RAM 300c.

Further, a plurality of display patterns of the hold display 212 are provided, and the display color is made different for each display pattern. In the main control board 300, when the hold is stored, the performance determination process at the time of acquisition (step S536) is executed, and the fluctuation information determined when the newly stored hold is read out to the 0th storage unit. A prefetch designation command indicating the following is sent to the sub control board 330. When the sub control board 330 receives the prefetch designation command, it determines the display pattern of the hold display 212 corresponding to the newly stored hold based on the received command. At this time, the selection ratio of each display pattern is set for each prefetch designation command, that is, for each variation information determined when the newly stored reservation is read out in the big winning lottery. In other words, since the selection ratio of each display pattern is set depending on whether the jackpot is won or not and the execution pattern of the variable effect, the reliability (expected value) of the jackpot is suggested by the display pattern of the pending display 212. It happens.

FIG. 68(a) is a diagram for explaining the final pending display pattern determination table, and FIG. 68(b) is a diagram for explaining the previous pending display pattern determining table. As described above, in the performance determination process at the time of acquisition in the main control board 300, the sub control board 330 sends a read-ahead designation command indicating the fluctuation mode number and fluctuation pattern number to be determined when a newly stored hold is read out. Send to. In other words, the pre-read designation command is a command that transmits to the sub-control board 330 the variation mode number and variation pattern number that are determined when the reservation is read. According to the final pending display pattern determination table, the selection ratio of the display pattern of the pending display 212 is set for each prefetch designation command (variation pattern number), and when the prefetch designation command is received, the final display pattern of the pending display 212 is set. The display pattern, that is, the final display pattern of the pending display 212a is determined.

According to the final hold display pattern determination table shown in FIG. One of the eight types of display patterns "Rainbow)" is determined. Then, when the final display pattern of the pending display 212a is determined, the display pattern of the pending display 212 displayed before that is determined by referring to the previous pending display pattern determination table shown in FIG. 68(b). Determined by According to this previous pending display pattern determination table, the selection ratio of the display pattern of the pending display 212 to be displayed before the moving display is set for each display pattern of the pending display 212.

For example, in the main control board 300, when a hold is stored in the second storage section of the first special figure hold storage area, the final hold display pattern determination table is referred to, and the final display pattern of the hold display 212a is determined. Suppose that is determined. In this case, next, the display pattern of the first hold display 212b is determined with reference to the previous hold display pattern determination table. At this time, the display pattern of the first pending display 212b is determined based on the final display pattern of the previously determined pending display 212a. For example, when the final display pattern of the relevant hold display 212a is "blue", according to the previous hold display pattern determination table, the display pattern of the first hold display 212b is "blinking" at 200/250. "Blue" is determined with a probability of 50/250.

In this way, when the display pattern of the first hold display 212b is determined, next, the previous hold display pattern determination table is again determined based on the display pattern of the first hold display 212b determined previously. With reference to this, the display pattern of the second hold display 212c is determined.

As described above, when a hold is stored, first, the final display pattern of the hold display 212a is determined, and then, based on the determined final display pattern of the hold display 212a, the first hold is Display patterns are sequentially determined so that the display order is reversed, such as the display pattern of display 212b being determined. According to the previous pending display pattern determination table, the selection ratio is set so that only the display pattern that is the same as the previously determined display pattern of the pending display 212 or has low reliability is determined. has been done.

As described above, in the hold display effect, a plurality of display patterns are provided for the hold display 212 with different expected values for giving a predetermined gaming profit. The pending display 212 may be displayed in one display pattern from when it is first displayed on the main effect display section 200a until it is finally erased, or the display pattern may change during the display period. In some cases.

In the production reference example, the timing at which the display pattern of the hold display 212 changes is when the newly stored special 1 hold (hereinafter also referred to as target hold) is moved to the first hold display 212b to the third hold display 212d. It can be roughly divided into the timing when the target is suspended, and the timing when the target is being changed due to the target being put on hold.

Next, processing in the sub-control board 330 for executing the above-mentioned variation effect will be explained. Note that, in the following, among the processes in the sub-control board 330, a description of processes that are unrelated to the variable performance will be omitted.

(Sub CPU initialization process of sub control board 330)
FIG. 69 is a flowchart illustrating the sub CPU initialization process (S1000) of the sub control board 330 according to the production reference example.

(Step S1000-1)
When the power is turned on, the sub CPU 330a reads a CPU initialization processing program from the sub ROM 330b, and performs initialization and setting processing of flags and the like stored in the sub RAM 330c.

(Step S1000-3)
Next, the sub CPU 330a performs a process of updating each performance random number, and thereafter repeatedly performs the process of step S1000-3 until an interrupt process is performed. Note that a plurality of types of performance random numbers are provided, and here, each performance random number is updated asynchronously.

(Sub-timer interrupt processing of sub-control board 330)
FIG. 70 is a flowchart illustrating the sub-timer interrupt processing (S1100) of the sub-control board 330 according to the production reference example. The sub-control board 330 is provided with a reset clock pulse generation circuit (not shown) that generates clock pulses at a predetermined period (30 times per second). Upon generation of a clock pulse by this reset clock pulse generation circuit, the sub CPU 330a reads the timer interrupt processing program and starts the sub timer interrupt processing.

(Step S1100-1)
The sub CPU 330a saves the register.

(Step S1100-3)
The sub CPU 330a performs processing to permit interrupts.

(Step S1100-5)
The sub CPU 330a performs updating processing of various timer counters used in the sub control board 330. Here, the various timer counters are decremented by 1 each time the sub-timer interrupt processing of the sub-control board 330 is performed, and stop subtraction when they reach 0, unless otherwise specified.

(Step S1200)
The sub CPU 330a analyzes commands stored in the reception buffer of the sub RAM 330c, and performs various processes according to the received commands. In the sub control board 330, when a command is transmitted from the main control board 300, a command reception interrupt process is performed, and the command transmitted from the main control board 300 is stored in a reception buffer. Here, the command stored in the reception buffer by command reception interrupt processing is analyzed.

(Step S1100-7)
The sub CPU 330a performs time schedule management processing that refers to the timetable and executes processing corresponding to the corresponding time stored in the timetable. Here, based on the time data set in the timetable, various flags are turned on and off, or commands are sent to each production device to perform various effects such as variable production and major production. It will control the execution of the performance.

(Step S1100-9)
The sub CPU 330a restores the register and ends the sub timer interrupt process.

FIG. 71 is a flowchart illustrating a prefetch designation command reception process according to a presentation reference example, which is executed when a prefetch designation command is received, among the command analysis processes described above. As described above, the prefetch designation command (prefetch designation variation pattern command) is set in the main control board 300 in the acquisition performance determination process (steps S536-21, S536-25, and S536-27 in FIG. 33). Thereafter, it is transmitted to the sub-control board 330 by sub-command transmission processing (step S100-65 in FIG. 23).

(Step S1210-1)
The sub CPU 330a first analyzes the received prefetch designation command.

(Step S1210-3)
The sub CPU 330a stores the preliminary determination information based on the analysis result of step S1210-1 above. Note that the sub RAM 330c of the sub control board 330 includes a first preliminary determination information storage section corresponding to the first special symbol reservation storage area of the main control board 300, and a second preliminary determination information storage section corresponding to the second special symbol reservation storage area. An information storage section is provided. The first preliminary determination information storage section includes four storage sections, a first storage section to a fourth storage section. The first storage section to the fourth storage section of the first preliminary determination information storage section correspond to the first storage section to the fourth storage section of the first special symbol reservation storage area, respectively. Similarly, the second preliminary determination information storage section includes four storage sections, a first storage section to a fourth storage section, and the first storage section to fourth storage section of these second preliminary determination information storage section are as follows: They respectively correspond to the first storage section to the fourth storage section of the second special figure reservation storage area. Here, among the first to fourth storage sections of the first special symbol reservation storage area or the second special symbol reservation storage area of the main control board 300, the storage section corresponding to the storage section in which the reservation is newly stored is stored. Pre-determination information is stored in .

(Step S1210-5)
The sub CPU 330a performs a final pending display pattern determination process to determine the final display pattern of the pending display 212. Here, based on the received prefetch designation command, the final pending display pattern determination table (FIG. 68(a)) is referred to, and the final display pattern of the pending display 212a is determined and stored.

(Step S1210-7)
The sub CPU 330a derives the number of times to determine the display pattern of the hold display 212, that is, the change timing of the hold display 212, based on the storage unit in which the hold is stored, and updates the previous hold display pattern determination table by the derived number of times. With reference to (FIG. 68(b)), the display pattern of the hold display 212 is determined. Then, the display pattern information of the determined hold display 212 is stored in a predetermined storage section, and the process moves to step S1210-9.

(Step S1210-9)
The sub CPU 330a performs a hold display start process to start displaying the hold display 212 based on the decisions in steps S1210-5 and S1210-7, and ends the prefetch designation command reception process. Thereby, when the hold is stored, the display of the corresponding hold display 212 is started.

FIG. 72 is a flowchart illustrating a variable command receiving process executed when a variable command is received, among the command analysis processes related to the production reference example. As described above, the variation command is set in the main control board 300 in the special symbol variation number determination process (steps S612-13 and S612-17 in FIG. 39), and then in the subcommand transmission process (step S100 in FIG. 23). 65) to the sub control board 330.

(Step S1220-1)
Upon receiving the variation command, the sub CPU 330a first analyzes and stores the received variation pattern command.

(Step S1220-3)
The sub CPU 330a acquires the effect random number (0 to 249) updated in step S1000-3, and determines the execution pattern of the latter half of the variable effect based on the obtained effect random number and the analysis result in step S1220-1. Decide, remember.

(Step S1220-5)
The sub CPU 330a analyzes and stores the received variable mode command.

(Step S1220-7)
The sub CPU 330a acquires the effect random number (0 to 249) updated in step S1000-3, and determines the execution pattern of the first half of the variable effect based on the obtained effect random number and the analysis result in step S1220-5. Decide, remember.

(Step S1220-9)
The sub CPU 330a acquires the performance random number (0 to 249) updated in step S1000-3 above for each preview performance, and based on the acquired performance random number and the analysis results in steps S1220-1 and S1220-5 above. , and determines and stores whether or not each preview performance is to be executed and the execution pattern by referring to each preview performance determination table.

(Step S1220-11)
The sub CPU 330a executes a shift process to shift the preliminary determination information stored in the preliminary determination information storage section. Here, when starting a variable effect based on special 1 suspension, the preliminary determination information stored in the fourth storage section to the second storage section of the first preliminary determination information storage section is replaced with the first preliminary determination information. When shifting to the third storage section to the first storage section of the storage section and starting a variable performance based on special 2 suspension, the information is stored in the fourth storage section to the second storage section of the second preliminary determination information storage section. The pre-determination information stored in the pre-determination information is shifted to the third storage section to the first storage section of the second pre-determination information storage section, respectively.

(Step S1220-13)
The sub CPU 330a performs a hold display shift process to move and display the hold display 212. Moreover, here, when the display pattern of the hold display 212 changes, execution data for changing the display pattern at a predetermined timing is set.

(Step S1220-15)
The sub CPU 330a sets the time data of the time table based on the decisions made in each of the above steps, and ends the variable command reception process. In addition, based on the timetable set here, in step S1100-7, processing for displaying images for variable effects on the main effect display section 200a, audio output processing, lighting control processing for the effect lighting device 204, etc. Performance execution control will be performed.

<Slot machine 400>
As shown in the external views of FIGS. 73 and 74, the slot machine 400 as a gaming machine includes a casing 402 with an open front, and a front surface that is rotatably arranged vertically in one end of the casing 402. An upper door 404 and a lower front door 406 are provided. A colorless and transparent pattern display window 408 made of a glass plate, a transparent resin plate, etc. is provided at approximately the center of the lower part of the front upper door 404, and at a position corresponding to the pattern display window 408 in the housing 402. , three reels 410 (left reel 410a, middle reel 410b, right reel 410c) are provided so as to be rotatable independently. On the outer peripheral surfaces of the left reel 410a, middle reel 410b, and right reel 410c, multiple types of symbols are arranged in each area divided into 20 equal parts, as shown in the symbol arrangement in FIG. 75(a). Through the symbol display window 408, the player can visually recognize three consecutive symbols on the left reel 410a, middle reel 410b, and right reel 410c, located in the upper, middle, and lower rows, for a total of nine symbols.

An operation unit installation base 412 is formed on the upper part of the lower front door 406, and the operation unit installation base 412 is provided with a medal insertion unit 414, a bet switch 416, a start switch 418, a stop switch 420, a performance switch 422, etc. There is. The medal insertion unit 414 accepts the insertion of medals as gaming value through the medal insertion slot 414a. The bet switch 416 inserts (bets) a specified number of medals required for one game among the medals electrically stored (hereinafter simply referred to as credits) inside the slot machine 400.

The start switch 418 is constituted by a lever capable of detecting a tilting operation, for example, and detects a game start operation by a player. The stop switches 420 (stop switch 420a, stop switch 420b, stop switch 420c) are provided corresponding to the left reel 410a, middle reel 410b, and right reel 410c, respectively, and detect the player's stop operation. Note that when the stop switch 420 can be stopped, the first stop operation by the player on any one of the stop switches 420a, 420b, and 420c is called a first stop, and the first stop is called a first stop. After that, operating one of the two stop switches 420 that has not been stopped is called a second stop, and after the second stop, operating the last remaining stop switch 420 is called a third stop. . The production switch 422 is composed of, for example, a press switch and a jog dial switch rotatably arranged around the press switch, and detects the player's press operation or rotation operation.

A liquid crystal display section 424 is provided approximately in the upper center of the front upper door 404 to display various images associated with the performance. In addition, on the upper part and on the left and right sides of the front upper door 404, display lamps 426 made of, for example, high-intensity light emitting diodes (LEDs) are provided. In addition, speakers 428 are provided at the left and right positions of the liquid crystal display section 424 on the back surface of the upper front door 404 and at the left and right positions on the back surface of the lower front door 406, for providing auditory effects such as sound effects and musical sounds.

The operation unit installation base 412 is provided with a main credit display section 430 and a main payout display section 432. Furthermore, a sub-credit display section 434 and a sub-payout display section 436 are provided between the symbol display window 408 and the operation section installation stand 412. The main credit display section 430 and sub-credit display section 434 display the number of credited medals (credit number), and the main payout display section 432 and sub-payout display section 436 display the number of medals to be paid out. .

A medal dispensing device (medal hopper) 442 for dispensing medals from a medal discharging port 440a is provided below the reel 410 in the housing 402. Further, a receiving tray portion 440 for storing medals dispensed from the medal ejection port 440a is provided at the lower front of the lower front door 406. Further, a power switch 444 is provided inside the housing 402. The power switch 444 is operated by an administrator who manages the slot machine 400 and is used to switch between two states: a power-off state and a power-on state.

Further, inside the housing 402, a setting door key and a setting change switch (not shown) are provided on a main control board 500, which will be described later. In the slot machine 400, when the power is turned on via the power switch 444 with a predetermined key (operation key) inserted into the setting door key and rotated from the OFF position to the ON position, the slot machine 400 shifts to the setting change mode. , the setting value can be changed (also simply referred to as setting change). The set value is a stepwise representation of the player's advantage (mechanical split), and is expressed in 6 levels from 1 to 6, for example. Generally, the larger the set value, the more advantageous the game is as a whole. It is set to be high (expected number of acquisitions is high). Then, each time the setting change switch is pressed in a state where settings can be changed, the setting value is incremented by 1, and the setting value is changed to one of the six setting values, for example, and the start switch 418 is operated. Then, the setting value is determined, and by returning the setting door key to its original position (OFF position), the setting change mode ends and the game becomes possible. Note that the settings can only be changed for a certain period of time after the power switch 444 is operated and the power is turned on.

In the slot machine 400, when a game can be started and a specified number of medals are bet, the active line A becomes active and the operation on the start switch 418 becomes active. Here, bets can be placed in two cases: by inserting credited medals through the operation of the bet switch 416, by inserting medals through the medal inserter 414, and by placing a replay combination, which will be described in detail later, on the active line A. This includes any case where medals are automatically inserted based on the situation. Further, the active line A is a line for determining whether or not the winning combination is won, and in this embodiment, there is only one active line A. As shown in FIG. 75(b), the active line A is the middle row of the left reel 410a, the middle row of the middle reel 410b, and It is set as a line connecting the positions corresponding to the symbols that stop at the top of the right reel 410c. The invalid line is used to determine the winning combination of winning combinations by displaying other symbol combinations that will make it easier to understand the winning combination when it is difficult to understand the winning combination using only the symbol combinations displayed on the active line A. In this embodiment, five invalid lines B1, B2, B3, C1, and C2 shown in FIG. 75(b) are assumed.

Then, when the start switch 418 is operated by the player, the game is started, the left reel 410a, the middle reel 410b, and the right reel 410c are rotated, and a winning type lottery and the like are executed. Thereafter, the corresponding left reel 410a, middle reel 410b, and right reel 410c are respectively stopped in accordance with the operation of the stop switches 420a, 420b, and 420c. Then, if a winning combination that can receive a medal payout is won based on the lottery result of the winning type lottery and the combination of symbols displayed on the active line A, a medal payout will be executed, and the winning type that can receive a medal payout will be executed. If the player does not win or wins but does not win, the game ends when the left reel 410a, middle reel 410b, and right reel 410c all stop.

In the present embodiment, the above-mentioned one game includes the insertion of medals through the medal insertion unit 414, the insertion of credited medals through the operation of the bet switch 416, or the replay combination displayed on the active line A. After one of the automatic medal insertions based on this is performed, the rotation of the left reel 410a, middle reel 410b, and right reel 410c is controlled in response to the player's operation of the start switch 418, and a winning type lottery is executed. The left reel 410a, middle reel 410b, and right reel corresponding to the operated stop switches 420a, 420b, and 420c are then displayed in accordance with the lottery results of the winning type lottery and the operation of the plurality of stop switches 420a, 420b, and 420c by the player. 410c is controlled to stop, and when a winning combination that can receive a payout of medals is won, it refers to the game until the payout of the medals is executed. In addition, if the winning type for which medals can be paid out is not won, or if the player wins but does not win, one game ends when the left reel 410a, middle reel 410b, and right reel 410c all stop. However, the start of one game may be read as the operation of the start switch 418 by the player instead of the above-described insertion of medals or winning of a replay combination. Further, the number of times such one game is repeated is defined as the number of games.

FIG. 76 is a block diagram showing a schematic electrical configuration of the slot machine 400. As shown in FIG. 76, the slot machine 400 includes a main control board 500 (main control unit) that controls the progress of the game, and a sub-control board 502 (sub-control unit) that controls the effects according to the progress of the game. A control board is provided that includes a control board. Furthermore, transmission of electrical signals between the main control board 500 and the sub-control board 502 is limited to only one direction, from the main control board 500 to the sub-control board 502, from the viewpoint of fraud prevention and the like.

(Main control board 500)
The main control board 500 has a semiconductor integrated circuit including a main CPU 500a as a central processing unit, a main ROM 500b storing programs etc., a main RAM 500c functioning as a work area, etc., and controls the entire slot machine 400 in an integrated manner. . Note that even if the power is turned off, the data in the main RAM 500c is retained without being erased unless the settings are changed and the RAM is cleared.

The main control board 500 also includes an initialization means 600, a bet means 602, a winning type lottery means 604, and a reel control means, which function when the main CPU 500a cooperates with the main RAM 500c based on a program stored in the main ROM 500b. 606, determination means 608, payout control means 610, game state control means 612, performance state control means 614, command transmission means 616, and other functional units.

The main control board 500 receives various detection signals from an inserted medal detection unit 414b that detects the insertion of medals into the medal slot 414a, a bet switch 416, a start switch 418, and stop switches 420a, 420b, and 420c. Based on the received detection signal, the main CPU 500a executes various processes.

Initialization means 600 executes initialization processing in main control board 500. The betting means 602 bets medals to be used in games. Based on the operation of the start switch 418, the winning type lottery means 604 performs a winning type lottery to determine the validity of the winning combination, more specifically, the validity of the winning type including the winning combination, as will be described in detail later.

The reel control means 606 controls the rotation of the left reel 410a, the middle reel 410b, and the right reel 410c in response to the operation of the start switch 418, and controls the rotation of the left reel 410a, middle reel 410b, and right reel 410c, respectively. In response to the operation of stop switches 420a, 420b, and 420c, the corresponding left reel 410a, middle reel 410b, and right reel 410c are controlled to stop. In addition, the reel control means 606 activates the operation of the stop switches 420a, 420b, and 420c in the previous game in response to the operation of the start switch 418, and then displays the lottery results of the winning type lottery by the player. The time until the operation of the stop switches 420a, 420b, 420c is enabled (invalidated by the completion of the operation of the stop switches 420a, 420b, 420c in the previous game) is extended from the specified time, and during that time, the reel 410a , 410b, and 410c may be rotated in various ways (freeze effect). Reel effects include not enabling a switch that should have been enabled for a predetermined period of time, suspending a process that should have been executed for a predetermined period of time, or causing signals from a switch that should have been sent or received to be sent or received for a predetermined period of time. This can be achieved by not having it.

Further, a reel drive control section 450 is connected to the main control board 500. The reel drive control unit 450 drives the stepping motor 452 based on rotation start signals for the left reel 410a, middle reel 410b, and right reel 410c transmitted from the reel control means 606 in response to the operation signal of the start switch 418. do. In addition, the reel drive control unit 450 detects stop signals for each of the left reel 410a, the middle reel 410b, and the right reel 410c and the rotational position detection circuit 454, which are transmitted from the reel control means 606 in response to the operation signal of the stop switch 420. Based on the signal, driving of the stepping motor 452 is stopped.

The determining means 608 determines whether the symbol combination corresponding to the winning combination has been displayed on the active line A. Here, the display of a symbol combination corresponding to a winning combination on the active line A may simply be called winning. The payout control means 610 pays out medals in the number (value amount) corresponding to the winning combination based on the symbol combination corresponding to the winning combination being displayed on the active line A (winning). Further, a medal payout device 442 is connected to the main control board 500, and the payout control means 610 dispenses the medals while counting the number of medals to be paid out.

The game state control means 612 refers to the result of the winning type lottery and the determination result of the determination means 608, and shifts the game state to one of a plurality of types of game states. Further, the performance state control means 614 refers to the result of the winning type lottery, the determination result of the determination means 608, and the transition information of the game state, and shifts the performance state to one of a plurality of types of performance states.

The command transmitting means 616 sends commands related to games associated with the operations of the betting means 602, winning type lottery means 604, reel control means 606, determination means 608, payout control means 610, game state control means 612, performance state control means 614, etc. are sequentially determined, and the determined commands are sequentially transmitted to the sub-control board 502.

Further, the main control board 500 is provided with a random number generator (random number generation means) 500d. The random number generator 500d sequentially increments the count value, loops it within a predetermined numerical range, and obtains a random number by extracting the count value at a predetermined time point. The random numbers generated by the random number generator 500d of the main control board 500 (hereinafter referred to as winning type lottery random numbers) are used to determine the gaming profit to be given to the player, for example, by the winning type lottery means 604 to determine the winning type. .

(Sub control board 502)
Further, like the main control board 500, the sub control board 502 has various semiconductor integrated circuits including a sub CPU 502a which is a central processing unit, a sub ROM 502b storing programs etc., and a sub RAM 502c which functions as a work area. , particularly controls the presentation based on commands from the main control board 500. Further, like the main RAM 500c, the sub RAM 502c is also connected to a backup power source (not shown), and even if the power is cut off, the data is retained without being erased. Note that the sub control board 502 is also provided with a random number generator (random number generation means) 502d, like the main control board 500, and the random numbers (hereinafter referred to as performance lottery random numbers) generated by the random number generator 502d are generated by the main control board 502. It is used to determine the mode of presentation.

In addition, in the sub control board 502, the sub CPU 502a operates an initialization determining means 630, a command receiving means 632, an effect controlling means 634, etc., which function by cooperating with the sub RAM 502c based on the program stored in the sub ROM 502b. It has a functional part.

Initialization determining means 630 executes initialization processing in sub control board 502. The command receiving means 632 receives commands from other control boards, such as the main control board 500, and processes the commands. The performance control means 634 receives the detection signal from the performance switch 422, and determines the performance of the game to be performed on each device of the liquid crystal display section 424, the speaker 428, and the performance lamp 426 based on the received command. Specifically, the production control means 634 controls the image data displayed on the liquid crystal display section 424 and the electricity for production through illumination devices such as the production lamp 426, the sub-credit display section 434, and the sub-payout display section 436. Decoration data is determined, and at the same time, audio data constituting the audio to be output from the speaker 428 is determined. Then, the performance control means 634 executes the determined game performance. Note that the production also includes auxiliary production. In the winning type lottery, when a selected winning type in which a correct winning combination (a specific winning combination) and an incorrect winning combination overlap is won, the correct answer of the stop switches 420a, 420b, and 420c, which is the winning condition for the correct winning combination, is used. This is a performance that notifies you of the operation mode. With this auxiliary performance, the player can easily display the symbol combination corresponding to the correct winning combination on the active line A. A performance state in which such an auxiliary performance is executed is called an AT (assist time) performance state. In addition, a so-called ART gaming state may be used in which an AT performance state and an RT (replay time) gaming state in which the probability of winning a replay combination is high are proceeded in parallel.

In the following, notifications managed by boards other than the main control board 500, including the sub-control board 502, such as the liquid crystal display section 424, the production lamp 426, the speaker 428, the sub-credit display section 434, and the sub-payout display section 436, will be described. The means may be referred to as other notification means. On the other hand, notification means managed by the main control board 500, such as the main credit display section 430 and the main payout display section 432, may be referred to as main notification means (instruction monitor). Further, the main notification means and other notification means capable of executing the auxiliary performance may be collectively referred to as auxiliary performance execution means. The performance state control means 614 causes the auxiliary performance execution means to execute the auxiliary performance in the AT performance state.

(Table used in main control board 500)
FIG. 77 is an explanatory diagram for explaining the winning combination, and FIGS. 78 and 79 are explanatory diagrams for explaining the winning type lottery table.

In the slot machine 400, as will be described in detail later, a plurality of types of gaming states and performance states are provided, and the gaming state and performance state are changed according to the progress of the game. In the main control board 500, a plurality of winning type lottery tables and the like corresponding to gaming states managed and controlled by the gaming state control means 612 are stored in the main ROM 500b. The winning type lottery means 604 draws a corresponding winning type lottery table into the main ROM 500b according to the current setting value (which shows the ease of obtaining a gaming profit in stages) stored in the main RAM 500c and the current gaming state. Based on the extracted winning type lottery table, it is determined which winning type lottery random number acquired in response to the operation signal of the start switch 418 corresponds to which winning type in the winning type lottery table.

Here, the winning combinations constituting the winning types extracted in the winning type lottery table include a replay winning combination, a minor winning combination, and a bonus winning combination. The replay combination is a combination that allows the player to play the game again without making a new bet for medals when a symbol combination corresponding to the replay combination is displayed on the active line A. A small winning combination is a winning combination in which a symbol combination corresponding to the small winning combination is displayed on the active line A, so that a predetermined number of medals can be paid out according to the symbol combination. In addition, for a bonus role, the symbol combination corresponding to the bonus role is displayed on the active line A, thereby changing the gaming state managed by the gaming state control means 612 to a bonus gaming state (a gaming state during RBB operation, which will be described later). This is a role that can be transitioned to.

As for the winning combinations in this embodiment, as shown in FIG. 77, winning combinations "Replay 1" to "Replay 7" are provided as replay combinations. In addition, as small roles, winning roles "Small Role 1" to "Small Role 39" are provided. In addition, a winning combination "RBB" is provided as a bonus combination. In FIG. 77, one or more symbols constituting each winning combination are associated with each of the left reel 410a, middle reel 410b, and right reel 410c.

Here, in this embodiment, when the stop switch 420 is operated by the player, if the symbols constituting the symbol combination corresponding to the winning combination that can be won are on the active line A, the reel control means In step 606, stop control is performed so that the symbol stops on the active line A. In addition, when the stop switch 420 is operated, the symbols constituting the symbol combination corresponding to the winning combination that can be won are not on the active line A, but four symbols in the opposite direction to the rotation direction of the reel 410 are displayed. If it is within the range (draw-in range) corresponding to the winning combination, the reel control means 606 controls the number of symbols that are apart from each other to become the number of sliding symbols, and activates the symbols constituting the symbol combination corresponding to the winning combination. Stop control is performed so that the rotation is maintained for the number of sliding frames so as to be drawn onto line A, and then stopped. In addition, if there are multiple symbols on the reels 410 that correspond to winning combinations that can be won, and all of them are within the pull-in range of the reels 410, any symbol is selected from the active line A according to a predetermined priority order. It is determined whether to draw the symbol upward, and stop control is performed so that the rotation is maintained for the number of sliding pieces so as to draw the prioritized symbol onto the active line A and then stopped. Note that when the stop switch 420 is pressed and a symbol that constitutes a symbol combination corresponding to a winning combination other than a winning combination that can be won is on the active line A, the reel control means 606 controls the symbol combination to A so-called kicking process is also executed in parallel to prevent the line from stopping on the effective line A. Furthermore, as will be described later, if the winning combination included in the winning type has an operation mode (operation order or operation timing) set as a winning condition, the reel control means 606 controls the winning combination according to the player's operation mode. Stop control is performed so that the symbol combination corresponding to the symbol combination can be displayed on the active line A.

For example, the symbols forming symbol combinations corresponding to the winning combinations "Replay 1" to "Replay 4", the winning combinations "Small Role 1" to "Small Role 6", and "Small Role 35" to "Small Role 39" are arranged on each reel 410 so that they can always be displayed on the active line A by the above-mentioned stop control. Such a winning combination may be expressed as PB=1. On the other hand, for example, the symbols constituting the symbol combinations corresponding to the winning combinations "Replay 5" to "Replay 7", the winning combinations "Small combination 7" to "Small combination 34", and the winning combination "RBB" are displayed on each reel 410. Due to the above-mentioned stop control, since the images are not necessarily arranged so as to be displayable on the effective line A, so-called dropouts may occur. Such a winning combination may be expressed as PB≠1.

As shown in FIGS. 78 and 79, in the winning type lottery table, multiple winning areas are divided, and the winning types that are subject to lottery differ depending on each game state, and the presence or absence of non-winning (loss) differs depending on each game state. or In FIGS. 78 and 79, the winning areas ( Although the winning type (winning type) is represented by "◎" or "○", in reality, a winning type lottery table corresponding to each of a plurality of gaming states is stored in the main ROM 500b. In addition, "◎" indicates that it is an advantageous section lottery possible winning type where a lottery to move to an advantageous section can be held, and "○" is a non-advantageous section lottery where it is impossible to conduct a lottery to transfer to an advantageous section. Indicates that it is a winning type.

In the winning type lottery table, each divided winning area is associated with a predetermined number (winning range value) that is a numerical value indicating the winning range, and the winning type. The total number of winning type lottery random numbers (65536) is obtained by summing up the numbers placed in the winning areas. Therefore, the probability that each winning type is determined is the value obtained by dividing the number associated with the winning area by the total number of winning type lottery random numbers. The winning type lottery means 604 sequentially acquires numbers from among the winning areas in the winning type lottery table with the highest number based on the gaming state at that time, and uses the numbers as winning type lottery random numbers. When the value after subtraction becomes less than 0, the winning type associated with the winning area at that time is determined as the lottery result of the winning type lottery. In addition, if the numbers of all the winning areas of winning area 1 and above are subtracted from the winning type lottery random number, and the value after subtraction is 0 or more, the winning type of winning area 0 is "lose". This is the lottery result.

Here, we will supplement the winning combination "RBB" that constitutes the winning type "RBB". The predetermined type 1 special accessory RB is an accessory that increases the number of combinations of symbols related to winnings for each specified number, or increases the probability that a conditional device related to winnings for each specified number will operate, and is predetermined. It is said to be able to operate when the game is played and continue to operate until the result of the game is obtained not more than 12 times. Here, the condition device is a device whose operation is a necessary condition for displaying a combination of symbols related to winning, replay, accessory, or operation of the accessory continuous operation device, A winning flag is a flag that is activated when a player wins a computer-based lottery held in a gaming machine. And, the accessory continuous activation device (winning combination "RBB") related to the first type special accessory that constitutes the winning type "RBB" is a device that can continuously operate the first type special accessory RB. This refers to a device that operates when a specific combination of symbols is displayed and ends the operation in a predetermined case.

According to the winning type lottery table in FIG. 78, for example, winning area 0 is associated with the winning type "Lose", and if you win in this winning type, the symbol corresponding to any of the winning combinations shown in FIG. The combination is also not displayed on the active line A, and no medals are paid out. However, as will be described later, if the RBB internal winning flag is carried over to the next game, the symbol combination corresponding to the winning combination "RBB" may be displayed on the active line A due to the winning type "Lose". It becomes possible.

Furthermore, the winning area 1 is associated with the winning type "Small role ALL" which includes the winning roles "Small role 1" to "Small role 39" overlappingly, and the winning area 2 is associated with the winning type "Small role ALL" which includes the winning role "Small role 1" to "Small role 39" overlappingly. The winning type "1 piece ALLA" which includes the winning combinations "Small prize 11" to "Small prize 39" is associated with the winning type "1 piece ALLA", and the winning combinations "Small prize 12" to "Small prize 27" are included in the winning area 3. The winning type "1 ticket ALLB" which is included twice is associated. In addition, the winning area 4 is associated with the winning type "1 Choice 1" which includes the winning combinations "Small Win 12" and "Small Win 20", and the winning area 5 is associated with the winning combination "Small Win 12" and "Small Win 20". The winning type ``Choice 1 2'' which includes duplicate winning combinations ``Win 13'' and ``Small Win 21'' is associated with the winning type ``Choice 1 2'', which includes duplicate winning combinations ``Small Win 14'' and ``Small Win 22'' in winning area 6. In the winning area 7, there is a winning type "1 choice 4" which includes the winning combinations "Small role 15" and "Small role 23" in duplicate. are associated. In addition, the winning area 8 is associated with the winning type "weak cherry" which includes the winning combinations "small winning combination 35" and "small winning combination 36", and the winning area 9 is associated with the winning winning combination "small winning combination 35" and "small winning combination 36". ” to “Small win 39” are associated with the winning type “Strong Cherry” which is duplicated, and in the winning area 10, the winning winnings “Small win 7”, “Small win 8”, and “Small win 11” are included. The winning type "Watermelon A" which is duplicated is associated with the winning type "Watermelon A", and the winning type "Watermelon B" which is duplicated with the winning combinations "Small Win 7" to "Small Win 10" is associated with the winning area 11. The winning area 12 is associated with the winning type "Strong Bell" which includes the winning winning combinations "Small winning combination 1", "Small winning combination 3", and "Small winning winning combination 5" overlappingly. In addition, the winning area 13 is associated with the winning type "Common Bell A" which includes the winning combinations "Small Role 1" to "Small Role 6" overlappingly, and the winning area 14 is associated with the winning type "Common Bell A" that includes the winning combinations "Small Role 1" to "Small Role 6". 1" to "Small win 6" and "Small win 11" are associated with the winning type "Common Bell B."

In addition, in winning areas 15 to 26, correct winning hands with a payout number of 11 coins (winning winning hands “Small Winner 1” to “Small Winner 6”) and incorrect winning hands with a payout number of 1 coin (winning hands “Small Winner 6”) with a payout number of 1 coin are shown. Selected winning types (winning types ``batting order bell 1A'' to ``batting order bell 6A'', ``batting order bell 1B'' to ``batting order bell 6B'') that include redundant combinations of ``batting order bell 12'' to ``minor role 34'') are associated with each other. It is being

Furthermore, according to the winning type lottery table in FIG. 79, winning areas 27 to 39 include winning types "Symbol Replay A1" to "Symbol Replay A7" in which the winning combinations "Replay 1" to "Replay 7" are duplicated. ", "Symbol Replay B1" to "Symbol Replay B6" are associated with each other. Furthermore, the winning area 40 is associated with a winning type "normal replay" which includes the winning combinations "replay 1" and "replay 2" in duplicate.

Furthermore, the winning areas 41 to 46 are associated with winning types "RBB1" to "RBB6" in which the winning combination "RBB" is included alone or in combination with other small winning combinations.

If you win a winning type that includes multiple winning combinations, the winning conditions regarding which symbol combination corresponding to the winning combination will be preferentially displayed on the active line A, such as stop The order in which the switches 420a, 420b, and 420c are operated is set.

In the following description, the operation of the stop switches 420a, 420b, and 420c that stop the reels in the order of the left reel 410a, the middle reel 410b, and the right reel 410c will be referred to as "batting order 1", and The operation of stop switches 420a, 420b, and 420c that stop the reels in order is called "batting order 2," and the operation of stop switches 420a, 420b, and 420c that stops the reels in order of middle reel 410b, left reel 410a, and right reel 410c is called "batting order." 3", and the operation of the stop switches 420a, 420b, 420c to stop the reels in the order of the middle reel 410b, right reel 410c, and left reel 410a is "batting order 4", and the operation of the stop switches 420a, 420b, and 420c is set as "batting order 4", and the reels are stopped in the order of the right reel 410c, the left reel 410a, and the middle reel 410b. The operation of the stop switches 420a, 420b, 420c to stop the reels is defined as "batting order 5", and the operation of the stop switches 420a, 420b, 420c to stop the reels in the order of right reel 410c, middle reel 410b, and left reel 410a is "batting order 6". ”.

For example, in a non-internal gaming state, if the winning type "batting order bell 1A" in the winning area 15 is won and the operation is performed according to the correct operation mode (batting order 1), the winning combination is a correct winning combination with a payout number of 11 pieces. Stop control is performed so that the symbol combination corresponding to "minor combination 1" is preferentially displayed on the active line A. In addition, when the operation is performed according to batting order 2, stop control is performed so that the symbol combination corresponding to the winning combination "Small combination 28", which is an incorrect combination with a payout number of 1 piece, is preferentially displayed on the active line A. is made and operations are performed in the batting order 3 and 4, the symbol combination corresponding to the winning combination "Small combination 12", which is an incorrect combination with a payout of 1 piece, is preferentially placed on active line A with 1/4 of the winning combination. If the stop control is performed so that the probability is displayed, and the operation is performed according to the batting order of 5 and 6, the symbol combination corresponding to the winning combination "Small combination 16", which is an incorrect combination with a payout number of 1 piece, will be displayed on the active line A. Stop control is performed so that it is preferentially displayed at the top with a probability of 1/4.

It should be noted that the winning probability (number) of each winning type in the winning areas 15 to 26 is set to be equal. Since the player usually cannot know which winning type he has won, by providing the winning areas 15 to 26 as described above, it is difficult to win the correct combination. Furthermore, as described above, even if the stop switches 420a, 420b, and 420c are operated in a batting order in which an incorrect combination is displayed preferentially, the symbol combination corresponding to the incorrect combination is not necessarily displayed on the active line A. Therefore, depending on the operation mode, spillage may occur (PB≠1).

In addition, when winning one of the above-mentioned winning types, the internal winning flag corresponding to each winning type is established (ON), and the stop control of each reel 410 is performed according to the establishment status of this internal winning flag. The Rukoto. At this time, if you win a winning type that includes a minor winning combination, but the symbol combination corresponding to these winning combinations cannot be displayed on the active line A in the game, after the game ends. The internal winning flag is turned off. In other words, the right to win a minor prize is limited only to the game in which the winning type that includes the minor prize is won, and the right cannot be carried over to the next game. On the other hand, if a winning type that includes the winning combination "RBB" is won, the RBB internal winning flag is established (ON) and the symbol combination corresponding to the winning combination "RBB" is placed on the active line A. The RBB internal winning flag is carried over across games until it is displayed. Furthermore, if the internal winning flag corresponding to a winning type that includes a replay combination is established, the symbol combination corresponding to one of the replay combinations included in that winning type will always be on the active line A. After the process necessary to play the next game without requiring medals is performed, the internal winning flag is turned off.

(Transition of gaming state)
Here, the transition of the gaming state will be explained using FIG. 80. Here, a plurality of gaming states are prepared, such as a non-internal gaming state, an RBB internal gaming state, and an RBB operating gaming state. As will be described later, each gaming state is changed depending on winning, winning (activation), and termination of a bonus combination.

The non-internal gaming state is a gaming state that corresponds to an initial state among a plurality of gaming states. In such a non-internal gaming state, the probability of winning a replay combination is set to approximately 1/7.3. Furthermore, in the non-internal gaming state, the winning combination "RBB" is determined with a predetermined probability (for example, about 1/30).

The gaming state control means 612 changes the gaming state in response to winning of the winning combination "RBB". For example, in a game in which the winning combination "RBB" is won, when a symbol combination corresponding to the winning combination "RBB" is displayed on the active line A, the gaming state control means 612 changes the gaming state to the RBB active gaming state. Transfer (1).

In the RBB active gaming state, the winning probability of the replay combination is set to 0. In addition, in such a gaming state during RBB operation, the winning types that can be won are the winning type "Small win ALL" in the winning area 1, and the winning types "1 piece ALLA" and "1 piece ALLB" in the winning areas 2 and 3. It is set. If you win the winning type "Small role ALL", a symbol combination corresponding to any of the winning roles "Small role 1" to "Small role 39" will be displayed on the active line A, and you will win the winning type "1 piece ALL". Then, the stop control is performed so that the symbol combination corresponding to any one of the winning combinations "Small Win 11" to "Small Win 39" is displayed on the active line A. Here, due to the configuration of such small winning combinations, the expected number of coins to be acquired per unit game in the gaming state during RBB operation is lowered.

When the termination condition of the RBB active gaming state is met, that is, when the number of acquired coins reaches a predetermined number, the gaming state control means 612 shifts the gaming state to a non-internal gaming state (2).

On the other hand, in a game in which the winning combination "RBB" is won, if the symbol combination corresponding to the winning combination "RBB" cannot be displayed on the active line A, the gaming state control means 612 controls the gaming state inside the RBB. A transition is made to a medium game state (special game state) (3).

In the RBB internal medium game state, the winning probability of the replay combination is set to approximately 1/5.9. Further, in the RBB internal medium game state, there is no possibility of winning the winning type "losing". In other words, if the symbol combination corresponding to the winning combination "RBB" could not be displayed on the active line A in a winning game with the winning combination "RBB", after that, the winning combination "RBB" would be smaller than the winning combination "RBB". Since the replay combination is controlled to stop on the active line A with priority, the symbol combination corresponding to the winning combination "RBB" cannot be displayed on the active line A. Therefore, once the gaming state shifts to the RBB internal medium gaming state, the RBB internal medium gaming state will be maintained without any subsequent gaming state transition. Here, while maintaining the RBB internal medium gaming state, an AT effect state is realized in the RBB internal medium gaming state.

Here, in the RBB internal medium game state, multiple types of correct combinations are won without overlapping each other, so it is possible to increase the chances of winning the correct combination, and as a result, for example, in the RBB internal medium game By performing the auxiliary performance in the AT performance state, medals can be easily obtained. On the other hand, in the RBB active gaming state, multiple types of correct winning combinations are won over and over again, so there are fewer opportunities to win the correct winning combination, so the correct winning combination is more likely to win than in the AT production state in other gaming states. This makes it difficult for players to increase the number of medals they own. Therefore, while the RBB active gaming state has the function of having a higher probability of winning winning combinations than the RBB internal playing state, in terms of medal acquisition performance, the RBB operating gaming state is the same as the RBB internal mid gaming state. It is possible to realize the specifications (accelerator RBB) that are inferior.

(Transition of production state)
FIG. 81 is an explanatory diagram for explaining the transition of the performance state. Hereinafter, the performance states (non-AT performance state, AT performance state) that are transitioned by the performance state control means 614 in the main control board 500 will be described in detail. In the following, a case where the gaming state is the RBB internal medium gaming state will be explained.

Here, in order to comprehensively and uniformly determine whether or not the gaming state with high medal acquisition performance is biased, a game section having performance related to the instruction function, that is, an auxiliary performance (instruction function) is executed. A game section that is advantageous to the player, including a game section, etc., is defined as an advantageous section (specific section). In addition, in the advantageous section, when the auxiliary effect is activated as a result of a lottery etc. related to the activation of the auxiliary effect on the main control board 500, the content of the instruction can be identified on the main control board 500. This is a game period in which instruction information may be transmitted to peripheral boards such as the sub-control board 502 only when displayed on the means. Furthermore, a game section different from the advantageous section is defined as a non-advantageous section. Therefore, the plurality of performance states (non-AT performance state, AT performance state) belong to either the advantageous section or the non-advantageous section which are the game sections. In this embodiment, almost all performance states belong to the advantageous section, and the non-advantageous section is realized in some performance states (here, non-advantageous performance state) of the non-AT performance state.

In addition, in the advantageous section, among the winning modes in which the correct winning combination would be missed if there is no auxiliary performance, in the selection winning type where the correct winning combination has the maximum payout (here, 11 coins), there is an assistance that helps the winning winning of the correct winning combination. When performing a performance (an auxiliary performance in which the maximum number of coins to be paid out can be obtained), the effect must be notified by, for example, lighting up the section display 460.

In addition, in the non-advantageous section, it is possible to vary the winning probability for each winning type depending on the setting value, but the probability that determines the transition to the performance state with auxiliary performance (AT performance state) for the same winning type must not be different for each setting value. On the other hand, in the advantageous section, both the winning probability of the winning type and the probability of determining the transition (or addition) to the performance state with auxiliary performance (AT performance state) for the same winning type differ depending on the setting value. It is possible to do so.

Therefore, the performance state control means 614 not only manages the transition of the performance state, but also manages the transition between the non-advantageous section and the advantageous section. Furthermore, regardless of such management, the advantageous section is forcibly terminated when the following termination conditions are met. For example, based on the fact that the value counted in the advantageous section has reached a predetermined value (for example, the number of stayed games (number of games played) has reached 1500 games, or the number of acquired coins (net increase number of coins) has exceeded 2400 coins) to forcefully exit. In either case, the performance state control means 614 resets all the information updated in the advantageous section (all variables that affect the performance related to the instruction function) by transitioning from the advantageous section to the non-advantageous section. .

(Non-AT performance state, AT performance state)
In the non-AT performance state, the frequency of execution of auxiliary performances is extremely low compared to the AT performance state, and since auxiliary performances are almost never performed, the number of medals that can be acquired is limited. Here, six performance states are provided as non-AT performance states: normal performance state, non-advantageous performance state, preparatory performance state, first interval performance state, continuous lottery performance state, and second interval performance state.

In the AT performance state, by causing the auxiliary performance execution means to perform the auxiliary performance when all selected winning types are won, it is possible to obtain a large number of medals while suppressing the consumption of medals. Therefore, by shifting to the AT performance state, the player can advance the game more advantageously than in the non-AT performance state. Here, a pseudo bonus performance state is provided as the AT performance state. Each performance state (normal performance state, pseudo-bonus performance state, non-advantageous performance state, preparatory performance state, first interval performance state, continuous lottery performance state, and second interval performance state) will be individually explained below.

(Each production state)
The normal performance state is a performance state corresponding to an initial state among a plurality of performance states. The performance state control means 614 performs an AT lottery in the normal performance state. The AT lottery is a lottery that determines transition to the AT performance state, and the performance state control means 614 performs the AT lottery with different probabilities for each winning type determined by the winning type lottery. If the AT lottery is won, the performance state control means 614 shifts the performance state to a pseudo-bonus performance state, which is an AT performance state, after a predetermined number of portent games have elapsed (1). Further, when a predetermined ceiling condition (for example, playing a predetermined number of games in a row in the normal performance state) is satisfied in the normal performance state without transitioning to the pseudo bonus performance state (so-called reaching the ceiling), the performance state control means 614 moves the performance state to a pseudo-bonus performance state (1).

In the pseudo-bonus performance state, the auxiliary performance is executed until a predetermined end condition (for example, the number of played games reaches a predetermined number of games) is met. You can get 3.5 sheets. In addition, in the pseudo-bonus effect state, two ending conditions are mainly prepared. For example, if the end condition is that the number of games played reaches a predetermined number of games, there are two levels of the predetermined number of games, 30 and 80, and one of them is determined by lottery. In the pseudo-bonus presentation state, the player will naturally gain more gaming profits as the number of games played increases. Therefore, the player would like the predetermined number of games to be 80 instead of 30. However, even if 30 is determined as the predetermined number of games, a promotion lottery is also held during which the predetermined number of games of the auxiliary performance is increased from 30 to 80. Note that here, as an example, the end condition of the pseudo-bonus performance state is that the number of played games has reached a predetermined number of games, but instead of this, the number of auxiliary performances that can obtain the maximum number of payout coins is set as a predetermined number. It is also possible to adopt a method in which the number of coins is reached, or the number of acquired coins (net increase in the number of coins) reaches a predetermined number.

Then, when a predetermined end condition is satisfied in the pseudo bonus performance state, the performance state control means 614 may shift the performance state to a non-advantageous performance state (2). At this time, the performance state control means 614 temporarily shifts the advantageous section to a non-advantageous section and resets all the information updated in the advantageous section. For example, if the previous pseudo-bonus performance state is the first pseudo-bonus performance state, that is, if it is a pseudo-bonus performance state immediately after transitioning from the normal performance state, the performance state control means 614 changes the performance state to an unfavorable state. At the same time as transitioning to the production state, the advantageous section is temporarily transferred to a non-advantageous section. Furthermore, even if the previous pseudo-bonus performance state is a pseudo-bonus performance state that is a multiple of 3 (3, 6, ...) without going through the normal performance state, the performance state control means 614 temporarily changes the advantageous section. , and at the same time, the advantageous section is temporarily transferred to the non-advantageous section.

Then, the production state control means 614 selects a lottery with a high probability (for example, 1/2) to shift to the advantageous section, returns to the advantageous section after playing the number game, and shifts the production state to the preparation production state ( 3). This is to avoid forcibly ending the pseudo-bonus effect state when the value counted in the advantageous section reaches a predetermined value.

On the other hand, if the previous pseudo-bonus performance state is not the first time, or the pseudo-bonus performance state is not a multiple of 3 without going through the normal performance state, the performance state control means 614 shifts the performance state to a non-advantageous performance state. The process directly shifts to the preparation performance state (4). This is to prevent the pseudo-bonus performance state from being forced to end when the value counted in the advantageous section reaches a predetermined value, and to prevent the advantageous section from ending unnecessarily.

In the preparation performance state, the performance state control means 614 selects a transition to the first interval performance state by lottery with a high probability (for example, 1/2), and changes the performance state based on the determination of transition to the first interval performance state. is shifted to the first interval presentation state (5).

The first interval performance state continues until a predetermined end condition (for example, 40 games have been played) is met, and during that time, the continuous lottery of the pseudo bonus performance state is executed. In this first interval performance state, unlike the pseudo-bonus performance state, the expected number of coins to be acquired per unit game is small and may be a negative value. Furthermore, in this embodiment, when winning an advantageous section in a non-advantageous section, the presentation state is set to always become the first interval presentation state. Therefore, after the end of the pseudo-bonus performance state, even if the advantageous period continues, even if the transition to the non-advantageous period occurs as described above, the transition to the first interval performance state will occur. becomes. Then, when a predetermined end condition in the first interval performance state is satisfied, the performance state control means 614 shifts the performance state to a continuous lottery performance state (6).

The continuous lottery performance state continues until a predetermined end condition (for example, five games are played) is met, and finally, the result of the continuous lottery in the pseudo bonus performance state in the first interval performance state is announced. Unlike the pseudo-bonus performance state, the continuous lottery performance state also has a small expected number of coins to be acquired per unit game, and may take a negative value. In the first interval performance state, if the transition to (continuation of) the pseudo-bonus performance state is determined, the performance state control means 614 shifts the performance state to the pseudo-bonus performance state (7). If it has not been decided to shift to the normal performance state, the performance state control means 614 returns the performance state to the normal performance state (8).

As described above, in the present embodiment, once the pseudo-bonus performance state is entered, the pseudo-bonus performance state → preparation performance state → first interval performance state → continuous lottery performance state unless the continuous lottery performance state is missed. By repeating the transition, the player can accumulate medals.

In addition, in the preparation performance state, the performance state control means 614 performs a lottery for transition to the second interval performance state in addition to a lottery for transition to the first interval performance state. However, the probability of transition to the second interval performance state (for example, 1/20) is set smaller than the probability of transition to the first interval performance state (for example, 1/2). In the preparatory performance state, if it is determined to transition to the second interval performance state before the transition to the first interval performance state is determined, the performance state control means 614 determines the transition to the second interval performance state. Based on this, the presentation state is shifted to the second interval presentation state (9). Here, an example is given in which a lottery for transition to the second interval performance state is performed in the preparatory performance state, but a lottery for transition to the second interval performance state may be similarly performed in the non-advantageous performance state.

Like the first interval performance state, the second interval performance state continues until a predetermined end condition (for example, 40 games have been played) is met, and during that time, the continuous lottery of the pseudo bonus performance state is executed. Like the first interval performance state, the second interval performance state differs from the pseudo bonus performance state in that the expected number of coins to be acquired per unit game is small and may take a negative value.

However, in the second interval performance state, the pseudo bonus performance state is determined with higher probability than in the first interval performance state. For example, in the first interval performance state, the pseudo-bonus performance state is determined at 1/58 for every game for 40 games (winning probability 50%), and in the second interval performance state, the pseudo-bonus performance state is determined for 40 games. is determined at 1/25 every game (80% probability of winning). Then, when a predetermined end condition is met, the performance state control means 614 shifts the performance state to a continuous lottery performance state (10). In addition, once it is decided to move to the second interval presentation state, thereafter, there will be no transition to the non-advantageous presentation state, the preparation presentation state, or the first interval presentation state, until the transition to the continuous lottery presentation state occurs. From the pseudo-bonus performance state, only the second interval performance state is entered (11). Therefore, the player can always receive a continuous lottery with a high probability. Furthermore, once the transition to the second interval performance state is determined, even if the transition to the pseudo bonus performance state is not determined in the continuous lottery performance state, the performance state control means 614 immediately changes the performance state. A transition is made to a non-advantageous performance state without returning to a normal performance state (12). Therefore, if it is not decided to shift to the pseudo bonus performance state in the continuous lottery performance state, the pseudo bonus performance state → preparation performance state → first interval performance state → continue until the continuous lottery in the continuous lottery performance state is missed again. It is possible to repeat the transition of the lottery performance state. In this way, once the transition to the second interval performance state occurs, it is possible to repeat the transition from the pseudo bonus performance state → the second interval performance state → the continuous lottery performance state with high probability, and furthermore, in the continuous lottery performance state, the pseudo bonus performance state can be repeated. Even if the transition to the bonus performance state is not decided, at least the transition from the pseudo bonus performance state to the preparation performance state to the first interval performance state to the continuous lottery performance state can be repeated again, so that the player can play more games. It becomes possible to accumulate medals. In other words, the second interval presentation state can be said to be more advantageous than the first interval presentation state.

Furthermore, as described above, when transitioning from the pseudo-bonus performance state to the second interval performance state, unlike the transition to the first interval performance state, the performance state control means 614 does not allow the transition to the non-advantageous section. do not have. In this embodiment, when the pseudo bonus performance state is the first pseudo bonus performance state, the performance state control means 614 does not shift to the second interval performance state, but temporarily changes the advantageous section to the non-advantageous section. , and the state is always shifted to the first interval performance state. This means that the advantageous section has been reset once. Therefore, even if the advantageous section is not reset when transitioning to the second interval presentation state, the pseudo bonus presentation state passing through the second interval presentation state will not end in a short period of time due to the limitation of the advantageous section, and the player A large number of medals can be obtained through the loop of pseudo bonus performance state → second interval performance state → continuous lottery performance state.

Hereinafter, specific processing in the main control board 500 and the sub control board 502 will be explained based on a flowchart.

(CPU initialization process of main control board 500)
FIG. 82 is a flowchart illustrating CPU initialization processing in main control board 500. When power is supplied from the power board, a system reset occurs in the main CPU 500a, and the main CPU 500a performs the following CPU initialization process (S2000).

(Step S2000-1)
When the power is turned on, the main CPU 500a reads a startup program from the main ROM 500b as an initial setting process, and performs setting processes necessary to execute various processes.

(Step S2000-3)
The main CPU 500a sets a wait processing time in a timer counter.

(Step S2000-5)
The main CPU 500a determines whether a power-off notice signal is detected. Note that the main control board 500 is provided with a power-off detection circuit, and when the power supply voltage falls below a predetermined value, a power-off warning signal is output from the power-off detection circuit. If a power cutoff notice signal is detected, the process moves to step S2000-3, and if a power cutoff notice signal is not detected, the process moves to step S2000-7.

(Step S2000-7)
Main CPU 500a determines whether the wait processing time set in step S2000-3 above has elapsed. As a result, if it is determined that the wait processing time has elapsed, the process moves to step S2000-9, and if it is determined that the wait time has not elapsed, the process moves to step S2000-5.

(Step S2000-9)
The main CPU 500a executes necessary processing to permit access to the main RAM 500c.

(Step S2000-11)
The main CPU 500a executes checksum confirmation processing. Here, the main CPU 500a calculates a checksum, and determines whether the calculated checksum does not match (is abnormal) the checksum saved at the time of power-off, and whether the backup is abnormal. Then, if the main CPU 500a determines that one or both of the backup and checksum is abnormal, it turns on the backup abnormality flag, and if it determines that both the backup and the checksum are not abnormal, it turns on the backup abnormality flag. Turn off.

(Step S2000-13)
The main CPU 500a determines whether the backup abnormality flag is on. As a result, if it is determined that the backup abnormality flag is on, the process moves to step S2010, and if it is determined that the backup abnormality flag is not on, the process moves to step S2020.

(Step S2010)
The main CPU 500a executes cold start processing. Note that this cold start processing will be described later.

(Step S2020)
The main CPU 500a executes a setting value switching process for switching setting values. Note that this setting value switching process will be described later.

(Step S2030)
The main CPU 500a executes a state recovery process to return to the state immediately before the power was turned off. Note that this state recovery process will be described later.

FIG. 83 is a flowchart illustrating cold start processing (S2010) in the main control board 500.

(Step S2010-1)
The main CPU 500a clears the used area in the main RAM 500c and executes a used area RAM check process to detect abnormalities in the used area.

(Step S2010-3)
The main CPU 500a clears the separate area (unused area) in the main RAM 500c, and executes a separate area RAM check process to detect an abnormality in the separate area. Note that if an abnormality is detected in another area in the other area RAM check process, the main CPU 500a turns on the RAM read/write error flag.

(Step S2010-5)
The main CPU 500a sets an error code "EA" indicating an abnormality in the main RAM 500c.

(Step S2010-7)
The main CPU 500a determines whether an abnormality is detected in step S2010-1. As a result, if it is determined that an abnormality has been detected in step S2010-1, the process moves to step S2011, and if it is determined that no abnormality has been detected in step S2010-1, the process moves to step S2010-9. Transfer processing.

(Step S2010-9)
The main CPU 500a acquires a RAM read/write error flag that is turned on when an abnormality is detected in step S2010-3.

(Step S2010-11)
The main CPU 500a determines whether the RAM read/write error flag is on. As a result, if it is determined that the RAM read/write error flag is on, the process moves to step S2011, and if it is determined that the RAM read/write error flag is not on, the process moves to step S2020.

(Step S2020)
The main CPU 500a executes a setting value switching process for switching setting values. Note that this setting value switching process will be described later.

(Step S2010-13)
The main CPU 500a sets an error code "E7" indicating a backup error.

(Step S2011)
The main CPU 500a executes error stop processing to stop the progress of the game due to an error. Note that this error stop processing will be described later.

FIG. 84 is a flowchart illustrating the error stop processing (S2011) in the main control board 500.

(Step S2011-1)
The main CPU 500a sets the initial stack pointer value as the address of the stack pointer.

(Step S2011-3)
The main CPU 500a executes an error setting process for setting an error display and a warning sound.

(Step S2011-5)
The main CPU 500a sets external signals 1 to 3 output bits off to turn off the output images of the bits corresponding to external signals 1 to 3.

(Step S2011-7)
The main CPU 500a executes output port image set processing to update the output image for the bits set in step S2011-5 above.

(Step S2011-9)
The main CPU 500a shifts to an eternal loop. As a result, the progress of the game will be stopped.

FIG. 85 is a flowchart illustrating the setting value switching process (S2020) in the main control board 500.

(Step S2020-1)
The main CPU 500a acquires a signal from input port 1, and determines whether a set value switching condition is satisfied based on the acquired signal from input port 1. As a result, if it is determined that the set value switching condition is not satisfied, the set value switching process is ended, and if it is determined that the set value switching condition is satisfied, the process is moved to step S2020-3. . Here, the signals of input port 1 include a signal indicating whether the upper front door 404 and lower front door 406 are open, and a signal indicating whether the setting door key is turned on. Here, the setting value switching condition is satisfied when a signal indicating that the upper front door 404 and lower front door 406 are open and a signal indicating that the setting door key is turned on is obtained. It is determined that this is the case.

(Step S2020-3)
The main CPU 500a executes RAM clear processing to clear the used area in the main RAM 500c that should be cleared when changing settings.

(Step S2020-5)
The main CPU 500a executes table content setting processing to transfer the table data of the setting value switching data table to the main RAM 500c.

(Step S2020-7)
The main CPU 500a sets a setting change start command in the transmission buffer, which indicates to start changing the setting value.

(Step S2020-9)
The main CPU 500a executes an edge check process to detect a rising edge (on edge) and a falling edge (off edge) of a signal at an input port.

(Step S2020-11)
The main CPU 500a obtains setting value data indicating current setting values.

(Step S2020-13)
The main CPU 500a determines whether an on-edge of the setting change switch is detected in step S2020-9. As a result, if it is determined that the on-edge of the setting change switch is not detected, the process moves to step S2020-17, and if it is determined that the on-edge of the setting change switch is detected, the process moves to step S2020-15. .

(Step S2020-15)
The main CPU 500a increments the setting value data by one.

(Step S2020-17)
The main CPU 500a determines whether the setting value data is within a range (1 to 6) that can be set as a setting value. As a result, if it is determined that the set value data is within the range, the process moves to step S2020-21, and if it is determined that the set value data is not within the range, the process moves to step S2020-19.

(Step S2020-19)
The main CPU 500a sets the setting value data to 0.

(Step S2020-21)
The main CPU 500a updates the setting value data to the value incremented or set in step S2020-15 or step S2020-19.

(Step S2020-23)
The main CPU 500a executes display data conversion processing to display the set value on the main credit display section 430.

(Step S2020-25)
The main CPU 500a determines whether an on-edge of the setting change switch is detected. As a result, if it is determined that the on-edge of the setting change switch is not detected, the process moves to step S2020-31, and if it is determined that the on-edge of the setting change switch is detected, the process moves to step S2020-27. move.

(Step S2020-27)
The main CPU 500a determines whether the setting change switch is on. As a result, if it is determined that the setting change switch is on, the process moves to step S2020-27, and if it is determined that the setting change switch is not on, the process moves to step S2020-29.

(Step S2020-29)
The main CPU 500a sets a setting change switch interval timer.

(Step S2020-31)
The main CPU 500a executes a timer wait process of waiting until the setting change switch interval timer reaches 0.

(Step S2020-33)
The main CPU 500a determines whether an on-edge of the start switch 418 has been detected. As a result, if it is determined that the on-edge of the start switch 418 is not detected, the process moves to step S2020-9, and if it is determined that the on-edge of the start switch 418 is detected, the process proceeds to step S2020-35. move.

(Step S2020-35)
The main CPU 500a determines whether the set door key is off. As a result, if it is determined that the set door key is off, the process moves to step S2020-35, and if it is determined that the set door key is not off, the process moves to step S2020-37.

(Step S2020-37)
The main CPU 500a determines whether the set door key is on. As a result, if it is determined that the set door key is on, the process moves to step S2020-37, and if it is determined that the set door key is not on, the process moves to step S2021.

(Step S2021)
The main CPU 500a executes initialization start processing to start initialization start. Note that this initialization start processing will be described later.

FIG. 86 is a flowchart illustrating the initialization start process (S2021) in the main control board 500.

(Step S2021-1)
The main CPU 500a sets a setting change end command in the transmission buffer indicating that the setting value change has been completed.

(Step S2021-3)
The main CPU 500a sets a setting change state command in the transmission buffer indicating the state when the setting value change is completed.

(Step S2021-5)
The main CPU 500a sets a wait timer at the start of initialization.

(Step S2021-7)
The main CPU 500a executes a timer wait process of waiting until the wait timer reaches 0 at the start of initialization.

(Step S2021-9)
The main CPU 500a executes a RAM clear process when changing settings to clear another area of the main RAM 500c.

(Step S2021-11)
The main CPU 500a executes RAM clear processing to clear the used area in the main RAM 500c that should be cleared when changing settings.

(Step S2021-13)
The main CPU 500a sets a gaming state command indicating the current gaming state in the transmission buffer.

(Step S2100)
The main CPU 500a executes a game start process for starting the game. Note that this game start process will be described later.

FIG. 87 is a flowchart illustrating the state recovery process (S2030) in the main control board 500.

(Step S2030-1)
The main CPU 500a restores the stack pointer.

(Step S2030-3)
The main CPU 500a executes an unused area clearing process to clear an unused area of the main RAM 500c.

(Step S2030-5)
The main CPU 500a clears the stack pointer storage buffer.

(Step S2030-7)
The main CPU 500a sets (turns on) a flag after power-off recovery.

(Step S2030-9)
The main CPU 500a executes port input processing to update the image of the input port.

(Step S2030-11)
The main CPU 500a executes an operation target bit extraction process for extracting information on the operation target bit based on the image of the input port updated in step S2030-9.

(Step S2030-13)
The main CPU 500a sets the operation target bit extracted in step S2030-11 above as the operation target bit in the previous state.

(Step S2030-15)
The main CPU 500a acquires the motor phases of the reels 410a, 410b, and 410c. Here, a motor phase is set as the state of the reels 410a, 410b, and 410c. The motor phase indicates the operating state of the reels 410a, 410b, 410c, that is, during acceleration, steady rotation, stop, and standby. Specifically, a 1-byte (memory unit) variable assigned to a motor phase is set according to the operating state of the stepping motor 452: accelerating = 3, steady rotation = 2, stopped = 1, and waiting = Changes to a value such as 0.

(Step S2030-17)
The main CPU 500a determines whether any of the reels 410a, 410b, and 410c are rotating steadily or accelerating based on the motor phase acquired in step S2030-15. As a result, if it is determined that none of the reels 410a, 410b, 410c is rotating normally or accelerating, the process moves to step S2030-21, and one of the reels 410a, 410b, 410c is rotating normally or accelerating. If it is determined that it is inside, the process moves to step S2030-19.

(Step S2030-19)
The main CPU 500a executes rotation error processing to perform settings when an error is detected for the reels 410a, 410b, and 410c.

(Step S2030-21)
The main CPU 500a restores the saved register group.

(Step S2030-23)
The main CPU 500a allows the interrupt and ends the state recovery process. As a result, the main CPU 500a returns to the state immediately before the power was turned off.

FIG. 88 is a flowchart illustrating the game start process (S2100) in the main control board 500.

(Step S2100-1)
The main CPU 500a executes a re-gaming state identification signal output setting process for outputting a re-gaming state identification signal indicating whether or not it is a re-gaming.

(Step S2100-3)
The main CPU 500a sets an input number display output bit off for turning off (turns off) a bit corresponding to the input number display that displays the number of medals inserted (bet number).

(Step S2100-5)
Main CPU 500a executes output port image set processing to update the output image for the bits set in step S2100-3 above.

(Step S2100-7)
The main CPU 500a sets a game start wait timer.

(Step S2100-9)
The main CPU 500a executes a timer wait process of waiting until the game start wait timer reaches 0.

(Step S2100-11)
The main CPU 500a executes one game RAM clearing process to clear the area to be cleared for each game among the used areas in the main RAM 500c.

(Step S2100-13)
The main CPU 500a executes a bonus signal setting process for setting a bonus signal.

(Step S2100-15)
The main CPU 500a executes edge clear processing to clear edge information of the input port image.

(Step S2200)
The main CPU 500a executes a game medal insertion process that accepts the insertion of medals. Note that this game medal insertion process will be described later.

FIG. 89 is a flowchart illustrating the game medal insertion process (S2200) in the main control board 500.

(Step S2200-1)
The main CPU 500a executes error confirmation processing to confirm the detection results of various errors.

(Step S2200-3)
The main CPU 500a executes an edge check process to detect a rising edge (on edge) and a falling edge (off edge) of a signal at an input port.

(Step S2200-5)
The main CPU 500a acquires a door open error detection flag that is set to 1 when the front upper door 404 or the front lower door 406 is opened.

(Step S2200-7)
Main CPU 500a determines whether upper front door 404 and lower front door 406 are closed based on the door open error detection flag acquired in step S2200-5 above. As a result, if it is determined that the front upper door 404 and the front lower door 406 are closed, the process moves to step S2200-17, and if at least one of the front upper door 404 or the front lower door 406 is not closed. If determined, the process moves to step S2200-9.

(Step S2200-9)
The main CPU 500a sets an error code "E8" indicating that at least one of the upper front door 404 and the lower front door 406 is open.

(Step S2200-11)
The main CPU 500a displays an error, requests a warning sound, and executes error wait processing for waiting for error recovery.

(Step S2200-13)
The main CPU 500a executes a setting value confirmation process to confirm the setting value.

(Step S2200-15)
The main CPU 500a executes edge clear processing to clear edge information of the input port image.

(Step S2200-17)
The main CPU 500a executes a credit button check process to refund the stored medals when a credit switch (not shown) for refunding the stored (credited) medals is pressed.

(Step S2200-19)
The main CPU 500a executes processing related to a game medal insertion button for betting medals. Here, when the bet switch 416 is pressed, the player bets the stored (credited) medals up to a specified number, and subtracts the stored number by the bet number. Furthermore, when medals are inserted through the medal slot 414a, bets are made up to a specified number of medals, and when more medals than the specified number are inserted, the corresponding amount is added to the stored number.

(Step S2200-21)
The main CPU 500a executes game medal acquisition processing to check whether the number of inserted medals is a specified number.

(Step S2200-23)
The main CPU 500a determines whether the number of inserted sheets is not the specified number based on the confirmation result in step S2200-21. As a result, if it is determined that the number of inserted sheets is not the specified number, the process moves to step S2200-1, and if it is determined that the number of inserted sheets is the specified number, the process moves to step S2200-25.

(Step S2200-25)
The main CPU 500a sets a start indicator output bit for turning on (lighting up) a start indicator (not shown) indicating whether or not the operation of the start switch 418 is valid.

(Step S2200-27)
The main CPU 500a determines whether a falling edge (pressing) of the start switch 418 has been detected. As a result, if it is determined that the falling edge of the start switch 418 has not been detected, the process moves to step S2200-1, and if it is determined that the falling edge of the start switch 418 has been detected, the process moves to step S2200-1. Processing moves to -29.

(Step S2200-29)
The main CPU 500a clears the main payout display section buffer in order to clear the display on the main payout display section 432.

(Step S2200-31)
The main CPU 500a executes a re-gaming state identification signal clearing process to clear the re-gaming state identification signal.

(Step S2200-33)
The main CPU 500a executes blocker closing preprocessing to turn off the start indicator.

(Step S2200-35)
The main CPU 500a sets a lever press command indicating that the start switch 418 has been pressed in the transmission buffer.

(Step S2300)
The main CPU 500a executes an internal lottery process for determining the winning type. Note that this internal lottery process will be described later.

FIG. 90 is a flowchart illustrating the internal lottery process (S2300) in the main control board 500.

(Step S2300-1)
The main CPU 500a acquires setting value data.

(Step S2300-3)
The main CPU 500a sets an error code "EC" indicating a setting value abnormality error.

(Step S2300-5)
The main CPU 500a determines whether the setting value data acquired in step S2300-1 is abnormal. As a result, if it is determined that the set value data is abnormal, the process moves to step S2011, and if it is determined that the set value data is not abnormal, the process moves to step S2300-7.

(Step S2300-7)
The main CPU 500a obtains the winning type lottery random number updated by the random number generator 500d.

(Step S2300-9)
The main CPU 500a executes a state offset acquisition process to acquire an offset value related to the gaming state.

(Step S2300-11)
The main CPU 500a sets the address of the internal lottery area definition table (winning type lottery table).

(Step S2300-13)
The main CPU 500a sets the value indicated by the address obtained by adding the offset value obtained in step S2300-9 above to the address set in step S2300-11 above as the initial value of the winning area. Here, the first winning area in the winning type lottery table of the current gaming state is set as the initial value.

(Step S2300-15)
The main CPU 500a acquires lottery data, which is a numerical value indicating the winning range of the winning area, and executes lottery data acquisition processing to shift the winning area by 1.

(Step S2300-17)
The main CPU 500a determines whether or not to perform a winning type lottery. As a result, if it is determined that the winning type lottery will not be performed, the process moves to step S2300-21, and if it is determined that the winning type lottery is to be performed, the process moves to step S2300-19.

(Step S2300-19)
The main CPU 500a subtracts the lottery data from the random number value.

(Step S2300-21)
The main CPU 500a determines whether the subtraction result in step S2300-19 is negative, that is, whether the winning area has been won by the winning type lottery. As a result, if it is determined that the player has won the winning type lottery, the process moves to step S2400, and if it is determined that the player has not won the winning type lottery, the process moves to step S2300-23.

(Step S2300-23)
The main CPU 500a determines whether the winning type lottery has ended. As a result, if it is determined that the winning type lottery has not ended, the process moves to step S2300-15, and if it is determined that the winning type lottery has ended, the process moves to step S2300-25.

(Step S2300-25)
The main CPU 500a clears the trigger role type.

(Step S2400)
The main CPU 500a executes a symbol code setting process for setting a symbol code based on the winning area and the gaming state. Note that this symbol code setting process will be described later.

FIG. 91 is a flowchart illustrating the symbol code setting process (S2400) in the main control board 500.

(Step S2400-1)
The main CPU 500a acquires the winning area won in step S2300, and executes a gaming state setting process of setting the gaming state to the internal medium gaming state if the acquired winning area includes a bonus combination.

(Step S2400-3)
The main CPU 500a sets the winning area acquired in step S2400-1 above as a stop control number.

(Step S2400-5)
The main CPU 500a determines (sets) the winning type based on the winning area acquired in step S2400-1 above.

(Step S2400-7)
The main CPU 500a executes a symbol code initial setting process for setting a symbol code indicating a displayable symbol and a drawing target symbol based on the stop control number set in step S2400-3.

(Step S2400-9)
The main CPU 500a executes display symbol bit initial value setting processing for setting display symbol bits.

(Step S2400-11)
The main CPU 500a executes an execution flag setting process that sets an execution flag, performs various processes related to the presentation state, processes related to auxiliary presentation, and the like.

(Step S2400-13)
The main CPU 500a sets a production command, which is a command related to an advantageous section, in the transmission buffer.

(Step S2400-15)
The main CPU 500a sets a winning information command indicating the winning type in the transmission buffer.

(Step S2400-17)
The main CPU 500a checks the one-game timer.

(Step S2400-19)
The main CPU 500a sets in the transmission buffer a pre-rotation command indicating that the reels 410a, 410b, and 410c are before rotation.

(Step S2400-21)
The main CPU 500a executes an excitation release wait process for waiting for excitation release of the stepping motor 452.

(Step S2400-23)
The main CPU 500a determines whether the one-game timer is not 0. As a result, if it is determined that the one-game timer is not 0, the process moves to step S2400-23, and if it is determined that the one-game timer is 0, the process moves to step S2400-25.

(Step S2400-25)
The main CPU 500a executes a reel start process for starting the rotation of the reels 410a, 410b, and 410c. Here, the motor phase of the reels 410a, 410b, and 410c is set to be accelerated to start the rotation of each reel, and the one-game timer is set to a value corresponding to 4.1 seconds.

(Step S2400-27)
The main CPU 500a sets a reel start command in the transmission buffer indicating that the rotation of the reels 410a, 410b, and 410c has started.

(Step S2500)
The main CPU 500a executes a reel rotation process which is a process while the reels 410a, 410b, and 410c are rotating. Note that this processing during rotation of the drum will be described later.

FIG. 92 is a flowchart illustrating processing during rotation of the drum (S2500) in the main control board 500.

(Step S2500-1)
The main CPU 500a sets the stop indicator output bit off (output image) to turn off (extinguish) the bit corresponding to the indicators (not shown) of the stop switches 420a, 420b, and 420c. Here, the stop indicator output bit is composed of a 3-bit bit string, and each bit is associated with the emission color of the three stop switches 420a, 420b, and 420c, and is represented by blue = 1 and red = 0. be done.

(Step S2500-3)
Main CPU 500a executes output port image set processing to update the output image for the bits set in step S2500-1 above.

(Step S2500-5)
The main CPU 500a executes error confirmation processing to confirm the detection results of various errors.

(Step S2500-7)
The main CPU 500a refers to the index flag and obtains the indexes of the rotating reels 410a, 410b, and 410c. Note that the index flag is set only after the reels 410a, 410b, and 410c reach a constant rotation speed.In other words, the index flag is set when the reels 410a, 410b, and 410c are rotated at a constant speed. It also shows that the speed has been reached.

(Step S2500-9)
The main CPU 500a determines whether the index flags of all the reels 410a, 410b, and 410c have been detected. As a result, if it is determined that all index flags have not been detected, the process moves to step S2500-1, and if it is determined that all index flags have been detected, the process moves to step S2500-11.

(Step S2500-11)
The main CPU 500a obtains stop reel bits indicating the reels 410a, 410b, and 410c that have stopped or started to stop. Here, the stop reel bit is composed of a 3-bit bit string, each bit is associated with one of the three reels 410a, 410b, and 410c, and the constant speed state = 1, acceleration state, and deceleration state. Alternatively, the stopped state is represented by 0.

(Step S2500-13)
The main CPU 500a stores the stop drum bit acquired in step S2500-11 above as a drum rotating flag.

(Step S2500-15)
The main CPU 500a sets the stop indicator output bit on (output image) to turn on (turn off) the bit corresponding to the indicators (not shown) of the stop switches 420a, 420b, and 420c.

(Step S2500-17)
The main CPU 500a acquires an image of input port 0, and executes operation target bit extraction processing for extracting operation target bits from the acquired image. Here, the bit to be manipulated is composed of a 3-bit bit string, and each bit is associated with one of the three stop switches 420a, 420b, and 420c, and the bit being manipulated = 1 and not being manipulated. =0.

(Step S2500-19)
The main CPU 500a calculates the logical product of the rotation drum flag acquired in step S2500-13 and the operation target bit extracted in step S2500-17. Here, if the reel 410 is rotating and the stop switch 420 corresponding to the reel is operated, that is, if the operated stop switch 420 corresponds to the reel 410 that is effectively rotating. , the logical product is 1.

(Step S2500-21)
The main CPU 500a determines whether the logical product calculated in step S2500-19 is 0, that is, whether the stop switch 420 corresponding to the rotating reel 410 has been operated. As a result, if it is determined that the stop switch 420 corresponding to the rotating reel 410 is not operated, the process moves to step S2500-3, and the stop switch 420 corresponding to the rotating reel 410 is not operated. If it is determined that it is, the process moves to step S2500-23.

(Step S2500-23)
The main CPU 500a obtains an output image including the stop indicator output bit, and calculates a logical product between the obtained output image and the logical product calculated in step S2500-19. Here, when the operated stop switch 420 is lit in red, the AND bit becomes 0, and when the operated stop switch 420 is lit in blue, the AND bit becomes 1.

(Step S2500-25)
The main CPU 500a determines whether the logical product calculated in step S2500-23 is 0, that is, whether the operated stop switch 420 is lit in red. As a result, if it is determined that the operated stop switch 420 is lit in red, the process moves to step S2500-1, and if it is determined that the operated stop switch 420 is not lit in red, the process proceeds to step S2500-1. The process moves to step 27.

(Step S2500-27)
The main CPU 500a determines whether or not the operated stop switch 420 is valid. As a result, if it is determined that the operated stop switch 420 is not valid, the process moves to step S2500-1, and if it is determined that the operated stop switch 420 is valid, the process moves to step S2500-29. Move. Note that here, it is determined whether or not the number of operated stop switches 420 is one. If it is determined that the number of operated stop switches 420 is one, the process moves to step S2500-29, and if it is determined that the number of operated stop switches 420 is not one, that is, two or more. Then, the process moves to step S2500-1.

(Step S2500-29)
The main CPU 500a executes a stop control reel setting process to obtain various parameters for stopping the reel 410 corresponding to the operated stop switch 420.

(Step S2500-31)
The main CPU 500a prohibits interrupts.

(Step S2500-33)
The main CPU 500a executes a press reference position acquisition process that derives the symbol number of the symbol located on the active line A as the press reference position.

(Step S2500-35)
The main CPU 500a executes a sliding piece number acquisition process that determines the number of sliding pieces on the reel 410.

(Step S2600)
The main CPU 500a executes a reel stop process to stop the reel 410 corresponding to the operated stop switch 420. Note that this rotation drum stop processing will be described later.

FIG. 93 is a flowchart illustrating the rotation drum stop process (S2600) in the main control board 500.

(Step S2600-1)
The main CPU 500a obtains the press reference position derived in step S2500-35 above.

(Step S2600-3)
The main CPU 500a calculates a stop request number by correcting the number of sliding frames determined in step S2500-37 above with respect to the press reference position obtained in step S2600-1 above.

(Step S2600-5)
The main CPU 500a sets a stop request flag (sets it to 1). The stop request flag is a flag for requesting a program running in parallel to stop the target reel 410. By setting the stop request flag to 1, the symbol corresponding to the stop request number is enabled. It becomes possible to stop on line A. The stop request flag and the above-mentioned stop request number are read by a program running in parallel, and the reel 410 is stopped. Note that when the stop processing is completed, the stop request flag is reset to 0 (OFF) by the program.

(Step S2600-7)
The main CPU 500a allows interrupts.

(Step S2600-9)
The main CPU 500a sets a stop information command indicating the order in which the reels 410 are stopped in the transmission buffer.

(Step S2600-11)
The main CPU 500a sets the stop indicator output bit OFF (output image) to turn off (extinguish) the bit corresponding to the indicator (not shown) of the stop switch 420.

(Step S2600-13)
Main CPU 500a executes output port image set processing to update the output image for the bits set in step S2600-11 above.

(Step S2600-15)
The main CPU 500a executes display symbol bit setting processing for setting display symbol bits.

(Step S2600-17)
The main CPU 500a executes next cylinder setting preprocessing to stop the next reel 410.

(Step S2600-19)
The main CPU 500a determines whether the stopping process for all reels 410 has been completed. As a result, if it is determined that the stop processing of all reels 410 has not been completed, the process moves to step S2500, and if it is determined that the stop processing of all reels 410 has been completed, the process proceeds to step S2600-21. Transfer processing.

(Step S2600-21)
The main CPU 500a determines whether the stop request flag is on for any reel 410, that is, whether all reels 410 have been stopped. As a result, if it is determined that all the reels 410 have not been stopped, the process moves to step S2600-21, and if it is determined that all the reels 410 have stopped, the process moves to step S2600-23.

(Step S2600-23)
The main CPU 500a executes error confirmation processing to confirm the detection results of various errors.

(Step S2600-25)
The main CPU 500a executes a manipulation target bit extraction process that extracts information on the manipulation target bit.

(Step S2600-27)
Main CPU 500a determines whether stop switch 420 is pressed based on the operation target bit acquired in step S2600-25 above. As a result, if it is determined that the stop switch 420 is pressed down, the process moves to step S2600-23, and if it is determined that the stop switch 420 is not pressed down, the process moves to step S2700.

(Step S2700)
The main CPU 500a executes a display determination process to determine the winning winning combination. Note that this display determination process will be described later.

FIG. 94 is a flowchart illustrating display determination processing (S2700) in main control board 500.

(Step S2700-1)
The main CPU 500a clears the buffer of the main payout display section 432.

(Step S2700-3)
The main CPU 500a determines whether a display determination abnormality has occurred based on whether or not the symbol combination displayed on the active line A matches the symbol combination that is permitted to be displayed on the active line A. Execute the detection process.

(Step S2700-5)
The main CPU 500a sets an error code "EE" indicating a display determination abnormality (error).

(Step S2700-7)
The main CPU 500a determines whether the display determination is abnormal based on the determination result in step S2700-3. As a result, if it is determined that the display determination is abnormal, the process moves to step S2011, and if it is determined that the display determination is not abnormal, the process moves to step S2700-9.

(Step S2700-9)
The main CPU 500a executes display symbol identification generation processing to determine the winning winning combination based on the symbol combinations stopped (displayed) on the active line A.

(Step S2700-11)
The main CPU 500a sets 0 as the initial value of the number of coins to be paid out.

(Step S2700-13)
The main CPU 500a determines whether a small winning combination has been won. As a result, if it is determined that a small winning combination has been won, the process moves to step S2700-15, and if it is determined that a small winning combination has not been won, the process moves to step S2700-35.

(Step S2700-15)
The main CPU 500a turns on a winning flag indicating that a small winning combination has been won.

(Step S2700-17)
The main CPU 500a executes a payout number setting process for setting a payout number according to the winning small winning combination.

(Step S2700-19)
The main CPU 500a determines whether it is an advantageous section. As a result, if it is determined that it is not an advantageous section, the process moves to step S2800, and if it is determined that it is an advantageous section, the process moves to step S2700-21.

(Step S2700-21)
The main CPU 500a obtains the value of the advantageous section MY counter that counts the net increase in the number of sheets during the advantageous section.

(Step S2700-23)
The main CPU 500a adds the number of coins to be paid out to the value of the advantageous section MY counter acquired in step S2700-23.

(Step S2700-25)
The main CPU 500a obtains the number of coins inserted in the game.

(Step S2700-27)
The main CPU 500a subtracts the number of inserted sheets from the value added in step S2700-23.

(Step S2700-29)
The main CPU 500a determines whether the subtraction result in step S2700-27 is not negative. As a result, if it is determined that the subtraction result is not negative, the process moves to step S2700-33, and if it is determined that the subtraction result is negative, the process moves to step S2700-31.

(Step S2700-31)
The main CPU 500a clears the value of the advantageous section MY counter (sets it to 0).

(Step S2700-33)
The main CPU 500a updates the value of the advantageous section MY counter to the value subtracted in step S2700-27 or the value cleared in step S2700-31.

(Step S2700-35)
The main CPU 500a determines whether or not the replay combination has won. As a result, if it is determined that the replay combination has not won, the process moves to step S2800, and if it is determined that the replay combination has won, the process moves to step S2700-37.

(Step S2700-37)
The main CPU 500a sets the number of coins to be put in to the number of coins to be paid out.

(Step S2700-39)
The main CPU 500a turns on the replay flag.

(Step S2700-41)
The main CPU 500a sets the number of automatically inserted sheets.

(Step S2800)
The main CPU 500a executes a payout process for paying out medals. Note that this payout process will be described later.

FIG. 95 is a flowchart illustrating the payout process (S2800) in the main control board 500.

(Step S2800-1)
The main CPU 500a acquires the re-gaming operation flag.

(Step S2800-3)
The main CPU 500a sets a payout start command in the transmission buffer indicating that the payout of medals has started.

(Step S2800-5)
The main CPU 500a determines whether the replay combination has won based on the replay active flag acquired in step S2800-1. As a result, if it is determined that the replay combination has won, the process moves to step S2800-41, and if it is determined that the replay combination has not won, the process moves to step S2800-7.

(Step S2800-7)
The main CPU 500a executes a main display display process to display 0 on the main payout display section 432.

(Step S2800-9)
The main CPU 500a determines that there is no payout (the number of coins to be paid out is 0). As a result, if it is determined that there is no payout, the process moves to step S2800-35, and if it is determined that there is a payout, the process moves to step S2800-11.

(Step S2800-11)
The main CPU 500a determines whether the number of stored sheets is 50 or more. As a result, if it is determined that the stored number is 50 or more, the process moves to step S2800-13, and if it is determined that the stored number is not 50 or more, the process moves to step S2800-15.

(Step S2800-13)
The main CPU 500a executes a medal payout device control process to pay out one medal from the medal payout device 442, and moves the process to step S2800-23.

(Step S2800-15)
The main CPU 500a sets a payout start interval timer.

(Step S2800-17)
The main CPU 500a determines whether the payout start timer is not 0, that is, whether it is the first payout. As a result, if it is determined that it is the first payout time, the process moves to step S2800-21, and if it is determined that it is not the first payout time, the process moves to step S2800-19.

(Step S2800-19)
The main CPU 500a executes a timer wait process to wait until the payout start interval timer becomes 0.

(Step S2800-21)
The main CPU 500a increments the number of stored sheets by one.

(Step S2800-23)
The main CPU 500a sets a payout execution command indicating that one medal has been paid out in the transmission buffer.

(Step S2800-25)
The main CPU 500a executes main display pre-display processing to display the number of coins that have already been paid out on the main payout display section 432.

(Step S2800-27)
The main CPU 500a determines whether the game is in a bonus game state or not. As a result, if it is determined that the bonus game state is not present, the process moves to step S2800-31, and if it is determined that the bonus game state is present, the process moves to step S2800-29.

(Step S2800-29)
The main CPU 500a increments the number of medals obtained during bonus operation, which is the number of medals paid out in the bonus game state, by one.

(Step S2800-31)
The main CPU 500a determines whether the payout of the number of medals to be paid out has not been completed. As a result, if it is determined that the payout has not been completed, the process moves to step S2800-11, and if it is determined that the payout has finished, the process moves to step S2800-33.

(Step S2800-33)
The main CPU 500a executes a payout end process to end the payout of medals.

(Step S2800-35)
The main CPU 500a determines whether an over error has been detected. As a result, if it is determined that no over error has been detected, the process moves to step S2800-41, and if it is determined that an over error has been detected, the process moves to step S2800-37.

(Step S2800-37)
The main CPU 500a sets an error code "E5" indicating an over error.

(Step S2800-39)
The main CPU 500a displays an error, requests a warning sound, and executes error wait processing for waiting for error recovery.

(Step S2800-41)
The main CPU 500a sets a payout end command indicating that the payout of medals has ended in the transmission buffer.

(Step S2900)
The main CPU 500a executes a game transition process that performs a game state transition, a process for managing advantageous sections, and the like. Note that this game transfer process will be described later.

FIG. 96 is a flowchart illustrating the game transfer process (S2900) in the main control board 500.

(Step S2900-1)
The main CPU 500a acquires the replay active flag, and turns on or off a bit corresponding to a replay indicator (not shown) indicating that the next game is a replay based on the acquired replay active flag. For this purpose, the stop indicator output bit off (output image) is set, and replay indicator control processing is executed to update the output bit of the set output image.

(Step S2900-3)
When a bonus combination is won, the main CPU 500a executes an accessory activation symbol display process that sets various parameters for controlling the bonus game state.

(Step S2900-5)
In the bonus game state, when the number of coins acquired during bonus operation reaches a predetermined number, the main CPU 500a executes a bonus operation termination process to shift the game state to a non-internal game state.

(Step S2900-7)
The main CPU 500a executes advantageous section update processing for managing advantageous sections.

(Step S2900-9)
The main CPU 500a determines whether the next game is in an AT performance state. As a result, if it is determined that the next game is not in the AT effect state, the process moves to step S2900-15, and if it is determined that the next game is in the AT effect state, the process moves to step S2900-11.

(Step S2900-11)
The main CPU 500a determines whether the game is in a bonus game state or not. As a result, if it is determined that the bonus game state is not present, the process moves to step S2900-15, and if it is determined that the bonus game state is present, the process moves to step S2900-13.

(Step S2900-13)
The main CPU 500a sets an advantageous lamp flag to turn on the section indicator 460.

(Step S2900-15)
The main CPU 500a executes a production command setting process that sets a production command, which is a command related to an advantageous section, in a transmission buffer.

(Step S2900-17)
The main CPU 500a sets a game end command indicating that one game has ended in the transmission buffer.

(Step S2900-19)
The main CPU 500a executes terminal board signal output processing for outputting external signals.

(Step S2900-21)
The main CPU 500a determines whether the performance wait timer set when ending the advantageous section in step S2900-7 is not 0. As a result, if it is determined that the presentation wait timer is not 0, the process moves to step S2900-21, and if it is determined that the presentation wait timer is 0, the process moves to step S2900-23.

(Step S2900-23)
The main CPU 500a sets a gaming status command indicating the gaming status in the transmission buffer.

(Step S2900-25)
The main CPU 500a sets a game start command indicating the start of the next game in the transmission buffer, and moves the process to step S2100.

One game is executed through a series of processes from step S2100 to step S2900. Thereafter, steps S2100 to S2900 will be repeated.

Next, the power-off saving process and timer interrupt process in the main control board 500 will be described.

(Evacuation processing when the main control board 500 is powered off)
FIG. 97 is a flowchart illustrating a power-off save process in the main control board 500. The main CPU 500a monitors the power-off detection circuit, and when the power supply voltage falls below a predetermined value, interrupts and executes a power-off save process.

(Step S3000-1)
When the power-off notice signal is input, the main CPU 500a saves the register.

(Step S3000-3)
The main CPU 500a checks the power-off notice signal.

(Step S3000-5)
The main CPU 500a determines whether a power-off notice signal is detected. As a result, if it is determined that a power-off notice signal has been detected, the process moves to step S3000-11, and if it is determined that a power-off notice signal has not been detected, the process moves to step S3000-7. .

(Step S3000-7)
The main CPU 500a restores the register.

(Step S3000-9)
The main CPU 500a performs processing to permit interrupts, and ends the power-off save processing.

(Step S3000-11)
The main CPU 500a executes output port clear processing to stop output from the output port.

(Step S3000-13)
The main CPU 500a executes a save process for another area when the power is turned off.

(Step S3000-15)
The main CPU 500a executes RAM protect setting processing necessary to prohibit access to the main RAM 300c.

(Step S3000-17)
The main CPU 500a sets the predetermined number of times the power outage detection signal has been detected to the counter value of the loop counter in order to set the power outage occurrence monitoring time.

(Step S3000-19)
The main CPU 500a subtracts 1 from the value of the loop counter set in step S3000-17 above.

(Step S3000-21)
The main CPU 500a determines whether the counter value of the loop counter is not zero. As a result, if it is determined that the counter value is not 0, the process moves to step S3000-19, and if it is determined that the counter value is 0, the process moves to the above-described CPU initialization process (step S1000).

Note that if a power outage actually occurs, the operation of the slot machine 400 is stopped while the steps S3000-19 to S3000-21 are looped.

(Timer interrupt processing of main control board 500)
FIG. 98 is a flowchart illustrating timer interrupt processing in main control board 500. The main control board 500 is provided with a reset clock pulse generation circuit that generates a clock pulse every predetermined period (1.49 milliseconds in the simultaneous running reference example, hereinafter referred to as "1.49ms"). Then, when a clock pulse is generated by the reset clock pulse generation circuit, an interrupt is generated and the following timer interrupt processing is executed.

(Step S3100-1)
The main CPU 500a saves the register.

(Step S3100-3)
The main CPU 500a clears the interrupt flag.

(Step S3100-5)
The main CPU 500a reads various input port images and executes port input processing to accurately obtain the latest switch status.

(Step S3100-7)
The main CPU 500a outputs the set output image to the output port, and displays the main credit display section 430, main payout display section 432, input number display, start display, stop switch 420a, 420b, and 420c display, and replay display. Dynamic port output processing is executed to control the lighting of the section indicator 460.

(Step S3100-9)
The main CPU 500a updates the timer interrupt phase. Note that the timer interrupt phase is one of 0 to 3, and here, when the timer interrupt phase is 0, 1, or 2, 1 is added, and when the timer interrupt phase is 3, it is added to 0. Be changed.

(Step S3100-11)
The main CPU 500a performs sub-command transmission processing to transmit the command stored in the transmission buffer to the sub-control board 502.

(Step S3100-13)
The main CPU 500a executes stepping motor control processing to control the stepping motor 452.

(Step S3100-15)
The main CPU 500a executes an output port image output process that outputs an output image to be output to the medal payout device 442.

(Step S3100-17)
The main CPU 500a executes random number update processing to update various random numbers.

(Step S3100-19)
The main CPU 500a executes fraud monitoring processing to detect errors in order to output external signals (external signals 4 and 5) corresponding to the errors to the outside.

(Step S3100-21)
The main CPU 500a executes a module (subroutine) corresponding to the timer interrupt processing phase updated in step S3100-9 above. Here, the timer interrupt processing phase is set to one of 0 to 3, and one module is provided corresponding to each of the timer interrupt processing phases 0 to 3 (total of 4). The two modules will be executed once every four times (every 5.96 ms) of timer interrupt processing. For example, a module that executes time monitoring processing for subtracting various timers is associated with one timer interrupt processing phase.

(Step S3100-23)
The main CPU 500a executes test signal output processing to output a test signal to the outside.

(Step S3100-25)
The main CPU 500a reads various input port images and executes port input processing to accurately obtain the latest switch status.

(Step S3100-27)
The main CPU 500a restores the register.

(Step S3100-29)
The main CPU 300a allows the interrupt and ends the timer interrupt processing.

Furthermore, in the above-described embodiment, the main control board 500 and the sub-control board 502 are arranged to share the functional parts for playing the game, but the functional parts of the main control board 500 are transferred to the sub-control board 502. The functional parts of the sub-control board 502 may be arranged on the main control board 500, or all the functional parts can be arranged on one control board.

In addition, in the above-described embodiment, only one type of AT performance state is provided, but it is possible to provide multiple types of AT performance states, such as a specialized zone for adding on the number of continuous games in the AT performance state, for example. Good too.

Further, in the above-described embodiment, the game is played using medals as the gaming value, but the gaming value may be electrical information (so-called medalless). In this case, when a winning combination is won, the amount of value corresponding to the winning combination may be given to the player in the form of electrical information.

Further, each process performed by the main control board 500 and the sub-control board 502 described above does not necessarily need to be performed in chronological order according to the order described in the flowchart, and may include processing in parallel or by a subroutine.

Further, each process performed by the main control board 500 and the sub-control board 502 described above does not necessarily need to be performed in chronological order according to the order described in the flowchart, and may include processing in parallel or by a subroutine.

<Configuration around the CPU of the main control board>
FIG. 99 is a diagram for explaining electrical connections around the main CPU 300a. Main CPU 300a includes a CPU core 700 and a bus controller 702. The CPU core 700 controls the bus controller 702 through a bus control signal (Bus Cont) output from the BC terminal, reads data from the main ROM 300b, main RAM 300c, or input/output section 704, or reads data from the main RAM 300c or the input/output section 704. Data is written to the section 704. Here, as the main CPU 300a, a microprocessor based on a Z80 series CPU sold by LETech is used. Although the main CPU 300a, main ROM 300b, and main RAM 300c of the pachinko machine will be described here, it goes without saying that they can be replaced with the main CPU 500a, main ROM 500b, and main RAM 500c of the slot machine 400.

For example, when reading data from the main ROM 300b, the main RAM 300c, or the input/output unit 704, the bus controller 702 outputs a 16-bit address (A[16]) signal, and the main ROM 300b, Identify either the main RAM 300c or the input/output unit 704, control the read (RD) signal, and read the data (D[8]) signal from the main ROM 300b, the main RAM 300c, or the input/output unit 704. . Furthermore, when writing data to the main RAM 300c or the input/output unit 704, the bus controller 702 outputs an address (A[16]) signal and a data (D[8]) signal, and writes the data to the main RAM 300c through the decoders 706b and 706c. , or the input/output unit 704, and controls the write (WR) signal to write the data (D[8]) signal to the main RAM 300c or the input/output unit 704.

Here, as will be described later, the address space of the input/output unit 704 is integrated with the address spaces of the main ROM 300b and main RAM 300c. Therefore, conventionally, a memory request (MREQ) terminal and an I/O request (IORQ) terminal for outputting a signal for specifying whether to access memory or I/O are not provided. By reassigning these two terminals to arbitrary other signals, the degree of freedom in program development can be increased.

The CPU core 700 also has an interrupt/wait (INT/WAIT) signal that triggers the start of interrupt processing, a non-maskable interrupt (NMI) signal that allows interrupt processing to be executed with the highest priority, and a bus signal that is set to high impedance. External signals such as a transitionable bus request (BUSREQ) signal are also input.

FIG. 100 is a block diagram showing the internal configuration of CPU core 700. CPU core 700 includes an external input unit 710, a state control unit 712, a central control unit 714, a register unit 716, and an arithmetic logic unit (ALU) 718. External input unit 710 receives an external signal and outputs control information based on the external signal to state control unit 712 and central control unit 714.

The state control unit 712 manages and transitions internal states (RESET, instruction fetch, instruction decode, calculation, memory load, memory store, HALT, etc.) based on input control information, and controls the operating state of the CPU core 700. At the same time, control information based on the operating state is output to the central control unit 714.

The central control unit 714 extracts an operation code (instruction) from the input data (DI[8]) input via the bus controller 702, and controls the ALU 718 based on the command decoded by the instruction decoder. Further, the central control unit 714 acquires necessary information from each register of the register unit 716 and updates each register using the decoded command.

The register unit 716 includes selector ports 722a, 722b, and 722c, an input bank selector 724, a first register bank 726, a second register bank 728, an output bank selector 730, an address port 732, and an individual register 734. The individual registers 734 include a 16-bit program counter (PC) that indicates the address of the program to be executed next, an 8-bit interrupt (I) register used in interrupt mode, and an 8-bit interrupt (I) register that counts opcode fetch cycles. It includes a bit refresh (R) register and an 8-bit interrupt enable (IFF) register that controls interrupt enable/disable.

In addition, the register unit 716 includes a random number generator for obtaining various random numbers (jackpot determination random number, winning symbol random number, reach group determination random number, reach mode determination random number, fluctuation pattern random number, hit determination random number) related to the big winning lottery. A latched random value is obtained through the input ports (FE73h to FE9Ch).

The random number generator operates on a system clock (a clock obtained by dividing an external input by two) and generates random numbers less than a predetermined maximum value. In addition, the random number generator is a random number generator that can set the maximum value of random numbers.As a maximum value setting random number generator, the random number generator that can set the maximum value of 16 bits has 4 channels and the maximum value of 8 bits. Eight channels of configurable random number generator are provided. Here, for the 16-bit maximum value setting random number generator, the random number update cycle can be selected within the range of 32 to 47 clocks, and the maximum value setting range can be set within the range of 256 to 65,535. In addition, for the 8-bit maximum value setting random number generator, the random number update cycle can be selected in the range of 16 to 31 clocks, and the maximum value setting range can be set in the range of 16 to 255 for 4 channels, and for the other 4 channels. It can be set in the range of 64 to 255. In addition, as a maximum value fixed random number generator, which is a random number generator with a fixed maximum value, there are 4 channels of random number generators that can set a maximum value of 16 bits, and a random number generator that can set a maximum value of 8 bits. The device is equipped with 8 channels. Here, in the 16-bit maximum value fixed random number generator, the random number update period is fixed to 1 clock, and the maximum value is fixed to 65535. Further, in the 8-bit fixed maximum value random number generator, the random number update period is fixed to 1 clock, and the maximum value is fixed to 255.

In addition, if there are insufficient types of random numbers, the random number obtained from the hardware random number generator (random number generator) is multiplied by a predetermined number in the program, and other random numbers are generated by dividing. Random number generator) is also possible.

FIG. 101 is a diagram illustrating the configuration of a register. The register unit 716 is provided with a first register bank (bank 0) 726 and a second register bank (bank 1) 728 that is paired with the first register bank 726. Further, the first register bank 726 is provided with a main register group (front register group) 726a and a sub-register group (back register group) 726b paired with the main register group 726a, and the second register bank 728 is provided with: A main register group 728a and a sub-register group 728b paired with the main register group 728a are provided. The main register group 726a and sub-register group 726b of the first register bank 726, and the main register group 728a and sub-register group 728b of the second register bank 728 include 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY). However, unlike the sub-register groups 726b and 728b, the main register groups 726a and 728a further include an 8-bit register (U) and a 16-bit register (SP). The main CPUs 300a and 500a can switch and use the first register bank 726 and the second register bank 728, and can access only one register bank indicated by the register bank designation register RB in the F register, which will be described later. The other register bank cannot be accessed at the same time.

Among the registers shown in FIG. 101, the Q register is an 8-bit register that is provided as an extension register in two sets in each register bank and stores the upper byte of an address used in some commands. For example, when F0h is set as the value of the Q register, the main CPUs 300a and 500a can use the Q register to access F000h to F0FFh of the main RAM 300c. The U register is an 8-bit register that is provided as an extension register in each register bank and stores the upper byte of an address used in some commands. For example, if FEh is set as the value of the U register, the main CPUs 300a and 500a will use built-in devices (timers, random number generators, external input/output circuits, etc.) connected to the input/output section 704 of FE00h to FFFFh. The U register can be used to access. The A register is a general-purpose register that also functions as an 8-bit accumulator used for arithmetic processing and data transfer. The F register is an 8-bit flag register that holds various calculation results. Here, as shown in FIG. 101, each bit of the F register is from the most significant bit (MSB) to the least significant bit (LSB), and S is 1 when the operation result is negative. Z is a zero flag (first zero flag) that is set to 1 when all bits are 0 as a result of an operation, and TZ is a sign flag that is set to 1 when all bits are 0 as a result of an operation. , is a specific bit flag (second zero flag) of the extended specifications for gaming machines that is set to 1 (value changes) when all bits are 0, and is sometimes called a teaset flag. H is a half-carry flag that the programmer cannot interact with, and RB (register bank specification register) is a register bank monitor that indicates the current register bank (first register bank 726 = 0, second register bank 728 = 1). , P/V are parity overflow flags, N is an addition/subtraction flag that the programmer cannot interact with, and C is a carry flag that is set to 1 when a carry or borrow occurs as a result of an operation. Note that the F register constitutes a pair register AF with the A register.

In addition, the B register, C register, D register, E register, H register, and L register are 8-bit general-purpose registers provided in two sets in each register bank, and each register is a 16-bit pair whose combination is determined in advance. It is used by configuring registers (for example, there are registers BC, DE, HL, and other combinations). The IX register and IY register are 16-bit general-purpose registers used for index addressing. The SP (stack pointer) register is 16 bits and stores an address that becomes a stack pointer. Q' register, A' register, F' register, B' register, C' register, D' register, E' register, H' register, L' register, IX' register, IY' register are Q register, A register. , F register, B register, C register, D register, E register, H register, L register, IX register, and IY register with the main register group 726a, 728a by an exchange command or a transfer command to exchange data (contents) or transfer data. Possible sub-register groups 726b and 728b, the A' register and F' register constitute a pair register AF', the B' register and C' register constitute a pair register BC', and the D' register and E' register. The register DE' constitutes a pair register DE', and the register H' and L' constitute a pair register HL'. Note that the pair registers are not limited to BC', DE', and HL', and there are a plurality of other combinations. On the other hand, one set of U registers and SP registers are provided in each register bank.

By the way, as described above, in the main control boards 300 and 500, the main CPU 300a controls the progress of the game in cooperation with the main RAM 300c based on the program stored in the main ROM 300b. Programs for executing these functional units are arranged in predetermined areas (used areas) of the main ROM 300b and main RAM 300c.

FIG. 102 is an explanatory diagram showing a memory map. Note that since the memory map in the pachinko machine has already been explained using FIG. 5, the memory map of the slot machine 400 will be described here. The main ROM 500b is assigned a memory space of 0000h to 3FFFh (12 kbytes), the main RAM 500c is assigned a memory space of F000h to F3FFh (1 kbyte), and the input/output unit 704 is assigned a memory space of FE00h to FFFFh (512 bytes). Memory space is allocated. Note that the instruction code of the program is written in assembler language. Here, the program is composed of instruction codes, and can be read by a computer and cooperate with data and a work area to realize a predetermined process.

A usable area is allocated to the memory space from 0000h to 1DF3h of the main ROM 500b. The usage area is an area for storing programs and data for executing game control processing that controls the progress of the game. Specifically, in a memory space (control area) limited to 0000h to 11FFh (4.5 kbyte), initialization means 600, betting means 602, winning type lottery means 604, reel control means 606, determination means 608, and payout control are stored. The command code of the program for executing the game control process for controlling the progress of the game by functioning the means 610, the game state control means 612, the production state control means 614, and the command transmission means 616 is stored, Data used for the game control processing program is stored in a memory space (data area) limited to .0 kbyte). Further, a comment area is allocated to the memory space from 1E00h to 1FFFh, and a program management area is allocated to the memory space from 3FC0h to 3FFFh. Further, a separate area (unused area) is allocated to the memory space from 2000h to 3FBFh. The separate area is an area for storing programs and data that are not specified to be stored in the used area, as will be described later. Specifically, the memory space from 2000h to 3FBFh contains some or all of the gaming machine test processing and security-related processing that does not affect the progress of the game (hereinafter simply referred to as processing outside of gaming control). Stores the instruction code and program data of a program that executes the program. Here, the test process for gaming machines is the test process for the slot machine 400 described in the Connection Specifications for Testing Machines for Reel-Type Gaming Machines (Fourth Edition). Security-related processing is processing for identifying abnormal conditions for the purpose of preventing fraud by third parties and discovering defects, and includes, for example, the above-mentioned backup flag determination and checksum execution. Note that there is no limit to the storage capacity of the separate area, and in the example of FIG. 102, it can be freely allocated to storage areas other than the used area, comment area, and program management area.

As described above, the main CPU 500a may perform not only game control processing but also gaming machine test processing and security related processing (processing outside of gaming control). However, the storage capacity of the used area is predetermined, and for example, as shown in FIG. 102, the control area is limited to 4.5 kbytes and the data area is limited to 3.0 kbytes. Therefore, if programs and data for not only gaming control processing but also testing processing for gaming machines and security-related processing are allocated to the usage area, the storage area for performing gaming control processing will be limited accordingly. Here, the program (used program) and data for executing the game control process must be stored in the usage area, but the process outside of game control (game program) that does not affect the progress of the game other than the game control process Programs (separate programs) and data for executing (machine test processing, security related processing, etc.) can be stored in both the used area and the separate area. Therefore, at least part of the programs and data for executing backup flag determination processing and checksum execution processing, which correspond to security-related processing, are stored in a storage area different from the used area (other than the used area). It is written in a separate area that is part of my work.

In this way, if there is a mixture of processing performed in the used area (here, gaming control processing) and processing that does not necessarily need to be performed in the used area (here, security-related processing), gaming control processing Store the program (used program) and data for executing in the used area, and perform processing outside of gaming control (security-related processing) that does not affect the progress of the game other than gaming control processing, which does not need to be performed in the used area. It is desirable to store programs to be executed (separate programs) and data in separate areas. By dividing the storage area into a plurality of areas in this way, there is an extra storage area (capacity) in the used area for the program moved to another area. Therefore, it becomes possible to allocate the usage area to the game control process (usage program) accordingly.

However, even when the storage area is divided into a used area and a separate area as described above, the fairness of the gaming machine must be ensured. Therefore, the following conditions (1) to (6) are defined in order to ensure the fairness of the gaming machine and to appropriately divide the roles between the usage area and the separate area.

Condition (1): Programs placed in a separate area are used for the purpose of outputting signals necessary for testing gaming machines (gaming machine test processing) and preventing fraud (security-related processing), and are not intended to harm the fairness of gaming. It must not be damaged. Condition (2): The control area and data area, which are separate from the used area, must be placed in clearly separated areas. Condition (3): The program placed in a separate area (separate program) is statically called and executed from the program in the used area (use program). In addition, the call destination address must be clearly stated in the program list. Condition (4): Programs placed in separate areas should be modularized for each function, and when called, the contents of all registers used in the used area should be protected. Condition (5): RAM in each area can only be accessed from the used area or from another area, and cannot be updated. Condition (6): It is not possible to call a subroutine in the control area of the used area from the control area of another area. Note that since a subroutine for performing interrupt processing is provided in the used area, it is necessary to disable interrupts when using a control area in another area. In addition, in order to properly perform the gaming control process, the time from disabling interrupts to canceling the disabling of interrupts must be within the interval of interrupt processing in the gaming control process (for example, 1.49 msec). Must be. Therefore, when calling a subroutine that uses a control area in another area, the total time required for one call is set to be within the interval of the interrupt process of the game control process.

Further, a usable area is allocated to the memory space F000h to F1FFh of the main RAM 500c. Specifically, the memory space from F000h to F13Fh is assigned a work area for the game control process, and is used for managing variables such as timers, counters, and flags. A stack area for the game control process is allocated to the memory space F1C0h to F1FFh. Further, a separate area is allocated to the memory space of F200h to F3FFh of the main RAM 500c. Specifically, the memory spaces F210h to F22Fh are allocated work areas for some or all of the security-related processes, and are used for managing variables such as timers, counters, and flags. A stack area for some or all of the security-related processes is allocated to the memory spaces F230h to F246h.

Furthermore, an input/output unit 704 is allocated to the memory space of FE00h to FFFFh. Conventionally, in order to access the device corresponding to the input/output unit 704, a 512-byte I/O space was provided independent of the memory space. On the other hand, in this embodiment, the MREQ and IORQ signals are eliminated, and access to the memory and input/output unit 704 is shared by the RD and WR signals. Further, a U register is provided as hardware for specifying an upper 8-bit address for accessing a device connected to the input/output unit 704, and the 8-bit upper address is specified in advance. As a result, the I/O space that was provided independently from the memory space is integrated into the memory space and becomes one address space, and when an IN instruction or an OUT instruction is executed, the input/output unit 704 assigned to the memory space On the other hand, the upper 8 bits are specified by the U register, and the lower 8 bits can be accessed using the lower 8 bits specified by the operands of the IN and OUT instructions.

In this embodiment, the LDQ instruction uses the value of the Q register to access memory space (mainly data area, work area), and the IN and OUT instructions use the U register to access devices (timers, random number generators, external It becomes possible to write programs to access I/O of input/output circuits, etc. This configuration makes it easier to understand the program at the time of design. In addition, memory and I/O, which were previously accessed by specifying 16-bit addresses, can now be accessed using lower 8-bit operands, and program capacity can be compressed. Furthermore, by having multiple upper specification registers such as the Q register, Q' register, and U register, the number of replacements due to reuse of upper registers is reduced compared to when there is only one upper register, further reducing program capacity. be able to.

In the above example, the memory space corresponding to the I/O space is accessed by the IN command and the OUT command, but the memory space may be directly accessed by the IN command and the OUT command. For example, when accessing three 256-byte areas on memory, specify the upper 8 bits of each in the Q register, Q' register, and U register, and use the LDQ instruction, IN instruction, and OUT instruction respectively. This can be achieved by accessing the area.

(Display of game information)
By the way, in a gaming machine, for example, the slot machine 400, if the frequency of transition to the above-mentioned bonus game state or AT performance state is uneven, there is a concern that the gambling property may become excessively high. Therefore, in order to comprehensively and uniformly determine whether or not the gaming state with high medal acquisition performance is biased, we have determined the advantageous section ratio, the instruction-inclusive role ratio, the continuous role ratio, the role role ratio, the role model, etc. Establish judgment criteria such as condition ratio. The advantageous section ratio is the number of games stayed in the advantageous section from the first startup, divided by the total number of games, and is the value expressed as a percentage. The object ratio is the number of medals paid out with instructions, which is the number of medals paid out by the payout control means 610 based on the operation of the accessory and the operation of the instruction function, such as bonus games, during a predetermined standard aggregation period from the time of initial activation. , is the value divided by the total number of payouts, which is the total number of medals paid out by the payout control means 610, and is expressed as a percentage. , the number of continuous accessory payouts, which is the number of medals paid out by the payout control means 610 due to the operation of the first type special accessory, is divided by the total number of payouts, which is the total number of medals paid out by the payout control means 610, and the result is calculated as a percentage. The accessory ratio is the number of accessory payouts, which is the number of medals paid out by the payout control means 610 based on the operation of the accessory, such as a bonus game, during a predetermined standard aggregation period from the time of initial activation. is divided by the total payout number, which is the total number of medals paid out by the payout control means 610, and is expressed as a percentage. etc., the number of active games, which is the number of games in which the accessory was activated, is divided by the total number of games, which is the total number of games, and the value is expressed as a percentage. Note that the advantageous section ratio, instruction-inclusive accessory ratio, continuous accessory ratio, accessory ratio, and accessory status ratio are not cleared by changing settings.

The display of the advantageous section ratio, designated accessory ratio, continuous accessory ratio, accessory ratio, accessory state ratio, etc. is performed by the dynamic port output processing (SYNMOUT module) of the timer interrupt processing S3100 shown in FIG. 98. This is executed in the used area corresponding winning ratio display acquisition process (E_SDPST module) in S3100-7.

Here, the advantageous section refers to a section in which the player stays in all performance states except for some performance states (here, non-advantageous performance states) among the non-AT performance states. Note that a non-advantageous performance state may be referred to as a non-advantageous section in contrast to an advantageous section. However, the advantageous section is not limited to the AT effect state or the non-AT effect state, but may be arbitrarily set to any one of the game state and the effect state in which the game progresses advantageously for the player.

Further, the accessory is a device for facilitating winning, and includes a regular bonus (RB), a challenge bonus (CB), a single bonus (SB), and the like. Further, among these accessories, a regular bonus (RB) corresponds to the first type special accessory. In addition, the regular big bonus (RBB) is a regular bonus (RB) that operates continuously without depending on the display of the symbol combination that indicates the winning form of the regular bonus (RB), which is the first type special bonus. Challenge Big Bonus (CBB) is a type 2 special bonus (one of the bonuses), which is a challenge bonus (CB) that is continuous regardless of the display of the symbol combination that indicates the winning form of the challenge bonus (CB). It operates with. Therefore, the continuous accessory ratio represents the ratio of the number of continuous accessory objects paid out due to the operation of the first type special accessory to the total number of payouts in a predetermined standard aggregation period, and the accessory ratio represents the ratio of the number of paid out accessories due to the operation of the accessory to the total number of paid out in a predetermined reference aggregation period.

Note that the reference aggregation period is a target period for accumulating the number of medals paid out by the payout control means 610. In this embodiment, for example, there are two cases: 6000 games, which is a finite value, and the entire period after the slot machine 400 is installed in the gaming hall (hereinafter referred to as "total cumulative total"). Therefore, as the continuous accessory ratio, the continuous accessory ratio of 6000 games and the total cumulative consecutive accessory ratio are derived, and as the accessory ratio, the accessory ratio of 6000 games and the total cumulative accessory ratio. Derive . However, it goes without saying that any number of games can be set as the standard aggregation period.

In order to obtain the advantageous section ratio, the designated accessory ratio, the continuous accessory ratio, the accessory ratio, and the accessory state ratio, an accumulating means (not shown) calculates the total number of games, the number of staying games, and the number of activated items. The number of games played, the total number of payouts, the number of directed accessory payouts, the number of consecutive accessory payouts, and the number of accessory payouts are accumulated. At this time, a counter is associated with each of the total number of games, the number of staying games, the number of active games, the total number of payouts, the number of directed accessory payouts, the number of continuous accessory payouts, and the number of accessory payouts. Specifically, when one game is started, the accumulating means increments a total number of games counter indicating the total number of games by one. Then, it is determined whether the current game is a game in an advantageous section, and if it is a game in an advantageous section, a stay game number counter indicating the number of stay games is incremented by one. Incidentally, in the case of a non-advantageous period, the updating of the stay game number counter starts from the next game after the game in which the game won in the advantageous period (the game for which the transition process to the advantageous period was performed). However, if you win an advantageous section based on winning the Regular Big Bonus (RBB) or Challenge Big Bonus (CBB), the next game after the game in which the bonus was won (the game for which the transition process to the advantageous section was performed) It starts from. Further, it is determined whether or not the current game is a game in which an accessory has been activated, and if it is a game in which an accessory has been activated, an activated game number counter indicating the number of activated games is incremented by one.

Further, when medals are paid out in the game, the accumulating means increments a total payout number counter indicating the total number of payouts by the number of medals paid out. If the payout of the medal is based on the operation of the accessory and the operation of the instruction function, the instruction-included accessory payout number counter indicating the number of instruction-included accessory payouts is incremented by the number of coins to be paid out, and the medal is paid out. If the medal is based on an accessory, the accessory payout counter indicating the number of medals paid out is incremented by the number of medals paid out, and if the medal payout is based on the first type special accessory, the number of medals paid out is incremented by the number of medals paid out. A continuous accessory payout number counter indicating the number of accessory payouts is incremented by the number of coins to be paid out.

Note that the total cumulative total can be counted only with such a counter, but regarding the continuous accessory ratio and accessory ratio, it is necessary to cover not only the total cumulative total but also a limited period such as the standard aggregation period, here 6000 games. Must be. Therefore, the 6,000 games are divided equally into, for example, 400 games, and a plurality of counters (for example, 15) that count each 400 games are provided and used as a ring buffer. Here, an example is given in which 6000 games are divided and counted every 400 games, but it goes without saying that the number of games to be divided can be arbitrarily set as long as it is a factor (divisor) of 6000.

Specifically, when medals are paid out in the game, the accumulation means updates the total payout counter, the continuous accessory payout number counter, and the accessory payout number counter up to 400 games, and when it reaches 400 games, The total number of payouts, the number of continuous accessory payouts, and the number of accessory payouts are derived by adding up the 14 counters counted in the past. Then, among the 14 counters, the counter that was counted in the oldest game is initialized, and the initialized counter is used to newly set the total payout number counter, continuous accessory payout number counter, and accessory payout number counter for 400 games. Update. In this way, it is possible to refer to the game information for the new 400 games and the game information for the past 5,600 games every 400 games, so the total number of payouts, the number of continuous accessory payouts, It becomes possible to derive the number of items to be paid out. Note that counting by such a counter is always performed regardless of the specified number or set value. In this way, the total number of games, the number of staying games, the number of active games, the total number of payouts, the number of directed accessory payouts, the number of continuous accessory payouts, and the number of accessory payouts are accumulated.

Subsequently, the ratio deriving means (not shown) calculates the total number of games, the number of stay games, the number of active games, the total number of payouts, the number of instruction-included accessory payouts, the number of continuous accessory payouts, and the number of consecutive accessory payouts accumulated by the accumulation means. Based on the number of payouts, an advantageous section ratio, a designated accessory ratio, a continuous accessory ratio, an accessory ratio, and an accessory state ratio are derived. Specifically, the ratio deriving means divides the number of stay games by the total number of games, converts it into a percentage to derive an advantageous section ratio, and divides the total cumulative number of instruction-inclusive accessory payouts by the total cumulative number of payouts. , convert it into a percentage to derive the total cumulative instructional accessory ratio, divide the total cumulative number of consecutive accessory payouts by the total cumulative number of payouts, and convert it into a percentage to derive the total cumulative consecutive accessory ratio. , Divide the total cumulative number of accessory payouts by the total cumulative number of payouts, convert it into a percentage to derive the total cumulative accessory ratio, divide the number of active games by the total number of games, convert it into a percentage, and calculate the percentage. Derive the isostate ratio. In addition, the ratio deriving means divides the number of continuous accessory payouts in the 6000 games by the total number of payouts in the 6000 games every 400 games, converts the result into a percentage, derives the continuous accessory ratio in the 6000 games, and calculates the number of consecutive accessory payouts in the 6000 games. The number of payouts for objects is divided by the total number of payouts for the 6000 game, and the result is converted into a percentage to derive the accessory ratio for the 6000 game.

Next, the ratio display means (not shown) displays, based on a predetermined display command, the advantageous section ratio derived by the ratio derivation means, the designated accessory ratio, the continuous accessory ratio for the 6000 game, the accessory for the 6000 game. The ratio, the total cumulative continuous accessory ratio, the total cumulative accessory ratio, and the accessory status ratio are displayed on the ratio display section 860.

FIG. 103 is an explanatory diagram showing the appearance of the main control board 500. As shown in FIG. 103(a), a plurality of connectors 870 are provided on the end side of the main control board 500, and a ratio display section 860 is provided near the center of the main control board 500. The ratio display section 860 is configured by juxtaposing four seven segments consisting of seven segments that can represent decimal Arabic numerals and a dot segment (DP) located at the lower right of the seven segments. When the main control board 500 is installed in the slot machine 400, the main control board 500 is housed in the board case 872, and the main control board 500 is mounted on the front part 872a of the board case 872, as shown in FIG. 103(b). Fix it from the back with screws 874. A transparent window 872b through which the ratio display section 860 can be visually recognized is provided at a position corresponding to the ratio display section 860 on the front surface portion 872a of the board case 872. Therefore, as shown in FIG. 74, with the front upper door 404 open, the administrator can visually check the display content of the ratio display section 860 through the transparent window 872b. Note that instead of the transparent window 872b, the entire board case 872 may be made of a transparent or semi-transparent material.

Here, only the four 7 segments that make up the ratio display section 860 are used, such as the advantageous section ratio, the continuous role object ratio for the 6000 game, the role object ratio for the 6000 game, the total continuous role object ratio, and the total cumulative role object ratio. In order to display five pieces of game information such as, an identifier is associated with each ratio, and the ratio display section 860 sequentially displays the identifier and each ratio. Note that each ratio is indicated in a range of 0 to 99. Therefore, among the four 7-segments, the two 7-segments located on the left side represent the identifier, and the two 7-segments located on the right side represent the ratio.

FIG. 104 is an explanatory diagram for explaining the display mode of the ratio display section 860. When the power switch 444 is turned on, as shown in FIG. 104(a), the ratio display means displays "7U", which is an identifier corresponding to the advantageous section ratio, and its ratio, for example, "70"%, all at once. (so-called 7U type). Furthermore, depending on the slot machine 100, a designated accessory ratio may be displayed instead of the advantageous section ratio. In this case, the ratio display means displays "7P", which is an identifier corresponding to the designated accessory ratio, and its ratio, for example, "70"% (so-called 7P type). Here, in the 7U type, it is possible to conduct a lottery to shift to an advantageous section by referring to winning types with different settings, but it is not possible to conduct a lottery to shift to an advantageous section by directly referring to the setting value. . On the other hand, in the 7P type, it is possible to conduct a lottery to shift to an advantageous section by referring to both winning types with different settings and setting values. Note that the ratio display means separates the identifier from the ratio by lighting up the second 7-segment dot segment of the ratio display section 860.

In this state, when a predetermined time (for example, 5.0 sec) has elapsed, the ratio display means displays "6Y", which is an identifier corresponding to the continuous role object ratio of the 6000 game, and the ratio, as shown in FIG. 104(b). A certain “60”% is displayed at once. Then, each time a predetermined time elapses, a combination of "7Y", which is an identifier corresponding to the accessory ratio of the 6000 game, and "70"%, which is the ratio, as shown in FIG. 104(c), is created. A combination of “6A”, which is an identifier corresponding to the continuous role ratio of the total cumulative total, and “60”%, which is the ratio, as shown in FIG. 104(e), A combination of "7A", which is an identifier corresponding to the object ratio, and "70"%, which is the ratio, and "5H", which is an identifier corresponding to the state ratio of accessories, etc., as shown in FIG. 104(f), Combinations with that ratio of "50"% are sequentially displayed. In addition, as shown in FIG. 104(f), when the combination of "5H", which is an identifier corresponding to the state ratio of accessories, etc., and "50"%, which is the ratio, is displayed, a predetermined period of time is added. When the time elapses, the identifier "7U" corresponding to the advantageous section ratio and "70"%, which is the ratio shown in FIG. Displayed in the order of advantageous section ratio (instruction included accessory ratio), continuous accessory ratio for 6000 games, accessory ratio for 6000 games, total cumulative consecutive accessory ratio, total cumulative accessory ratio, and accessory status ratio. is switched.

Although an example has been described here in which the identifier and the ratio are displayed at the same time using four 7-segments, it is also possible to use only two 7-segments and switch between the identifier and the ratio. In this case, the ratio display section 860 displays, for example, "7U" → "70" → "6Y" → "60" → "7Y" → "70" → "6A" every time a predetermined time elapses. ” → “60” → “7A” → “70” → “5H” → “50”.

Note that the ratio display means displays the identifier and the ratio on the existing display parts (main credit display part 430 and main payout display part 432) corresponding to the four 7 segments instead of the ratio display part 860 of the main control board 500. You can also switch the display. In this case, after the result of one game is announced and before the start of the next game, the upper front door 404 is opened, and in this state, an operation is performed to set or change an existing switch, for example, a set value. By operating the switch, the identifier corresponding to the advantageous section ratio and its ratio are displayed, and from then on, every time a predetermined period of time passes, the advantageous section ratio (instruction included accessory ratio) → continuous accessory ratio of 6000 games The display will be repeatedly switched in the order of → 6000 game accessory ratio → total cumulative continuous accessory ratio → total cumulative accessory ratio → instruction-included accessory ratio. In addition, the ratio display means displays the advantageous section ratio (instruction-inclusive accessory ratio), continuous accessory ratio of 6000 games, accessory ratio of 6000 games, continuous accessory ratio of total cumulative value, total cumulative winning ratio on the existing display part. Even while the object ratio, accessory state ratio, etc. is being displayed, if there is a change in the state of the slot machine 400 such as the insertion of a medal, the display is deleted.

The administrator can display the advantageous section ratio, instruction-inclusive accessory ratio, continuous accessory ratio for 6000 games, accessory ratio for 6000 games, and total continuous accessory ratio through such a ratio display section 860 or an existing display section. , the total cumulative ratio of accessories, and the state ratio of accessories, etc., can be visually confirmed. Then, it is possible to determine whether the game information is within an appropriate range and to determine whether the slot machine 400 is operating properly.

Such appropriate ranges include, for example, advantageous section ratio <70%, instruction-inclusive accessory ratio <70%, continuous accessory ratio for 6000 games <60%, accessory ratio for 6000 games <70%, continuous total. The accessory ratio is set as <60%, the total cumulative accessory ratio is <70%, and the state ratio of accessory items, etc. is <50%. If the ratio is outside the appropriate range, the ratio display means may blink each segment of the ratio display section 860 at a cycle of, for example, 0.6 seconds regarding the target ratio. This blinking display allows the administrator to quickly grasp the identifiers that are out of the appropriate range and the ratio thereof.

By the way, as mentioned above, the ratio deriving means divides the number of stay games by the total number of games to derive the advantageous section ratio, and divides the total cumulative number of instruction-included accessory payouts by the total cumulative total number of payouts. Derive the total cumulative number of paid out accessories including instructions, divide the total cumulative number of consecutive accessory paid out by the total number of total paid out, derive the total cumulative number of consecutive accessory paid out, and calculate the total cumulative number of paid out accessories. The number is divided by the total cumulative number of payouts to derive the total number of paid out accessories, and the number of active games is divided by the total number of games to derive the state ratio of accessories, etc. However, the main CPU 500a in the main control board 500 has low processing power, and the multiplication instructions and division instructions that can be used by the main CPU 500a are limited in the range of multiplicands, multipliers, dividends, and numerical values used as divisors. For example, in the DIV instruction for executing division, which is prepared in advance as an arithmetic instruction in the main CPU 500a, the numerical range of both the dividend and the divisor may be limited to 2 bytes, that is, from 0 to 65535. In some cases, it may only be possible to handle up to a certain extent. In this case, if the total number of games is, for example, 175,000 games or more, the numerical value range will be exceeded, and the 2-byte DIV command cannot be simply used. In this case, a program that repeats addition and subtraction must be prepared separately, similar to when a person performs division by hand, resulting in an increase in processing load. Therefore, the present embodiment aims to obtain gaming information appropriately while suppressing an increase in processing load.

In addition, in the above, in the slot machine 400, for example, the advantageous section ratio, the instruction-inclusive accessory ratio, the consecutive accessory ratio of 6000 games, the accessory ratio of 6000 games, the total cumulative consecutive accessory ratio, and the total cumulative accessory ratio. The explanation has been given by giving an example in which game information such as a ratio, a state ratio of accessories, etc. is displayed on the ratio display section 860. In a pachinko machine, for example, the number of prize balls (low probability payout number, which is the number of payouts when the probability is low and there is no time saving) in a predetermined reference aggregation period, and the number of outs (the number of balls out when the probability is low and there is no time saving). The base value expressed in percentage may be displayed on the performance display monitor (ratio display section 860). Note that, unlike the slot machine 400, the base value in a pachinko machine is rounded off without rounding down to the nearest whole number.

(Derivation process of each ratio)
Here, we will explain several processing examples for deriving each ratio (advantageous interval ratio, instruction-inclusive accessory ratio, continuous accessory ratio, accessory ratio, accessory state ratio). The common parts are explained in detail. In this embodiment, values converted into percentages are finally calculated as the advantageous section ratio, the designated accessory ratio, the continuous accessory ratio, the accessory ratio, and the accessory state ratio. This indicates that only two decimal places are required for the division result. Furthermore, in the slot machine 400, values below the decimal point are rounded down when converted to a percentage. This means that if only two digits below the decimal point can be derived from the result of division, no calculations after the third digit after the decimal point are required. Therefore, in this embodiment, the result of division is multiplied by a predetermined multiplier (here, 100) in order to carry the division result forward by two digits. In addition, here, we gave an example of multiplying by "100" as a multiplier because only two digits of decimal point are required, but if three digits of decimal point are required, multiply by "1000" as a multiplier, etc. can be changed.

In addition, here, we will explain the "accessory ratio" as a target of the derivation process, but the same processing can be applied to the advantageous interval ratio, the instruction-inclusive accessory ratio, the continuous accessory ratio, and the accessory status ratio. Needless to say. As described above, the accessory ratio is derived by dividing the number of accessory objects paid out by the total number of payouts, and converting the result into a percentage. This point of "converting into %" corresponds to multiplying by a multiplier of "100". Therefore, it can be expressed by the following formula: accessory ratio = number of accessory items paid out/total number of paid items x 100. However, since the number of accessory payouts ≦ the total number of payouts, unless the number of accessory payouts = total number of payouts, in the order of this formula, the number of accessory payouts ÷ the total number of payouts will always be a value below the decimal point. For example, the main CPU 500a becomes unable to perform calculations.

Therefore, we changed the calculation order, and the order was as follows: Accessory object ratio = Number of paid objects × 100 ÷ Total number of paid objects, that is, first, the number of paid objects was multiplied by the multiplier (100), and then the result of multiplying by the multiplier (dividend ) is calculated in the order of dividing by the total number of payouts. By doing so, it becomes possible to complete the calculation result using only integers without performing calculations below the decimal point, and as a result, truncation after the decimal point can be easily realized.

FIG. 105 is a flowchart showing an example of calculating the accessory ratio. In the example of FIG. 105, the accessory ratio is derived assuming that the number of paid out accessories is "7123" and the total number of paid out is "10000." Here, for example, by replacing division with subtraction, division of numbers exceeding the numerical range (0 to 65535) is realized. The numerical values of step S in this figure will be used only in the explanation of this figure.

First, the ratio deriving means determines whether or not the number of accessory payouts is greater than the total number of payouts (S1). As a result, if it is determined that the number of paid out accessories is larger than the total number of paid out (YES in S1), it is determined that the number of paid out accessories or the total number of paid out is not an appropriate value, and the result that the ratio of accessories is abnormal. The calculation process is completed (S2). If it is determined that the number of accessory payouts is less than or equal to the total number of payouts (NO in S1), the ratio deriving means determines whether the total number of payouts is 0 (S3). As a result, if the total number of payouts is 0, that is, no medals have been paid out yet (YES in S3), the accessory ratio is determined to be 0% and the calculation process is ended (S4 ). If it is determined that the total number of payouts is not 0 (NO in S3), the ratio deriving means determines whether or not the number of accessory payouts is equal to the total number of payouts (S5). As a result, if it is determined that the number of accessory payouts and the total number of payouts are equal (YES in S5), the accessory ratio is determined to be 99% and the calculation process is ended (S6). In this manner, in this embodiment, when the number of paid out accessories is equal to the total number of paid out, the accessory ratio is expressed as 99% instead of 100%. By doing this, it becomes possible to express all the accessory ratios in two digits.

If it is determined that the number of paid out accessories and the total number of paid out are not equal (NO in S5), the ratio derivation means multiplies the number of paid out accessories "7123" by a multiplier "100" (= "712300"), and calculates the dividend. (S7). Subsequently, the ratio deriving means divides the dividend number "712300" by the total payout number "10000" which is the divisor to obtain a quotient (="71") (S8). This quotient "71" becomes the accessory ratio. This corresponds to the integer part of 71.23%, which is the result of dividing the number of paid out accessories "7123" by the total number of paid out "10000" and converted into a percentage, so it can be understood that this calculation is correct.

With such a calculation example of the accessory ratio, it becomes possible to realize division using only simple calculations such as addition, subtraction, and multiplication, and using only integers.

In addition, in the above, it is assumed that the fraction below the decimal point of the accessory ratio is rounded down, but this is not limited to such a case. When rounding the fraction below the decimal point of the accessory ratio, the final dividend value that becomes negative (here, " This can be realized by rounding down if the absolute value of ``-7700'' is greater than 1/2 of the divisor (total number of payouts, here ``10000''), and rounding up if it is less than 1/2.

Here, we will further explain the two-step calculation procedure when calculating the accessory ratio, that is, the calculation of the number of accessory objects paid out x the multiplier (S7 in FIG. 105), and the calculation of the multiplication result divided by the total number of payouts (S8 in FIG. 105). We will search for effective calculation procedures. Specifically, first, we will examine the effectiveness of multiple calculation procedures that execute the number of accessory payouts x multiplier, and then examine the effectiveness of multiple calculation procedures that execute the multiplication result ÷ total number of payouts.

(Number of accessories paid out x multiplier)
When expressing the number of accessory payouts as a numerical value, the maximum value is 3 bytes due to the numerical range, and 3 bytes (24 bits) are required as memory capacity. Furthermore, since the multiplier is 100 here, it can be represented by 1 byte (8 bits). Then, the calculation of the number of paid out accessories x multiplier becomes a 24-bit x 8-bit calculation. Here, the main CPU 500a can execute a 24-bit x 8-bit operation using an 8-bit MUL instruction that can obtain a 16-bit operation result by performing an 8-bit x 8-bit multiplication.

Furthermore, as described above, the main CPU 500a has built-in multipliers and dividers that can execute calculations independently and in parallel with the main CPU 500a as built-in devices. Here, the multiplier performs, for example, 16-bit x 16-bit multiplication in parallel with command processing, and writes the multiplicand to the specified address (multiplicand setting register) of the built-in register, and writes the multiplicand to the other specified address. When a multiplier is written to the multiplier setting register, multiplication is executed in the multiplier, and after a predetermined period of time, a 32-bit multiplication result is set to a different specified address (multiplication result register). . In addition, the divider performs, for example, 32 bits/32 bits division in parallel with command processing, and writes the dividend to a specified address (dividend setting register) in the built-in register, and writes the dividend to another specified address ( When a divisor is written to the divisor setting register, division is executed in the divider, and after a predetermined period of time, a 32-bit division result is set in a different specified address (division result register). Therefore, in addition to the above-mentioned 8-bit MUL instruction, the main CPU 500a can employ a 16-bit x 16-bit multiplier (hereinafter simply referred to as a 16-bit multiplier).

Here, a first calculation example using only an 8-bit MUL instruction and a second calculation example using a 16-bit multiplier will be given and their effectiveness will be compared.

(First calculation example of executing number of accessory payouts x multiplier)
FIG. 106 is an explanatory diagram for explaining a first calculation example using only 8-bit MUL instructions. In the first calculation example using only the 8-bit MUL instruction, the multiplicand (3 bytes) x multiplier (1 byte) is calculated, so the multiplicand is stored in the BCD register (BC register and D Using an 8-bit MUL instruction, the value of the D register, the value of the C register, and the value of the B register separated into 1-byte units are multiplied by a multiplier (100) in that order. Then, by adding (integrating) the multiplication results of the D register value x 100, the C register value x 100, and the B register value x 100, the calculation result of the BCD register value x 100 (4 bytes ) can be obtained.

FIG. 107 is a flowchart showing specific processing for realizing the first calculation example, and FIG. 108 is a diagram showing an example of specific commands for realizing the first calculation example. be. The numerical values in step S in the explanation of FIG. 107 will be used only in the explanation of this figure.

As shown in FIG. 107, first, the value of the cumulative accessory counter is read into the BCD register (S1). Specifically, the command "LD A, (_EX_YAKR)" on the second line in FIG. , A", the value of the A register is copied to the D register, and the fourth line command "LD BC, (_EX_YAKR+1)" reads the 2-byte value stored at the address "_EX_YAKR+1" to the BC register.

Next, as shown in FIG. 107, it is determined whether the value of the cumulative accessory counter stored in the BCD register is 0 (S2), and if it is 0 (YES in S2), even if the value is multiplied by the multiplier. Since the result does not change (because it is 0), the first operation example is ended. Specifically, the command "OR A, B" on the 5th line of FIG. 108 calculates the logical sum of the value of the A register and the value of the B register, which is equal to the value of the D register, and the command "OR A, B" on the 6th line of FIG. The command "OR A, C" calculates the logical sum of the value of the A register and the value of the C register, which is the result of the operation on the 5th line, and the command "JR Z, E_PYSAV28" on the 7th line calculates the logical sum of the BCD register. If the logical sum is 0, the process moves to the index "E_PYSAV28" (not shown) indicating another process. Note that if the processing differs depending on the contents of the F register, such as the command "JR Z, E_PYSAV28", the number of cycles will also differ. For example, if the command "JR Z, E_PYSAV28" involves movement, it will take 3 cycles as shown to the left of the slash in the number of cycles in Figure 108, and if it does not involve movement, it will take 2 cycles as shown to the right of the slash in the number of cycles. It becomes a cycle. The following commands are also displayed in the same way if the processing differs depending on the contents of the F register.

Subsequently, as shown in FIG. 107, the value of the D register, which is the least significant byte of the multiplicand, is multiplied by a multiplier (100) (S3), and the result of the operation is set in the DE register (S4). Specifically, the command "LD A, D" on the 8th line of FIG. 108 copies the value of the D register to the A register, and the command "MUL HL, A, 100" on the 9th line copies the value of the A register. The result of multiplying by 100 is held in the HL register, and the value of the HL register is set in the DE register by the command "EX DE, HL" on the 10th line.

Next, as shown in FIG. 107, the value of the C register, which is the middle byte of the multiplicand, is multiplied by the multiplier (100) (S5), and the result of adding the value of the D register to the operation result is returned to the D register. (S6), and set in the main RAM 500c (S7). Specifically, the command "LD A, C" on the 11th line of FIG. 108 copies the value of the C register to the A register, and the command "MUL HL, A, 100" on the 12th line copies the value of the A register. The result of multiplying by 100 is held in the HL register, and the command "ADDWB HL,D" on the 13th line stores the DE set in the HL register of the multiplication result by the command "EX DE, HL" on the 10th line. Only the upper 1 byte (value of D register) of the registers is added, and the lower 1 byte of the addition result is returned to the D register by the command "LD D, L" on the 14th line, and the command "LD D, L" on the 15th line is added. EX DE, HL" moves the value of the DE register corresponding to the lower 2 bytes of the multiplication result to the HL register, and the command "LD (_EX_WRK2), HL" on the 16th line addresses the 2-byte value of the HL register. Store in "_EX_WRK2".

Next, as shown in FIG. 107, the value of the B register, which is the most significant byte of the multiplicand, is multiplied by the multiplier (100) (S8), and the result of the operation is multiplied by the upper 1 byte (H register value) (S9), and sets it in the main RAM 500c (S10). Specifically, the command "LD A, B" on the 17th line of FIG. 108 copies the value of the B register to the A register, and the command "MUL HL, A, 100" on the 18th line copies the value of the A register. The result of multiplying by 100 is held in the HL register, and the command "ADDWB HL,D" on the 19th line stores the DE set in the HL register of the multiplication result by the command "EX DE, HL" on the 15th line. Add only the upper 1 byte (value of the D register) of the register (the calculation result of the command "ADDWB HL, D" on the 13th line), and add the HL by the command "LD (_EX_WRK2+2), HL" on the 20th line. Store the 2-byte value of the register at address "_EX_WRK2+2". In this way, the calculation result of the value of the 4-byte BCD register x 100 can be obtained at the address "_EX_WRK2".

Here, in this command example, as shown in FIG. 108, the total command size is 38 bytes, and the simple total number of cycles (simply totaling the number of cycles without considering movement commands) is 49/48. It becomes a cycle.

(Second calculation example of executing number of accessory payouts x multiplier)
FIG. 109 is an explanatory diagram for explaining a second calculation example using a 16-bit multiplier. In the second operation using a 16-bit multiplier, the multiplicand (3 bytes) x multiplier (1 byte) is calculated, so the multiplicand is stored in the BCD register (BC register and D register) as shown in Figure 109. Then, multiply the value of the BC register (2-byte value) and the multiplier (100) using a 16-bit multiplier, and multiply each value of the D register and the multiplier (100) using an 8-bit MUL instruction. . Then, as a result of the multiplication, by adding the value of the BC register x 100 and the value of the D register x 100, it is possible to obtain the calculation result of the value of the 4-byte BCD register x 100.

FIG. 110 is a flowchart showing specific processing for realizing the second example of calculation, and FIG. 111 is a diagram showing an example of specific commands for realizing the second example of calculation. be. The numerical values in step S in the explanation of FIG. 110 will be used only in the explanation of this figure.

As shown in FIG. 110, first, the value of the cumulative accessory counter is read into the BCD register (S1). Specifically, the command "LD A, (_EX_YAKR)" on the second line in FIG. 111 reads the 1-byte value stored at the address "_EX_YAKR" into the A register, and the command "LD , A", the value of the A register is copied to the D register, and the fourth line command "LD BC, (_EX_YAKR+1)" reads the 2-byte value stored at the address "_EX_YAKR+1" to the BC register.

Next, as shown in FIG. 110, it is determined whether the value of the cumulative accessory counter stored in the BCD register is 0 (S2), and if it is 0 (YES in S2), even if the multiplier is Since the result does not change (because it is 0), the second operation example is ended. Specifically, the command "OR A, B" on the 5th line of FIG. 111 calculates the logical sum of the value of the A register, which is equal to the value of the D register, and the value of the B register, and the command "OR A, B" on the 6th line of FIG. The command "OR A, C" calculates the logical sum of the value of the A register and the value of the C register, which is the result of the operation on the 5th line, and the command "JR Z, E_PYSAV28" on the 7th line calculates the value of the BCD register. If the logical sum is 0, the process moves to the index "E_PYSAV28" (not shown) indicating another process.

Subsequently, as shown in FIG. 110, the upper two bytes of the multiplicand are set in the multiplicand setting register (S3), the multiplier (100) is set in the multiplier setting register, and multiplication is executed (S4). Specifically, the command "LD (@MULA16_), BC" on the 8th line in FIG. 111 sets the value of the BC register in the multiplicand setting register "@MULA16_", and the command "LD A, 100" on the 9th line sets the multiplier "100" to the A register, and the command "OUT (LOW @MULB16_), A" on the 10th line sets the value of the U register to the upper 1 byte of the address, and sets the address "@MULB16_" to the lower 1 byte. byte, and outputs the value of the A register to the multiplier setting register indicated by that address. Note that "00H" is set as a default value in the upper one byte of the multiplier setting register "@MULB16_". In this way, the 16-bit multiplier is operated and the multiplication result is stored in the multiplication result register.

Next, as shown in FIG. 110, the value of the D register, which is the least significant byte of the multiplier, is multiplied by the multiplier (100) (S5). Specifically, the command "LD A, D" on the 11th line of FIG. 111 copies the value of the D register to the A register, and the command "MUL HL, A, 100" on the 12th line copies the value of the A register. The result of multiplying by 100 is held in the HL register.

Subsequently, as shown in FIG. 110, the lower 3 bytes of the multiplication result stored in the multiplication result register are read to the DEA register (S6), and the value of the A register and the upper 1 byte (H register value) (S7), and sets it in the main RAM 500c (S8). Specifically, the command "IN A, (LOW @MUL32__+0" on the 13th line in FIG. 111) sets the value of the U register to the upper 1 byte of the address, sets the address "@MULB32__+0" to the lower 1 byte, and sets the value indicated by that address. Read the value of the multiplication result register to the A register, and read the second and third bytes from the bottom of the multiplication result register to the DE register by the command "LD ED, (LOW @MUL32__+1") on the 14th line, The second command "ADD A, H" adds the upper 1 byte (value of the H register) of the multiplication result set by the command "MUL HL, A, 100" on the 12th line to the value of the A register, The command "LD H, A" on the 16th line returns the addition result (value of the A register) to the H register, and the command "OUT (LOW @DIVA32_+0), HL" on the 17th line sets the value of the U register to the address. and the address "@DIVA32_" as the lower one byte, and outputs the value of the HL register to the dividend setting register "@DIVA32_" indicated by that address.

Next, as shown in FIG. 110, the value of the DE register set in step S6 is copied to the HL register (S9), and it is determined whether the value was carried up in the addition of step S7 (S10). If so (YES in S10), the carried amount is added to the HL register (S11) and set in the main RAM 500c (S12). Specifically, the command "EX DE, HL" on the 18th line in FIG. ADD A,H" determines whether the carry flag is set. If the carry flag is not set, move to the index "E_PYSAVX1" on the 21st line. If the carry flag is set, execute the command on the 20th line. By "INC HL", the value of the HL register is incremented by 1, and by the command "OUT (LOW @DIVA32_+2), HL" on the 22nd line, the value of the U register is set to the upper 1 byte of the address, and the address is "@DIVA32_+2". is set as the lower 1 byte, and outputs the value of the HL register to the divisor setting register indicated by that address.

Here, in this command example, as shown in FIG. 111, the total command size is 43 bytes, and the simple total number of cycles is 59/57 cycles.

As explained above, when comparing the first calculation example that executes the number of accessory payouts x multiplier with the second calculation example that executes the number of accessory payouts x multiplier, we find that the total command size and the number of cycles are simple. All of the sums are smaller in the first calculation example. Therefore, when executing the number of paid out accessories x multiplier in the slot machine 400, it is preferable to execute only with an 8-bit MUL instruction, as explained using FIGS. 106 to 108.

Note that in the first calculation example described above, the command "LD" was used as the command on the 16th line and the 20th line in FIG. Therefore, the command "OUT" may be used as the command on the 16th and 20th lines. In the case of FIG. 112, as in FIG. 108, the total command size is 38 bytes, and the simple total number of cycles is 49/48 cycles.

(Multiplication result ÷ total number of payouts)
Next, among the multiple steps of the calculation procedure when calculating the accessory ratio, the effectiveness of the multiplication result (number of accessory objects paid out x multiplier) divided by the total number of payouts will be examined. As described above, the multiplication result of the number of accessory payouts (3 bytes) x the multiplier (1 byte) is a maximum of 4 bytes, so the memory capacity requires 4 bytes or more. Therefore, here, the multiplication result is expressed in 4 bytes (32 bits). Furthermore, since the maximum value of the total number of payouts is 3 bytes, a memory capacity of 3 bytes or more is required. Therefore, the total number of payouts is also expressed in 4 bytes. Then, the calculation of multiplication result/total number of payouts becomes 32 bits/32 bits. The main CPU 500a repeatedly subtracts the total number of payouts from the multiplication result, and can realize the calculation of 32 bits/32 bits by the number of subtractions.

However, in the method of simply repeatedly subtracting the total payout number from the multiplication result, the total payout number must be subtracted from the repeated multiplication result a number of times corresponding to the accessory ratio. In this case, the subtraction process will be executed a maximum of 100 times. Therefore, it is conceivable to reduce the number of times of subtraction processing by multiplying the total number of payouts, which is a divisor, by an integer and subtracting the result. For example, if the number of paid out accessories is "7123" and the total number of paid out is "10000", the total number of paid out "10000" is not simply subtracted from the multiplication result "712300" which is the dividend, but the total number of paid out " By subtracting "100000" obtained by multiplying "10000" by the integer "10", "7" corresponding to the second digit (10's digit) of the accessory ratio can be derived. In addition, by subtracting the original total payout number "10000" from the updated (subtracted) multiplication result, "1" corresponding to the first digit (1's digit) of the accessory ratio can be derived. can. In this way, by multiplying the total number of payouts (divisor) by an integer, it is possible to reduce the number of subtraction processes to at most 20 times.

However, since the main CPU 500a performs calculations using binary numbers, the number "2" corresponding to a binary number carry is used here instead of the number "10" corresponding to a decimal number carry. Therefore, here, from the multiplication result "712300", we subtract the number obtained by multiplying the total number of payouts "10000" by a predetermined integer "64 (2 to the 6th power)", which is a power of 2. "32 (2 to the 5th power)" → "16 (2 to the 4th power)" → "8 (2 to the 3rd power)" → "4 (2 to the 2nd power)" → "2 (2 to the 1st power)" → Change the order of "1 (2 to the 0th power)", multiply by the total number of payouts, and subtract from the multiplication result. Here, the integer to be multiplied by the total payout number starts from 64, which is a power of 2, because the accessory ratio falls within the range of 0 to 99. This is because there is no need to subtract numbers.

Further, as described above, the main CPU 500a includes, for example, a 32-bit/32-bit divider (hereinafter simply referred to as a 32-bit divider). Therefore, in the main CPU 500a, instead of repeatedly subtracting the total number of payouts multiplied by a power of 2 from the above multiplication result (hereinafter simply referred to as repeated subtraction of the number multiplied by a power of 2), A 32-bit divider can be employed.

Here, a third calculation example using repeated subtraction of a number multiplied by a power of 2 and a fourth calculation example using a 32-bit divider will be given and their effectiveness will be compared.

(Third calculation example of executing multiplication result ÷ total number of payouts)
FIG. 113 is an explanatory diagram for explaining a third calculation example using repeated subtraction of a number multiplied by a power of two. In the third calculation example using repeated subtraction of a number multiplied by a power of 2, an example of calculation of the multiplicand (4 bytes) which is the multiplication result/divisor (4 bytes) which is the total payout number is shown. Here, it is assumed that the dividend is "712300" and the divisor is "64×10000", which is the original divisor "10000" multiplied by 64.

As shown in FIG. 113, if it is determined in the first judgment that the dividend ≧ the divisor, the divisor can be subtracted from the multiplicand. The dividend is updated to "72300" and "64" is added to the quotient "0" to update the quotient to "64 (1000000B expressed in binary)". In the second to fourth judgments, the dividend is less than the divisor, so the divisor is not subtracted. In the fifth judgment, if it is determined that the dividend ≧ the divisor, the ratio deriving means subtracts the divisor “4×10000” from the dividend “72300” to update the dividend to “32300”, and also updates the dividend to quotient “64”. Add "4" to update the quotient to "68 (1000100B in binary)". Similarly, in the sixth judgment, if it is determined that the dividend ≧ the divisor, the ratio deriving means subtracts the divisor “2×10000” from the dividend “32300” to update the dividend to “12300”, and the quotient “ 68'' and ``2'' to update the quotient to ``70 (1000110B in binary)''. In the seventh judgment, if it is determined that the dividend ≧ the divisor, the ratio deriving means subtracts the divisor “1×10000” from the dividend “12300” to update the dividend to “2300”, and also changes the quotient to “70”. Add "1" to update the quotient to "71 (1000111B in binary)".

If you repeat the subtraction step and addition step 7 times from an integer = "64", the integer will be rounded down to 0 (<1), so the arithmetic processing will be completed and the accessory ratio will be the quotient at that point. It becomes "71". This corresponds to the integer part of 71.23%, which is the result of dividing the number of paid out accessories "7123" by the total number of paid out "10000" and converted into a percentage, so it can be understood that this calculation is correct.

FIG. 114 is a flowchart showing specific processing for realizing the third example of calculation, and FIG. 115 is a diagram showing an example of specific commands for realizing the third example of calculation. be. The numerical values in step S in the explanation of FIG. 114 will be used only in the explanation of this figure. Here, it is assumed that an address "_EX_WRK1" storing a 4-byte divisor and an address "_EX_WRK2" storing a 4-byte dividend are arranged consecutively.

As shown in FIG. 114, first, the quotient is initialized to 0, the integer (power of 2) is initialized to 64 (S1), the upper 2 bytes of the dividend and the upper 2 bytes of the divisor are read (S2), and the upper 2 bytes of the dividend are read. It is determined whether the 2 bytes are less than the upper 2 bytes of the divisor (S3). If the upper two bytes of the dividend are less than the upper two bytes of the divisor (YES in S3), the process moves to step S10. Specifically, the command "XOR A, A" on the first line of FIG. 115 sets "0" in the A register indicating the quotient, and the command "LD C, 64" on the second line sets the C register indicating the integer. Set "64" and use the command "LD HL,_EX_WRK2+2" on the fourth line to add 2 to the value of the address "_EX_WRK2" that stores the dividend (the multiplication result of the number of paid out accessories x multiplier) ( The value of the upper 2 bytes) is read to the HL register, and the command "LD DE, (HL-4)" on the 5th line reads the address "_EX_WRK1" located 4 bytes lower than the address "_EX_WRK2" that stores the dividend. Read the upper 2 bytes of the divisor stored in the DE register, and use the command "JCP C, (HL), DE, E_PYSAV27" on the 6th line to read the value of the address indicated in the HL register (the upper 2 bytes of the dividend) and , the value of the DE register (the upper 2 bytes of the divisor) is compared, and if the carry flag is set, that is, if the upper 2 bytes of the dividend are less than the upper 2 bytes of the divisor, the index "E_PYSAV27" on the 20th line is compared. ”.

Next, as shown in FIG. 114, if the upper 2 bytes of the dividend are greater than or equal to the upper 2 bytes of the divisor (NO in S3), the lower 2 bytes of the dividend and the lower 2 bytes of the divisor are read for subsequent calculations. (S4), it is determined whether the upper two bytes of the dividend and the upper two bytes of the divisor are not equal, that is, whether the upper two bytes of the dividend are larger than the upper two bytes of the divisor (S5). If the upper two bytes of the dividend and the upper two bytes of the divisor are not equal (YES in S5), the process moves to step S8. Specifically, the command "LD HL,_EX_WRK1" on the 7th line in FIG. HL+4)'' reads the lower 2 bytes of the dividend stored at the address "_EX_WRK2" located 4 bytes above the address "_EX_WRK1" storing the divisor into the DE register, and the command "JR NZ, If the zero flag is not set by executing the command on the 6th line, the index moves to the index ``E_PYSAV26'' on the 12th line.

Next, as shown in FIG. 114, it is determined whether the lower two bytes of the dividend read in step S4 are larger than the lower two bytes of the divisor (S6), and the lower two bytes of the dividend are larger than the lower two bytes of the divisor. If the lower two bytes of the divisor are less than or equal to the lower two bytes of the divisor (NO in S6), then in step S6, the lower two bytes of the dividend and the lower two bytes of the divisor are It is determined whether they are not equal, that is, whether the lower two bytes of the dividend are less than the lower two bytes of the divisor (S7). If the lower two bytes of the dividend and the lower two bytes of the divisor are not equal (YES in S7), the process moves to step S10. Specifically, the command "JCP C, (HL), DE, E_PYSAV26" on the 10th line of FIG. (lower 2 bytes) and if the carry flag is set, that is, if the lower 2 bytes of the dividend are larger than the lower 2 bytes of the dividend, move to the index "E_PYSAV26" on the 12th line, and move to the index "E_PYSAV26" on the 11th line. The command "JR NZ, E_PYSAV27" moves to the index "E_PYSAV27" on the 20th line if the zero flag is not set by executing the command on the 10th line.

Next, as shown in FIG. 114, if the dividend is greater than or equal to the divisor, the current integer is added to the quotient (S8), the divisor is subtracted from the dividend, and the subtraction result is updated as a new dividend ( S9). Specifically, the command "ADD A, C" on the 13th line of FIG. ”, the value of the lower 2 bytes of the divisor stored at the address indicated by the HL register is subtracted from the value of the DE register where the lower 2 bytes of the dividend are stored, and the DE register is updated, and the command on the 15th line "LD (HL+4), DE" stores the lower 2 bytes of the updated dividend, which is the result of subtraction, at the address indicating the dividend located 4 bytes above the address that stores the divisor indicated by the HL register. , the command "LD DE, (HL+2)" on the 16th line reads the upper 2 bytes of the divisor stored at the address indicated by the HL register into the DE register, and the command "LD HL, (HL+6)" on the 17th line reads the high-order 2 bytes of the dividend located 6 bytes above the address storing the divisor indicated in the HL register to the HL register, and the command "SBC HL,DE" on the 18th line reads the high-order 2 bytes of the dividend. The value of the DE register in which the upper two bytes of the divisor are stored is subtracted from the value in the DE register in which the upper two bytes of the divisor are stored, and the HL register is updated. The upper two bytes of the updated dividend, which is the result of the subtraction, are stored in the upper two bytes of the dividend indicated by "_EX_WRK2".

Next, as shown in FIG. 114, the divisor is divided by 2 (bit shifted to the right) and updated as a new divisor (S10), the integer is divided by 2 (bit shifted to the right), and the new integer is It is updated (S11), and it is determined whether the integer is not 0 (S12). If it is not 0 (YES in S12), the process from step S2 is repeated, and if it is 0 (NO in S12), the accessory The ratio is set in the main RAM 500c (S13), and the process of repeatedly subtracting the number multiplied by the power of 2 is completed. Specifically, the command "LD HL,_EX_WRK1+3" on the 21st line in FIG. The value of the address indicated by the HL register (4th byte of the divisor) is bit-shifted by 1 to the right, and the command "DEC HL" on the 23rd line decrements the value of the HL register by 1, and the command on the 24th line "RR (HL)" shifts the value of the address indicated in the HL register (3rd byte from the lowest of the divisor) by 1 bit to the right, and the command "DEC HL" on the 25th line changes the value of the HL register to 1. The command "RR (HL)" on the 26th line shifts the value of the address indicated in the HL register (the second byte from the bottom of the divisor) to the right by 1, and the command "DEC HL" on the 27th line ”, the value of the HL register is decremented by 1, and the command “RR (HL)” on the 28th line shifts the value of the address indicated by the HL register (the lowest 1 byte of the divisor) to the right by 1, The command "SRL C" on the 29th line shifts the value of the C register indicating an integer by 1 bit to the right, and the command "JR NZ, E_PYSAV25" on the 30th line sets the zero flag by executing the command on the 29th line. If not, move to the index "E_PYSAV25" on the third line, and store the value of the A register, which is the quotient, at the address "_EX_DPA7" by "LD (_EX_DPA7), A" on the 32nd line.

With this third operation example, it becomes possible to realize division using only simple operations such as addition, subtraction, and multiplication, and using only integers. Furthermore, since it is sufficient to repeat the subtraction and addition processes seven times, the arithmetic processing can be performed quickly. Furthermore, if it is assumed that the fractions below the decimal point of the accessory ratio are rounded down, no errors will occur, so it is possible to accurately derive the accessory ratio.

Here, in this command example, as shown in FIG. 115, the total command size is 59 bytes, and the simple total number of cycles is 95/90 cycles. Moreover, the actual number of cycles is as follows. That is, in this process, the command from the command next to the index "E_PYSAV25" (line 4) to the command immediately before the index "E_PYSAV28" (line 30) is looped seven times. At this time, in all seven loops, if the command "JCP C, (HL), DE, E_PYSAV27" on the 6th line moves to the index "E_PYSAV27", the commands on the 7th to 19th lines will not be executed. , the number of cycles is the minimum 321 (3+45 (first 6 loops)×6+44 (7th loop)+4) cycles. On the other hand, in all loops, if the command "JCP C, (HL), DE, E_PYSAV27" on the 6th line does not move to the index "E_PYSAV27", the number of cycles becomes the maximum. However, considering that the ratio of accessories will not exceed 100% and that the processing load will be maximum at 95% and 63%, the maximum number of cycles will be 566 (3 + 61 (first loop) + 83 (remaining 6 loop)×6+4) cycle. Therefore, the effective total number of cycles ranges from 321 to 566 cycles.

Here, too, it is assumed that the fraction below the decimal point of the accessory ratio is rounded off, but this is not limited to this case. When rounding off the fraction below the decimal point of the accessory ratio, the subtraction and addition processes are repeated eight times, and the eighth judgment is performed. This can be realized by adding 1 to the quotient if it is determined that the dividend≧the divisor.

(Fourth calculation example of executing multiplication result ÷ total number of payouts)
FIG. 116 is a flowchart showing specific processing for realizing the fourth example of calculation, and FIG. 117 is a diagram showing an example of specific commands for realizing the fourth example of calculation. be. The numerical values in step S in the explanation of FIG. 116 will be used only in the explanation of this figure. Here, as explained using FIG. 112, it is assumed that the dividend, which is the result of multiplying the number of paid out accessories x the multiplier, has already been set in the dividend setting register "DIVA32".

As shown in FIG. 116, first, the value of the cumulative accessory counter is called into the register and set in the divisor setting register "DIVB32" (S1). Specifically, the command "LD HL, (_EX_PRZR)" in the first line of FIG. 117 reads the value stored in the address "_EX_PRZR" indicating the cumulative accessory counter to the HL register, and The command "LD A, (_EX_PRZR+2)" reads the value stored in the address "_EX_PRZR+2" indicating the upper 1 byte of the cumulative accessory counter to the A register, and the command "OUT (LOW @DIVB32_+0) on the third line ), HL", the value of the U register is set as the upper 1 byte of the address, the address "@DIVB32_" is set as the lower 1 byte, the value of the HL register is output to that address, and the command "OUT (LOW @DIVB32_+2), A" sets the value of the U register as the upper 1 byte of the address, sets the address "@DIVB32_+2" as the lower 1 byte, and outputs the value of the A register to that address. Note that "00H" is set as a default value in the upper one byte of the divisor setting register "@DIVB32_".

Next, as shown in FIG. 116, the CPU waits for the division time (S2), and after a predetermined time has elapsed, the calculation result is set in the main RAM 500c (S3). Specifically, the command "NOP" on the 5th to 8th lines in FIG. The value of the division result register indicated by that address is read into the A register, and the quotient is stored in the A register by "LD (_EX_DPA7), A" on the 11th line. The value of is stored in the address "_EX_DPA7".

Here, in this command example, as shown in FIG. 117, the total command size is 20 bytes, and the total number of cycles is 28 cycles.

As explained above, when comparing the third calculation example that executes the multiplication result ÷ total number of payouts with the fourth calculation example that executes the multiplication result ÷ total number of payouts, the total command size and the total number of cycles Both are smaller in the fourth calculation example. Therefore, when calculating the multiplication result divided by the total number of payouts in the slot machine 400, it is preferable to use a 32-bit divider as described with reference to FIGS. 116 and 117.

Above, the calculation mode of the accessory ratio in the slot machine 400 has been explained by citing the first calculation example to the fourth calculation example. The base value in pachinko machines will be explained below. Note that the advantageous section ratio, instruction-inclusive role object ratio, continuous role object ratio, role object ratio, and role object state ratio in the slot machine 400 are rounded down to the nearest whole number; (number of outs/number of outs) is rounded off to the nearest whole number. Therefore, in pachinko machines, "200" is used instead of "100" as a multiplier for the number of prize balls, and whether or not the decimal point is 0.5 or more is determined by replacing it with an integer (the least significant bit). Therefore, the base value is determined by multiplying the number of prize balls by a multiplier (200), then dividing the result (dividend) multiplied by the multiplier by the number of outs, and determining whether to round up or down according to the least significant bit (MLB).

Here, we will give a fifth operation example using an 8-bit MUL instruction and repeated subtraction of a number multiplied by a power of 2, and a sixth operation example using a 16-bit multiplier and a 32-bit divider. Compare effectiveness.

(Fifth calculation example to execute number of prize balls x multiplier ÷ number of outs)
FIG. 118 is a flowchart showing a specific process for realizing the fifth operation example using an 8-bit MUL instruction and repeated subtraction of a number multiplied by a power of 2, and FIG. FIG. 3 is a diagram illustrating an example of a specific command for realizing an example calculation. The numerical values in step S in the explanation of FIG. 118 will be used only in the explanation of this figure. In addition, here, the address "R_ERW_BF1" that stores the 3-byte dividend (the result of multiplying the number of prize balls by the multiplier) and the address "R_ERW_BF2" that stores the 3-byte divisor (number of outs). Suppose that they are arranged consecutively.

As shown in FIG. 118, first, the value of the normal prize ball counter is read into the BC register (S1), the value of the normal out counter is read into the HL register (S2), and it is determined whether or not the HL register is 0 ( S3), if it is 0 (YES in S3), the process moves to step S23. Specifically, the command "XOR A, A" on the second line of FIG. 119 initializes the value of the A register, which will be used later to calculate the divisor, and the command "LD BC, (R_ERW_TJS)" on the third line, The value of the normal prize ball counter (number of prize balls) indicated by the address "R_ERW_TJS" is read to the BC register, and the value of the normal out counter indicated by the address "R_ERW_TJO" is read out to the BC register by the command "LD HL, (R_ERW_TJO") on the fourth line. The value (number of outs) is read to the HL register, and if the value of the HL register is 0 by the command "JR TZ, E_SHYMT_60" on the 5th line, it moves to the index "E_SHYMT_60" on the 49th line.

Next, as shown in FIG. 118, the out number is multiplied by an integer (a power of 2, here 128) (S4), and the result of the operation is stored in the main RAM 500c as a divisor buffer (S5). Specifically, the command "SRL H" on the 6th line in FIG. 119 shifts the value of the H register by 1 bit to the right, and the command "RR L" on the 7th line shifts the value of the The value of the register is bit-shifted by 1 to the right, and the value of the A register, including the carrier from the L register, is bit-shifted by 1 to the right by the command "RRA" on the 8th line. Here, if we judge the numerical value in units of HLA registers, we can assume that the value of the HL register is multiplied by 256, and then the bit is shifted by 1 to the right, so we multiply the number of outs by 128 (256/2). Therefore, this becomes the divisor. Then, the value of the A register, which is the lower byte of the divisor, is stored in the address "R_ERW_BF2" by the command "LD (R_ERW_BF2), A" on the 9th line of FIG. HL", the value of the HL register, which is the upper two bytes of the divisor, is stored in the address "R_ERW_BF2+1".

Subsequently, as shown in FIG. 118, the value of the C register, which is the lower byte of the multiplicand (number of prize balls), is multiplied by the multiplier (200) (S6), and the result of the operation is set in the DE register (S7). Specifically, the command "LD A, C" on the 11th line of FIG. 119 copies the value of the C register to the A register, and the command "MUL HL, A, 200" on the 12th line copies the value of the A register. The result of multiplying by 200 is held in the HL register, and the value of the HL register is set in the DE register by the command "EX DE, HL" on the 13th line.

Next, as shown in FIG. 118, the value of the B register, which is the upper byte of the multiplicand, is multiplied by the multiplier (200) (S8), and the value of the D register is added to the result of the calculation to update the result of the calculation ( S9), the calculation result is stored in the main RAM 500c as a dividend buffer (S10). Specifically, the command "LD A, B" on the 14th line of FIG. 119 copies the value of the B register to the A register, and the command "MUL HL, A, 200" on the 15th line copies the value of the A register. The result obtained by multiplying by Only the upper 1 byte (D register value) of the registers is added, and the command "LD A, E" on the 17th line adds up the DE register set by the command "EX DE, HL" on the 13th line. Set the lower 1 byte to the A register, use the command "LD (R_ERW_BF1), A" on the 18th line to store the value of the A register, which is the lower byte of the dividend, to the address "R_ERW_BF1", and use the command "LD (R_ERW_BF1), A" on the 19th line. LD (R_ERW_BF1+1), HL", the value of the HL register, which is the upper two bytes of the dividend, is stored in the address "R_ERW_BF1+1".

Next, as shown in FIG. 118, the number of loops is initialized to 8, the quotient is initialized to 0 (S11), the quotient is doubled (S12), and the upper 2 bytes of the dividend and the upper 2 bytes of the divisor are read (S13). ), it is determined whether the upper two bytes of the dividend are less than the upper two bytes of the divisor (S14). If the upper two bytes of the dividend are less than the upper two bytes of the divisor (YES in S14), the process moves to step S20. Specifically, the command "LD BC, 8*256+0" on the 20th line of FIG. C" shifts the value of the C register to the left by 1 bit (0 is entered in the MSB), and the command "LD HL, R_ERW_BF1+1" on the 23rd line stores the dividend (the result of multiplying the number of prize balls x multiplier). Read the value obtained by adding 1 to the value of the address "R_ERW_BF1" stored in the HL register, and use the command "LD DE, (HL+3)" on the 24th line to read the 3 upper bytes of the address "R_ERW_BF1" that stores the dividend. The upper 2 bytes of the divisor stored in the address “R_ERW_BF2” located at The value of the DE register (the upper 2 bytes of the divisor) is compared with the value of the DE register (the upper 2 bytes of the divisor), and if the carry flag is set, that is, if the upper 2 bytes of the dividend are less than the upper 2 bytes of the divisor, Move to the index “E_SHYMT_55” on the 38th line.

Next, as shown in FIG. 118, if the upper 2 bytes of the dividend are greater than or equal to the upper 2 bytes of the divisor (NO in S14), the lower 1 byte of the divisor and the lower 1 byte of the dividend are read for subsequent calculations. (S15), In step S14, it is determined whether the upper 2 bytes of the dividend and the upper 2 bytes of the divisor are not equal, that is, whether the upper 2 bytes of the dividend are larger than the upper 2 bytes of the divisor (S16). . If the upper 2 bytes of the dividend and the upper 2 bytes of the divisor are not equal (YES in S16), the process moves to step S18, and if the upper 2 bytes of the dividend and the upper 2 bytes of the divisor are equal (NO in S16), It is determined whether the lower 1 byte of the dividend is less than the lower 1 byte of the divisor (S17). If the lower 1 byte of the dividend is less than the lower 1 byte of the divisor (YES in S17), the process moves to step S20, and if the lower 1 byte of the dividend is greater than or equal to the lower 1 byte of the divisor (NO in S17), the process moves to step S20. Move to S18. Specifically, the command "LDL, LOW R_ERW_BF2" on the 26th line in FIG. The upper 1 byte of "R_ERW_BF2" is already held by the command "LD HL, R_ERW_BF1+1" on the 27th line), and the address where the divisor is stored by the command "LD A, (HL-3)" on the 27th line. The lower 1 byte of the dividend stored in the address "R_ERW_BF1" located 3 bytes lower than "R_ERW_BF2" is read into the A register, and the command "JR NZ, E_SHYMT_50" on the 28th line is executed, and the command on the 25th line is executed. If the zero flag is not set, move to the index "E_SHYMT_50" on the 31st line, and use the command "CP A, (HL)" on the 29th line to save the value of the A register (lower 1 byte of the dividend) and the HL register. The value of the indicated address (the lower 1 byte of the divisor) is compared, and if the carry flag is set by the command "JRC,E_SHYMT_55" on the 30th line, that is, the lower 1 byte of the dividend is the lower 1 byte of the divisor. If it is less than bytes, move to the index "E_SHYMT_55" on the 38th line.

Subsequently, as shown in FIG. 118, if the dividend is greater than or equal to the divisor, the divisor is subtracted from the dividend, the subtraction result is updated as a new dividend (S18), and 1 is added to the quotient (S19). Specifically, the command "SUB A, (HL)" on the 32nd line of FIG. 119 calculates the value of the lower 1 byte of the divisor indicated by the HL register from the value of the A register, which stores the lower 1 byte of the dividend. Then, the command "LD (HL-3), A" on the 33rd line updates the address indicating the dividend located 3 bytes lower than the address storing the divisor indicated by the HL register, which is the result of the subtraction. The command "LD HL, (HL-2)" on the 34th line stores the lower 1 byte of the dividend indicated by the HL register. Read the address indicating 2 bytes to the HL register, and use the command "SBC HL,DE" on the 35th line to change the value of the HL register, which stores the upper 2 bytes of the dividend, to the DE register, which stores the upper 2 bytes of the divisor. , and by the command "LD (R_ERW_BF1+1),HL" on the 36th line, store the upper two bytes of the updated dividend, which is the result of the subtraction, in the upper two bytes of the dividend indicated by the address "R_ERW_BF1", The command "INC C" on the 37th line increments the value of the C register indicating the quotient by 1.

Next, as shown in FIG. 118, the divisor is divided by 2 (bit shifted to the right), updated as a new divisor (S20), the number of loops is subtracted, and it is determined whether the number of loops is not 0. (S21), and if it is not 0 (YES in S21), the process from step S12 is repeated, and if it is 0 (NO in S21), rounding is executed (S22), and the base value is set in the main RAM 500c. (S23), the process ends. Specifically, the command "LD HL, R_ERW_BF2+2" on the 39th line of FIG. The value of the address indicated by the register (3rd byte of the divisor) is bit-shifted by 1 to the right, and the command "DEC HL" on the 41st line decrements the value of the HL register by 1, and the command "DEC HL" on the 42nd line decrements the value of the HL register by 1. RR (HL)'' causes the value of the address indicated in the HL register (2nd byte of the divisor) to be bit-shifted by 1 to the right, and the command ``DEC HL'' on the 43rd line decrements the value of the HL register by 1. , the command "RR (HL)" on the 44th line shifts the value of the address indicated in the HL register (the first byte of the divisor) by 1 bit to the right, and the command "DJNZ E_SHYMT_45" on the 45th line shifts the number of loops. The value of the B register indicating the value is decremented by 1, and if the value is not 0, the process moves to the index "E_SHYMT_45" on the 21st line. On the other hand, when the number of loops becomes 0, the value of the C register indicating the quotient is copied to the A register by the command "LD A, C" on the 46th line in FIG. If the value of the address indicated in the register is bit-shifted by 1 to the right, and the carry flag is set by the command "ADC A, 0" on the 48th line and the command "SRL A" on the 47th line, that is, the decimal point is If the following is 0.5 or more, 1 is added to the A register, the address "R_ERW_BAS" indicating the base value is set in the HL register by the command "LD HL, R_ERW_BAS" on the 50th line, and the address "R_ERW_BAS" indicating the base value is set in the HL register, and The command "LD (HL), A" stores the value of the A register indicating the base value at the address "R_ERW_BAS".

According to the fifth calculation example, it is possible to derive the base value using only simple calculations such as addition, subtraction, and multiplication, or by repeatedly subtracting a number multiplied by a power of 2.

Here, in this command example, as shown in FIG. 119, the total command size is 97 bytes, and the simple total number of cycles is 136/131 cycles. Moreover, the actual number of cycles is as follows. That is, in this process, the command from the next command (22nd line) of the index "E_SHYMT_45" to the command "DJNZ E_SHYMT_45" on the 45th line is looped eight times. At this time, in all 8 loops, if the command "JCP C, (HL), DE, E_SHYMT_55" on the 25th line moves to the index "E_SHYMT_55", the commands on the 26th to 37th lines will not be executed. , the number of cycles is the minimum 367 (54 + 38 (first 7 loops) x 7 + 37 (8th loop) + 10) cycles. On the other hand, in all loops, if the command "JCP C, (HL), DE, E_SHYMT_55" on the 25th line does not move to the index "E_SHYMT_55", the number of cycles becomes the maximum. However, due to possible numerical values, in the first and second loops, the command "JCP C, (HL), DE, E_SHYMT_55" on the 25th line does not move, but the command "JR NZ, E_SHYMT_50" on the 28th line In the 3rd to 8th loops, the command "JCP C, (HL), DE, E_SHYMT_55" on the 25th line, the command "JR NZ, E_SHYMT_50" on the 28th line, and the command "JR C , E_SHYMT_55'', the maximum number of cycles is 601 (54 + 65 (first 2 loops) x 2 + 68 (subsequent 5 loops) x 5 + 67 (8th loop) + 10 ) cycle. Therefore, the effective total number of cycles ranges from 367 to 601 cycles.

(Sixth calculation example to execute number of prize balls x multiplier ÷ number of outs)
FIG. 120 is a flowchart showing specific processing for realizing the sixth operation example using a 16-bit multiplier and a 32-bit divider, and FIG. FIG. 2 is a diagram showing an example of a specific command. The numerical values in step S in the explanation of FIG. 120 will be used only in the explanation of this figure.

As shown in FIG. 120, first, the number of prize balls is set in the multiplicand register (S1), and the multiplier "200" is set in the multiplier register (S2). Specifically, by the command "LD HL, (R_ERW_TJS)" in the first line of FIG. 121, the value of the normal prize ball counter (number of prize balls) indicated by the address "R_ERW_TJS" is read into the HL register, and the second line The second command "OUT (LOW @MULA16_)" sets the value of the U register as the upper 1 byte of the address, sets the address "@MULA16_" as the lower 1 byte, and outputs the value of the HL register to the multiplier setting register indicated by that address. Then, the command "EX DE, HL" on the third line copies the value of the HL register to the DE register, and the command "LD A, 200" on the fourth line sets the multiplier "200" to the A register. The command "OUT (LOW @MULB16_), A" on the fifth line sets the value of the U register to the upper 1 byte of the address, sets the address "@MULB16_" to the lower 1 byte, and sets A to the multiplier setting register indicated by that address. Output the register value. Note that "00H" is set as a default value in the upper one byte of the multiplier setting register "@MULB16_".

Next, as shown in FIG. 120, assuming that the normal prize ball counter is 0, 0 is set as the initial value of the base value (S3), and it is determined whether the number of outs is 0 (S4). ), if it is 0 (YES in S4), the result does not change even if the multiplier is multiplied (because it is 0), so move to step S13, and if it is not 0 (NO in S4), set the base value to 100. (S5), it is determined whether the number of outs is less than the number of prized balls (S6), and if the number of outs is less than the number of prized balls (YES in S6), the process moves to step S13. Specifically, the command "XOR A, A" on the 6th line of FIG. 121 sets the value of the A register indicating the base value to 0, and the command "LD HL, (R_ERW_TJO)" on the 7th line sets the address " The value of the normal out counter (number of outs) indicated by "R_ERW_TJO" is read to the HL register, and if the value of the HL register is 0 by the command "JR TZ, E_SHYMT_60" on the 8th line, the index on the 23rd line is read out. Move to "E_SHYMT_60" and use the command "LD A, 100" on the 9th line to set 100 as the initial value in the A register indicating the base value, and execute the command "JCP C, HL, DE, E_SHYMT_60" on the 10th line. The value of the HL register (number of outs) and the value of the DE register (number of prize balls) are compared, and if the carry flag is set, that is, if the number of outs is less than the number of prize balls, the value in the 23rd line is Move to the index "E_SHYMT_60".

Next, as shown in FIG. 120, the out number is set in the divisor setting register (S7), the multiplication result by the 16-bit multiplier is read into the HLA register (HL register and A register) (S8), and it is set as the dividend. Set in the register (S9). Specifically, the command "OUT (LOW @DIVB32_), HL" on the 11th line in Figure 121 sets the value of the U register to the upper 1 byte of the address, sets the address "@DIVB32_" to the lower 1 byte, and performs operations at that address. The value of the HL register is output to the indicated divisor setting register "@DIVB32_", and the command "IN A, (LOW @MUL32__" on the 12th line) sets the value of the U register to the upper 1 byte of the address, and the address "@MULB32__" is output. ” as the lower 1 byte, read the 1-byte value of the multiplication result register indicated by that address to the A register, and use the command “IN HL, (LOW @MUL32__+1” on the 13th line) to set the value of the U register to the upper 1 byte of the address. Byte, the address "@MULB32__+1" is the lower 1 byte, the 2-byte value of the multiplication result register indicated by that address is read to the HL register, and the command "OUT (LOW @DIVA32_+0), A" on the 14th line is used to write U. The value of the register is set as the upper 1 byte of the address, the address "@DIVA32_" is set as the lower 1 byte, the value of the A register is output to the dividend setting register "@DIVA32_" indicated by that address, and the command "OUT" on the 15th line is output. (LOW @DIVA32_+1), HL" sets the value of the U register as the upper 1 byte of the address, sets the address "@DIVA32_+1" as the lower 1 byte, and sets the value of the HL register to the dividend setting register "@DIVA32_+1" indicated by that address. In this way, the 16-bit multiplier is operated, and the multiplication result is stored in the multiplication result register.

Next, as shown in FIG. 120, the division waits (S10), and after a predetermined time has elapsed, the calculation result is read into the A register (S11), rounding is performed (S12), and the base value is stored in the main RAM 500c. The settings are made (S13), and the process ends. Specifically, the command "NOP" on lines 16 to 19 in FIG. The command "SRL A" on the 21st line shifts the value of the address indicated in the A register by 1 bit to the right, and the command "ADC A, 0" on the 22nd line reads the value of the address indicated in the A register. If the carry flag is set by "A", that is, if the number after the decimal point is 0.5 or more, 1 is added to the A register, and the address indicating the base value is added by the command "LD HL, R_ERW_BAS" on the 24th line. "R_ERW_BAS" is set in the HL register, and the value of the A register indicating the base value is stored in the address "R_ERW_BAS" by the command "LD (HL), A" on the 25th line.

Here, in this command example, as shown in FIG. 121, the total command size is 49 bytes, and the simple total number of cycles is 68/66 cycles.

As explained above, when comparing the fifth calculation example for deriving the base value and the sixth calculation example for deriving the base value, it is found that both the total command size and the simple total of the number of cycles are 16-bit multiplication. The sixth calculation example using a 32-bit divider and a 32-bit divider is smaller. Therefore, when executing the base value in a pachinko machine, it is preferable to use a 16-bit multiplier and a 32-bit divider, as described using FIGS. 120 and 121.

As described above, according to the present embodiment, by suppressing the increase in processing load, it is possible to shorten the period in which timer interrupts are prohibited, thereby stabilizing the operation of the gaming machine while appropriately obtaining gaming information. It becomes possible to convert into

Note that in the above-described embodiment, in the fourth operation example and the sixth operation example, "NOP", which consumes one cycle of time for waiting for division by a 32-bit divider, is used four times in a row. ing. However, the command is not limited to this case, and other commands may be used as long as four cycles are secured. For example, a 2-cycle command with a command size of 1 byte may be used twice, a 4-cycle command with a 1-byte command size, or a 4-cycle command with a 2-byte command size may be used. In this way, the command size can be reduced.

In addition, in the above-described embodiment, a first calculation example using only an 8-bit MUL instruction and a second calculation example using a 16-bit multiplier are given as calculation examples for executing the number of paid out accessories x multiplier. In addition, as an example of calculating the multiplication result divided by the total number of payouts, a third calculation example using repeated subtraction of a number multiplied by a power of 2 and a fourth calculation example using a 32-bit divider are listed. Ta. In the embodiment described above, after calculating the number of accessory payouts x the multiplier, the multiplication result is used to calculate the multiplication result ÷ the total number of payouts, so the first calculation example or the second calculation example and the third calculation example The calculation is performed by combining the calculation example or the fourth calculation example. Any combination of such calculation examples can be set. For example, a combination of the first calculation example and the third calculation example, a combination of the first calculation example and the fourth calculation example, a combination of the second calculation example and the third calculation example, a combination of the second calculation example and the third calculation example, A combination of the calculation example and the fourth calculation example can be adopted. In addition, both the fifth calculation example and the sixth calculation example can be divided into the number of paid out accessories x multiplier and the multiplication result divided by the total number of payouts, and the combination of these calculation examples can be set arbitrarily. For example, a combination of the number of accessory payouts x multiplier in the fifth calculation example described above and the multiplication result ÷ total number of payouts in the fifth calculation example, the combination of the number of accessory payouts x multiplier in the sixth calculation example, and the combination of the multiplication result ÷ total number of payouts in the fifth calculation example, In addition to the combination of the multiplication result ÷ total number of payouts in the calculation example, the combination of the number of accessory payouts × multiplier in the fifth calculation example and the multiplication result ÷ total number of payouts in the sixth calculation example, the sixth calculation A combination of the number of accessory payouts x multiplier in the example and the multiplication result divided by the total number of payouts in the fifth calculation example can be adopted.

Further, in the above-described embodiment, various calculations (first calculation example to fourth calculation example) were performed using the accessory ratio of the slot machine 400 as an example, but the slot machine 400 is not limited to this case. Each ratio of the machine 400 (advantageous section ratio, instructional accessory ratio, continuous accessory ratio of 6000 games, accessory ratio of 6000 games, total cumulative consecutive accessory ratio, total cumulative accessory ratio, accessory etc. status Needless to say, it can be applied to ratios). Further, the present invention is not limited to the slot machine 400, but can also be applied to the base value of a pachinko machine, as explained using the fifth calculation example and the sixth calculation example.

<Module and command description>
Hereinafter, for each of the above-mentioned processes (modules), specific instruction codes (command groups) for realizing the processes will be explained in units of commands mainly used within the module.

<Command “ADDALD”>
The BYTESEL module is a general-purpose module for byte data selection processing, that is, for offsetting a selected address and reading a 1-byte value stored at the offset address. A general-purpose module is a subroutine of the same processing used to execute a program, and indicates a module that is particularly frequently called by other modules. A general-purpose module is often placed near the lowest address 0000H on the memory map shown in FIG. 5 (or FIG. 102). This is because by placing a frequently called general-purpose module near 0000H, it can be called using not only the command "CALL" used for calling but also another command "RST". Note that an example will be described in which the BYTESEL module is placed at 0008H on the memory map.

Here, the command "RST" is a low numerical address near 0000H in the memory map, and is one of multiple addresses (0008H, 0010H, 0018H, 0020H, 0028H, 0030H, 0038H, 0040H) separated by 8 bytes. This is a command that can be called. The command "RST" has the same execution cycle as the normal command "CALL" used for calling, which is "4", but the command size of the normal command "CALL" is "3", while the command "RST" The command size of is "1". Therefore, by using the command "RST", the program can be shortened.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls the BYTESEL module as a subroutine in any process, and executes the BYTESEL module. The BYTESEL module offsets the selected address by a predetermined value and holds the 1-byte value stored at the offset address. In this way, a value can be set according to the offset.

FIG. 122 is a flowchart showing specific processing of the BYTESEL module. Here, as an arbitrary process, a part of the LED_PRC module that executes the LED display setting process shown in S400-31 in FIG. 26 will be described. The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the description of the BYTESEL module, the first register is the HL register, and the second register is the A register.

As shown in FIG. 122(a), the main CPU 300a sets an offset in the A register (S1) and sets the first address of the address group to be read in the HL register (S2) in an arbitrary process. Then, the BYTESEL module is called as a subroutine (S3).

As shown in FIG. 122(b), the main CPU 300a updates the HL register by adding the value of the A register to the value of the HL register in the BYTESEL module, and updates the 1-byte value stored at the address indicated by the HL register. is read into the A register (S4). Next, the main CPU 300a sets a zero flag (first zero flag) depending on whether the value of the A register is 0 (zero) (S5). Then, the BYTESEL module is terminated and the routine returns to the next step higher (S6).

123 and 124 are explanatory diagrams for explaining examples of commands for implementing the BYTESEL module. Of these, FIG. 123(a) shows a command group for arbitrary processing that calls the BYTESEL module, FIG. 123(b) shows a command group for the BYTESEL module, and FIG. 123(c) shows the program data of the main ROM 300b. This shows the arrangement of 1-byte data group in . The flowchart shown in FIG. 122 is realized, for example, by the program shown in FIG. 123.

The command "LDQ A, (LOW R_TZ1_DSP)" in the first line of FIG. 123(a) sets the value of the Q register as the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_TZ1_DSP" as the lower 1 byte of the address. Then, the value stored at that address (the counter value of the special symbol 1 display symbol counter) is read into the A register. The command on the first line corresponds to step S1 in FIG. 122(a). The command "LD HL, D_DSP_TZ" on the second line sets the head address "D_DSP_TZ" of the data group of the special symbol display LED output data table from which to read the data in the HL register. The command on the second line corresponds to step S2 in FIG. 122(a). Then, the BYTESEL module is called as a subroutine by the command "RST BYTESEL" on the third line. The command on the third line corresponds to step S3 in FIG. 122(a).

The index “BYTESEL:” in the first line of FIG. 123(b) indicates the start address of the BYTESEL module. The command "ADDWB HL,A" on the second line adds the value of the A register to the value of the HL register, thereby updating the value of the HL register. Then, by the command "LD A, (HL)" on the third line, the 1-byte value stored at the address indicated by the HL register is read into the A register. The commands on the second and third lines correspond to step S4 in FIG. 122(b). The command "OR A, A" on the fourth line calculates the logical sum of the value of the A register and the value of the A register. In such a command "OR A, A", the value of the A register does not change because it is a logical sum of the values of the A register. On the other hand, the zero flag (the first zero flag and the second zero flag) can be changed by the logical sum. That is, in such a BYTESEL module, it is possible to determine whether or not the read value of the A register is zero based on the zero flag. The command on the fourth line corresponds to step S5 in FIG. 122(b). Then, the command "RET" on the fifth line returns to the routine one stage higher. The command on the fifth line corresponds to step S6 in FIG. 122(b).

Note that the table starting from the index "D_DSP_TZ" in FIG. 123(c) shows, for example, information regarding the special 1 jackpot symbol and the special 2 jackpot symbol. For example, when the variable "R_TZ1_DSP", that is, the counter value of the special symbol 1 display symbol counter is "02H", as shown in FIG. 124, the table (2AH, A2H, A8H , 36H...5DH, FDH), the value (A8H) stored at the address (third address from the lowest) that is the sum of the selected address (e.g. 1250H) and the value of the A register (e.g. 02H) is stored in the A register. Can be read. In this manner, it is possible to obtain a desired 1-byte value in a table in which a plurality of values of the same byte length are consecutively arranged.

The BYTESEL module is called as a subroutine by multiple modules. For example, the SBCMDST module executes the subcommand group set process shown in step S100-55 of FIG. 23, the LED_PRC module executes the LED display setting process shown in step S400-31 of FIG. 26, and the step S400-33 of FIG. The SOL_SET module executes the solenoid data setting process (solenoid output image synthesis process) shown in FIG. 26, and the MEM_DAT module executes the held pitch count bit data synthesis process which is a subroutine of the LED display setting process shown in step S400-31 of FIG. , TDN_PAS module that executes the count switch passage processing (second starting opening passage processing, big winning opening passage processing) shown in steps S530 and S540 of FIG. 28, and the special symbol stop symbol display processing shown in step S630 of FIG. 43. TZ_STP module to be executed, TD_OPN module to execute the big winning opening control process shown in step S720 of FIG. 47, normal symbol fluctuation time setting process (normal symbol fluctuation time determination process) shown in step S810-11 of FIG. 52 The FSPNTMR module executes the special symbol variation pattern determination process (special symbol variation number determination process) shown in step S612 of FIG. 39, and the THPTSEL module executes the preliminary area setting process shown in step S610-17 of FIG. 37. TRSVSEL module that executes the ending time setting process shown in step S730-9 of FIG. 48, TENDTMR module that executes the ending time setting process shown in step S730-9 of FIG. 48, and symbol offset acquisition that is executed in step S630-13 of FIG. It is called from the ZUGOFFS module that executes a process (not shown), the RGETCHK module that executes the effect determination process at the time of acquisition shown in step S536 of FIG. 33, and the like.

In this way, the total command size of the BYTESEL module commands shown in Figure 123(b) is 1 byte for the command "ADDWB HL, A" on the second line + 1 byte for the command "LD A, (HL)" on the third line. + 1 byte of the command “OR A, A” on the 4th line + 1 byte of the command “RET” on the 5th line = 4 bytes, and the total execution cycle is 1 cycle on the 2nd line + 2 cycles on the 3rd line + 1 cycle on the 4th line + 5 lines 3rd cycle = 7th cycle. By providing such a BYTESEL module, it is possible to use the command "RST BYTESEL" with a command size of 1 byte without performing byte data selection processing in each of the above-mentioned modules, so the command can be shortened and the game control processing This makes it possible to secure the capacity of the control area for performing this.

FIG. 125 is an explanatory diagram for explaining another example of commands for realizing the BYTESEL module. Here, the BYTESEL module command group in FIG. 123(b) is replaced with the BYTESEL module command group in FIG. 125(b), and any other command group for any process that calls the BYTESEL module in FIG. 123(a). , and the 1-byte data group in the program data of the main ROM 300b in FIG. 123(c) are used as they are in FIGS. 125(a) and 125(c). 125(a) and 125(c), which are substantially the same as those in FIG. 123(a) and FIG. 123(c), will be omitted, and different Only the processing will be explained.

The index “BYTESEL:” in the first line of FIG. 125(b) indicates the start address of the BYTESEL module. The command "ADDALD A, (HL)" on the second line adds the value of the A register to the value of the HL register, and reads the 1-byte value stored at the address indicated by the HL register after the addition to the A register. . The command on the second line corresponds to step S4 in FIG. 122(b). The command "OR A, A" on the third line calculates the logical sum of the value of the A register and the value of the A register. The zero flag (first zero flag and second zero flag) can be changed by such a logical sum. That is, in the BYTESEL module, it is possible to determine whether or not the read value of the A register is zero based on the zero flag. The command on the third line corresponds to step S5 in FIG. 122(b). Then, the command "RET" on the fourth line returns to the routine one level higher. The command on the fourth line corresponds to step S6 in FIG. 122(b).

Here, the command "ADDALD A, (HL)" updates the HL register by adding the value of the A register to the value of the HL register, and reads the value stored at the address indicated by the HL register to the A register. It is a command. The command size of such a command is "1" and the execution cycle is "3".

The total command size of the BYTESEL module commands in Figure 125(b) is: 1 byte of the command “ADDALD A, (HL)” on the 2nd line + 1 byte of the command “OR A, A” on the 3rd line + 1 byte of the command “OR A, A” on the 4th line RET'' 1 byte = 3 bytes, and the total execution cycle is 3 cycles on the 2nd line + 1 cycle on the 3rd line + 3 cycles on the 4th line = 7 cycles. Therefore, it can be seen that the total command size is reduced by 1 byte compared to the case of FIG. 123(b). With such a BYTESEL module, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

Also, in order to understand by comparing FIG. 123(b) and FIG. 125(b), the command group that occupied two lines (second and third lines) in FIG. 123(b) is b) can be expressed in one line (second line), making it possible to reduce the number of commands and the design load.

FIG. 126 is an explanatory diagram for explaining still another example of commands for realizing the BYTESEL module. Here, the command group for an arbitrary process that calls the BYTESEL module in FIG. 125(a) and the command group for the BYTESEL module in FIG. 125(b) are replaced with the command group for an arbitrary process in FIG. 126(a). The other 1-byte data group in the program data of the main ROM 300b in FIG. 125(c) is used as is as shown in FIG. 126(b). Here, as in FIG. 126(b), a description of processes that are substantially the same as those in FIG. 125(c) will be omitted, and only processes that are different from FIG. 126(a) will be described.

The command "LDQ A, (LOW R_TZ1_DSP)" in the first line of FIG. 126(a) sets the value of the Q register as the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_TZ1_DSP" as the lower 1 byte of the address. and reads the value stored at that address into the A register. The command on the first line corresponds to step S1 in FIG. 122(a). The command "LD HL, D_DSP_TZ" on the second line sets the start address "D_DSP_TZ" of the 1-byte data group to be read from in the HL register. The command on the second line corresponds to step S2 in FIG. 122(a). Then, the command "ADDALD A, (HL)" on the third line adds the value of the A register to the value of the HL register, and the 1-byte value stored at the address indicated by the HL register after the addition is transferred to the A register. Read out. The command on the third line corresponds to step S4 in FIG. 122(b).

In the example of FIG. 126, the command "RST BYTESEL" corresponding to step S3 of FIG. 122(a), the command "OR A, A" corresponding to step S5 of FIG. 122(b), and the command "OR A, A" of FIG. 122(b) The command "RET" corresponding to step S6 is omitted.

The total command size of the command group for any process in FIG. 126(a) is: 2 bytes of the command “LDQ A, (LOW R_TZ1_DSP)” in the 1st line + 3 bytes of the command “LD HL, D_DSP_TZ” in the 2nd line + 3 bytes of the command “LDQ A, (LOW R_TZ1_DSP)” in the 3rd line The command "ADDALD A, (HL)" has 1 byte = 6 bytes, and the total execution cycle is 2 cycles for the 1st line + 3 cycles for the 2nd line + 3 cycles for the 3rd line = 8 cycles.

On the other hand, the total command size of the arbitrary processing and BYTESEL module commands in FIGS. 125(a) and 125(b) is the command "LDQ A, (LOW R_TZ1_DSP)" in the first line of FIG. 125(a). 2 bytes + 2nd line command “LD HL, D_DSP_TZ” 3 bytes + 3rd line command “RST BYTESEL” 1 byte + 2nd line command “ADDALD A, (HL)” in Figure 125(b) 1 byte + 3 lines 1 byte of the command “OR A, A” on the 4th line + 1 byte of the command “RET” on the 4th line = 9 bytes, and the total execution cycle is 2 cycles on the 1st line + 3 cycles on the 2nd line + 3 cycles on the 3rd line in Figure 125(a) 4 cycles + 3 cycles on the 2nd line + 1 cycle on the 3rd line + 3 cycles on the 4th line in FIG. 125(b) = 16 cycles. Therefore, in the example of FIG. 126, the total command size is reduced by 3 bytes and the total execution cycle is reduced by 8 cycles compared to the case of FIG. 125. In this way, by embedding the BYTESEL module itself as a command in arbitrary processing, it is possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing game control processing. .

Also, as can be understood by comparing FIGS. 125 and 126, the command group that occupied 4 lines (1st to 4th lines) in FIG. 125(b) no longer needs to be written in FIG. 126. Therefore, it is possible to reduce the number of commands and the design load.

In addition, the BYTESEL module is a general-purpose module that is the target of the command "RST", but by omitting this general-purpose module, valuable general-purpose module space can be freed up and other modules can be placed in that area. . In this way, resources can be used effectively.

However, in the example of FIG. 126, by omitting the command "OR A, A", the first zero flag cannot be changed. That is, it becomes impossible to determine whether the read value of the A register is zero or not based on the first zero flag. However, if there is no need to determine whether the value of the A register is zero after the byte data selection process, this function is not needed in the first place. Further, the command "ADDALD A, (HL)" can change the second zero flag simply by executing the command. Therefore, when it is necessary to determine whether the value of the A register is zero, it is possible to determine whether the value of the A register is zero by referring to the second zero flag.

The BYTESEL module is used not only in pachinko machines but also in slot machines, for example, as a module for executing register addition processing.

<Command “ADDALDW”>
The WORDSEL module is a general-purpose module for word data selection processing, that is, for offsetting a selected address and setting a 2-byte value stored at the offset address. Here, an example will be described in which the WORDSEL module is placed at 0018H on the memory map.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls the WORDSEL module as a subroutine in any process, and executes the WORDSEL module. In the WORDSEL module, the selected address is offset by a predetermined value and the 2-byte value stored at the offset address is held. In this way, a value can be set according to the offset.

FIG. 127 is a flowchart showing specific processing of the WORDSEL module. Here, as an arbitrary process, a part of the FUT_PRC module that executes the normal game management process shown in step S800 in FIG. 51 will be described. The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the description of the WORDSEL module, the first register is the HL register, and the second register is the A register.

As shown in FIG. 127(a), the main CPU 300a sets an offset in the A register (S1) and sets the first address of the address group to be read in the HL register (S2) in an arbitrary process. Then, the WORDSEL module is called as a subroutine (S3).

As shown in FIG. 127(b), in the WORDSEL module, the main CPU 300a adds the value of the A register to the value of the HL register twice, or adds the value obtained by doubling the value of the A register to set the HL register. Update (S4), and read the 2-byte value stored at the address indicated by the HL register into the HL register (S5). Next, the main CPU 300a sets the value of the L register to the A register (S6). Then, the WORDSEL module is terminated and the routine returns to the next step higher (S7).

When a 2-byte value is set in the HL register by the WORDSEL module, the main CPU 300a performs various processes using the value of the HL register. For example, here, as shown in FIG. 127(a), the address indicated by the HL register is called as a subroutine (S8).

128 and 129 are explanatory diagrams for explaining examples of commands for implementing the WORDSEL module. Of these, FIG. 128(a) shows a command group for arbitrary processing that calls the WORDSEL module, FIG. 128(b) shows a command group for the WORDSEL module, and FIG. 128(c) shows the program data of the main ROM 300b. This shows the arrangement of 2-byte data groups in . The flowchart shown in FIG. 127 is realized, for example, by the program shown in FIG. 128.

The command "LDQ A, (LOW R_FUT_PHS)" in the first line of FIG. 128(a) sets the value of the Q register as the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_TZ1_DSP" as the lower 1 byte of the address. and reads the value stored at that address into the A register. The command on the first line corresponds to step S1 in FIG. 127(a). The command "LD HL, J_JMP_FUT" on the second line sets the start address "J_JMP_FUT" of the 2-byte data group to be read from in the HL register. The command on the second line corresponds to step S2 in FIG. 127(a). Then, the WORDSEL module is called as a subroutine by the command "RST WORDSEL" on the third line. The command on the third line corresponds to step S3 in FIG. 127(a).

The index “WORDSEL:” in the first line of FIG. 128(b) indicates the start address of the WORDSEL module. The command "ADDWB HL,A" on the second line adds the value of the A register to the value of the HL register, and updates the HL register. Furthermore, the command "ADDWB HL,A" on the third line adds the value of the A register to the value of the HL register, thereby updating the HL register. Here, the value of the A register is added to the HL register twice because the value from which to read is a 2-byte value. That is, since data is allocated to the table in units of 2 bytes, it is necessary to offset the address by 2 in order to read the data. Note that here, by executing the command "ADDWB HL,A" twice, the value of the A register is added to the HL register twice, but instead of the command "ADDWB HL,A" on the second line, This can also be achieved by using the command "ADD A, A" to double the value in the A register in advance and then adding it to the HL register. The commands on the second and third lines correspond to step S4 in FIG. 127(b).

Then, the 2-byte value stored at the address indicated by the HL register is read to the HL register by the command "LD HL, (HL)" in the fourth line of FIG. 128(b). The command on the fourth line corresponds to step S5 in FIG. 127(b). The command "LD A,L" on the fifth line sets the value of the L register among the HL registers in the A register. In this way, the lower one byte of the value of the HL register is set in advance in the A register. The command on the fifth line corresponds to step S6 in FIG. 127(b). Then, the command "RET" on the sixth line returns to the routine one stage higher. The command on the sixth line corresponds to step S7 in FIG. 127(b).

Note that the table starting from the index "J_JMP_FUT" in FIG. 128(c) shows, for example, an address indicating the state of the normal game. For example, if the value of the variable "R_FUT_PHS", that is, the normal game management phase, is "02H", as shown in FIG. 129, the table (FZ_STA, FZ_SPN, FZ_STP, FD_PRE, FD_OPN, FD_END), the value stored at the selected address (e.g. 1270H) plus the value twice the value of the A register (e.g. 04H) (5th and 6th addresses from the lowest), here. In this case, 0832H (FZ_STP) can be held in the HL register. In this manner, it is possible to obtain a desired 2-byte value in a table in which a plurality of values of the same byte length are consecutively arranged.

Here, FZ_STA indicates the address value of the normal symbol fluctuation waiting process shown in step S810 of FIG. 52, FZ_SPN indicates the address value of the normal symbol fluctuation process shown in step S820 of FIG. 53, and FZ_STP is FD_PRE indicates the address value of the normal symbol stop symbol display process shown in step S830 of FIG. 54, FD_PRE indicates the address value of the normal electric accessory prize opening preprocessing shown in step S840 of FIG. 57, FD_CLS indicates the address value of the normal electric accessory prize opening control process shown in step S850 of FIG. , indicates the address value of the normal electric accessory prize opening end wait process shown in step S870 of FIG.

Subsequently, the acquired 2-byte value, that is, the address value corresponding to the normal game state, is called by the command "CALL (HL)" on the fourth line of FIG. 128(a). For example, as mentioned above, when 0832H (FZ_STP) is read into the HL register in the table, the address indicated by "FZ_STP" is called by the command "CALL (HL)" and the normal symbol stop symbol display process is executed. becomes. The command on the fourth line corresponds to step S8 in FIG. 127(a).

The WORDSEL module is called as a subroutine by multiple modules. For example, the DBLBYTE module that executes the double byte selection process (not shown) executed in the special symbol stop symbol display process shown in step S630 in FIG. 43, and the subcommand transmission shown in step S100-65 in FIG. SBC_OUT module that executes the process, DYM_OUT module that executes the dynamic port output process shown in step S400-5 in FIG. 26, FUT_PRC module that executes the normal game management process shown in step S800 in FIG. 51, and step S600 in FIG. TOK_PRC module that executes the special game management process shown in FIG. 44, TDN_PRC module that executes the special electric accessory game management process in step S700 of FIG. 44, STA_PAS that executes the second starting port passage process shown in step S530 of FIG. module, TDN_PAS module that executes the count switch passage process (big winning opening passage process) shown in step S540 of FIG. 34, TZ_RGET module that executes the special symbol random number acquisition process shown in step S535 of FIG. 32, normal symbol fluctuation time The FSPNTMR module executes the setting process, the FDNCHG module executes the normal electric accessory prize opening opening/closing switching process shown in step S841 in FIG. 56, and the special symbol storage area shift process shown in step S610-9 in FIG. 37. TMEMSFT module, THPTSEL module that executes the special symbol fluctuation pattern determination process shown in step S612 of FIG. 39, special symbol fluctuation time setting process shown in step S610-15 of the special symbol fluctuation waiting process shown in step S610 of FIG. 37 TSPNTM module that executes the opening time setting process shown in step S630-15 of FIG. 43, TSTATMR module that executes the opening time setting process shown in step S630-15 of FIG. The TCLSTMR module that executes the big prize opening closing time setting process shown in S730-7, the TENDTMR module that executes the ending time setting process shown in step S730-9 of FIG. 48, and the fluctuation pattern shown in S612-15 of FIG. 39. HPT_MOD module that executes the selection 2 process (variation pattern number determination process), HPT_PAT module that executes the variation pattern selection 3 process (variation pattern number determination process) shown in S612-15 in FIG. 39, step S810-5 in FIG. The WORD DJDG module executes the word data determination process (not shown) executed in the process, the RGETCHK module executes the acquisition performance determination process shown in step S536 in FIG. 33, and the RGETCHK module shown in step S720-9 in FIG. It is called from the TEF_SEL module etc. which executes the big winning opening closing effective time selection process which is a subroutine of the big winning opening closing valid time setting process.

In this way, the total command size of the WORDSEL module commands shown in Figure 128(b) is: 1 byte of the command "ADDWB HL,A" on the 2nd line + 1 byte of the command "ADDWB HL,A" on the 3rd line + 4 lines 2nd command “LD HL, (HL)” 2 bytes + 5th line command “LD A,L” 1 byte + 6th line command “RET” 1 byte = 6 bytes, and the total execution cycle is 2nd line 1 Cycle + 1 cycle on the 3rd row + 4 cycles on the 4th row + 1 cycle on the 5th row + 3 cycles on the 6th row = 10 cycles. By providing such a WORDSEL module, it is possible to use the command "RST WORDSEL", which has a command size of 1 byte, without having to perform word data selection processing in each of the above-mentioned modules, so the command can be shortened and the game control processing This makes it possible to secure the capacity of the control area for performing this.

FIG. 130 is an explanatory diagram for explaining another example of commands for realizing the WORDSEL module. Here, the command group of the WORDSEL module in FIG. 128(b) is replaced with the command group of the WORDSEL module in FIG. 130(b), and the command group for any other process that calls the WORDSEL module in FIG. 128(a). , and the 2-byte data group in the program data of the main ROM 300b in FIG. 128(c) are used as they are in FIGS. 130(a) and 130(c). 130(a) and 130(c), which are substantially the same as those in FIG. 128(a) and FIG. 128(c), will be omitted, and different Only the processing will be explained.

The index “WORDSEL:” in the first line of FIG. 130(b) indicates the start address of the WORDSEL module. The command "ADDALDW HL, (HL)" on the second line adds the value of the A register to the value of the HL register twice, and the 2-byte value stored at the address indicated by the HL register after the addition is stored in the HL register. Read out. The command on the second line corresponds to steps S4 and S5 in FIG. 127(b). The command "LD A,L" on the third line sets the value of the L register among the HL registers to the A register. In this way, the lower one byte of the value of the HL register is set in advance in the A register. The command on the third line corresponds to step S6 in FIG. 127(b). Then, the command "RET" on the fourth line returns to the routine one stage higher. The command on the sixth line corresponds to step S7 in FIG. 127(b).

Here, the command "ADDALDW HL, (HL)" adds the value of the A register to the value of the HL register twice, updates the HL register, and also updates the value stored at the address indicated by the HL register after the addition. This is a command to read to the HL register. The command size of such a command is "2" and the execution cycle is "6".

Subsequently, the acquired 2-byte value, that is, the address value corresponding to the normal game state, is called by the command "CALL (HL)" on the fourth line of FIG. 130(a). The command on the fourth line corresponds to step S8 in FIG. 127(a).

The total command size of the WORDSEL module commands in Figure 130(b) is: 2 bytes of the command “ADDALDW HL, (HL)” on the 2nd line + 1 byte of the command “LD A,L” on the 3rd line + 1 byte of the command “ADDALDW HL, (HL)” on the 4th line ``RET'' 1 byte = 4 bytes, and the total execution cycle is 6 cycles on the 2nd line + 1 cycle on the 3rd line + 3 cycles on the 4th line = 10 cycles. Therefore, the total command size is reduced by 2 bytes compared to the case of FIG. 128(b). With such a WORDSEL module, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

Also, in order to understand by comparing FIG. 128(b) and FIG. 130(b), the command group that occupied three lines (2nd, 3rd, and 4th lines) in FIG. 128(b) is 130(b), it can be expressed in one line (second line), making it possible to reduce the number of commands and reduce the design load.

FIG. 131 is an explanatory diagram for explaining still another example of commands for implementing the WORDSEL module. Here, the command group for an arbitrary process that calls the WORDSEL module in FIG. 130(a) and the command group for the WORDSEL module in FIG. 130(b) are replaced with the command group for an arbitrary process in FIG. 131(a). The other 2-byte data group in the program data of the main ROM 300b in FIG. 130(c) is used as is as shown in FIG. 131(b). Here, as in FIG. 131(b), explanations of processes that are substantially the same as those in FIG. 130(c) will be omitted, and only processes that are different from FIG. 131(a) will be explained.

The command "LDQ A, (LOW R_FUT_PHS)" in the first line of FIG. 131(a) sets the value of the Q register as the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_FUT_PHS" as the lower 1 byte of the address. and reads the value stored at that address into the A register. The command on the first line corresponds to step S1 in FIG. 127(a). The second line command “LD HL
, J_JMP_FUT" sets the start address "J_JMP_FUT" of the 1-byte data group to be read from in the HL register. The command on the second line corresponds to step S2 in FIG. 127(a). Then, by the command "ADDALDW HL, (HL)" on the third line, the value of the A register is added twice to the value of the HL register, and the 2-byte value stored at the address indicated by the HL register after the addition is added to the HL register. Read into register. The command on the third line corresponds to steps S4 and S5 in FIG. 127(b). The command "CALL (HL)" on the fourth line calls the acquired 2-byte value, that is, the address value corresponding to the normal game state. The command on the fourth line corresponds to step S8 in FIG. 127(a).

In the example of FIG. 131, the command "RST WORDSEL" corresponding to step S3 in FIG. 127(a), the command "LD A,L" corresponding to step S6 in FIG. 127(b), and the command "LD A,L" corresponding to step S6 in FIG. 127(b) are The command "RET" corresponding to step S7 is omitted.

The total command size of the arbitrary processing and WORDSEL module commands in FIG. 131(a) is 2 bytes of the command "LDQ A, (LOW R_FUT_PHS)" on the first line + 3 bytes of the command "LD HL, J_JMP_FUT" on the second line + 3 The command “ADDALDW HL, (HL)” on the 4th line is 2 bytes + the command “CALL (HL)” on the 4th line is 2 bytes = 9 bytes, and the total execution cycle is 2 cycles on the 1st line + 3 cycles on the 2nd line + 3 cycles on the 3rd line. 6 cycles + 5 cycles in the 4th row = 16 cycles.

On the other hand, the total command size of the arbitrary processes and WORDSEL module commands in FIGS. 130(a) and 130(b) is the command "LDQ A, (LOW R_FUT_PHS)" in the first line of FIG. 130(a). 2 bytes + 2nd line command “LD HL, J_JMP_FUT” 3 bytes + 3rd line command “RST WORDSEL” 1 byte + 4th line command “CALL (HL)” 2 bytes + 2nd line in Figure 130(b) 2 bytes of the command “ADDALDW HL, (HL)” + 1 byte of the command “LD A, L” on the 3rd line + 1 byte of the command “RET” on the 4th line = 12 bytes, and the total execution cycle is as shown in Figure 130 (a). 1st row 2 cycles + 2nd row 3 cycles + 3rd row 4 cycles + 4th row 5 cycles + 2nd row 6 cycles + 3rd row 1 cycle + 4th row 3 cycles = 24 cycles. Therefore, in the example of FIG. 131, compared to the case of FIG. 130, the total command size is reduced by 3 bytes, and the total execution cycle is reduced by 8 cycles. In this way, by embedding the WORDSEL module itself as a command in arbitrary processing, it is possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing game control processing. .

Also, as can be understood by comparing FIGS. 130 and 131, the command group that occupied 4 lines (1st to 4th lines) in FIG. 130(b) no longer needs to be written in FIG. 131. Therefore, it is possible to reduce the number of commands and the design load.

Furthermore, the WORDSEL module is a general-purpose module that is the target of the command "RST," but by omitting this general-purpose module, valuable general-purpose module space can be freed up and other modules can be placed in that area. . In this way, resources can be used effectively.

However, in the example of FIG. 131, the command "LD A,L" is omitted. Therefore, if it is necessary to set the value of the L register to the A register, it is necessary to separately add the command "LD A,L". However, since the command "LD A,L" has a command size of "1" and an execution cycle of "1", the effect of adding such a command is small.

Note that this WORDSEL module is not limited to pachinko machines, but also slot machines, for example, the CAL_MOD module for executing the state-based module execution process shown in step S3100-21 in FIG. It is used in the HID_JUG module for executing this precursor start determination process.

FIG. 132 is an explanatory diagram for explaining the CAL_MOD module. The CAL_MOD module shown in FIG. 132 executes module execution processing for each state, that is, executes a module corresponding to the state.

At the stage of executing such a CAL_MOD module, an offset value is already held in a predetermined register (eg, A register). The index “CAL_MOD:” in the first line of FIG. 132(a) indicates the start address of the CAL_MOD module. The command "LD HL, T_INT_PHASE" on the second line sets the start address "T_INT_PHASE" of the 2-byte data group to be read from in the HL register. The command "ADD A, A" on the third line adds the value of the A register to the value of the A register, thereby doubling the value of the A register. Here, the value of the A register is doubled because the value from which to read is a 2-byte value. That is, since data is allocated to the table in units of 2 bytes, it is necessary to offset the address by 2 in order to read the data. The command "ADDWB HL,A" on the fourth line adds the value of the A register to the value of the HL register, and updates the HL register.

Then, the 2-byte value stored at the address indicated by the HL register is read to the HL register by the command "LD HL, (HL)" on the 5th line of FIG. 132(a). The command "JP (HL)" on the sixth line moves to the address indicated by the HL address.

Here, by replacing the command with "ADDALDW", the command group in FIG. 132(a) can be changed as shown in FIG. 132(b). The index “CAL_MOD:” in the first line of FIG. 132(b) indicates the start address of the CAL_MOD module. The command "LD HL, T_INT_PHASE" on the second line sets the start address "T_INT_PHASE" of the 2-byte data group to be read from in the HL register. The command "ADDALDW HL, (HL)" on the third line adds the value of the A register to the value of the HL register twice, and the 2-byte value stored at the address indicated by the HL register after the addition is stored in the HL register. Read out. Then, the command "JP (HL)" on the fourth line moves to the address indicated by the HL address.

Here, the total command size of the commands of the CAL_MOD module shown in FIG. 132(a) is 3 bytes of the command "LD HL, T_INT_PHASE" on the 2nd line + 1 byte of the command "ADD A, A" on the 3rd line + 1 byte of the command "ADD A, A" on the 4th line. 1 byte of the command “ADDWB HL,A” + 2 bytes of the command “LD HL, (HL)” on the 5th line + 2 bytes of the command “JP (HL)” on the 6th line = 9 bytes, and the total execution cycle is 2 lines. 3rd cycle + 1 cycle on 3rd row + 1 cycle on 4th row + 4 cycles on 5th row + 2 cycles on 6th row = 11 cycles. On the other hand, the total command size of the CAL_MOD module commands shown in FIG. 132(b) is 3 bytes for the command "LD HL, T_INT_PHASE" on the second line + 2 bytes for the command "ADDALDW HL, (HL)" on the third line + 4 lines. The second command "JP (HL)" is 2 bytes = 7 bytes, and the total execution cycle is 3 cycles for the 2nd line + 6 cycles for the 3rd line + 2 cycles for the 4th line = 11 cycles. Therefore, by replacing the command group in FIG. 132(a) with the command group in FIG. 132(b), the total command size is reduced by 2 bytes. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 133 is an explanatory diagram for explaining the HID_JUG module. The HID_JUG module shown in FIG. 133 executes this precursor start determination process.

The index “HID_JUG:” in the first line of FIG. 133(a) indicates the start address of the HID_JUG module. The command "LDQ A, (LOW _NMD_KND)" on the second line sets the value of the Q register as the upper 1 byte of the address, sets the value of the lower 1 byte of the address "_NMD_KND" as the lower 1 byte of the address, and stores it at that address. Read the value (normal mode type) to the A register. The command "LD HL, T_DAT_PGM-2" on the third line sets the start address (the value obtained by subtracting 2 from "T_DAT_PGM") of the 2-byte data group to be read from in the HL register. The command "ADD A, A" on the fourth line adds the value of the A register to the value of the A register, thereby doubling the value of the A register. Here, the value of the A register is doubled because the value from which to read is a 2-byte value. That is, since data is allocated to the table in units of 2 bytes, it is necessary to offset the address by 2 in order to read the data. The command "ADDWB HL,A" on the fifth line adds the value of the A register to the value of the HL register, and updates the HL register. Then, the 2-byte value stored at the address indicated by the HL register is read to the HL register by the command "LD HL, (HL)" on the 6th line of FIG. 133(a).

Here, by replacing the command with "ADDALDW", the command group in FIG. 133(a) can be changed as shown in FIG. 133(b). The index “HID_JUG:” in the first line of FIG. 133(b) indicates the start address of the HID_JUG module. The command "LDQ A, (LOW _NMD_KND)" on the second line sets the value of the Q register as the upper 1 byte of the address, sets the value of the lower 1 byte of the address "_NMD_KND" as the lower 1 byte of the address, and stores it at that address. Read the value (normal mode type) to the A register. The command "LD HL, T_DAT_PGM-2" on the third line sets the start address (the value obtained by subtracting 2 from "T_DAT_PGM") of the 2-byte data group to be read from in the HL register. The command "ADDALDW HL, (HL)" on the fourth line adds the value of the A register to the value of the HL register twice, and the 2-byte value stored at the address indicated by the HL register after the addition is stored in the HL register. Read out.

Here, the total command size of the HID_JUG module commands shown in FIG. 133(a) is 2 bytes of the command "LDQ A, (LOW_NMD_KND)" on the second line + the command "LD HL, T_DAT_PGM-2" on the third line. 3 bytes + 4th line command “ADD A, A” 1 byte + 5th line command “ADDWB HL, A” 1 byte + 6th line command “LD HL, (HL)” 2 bytes = 9 bytes, total execution The cycle is 2 cycles for the 2nd row + 3 cycles for the 3rd row + 1 cycle for the 4th row + 1 cycle for the 5th row + 4 cycles for the 6th row = 11 cycles. On the other hand, the total command size of the HID_JUG module commands shown in FIG. 133(b) is 2 bytes of the command "LDQ A, (LOW_NMD_KND)" on the second line + 3 bytes of the command "LD HL, T_DAT_PGM-2" on the third line. Byte + 2 bytes of the command "ADDALDW HL, (HL)" on the 4th line = 7 bytes, and the total execution cycle is 2 cycles on the 2nd line + 3 cycles on the 3rd line + 6 cycles on the 4th line = 11 cycles. Therefore, by replacing the command group in FIG. 133(a) with the command group in FIG. 133(b), the total command size is reduced by 2 bytes. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

<Command “INLD”, “INLDTQR”>
The RAMSET module is a general-purpose module for RAM set processing, that is, for setting predetermined values (initial values) to variables of the main RAM 300c. Here, an example will be described in which the RAMSET module is placed at 0020H on the memory map.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls the RAMSET module as a subroutine in any process, and executes the RAMSET module. The RAMSET module transfers a plurality of one-byte values written in the program data of the main ROM 300b to an area that holds a plurality of data treated as variables in the work area of the main RAM 300c. In this way, the values of multiple variables are set. Here, the number of data to be transferred is simply referred to as the number of data.

FIG. 134 is a flowchart showing specific processing of the RAMSET module. Here, as an arbitrary process, a part of the CPU INIT module that executes the CPU initialization process shown in step S100 in FIG. 22 will be described. The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the description of the RAMSET module, the first register is the B register, the second register is the HL register, the first value is "1", and the second value is "2". Note that it goes without saying that the first value and the second value can be set arbitrarily.

As shown in FIG. 134(a), the main CPU 300a sets the start address of a 1-byte data group to be a transfer source in the HL register in an arbitrary process (S1). Then, the RAMSET module is called as a subroutine (S2).

As shown in FIG. 134(b), the main CPU 300a reads the 1-byte value stored in the address indicated by the HL register in the RAMSET module to the B register (S3). This 1-byte value indicates the number of data. Next, the main CPU 300a stores the data at the address specified by adding "2" to the HL register to the address specified by the value stored at the address shown by adding "1" to the HL register. The next address to be transferred is set by adding "2" to the value of the HL register (S4). Next, the main CPU 300a decrements the value of the B register (subtracts "1") and determines whether the decremented result is 0 (S5). Here, if the decremented result is not 0 (NO in S5), the process from step S4 is repeated, and if the decremented result is 0 (YES in S5), the corresponding RAMSET module is terminated and Return to the routine (S6).

FIGS. 135 and 136 are explanatory diagrams for explaining an example of a command for implementing the RAMSET module. Of these, FIG. 135(a) shows a command group for arbitrary processing that calls the RAMSET module, FIG. 135(b) shows a command group for the RAMSET module, and FIG. 135(c) shows the program data of the main ROM 300b. FIG. 135(d) shows the arrangement of the 1-byte data group in the work area of the main RAM 300c. The flowchart shown in FIG. 134 is realized, for example, by the program shown in FIG. 135.

The command "LD HL, D_RAM_RST_INI" in the first line of FIG. 135(a) sets the start address "D_RAM_RST_INI" of the 1-byte data group to be the transfer source in the HL register. The command on the first line corresponds to step S1 in FIG. 134(a). Then, the RAMSET module is called as a subroutine by the command "RST RAMSET" on the second line. The command on the second line corresponds to step S2 in FIG. 134(a).

The index “RAMSET:” in the first line of FIG. 135(b) indicates the start address of the RAMSET module. The command "LD B, (HL)" on the second line reads the 1-byte value stored at the address indicated by the HL register into the B register. At this time, the address "D_RAM_RST_INI" is set in the HL register as shown in FIG. 135(a). Therefore, the 1-byte value "(@D_RAM_RST_INI-D_RAM_RST_INI-1)/2" in the second line of FIG. 135(c) is read to the B register as the data number (transfer repetition number). Note that "@D_RAM_RST_INI" is the address next to the last address of the 1-byte data group that is the transfer source, and D_RAM_RST_INI is the first address of the 1-byte data group that is the transfer source, so the value of @D_RAM_RST_INI - D_RAM_RST_INI - 1 ( The value of 1-byte value indicating the number of data) is the total number of bytes of the 1-byte value, and by dividing that value by 2, which is the number of combinations of address and value, the number of data is derived. In the example of FIG. 135(c), the number of data is (11-1)/2=5. The command on the second line of FIG. 135(c) corresponds to step S3 of FIG. 134(b).

The index "RAMSET_10:" in the third line of FIG. 135(b) indicates the start address of the repeat process. The command “INLD AC, (HL)” on the 4th line and the command “LDQ (C), A” on the 5th line specify the value stored at the address indicated by adding “1” to the HL register. The value stored in the address indicated by adding "2" to the HL register is stored in the address, and "2" is added to the value of the HL register to set the next address to be transferred. The commands on the fourth and fifth lines correspond to step S4 in FIG. 134(b).

Here, the command "INLD AC, (HL)" stores the value stored in the address indicated by adding "1" to the HL register into the C register, and then stores the value stored in the address indicated by adding "1" to the HL register and adding "2" to the HL register. This command stores the value stored at the address indicated by in the A register, adds "2" to the value of the HL register, and updates the value of the HL register. The command size of such a command is "2" and the execution cycle is "4".

For example, if the HL register has the value of the address "D_RAM_RST_INI", the lower 1 byte value of the 2-byte variable "R_TZ1_STP" in the third line of FIG. 135(c) is stored in the C register, and The value of "@DSP_HAZ" in the third line is stored in the A register.

In addition, the command "LDQ (C), A" on the 5th line of FIG. , is a command to store the value of the A register. The command size of such a command is "2" and the execution cycle is "3".

For example, the value of the C register, that is, the value of the lower 1 byte of "R_TZ1_STP" is set as the lower 1 byte of the address, and the value of the A register, that is, the value of "@DSP_HAZ" is stored in that address.

Here, in FIG. 135(c) and FIG. 135(d), the variable "R_TZ1_STP" indicates the special symbol 1 stop symbol number, the variable "R_TZ2_STP" indicates the special symbol 2 stop symbol number, and the variable "R_TZ1_DSP" indicates the counter value of the special symbol 1 display symbol counter, the variable "R_TZ2_DSP" indicates the counter value of the special symbol 2 display symbol counter, and the variable "R_EXT_SEC_TMR" indicates the security external signal timer value. Note that the arrangement of variables shown in FIG. 135(d) does not need to be continuous as shown in the figure, and may be spaced apart.

Next, the value of the B register is decremented (subtracted by "1") by the command "DJNZ RAMSET_10" on the 6th line of FIG. , if the decremented result is 0, the process moves to the command next to the command in question. Here, the number of data is "5", so if the process from "RAMSET_10" is repeated five times, the value of the B register becomes 0. The command on the sixth line corresponds to step S5 in FIG. 134(b). Then, the command "RET" on the seventh line returns to the routine one stage higher. The command on the seventh line corresponds to step S6 in FIG. 134(b).

In this way, as shown in FIG. 136, multiple 1-byte values (55H, 77H, 66H, 22H, AAH) written in the program data of the main ROM 300b are stored in the variables ("R_TZ1_STP", "R_TZ2_STP") in the work area of the main RAM 300c. ", "R_TZ1_DSP", "R_TZ2_DSP", "R_EXT_SEC_TMR").

The RAMSET module is called as a subroutine by multiple modules. For example, the CPUINIT module executes the CPU initialization process shown in step S100 in FIG. 22, the SEC_SET module executes the security setting process, and the state management process (error management process) shown in step S400-21 in FIG. STC_PRC module, FZ_STA module that executes the normal symbol fluctuation waiting process shown in step S810 of FIG. 52, FZ_SPN module that executes the normal symbol fluctuation process shown in step S820 of FIG. 53, normal symbol change process shown in step S830 of FIG. 54 The FZ_STP module that executes the symbol stop symbol display process, the FD_PRE module that executes the normal electric accessory prize opening preprocessing shown in step S840 in FIG. 55, and the normal electric accessory prize opening control shown in step S850 in FIG. 57 FD_OPN module that executes the process, TZ_STA module that executes the special symbol change waiting process shown in step S610 of FIG. 37, TZ_SPN module that executes the special symbol change process shown in step S620 of FIG. 41, step S630 of FIG. 43 The TZ_STP module executes the special symbol stop symbol display process shown in , the TD_PRE module executes the big winning opening pre-opening process shown in step S710 of FIG. 45, and the big winning opening control process shown in step S720 of FIG. 47. TD_OPN module to execute, TD_EFF module to execute the big winning opening closing effective process shown in step S730 of FIG. 48, TD_END module to execute the big winning opening end wait process shown in step 740 of FIG. 49, step S630 of FIG. 43 The TOKZERO module executes the special symbol change waiting state transition process (not shown) executed in the process, the CHGSTS module executes the number-cut management process shown in step S613 of FIG. 40, and the CHGSTS module shown in step S450 of FIG. It is called from the RNK_PRC module, etc. that executes settings-related processing.

In this way, the total command size of the RAMSET module commands shown in Figure 135(b) is 1 byte of the command "LD B, (HL)" on the second line + the command "INLD AC, (HL)" on the fourth line. 2 bytes + 5th line command “LDQ (C), A” 2 bytes + 6th line command “DJNZ RAMSET_10” 2 bytes + 7th line command “RET” 1 byte = 8 bytes, and the total execution cycle is 2 lines. 2nd cycle + 4th cycle in the 4th row + 3 cycles in the 5th row + 3 cycles (or 2 cycles) in the 6th row + 3 cycles in the 7th row = 15 cycles (or 14 cycles). Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "DJNZ RAMSET_10". By providing such a RAMSET module, the command size "RST RAMSET" with a command size of 1 byte can be used without performing RAM set processing in each of the above-mentioned modules, so the command can be shortened and the game control processing can be This makes it possible to secure the capacity of the control area for this purpose.

FIG. 137 is an explanatory diagram for explaining another example of commands for implementing the RAMSET module. Here, the command group of the RAMSET module in FIG. 135(b) is replaced with the command group of the RAMSET module in FIG. 137(b), and the command group for any other process that calls the RAMSET module in FIG. 135(a) , a 1-byte data group in the program data of the main ROM 300b in FIG. 135(c), and a 1-byte data group in the work area of the main RAM 300c in FIG. 135(d) are shown in FIGS. 137(a), 137(c), It is used as is as shown in FIG. 137(d). Here, as in FIGS. 137(a), 137(c), and 137(d), processing substantially equivalent to FIGS. 135(a), 135(c), and 135(d) will be explained. The explanation will be omitted and only the different processing in FIG. 137(b) will be explained.

The index “RAMSET:” in the first line of FIG. 137(b) indicates the start address of the RAMSET module. The command "LD B, (HL)" on the second line reads the 1-byte value stored at the address indicated by the HL register into the B register. At this time, the address "D_RAM_RST_INI" is set in the HL register as shown in FIG. 137(a). Therefore, the 1-byte value "(@D_RAM_RST_INI-D_RAM_RST_INI-1)/2" in the second line of FIG. 137(c) is read to the B register as the data count. The command on the second line of FIG. 137(b) corresponds to step S3 of FIG. 134(b).

The command "INLDTQR AC, (HL)" on the third line of FIG. The value stored in the address indicated by adding "2" is transferred, "2" is added to the value of the HL register to set the next address to be transferred, and the value of the B register is decremented ("1"). This process is repeated until the decremented result becomes 0. The command on the third line corresponds to steps S4 and S5 in FIG. 134(b).

Here, the command "INLDTQR AC, (HL)" takes the value of the Q register as the upper 1 byte of the address, and sets the value stored at the address indicated by adding "1" to the HL register as the lower 1 byte of the address. Byte, transfer the value stored in the address indicated by adding "2" to the HL register to that address, add "2" to the value of the HL register and update the value of the HL register, and This is a command that decrements the value of the register (subtracts by "1") and repeats the value transfer until the decremented result becomes 0. The command size of such a command is "2" and the execution cycle is "5".

For example, if the HL register has the value of the address "D_RAM_RST_INI", the value of the Q register is the upper 1 byte of the address, and the value of the lower 1 byte of "R_TZ1_STP" in the 3rd line of FIG. 137(c) is the value of the address. The value of "@DSP_HAZ" in the third line of FIG. 137(c) is transferred to that address, "2" is added to the value of HL register, and the value of B register is decremented ("1"). '') and the transfer is repeated five times until the decremented result becomes 0, that is, the transfer is repeated five times.

Then, the command "RET" on the fourth line in FIG. 137(b) returns to the routine one stage higher. The command on the fourth line corresponds to step S6 in FIG. 134(b).

The total command size of the RAMSET module commands in Figure 137(b) is 1 byte for the command “LD B, (HL)” on the 2nd line + 2 bytes for the command “INLDTQR AC, (HL)” on the 3rd line + 2 bytes for the command “INLDTQR AC, (HL)” on the 4th line. 1 byte of the command "RET" = 4 bytes, and the total execution cycle is 2 cycles on the 2nd line + 5 cycles on the 3rd line + 3 cycles on the 4th line = 10 cycles. Therefore, compared to the case of FIG. 135(b), the total command size is reduced by 4 bytes, and the total execution cycle is also reduced by at least 4 cycles. In particular, in the example of FIG. 135(b), if the value of the B register in the command "DJNZ RAMSET_10" is 2 or more, that value is applied for 10 cycles (4 cycles on the 4th line + 3 cycles on the 5th line + 3 cycles on the 6th line). Since the total execution cycles increase by the amount multiplied by , the amount of reduction in the total execution cycles in FIG. 137(b) also increases. With such a RAMSET module, it is possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing game control processing.

Also, compared to the example of FIG. 135, the A register and C register are not used here. Therefore, the value of the A register or the C register will not be updated unintentionally. In addition, in the example in Figure 135, if the A register or C register was already in use, it was necessary to stack it and save the values of the A register or C register, but here, the A register or C register is used. Therefore, there is no need for stack processing. In this way, resources can be used effectively.

Also, in order to understand by comparing FIG. 135(b) and FIG. 137(b), the command group that occupied four lines (3rd to 6th lines) in FIG. 135(b) is 137(b), it can be expressed in one line (third line), making it possible to reduce the number of commands themselves and reduce the design load.

Note that this RAMSET module is used not only in pachinko machines but also in slot machines as a TABLSET module (general-purpose module) that executes table setting processing to set predetermined values (initial values) to variables in the main RAM 500c. ing.

FIG. 138 is an explanatory diagram for explaining an example of a command for implementing the TABLSET module. Of these, FIG. 138(a) shows a command group for arbitrary processing that calls the TABLSET module, FIG. 138(b) shows a command group for the TABLSET module, and FIG. 138(c) shows the program data of the main ROM 500b. FIG. 138(d) shows the arrangement of the 1-byte data group in the work area of the main RAM 500c.

Here, as an optional process, the error wait process shown in step S2200-11 in FIG. 89 and step S2800-39 in FIG. Some of them are mentioned.

The command "LD HL, T_ERR_RCV" in the first line of FIG. 138(a) sets the start address "T_ERR_RCV" of the 1-byte data group to be the transfer source in the HL register. Then, the TABLSET module is called as a subroutine by the command "RST TABLSET" on the second line.

The index “TABLSET:” in the first line of FIG. 138(b) indicates the start address of the TABLSET module. The command "PUSH BC" on the second line saves the value of the BC register to the stack area. Interrupts are prohibited by the command "DI" on the third line.

The 1-byte value stored at the address indicated by the HL register is read into the B register by the command "LD B, (HL)" in the fourth line of FIG. 138(b). At this time, the address "T_ERR_RCV" is set in the HL register as shown in FIG. 138(a). Therefore, the 1-byte value "(T_ERR_RCV_-T_ERR_RCV)/2" in the second line of FIG. 138(c) is read into the B register as the data number (transfer repetition number). Note that "T_ERR_RCV_" is the address after the last address of the 1-byte data group that is the transfer source, and T_ERR_RCV is the first address of the 1-byte data group that is the transfer source, so the value of T_ERR_RCV_ - T_ERR_RCV (indicating the number of data The value of 1-byte value) is the total number of bytes of the 1-byte value, and by dividing that value by 2, which is the number of combinations of addresses and values, the number of data is derived. In the example of FIG. 138(c), the number of data is 9/2=4.

The index “TABLSET10:” in the fifth line of FIG. 138(b) indicates the start address of the repetitive process. The command “INLD AC, (HL)” on the 6th line and the command “LDQ (C), A” on the 7th line specify the value stored at the address indicated by adding “1” to the HL register. The value stored in the address indicated by adding "2" to the HL register is stored in the address, and "2" is added to the value of the HL register to set the next address to be transferred.

For example, if the HL register has the value of the address "T_ERR_RCV", the lower 1 byte value of the 2-byte variable "_ERR_NUM" in the third line of FIG. 138(c) is stored in the C register, and The value "0" in the third line is stored in the A register.

In addition, the command "LDQ (C), A" on the 7th line of FIG. , is a command to store the value of the A register.

For example, the value of the C register, that is, the value of the lower 1 byte of "_ERR_NUM" is set as the lower 1 byte of the address, and the value of the A register, that is, the value of "0" is stored in that address.

Here, in FIGS. 138(c) and 138(d), the variable "_ERR_NUM" indicates the error number, the variable "_CRE_TMR" indicates the credit button detection timer, and the variable "_CRE_FLG" indicates the credit button detection flag. , and the variable "_SNS_OLD" indicates the previous state of the medal passing sensor bit. Note that the arrangement of variables shown in FIG. 138(d) does not need to be continuous as shown in the figure, and may be spaced apart.

Next, the value of the B register is decremented (subtracted by "1") by the command "DJNZ TABLSET10" on the 8th line of FIG. , if the decremented result is 0, the process moves to the command next to the command in question. Here, the number of data is "4", so if the process from "TABLSET10" is repeated four times, the value of the B register becomes 0.

Interruption is permitted by the command "EI" on the 9th line of FIG. 138(b). The data saved in the stack area is returned to the BC register by the command "POP BC" on the 10th line. Then, the command "RET" on the 11th line returns to the routine one level higher.

Here, by replacing the command with "INLDTQR", the command group can be written as follows.

FIG. 139 is an explanatory diagram for explaining another example of commands for realizing the TABLSET module. Here, the command group of the TABLSET module in FIG. 138(b) is replaced with the command group of the TABLSET module in FIG. 139(b), and any other processing command that calls the TABLSET module in FIG. 138(a) The 1-byte data group in the program data of the main ROM 500b in FIG. 138(c) and the 1-byte data group in the work area of the main RAM 500c in FIG. 138(d) are shown in FIGS. 139(a) and 139(c). , is used as is as shown in FIG. 139(d). Here, as in FIGS. 139(a), 139(c), and 139(d), processing substantially equivalent to FIGS. 138(a), 138(c), and 138(d) will be explained. The explanation will be omitted and only the different processing in FIG. 139(b) will be explained.

The index “TABLSET:” in the first line of FIG. 139(b) indicates the start address of the TABLSET module. The command "PUSH BC" on the second line saves the value of the BC register to the stack area. Interrupts are prohibited by the command "DI" on the third line.

The 1-byte value stored at the address indicated by the HL register is read into the B register by the command "LD B, (HL)" in the fourth line of FIG. 139(b). At this time, the address "T_ERR_RCV" is set in the HL register as shown in FIG. 139(a). Therefore, the 1-byte value "(T_ERR_RCV_-T_ERR_RCV)/2" in the second line of FIG. 139(c) is read into the B register as the data number (transfer repetition number). In the example of FIG. 139(c), the number of data is 4.

The command "INLDTQR (HL)" on the 5th line of FIG. The value stored in the address indicated by the value added by `` is transferred, the next address to be transferred is set by adding ``2'' to the value of the HL register, and the value of the B register is decremented (subtracted by ``1''). The process is repeated until the decremented result becomes 0.

Subsequently, an interrupt is permitted by the command "EI" on the 6th line of FIG. 139(b). The command "POP BC" on the seventh line causes the data saved in the stack area to be returned to the BC register. Then, the command "RET" on the 8th line returns to the routine one stage higher.

Here, the total command size of the commands of the TABLSET module shown in FIG. 138(b) is 1 byte of the command "PUSH BC" on the 2nd line + 1 byte of the command "DI" on the 3rd line + 1 byte of the command "LD B" on the 4th line. , (HL)'' 1 byte + 6th line command ``INLD AC, (HL)'' 2 bytes + 7th line command ``LDQ (C), A'' 2 bytes + 8th line command ``DJNZ TABLSET10'' 2 bytes + 9 lines 1 byte of the command “EI” on the 10th line + 1 byte of the command “POP BC” on the 11th line + 1 byte of the command “RET” on the 11th line = 12 bytes, and the total execution cycle is 3 cycles on the 2nd line + 1 cycle on the 3rd line + 4 2 cycles on the row + 4 cycles on the 6th row + 3 cycles on the 7th row + 3 cycles (or 2 cycles) on the 8th row + 1 cycle on the 9th row + 3 cycles on the 10th row + 3 cycles on the 11th row = 23 cycles (or 22 cycles). On the other hand, the total command size of the commands of the TABLSET module shown in FIG. 139(b) is: 1 byte of the command "PUSH BC" on the 2nd line + 1 byte of the command "DI" on the 3rd line + 1 byte of the command "LD B," on the 4th line. (HL)” 1 byte + 5th line command “INLDTQR (HL)” 2 bytes + 6th line command “EI” 1 byte + 7th line command “POP BC” 1 byte + 8th line command “RET” 1 byte = 8 bytes, and the total execution cycle is 3 cycles on the 2nd line + 1 cycle on the 3rd line + 2 cycles on the 4th line + 5 cycles on the 5th line + 1 cycle on the 6th line + 3 cycles on the 7th line + 3 cycles on the 8th line = 18 cycles. . Therefore, compared to the case of FIG. 138(b), the total command size is reduced by 4 bytes, and the total execution cycle is also reduced by at least 5 cycles. In particular, in the example of FIG. 138(b), if the value of the B register in the command "DJNZ TABLSET10" is 2 or more, that value is applied for 10 cycles (4 cycles on the 6th line + 3 cycles on the 7th line + 3 cycles on the 8th line). Since the total execution cycles increase by the amount multiplied by , the amount of reduction in the total execution cycles in FIG. 139(b) also increases. By using such a TABLSET module, it is possible to shorten commands, reduce processing load, and secure the capacity of the control area for performing game control processing.

Also, compared to the example of FIG. 138, the A register and C register are not used here. Therefore, the value of the A register or the C register will not be updated unintentionally. In addition, in the example in Figure 138, if the A register and C register were already used, it was necessary to stack them and save the values of the A register and C register, but here, the A register and C register are used. Therefore, there is no need for stack processing. In this way, resources can be used effectively.

In addition, in order to understand by comparing FIG. 138(b) and FIG. 139(b), the command group that occupied four lines (5th line to 8th line) in FIG. 138(b) is 139(b), it can be expressed in one line (fifth line), making it possible to reduce the number of commands themselves and reduce the design load.

Note that the TABLSET module is called as a subroutine not only by the ERRWAIT module but also by a plurality of modules. For example, in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, the transition is made selectively depending on the gaming state and performance state, and the present premonitory process (AT state = "3") is executed. The HID_LOT module executes the execution flag setting process shown in step S2400-11 in FIG. 91, and the EXE_SET module executes the execution flag setting process shown in step S2400-11 in FIG. The FIN_LOT module that executes the execution flag setting process shown in step S2400-11 in FIG. 91 and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. ), and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. ”), and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 7"), the RANKSET module that executes the setting value switching process shown in step S2020 of FIG. 85, the FGSETUP module that executes the symbol code setting process shown in step S2400 of FIG. 91, and step S2900 of FIG. 96. It is called from the GAMESET module that executes the game transition process shown in , the JCGMSET module that executes the accessory action symbol display process shown in step S2900-3 of FIG. 96, and the like.

<Command “DECM”, “DECWM”>
The BYTEDEC module is a general-purpose module for byte counter subtraction processing, that is, for decrementing a 1-byte variable in the main RAM 300c by 1. Note that the BYTEDEC module not only decrements, but also sets a zero flag and a carry flag as a result of the decrement.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls the BYTEDEC module as a subroutine in any process, and executes the BYTEDEC module. The BYTEDEC module decrements the 1-byte value held in the main RAM 300c.

FIG. 140 is a flowchart showing specific processing of the BYTEDEC module. Here, as an arbitrary process, a part of the TZ_STP module that executes the special symbol stop symbol display process shown in step S630 of FIG. 43 will be described. The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the description of the BYTEDEC module, the predetermined register is the HL register.

The main CPU 300a executes arbitrary processing as shown in FIG. 140(a). The main CPU 300a first sets the address of the variable to be decremented in the HL register (S1). Then, the BYTEDEC module is called as a subroutine (S2).

As shown in FIG. 140(b), the main CPU 300a decrements by 1 the 1-byte value stored at the address indicated by the HL register in the BYTEDEC module, and sets a zero flag and a carry flag (S3). Then, the BYTEDEC module is terminated and the routine returns to the next step higher (S4). The decrement mode and flag setting will be described in detail below.

FIG. 141 is an explanatory diagram for explaining the decrement mode and the setting of the zero flag and carry flag in the BYTEDEC module. Here, if the value before decrementing is 1 or more (1 or 2 or more), the value after decrementing will be the value decremented by 1. However, if the value before the decrement is 0, the value after the decrement is not -1 but 0. That is, the lower limit value is 0 and never becomes a negative value. Such maintenance of 0 may be achieved by decrementing and further incrementing, or forcibly reading 0, if the value before decrementing is 0, or may be achieved by not decrementing.

Also, if the value before decrement is 2 or more, the value after decrement will be 1 or more, so the zero flag will not be set and will be 0. However, if the value before decrement is 1 or 0, it will be 0 after decrement, so the zero flag will be set. becomes 1. Further, in the BYTEDEC module, if the value is 1 before decrementing, it becomes 0 after decrementing, and in that case, the carry flag is set to 1. If the value before decrement is 2 or more or 0, the carry flag is not set and is set to 0.

Returning to FIG. 140(a), when the zero flag and carry flag are set by the BYTEDEC module, the main CPU 300a performs various processes using the values of the flags. For example, here, it is determined that the decrement is not a process of subtracting 1 to make 0 (S5), and as a result, if it is not a process of subtracting 1 to make 0 (YES in S5), then the special symbol If the process is to move to a predetermined address (TZ_STP_10) for flag check processing (S6) and subtract 1 to make it 0 (NO in S5), the next process is performed without moving.

FIG. 142 is an explanatory diagram for explaining an example of a command for implementing the BYTEDEC module. Of these, FIG. 142(a) shows a command group for arbitrary processing that calls the BYTEDEC module, and FIG. 142(b) shows a command group for the BYTEDEC module. The flowchart shown in FIG. 140 is realized, for example, by the program shown in FIG. 142.

The command "LDQ HL, LOW R_EXT_HCT" in the first line of FIG. 142(a) reads the value of the Q register to the H register, and reads the value of the lower 1 byte of the address "R_EXT_HCT" to the L register. The command on the first line corresponds to step S1 in FIG. 140(a). Then, the BYTEDEC module is called as a subroutine by the command "CALLF BYTEDEC" on the second line. The command on the second line corresponds to step S2 in FIG. 140(a).

Here, the command "CALLF BYTEDEC" is a command that can call only the range from 0000H to 11FFH in the memory map. The command "CALLF" used for calling has the same execution cycle as the normal command "CALL" at "4", but the command size of the normal command "CALL" is "3", while the command size of the command "CALLF" The command size is "2". Therefore, the program can be shortened. Note that instead of the command "CALLF BYTEDEC", the BYTEDEC module may be called using "RST BYTEDEC", similar to the general-purpose module described above. By doing so, the command size can be set to "1".

The index “BYTEDEC:” in the first line of FIG. 142(b) indicates the start address of the BYTEDEC module. The command "LD A, (HL)" on the second line reads the 1-byte value stored at the address indicated by the HL register into the A register. In such a command "LD A, (HL)", the second zero flag changes by its execution. Then, by the command "RT Z, A" on the third line, if the value of the A register is 0 (if the second zero flag is 1), the routine returns to the routine one stage higher. At this time, if the value of the A register is 0, the zero flag (first zero flag) becomes 1 and the carry flag becomes 0 by the command "RT Z, A". In this way, if the value stored at the address indicated by the HL register is 0, it is possible to set the zero flag to 1 and the carry flag to 0 without decrementing the value.

The command "CP A, 2" on the 4th line of FIG. 142(b) compares the value of the A register with 2. If the A register is 2 or more, the carry flag is not set and becomes 0, and if it is 1, the carry flag is set to 0. , the carry flag is set to 1. Note that the command "CP A, 2" is a command that sets a carry flag when the A register is less than 2, but at the execution stage of the command "CP A, 2", the value of the A register is 1 or 2 or more. (Since it is not 0), by setting the carry flag when it is less than 2, the carry flag will be set when it is 1. In this way, if the value of the A register is 1, the carry flag can be set to 1. The command "DEC (HL)" on the fifth line decrements the 1-byte value stored at the address indicated by the HL register by 1, thereby updating the value stored at the address indicated by the HL register. Here, if the value stored at the address indicated by the HL register is 2 or more, the decremented value is 1 or more, so the zero flag is not set and becomes 0, and if it is 1, the decremented value becomes 0, so The zero flag is set and becomes 1. Note that the carry flag does not change depending on the command "DEC (HL)". In this way, if the value stored at the address indicated by the HL register is 2 or more, it can be set as zero flag = 0 and carry flag = 0, and if it is 1, it can be set as zero flag = 1 and carry flag = 1. The commands on the second to fifth lines correspond to step S3 in FIG. 140(b). Then, the command "RET" on the sixth line returns to the routine one stage higher. The command on the sixth line corresponds to step S4 in FIG. 140(b). In this way, it is possible to decrement the value stored at the address indicated by the HL register by 1, and to set the zero flag and carry flag.

Subsequently, if the carry flag is 0 (NC), the command "JR NC, TZ_STP_10" on the third line of FIG. 142(a) moves to TZ_STP_10. The command on the third line corresponds to steps S5 and 6 in FIG. 140(a). In this way, processing based on the results of the BYTEDEC module becomes possible.

The BYTEDEC module is called as a subroutine by multiple modules. For example, the TMR_NEW module executes the timer update process shown in step S400-15 in FIG. 26, the STC_PRC module executes the state management process (error management process) shown in step S400-21 in FIG. 26, and step S630 in FIG. The TZ_STP module executes the special symbol stop symbol display process shown in , the CHGSTS module executes the count cut management process shown in step S613 of FIG. 40, and the count switch passage process (big prize opening passage The TDOVCHK module executes the big winning hole excessive winnings monitoring process that is executed after setting the big winning hole entry command (S540-3) in the process), and the state management process (error management process) shown in step S400-21 of FIG. ) is called from the BER_CHK module that executes base abnormality error monitoring processing, which is a subroutine.

In this way, the total command size of the BYTEDEC module commands shown in Figure 142(b) is 1 byte for the command "LD A, (HL)" on the second line + 1 byte for the command "RT Z, A" on the third line. + 2 bytes of the command “CP A, 2” on the 4th line + 1 byte of the command “DEC (HL)” on the 5th line + 1 byte of the command “RET” on the 6th line = 6 bytes, and the total execution cycle is 2 bytes on the 2nd line. cycle + 4 cycles (or 2 cycles) on the 3rd row + 2 cycles on the 4th row + 4 cycles on the 5th row + 3 cycles on the 6th row = 15 cycles (or 13 cycles). Note that the cycle number in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "RT Z, A". By providing such a BYTEDEC module, the command size "CALLF BYTEDEC" with a command size of 2 bytes can be used without performing byte counter subtraction processing in each of the above-mentioned modules, so the command can be shortened and the game control processing This makes it possible to secure the capacity of the control area for performing this.

FIG. 143 is an explanatory diagram for explaining another example of commands for realizing the BYTEDEC module. Here, the BYTEDEC module command group in FIG. 142(b) is replaced with the BYTEDEC module command group in FIG. 143(b), and any other command group for any process that calls the BYTEDEC module in FIG. 142(a). is used as is in FIG. 143(a). Here, as shown in FIG. 143(a), a description of the processing that is substantially the same as that of FIG. 142(a) will be omitted, and only the different processing of FIG. 143(b) will be described.

The index “BYTEDEC:” in the first line of FIG. 143(b) indicates the start address of the BYTEDEC module. By the command "DECM (HL)" on the second line, if the value stored at the address indicated by the HL register is 1 or more, it is decremented by 1, and if it is 0, it is maintained at 0.

Here, the command "DECM (HL)" decrements the 1-byte value stored at the address indicated by the HL register, and if the carry flag is set (-1), the address indicated by the HL register is This command forcibly stores 0 in a 1-byte value stored in . Then, if the value stored at the address indicated by the HL register is 1 or more, it is decremented by 1, and if it is 0, it is maintained at 0. By executing the command "DECM (HL)", if the value after decrement is zero (if the value before decrement is 1 or 0), zero flags (first zero flag and second zero flag) are set. If the value before decrement is zero, set a carry flag and set it to 1. The command size of such a command is "2" and the execution cycle is "5".

By the command "RET NZ" on the third line of FIG. 143(b), if the zero flag is not 1 (if the value after decrement is not zero), the routine returns to the routine one stage higher. Here, since decrement has already been performed by the command "DECM (HL)", the fact that the zero flag is not 1 indicates that the value before decrement is 2 or more. In that case, the zero flag is not set and becomes 0, and the carry flag is also not set and becomes 0, so it is possible to return to the routine one step higher. Note that "NZ" is mentioned here and the first zero flag is referred to, but normally when the first zero flag is changed, the second zero flag is also changed, so "NZ" is used in all processing. "NTZ" can also be used instead.

In addition, in the command "DECM (HL)", if the value stored at the address indicated by the HL register before decrementing is 1, it becomes 0 after decrementing, the zero flag = 1, the carry flag = 0, and the value is 0. If there is, it is not decremented and remains at 0, and the zero flag is set to 1 and the carry flag is set to 1. That is, regarding the carry flag, the specifications shown in FIG. 141 are reversed. Therefore, the carry flag is inverted (1→0, 0→1) by the command "CCF" on the fourth line of FIG. 143(b). Note that the zero flag does not change depending on the command "CCF". In this way, if the value stored at the address indicated by the HL register before decrementing is 1, it can be set as zero flag = 0 and carry flag = 1, and if it is 0, it can be set as zero flag = 1 and carry flag = 0. . The commands on the second to fourth lines correspond to step S3 in FIG. 140(b). Then, the command "RET" on the fifth line returns to the routine one stage higher. The command on the fifth line corresponds to step S4 in FIG. 140(b). In this way, it is possible to decrement the value stored at the address indicated by the HL register by 1, and to set the zero flag and carry flag.

Subsequently, if the carry flag is 0 (NC) by the command "JR NC, TZ_STP_10" on the third line of FIG. 143(a), the process moves to TZ_STP_10. The command on the third line corresponds to steps S5 and 6 in FIG. 140(a). In this way, processing based on the results of the BYTEDEC module becomes possible.

The total command size of the BYTEDEC module commands in Figure 143(b) is 2 bytes for the command “DECM (HL)” on the 2nd line + 1 byte for the command “RET NZ” on the 3rd line + 2 bytes for the command “CCF” on the 4th line. + 1 byte of the command "RET" on the 5th line = 6 bytes, and the total execution cycle is 5 cycles on the 2nd line + 3 cycles on the 3rd line (1 cycle) + 2 cycles on the 4th line + 3 cycles on the 6th line = 13 cycles (11 cycles) ). Note that the cycle number in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "RET NZ". Therefore, the total execution cycle is reduced by at least two cycles compared to the case of FIG. 142(b). With such a BYTEDEC module, it is possible to secure the capacity of the control area for performing game control processing while reducing the processing load.

Also, compared to the example in FIG. 142, the A register is not used here. Therefore, the value of the A register will not be updated unintentionally. Furthermore, in the example of FIG. 142, if the A register is already in use, it is necessary to stack and save the value of the A register, but here, since the A register is not used, there is no need for stack processing. In this way, resources can be used effectively.

Also, in order to understand by comparing FIG. 142(b) and FIG. 143(b), the command group that occupied four lines (second to fifth lines) in FIG. 142(b) is 143(b), it can be expressed in three lines (second to fourth lines), making it possible to reduce the number of commands themselves and reduce the design load.

Note that this BYTEDEC module is used not only in pachinko machines but also in slot machines, in which the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91 selectively transitions depending on the gaming state and performance state. Then, the REG_LOT module that executes the REG process (AT state = "6") and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. The BIG_LOT module executes the BIG process (AT state = "7"), the JCGMSET module executes the accessory action symbol display process shown in step S2900-3 in FIG. 96, and the JCGMSET module shown in step S3100 in FIG. 98. In the TMR_IPT module that executes timer interrupt processing and the CAL_MOD module that executes state-based module execution processing shown in step S3100-21 in FIG. In the IPT_PA module that selectively transitions to the terminal board output control process (every 5.96 msec) and the CAL_MOD module that executes the status-specific module execution process shown in step S3100-21 in FIG. The IPT_PC module selectively transitions once every four times (every 5.96 msec) according to the interrupt processing phase (0 to 3) and executes time monitoring processing, and the IPT_PC module shown in step S3100-21 in FIG. In the CAL_MOD module for executing state-specific module execution processing, the external signal output control is selectively shifted once every four times (every 5.96 msec) according to the timer interrupt processing phase (0 to 3). It is used as a RAM_DEC module (general-purpose module) that executes counter subtraction processing, which is called by the command "RST" from the IPT_PD module or the like that executes processing.

FIG. 144 is an explanatory diagram for explaining the RAM_DEC module. The RAM_DEC module shown in FIG. 144 is a general-purpose module for counter subtraction processing, that is, for decrementing a 1-byte variable in the main RAM 500c by 1, like the BYTEDEC module described above. Note that in the RAM_DEC module, as in the BYTEDEC module, not only is the value decremented, but as a result of the decrement, the zero flag and carry flag shown in FIG. 141 are set.

The index “RAM_DEC:” in the first line of FIG. 144(a) indicates the start address of the RAM_DEC module. The command "LD A, (HL)" on the second line reads the 1-byte value stored at the address indicated by the HL register into the A register. In such a command "LD A, (HL)", the second zero flag changes by its execution. Then, by the command "RT Z, A" on the third line, if the value of the A register is 0 (if the second zero flag is 1), the routine returns to the routine one stage higher. At this time, if the value of the A register is 0, the zero flag (first zero flag) becomes 1 and the carry flag becomes 0 by the command "RT Z, A". In this way, if the value stored at the address indicated by the HL register is 0, it is possible to set the zero flag to 1 and the carry flag to 0 without decrementing the value.

The command "CP A, 2" on the 4th line in FIG. 144(a) compares the value of the A register with 2. If the A register is 2 or more, the carry flag is not set and becomes 0, and if it is 1, the carry flag is set to 0. , the carry flag is set to 1. Note that the command "CP A, 2" is a command that sets a carry flag when the A register is less than 2, but at the execution stage of the command "CP A, 2", the value of the A register is 1 or 2 or more. (Since it is not 0), by setting the carry flag when it is less than 2, the carry flag will be set when it is 1. In this way, if the value of the A register is 1, the carry flag can be set to 1. The command "DEC A" on the fifth line decrements the 1-byte value stored at the address indicated by the A register by 1. The command "LD (HL), A" on the sixth line stores the value of the A register at the address indicated by the HL register. Here, if the value stored at the address indicated by the HL register is 2 or more, the decremented value is 1 or more, so the zero flag is not set and becomes 0, and if it is 1, the decremented value becomes 0, so The zero flag is set and becomes 1. Note that the carry flag does not change depending on the command "DEC A". In this way, if the value stored at the address indicated by the HL register is 2 or more, it can be set as zero flag = 0 and carry flag = 0, and if it is 1, it can be set as zero flag = 1 and carry flag = 1. Then, the command "RET" on the seventh line returns to the routine one stage higher. In this way, it is possible to decrement the value stored at the address indicated by the HL register by 1, and to set the zero flag and carry flag.

Here, by replacing the command with "DECM", the command group in FIG. 144(a) can be changed as shown in FIG. 144(b). The index “RAM_DEC:” in the first line of FIG. 144(b) indicates the start address of the RAM_DEC module. By the command "DECM (HL)" on the second line, if the value stored at the address indicated by the HL register is 1 or more, it is decremented by 1, and if it is 0, it is maintained at 0.

By the command "RET NZ" on the third line in FIG. 144(b), if the zero flag is not 1 (if the value after decrement is not zero), the routine returns to the routine one step above. Here, since decrement has already been performed by the command "DECM (HL)", the fact that the zero flag is not 1 indicates that the value before decrement is 2 or more. In that case, the zero flag is not set and becomes 0, and the carry flag is also not set and becomes 0, so it is possible to return to the routine one step higher. Subsequently, the carry flag is inverted (1→0, 0→1) by the command "CCF" on the fourth line. Note that the zero flag does not change depending on the command "CCF". In this way, if the value stored at the address indicated by the HL register before decrementing is 1, it can be set as zero flag = 0 and carry flag = 1, and if it is 0, it can be set as zero flag = 1 and carry flag = 0. . Then, the command "RET" on the fifth line returns to the routine one stage higher. In this way, it is possible to decrement the value stored at the address indicated by the HL register by 1, and to set the zero flag and carry flag.

Here, the total command size of the RAM_DEC module commands shown in FIG. 144(a) is 1 byte of the command "LD A, (HL)" on the 2nd line + 1 byte of the command "RT Z, A" on the 3rd line + 4 Command “CP A, 2” on the 5th line 2 bytes + Command “DEC A” on the 5th line 1 byte + Command “LD (HL), A” on the 6th line 1 byte + Command “RET” on the 7th line 1 byte = 7 bytes, and the total execution cycle is 2 cycles on the 2nd line + 4 cycles on the 3rd line (or 2 cycles) + 2 cycles on the 4th line + 1 cycle on the 5th line + 2 cycles on the 6th line + 3 cycles on the 7th line = 14 cycles (or 12 cycles) ). Note that the cycle number in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "RT Z, A". On the other hand, the total command size of the RAM_DEC module commands shown in FIG. 144(b) is: 2 bytes of the command "DECM (HL)" on the 2nd line + 1 byte of the command "RET NZ" on the 3rd line + 1 byte of the command "RET NZ" on the 4th line CCF" 2 bytes + 5th line command "RET" 1 byte = 6 bytes, and the total execution cycle is 2nd line 5 cycles + 3rd line 3 cycles (1 cycle) + 4th line 2 cycles + 6th line 3 cycles = 13 cycle (11 cycles). Note that the cycle number in parentheses indicates the execution cycle when the routine does not move to the next higher routine by the command "RET NZ". Therefore, by replacing the command group in FIG. 144(a) with the command group in FIG. 144(b), the total command size is reduced by 1 byte, and the total execution cycle is reduced by at least 1 cycle. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

The WORDDEC module is a general-purpose module that performs word counter subtraction processing, that is, decrements a 2-byte variable in the main RAM 300c by one. Note that the WORDDEC module not only decrements, but also sets a zero flag and a carry flag as a result of the decrement.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls the WORDDEC module as a subroutine in any process, and executes the WORDDEC module. The WORDDEC module decrements the 2-byte data held in the main RAM 300c.

FIG. 145 is a flowchart showing specific processing of the WORDDEC module. Here, as an optional process, a part of the NHI_CHK module that executes winning frequency abnormality error determination process, which is a subroutine of the state management process (error management process) shown in step S400-21 in FIG. 26, will be described. The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the description of the WORDDEC module, the predetermined register is the HL register.

The main CPU 300a executes arbitrary processing as shown in FIG. 145(a). The main CPU 300a first sets the address of the variable to be decremented in the HL register (S1). Then, the WORDDEC module is called as a subroutine (S2).

As shown in FIG. 145(b), the main CPU 300a decrements the 2-byte value stored at the address indicated by the HL register in the WORDDEC module by 1, and sets a zero flag and a carry flag (S3). Then, the WORDDEC module is terminated and the process returns to the subroutine one step above (S4). Note that the decrement mode and flag setting are explained in FIG. 141 similarly to the BYTEDEC module.

When the zero flag and carry flag are set by the WORDDEC module, the main CPU 300a performs various processes using the value of the HL register. For example, here, it is determined that the decrement result is not 0 (S5), and if it is not 0 (YES in S5), the subroutine returns (S6), and if it is 0 (NO in S5), Perform the next process without moving.

FIG. 146 is an explanatory diagram for explaining an example of a command for implementing the WORDDEC module. Of these, FIG. 146(a) shows a command group for arbitrary processing, and FIG. 146(b) shows a command group for the WORDDEC module. The flowchart shown in FIG. 145 is realized, for example, by the program shown in FIG. 146.

The command "POP HL" in the first line of FIG. 146(a) causes the address value of the winning frequency abnormality error monitoring timer that was saved in the stack area to be restored to the HL register. The command on the first line corresponds to step S1 in FIG. 145(a). Then, the command "CALLF WORDDEC" on the second line calls the WORDDEC module as a subroutine. The command on the second line corresponds to step S2 in FIG. 145(a).

The index “WORDDEC:” in the first line of FIG. 146(b) indicates the start address of the WORDDEC module. The command "JTW Z, (HL), WORDDEC_99" on the second line determines whether the 2-byte value stored at the address indicated by the HL register is 0, and if it is 0, moves to the index "WORDDEC_99:" . In such a command "JTW Z, (HL), WORDDEC_99", the zero flag changes by its execution. For example, if the value stored at the address indicated by the HL register is 0, the zero flag becomes 1 and the carry flag becomes 0. Furthermore, if the value stored at the address indicated by the HL register is 0, the process moves to the index "WORDDEC_99:" and returns to the subroutine one level higher by the command "RET" on the seventh line. In this way, if the value stored at the address indicated by the HL register is 0, it is possible to set the zero flag to 1 and the carry flag to 0 without decrementing the value.

The command "DECW (HL)" on the third line in FIG. 146(b) decrements the 2-byte value stored at the address indicated by the HL register by 1, and the value stored at the address indicated by the HL register is obtained. Update. Here, if the value stored at the address indicated by the HL register is 2 or more, the decremented value is 1 or more, so the zero flag is not set and becomes 0, and if it is 1, the decremented value becomes 0, so The zero flag (second zero flag) is set to 1. Then, by the command "RET NTZ" on the fourth line, if the zero flag is not 1, the process returns to the subroutine one step higher. The reason why "NTZ" is used here is that the second zero flag changes by the command "DECW (HL)" but the first zero flag does not change. Note that neither the zero flag nor the carry flag changes depending on the command "RET NTZ". At this time, the zero flag does not become 1 (returns to the subroutine one stage higher) when the value stored at the address indicated by the HL register before decrement is 2 or more. Therefore, if the value before decrement is 2 or more, the zero flag = 0 and the carry flag = 0, so there is no problem in returning to the subroutine one level higher.

Further, if the zero flag is 1, the value stored at the address indicated by the HL register before decrement is 1, and the zero flag=1 and the carry flag=0. That is, regarding the carry flag, the specifications shown in FIG. 141 are reversed. Therefore, the carry flag is forcibly set to 1 by the command "SCF" on the fifth line. In this way, if the value stored at the address indicated by the HL register before decrementing is 1, the zero flag=1 and the carry flag=1. Note that the zero flag does not change depending on the command "SCF". The commands on the second to sixth lines correspond to step S3 in FIG. 145(b). Then, the command "RET" on the seventh line returns to the subroutine one level above. The command on the seventh line corresponds to step S4 in FIG. 145(b). In this way, it is possible to decrement the value stored at the address indicated by the HL register by 1, and to set the zero flag and carry flag.

Subsequently, if the zero flag (second zero flag) is not 1 (if it is 0) by the command "RET NTZ" on the third line of FIG. 146(a), the process returns to the subroutine one level higher. The command on the third line corresponds to steps S5 and 6 in FIG. 145(a). In this way, processing based on the results of the WORDDEC module becomes possible.

The WORDDEC module is called as a subroutine by multiple modules. For example, the TMR_NEW module executes the timer update process shown in step S400-15 in FIG. 26, the TZ_SPN module executes the special symbol fluctuation process shown in step S620 in FIG. It is called from the NHI_CHK module, etc., which executes winning frequency abnormality error determination processing, which is a subroutine of state management processing (error management processing).

In this way, the total command size of the WORDDEC module commands shown in Figure 146(b) is 3 bytes for the command "JTW Z, (HL), WORDDEC_99" on the second line + the command "DECW (HL)" on the third line. 2 bytes + 1 byte of the command “RET NTZ” on the 4th line + 2 bytes of the command “SCF” on the 5th line + 1 byte of the command “RET” on the 7th line = 9 bytes, and the total execution cycle is 6 cycles on the 2nd line (or 5 cycles) + 7 cycles on the 3rd row + 3 cycles (or 1 cycle) on the 4th row + 2 cycles on the 5th row + 3 cycles on the 7th row = 21 cycles (or 18 cycles). Note that the number of cycles in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "JTW Z, (HL), WORDDEC_99" or the command "RET NTZ". By providing such a WORDDEC module, the command size "CALLF WORDDEC" with a command size of 2 bytes can be used without performing the word counter subtraction process in each of the modules described above, so the command can be shortened and the game control processing This makes it possible to secure the capacity of the control area for performing this.

FIG. 147 is an explanatory diagram for explaining another example of commands for implementing the WORDDEC module. Here, the command group of the WORDDEC module in FIG. 146(b) is replaced with the command group of the WORDDEC module in FIG. 147(b), and the command group for any other process that calls the WORDDEC module in FIG. 146(a). is used as is in FIG. 147(a). Here, as shown in FIG. 147(a), a description of the processing that is substantially the same as that of FIG. 146(a) will be omitted, and only the different processing of FIG. 147(b) will be described.

The index “WORDDEC:” in the first line of FIG. 147(b) indicates the start address of the WORDDEC module. By the command "DECWM (HL)" on the second line, if the value stored at the address indicated by the HL register is 1 or more, it is decremented by 1, and if it is 0, it is maintained at 0.

Here, the command "DECWM (HL)" decrements the 2-byte value stored at the address indicated by the HL register, and if the carry flag is set (-1), the address indicated by the HL register is This command forcibly stores 0 in the 2-byte value stored in . Then, if the value stored at the address indicated by the HL register is 1 or more, it is decremented by 1, and if it is 0, it is maintained at 0. By executing this command "DECWM (HL)", if the value after decrement is zero (if the value before decrement is 1 or 0), zero flags (first zero flag and second zero flag) are set. If the value before decrement is zero, set a carry flag and set it to 1. The command size of such a command is "2" and the execution cycle is "7".

By the command "RET NZ" on the third line of FIG. 147(b), if the zero flag is not 1 (if the value after decrement is not zero), the process returns to the subroutine one step higher. Here, since decrement has already been performed by the command "DECWM (HL)", the fact that the zero flag is not 1 indicates that the value before decrement is 2 or more. In that case, the zero flag is not set and becomes 0, and the carry flag is also not set and becomes 0, so it is possible to return to the subroutine one step higher.

In addition, in the command "DECWM (HL)", if the value stored in the address indicated by the HL register before decrementing is 1, it becomes 0 after decrementing, the zero flag = 1, the carry flag = 0, and the value is 0. If there is, it is not decremented and remains at 0, and the zero flag is set to 1 and the carry flag is set to 1. That is, regarding the carry flag, the specifications shown in FIG. 141 are reversed. Therefore, the carry flag is inverted (1→0, 0→1) by the command "CCF" on the fourth line of FIG. 147(b). Note that the zero flag does not change depending on the command "CCF". In this way, if the value stored at the address indicated by the HL register before decrementing is 1, it can be set as zero flag = 1 and carry flag = 1, and if it is 0, it can be set as zero flag = 1 and carry flag = 0. . The commands on the second to fourth lines correspond to step S3 in FIG. 145(b). Then, the command "RET" on the fifth line returns to the subroutine one step higher. The command on the fifth line corresponds to step S4 in FIG. 145(b). In this way, it is possible to decrement the value stored at the address indicated by the HL register by 1, and to set the zero flag and carry flag.

Subsequently, if the zero flag (second zero flag) is not 1 (if it is 0) by the command "RET NTZ" on the third line of FIG. 147(a), the process returns to the subroutine one level higher. The command on the third line corresponds to steps S5 and 6 in FIG. 145(a). In this way, processing based on the results of the WORDDEC module becomes possible.

The total command size of the WORDDEC module command in Figure 147(b) is 2 bytes on the 2nd line + 1 byte on the 3rd line + 2 bytes on the 4th line + 1 byte on the 5th line = 6 bytes, and the total execution cycle is 7 bytes on the 2nd line. Cycle + 3 cycles on the 3rd row (1 cycle) + 2 cycles on the 4th row + 3 cycles on the 6th row = 15 cycles (13 cycles). Note that the cycle number in parentheses indicates the execution cycle when the routine does not move to the next higher routine by the command "RET NZ". Therefore, compared to the case of FIG. 146(b), the total command size is reduced by 3 bytes, and the total execution cycle is reduced by at least 6 cycles. With such a WORDDEC module, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

Also, in order to understand by comparing FIG. 146(b) and FIG. 147(b), the command group that occupied five lines (second to sixth lines) in FIG. 146(b) is 147(b), it can be expressed in three lines (second to fourth lines), making it possible to reduce the number of commands themselves and reduce the design load.

<Command “RCP”>
FIG. 148 is an explanatory diagram for explaining an example of the process of returning from a subroutine. The command “CP A,n” in FIG. 148(a) is a command that compares the value of the A register with a predetermined value n. If A=n, the zero flag is set and becomes 1, and if A<n. If so, the carry flag is set to 1. The command size of such command "CP A,n" is "2" and the execution cycle is "2".

The command "RET cc" in FIG. 148(a) is a command that refers to the zero flag or carry flag and returns from the subroutine to the routine one level higher if the target flag is 1. The command size of the command "RET cc" is "1" and the execution cycle is "3" (or "1"). Note that the cycle number in parentheses indicates the execution cycle when the command "RET cc" does not move to the next higher routine (does not return from the subroutine).

Here, as shown in FIG. 148(a), the command "CP A,n" on the first line compares the value of the A register with a predetermined value n, and the command "RET cc" on the second line compares the value of the A register with a predetermined value n. , it is determined whether to return from the subroutine depending on the comparison result. Here, these two commands can be combined (replaced) into one command "RCP cc, A, n" as shown in FIG. 148(b).

The command "RCP cc, A, n" in FIG. 148(b) is a command that compares the value of the A register with a predetermined value n, and returns from the subroutine to the routine one level higher depending on the comparison result. . The command size of the command "RCP cc, A, n" is "2" and the execution cycle is "5" (or "3"). Note that the cycle number in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "RCP cc, A, n".

Here, the total command size of the command group shown in Figure 148(a) is 2 bytes for the command "CP A, n" on the first line + 1 byte for "RET cc" on the second line = 3 bytes, and the total execution cycle 2 cycles in the first row + 3 cycles in the second row (1 cycle) = 5 cycles (3 cycles). On the other hand, the command size of the command "RCP cc, A, n" shown in FIG. 148(b) is 2 bytes, and the execution cycle is 5 cycles (3 cycles). Therefore, by replacing the command group in FIG. 148(a) with the command in FIG. 148(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing. A plurality of modules that can be replaced in this way will be described below.

FIG. 149 is an explanatory diagram for explaining the PY_CMDA module. The PY_CMDA module shown in FIG. 149 executes the main command analysis process shown in step S100-63 in FIG. 23, that is, the process of analyzing the main command and detecting an abnormality in the main command.

The index “PY_CMDA:” in the first line of FIG. 149(a) indicates the start address of the PY_CMDA module. The command "LDQ A, (LOW R_BCR_BUF)" on the second line sets the value of the Q register as the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_BCR_BUF" that stores the buffer value of the main command as the lower address. The value stored at that address (main command) is read into the A register.

Then, when the buffer is cleared and the payout start designation command confirmation process is executed, as a reception data confirmation process, the value of the A register is changed to ``@ A fixed value indicated by "BCR_PAY_CLR", in this case 20H, is subtracted. Then, the command "CP A, 00CH" on the fourth line compares the subtracted value of the A register with 0CH. Here, it is confirmed that the main command is included in the range of 20H to 2BH. That is, if the value of the A register is less than 20H, the command "SUB A, @BCR_PAY_CLR" causes the value of the A register to become a negative value, which becomes larger than 0CH when viewed as a 1-byte value. Therefore, if the subtracted value of the A register is less than 0CH, the carry flag is set to 1 by the command "CP A, 00CH". Then, by "RET NC" on the fifth line, if the carry flag is not 1, the process returns to the routine one stage higher. Note that if the carry flag is 1 (included in the range of 20H to 2BH), a payout error designation command set process and a payout radio wave error flag setting process are executed, and the process returns to the routine one level higher.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 149(a) can be changed as shown in FIG. 149(b). The index “PY_CMDA:” in the first line of FIG. 149(b) indicates the start address of the PY_CMDA module. The command "LDQ A, (LOW R_BCR_BUF)" on the first line sets the value of the Q register as the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_BCR_BUF" that stores the buffer value of the main command as the lower address. The value stored at that address (main command) is read into the A register.

Then, after clearing the buffer and executing the predetermined process for the payout start designation command, the command “SUB A, @BCR_PAY_CLR” on the third line in FIG. A fixed value, in this case 20H, is subtracted. The command "RCP NC, A, 00CH" on the fourth line compares the subtracted value of the A register with 0CH, and if the carry flag is not 1, the process returns to the routine one step above. Here, it is confirmed that the main command is within the range of 20H to 2BH, and if it is not within that range, no further processing is performed and the routine returns to the next step higher. Note that if the carry flag is 1, a payout error designation command set process and a payout radio wave error flag setting process are executed, and the process returns to the routine one step above.

Here, the total command size of the command group shown in FIG. 149(a) is 2 bytes of the command "LDQ A, (LOW R_BCR_BUF)" on the 2nd line + 2 bytes of the command "SUB A, @BCR_PAY_CLR" on the 3rd line + 4 2 bytes of the command “CP A,00CH” on the 5th line + 1 byte of “RET NC” on the 5th line = 7 bytes, and the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 2 cycles on the 4th line + 2 cycles on the 5th line 3 cycles (1 cycle) = 10 cycles (8 cycles). On the other hand, the total command size of the command group shown in FIG. 149(b) is 2 bytes of the command "LDQ A, (LOW R_BCR_BUF)" on the second line + 2 bytes of the command "SUB A, @BCR_PAY_CLR" on the third line + 4 lines. The second command "RCP NC, A, 00CH" 2 bytes = 6 bytes, and the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 5 cycles (3 cycles) on the 4th line = 10 cycles (8 cycles). Become. Therefore, by replacing the command group in FIG. 149(a) with the command group in FIG. 149(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 150 is an explanatory diagram for explaining the GAT_PAS module. The GAT_PAS module shown in FIG. 150 performs the gate switch passing process (gate passing process) shown in step S510 in FIG. , executes processing related to normal symbols.

As the memory count check process, the index "GAT_PAS:" in the first line of FIG. 150(a) indicates the start address of the GAT_PAS module. The command "LDQ DE, LOW R_FZ_MEM" on the second line sets the value of the Q register as the upper 1 byte of the address, sets the value of the lower 1 byte of the address "R_FZ_MEM" as the lower 1 byte of the address, and stores the data at that address. Read the 2-byte value (address of the normal symbol pending ball counter) to the DE register. The command "LD A, (DE)" on the third line reads the value (counter value of the normal symbol reserved ball number counter) stored in the address (namely R_FZ_MEM) indicated by the DE register into the A register.

Then, the value of the A register is compared with the fixed value "@FZ_MEM_MAX", which is "4" here, by the command "CP A, @FZ_MEM_MAX" on the fourth line of FIG. 150(a). That is, if the value of the A register is less than 4, the carry flag is set to 1. Then, by "RET NC" on the fifth line, if the carry flag is not 1, the routine returns to the routine one stage higher. That is, if the counter value of the normal symbol reserved ball number counter is 4 or more, the normal symbol reserved ball number counter will not be counted any more, so the GAT_PAS module is ended. If the carry flag is 1, the process executes the random number acquisition process, the memory number addition process, the winning determination random number acquisition process, the transfer destination address calculation process, and the storage area storage process, and then returns to the routine one step above. .

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 150(a) can be changed as shown in FIG. 150(b). The index “GAT_PAS:” in the first line of FIG. 150(b) indicates the start address of the GAT_PAS module. The command "LDQ DE, LOW R_FZ_MEM" on the first line sets the value of the Q register as the upper 1 byte of the address, sets the value of the lower 1 byte of the address "R_FZ_MEM" as the lower 1 byte of the address, and stores the data at that address. Read the 2-byte value (address of the normal symbol pending ball counter) to the DE register. The command "LD A, (DE)" on the third line reads the value (counter value of the normal symbol reserved ball number counter) stored in the address (namely R_FZ_MEM) indicated by the DE register into the A register.

Then, the command "RCP NC, A, @FZ_MEM_MAX" on the 4th line of FIG. Return to the above routine. That is, if the counter value of the normal symbol reserved ball number counter is 4 or more, the normal symbol reserved ball number counter will not be counted any more, so the GAT_PAS module is ended. Note that if the carry flag is 1, the process executes the memory number addition process, the winning determination random number acquisition process, the transfer destination address calculation process, and the storage area storage process, and returns to the routine one step above.

Here, the total command size of the command group shown in FIG. 150(a) is 2 bytes of the command "LDQ DE, LOW R_FZ_MEM" on the 2nd line + 1 byte of the command "LD A, (DE)" on the 3rd line + 4 lines. The second command “CP A, @FZ_MEM_MAX” 2 bytes + the 5th line “RET NC” 1 byte = 6 bytes, and the total execution cycle is 2 cycles on the 2nd line + 2 cycles on the 3rd line + 2 cycles on the 4th line + 5th line 3 cycles (1 cycle) = 9 cycles (7 cycles). On the other hand, the total command size of the command group shown in FIG. 150(b) is: 2 bytes of the command "LDQ DE, LOW R_FZ_MEM" on the 2nd line + 1 byte of the command "LD A, (DE)" on the 3rd line + 1 byte of the command "LDQ DE, LOW R_FZ_MEM" on the 4th line The command "RCP NC, A, @FZ_MEM_MAX" 2 bytes = 5 bytes, and the total execution cycle is 2 cycles on the 2nd line + 2 cycles on the 3rd line + 5 cycles (3 cycles) on the 4th line = 9 cycles (7 cycles). Become. Therefore, by replacing the command group in FIG. 150(a) with the command group in FIG. 150(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 151 is an explanatory diagram for explaining the TDN_PAS module. The TDN_PAS module shown in FIG. 151 executes the count switch passing process (big winning opening passing process) shown in step S540 of FIG. 34, that is, the process of managing the winnings of the big winning opening based on the count switch judgment value. .

The index "TDN_PAS:" in the first line of FIG. 151(a) indicates the start address of the TDN_PAS module. Then, when the count switch judgment value confirmation process, the special electric accessory continuous operation number determination process, the big winning opening prize designation command set process, and the big winning opening excessive winnings monitoring process are executed, two lines are displayed as the special electric accessory operation check process. The second command "LDQ A, (LOW R_TDN_PHS)" makes the value of the Q register the upper 1 byte of the address, the value of the lower 1 byte of the address "R_TDN_PHS" the lower 1 byte of the address, and the data stored at that address. Read the value (special electric accessory game management phase) to the A register.

The command "JCP Z, A, @TD_OPN_BHT, TDN_PAS_10" on the third line of FIG. 151(a) compares the value of the A register with the fixed value "@TD_OPN_BHT", here 2, and if the results are equal, Move to address “TDN_PAS_10”. In this way, if the value of the A register is the jackpot jackpot opening control state specified value (the special electric accessory game management phase is 02H), the subsequent processing is omitted and the process moves to the index "TDN_PAS_10:" on the 6th line. be able to. The command "CP A, @TD_OPN_SHT" on the fourth line compares the value of the A register with the fixed value "@TD_OPN_SHT", here 6, which indicates the small hit large prize opening control state specification value, and if they are equal. (Special electric accessory game management phase is 06H), the zero flag is set and becomes 1. Then, by "RET NZ" on the fifth line, if the zero flag is not 1, the process returns to the routine one level higher. That is, if the value of the A register is not the jackpot large winning opening control state specification value or the small winning large winning opening opening control state specification value, the TDN_PAS module is terminated. If the zero flag is 1, the special electric accessory winning ball number counting process, the special electric fraudulent prize winning detection condition confirmation process, and the special electric fraudulent winning error processing are executed, and the process returns to the routine one step higher.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 151(a) can be changed as shown in FIG. 151(b). The index “TDN_PAS:” in the first line of FIG. 151(b) indicates the start address of the TDN_PAS module. Then, when the count switch judgment value confirmation process, the special electric accessory continuous operation number judgment process, the big winning opening winning designation command set process, and the big winning opening excessive winnings monitoring process are executed, the second line command "LDQ A, (LOW R_TDN_PHS)", the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "R_TDN_PHS" is set as the lower 1 byte of the address, and the value stored at that address (special electric accessory game management phase ) is read into the A register.

The command "JCP Z, A, @TD_OPN_BHT, TDN_PAS_10" on the third line of FIG. 151(b) compares the value of the A register with the fixed value "@TD_OPN_BHT", here 2, and if the results are equal, Move to address “TDN_PAS_10”. In this way, if the value of the A register is the jackpot jackpot opening control state specification value, it is possible to skip the subsequent processing and move to the index "TDN_PAS_10:" on the fifth line. The command "RCP NZ, A, @TD_OPN_SHT" on the fourth line compares the value of the A register with the fixed value "@TD_OPN_SHT", here 6, which indicates the small win large prize opening control state specified value, If they are equal, return to the routine one level higher. That is, if the value of the A register is not the jackpot big winning opening control state specification value or the small winning big winning opening control state specification value, the TDN_PAS module is ended. Incidentally, if the zero flag is 0, the special electric accessory winning ball number counting process, the special electric fraudulent prize winning detection condition confirmation process, and the special electric fraudulent prize winning error processing are executed, and the process returns to the next step higher routine.

Here, the total command size of the command group shown in FIG. 151(a) is 2 bytes of the command "LDQ A, (LOW R_TDN_PHS)" on the second line + the command "JCP Z, A, @TD_OPN_BHT, TDN_PAS_10" on the third line. ” 3 bytes + 4th line command “CP A, @TD_OPN_SHT” 2 bytes + 5th line “RET NZ” 1 byte = 8 bytes, and the total execution cycle is 3 cycles on the 2nd line + 4 cycles on the 3rd line (or 3 cycle) + 2 cycles on the 4th line + 3 cycles on the 5th line (1 cycle) = 12 cycles (9 cycles). On the other hand, the total command size of the command group shown in FIG. 151(b) is 2 bytes of the command "LDQ A, (LOW R_TDN_PHS)" on the second line + the command "JCP Z, A, @TD_OPN_BHT, TDN_PAS_10" on the third line. 3 bytes + 2 bytes of command "RCP NZ, A, @TD_OPN_SHT" on the 4th line = 7 bytes, and the total execution cycle is 3 cycles on the 2nd line + 4 cycles (or 3 cycles) on the 3rd line + 5 cycles (or 3 cycles) on the 4th line. cycle) = 12 cycles (9 cycles). Therefore, by replacing the command group in FIG. 151(a) with the command group in FIG. 151(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 152 is an explanatory diagram for explaining the FD_OPN module. The FD_OPN module shown in FIG. 152 performs the normal electric accessory prize opening control process shown in step 850 in FIG. Execute.

The index “FD_OPN:” in the first line of FIG. 152(a) indicates the start address of the FD_OPN module. Then, when the normal electric accessory prize opening opening/closing operation switching process is executed, the value of the Q register is set as the upper 1 byte of the address by the command "LDQ A, (LOW R_FDN_CNT)" on the second line as the specified number of winnings confirmation process. , the value of the lower 1 byte of the address "R_FDN_CNT" is set as the lower 1 byte of the address, and the value stored at that address (the counter value of the normal electric accessory winning ball number counter) is read into the A register.

The command “CP A, @FDN_CNT” on the third line of FIG. 152(a) sets the value of the A register and the fixed value “@FDN_CNT”, which indicates the maximum number of winning balls for ordinary electric accessories, here. Now, compare it with 8, and if it is less than 8, the carry flag is set and becomes 1. Then, if the carry flag is 1 by "RET C" on the fourth line, the routine returns to the routine one stage higher. That is, if the value of the A register is less than the number of winning balls in the winning hole related to the normal electric accessory, the FD_OPN module is ended. Note that if the carry flag is 0, a normal electric accessory operation end setting process is executed and the routine returns to the next step higher.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 152(a) can be changed as shown in FIG. 152(b). The index “FD_OPN:” in the first line of FIG. 152(b) indicates the start address of the FD_OPN module. Then, when the normal electric accessory prize opening opening/closing operation switching process is executed, the value of the Q register is set as the upper 1 byte of the address by the command "LDQ A, (LOW R_FDN_CNT)" on the second line as the specified number of winnings confirmation process. , the value of the lower 1 byte of the address "R_FDN_CNT" is set as the lower 1 byte of the address, and the value stored at that address (the counter value of the normal electric accessory winning ball number counter) is read into the A register.

The command “RCP C, A, @FDN_CNT” on the third line of FIG. 152(b) sets the value of the A register and the fixed value “@FDN_CNT” which indicates the maximum number of winning balls for ordinary electric accessories. , here, is compared with 8, and if it is less than 8, the routine returns to the next step higher. That is, if the value of the A register is less than the number of winning balls in the winning hole related to the normal electric accessory, the FD_OPN module is ended. Note that if the carry flag is 0, a normal electric accessory operation end setting process is executed and the routine returns to the next step higher.

Here, the total command size of the command group shown in FIG. 152(a) is 2 bytes of the command "LDQ A, (LOW R_FDN_CNT)" on the second line + 2 bytes of the command "CP A, @FDN_CNT" on the third line + 4 1 byte of "RET C" in the row = 5 bytes, and the total execution cycle is 3 cycles in the 2nd row + 2 cycles in the 3rd row + 3 cycles (1 cycle) in the 4th row = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 152(b) is 2 bytes for the command "LDQ A, (LOW R_FDN_CNT)" on the second line + 2 bytes for the command "RCP C, A, @FDN_CNT" on the third line. = 4 bytes, and the total execution cycle is 3 cycles on the second line + 5 cycles on the third line (3 cycles) = 8 cycles (6 cycles). Therefore, by replacing the command group in FIG. 152(a) with the command group in FIG. 152(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 153 is an explanatory diagram for explaining the TZ_STA module. The TZ_STA module shown in FIG. 153 executes the special symbol change waiting process shown in step S610 of FIG. 37, that is, the special symbol change preparation process based on the number of special symbol reserved balls.

The index "TZ_STA:" in the first line of FIG. 153(a) indicates the start address of the TZ_STA module. Then, when the special symbol reserved ball number confirmation process is executed, the DATSEL module, which is a general-purpose module, is called by the command "RST DATSEL" on the second line as a non-processing special symbol state confirmation process, and the selection result of the control data is Stored in A register.

The command "CP A, @TZ_BHT" in the third line of FIG. If they are equal, a zero flag is set and becomes 1. Then, by "RET Z" on the fourth line, if the zero flag is 1, the routine returns to the routine one stage higher. That is, if the jackpot is confirmed, the TZ_STA module is ended. The command "CP A, @TZ_SHT" on the 5th line compares the value of the A register with the fixed value "@TZ_SHT" indicating special symbol small hit information, here 02H, and if it is equal to 02H, the zero flag is set. Stand up and become 1. Then, if the zero flag is 1 by "RET Z" on the 6th line, the process returns to the routine one stage higher. That is, if the small win is confirmed, the TZ_STA module is ended. In addition, if the zero flag is not 1, the special symbol variation start time setting process, the number of times command set process, and the special symbol variation preparation process are executed, and the process returns to the routine one stage higher.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 153(a) can be changed as shown in FIG. 153(b). The index “TZ_STA:” in the first line of FIG. 153(b) indicates the start address of the TZ_STA module. Then, when the special symbol reserved ball number confirmation process is executed, the DATSEL module is called by the command "RST DATSEL" on the second line as a non-processing special symbol status confirmation process, and the control data selection result is stored in the A register. be done.

The command "RCP Z, A, @TZ_BHT" on the third line of FIG. 153(b) compares the value of the A register with the fixed value "@TZ_BHT" indicating special symbol jackpot information, here 01H, If it is equal to 01H, the routine returns to the next step higher. That is, if the jackpot is confirmed, the TZ_STA module is ended. The command "RCP Z, A, @TZ_SHT" on the fourth line compares the value of the A register with the fixed value "@TZ_SHT" indicating special symbol small hit information, here 02H, and if it is equal to 02H, Return to the routine one step above. That is, if the small win is confirmed, the TZ_STA module is ended. In addition, if the zero flag is not 1, the special symbol variation start time setting process, the number of times command set process, and the special symbol variation preparation process are executed, and the process returns to the routine one stage higher.

Here, the total command size of the command group shown in FIG. 153(a) is 1 byte of the command "RST DATSEL" on the 2nd line + 2 bytes of the command "CP A, @TZ_BHT" on the 3rd line + 2 bytes of the command "RET" on the 4th line. Z” 1 byte + 5th line command “CP A, @TZ_SHT” 2 bytes + 6th line “RET Z” 1 byte = 7 bytes, and the total execution cycle is 2nd line 4 cycles + 3rd line 2 cycles + 4 lines 3rd cycle (1 cycle) on the 5th row + 3 cycles on the 6th row (1 cycle) = 14 cycles (10 cycles). On the other hand, the total command size of the command group shown in FIG. 153(b) is 1 byte of the command "RST DATSEL" on the 2nd line + 2 bytes of the command "RCP Z, A, @TZ_BHT" on the 3rd line + 2 bytes of the command on the 4th line. "RCP Z, A, @TZ_SHT" 2 bytes = 5 bytes, and the total execution cycle is 2nd line 4 cycles + 3rd line 5 cycles (3 cycles) + 4th line 5 cycles (3 cycles) = 14 cycles (10 cycles) ). Therefore, by replacing the command group in FIG. 153(a) with the command group in FIG. 153(b), the total command size is reduced by 2 bytes. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 154 is an explanatory diagram for explaining the TZ_RGET module. The TZ_RGET module shown in FIG. 154 performs the special symbol random number acquisition process shown in step S535 in FIG. Executes processing to store numerical values.

The index "TZ_RGET:" in the first line of FIG. 154(a) indicates the start address of the TZ_RGET module. The jackpot determination random number acquisition process is executed, and as the special symbol pending ball number update process, the value stored in the address indicated by the DE register (target special symbol pending ball Read the counter value of the number counter to the A register. It is assumed that when the TZ_RGET module is called, an address indicating the counter value of the target special symbol reserved ball number counter is stored in advance in the DE register.

Then, by the command "CP A, @TZ_MEM_MAX" on the third line of FIG. 154(a), the value of the A register and the fixed value "@TZ_MEM_MAX" indicating the upper limit of the number of special symbols reserved balls, here "4" Compare with. That is, if the value of the A register is less than 4, the carry flag is set to 1. Then, by "RET NC" on the fourth line, if the carry flag is not 1, the process returns to the routine one stage higher. That is, if the counter value of the target special symbol reserved ball number counter is 4 or more, the target special symbol reserved ball number counter will not be counted any more, so the TZ_RGET module is ended. In addition, if the carry flag is 1, fluctuation pattern random number acquisition processing, reach group determination random number acquisition processing, reach mode determination random number acquisition processing, transfer destination address calculation processing, storage area storage processing, performance determination processing at the time of acquisition, and special Execute the figure hold designation command set process and return to the routine one step above.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 154(a) can be changed as shown in FIG. 154(b). The index “TZ_RGET:” in the first line of FIG. 154(b) indicates the start address of the TZ_RGET module. The jackpot determination random number acquisition process is executed, and as the special symbol pending ball number update process, the value (target The counter value of the special symbol reserved balls counter) is read out to the A register.

Then, the command "RCP NC, A, @TZ_MEM_MAX" on the third line of FIG. 4'' and if the value of the A register is 4 or more, the process returns to the routine one stage higher. That is, if the counter value of the target special symbol reserved ball number counter is 4 or more, the target special symbol reserved ball number counter will not be counted any more, so the TZ_RGET module is ended. Note that if the value of the A register is less than 4, fluctuation pattern random number acquisition processing, reach group determination random number acquisition processing, reach mode determination random number acquisition processing, transfer destination address calculation processing, storage area storage processing, performance determination processing at the time of acquisition, Then, the special figure reservation designation command set process is executed and the routine returns to the next level higher.

Here, the total command size of the command group shown in FIG. 154(a) is 1 byte of the command "LD A, (DE)" on the 2nd line + 2 bytes of the command "CP A, @TZ_MEM_MAX" on the 3rd line + 4 lines. 1 byte of the second "RET NC" = 4 bytes, and the total execution cycle is 2 cycles on the 2nd line + 2 cycles on the 3rd line + 3 cycles on the 4th line (1 cycle) = 7 cycles (5 cycles). On the other hand, the total command size of the command group shown in FIG. 154(b) is 1 byte of the command "LD A, (DE)" on the second line + 2 bytes of the command "RCP NC, A, @TZ_MEM_MAX" on the third line = The total execution cycle is 3 bytes, and the total execution cycle is 2 cycles on the 2nd line + 5 cycles on the 3rd line (3 cycles) = 7 cycles (5 cycles). Therefore, by replacing the command group in FIG. 154(a) with the command group in FIG. 154(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 155 is an explanatory diagram for explaining the TRSVSEL module. The TRSVSEL module shown in FIG. 155 executes the preliminary area setting process shown in step S610-17 in FIG. 37, that is, confirms the special symbol hit and executes the preliminary setting process of the special symbol probability state and special symbol state.

The index “TRSVEL:” in the first line of FIG. 155(a) indicates the start address of the TRSVSEL module. Then, when the state offset check flag setting process is executed, the DATSEL module, which is a general-purpose module, is called by the command "RST DATSEL" on the second line as a special symbol hit confirmation process, and the control data selection result is stored in the A register. be done.

The command "CP A, @TZ_BHT" in the third line of FIG. If they are equal, a zero flag is set and becomes 1. Then, by "RET NZ" on the fourth line, if the zero flag is not 1, the process returns to the routine one stage higher. That is, if the jackpot is not confirmed, the TRSVSEL module is ended. In addition, if the zero flag is 1, special symbol probability state preliminary setting processing and special symbol state preliminary setting processing are executed, and the routine returns to the next step higher.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 155(a) can be changed as shown in FIG. 155(b). The index “TRSVEL:” in the first line of FIG. 155(b) indicates the start address of the TRSVSEL module. Then, when the state offset check flag setting process is executed, the DATSEL module is called by the command "RST DATSEL" on the second line as a special symbol hit confirmation process, and the control data selection result is stored in the A register.

The command "RCP NZ, A, @TZ_BHT" on the third line of FIG. 155(b) compares the value of the A register with the fixed value "@TZ_BHT" indicating special symbol jackpot information, here 01H, If it is not equal to 01H, the routine returns to the next step higher. That is, if the jackpot is not confirmed, the TRSVSEL module is ended. In addition, if it is equal to 01H, special symbol probability state preliminary setting processing and special symbol state preliminary setting processing are executed, and the process returns to the routine one stage higher.

Here, the total command size of the command group shown in FIG. 155(a) is 1 byte of the command "RST DATSEL" on the 2nd line + 2 bytes of the command "CP A, @TZ_BHT" on the 3rd line + 2 bytes of the command "RET" on the 4th line. NZ'' 1 byte = 4 bytes, and the total execution cycle is 4 cycles on the 2nd line + 2 cycles on the 3rd line + 3 cycles on the 4th line (1 cycle) = 9 cycles (7 cycles). On the other hand, the total command size of the command group shown in FIG. 155(b) is 1 byte of the command "RST DATSEL" on the second line + 2 bytes of the command "RCP NZ, A, @TZ_BHT" on the third line = 3 bytes. The total execution cycle is 4 cycles on the second line + 5 cycles on the third line (3 cycles) = 9 cycles (7 cycles). Therefore, by replacing the command group in FIG. 155(a) with the command group in FIG. 155(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 156 is an explanatory diagram for explaining the TDOVCHK module. The TDOVCHK module shown in FIG. 156 executes the big winning hole excessive amount after setting the big winning hole entry command (S540-5) in the count switch passing process (big winning hole passing process) shown in step S540 of FIG. Winning monitoring processing, that is, updating processing of the winning ball number counter of the big winning hole and the number of excessive winnings counter of the big winning hole is executed.

The index “TDOVCHK:” in the first line of FIG. 156(a) indicates the start address of the TDOVCHK module. Then, as a special electric accessory game management phase confirmation process, the command "LDQ A, (LOW R_TDN_PHS)" on the second line sets the value of the Q register to the upper 1 byte of the address, and the lower 1 byte of the address "R_TDN_PHS". The value is set to the lower 1 byte of the address, and the value stored at that address (special electric accessory game management phase) is read to the A register.

The command "JCP NC, A, @TD_PRE_SHT, TDOVCHK_10" in the third line of FIG. If there is, move to address "TDOVCHK_10". In this way, if the value of the A register is a specified value that is later than the specified value of the pre-opening state of the small hit large winning opening, it is possible to skip the subsequent processing and move to the index "TDOVCHK_10" on the 6th line. The command "CP A, @TD_OPN_BHT" on the fourth line compares the value of the A register with the fixed value "@TD_OPN_BHT", here 2, which indicates the jackpot jackpot opening control state specified value, and if they are equal, The zero flag is set and becomes 1. Then, by "RET Z" on the fifth line, if the zero flag is 1, the process returns to the routine one stage higher. That is, if the value of the A register is the jackpot jackpot opening control state designation value, the TDOVCHK module is ended. In addition, if the zero flag is not 1, the process of updating the winning ball number counter for the winning opening, the updating process for the number of winnings in the excessive winning opening, and the processing for the excessive winning opening error are executed, and the process returns to the next higher routine. return.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 156(a) can be changed as shown in FIG. 156(b). The index “TDOVCHK:” in the first line of FIG. 156(b) indicates the start address of the TDOVCHK module. Then, as a special electric accessory game management phase confirmation process, the command "LDQ A, (LOW R_TDN_PHS)" on the second line sets the value of the Q register to the upper 1 byte of the address, and the lower 1 byte of the address "R_TDN_PHS". The value is set to the lower 1 byte of the address, and the value stored at that address (special electric accessory game management phase) is read to the A register.

The command "JCP NC, A, @TD_PRE_SHT, TDOVCHK_10" on the third line of FIG. If there is, move to address "TDOVCHK_10". In this way, if the value of the A register is a specified value that is later than the specified value of the pre-opening state of the small hit large prize opening, it is possible to skip the subsequent processing and move to the index "TDOVCHK_10" on the fifth line. The command "RCP Z, A, @TD_OPN_BHT" on the fourth line compares the value of the A register with the fixed value "@TD_OPN_BHT", here 2, which indicates the jackpot opening control state specified value, and if they are equal. If so, return to the routine one step above. That is, if the value of the A register is the jackpot jackpot opening control state designation value, the TDOVCHK module is ended. In addition, if the zero flag is not 1, the process of updating the winning ball number counter for the winning opening, the updating process for the number of winnings in the excessive winning opening, and the processing for the excessive winning opening error are executed, and the process returns to the next higher routine. return.

Here, the total command size of the command group shown in FIG. 156(a) is 2 bytes of the command "LDQ A, (LOW R_TDN_PHS)" on the second line + the command "JCP NC, A, @TD_PRE_SHT, TDOVCHK_10" on the third line. ” 3 bytes + 4th line command “CP A, @TD_OPN_BHT” 2 bytes + 5th line “RET Z” 1 byte = 8 bytes, and the total execution cycle is 3 cycles on the 2nd line + 4 cycles on the 3rd line (or 3 cycle) + 2 cycles on the 4th line + 3 cycles on the 5th line (1 cycle) = 12 cycles (9 cycles). On the other hand, the total command size of the command group shown in FIG. 156(b) is the command "LDQ A, (LOW R_TDN_PHS)" on the second line, 2 bytes + the command "JCP NC, A, @TD_PRE_SHT, TDOVCHK_10" on the third line. 3 bytes + 2 bytes of the command "RCP Z, A, @TD_OPN_BHT" on the 4th line = 7 bytes, and the total execution cycle is 3 cycles on the 2nd line + 4 cycles (or 3 cycles) on the 3rd line + 5 cycles (3 cycles) on the 4th line. cycle) = 12 cycles (9 cycles). Therefore, by replacing the command group in FIG. 156(a) with the command group in FIG. 156(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 157 is an explanatory diagram for explaining the BER_CHK module. The BER_CHK module shown in FIG. 157 performs base abnormality error monitoring processing, which is a subroutine of the state management processing (error management processing) shown in step S400-21 in FIG. 26, that is, processing for monitoring the counter value of the base abnormality confirmation counter. Execute.

As the out-switch confirmation process, the index "BER_CHK:" in the first line of FIG. 157(a) indicates the start address of the BER_CHK module. The command "LDQ HL, LOW R_BAS_CNT" on the second line reads the value of the Q register to the H register, and reads the value of the lower 1 byte of the address "R_BAS_CNT" to the L register. The command "LD A, (HL)" on the third line reads the value (counter value of the base abnormality confirmation counter) stored at the address indicated by the HL register (ie, R_BAS_CNT) into the A register.

Then, the value of the A register is compared with the fixed value "@BAS_CHK_CNT" (here, 20) indicating the number of base abnormality detection pitches by the command "CP A, @BAS_CHK_CNT" on the fourth line of FIG. 157(a). That is, if the value of the A register is less than 20, the carry flag is set to 1. Then, if the carry flag is 1 by "RET C" in the fifth line, the routine returns to the routine one stage higher. That is, if the counter value of the base abnormality confirmation counter is less than 20, the BER_CHK module is terminated. Note that if the carry flag is not 1, the security setting process is executed and the routine returns to the next step higher.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 157(a) can be changed as shown in FIG. 157(b). The index “BER_CHK:” in the first line of FIG. 157(b) indicates the start address of the BER_CHK module. The command "LDQ HL, LOW R_BAS_CNT" on the second line reads the value of the Q register to the H register, and reads the value of the lower 1 byte of the address "R_BAS_CNT" (address for storing the base abnormality confirmation counter) to the L register. The command "LD A, (HL)" on the third line reads the value (counter value of the base abnormality confirmation counter) stored at the address indicated by the HL register (ie, R_BAS_CNT) into the A register.

Then, the command "RCP C, A, @BAS_CHK_CNT" on the fourth line of FIG. However, if the value of the A register is less than 20, the routine returns to the next step higher. Note that if the value of the A register is 20 or more, security setting processing is executed and the routine returns to the next step higher.

Here, the total command size of the command group shown in FIG. 157(a) is the command "LDQ HL, LOW R_BAS_CNT" on the second line, 2 bytes + the command "LD A, (HL)" on the third line, 1 byte + 4 lines. The second command “CP A, @BAS_CHK_CNT” 2 bytes + the 5th line “RET C” 1 byte = 6 bytes, and the total execution cycle is 2 cycles on the 2nd line + 2 cycles on the 3rd line + 2 cycles on the 4th line + 5 lines 3rd cycle (1 cycle)=9 cycles (7 cycles). On the other hand, the total command size of the command group shown in FIG. 157(b) is 2 bytes of the command "LDQ HL, LOW R_BAS_CNT" on the 2nd line + 1 byte of the command "LD A, (HL)" on the 3rd line + 1 byte of the command "LDQ HL, LOW R_BAS_CNT" on the 4th line. The command "RCP C, A, @BAS_CHK_CNT" 2 bytes = 5 bytes, and the total execution cycle is 2 cycles on the 2nd line + 2 cycles on the 3rd line + 5 cycles (3 cycles) on the 4th line = 9 cycles (7 cycles). Become. Therefore, by replacing the command group in FIG. 157(a) with the command group in FIG. 157(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 158 is an explanatory diagram for explaining the TEF_SEL module. The TEF_SEL module shown in FIG. 158 performs the big winning opening closing effective time selection process, which is a subroutine of the big winning opening closing valid time setting process shown in step S720-9 in FIG. Execute the process of selecting the valid time from the table.

The index “TEF_SEL:” in the first line of FIG. 158(a) indicates the start address of the TEF_SEL module. Then, as the big prize opening closing valid time data selection process, the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the second line sets the value of the Q register to the upper 1 byte of the address, and the lower 1 byte of the address "R_ZUG_CHK_FIX". The value is set to the lower 1 byte of the address, and the value (special symbol determination flag) stored at that address is read to the A register.

The command "CP A, @ZUG_SML1" on the third line of FIG. 158(a) compares the value of the A register with the fixed value "@ZUG_SML1" indicating small winning symbol 1 designation data, here 07H, If it is less than 07H, the carry flag is set to 1. Then, by "RET NC" on the fourth line, if the carry flag is not 1, the process returns to the routine one stage higher. That is, if the value of the A register is greater than or equal to the small winning symbol 1 designation data, the TEF_SEL module is terminated. Note that if the carry flag is 1, word data selection processing is executed and the process returns to the routine one stage higher.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 158(a) can be changed as shown in FIG. 158(b). The index “TEF_SEL:” in the first line of FIG. 158(b) indicates the start address of the TEF_SEL module. Then, as the big prize opening closing valid time data selection process, the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the second line sets the value of the Q register to the upper 1 byte of the address, and the lower 1 byte of the address "R_ZUG_CHK_FIX". The value is set to the lower 1 byte of the address, and the value (special symbol determination flag) stored at that address is read to the A register.

The command “RCP NC, A, @ZUG_SML1” on the third line of FIG. 158(b) compares the value of the A register with the fixed value “@ZUG_SML1” indicating small winning symbol 1 designation data, here 07H. However, if it is 07H or higher, the routine returns to the next step higher. That is, if the value of the A register is greater than or equal to the small winning symbol 1 designation data, the TEF_SEL module is terminated. Note that if the value of the A register is less than the small winning symbol 1 designated data, word data selection processing is executed and the routine returns to the next step higher.

Here, the total command size of the command group shown in FIG. 158(a) is: 2 bytes of the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the 2nd line + 2 bytes of the command "CP A, @ZUG_SML1" on the 3rd line + 4 1 byte of "RET NC" in the row = 5 bytes, and the total execution cycle is 3 cycles in the 2nd row + 2 cycles in the 3rd row + 3 cycles (1 cycle) in the 4th row = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 158(b) is 2 bytes for the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the second line + 2 bytes for the command "RCP NC, A, @ZUG_SML1" on the third line. = 4 bytes, and the total execution cycle is 3 cycles on the second line + 5 cycles on the third line (3 cycles) = 8 cycles (6 cycles). Therefore, by replacing the command group in FIG. 158(a) with the command group in FIG. 158(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

Note that the replacement shown in FIG. 148 is called as a subroutine from a plurality of modules not only in pachinko machines but also in slot machines. For example, the game state and The PRE_LOT module selectively transitions depending on the performance state and executes the preparation process (AT state = "5"), and the EXE_SET module executes the execution flag setting process shown in step S2400-11 in FIG. 91. and the REG_LOT module that selectively transitions depending on the performance state and executes the REG process (AT state = "6"), and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. A BIG_SLT module that executes a BIG stock number lottery process in a BIT_LOT module that selectively transitions depending on the state and performance state and executes a BIG medium process (AT state = "7"), as shown in step S2400-11 in FIG. It is called from the NAV_SET module, etc., which executes the instruction information setting process in the execution flag setting process.

FIG. 159 is an explanatory diagram for explaining the SET_RIG module. The SET_RIG module shown in FIG. 159 executes reverse push data setting processing, that is, processing for setting data necessary for stop control.

The index “SET_RIG:” in the first line of FIG. 159(a) indicates the start address of the SET_RIG module. The command "LDQ A, (LOW _HIT_NUM)" on the second line sets the value of the Q register as the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "_HIT_NUM" that stores the stop control number as the lower 1 byte of the address. and reads the value (stop control number) stored at that address into the A register.

Then, as a second stop operation bit data update process, the fixed value "10" is subtracted from the value of the A register by the command "SUB A,10" on the third line of FIG. 159(a). Then, the command "CP A, 57-10+1" on the fourth line compares the subtracted value of the A register with 48 (57-10+1). Here, it is confirmed that the stop control number is within the range of 10 to 57. That is, if the value of the A register is less than 10, the command "SUB A, 10" causes the value of the A register to become a negative value, which becomes larger than 48 when viewed as a 1-byte value. Therefore, if the subtracted value of the A register is less than 10, the carry flag is set to 1 by the command "CP A, 57-10+1". Then, by "RET NC" on the fifth line, if the carry flag is not 1, the routine returns to the routine one stage higher. Note that if the carry flag is 1 (if the stop control number is within the range of 10 to 57), the next process is executed.

Next, the command "LDQ A, (LOW _HIT_NUM)" on the 6th line of FIG. The value of the byte is set as the lower 1 byte of the address, and the value (stop control number) stored at that address is read into the A register. The command "CP A, 34" on the seventh line compares the value of the A register with the fixed value "34". Here, it is confirmed that the stop control number is less than 34. If the value of the A register is less than 34, a carry flag is set to 1 by the command "CP A, 34". Then, by "RET NC" on the 8th line, if the carry flag is not 1, the process returns to the routine one stage higher. Note that if the carry flag is 1 (if the stop control number is less than 34), the remaining processing is executed and the routine returns to the next step higher.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 159(a) can be changed as shown in FIG. 159(b). The index “SET_RIG:” in the first line of FIG. 159(b) indicates the start address of the SET_RIG module. The command "LDQ A, (LOW _HIT_NUM)" on the second line sets the value of the Q register as the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "_HIT_NUM" that stores the stop control number as the lower 1 byte of the address. and reads the value (stop control number) stored at that address into the A register.

Then, as a second stop operation bit data update process, the fixed value "10" is subtracted from the value of the A register by the command "SUB A,10" on the third line of FIG. 159(b). The command "RCP NC, A, 57-10+1" on the fourth line compares the subtracted value of the A register with 48 (57-10+1), and if the carry flag is not 1, it moves to the routine one level higher. return. Here, it is confirmed that the stop control number is within the range of 10 to 57, and if it is not within that range, the process returns to the routine one level higher without performing any further processing. Note that if the carry flag is 1 (if the stop control number is within the range of 10 to 57), the next process is executed.

Next, the command "LDQ A, (LOW _HIT_NUM)" on the 5th line of FIG. The value of the byte is set as the lower 1 byte of the address, and the value (stop control number) stored at that address is read into the A register. The command "RCP NC, A, 34" on the sixth line compares the value of the A register with the fixed value "34", and if the carry flag is not 1, the process returns to the routine one step above. Here, it is confirmed that the stop control number is less than 34, and if it is 34 or more, the subsequent processing is not performed and the routine returns to the next step higher. Note that if the carry flag is 1 (if the stop control number is less than 34), the remaining processing is executed and the process returns to the routine one stage higher.

Here, the total command size of the command group shown in Figure 159(a) is 2 bytes of the command "LDQ A, (LOW_HIT_NUM)" on the 2nd line + 2 bytes of the command "SUB A, 10" on the 3rd line + 4 lines. 2nd command “CP A,57-10+1” 2 bytes + 5th line “RET NC” 1 byte + 6th line command “LDQ A, (LOW _HIT_NUM)” 2 bytes + 7th line command “CP A, 34” 2 bytes + 1 byte of "RET NC" on the 8th line = 12 bytes, and the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 2 cycles on the 4th line + 3 cycles (1 cycle) on the 5th line + 3 cycles on the 6th line. Cycle + 2 cycles on the 7th line + 3 cycles on the 8th line (1 cycle) = 18 cycles (14 cycles). On the other hand, the total command size of the command group shown in FIG. 159(b) is 2 bytes of the command "LDQ A, (LOW _HIT_NUM)" on the 2nd line + 2 bytes of the command "SUB A, 10" on the 3rd line + 4 lines. 2nd command “RCP NC, A, 57-10+1” 2 bytes + 5th line command Command “LDQ A, (LOW _HIT_NUM)” 2 bytes + 6th line command “RCP NC, A, 34” 2 bytes = 10 bytes Therefore, the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 5 cycles (3 cycles) on the 4th line + 3 cycles on the 5th line + 5 cycles (3 cycles) on the 6th line = 18 cycles (14 cycles). Therefore, by replacing the command group in FIG. 159(a) with the command group in FIG. 159(b), the total command size is reduced by 2 bytes. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 160 is an explanatory diagram for explaining the PRE_LOT module. The PRE_LOT module shown in FIG. 160 selectively transitions depending on the gaming state and performance state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. A lottery process is executed when the state is a predetermined value (for example, 5).

The index “PRE_LOT:” in the first line of FIG. 160(a) indicates the start address of the PRE_LOT module. The command "LDQ A, (LOW_TRG_KND)" on the second line sets the value of the Q register as the upper 1 byte of the address, and the value of the lower 1 byte of the address "_TRG_KND" as the lower 1 byte of the address, and stores it at that address. The value (trigger role type) is read out to the A register.

The command "CP A, @LOT_OFS_1FK" on the third line of FIG. 160(a) sets the value of the A register and the fixed value "@LOT_OFS_1FK", which indicates "1 fake" as the trigger role type, here 3. If the value is less than 3, the carry flag is set to 1. Then, if the carry flag is 1 by "RET C" on the fourth line, the routine returns to the routine one stage higher. That is, if the value of the A register is less than a fixed value indicating "one fake", the PRE_LOT module is terminated. Note that if the carry flag is 0, the REG start time setting process, the BIG start time BIG stock lottery process, and the BIG start time setting process are executed, and the process returns to the routine one level higher.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 160(a) can be changed as shown in FIG. 160(b). The index “PRE_LOT:” in the first line of FIG. 160(b) indicates the start address of the PRE_LOT module. The command "LDQ A, (LOW_TRG_KND)" on the second line sets the value of the Q register as the upper 1 byte of the address, and the value of the lower 1 byte of the address "_TRG_KND" as the lower 1 byte of the address, and stores it at that address. The value (trigger role type) is read out to the A register.

The command "RCP C, A, @LOT_OFS_1FK" on the third line of FIG. If the value is less than 3, the routine returns to the next step higher. That is, if the value of the A register is less than a fixed value indicating "one fake", the PRE_LOT module is terminated.

Here, the total command size of the command group shown in FIG. 160(a) is 2 bytes of the command "LDQ A, (LOW_TRG_KND)" on the second line + 2 bytes of the command "CP A, @LOT_OFS_1FK" on the third line + 3 1 byte of "RET C" in the row = 5 bytes, and the total execution cycle is 3 cycles in the 2nd row + 2 cycles in the 3rd row + 3 cycles (1 cycle) in the 4th row = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 160(b) is 2 bytes for the command "LDQ A, (LOW_TRG_KND)" on the second line + 2 bytes for the command "RCP C, A, @LOT_OFS_1FK" on the third line. = 4 bytes, and the total execution cycle is 3 cycles on the second line + 5 cycles on the third line (3 cycles) = 8 cycles (6 cycles). Therefore, by replacing the command group in FIG. 160(a) with the command group in FIG. 160(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 161 is an explanatory diagram for explaining the REG_LOT module. The REG_LOT module shown in FIG. 161 selectively transitions depending on the gaming state and performance state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. A lottery process is executed when the state is a predetermined value (for example, 6).

The index “REG_LOT:” in the first line of FIG. 161(a) indicates the start address of the REG_LOT module. The command "LDQ A, (LOW_TRG_KND)" on the second line sets the value of the Q register as the upper 1 byte of the address, and the value of the lower 1 byte of the address "_TRG_KND" as the lower 1 byte of the address, and stores it at that address. The value (trigger role type) is read out to the A register.

The command "CP A, @LOT_OFS_PDJ" on the third line of FIG. 161(a) compares the value of the A register with the fixed value "@LOT_OFS_PDJ", here 5, which indicates "batting order bell" as the trigger role type. However, if it is 5, the zero flag is set and becomes 1. Then, by "RET NZ" on the fourth line, if the zero flag is not 1, the process returns to the routine one stage higher. That is, if the value of the A register is not a fixed value indicating "batting order bell", the REG_LOT module is terminated. Note that if the zero flag is 0, the REG remaining navigation count subtraction process and the REG end setting process are executed, and the process returns to the routine one step above.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 161(a) can be changed as shown in FIG. 161(b). The index “REG_LOT:” in the first line of FIG. 161(b) indicates the start address of the REG_LOT module. The command "LDQ A, (LOW_TRG_KND)" on the second line sets the value of the Q register as the upper 1 byte of the address, and the value of the lower 1 byte of the address "_TRG_KND" as the lower 1 byte of the address, and stores it at that address. The value (trigger role type) is read out to the A register.

The command "RCP NZ, A, @LOT_OFS_PDJ" on the third line of FIG. 161(b) sets the value of the A register and the fixed value "@LOT_OFS_PDJ" indicating "batting order bell" as the trigger role type, here 5. If the value is not 5, the routine returns to the next higher level. That is, if the value of the A register is not a fixed value indicating "batting order bell", the REG_LOT module is terminated.

Here, the total command size of the command group shown in FIG. 161(a) is 2 bytes of the command "LDQ A, (LOW_TRG_KND)" on the second line + 2 bytes of the command "CP A, @LOT_OFS_PDJ" on the third line + 4 1 byte of "RET NZ" in the row = 5 bytes, and the total execution cycle is 3 cycles in the 2nd row + 2 cycles in the 3rd row + 3 cycles (1 cycle) in the 4th row = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 161(b) is 2 bytes for the command "LDQ A, (LOW_TRG_KND)" on the second line + 2 bytes for the command "RCP NZ, A, @LOT_OFS_PDJ" on the third line. = 4 bytes, and the total execution cycle is 3 cycles on the second line + 5 cycles on the third line (3 cycles) = 8 cycles (6 cycles). Therefore, by replacing the command group in FIG. 161(a) with the command group in FIG. 161(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 162 is an explanatory diagram for explaining the BIG_SLT module. The BIG_SLT module shown in FIG. 162 executes the BIG stock number lottery process.

The index “BIG_SLT:” in the first line of FIG. 162(a) indicates the start address of the BIG_SLT module. The command "LDQ A, (LOW_TRG_KND)" on the second line sets the value of the Q register as the upper 1 byte of the address, and the value of the lower 1 byte of the address "_TRG_KND" as the lower 1 byte of the address, and stores it at that address. The value (trigger role type) is read out to the A register.

The command "CP A, @LOT_OFS_LCY" on the third line of FIG. 162(a) compares the value of the A register with the fixed value "@LOT_OFS_LCY", here 6, which indicates "weak cherry" as the trigger role type. However, if it is less than 6, the carry flag is set to 1. Then, if the carry flag is 1 by "RET C" on the fourth line, the routine returns to the routine one stage higher. That is, if the value of the A register is less than the fixed value indicating "weak cherry", the corresponding BIG_SLT module is terminated. Note that if the carry flag is 0, the BIG medium stock lottery process is executed and the routine returns to the next step higher.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 162(a) can be changed as shown in FIG. 162(b). The index “BIG_SLT:” in the first line of FIG. 162(b) indicates the start address of the BIG_SLT module. The command "LDQ A, (LOW_TRG_KND)" on the second line sets the value of the Q register as the upper 1 byte of the address, and the value of the lower 1 byte of the address "_TRG_KND" as the lower 1 byte of the address, and stores it at that address. The value (trigger role type) is read out to the A register.

The command "RCP C, A, @LOT_OFS_LCY" on the third line of FIG. 162(b) sets the value of the A register and the fixed value "@LOT_OFS_LCY" indicating "weak cherry" as the trigger role type, here 6. If the value is less than 6, the routine returns to the next step higher. That is, if the value of the A register is less than the fixed value indicating "weak cherry", the corresponding BIG_SLT module is terminated.

Here, the total command size of the command group shown in FIG. 162(a) is 2 bytes of the command "LDQ A, (LOW_TRG_KND)" on the second line + 2 bytes of the command "CP A, @LOT_OFS_LCY" on the third line + 4 1 byte of "RET C" in the row = 5 bytes, and the total execution cycle is 3 cycles in the 2nd row + 2 cycles in the 3rd row + 3 cycles (1 cycle) in the 4th row = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 162(b) is 2 bytes for the command "LDQ A, (LOW_TRG_KND)" on the second line + 2 bytes for the command "RCP C, A, @LOT_OFS_LCY" on the third line. = 4 bytes, and the total execution cycle is 3 cycles on the second line + 5 cycles on the third line (3 cycles) = 8 cycles (6 cycles). Therefore, by replacing the command group in FIG. 162(a) with the command group in FIG. 162(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 163 is an explanatory diagram for explaining the NAV_SET module. The NAV_SET module shown in FIG. 163 executes instruction information setting processing, that is, instruction information type setting processing.

The index “NAV_SET:” in the first line of FIG. 163(a) indicates the start address of the NAV_SET module. The command "LDQ A, (LOW _YRI_LMP)" on the second line sets the value of the Q register as the upper 1 byte of the address, sets the value of the lower 1 byte of the address "_YRI_LMP" as the lower 1 byte of the address, and stores it at that address. Read the value (valid lamp flag) to the A register.

The command "CP A, @AT_MOD_PRE" in the third line of FIG. 163(a) compares the value of the A register with the fixed value "@AT_MOD_PRE", here 5, which indicates that the AT state definition is "in preparation". However, if it is less than 5, the carry flag is set to 1. Then, if the carry flag is 1 by "RET C" on the fourth line, the routine returns to the routine one stage higher. That is, if the value of the A register is less than a fixed value indicating "in preparation", the NAV_SET module is terminated. Note that if the carry flag is 0, the remaining processing is executed and the process returns to the routine one stage higher.

Here, by performing the substitution shown in FIG. 148, the command group in FIG. 163(a) can be changed as shown in FIG. 163(b). The index “NAV_SET:” in the first line of FIG. 163(b) indicates the start address of the NAV_SET module. The command "LDQ A, (LOW _YRI_LMP)" on the second line sets the value of the Q register as the upper 1 byte of the address, sets the value of the lower 1 byte of the address "_YRI_LMP" as the lower 1 byte of the address, and stores it at that address. Read the value (valid lamp flag) to the A register.

The command "RCP C, A, @AT_MOD_PRE" on the third line of FIG. 163(b) changes the value of the A register and the fixed value "@AT_MOD_PRE" indicating that the AT status definition is "in preparation", here 5. If the value is less than 5, the routine returns to the next higher level. That is, if the value of the A register is less than a fixed value indicating "in preparation", the NAV_SET module is terminated.

Here, the total command size of the command group shown in FIG. 163(a) is 2 bytes of the command "LDQ A, (LOW_YRI_LMP)" on the second line + 2 bytes of the command "CP A, @AT_MOD_PRE" on the third line + 4 1 byte of "RET C" in the row = 5 bytes, and the total execution cycle is 3 cycles in the 2nd row + 2 cycles in the 3rd row + 3 cycles (1 cycle) in the 4th row = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 163(b) is: 2 bytes of the command "LDQ A, (LOW_YRI_LMP") on the 2nd line + 2 bytes of the command "RCP C, A, @AT_MOD_PRE" on the 3rd line = 4 bytes, and the total execution cycle is 3 cycles on the 2nd line + 5 cycles on the 3rd line (3 cycles) = 8 cycles (6 cycles). Therefore, the command group in Figure 163 (a) is changed to the command group in Figure 163 (b). By replacing the commands with a group of commands, the total command size is reduced by 1 byte.By such replacement, it is possible to further shorten the commands and secure the capacity of the control area for performing game control processing.

<XORQ>
FIG. 164 is a flowchart showing specific processing of the TOK_PRC module. The TOK_PRC module executes the special game management process in step S600 (see FIG. 36). The numerical values of step S in this figure will be used only in the explanation of this figure.

As shown in FIG. 164, the main CPU 300a loads the special game special symbol determination flag (S1), inverts the loaded special game special symbol determination flag (S2), and saves the inverted special game special symbol determination flag ( S3). Note that step S1 corresponds to step S600-5 in FIG. 36, step S2 corresponds to step S600-7 in FIG. 36, and step S3 corresponds to step S600-9 in FIG.

FIG. 165 is an explanatory diagram for explaining an example of a command for realizing the TOK_PRC module. The flowchart shown in FIG. 164 is realized, for example, by the program shown in FIG. 165.

The index “TOK_PRC:” in the first line of FIG. 165(a) indicates the start address of the TOK_PRC module. Then, as a special game management process, the command "LDQ A, (LOW R_STA_TZ)" on the second line of FIG. The value of is set as the lower 1 byte of the address, and the value (special game special symbol determination flag) stored at that address is read to the A register. The command on the second line corresponds to step S1 in FIG. 164. The command "XOR 001H" on the third line calculates the exclusive OR of the read value (special game special symbol determination flag) and the fixed value (here 001H). As a result, the special game special symbol determination flag is inverted. The command on the second line corresponds to step S2 in FIG. 164. Then, the command "LDQ (LOW R_STA_TZ), A" on the fourth line sets the value of the Q register as the upper 1 byte of the address, sets the value of the lower 1 byte of the address "R_STA_TZ" as the lower 1 byte of the address, and sets the value of the Q register as the lower 1 byte of the address. The value of the A register is stored in . The command on the fourth line corresponds to step S3 in FIG. 164.

Here, the command group in FIG. 165(a) can be changed as shown in FIG. 165(b). The index “TOK_PRC:” in the first line of FIG. 165(b) indicates the start address of the TOK_PRC module. Then, when the special game management process is executed, the command "XORQ (LOW R_STA_TZ), 001H" on the second line sets the value of the Q register to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_STA_TZ" to the address. The exclusive OR of the value stored at that address (special game special symbol determination flag) and a fixed value (here 001H) is calculated, and the calculation result is stored at the same address.

Here, the total command size of the command group shown in FIG. 165(a) is 2 bytes of the command "LDQ A, (LOW R_STA_TZ)" on the 2nd line + 2 bytes of the command "XOR 001H" on the 3rd line + 2 bytes of the command on the 4th line. "LDQ (LOW R_STA_TZ), A" 2 bytes = 6 bytes, and the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 3 cycles on the 4th line = 8 cycles. On the other hand, the total command size of the command group shown in FIG. 165(b) is "XORQ (LOW R_STA_TZ), 001H" 4 bytes = 4 bytes, and the total execution cycle is 7 cycles on the second line = 7 cycles. Therefore, by replacing the command group in FIG. 165(a) with the command group in FIG. 165(b), the total command size is reduced by 2 bytes, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

In addition, in order to understand by comparing FIG. 165(a) and FIG. 165(b), the command group that occupied three lines (second to fourth lines) in FIG. 165(a) is 165(b), it can be expressed in one line (second line), making it possible to reduce the number of commands themselves and reduce the design load.

Further, here, in the example of FIG. 165(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. In addition, in the example of FIG. 165(a), if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, the stack processing is also not necessary. unnecessary. In this way, resources can be used effectively.

<CPQ>
FIG. 166 is a flowchart showing specific processing of the TEF_SEL module. The TOK_PRC module is executed when setting the special electric accessory game timer as the special electric accessory game timer in the special winning opening opening control process (see FIG. 47) (see FIG. 47). The numerical values of step S in this figure will be used only in the explanation of this figure.

As shown in FIG. 166, the main CPU 300a sets the big winning opening closing effective time for the small winning game (S1), loads the special symbol determination flag (S2), and uses the loaded special symbol determination flag and the small winning symbol. It is compared with a predetermined value (here, 007H) indicating that there is a certain value (S3). The special symbol determination flag is set to 00H if it is a losing symbol, one of 01H to 06H if it is a jackpot symbol, and one of 07H to 09H if it is a small winning symbol.

Then, if the comparison result is a small winning symbol (YES in S4), the TEF_SEL module is terminated (S6), and if the comparison result is not a small winning symbol (NO in S4), that is, if it is a jackpot symbol, A big prize opening closing effective time table for the big prize game is set (S5), and the TEF_SEL module is ended (S6).

FIG. 167 is an explanatory diagram for explaining an example of a command for realizing the TEF_SEL module. The flowchart shown in FIG. 166 is realized, for example, by the program shown in FIG. 167.

The index “TEF_SEL:” in the first line of FIG. 167(a) indicates the start address of the TEF_SEL module. Then, the value of "@TMR_TDN_EF3" is stored in the HL register by the command "LD HL, @TMR_TDN_EF3" on the second line of FIG. 167(a). In addition, in "@TMR_TDN_EF3", the effective time for closing the big prize opening of the small winning game is set. The command on the first line corresponds to step S1 in FIG. 166.

The command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the third line of FIG. 167(a) sets the value of the Q register to the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_ZUG_CHK_FIX" to the lower 1 byte of the address. Then, the value (special symbol determination flag) stored at that address is read into the A register. The command on the third line corresponds to step S2 in FIG. 166.

The command “CP A, @ZUG_SML1” on the fourth line of FIG. 167(a) sets the value of the A register and the fixed value “@ZUG_SML1” indicating the small winning symbol 1 designation data (small winning symbol), here 07H. If the value of the A register is less than 07H, the carry flag is set to 1. The command on the fourth line corresponds to step S3 in FIG. 166.

Then, by the command "RET NC" on the 5th line of FIG. 167(a), if the carry flag is not 1, the routine returns to the routine one stage higher. That is, if the value of the A register is greater than or equal to the small winning symbol 1 designation data, the TEF_SEL module is terminated. The command on the fifth line corresponds to YES in step S4 and step S6 in FIG. 166.

On the other hand, if the carry flag is 1, the command "LDQ A, (LOW R_TDN_FLG)" on the 6th line of FIG. 167(a) sets the value of the Q register to the upper 1 byte of the address, and The value of 1 byte is the lower 1 byte of the address, the value stored in that address (special electric accessory designation flag) is read out to the A register, and the command "LD HL,D_EFF_TMR-" on the 7th line of FIG. 167(a) is executed. 2" sets the start address "D_EFF_TMR-2" of the 1-byte data group to be the transfer source in the HL register.

The WORDSEL module is called as a subroutine by the command "RST WORDSEL" on the 8th line of FIG. After the value is read into the A register, the command "RET" on the 9th line in FIG. 167(a) returns to the routine one level higher. In addition, in the subsequent one-step higher routine (in subsequent processing), the big prize opening closing effective time of the big winning game will be set in the timer. The 6th to 8th lines correspond to step S5 in FIG. 166.

Here, the command group in FIG. 167(a) can be changed as shown in FIG. 167(b). Here, descriptions of processes that are substantially the same as those in FIG. 167(a) will be omitted, and only processes that are different from those in FIG. 167(b) will be described.

The command "CPQ (LOW R_ZUG_CHK_FIX),@ZUG_SML1" on the third line of FIG. Compare the value stored at that address (special symbol judgment flag) with the fixed value "@ZUG_SML1", here 07H, indicating the small winning symbol 1 designation data (small winning symbol), and if it is less than 07H. If so, the carry flag is set to 1. The command on the third line corresponds to step S2 and step S3 in FIG. 166. The command size of such a command is "3" and the execution cycle is "4".

Here, the total command size of the command group shown in FIG. 167(a) is: 2nd line command "LD HL, @TMR_TDN_EF3" 3 bytes + 3rd line command "LDQ A, (LOW R_ZUG_CHK_FIX)" 2 bytes + 4 lines 2nd command “CP A, @ZUG_SML1” 2 bytes + 5th line “RET NC” 1 byte + 6th line command “LDQ A, (LOW R_TDN_FLG)” 2 bytes + 7th line command “LD HL,D_EFF_TMR-2 ” 3 bytes + 8th line command “RST WORDSEL” 1 byte + 9th line “RET” 1 byte = 15 bytes, and the execution cycle is 2nd line 3 cycles + 3rd line 2 cycles + 4th line 2 cycles + 5th line 3 Cycle (1 cycle) + 2 cycles on the 6th line + 3 cycles on the 7th line + 4 cycles on the 8th line + 3 cycles on the 9th line = 22 cycles (20 cycles). Note that the cycle number in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "RET NC".

On the other hand, the total command size of the command group shown in FIG. 167(b) is: 2nd line command "LD HL, @TMR_TDN_EF3" 3 bytes + 3rd line command "CPQ (LOW R_ZUG_CHK_FIX), @ZUG_SML1" 3 bytes + 4 lines 1 byte of "RET NC" on the 5th line + 2 bytes of the command "LDQ A, (LOW R_TDN_FLG)" on the 5th line + 3 bytes of the command "LD HL,D_EFF_TMR-2" on the 6th line + 1 byte of the command "RST WORDSEL" on the 7th line + 8th line "RET" 1 byte = 14 bytes, and the execution cycle is 2nd line 3 cycles + 3rd line 4 cycles + 4th line 3 cycles (1 cycle) + 5th line 2 cycles + 6th line 3 cycles + 7th line 4 Cycle + 3 cycles in the 8th row = 22 cycles (20 cycles). Note that the cycle number in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "RET NC".

Therefore, by replacing the command group in FIG. 167(a) with the command group in FIG. 167(b), the total command size is reduced by 1 byte. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing game control processing.

In addition, in order to understand by comparing FIG. 167(a) and FIG. 167(b), the command group that occupied two lines (third and fourth lines) in FIG. 167(a) is 167(b), it can be expressed in one line (third line), making it possible to reduce the number of commands themselves and reduce the design load.

Further, in the example of FIG. 167(b), the A register is not used in the command on the third line. Therefore, the value of the A register will not be updated unintentionally. In addition, in the example of FIG. 167(a), if the A register was already in use when executing the command on the third line, it was necessary to stack and save the value of the A register, but here, Since the A register is not used, there is no need for stack processing. In this way, resources can be used effectively.

<JTANDQ>
FIG. 168 is a flowchart showing specific processing of the SWI_PRC module. The SWI_PRC module executes the switch management process in step S500 (see FIG. 28). The numerical values of step S in this figure will be used only in the explanation of this figure.

As shown in FIG. 168, the main CPU 300a determines whether the first variable starting port detection switch 120Bs is detected (S1), and if the first variable starting port detection switch 120Bs is detected (YES in S1). , executes the first starting port passing process (S2) and the normal electric accessory prize winning confirmation process (S3). On the other hand, if the first variable starting port detection switch 120Bs is not detected (NO in S1), the first starting port passing process (S2) and the normal electric accessory prize winning confirmation process (S3) are skipped. Note that step S1 corresponds to step S500-7 in FIG. 28, step S2 corresponds to step S520 in FIG. 28, and step S3) corresponds to step S500-9 in FIG.

FIG. 169 is an explanatory diagram for explaining an example of a command for implementing the SWI_PRC module. The flowchart shown in FIG. 168 is realized, for example, by the program shown in FIG. 169.

The index “SWI_PRC:” in the first line of FIG. 169(a) indicates the start address of the SWI_PRC module. Then, by the command "LDQ A, (LOW R_IN3_PON)" on the second line of FIG. 1 byte, and read the value stored at that address to the A register. Here, in the value stored at the same address, for example, the least significant bit holds the detection result of the first fixed starting port detection switch 120As (input section), and the second lower bit holds the detection result of the second starting port detection switch 120As (input section). The detection result of the mouth detection switch 122s (input part) is held, and the detection result of the first variable starting mouth detection switch 120Bs (input part) is held in the third lower bit. Each of these bits becomes "1" when the detection switch detects that the game ball has entered the ball, and becomes "0" when the detection switch does not detect that the game ball has entered the ball.

The command "AND A, @IN3_ST2_BIT" on the third line calculates the AND of the read value and the fixed value "@IN3_ST2_BIT (00000100b here). As a result, all but the third lower bit of the read value are set to 0. (masked), and if the lower 3 bits of the read value are 0, the zero flag = 1, and if the lower 3 bits of the read value are 1, the zero flag = 0. In other words, the first variable start If the detection result of the mouth detection switch 120Bs is 1 (if the entry of a game ball is detected), the zero flag = 0, and if the detection result of the first variable starting mouth detection switch 120Bs is 0 (if the entry of a game ball is detected), the zero flag = 0. (If no ball entering the ball is detected), the zero flag becomes 0.

Then, by the command "JR Z, SWI_PRC_20" on the fourth line, if the zero flag is 1 (Z), the process moves to SWI_PRC_20 (seventh line). The commands on the second to fourth lines correspond to step S1 in FIG. 168.

On the other hand, if the zero flag is not 1 by the command "JR Z,SWI_PRC_20" on the 4th line, the STA_PAS module is called as a subroutine by the command "CALLF STA_PAS" on the 5th line, and the STA_PAS module performs the first starting port passage process. is executed. The command on the fifth line corresponds to step S2 in FIG. 168. Further, the command "CALLF FDN_CHK" on the 6th line calls the FDN_CHK module as a subroutine, and the FDN_CHK module executes the normal electric accessory winning confirmation process. The command on the sixth line corresponds to step S3 in FIG. 168.

Here, the command group in FIG. 169(a) can be changed as shown in FIG. 169(b). Here, descriptions of processes that are substantially the same as those in FIG. 169(a) will be omitted, and only processes that are different from those in FIG. 169(b) will be described.

The command "JTANDQ Z, (LOW R_IN3_PON), @IN3_ST2_BIT, SWI_PRC_20" in the second line of FIG. The lower 1 byte of the address is calculated, and the logical product of the value stored at the address and the fixed value "@IN3_ST2_BIT" is calculated, and if the zero flag is 1, the process moves to SWI_PRC_20. The command on the second line corresponds to step S1 in FIG. 168. The command size of such a command is "4" and the execution cycle is "5 (6)". Note that the cycle number in parentheses indicates the execution cycle when the zero flag is 1 and the process moves to SWI_PRC_20.

Here, the total command size of the command group shown in FIG. 169(a) is 2 bytes of the second line command "LDQ A, (LOW R_IN3_PON)" + 2 bytes of the third line command "AND A, @IN3_ST2_BIT" + 4 lines. 2nd command “JR Z,SWI_PRC_20” 2 bytes + 5th line command “CALLF STA_PAS” 2 bytes + 6th line command “CALLF FDN_CHK” 2 bytes = 10 bytes, and the total execution cycle is 2nd line 3 cycles + 3 lines 2 cycles on the 4th row + 2 (3) cycles on the 4th row + 4 cycles on the 5th row + 4 cycles on the 6th row = 15 (16) cycles. Note that the cycle number in parentheses indicates the execution cycle when the zero flag is 1 and the process moves to SWI_PRC_20.

On the other hand, the total command size of the command group shown in FIG. 169(b) is 4 bytes for the command "JTANDQ Z, (LOW R_IN3_PON), @IN3_ST2_BIT, SWI_PRC_20" on the second line + 2 bytes for the command "CALLF STA_PAS" on the third line. +2 bytes of the command "CALLF FDN_CHK" on the 4th line = 8 bytes, and the total execution cycle is 5 (6) cycles on the 2nd line + 4 cycles on the 3rd line + 4 cycles on the 4th line = 13 (14) cycles.

Therefore, by replacing the command group in FIG. 169(a) with the command group in FIG. 169(b), the total command size is reduced by 2 bytes, and the total execution cycle is also reduced by at least 2 cycles. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

Also, in order to understand by comparing FIG. 169(a) and FIG. 169(b), the command group that occupied three lines (second to fourth lines) in FIG. 169(a) is 169(b), it can be expressed in one line (second line), and it is possible to reduce the number of commands themselves and reduce the design load.

Further, in the example of FIG. 169(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. In addition, in the example of FIG. 169(a), if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, the stack processing is also not necessary. unnecessary. In this way, resources can be used effectively.

<OUT>
FIG. 170 is a flowchart showing specific processing of the CPUINIT module. The CPUINIT module executes the CPU initialization process (see FIG. 22). The numerical values of step S in this figure will be used only in the explanation of this figure.

The main CPU 300a executes an access permission process to permit access to the RAM 300c, as shown in FIG. 170 (S1). Note that step S1 corresponds to step S100-9 in FIG. 22.

FIG. 171 is an explanatory diagram for explaining an example of a command for implementing the CPUINIT module. The flowchart shown in FIG. 170 is realized, for example, by the program shown in FIG. 171.

The index “CPUINIT:” in the first line of FIG. 171(a) indicates the start address of the CPUINIT module. Then, by the command "LD A, (@RAMENBL)" on the second line of FIG. 171(a), a fixed value "@RAMENBL" (here, 1) indicating that access is permitted is read into the A register. Then, the command “OUT (@RAP_＿＿＿),A” on the third line in FIG. 171(a) sets the value of the U register to the upper 1 byte of the address, and sets the value of the U register to the upper 1 byte of the address, and The fixed value "@RAP______" indicating the lower 1 byte of the address is set as the lower 1 byte, and the value (1) of the A register is output to that address. Note that the upper 1 byte (for example, "FEH") of the address of the RAM access protection register port (internal register I/O port) is preset in the U register.

Here, the command group in FIG. 171(a) can be changed as shown in FIG. 171(b). Here, a description of processes that are substantially the same as those in FIG. 171(a) will be omitted, and only processes that are different from those in FIG. 171(b) will be described.

The command “OUT (@RAP______), @RAMENBL” on the second line of FIG. 171(b) sets the value of the U register to the upper 1 byte of the address, and sets the address of the RAM access protect register port (internal register I/O port). The fixed value "@RAP______" indicating the lower 1 byte of is set as the lower 1 byte, and the fixed value "@RAMENBL", that is, 1, is output to that address. The command size of such a command is "3" and the execution cycle is "4".

Here, the total command size of the command group shown in FIG. 171(a) is 2 bytes for the command "LD A, (@RAMENBL)" on the second line + 2 bytes for the command "OUT (@RAP______),A" on the third line. = 4 bytes, and the total execution cycle is 2 cycles on the 2nd line + 3 cycles on the 3rd line = 5 cycles.

On the other hand, the total command size of the command group shown in FIG. 171(b) is 3 bytes = 3 bytes for the command "OUT (@RAP______), @RAMENBL" in the second line, and the total execution cycle is 4 cycles in the second line. = 4 cycles.

Therefore, by replacing the command group in FIG. 171(a) with the command group in FIG. 171(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

Also, in order to understand by comparing FIG. 171(a) and FIG. 171(b), the command group that occupied two lines (second to third lines) in FIG. 171(a) is 171(b), it can be expressed in one line (second line), making it possible to reduce the number of commands themselves and reduce the design load.

Further, in the example of FIG. 171(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. In addition, in the example of FIG. 171(a), if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, the stack processing is also not necessary. unnecessary. In this way, resources can be used effectively.

FIG. 172 is an explanatory diagram for explaining the TMR_IPT module. The TMR_IPT module shown in FIG. 172 executes the timer interrupt process shown in FIG. 98.

The index “TMR_IPT:” in the first line of FIG. 172(a) indicates the start address of the TMR_IPT module. Then, by the command "LD A, @TOCRVAL" on the second line of FIG. 172(a), a fixed value "@TOCRVAL" (here, 1) indicating that access is permitted is read into the A register. Then, the command "OUT (@PTOCR__),A" on the third line of FIG. 172(a) sets the value of the U register to the upper 1 byte of the address, and sets the value of the U register to the upper 1 byte of the address and sets the value of the RAM access protect register port (internal register I/O port). The fixed value "@PTOCR__" indicating the lower 1 byte of the address is set as the lower 1 byte of the address, and the value (1) of the A register is output to that address. Note that the upper 1 byte (for example, "FEH") of the address of the RAM access protection register port (internal register I/O port) is preset in the U register.

Here, the command group in FIG. 172(a) can be changed as shown in FIG. 172(b). Here, a description of processes that are substantially the same as those in FIG. 172(a) will be omitted, and only processes that are different from those in FIG. 172(b) will be described.

The command “OUT (@PTOCR___), @TOCRVAL” on the second line of FIG. 172(b) sets the value of the U register to the upper 1 byte of the address, and sets the address of the RAM access protect register port (internal register I/O port). The fixed value "@PTOCR__" indicating the lower 1 byte of the address is set as the lower 1 byte of the address, and the fixed value "@TOCRVAL", that is, 1 is output to that address. The command size of such a command is "3" and the execution cycle is "4".

Here, the total command size of the command group shown in FIG. 172(a) is: 2 bytes of the command "LD A, @TOCRVAL" on the 2nd line + 2 bytes of the command "OUT (@PTOCR__),A" on the 3rd line = The total execution cycle is 4 bytes, and the total execution cycle is 2 cycles on the second line + 3 cycles on the third line = 5 cycles.

On the other hand, the total command size of the command group shown in FIG. 172(b) is 3 bytes = 3 bytes for the command "OUT (@PTOCR__), @TOCRVAL" in the second line, and the total execution cycle is 4 cycles in the second line. = 4 cycles.

Therefore, by replacing the command group in FIG. 172(a) with the command group in FIG. 172(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

In addition, in order to understand by comparing FIG. 172(a) and FIG. 172(b), the command group that occupied two lines (second to third lines) in FIG. 172(a) is 172(b) can be expressed in one line (second line), making it possible to reduce the number of commands themselves and reduce the design load.

Further, in the example of FIG. 172(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. In addition, in the example of FIG. 172(a), if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, the stack processing is also not necessary. unnecessary. In this way, resources can be used effectively.

<LDQ>
FIG. 173 is a flowchart showing specific processing of the FZ_SPN module. The FZ_SPN module executes the normal symbol fluctuation processing (see FIG. 53). The numerical values of step S in this figure will be used only in the explanation of this figure.

The main CPU 300a saves the normal symbol stop symbol number (counter value) in the normal symbol display symbol counter as shown in FIG. 173. (S1). Note that step S1 corresponds to step S820-9 in FIG. 53.

FIG. 174 is an explanatory diagram for explaining an example of a command for realizing the FZ_SPN module. The flowchart shown in FIG. 173 is realized, for example, by the program shown in FIG. 174.

The index “FZ_SPN:” in the first line of FIG. 174(a) indicates the start address of the FZ_SPN module. Then, the command "LDQ A, (LOW R_FZ_STP)" on the second line of FIG. It is set to 1 byte, and the value stored at that address (normal symbol stop symbol number) is read to the A register.

Then, the command "LDQ (LOW R_FZ_DSP), A" on the second line of FIG. It is set to 1 byte, and the value of the A register is stored at that address (the address of the normal symbol display symbol counter).

Here, the command group in FIG. 174(a) can be changed as shown in FIG. 174(b). Here, a description of processes that are substantially the same as those in FIG. 174(a) will be omitted, and only processes that are different from those in FIG. 174(b) will be described.

The command "LDQ (LOW R_FZ_DSP), (LOW R_FZ_STP)" on the second line of FIG. The value stored at that address is set as the lower 1 byte, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "R_FZ_DSP" is set as the lower 1 byte of the address, and the value is stored at that address.

Here, the total command size of the command group shown in FIG. 174(a) is 2 bytes for the command "LDQ A, (LOW R_FZ_STP)" on the second line + 2 bytes for the command "LDQ (LOW R_FZ_DSP), A" on the third line. = 4 bytes, and the total execution cycle is 3 cycles on the 2nd line + 3 cycles on the 3rd line = 6 cycles.

On the other hand, the total command size of the command group shown in FIG. 174(b) is 4 bytes = 4 bytes for the command "LDQ (LOW R_FZ_DSP), (LOW R_FZ_STP)" on the second line, and the total execution cycle is as follows: 6 cycles = 6 cycles.

Therefore, as can be understood by comparing FIG. 174(a) and FIG. 174(b), the command group that occupied two lines (second to third lines) in FIG. 174(a) is It can be expressed in one line (second line) in Figure 174(b) without changing the command size and total execution cycle, making it possible to reduce the number of commands themselves and reduce the design load. .

Further, in the example of FIG. 174(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. In addition, in the example of FIG. 174(a), if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, the stack processing is also not necessary. unnecessary. In this way, resources can be used effectively.

FIG. 175 is an explanatory diagram for explaining an example of a command for implementing the CPUINIT module. Here, the special game progresses in either a low probability game state or a high probability game state. The gaming machine 100 is provided with an indicator that indicates that the gaming state is a high probability gaming state, and when the gaming state is the high probability gaming state, the indicator lights up. When the player is not informed of the high probability gaming state upon recovery from power outage (so-called latent state), the display device can be hidden. At this time, if it is determined whether or not the display is lit based on the actual gaming state, if the gaming state at the time of power failure recovery is a high probability gaming state, the display will be lit. Therefore, a flag indicating that the game is in hiding is prepared from when the power is restored until the big prize game is started for the first time, and it is determined whether the display is lit or not based on the flag.

The index “CPUINIT:” in the first line of FIG. 175(a) indicates the start address of the CPUINIT module. Then, by the command "LDQ A, (LOW R_KAK_FLG)" on the second line of FIG. 1 byte, and the value stored at that address (the address of the flag indicating whether or not it is a high probability gaming state) (1 if it is a high probability gaming state, 0 if it is not a high probability gaming state) is stored in the A register. read out.

Then, the command "LDQ (LOW R_KAK_HOT), A" on the third line of FIG. It is set to 1 byte, and the value of the A register is stored at that address (the address of the flag indicating that it is hidden).

Here, the command group in FIG. 175(a) can be changed as shown in FIG. 175(b). Here, descriptions of processes that are substantially the same as those in FIG. 175(a) will be omitted, and only processes that are different from those in FIG. 175(b) will be described.

The command “LDQ (LOW R_KAK_HOT), (LOW R_KAK_FLG)” in the second line of FIG. The value stored at that address is set as the lower 1 byte, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "R_KAK_HOT" is set as the lower 1 byte of the address, and the value is stored at that address.

Here, the total command size of the command group shown in Figure 175(a) is 2 bytes for the command "LDQ A, (LOW R_KAK_FLG)" on the second line + 2 bytes for the command "LDQ (LOW R_KAK_HOT), A" on the third line. = 4 bytes, and the total execution cycle is 3 cycles on the 2nd line + 3 cycles on the 3rd line = 6 cycles.

On the other hand, the total command size of the command group shown in FIG. 175(b) is 4 bytes = 4 bytes for the command "LDQ (LOW R_KAK_HOT), (LOW R_KAK_FLG)" on the second line, and the total execution cycle is as follows: 6 cycles = 6 cycles.

Therefore, in order to understand by comparing FIG. 175(a) and FIG. 175(b), the command group that occupied two lines (second to third lines) in FIG. 175(a) is 175(b), it can be expressed in one line (second line), making it possible to reduce the number of commands themselves and reduce the design load.

Further, in the example of FIG. 175(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. In addition, in the example of FIG. 175(a), if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, the stack processing is also not necessary. unnecessary. In this way, resources can be used effectively.

FIG. 176 is an explanatory diagram for explaining an example of a command for realizing the EXE_SET module. The EXE_SET module shown in FIG. 176 executes the execution flag setting process shown in step S2400-11 in FIG.

The index “EXE_SET:” in the first line of FIG. 176(a) indicates the start address of the EXE_SET module. Then, by the command "LDQ A, (LOW AT_NXT)" on the second line of FIG. 1 byte, and the value (value indicating the performance status of the next game) stored at that address (address of the value indicating the performance status of the next game) is read into the A register.

Then, the command "LDQ (LOW AT_MOD), A" on the third line of FIG. It is assumed to be 1 byte, and the value of the A register is stored at that address (the address of the value indicating the performance state of the game).

Here, the command group in FIG. 176(a) can be changed as shown in FIG. 176(b). Here, a description of processes that are substantially the same as those in FIG. 176(a) will be omitted, and only processes that are different from those in FIG. 176(b) will be described.

The command "LDQ (LOW AT_MOD), (LOW AT_NXT)" in the second line of FIG. 176(b) sets the value of the Q register to the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "AT_NXT" to the address. The value stored at that address is set as the lower 1 byte, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "AT_MOD" is set as the lower 1 byte of the address, and the value is stored at that address.

Here, the total command size of the command group shown in Figure 176(a) is 2 bytes for the command "LDQ A, (LOW AT_NXT)" on the second line + 2 bytes for the command "LDQ (LOW AT_MOD), A" on the third line. = 4 bytes, and the total execution cycle is 3 cycles on the 2nd line + 3 cycles on the 3rd line = 6 cycles.

On the other hand, the total command size of the command group shown in FIG. 176(b) is 4 bytes = 4 bytes for the command "LDQ (LOW AT_MOD), (LOW AT_NXT)" on the second line, and the total execution cycle is as follows: 6 cycles = 6 cycles.

Therefore, in order to understand by comparing FIG. 176(a) and FIG. 176(b), the command group that occupied two lines (second to third lines) in FIG. 176(a) is 176(b), it can be expressed in one line (second line), making it possible to reduce the number of commands and reduce the design load.

Further, in the example of FIG. 176(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. In addition, in the example of FIG. 176(a), if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, the stack processing is also not necessary. unnecessary. In this way, resources can be used effectively.

<LDIN>
FIG. 177 is a flowchart showing specific processing of the HPT_GRP module. The HPT_GRP module executes the reach group determination process of step S612-7 in the special symbol variation number determination process (see FIG. 39). The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the description of the HPT_GRP module, the first register is the HL register, and the other registers are the BC register or the A register.

In the reach group determination process, the address of the reach group determination random number determination table determined in advance according to the reservation type, the number of reservations, the gaming state, etc. is stored in advance in the HL register.

As shown in FIG. 177, the main CPU 300a loads the comparison value stored at the address (table address) indicated in the HL register into the BC register, and adds 2 to the value in the HL register (S1). As will be described in detail later, in the reach group determination random number judgment table, a 2-byte long comparison value and a 1-byte long group number are set as one set, and a plurality of these sets are stored consecutively in order. . Therefore, here, by adding 2 to the value of the HL register after loading the comparison value, the HL register becomes the address value in which the group number stored next to the loaded comparison value is stored.

After that, the main CPU 300a compares the comparison value loaded into the BC register with the reach group determination random number (random value) loaded in advance into the DE register (S2), and determines the reach group stored at the address indicated in the HL register. Load the group number (S3).

After that, the main CPU 300a adds 1 to the value of the HL register (table address) (S4). Here, by adding 1 to the value of the HL register after loading the group number, the HL register becomes the address value where the comparison value stored next to the loaded group number is stored.

Then, as a result of the comparison in step S2, if the comparison value is less than or equal to the reach group determination random number (random value) (YES in S5), the main CPU 300a returns the process to step S1, and the comparison value is the reach group determination random number. If it is not below (NO in S5), the HPT_GRP module is ended (S6).

FIGS. 178(a) and 178(b) are explanatory diagrams for explaining an example of commands for realizing the HPT_GRP module. FIG. 178(c) is an explanatory diagram for explaining an example of a reach group determination random number determination table. The flowchart shown in FIG. 177 is realized, for example, by the programs shown in FIGS. 178(a) and 178(b). First, the reach group determination random number determination table shown in FIG. 178(c) will be explained, and then the commands for realizing the HPT_GRP module shown in FIGS. 178(a) and 178(b) will be explained.

The table starting from the index “D_GRP_SEL_00:” in FIG. 178(c) indicates the start address of any reach group determination random number determination table. The fixed value "8999" on the second line, the fixed value "9099" on the fourth line, and the fixed value "9299" on the sixth line are each 2-byte long comparison values, and the fixed value " The fixed value "@D_MOD_SEL_00", the fixed value "@D_MOD_SEL_01" on the fifth line, and the fixed value "@D_MOD_SEL_02" on the seventh line are each 1-byte long group numbers. In the reach group determination random number determination table, a 2-byte length comparison value and a 1-byte length group number corresponding to the comparison value are stored in one set in succession.

The index “HPT_GRP:” in the first line of FIG. 178(a) indicates the start address of the HPT_GRP module. Then, the command "LDIN BC, (HL)" on the second line of FIG. 178(a) reads (loads) the 2-byte length value (comparison value) stored at the address indicated by the HL register into the BC register. ), add 2 to the value of the HL register. The command on the second line corresponds to step S1 in FIG. 177. Note that the address of a predetermined reach group determination random number determination table is loaded in advance into the HL register.

Then, the command "CP BC, DE" in the third line of FIG. 178(a) compares the value stored in the BC register (comparison value) with the value stored in the DE register (reach group determination random number). do. Here, if the value stored in the BC register is less than or equal to the value stored in the DE register, 1 will be set in the zero flag (if equal) or the carry flag (if less than). Note that a reach group determination random number is stored in advance in the DE register. The command on the third line corresponds to step S2 in FIG. 177.

Thereafter, the 1-byte length value (group number) stored at the address indicated by the HL register is read into the A register by the command "LD A, (HL)" in the fourth line of FIG. 178(a). The command on the fourth line corresponds to step S3 in FIG. 177. Then, the value of the HL register is incremented by 1 by the command "INC HL" on the 5th line of FIG. 178(a). The command on the fifth line corresponds to step S4 in FIG. 177.

Next, if the zero flag or carry flag is set to 1 by the command "CP BC, DE" in the third line by the command "JLS HPT_GRP" in the sixth line of FIG. 178(a), the address indicated by "HPT_GRP" is If the zero flag and carry flag are not set to 1, the HPT_GRP module is terminated by the command "RET" on the 7th line of FIG. 178(a). The commands on the 6th and 7th lines correspond to steps S5 and S6 in FIG. 177. Then, when the HPT_GRP module is completed, the group number corresponding to the range shown in FIG. 9 will be stored in the A register.

Here, the command group in FIG. 178(a) can be changed as shown in FIG. 178(b). Here, a description of processes that are substantially the same as those in FIG. 178(a) will be omitted, and only processes that are different from those in FIG. 178(b) will be described.

The command "LDIN A, (HL)" in the fourth line of FIG. 178(b) reads the 1-byte length value (group number) stored at the address indicated by the HL register into the A register, and reads the value of the HL register. Add 1 to The command on the fourth line corresponds to steps S3 and S4 in FIG. 177. The command size of such a command is "1" and the execution cycle is "2".

Here, the total command size of the command group shown in FIG. 178(a) is 2 bytes of the command "LDIN BC, (HL)" on the 2nd line + 2 bytes of the command "CP BC, DE" on the 3rd line + 2 bytes of the command "CP BC, DE" on the 4th line. Command “LD A, (HL)” 1 byte + 5th line command “INC HL” 1 byte + 6th line command “JLS HPT_GRP” 3 bytes + 7th line command “RET” 1 byte = 10 bytes, total execution The cycle is 4 cycles on the 2nd row + 2 cycles on the 3rd row + 2 cycles on the 4th row + 1 cycle on the 5th row + 4 (3) cycles on the 6th row + 3 cycles on the 7th row = 16 (15) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "JLS HPT_GRP".

On the other hand, the total command size of the command group shown in Figure 178(b) is: 2 bytes of the command "LDIN BC, (HL)" on the 2nd line + 2 bytes of the command "CP BC, DE" on the 3rd line + 2 bytes of the command on the 4th line "LDIN A, (HL)" 1 byte + 5th line command "JLS HPT_GRP" 3 bytes + 6th line command "RET" 1 byte = 9 bytes, and the total execution cycle is 4 cycles on the 2nd line + 2 cycles on the 3rd line. Cycle + 2 cycles in the 4th row + 4 (3) cycles in the 5th row + 3 cycles in the 6th row = 15 (14) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "JLS HPT_GRP".

Therefore, by replacing the command group in FIG. 178(a) with the command group in FIG. 178(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

In addition, in order to understand by comparing FIG. 178(a) and FIG. 178(b), the command group that occupied two lines (4th to 5th lines) in FIG. 178(a) is 178(b), it can be expressed in one line (fourth line), making it possible to reduce the number of commands themselves and reduce the design load.

In the example shown in FIG. 178(b), when obtaining a desired 2-byte or 1-byte value from a table in which multiple values with different byte lengths are arranged alternately, the value of the HL register is Addition by 2 and addition by 1 can be executed with the same command "LDIN", making it possible to reduce the design load.

FIG. 179 is an explanatory diagram for explaining the E_ILGER module. The E_ILGER module shown in FIG. 179 executes the fraud monitoring process shown in step S3100-19 in FIG. 98.

The index “E_ILGER:” in the first line of FIG. 179(a) indicates the start address of the E_ILGER module. The command "LD HL,_EX_ILTM" on the second line reads the address "EX_ILTM" in which the illegal input monitoring timer is stored into the HL register.

Thereafter, the command "LD A, (HL)" on the third line of FIG. 179(a) reads the 1-byte length value (incorrect input monitoring timer) stored at the address indicated by the HL register into the A register. Then, the value of the HL register is incremented by 1 by the command "INC HL" on the fourth line of FIG. 179(a). Next, the command "JT Z, A, E_ILGER01" on the 5th line of FIG. 179(a) is used to omit the subsequent processing if the value of the A register is 0 (if the illegal input monitoring timer is 0). Then, the command moves to the index "E_ILGER01:" on the sixth line, and if the value of the A register is not 0, the process moves to the command next to the command in question.

Here, the command group in FIG. 179(a) can be changed as shown in FIG. 179(b). Here, descriptions of processes that are substantially the same as those in FIG. 179(a) will be omitted, and only processes that are different from those in FIG. 179(b) will be described.

The command "LDIN A, (HL)" on the third line in FIG. 179(b) reads the 1-byte length value (incorrect input monitoring timer) stored at the address indicated by the HL register into the A register, Add 1 to the value of . The command size of such a command is "1" and the execution cycle is "2".

Here, the total command size of the command group shown in FIG. 179(a) is 3 bytes for the command "LD HL,_EX_ILTM" on the 2nd line + 1 byte for the command "LD A, (HL)" on the 3rd line + 1 byte for the command "LD A, (HL)" on the 4th line. 1 byte of the command “INC HL” + 2 bytes of the command “JT Z, A, E_ILGER01” on the 5th line = 7 bytes, and the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 1 cycle on the 4th line + 5 lines 3rd (2) cycle = 9 (8) cycle. Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "JT Z, A, E_ILGER01".

On the other hand, the total command size of the command group shown in FIG. 179(b) is 3 bytes for the command "LD HL,_EX_ILTM" on the 2nd line + 1 byte for the command "LDIN A, (HL)" on the 3rd line + 1 byte for the command "LDIN A, (HL)" on the 4th line. Command "JT Z, A, E_ILGER01" 2 bytes = 6 bytes, and the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 3 (2) cycles on the 4th line = 8 (7) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "JT Z, A, E_ILGER01".

Therefore, by replacing the command group in FIG. 179(a) with the command group in FIG. 179(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

Also, in order to understand by comparing FIG. 179(a) and FIG. 179(b), the command group that occupied two lines (3rd to 4th lines) in FIG. 179(a) is 179(b), it can be expressed in one line (third line), making it possible to reduce the number of commands themselves and reduce the design load.

FIG. 180 is an explanatory diagram for explaining the E_LEVOT module. The E_LEVOT module shown in FIG. 180 is a subroutine called in the execution flag setting process shown in step S2400-11 in FIG. 91, and executes the lever press test signal transmission process.

The index “E_LEVOT:” in the first line of FIG. 180(a) indicates the start address of the E_LEVOT module. The command "LD HL, T_EXM_STP" on the second line reads the address "T_EXM_STP" for storing the test stop information transmission table into the HL register. In this test stop information transmission table, six 1-byte length test signal values are stored consecutively as one set, and a plurality of sets are stored consecutively.

Thereafter, the value of the A register is added to the value of the HL register by the command "ADDWB HL,A" on the third line of FIG. 180(a), and the value of the HL register is updated. Note that the A register stores a value obtained by multiplying the instruction information type by 6. Therefore, here, the value of the HL register indicates one set of leading addresses corresponding to the instruction information type in the test stop information transmission table.

Then, the fixed value "6" is read into the B register by the command "LD B,6" on the fourth line. The index "E_LEVOT01:" in the fifth line of FIG. 180(a) indicates the address of the index "E_LEVOT01."

The command "LD A, (HL)" on the 6th line of FIG. 180(a) reads the 1-byte length value (test signal value) stored at the address indicated by the HL register into the A register. Then, by the command "OUT (@S2DT__),A" on the 7th line of FIG. 180(a), the value of the U register is set to the upper 1 byte of the address, and the RAM access protect register port (internal register I/O port) is set. The fixed value "@S2DT__" indicating the lower 1 byte of the address is set as the lower 1 byte, and the value of the A register is output to that address.

The command "INC HL" on the 8th line of FIG. 180(a) adds 1 to the value of the HL register. Next, the value of the B register is decremented (subtracted by 1) by the command "DJNZ E_LEVOT01" on the 9th line of FIG. , if the decremented result is 0, the process moves to the command next to the command in question.

Here, the command group in FIG. 180(a) can be changed as shown in FIG. 180(b). Here, a description of processes that are substantially the same as those in FIG. 180(a) will be omitted, and only processes that are different from those in FIG. 180(b) will be described.

The command "LDIN A, (HL)" on the 6th line in Figure 180(b) reads the 1-byte length value (test signal value) stored at the address indicated by the HL register into the A register, Add 1 to the value of . The command size of such a command is "1" and the execution cycle is "2".

Here, the total command size of the command group shown in FIG. 180(a) is 3 bytes of the command "LD HL, T_EXM_STP" on the 2nd line + 1 byte of the command "ADDWB HL,A" on the 3rd line + 1 byte of the command on the 4th line. “LD B,6” 2 bytes + 6th line command “LD A, (HL)” 1 byte + 7th line command “OUT (@S2DT___),A” 2 bytes + 8th line command “INC HL” 1 byte +2 bytes of the command “DJNZ E_LEVOT01” on the 9th line = 12 bytes, and the total execution cycle is 3 cycles on the 2nd line + 1 cycle on the 3rd line + 2 cycles on the 4th line + 2 cycles on the 6th line + 3 cycles on the 7th line + 1 cycle on the 8th line Cycle+9th row 3(2) cycles=15(14) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "DJNZ E_LEVOT01".

On the other hand, the total command size of the command group shown in FIG. 180(b) is 3 bytes for the command "LD HL,T_EXM_STP" on the 2nd line + 1 byte for the command "ADDWB HL,A" on the 3rd line + 1 byte for the command "ADDWB HL,A" on the 4th line. LD B, 6” 2 bytes + 6th line command “LDIN A, (HL)” 1 byte + 7th line command “OUT (@S2DT__),A” 2 bytes + 5th line command “DJNZ E_LEVOT01” 2 bytes = The total execution cycle is 11 bytes, and the total execution cycle is 3 cycles on the 2nd line + 1 cycle on the 3rd line + 2 cycles on the 4th line + 2 cycles on the 6th line + 3 cycles on the 7th line + 3 (2) cycles on the 9th line = 14 (13) cycles. . Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "DJNZ E_LEVOT01".

Therefore, by replacing the command group in FIG. 180(a) with the command group in FIG. 180(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. In particular, in the example of FIG. 180(a), if the value of the B register in the command "DJNZ E_LEVOT01" is 2 or more, the difference in total execution cycles increases by the value multiplied by 1 cycle. The amount of reduction in the total execution cycle in b) is also large. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

In addition, in order to understand by comparing FIG. 180(a) and FIG. 180(b), the command group that occupied two lines (6th line, 8th line) in FIG. 180(a) is 180(b), it can be expressed in one line (sixth line), making it possible to reduce the number of commands and the design load.

<LDQP>
FIG. 181 is a flowchart showing specific processing of the SBC_OUT module. The SBC_OUT module executes the subcommand transmission process (see FIG. 23) in step S100-65 above. The numerical values of step S in this figure will be used only in the explanation of this figure.

Here, the subcommand is set in the transmission buffer in multiple processes in the interrupt process, and is transmitted in the subcommand transmission process. Here, the transmission buffer is, for example, a 96-byte ring buffer, and subcommands are set in order in a plurality of processes, and in the subcommand transmission process, the subcommands set first are sent to the sub control board 330 in order. It is FIFO.

As shown in FIG. 181, the main CPU 300a reads the value of the subcommand write pointer into the A register (S1), and compares the value of the subcommand write pointer with the value of the subcommand read pointer (S2). Here, if the value of the subcommand write pointer and the value of the subcommand read pointer are the same, that is, if there are no unsent subcommands, the zero flag is set to 1, and if they are different, that is, there are no unsent subcommands. If there is, the zero flag will not be set to 1.

If the zero flag is 1 (YES in S3), the main CPU 300a terminates the SBC_OUT module, and if the zero flag is not 1 (NO in S3), the main CPU 300a sets the subcommand pointer upper limit value and the address of the subcommand read pointer. The lower bytes are each read into the DE register (S4), and the value of the sub-command read pointer is incremented by 1 if it is less than the sub-command pointer upper limit value, and cleared to zero by the count-up process which is a general-purpose module. S5).

After that, the main CPU 300a reads the address of the subcommand buffer (transmission buffer) into the HL register (S6), executes the word data selection process described above (S7), and then reads the address of the subcommand buffer (transmission buffer) into the SCU1 data register for transmitting the subcommand. The command is output (S8), the subsequent command is read to the A register (S9), the subsequent command is output to the SCU1 data register (S10), and the SBC_OUT module ends (S11).

FIG. 182 is an explanatory diagram for explaining an example of a command for implementing the SBC_OUT module.

The index “SBC_OUT:” in the first line of FIG. 182(a) indicates the start address of the SBC_OUT module. Then, by the command "LDQ A, (LOW R_SBC_WPT)" on the second line of FIG. The value stored at that address (the value of the subcommand write pointer) is read into the A register. The command on the second line corresponds to step S1 in FIG. 181.

The command "CPQ A, (LOW R_SBC_RPT)" on the third line of FIG. 182(a) sets the value of the Q register as the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_SBC_RPT" as the lower 1 byte of the address. The value stored at that address (the value of the subcommand read pointer) is compared with the value of the A register (the value of the subcommand write pointer). Here, if the value stored at the same address matches the value of the A register, 1 is set in the zero flag. The command on the third line corresponds to step S2 in FIG. 181.

If the zero flag is set to 1 by the command "RET Z" in the fourth line of FIG. 182(a), the SBC_OUT module is terminated. The command on the fourth line corresponds to step S3 in FIG. 181.

By the command "LD DE,@LMT_CMD_BFP*256+LOW R_SBC_RPT" on the 5th line of FIG. "R_SBC_RPT" indicating the lower byte of is read to the E register. The command on the fifth line corresponds to step S4 in FIG. 181.

The command "RST COUNTUP" on the 6th line of FIG. 182(a) reads and executes the COUNTUP module, which is a general-purpose module. As a result, the value of the subcommand read pointer is incremented by 1 if it is less than the subcommand pointer upper limit, and cleared to zero if it is greater than or equal to the subcommand pointer upper limit. The command on the sixth line corresponds to step S5 in FIG. 181.

By the command "LD HL,R_SBC_SBF" on the 7th line of FIG. 182(a), "R_SBC_SBF" indicating the address of the subcommand buffer (transmission buffer) is read into the HL register. The command on the seventh line corresponds to step S6 in FIG. 181. Here, "R_SBC_SBF" is 2-byte length data. If the upper 1 byte of the address of the subcommand buffer is "F0H", it can be read by the command "LDQ", but since the upper 1 byte of the subcommand buffer may be "F1H", Here, 2-byte length data is read without using the command "LDQ".

The WORDSEL module, which is a general-purpose module, is read by the command "RST WORDSEL" on the 8th line of FIG. 182(a), the value of the A register is added to the HL register twice, and the The value of the lower byte (the value of the L register, ie, the preceding command) is read into the A register. The command on the eighth line corresponds to step S7 in FIG. 181.

The command "OUT (@S1DT__),A" on the 9th line of FIG. 182(a) outputs the value of the A register (preceding command) to the address indicated by the fixed value "@S1DT__". The command on the ninth line corresponds to step S8 in FIG. 181.

The value of the H register (subsequent command) is read to the A register by the command "LD A,H" on the 10th line of FIG. 182(a). The command on the 10th line corresponds to S9 in FIG. 181.

The command “OUT (@S1DT___),A” on the 11th line of FIG. 182(a) outputs the value of the A register (subsequent command) to the address indicated by the fixed value “@S1DT___”, and the corresponding SBC_OUT module finish. The command on the 11th line corresponds to step S10 in FIG. 181, and the command on the 12th line corresponds to step S11 in FIG. 181.

Here, the command group in FIG. 182(a) can be changed as shown in FIG. 182(b). Here, we will explain the case where the upper 1 byte of the subcommand buffer (transmission buffer) is "F1H", omit the explanation of the process that is substantially the same as that in Figure 182(a), and Only the different processes will be explained.

The command "LDQP HL, LOW R_SBC_SBF" on the 7th line of FIG. subcommand buffer address) is read into the HL register. The command on the seventh line corresponds to step S6 in FIG. 181. The command size of such a command is "3" and the execution cycle is "7 (5)".

Here, the total command size of the command group shown in FIG. 182(a) is 2 bytes of the second line command "LDQ A, (LOW R_SBC_WPT)" + 3 bytes of the third line command "CPQ A, (LOW R_SBC_RPT)" + 4th line command “RET Z” 1 byte + 5th line command “LD DE,@LMT_CMD_BFP*256+LOW R_SBC_RPT” 2 bytes + 6th line command “RST COUNTUP” 1 byte + 7th line command “LD HL,R_SBC_SBF” 3 bytes + 8th line command “RST WORDSEL” 1 byte + 9th line command “OUT (@S1DT__),A” 2 bytes + 10th line command “LD A,H” 1 byte + 11th line command “OUT ( @S1DT__),A" 2 bytes + 1 byte of the command "RET" on the 12th line = 19 bytes, and the total execution cycle is 2 cycles on the 2nd line + 4 cycles on the 3rd line + 3 (1) cycles on the 4th line + 2 cycles on the 5th line. Cycle + 4 cycles on the 6th line + 3 cycles on the 7th line + 4 cycles on the 8th line + 3 cycles on the 9th line + 1 cycle on the 10th line + 3 cycles on the 11th line + 3 cycles on the 12th line = 32 (30) cycles. Note that the cycle number in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "RET Z".

On the other hand, the total command size of the command group shown in FIG. 182(b) is 2 bytes for the second line command "LDQ A, (LOW R_SBC_WPT)" + 3 bytes for the third line command "CPQ A, (LOW R_SBC_RPT)" + 4 Line command “RET Z” 1 byte + 5th line command “LD DE,@LMT_CMD_BFP*256+LOW R_SBC_RPT” 2 bytes + 6th line command “RST COUNTUP” 1 byte + 7th line command “LDQP HL,LOW R_SBC_SBF” 3 bytes + 8th line command “RST WORDSEL” 1 byte + 9th line command “OUT (@S1DT__),A” 2 bytes + 10th line command “LD A,H” 1 byte + 11th line command “OUT ( @S1DT__),A" 2 bytes + 1 byte of the command "RET" on the 12th line = 19 bytes, and the total execution cycle is 2 cycles on the 2nd line + 4 cycles on the 3rd line + 3 (1) cycles on the 4th line + 2 cycles on the 5th line. Cycle + 4 cycles on the 6th line + 5 cycles on the 7th line + 4 cycles on the 8th line + 3 cycles on the 9th line + 1 cycle on the 10th line + 3 cycles on the 11th line + 3 cycles on the 12th line = 34 (32) cycles. Note that the cycle number in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "RET Z".

Therefore, by replacing the command group in FIG. 182(a) with the command group in FIG. 182(b), when accessing an address after F100H with "F0" set in the Q register (upper 1 When the byte is "F1H"), it is possible to reduce the design load. In addition, in the special symbol storage area shift processing shown in step S610-9 of FIG. 37, when reading the special game special symbol discrimination flag, the upper 1 byte of the address where the special game special symbol discrimination flag is stored is set as "F1H". , the command "LDQP" may be used. Furthermore, in the external information management process shown in step S400-29 in FIG. You may also use Furthermore, in the power-off saving process of FIG. 25, when saving the backup validity determination value in the backup validity determination flag, the upper 1 byte of the address where the backup validity determination flag is stored is set to "F1H", and the command "LDQP" You may also use

<RCPQ>
FIG. 183 is an explanatory diagram for explaining an example of another command for implementing the SBC_OUT module. Note that since FIG. 183(a) is the same as FIG. 182(a), the explanation will be omitted. Further, regarding FIG. 183(b), descriptions of processes that are substantially the same as those in FIG. 183(a) will be omitted, and only processes that are different from FIG. 183(b) will be described.

The command "RCPQ Z,A, (LOW R_SBC_RPT)" on the third line of FIG. Compare the value stored at that address (subcommand read pointer value) with the value of the A register (subcommand write pointer value), and if the zero flag is set to 1, execute the command "RET". ”, the SBC_OUT module is terminated. The command on the third line corresponds to steps S2 to S4 in FIG. 181. The command size of such a command is "3" and the execution cycle is "7 (5)". Note that the cycle number in parentheses indicates the execution cycle when the command does not move to the next higher routine.

Here, the total command size of the command group shown in FIG. 183(b) is the command "LDQ A, (LOW R_SBC_WPT)" on the second line, 2 bytes + the command "RCPQ Z,A, (LOW R_SBC_RPT)" on the third line. 3 bytes + 4th line command “LD DE,@LMT_CMD_BFP*256+LOW R_SBC_RPT” 2 bytes + 5th line command “RST COUNTUP” 1 byte + 6th line command “LD HL,R_SBC_SBF” 3 bytes + 7th line command “RST” WORDSEL” 1 byte + 8th line command “OUT (@S1DT__),A” 2 bytes + 9th line command “LD A,H” 1 byte + 10th line command “OUT (@S1DT__),A” 2 bytes + 11 The command "RET" on the line 1 byte = 18 bytes, and the total execution cycle is 2 cycles on the 2nd line + 7 (5) cycles on the 3rd line + 2 cycles on the 4th line + 4 cycles on the 5th line + 3 cycles on the 6th line + 7th line 4 cycles + 3 cycles on the 8th row + 1 cycle on the 9th row + 3 cycles on the 10th row + 3 cycles on the 11th row = 32 (30) cycles. Note that the cycle number in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "RCPQ Z, A, (LOW R_SBC_RPT)".

Therefore, by replacing the command group in FIG. 183(a) with the command group in FIG. 183(b), the total command size is reduced by 1 byte. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing game control processing.

Also, in order to understand by comparing FIG. 183(a) and FIG. 183(b), the command group that occupied two lines (3rd to 4th lines) in FIG. 183(a) is 183(b), it can be expressed in one line (third line), making it possible to reduce the number of commands themselves and reduce the design load.

FIG. 184 is an explanatory diagram for explaining an example of a command for realizing the FZ_OPN module. The FZ_OPN module shown in FIG. 184 executes the normal electric accessory prize opening control process (see FIG. 57).

In the normal electric accessory prize opening control process, in the above step S850-5, whether the counter value of the ordinary electric accessory winning ball number counter has not reached the specified number, that is, if the first variable starting opening 120B has 1 It is determined whether the same number of game balls as the maximum possible winning number during the opening/closing control of the game are entered. As a result, if it is determined that the specified number has not been reached, the normal electric accessory prize opening control process is ended, and if it is determined that the specified number has been reached, the process moves to step S850-7.

As this normal electric accessory prize opening control process, the index "FZ_OPN:" in the first line of FIG. 184(a) indicates the start address of the FZ_OPN module. Then, in step S850-5, the command "LDQ A, (LOW R_FDN_CNT)" on the second line sets the value of the Q register as the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_FDN_CNT" as the lower 1 byte of the address. 1 byte, and the value stored at that address (the counter value of the normal electric accessory winning ball counter) is read into the A register. The command "CP A, @FDN_CNT" on the third line compares the value of the A register with a fixed value "@FDN_CNT" indicating a specified number, in this case 8. That is, if the value of the A register is less than 8, the carry flag is set to 1. Then, if the carry flag is 1 by "RET C" on the fourth line, the FZ_OPN module is terminated. That is, if the counter value of the normal electric accessory winning ball number counter is less than 8, the FZ_OPN module is ended. Note that if the carry flag is not 1, the subsequent processing is executed.

Here, the command group in FIG. 184(a) can be changed as shown in FIG. 184(b). Here, a description of processes that are substantially the same as those in FIG. 184(a) will be omitted, and only processes that are different from those in FIG. 184(b) will be described.

The command "RCPQ C, (LOW R_FDN_CNT),@FDN_CNT" on the second line of FIG. The value stored in the lower 1 byte (the counter value of the normal electric accessory winning ball counter) is compared with the fixed value "@FDN_CNT" indicating the specified number, here 8, and the carry flag is determined. If it is 1, the FZ_OPN module is terminated to execute the command "RET". The command size of such a command is "4" and the execution cycle is "8 (6)". Note that the cycle number in parentheses indicates the execution cycle when the command does not move to the next higher routine.

Here, the total command size of the command group shown in FIG. 184(a) is 2 bytes for the second line command "LDQ A, (LOW R_FDN_CNT)" + 3 bytes for the third line command "CP A, @FDN_CNT" + 4 lines. The second command "RET C" 1 byte = 6 bytes, and the total execution cycle is 2 cycles on the 2nd line + 4 cycles on the 3rd line + 3 (1) cycles on the 4th line = 9 (7) cycles. Note that the cycle number in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "RET C".

On the other hand, the total command size of the command group shown in FIG. 184(b) is 4 bytes = 4 bytes for the command "RCPQ C, (LOW R_FDN_CNT), @FDN_CNT" on the second line, and the total execution cycle is as follows: 8 (6) cycles = 8 (6) cycles. Note that the cycle number in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "RCPQ C, (LOW R_FDN_CNT), @FDN_CNT".

Therefore, by replacing the command group in FIG. 184(a) with the command group in FIG. 184(b), the total command size is reduced by 2 bytes, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

In addition, in order to understand by comparing FIG. 184(a) and FIG. 184(b), the command group that occupied three lines (second to fourth lines) in FIG. 184(a) is 184(b), it can be expressed in one line (second line), making it possible to reduce the number of commands themselves and reduce the design load.

Further, in the example of FIG. 184(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. In addition, in the example of FIG. 184(a), if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, the stack processing is also not necessary. unnecessary. In this way, resources can be used effectively.

FIG. 185 is an explanatory diagram for explaining an example of a command for implementing the TD_OPN module. The TD_OPN module shown in FIG. 185 executes the big winning opening control process (see FIG. 47).

In the grand prize opening control process, in step S720-5 above, it is determined whether the counter value of the grand prize opening winning balls counter has not reached the specified number, that is, the maximum possible number of prizes in one round is determined in the grand prize opening. It is determined whether the same number of game balls have entered the ball. As a result, if it is determined that the specified number has not been reached, the big winning opening control process is ended, and if it is determined that the specified number has been reached, the process moves to step S720-7.

As this big winning opening control process, the index "TD_OPN:" in the first line of FIG. 185(a) indicates the start address of the TD_OPN module. Then, in step S720-5, the command "LDQ A, (LOW R_TDN_FLG)" on the second line sets the value of the Q register to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_TDN_FLG" to the lower 1 byte of the address. The value stored at that address (special motorized accessory designation flag) is read into the A register. In addition, the special electric accessory designation flag indicates which big winning hole is the target of the big winning hole opening control process.

The command "LD HL, D_TDC_MAX-1" on the third line subtracts 1 from the address of the big prize opening stipulated winning number data table (the table showing the stipulated number of the special electric accessory actuation ram set table in Figure 14). is read into the HL register.

The BYTESEL module, which is a general-purpose module, is read by the command "RST BYTESEL" on the fourth line of FIG. 185(a), the value of the A register is added to the HL register, and the value stored at the address indicated in the HL register is (specified number) is read into the A register.

The command "CPQ A, (LOW R_TDN_CNT)" on the 5th line of FIG. 185(a) sets the value of the Q register as the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_TDN_CNT" as the lower 1 byte of the address. Then, the value stored at that address (counter value of the big winning hole winning ball number counter) and the value of the A register, 10 in this case, are compared. That is, if the value stored at the same address is less than 10, the carry flag is not set and becomes 0. Then, if the carry flag is 0 by "RET NC" on the 6th line, the corresponding TD_OPN module is ended. That is, if the counter value of the big winning hole winning ball number counter is less than 10, the TD_OPN module is ended. Note that if the carry flag is 1, the subsequent processing is executed.

Here, the command group in FIG. 185(a) can be changed as shown in FIG. 185(b). Here, descriptions of processes that are substantially the same as those in FIG. 185(a) will be omitted, and only processes that are different from those in FIG. 185(b) will be described.

The command "RCPQ NC,A, (LOW R_TDN_CNT)" on the 5th line of FIG. 1 byte, and compares the value stored at that address (counter value of the winning ball winning slot counter) with the value of the A register (default value), here 10, and if the carry flag is 0. , terminates the TD_OPN module to execute the command "RET". The command size of such a command is "3" and the execution cycle is "7 (5)". Note that the cycle number in parentheses indicates the execution cycle when the command does not move to the next higher routine.

Here, the total command size of the command group shown in FIG. 185(a) is 2 bytes of the command "LDQ A, (LOW R_TDN_FLG)" on the second line + 3 bytes of the command "LD HL, D_TDC_MAX-1" on the third line + 4 The command “RST BYTESEL” on the 5th line is 1 byte + the command on the 5th line is 3 bytes “CPQ A, (LOW R_TDN_CNT)” + the command “RET NC” on the 4th line is 1 byte = 10 bytes, and the total execution cycle is 2 on the 2nd line. Cycle + 3 cycles on the 3rd row + 3 cycles on the 4th row + 4 cycles on the 5th row + 3 (1) cycles on the 4th row = 15 (13) cycles. Note that the cycle number in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "RET NC".

On the other hand, the total command size of the command group shown in FIG. 185(b) is 2 bytes for the second line command "LDQ A, (LOW R_TDN_FLG)" + 3 bytes for the third line command "LD HL, D_TDC_MAX-1" + 4 lines. The second command “RST BYTESEL” 1 byte + the 5th line command “RCPQ NC,A, (LOW R_TDN_CNT)” 3 bytes = 9 bytes, and the total execution cycle is 2 cycles on the 2nd line + 3 cycles on the 3rd line + 3 cycles on the 4th line Cycle + 7 (5) cycles in the 5th row = 15 (13) cycles. Note that the cycle number in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the command "RCPQ NC,A, (LOW R_TDN_CNT)".

Therefore, by replacing the command group in FIG. 185(a) with the command group in FIG. 185(b), the total command size is reduced by 1 byte. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing game control processing.

Also, in order to understand by comparing FIG. 185(a) and FIG. 185(b), the command group that occupied two lines (5th line to 6th line) in FIG. 185(a) is 185(b), it can be expressed in one line (fifth line), making it possible to reduce the number of commands and reduce the design load.

<JCPQ>
FIG. 186 is an explanatory diagram for explaining an example of a command for implementing the HSY_PRC module. The HSY_PRC module shown in FIG. 186 executes launch position designation management processing (see step S400-27 in FIG. 26).

As part of this firing position designation management process, the index "HSY_PRC:" in the first line of FIG. 186(a) indicates the start address of the HSY_PRC module. The command "XOR A,A" on the second line calculates the exclusive OR of the value of the A register and the value of the A register, and initializes the A register.

Then, by the command "LDQ HL, LOW R_TDN_FLG" on the third line, the value of the Q register is read to the H register, and the value of the lower 1 byte of the address "R_TDN_FLG" is read to the L register.

The command "JCP NZ, (HL),@TDK_AT2,HSY_PRC_10" on the fourth line sets the value shown in the HL register (special electric accessory designation flag) and the fixed value "@TDK_AT2" indicating the second grand prize opening. If the zero flag is not set to 1, the process moves to the address indicated by the index "HSY_PRC_10" on the 7th line (the process branches).

On the other hand, if the zero flag is set to 1, the command "LDQ HL,LOW R_ZUG_CHK_FIX" on the fifth line reads the value of the Q register to the H register, and reads the value of the lower 1 byte of the address "R_ZUG_CHK_FIX" to the L register. .

The command "JCP NZ, (HL), @ZUG_SML1, HSY_PRC_20" on the 6th line sets the value shown in the HL register (special symbol judgment flag) and the fixed value "@ZUG_SML1" indicating the small winning symbol 1 designation data here. Then, compare it with 07H, and if the zero flag is not set to 1, move to the address indicated by the index "HSY_PRC_20" on the 8th line (branch the process).

Here, the command group in FIG. 186(a) can be changed as shown in FIG. 186(b). Here, a description of processes that are substantially the same as those in FIG. 186(a) will be omitted, and only processes that are different from those in FIG. 186(b) will be described.

The command "JCPQ NZ, (LOW R_TDN_FLG),@TDK_AT2,HSY_PRC_10" on the third line of FIG. The lower 1 byte of the address is used, and the value shown in that address (special electric accessory designation flag) is compared with the fixed value "@TDK_AT2" indicating the second big prize opening, and if 1 is not set in the zero flag, Move to the address indicated by the index "HSY_PRC_10" on the fifth line (branch the process).

The command "JCPQ NZ, (LOW R_ZUF_CHK_FIX, @ZUG_SML1, HSY_PRC_20") on the fourth line of FIG. The value shown at that address (special symbol determination flag) is compared with the fixed value "@TDK_AT2" indicating the second major winning opening, and the fixed value "@TDK_AT2" indicating the small winning symbol 1 designation data is determined. ZUG_SML1", here 07H, and if the zero flag is not set to 1, the process moves to the address indicated by the index "HSY_PRC_20" on the 6th line (branching the process).

Here, the total command size of the command group shown in FIG. 186(a) is 1 byte of the command "XOR A, A" on the 2nd line + 2 bytes of the command "LDQ HL, LOW R_TDN_FLG" on the 3rd line + 2 bytes of the command "LDQ HL, LOW R_TDN_FLG" on the 4th line. Command “JCP NZ,(HL),@TDK_AT2,HSY_PRC_10” 4 bytes + 5th line command “LDQ HL,LOW R_ZUG_CHK_FIX” 2 bytes + 6th line command “JCP NZ,(HL),@ZUG_SML1,HSY_PRC_20” 4 bytes = 13 bytes, and the total execution cycle is 1 cycle on the 2nd line + 2 cycles on the 3rd line + 6 (5) cycles on the 4th line + 2 cycles on the 5th line + 2 cycles on the 6th line 6 (5) = 17 (15) cycles . Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "JCP NZ, . . .".

On the other hand, the total command size of the command group shown in FIG. 186(b) is the command "XOR A, A" 1 byte on the second line + the command "JCPQ NZ, (LOW R_TDN_FLG), @TDK_AT2,HSY_PRC_10" on the third line. 4 bytes + 4th line command "JCPQ NZ, (LOW R_ZUG_CHK_FIX, @ZUG_SML1, HSY_PRC_20") 4 bytes = 9 bytes, and the total execution cycle is 1 cycle on the 2nd line + 6 (5) cycles on the 3rd line + 6 (5) cycles on the 4th line. 5)=13 (11) cycles.The number of cycles in parentheses indicates the execution cycle when no movement is performed by the command "JCP NZ,...".

Therefore, by replacing the command group in FIG. 186(a) with the command group in FIG. 186(b), the total command size is reduced by 4 bytes, and the total execution cycle is also reduced by at least 4 cycles. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

Also, in order to understand by comparing FIG. 186(a) and FIG. 186(b), the command group that occupied four lines (3rd to 6th lines) in FIG. 186(a) is 186(b), it can be expressed in two lines (3rd to 4th lines), making it possible to reduce the number of commands themselves and reduce the design load.

Further, in the example of FIG. 186(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. In addition, in the example of FIG. 186(a), if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, the stack processing is also not necessary. unnecessary. In this way, resources can be used effectively.

FIG. 187 is an explanatory diagram for explaining an example of a command for implementing the FDN_CHK module. The FDN_CHK module shown in FIG. 187 executes a normal electric accessory winning confirmation process (see step S500-9 in FIG. 28).

As this normal electric accessory winning confirmation process, the index "FDN_CHK:" in the first line of FIG. 187(a) indicates the start address of the FDN_CHK module.

Then, the command "LDQ HL, (LOW R_FDN_EFF)" on the second line sets the value of the Q register to the upper 1 byte of the address, sets the value of the lower 1 byte of the address "R_FDN_EFF" to the lower 1 byte of the address, and sets the value of the Q register to the lower 1 byte of the address. (the value of the normal electric accessory closure valid timer) is read into the HL register.

The command "RET NTZ" on the third line terminates the FDN_CHK module if the zero flag is not 1. The reason why "NTZ" is used here is that the second zero flag changes by the command "LDQ HL, (LOW R_FDN_EFF)" but the first zero flag does not change.

The command "LDQ A, (LOW R_FUT_PHS)" on the fourth line sets the value of the Q register as the upper 1 byte of the address, sets the value of the lower 1 byte of the address "R_FUT_PHS" as the lower 1 byte of the address, and sets the value of that address. (Normal game management phase) is read into the A register.

The command "JCP NZ, A, @FD_OPN, FDN_CHK_10" on the 5th line sets the value shown in the A register (normal game management phase) and the fixed value "@FD_OPN" indicating the normal electric accessory prize opening control process, Here, it is compared with 04H, and if the zero flag is not set to 1, the process moves to the address indicated by the index "FDN_CHK_10" on the 8th line (the process branches).

On the other hand, if the zero flag is set to 1, the command "INCQ (LOW R_FDN_CNT)" on the 6th line sets the value of the Q register to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_FDN_CNT" to the address. Add 1 to the value stored at that address (the counter value of the normal electric accessory winning ball counter), store the added value at the same address, and use the command "RET" on the 7th line. , terminate the corresponding FDN_CHK module.

Here, the command group in FIG. 187(a) can be changed as shown in FIG. 187(b). Here, a description of processes that are substantially the same as those in FIG. 187(a) will be omitted, and only processes that are different from those in FIG. 187(b) will be described.

The command "JCPQ NZ, (LOW R_FUT_PHS), @FD_OPN, FDN_CHK_10" on the fourth line of FIG. The lower 1 byte of the address is compared with the value of the address (normal game management phase) and the fixed value "@FD_OPN", here 04H, which indicates the normal electric accessory prize opening control process, and 1 is set in the zero flag. If not, the process moves to the address indicated by the index "FDN_CHK_10" on the seventh line (the process branches).

Here, the total command size of the command group shown in Figure 187(a) is: 2 bytes of the command "LDQ HL, (LOW R_FDN_EFF)" on the 2nd line + 1 byte of the command "RET NTZ" on the 3rd line + 1 byte of the command "RET NTZ" on the 4th line. Command “LDQ A, (LOW R_FUT_PHS)” 2 bytes + 5th line command “JCP NZ,A,@FD_OPN,FDN_CHK_10” 3 bytes + 6th line command “INCQ (LOW R_FDN_CNT)” 2 bytes + 7th line command “ RET" 1 byte = 11 bytes, and the total execution cycle is 4 cycles on the 2nd line + 3 (1) cycles on the 3rd line + 2 cycles on the 4th line + 4 (3) cycles on the 5th line + 5 cycles on the 6th line + 3 cycles on the 7th line. =21 (18) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the commands "RET NTZ" and "JCP NZ, . . .".

On the other hand, the total command size of the command group shown in FIG. 187(b) is 2 bytes of the command "LDQ HL, (LOW R_FDN_EFF)" on the 2nd line + 1 byte of the command "RET NTZ" on the 3rd line + 1 byte of the command on the 4th line. “JCPQ NZ, (LOW R_FUT_PHS),@FD_OPN,FDN_CHK_10” 4 bytes + 5th line command “INCQ (LOW R_FDN_CNT)” 2 bytes + 6th line command “RET” 1 byte = 10 bytes, and the total execution cycle is: 4 cycles on the 2nd row + 3 (1) cycles on the 3rd row + 6 (5) cycles on the 4th row + 5 cycles on the 5th row + 3 cycles on the 6th row = 19 (16) cycles. Note that the number of cycles in parentheses indicates the execution cycle when no movement is performed by the commands "RET NZ" and "JCPQ NTZ, . . .".

Therefore, by replacing the command group in FIG. 187(a) with the command group in FIG. 187(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 2 cycles. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

In addition, in order to understand by comparing FIG. 187(a) and FIG. 187(b), the command group that occupied two lines (4th line to 5th line) in FIG. 187(a) is 187(b), it can be expressed in one line (fourth line), making it possible to reduce the number of commands themselves and reduce the design load.

Further, in the example of FIG. 187(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. In addition, in the example of FIG. 187(a), if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, the stack processing is also not necessary. unnecessary. In this way, resources can be used effectively.

FIG. 188 is an explanatory diagram for explaining an example of a command for realizing the FZ_STP module. The FZ_STP module shown in FIG. 188 executes a normal symbol stop symbol display process (see FIG. 54).

As this normal symbol stop symbol display processing, the index "FZ_STP:" in the first line of FIG. 188(a) indicates the start address of the FZ_STP module.

Then, if the second zero flag is not set to 1 by the command "RET NTZ" on the second line, the FZ_STP module is terminated.

The command "LDQ A, (LOW R_FZ_ATA)" on the third line sets the value of the Q register as the upper 1 byte of the address, sets the value of the lower 1 byte of the address "R_FZ_ATA" as the lower 1 byte of the address, and sets the value of that address. (Normal symbol hit flag) is read into the A register. The normal symbol winning flag becomes 01H when a win is determined in the common symbol lottery, and becomes 00H when a loss is determined.

The command "JCP Z, A, @FZ_ATA, FZ_STP_10" on the fourth line compares the value shown in the A register (normal symbol hit flag) with the fixed value "@FZ_ATA" indicating a hit, here 01H, If the zero flag is set to 1, the process moves to the address indicated by the index "FZ_STP_10" on the 8th line (processing branches).

On the other hand, if the zero flag is not set to 1, the command "CLRQ (LOW R_FUT_PHS)" on the 5th line sets the value of the Q register to the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_FUT_PHS" to the address. It is set as the lower 1 byte, and 0 is assigned (cleared) to the value stored at that address (normal game management phase).

The command "CLRQ (LOW R_FZ_STP)" on the 6th line sets the value of the Q register as the upper 1 byte of the address, the value of the lower 1 byte of the address "R_FZ_STP" as the lower 1 byte of the address, and stores the data at that address. 0 is assigned (cleared) to the value (normal symbol stop symbol number), and the command "RET" on the 7th line terminates the FZ_STP module.

Here, the command group in FIG. 188(a) can be changed as shown in FIG. 188(b). Here, descriptions of processes that are substantially the same as those in FIG. 188(a) will be omitted, and only processes that are different from those in FIG. 188(b) will be described.

The command "JCPQ Z, (LOW R_FZ_ATA), @FZ_ATA, FZ_STP_10" on the third line of FIG. The lower 1 byte of the address is compared with the value of that address (normal symbol hit flag) and the fixed value "@FZ_ATA" indicating a hit, here 01H, and if the zero flag is set to 1, the value of the 7th line is Move to the address indicated by the index "FZ_STP_10" (branch the process).

Here, the total command size of the command group shown in Figure 188(a) is 1 byte of the command "RET NTZ" on the 2nd line + 2 bytes of the command "LDQ A, (LOW R_FZ_ATA)" on the 3rd line + 2 bytes of the command "LDQ A, (LOW R_FZ_ATA)" on the 4th line. Command “JCP Z,A,@FZ_ATA,FZ_STP_10” 3 bytes + 5th line command “CLRQ (LOW R_FUT_PHS)” 2 bytes + 6th line command “CLRQ (LOW R_FZ_STP)” 2 bytes + 7th line command “RET” 1 byte = 11 bytes, and the total execution cycle is 3 (1) cycles on the 2nd line + 2 cycles on the 3rd line + 4 (3) cycles on the 4th line + 2 cycles on the 5th line + 2 cycles on the 6th line + 3 cycles on the 7th line = 16 (13) It becomes a cycle. Note that the number of cycles in parentheses indicates the execution cycle when the routine is not moved to the next higher routine by the commands "RET NTZ" and "JCP Z, . . .".

On the other hand, the total command size of the command group shown in FIG. 188(b) is 1 byte for the command "RET NTZ" on the second line + 4 bytes for the command "JCPQ Z, (LOW R_FZ_ATA), @FZ_ATA, FZ_STP_10" on the third line. + 2 bytes of the command “CLRQ (LOW R_FUT_PHS)” on the 4th line + 2 bytes of the command “CLRQ (LOW R_FZ_STP)” on the 5th line + 1 byte of the command “RET” on the 6th line = 10 bytes, and the total execution cycle is 2 lines. 3rd (1) cycle + 6 (5) cycles in the 3rd row + 2 cycles in the 4th row + 2 cycles in the 5th row + 3 cycles in the 6th row = 16 (13) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the commands "RET NTZ" and "JCPQ Z, . . .".

Therefore, by replacing the command group in FIG. 188(a) with the command group in FIG. 188(b), the total command size is reduced by 1 byte. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing game control processing.

Also, in order to understand by comparing FIG. 188(a) and FIG. 188(b), the command group that occupied two lines (3rd to 4th lines) in FIG. 188(a) is 188(b), it can be expressed in one line (third line), making it possible to reduce the number of commands themselves and reduce the design load.

Further, in the example of FIG. 188(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. In addition, in the example of FIG. 188(a), if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, the stack processing is also not necessary. unnecessary. In this way, resources can be used effectively.

<Random number generator>
FIG. 189 is a block diagram for explaining the configuration of random number generators 740-746. As described above, the main CPUs 300a and 500a are provided with a plurality of random number generators.

For example, as shown in FIG. 189, the main CPUs 300a and 500a have four channels of a maximum value setting random number generator 740, which is a random number generator that can set a maximum value of 16 bits, and the maximum value of 16 bits is fixed at 65536. The maximum value fixed random number generator 742, which is a random number generator, has 4 channels, and the maximum value setting random number generator 744, which is a random number generator that can set the maximum value of 8 bits, has 8 channels, and the maximum value of 8 bits is 255. A maximum value fixed random number generator 746, which is a random number generator fixed to , is provided with eight channels. These random number generators 740 to 746 are hardware random number generators (hardware random number generators).

The maximum value setting random number generator 740 can set the random number update cycle to any one of 32 to 47 clocks, and the start value can be set to 0001h, a value based on an ID number, or a value that is changed every time the system is reset. It can be set as follows. The maximum value fixed random number generator 742 has a random number update period of one clock, and a start value that is changed every time the system is reset. Note that the system reset is to reset the state in terms of hardware, and is executed when a predetermined abnormality occurs when the power is turned on.

The maximum value setting random number generator 744 can set the random number update cycle to any one of 16 to 31 clocks, and the start value can be set to 01h, a value based on the ID number, or a value that is changed every time the system is reset. It can be set as follows. The maximum value fixed random number generator 746 has a random number update period of one clock, and a start value that is changed every time the system is reset. In the initial setting process of step S100-1, a start value is set and saved, and a random number update cycle of maximum value setting random number generators 740 and 744 is set and saved.

Further, the start values of these random number generators 740 to 746 are updated every time the system is reset. Then, the maximum value setting random number generator 740 updates the random number (random number counter) once at any one of the 32nd clock to the 47th clock of the internal system clock using hardware. The maximum value setting random number generator 744 updates the random number (random number counter) once at any one of the 16th to 31st clocks of the internal system clock using hardware. The maximum value fixed random number generators 742 and 746 update random numbers (random number counters) once per clock of the internal system clock using hardware. Further, these random number generators 740 to 746 update the random numbers according to a certain rule, and the random number string is automatically updated every time the random number string is passed around. Then, when the software determines that the game ball has passed through the predetermined area, a random number (hardware random number count value) is obtained from the random number register.

Furthermore, in the main CPUs 300a and 500a, it is also possible to generate software random numbers by multiplying and dividing the random numbers obtained from the random number generators 740 to 746 by a predetermined value within the program (software random number generation unit). It is. The software random number generation unit updates the random number while the interrupt processing that occurs every 4 ms is not being executed. Specifically, the software random number generation unit compares the previous random number with the maximum value, sets the random number to 0 if the previous random number has reached the maximum value, and sets the random number to 0 if the previous random number has not reached the maximum value. If so, add 1 to the random number. Then, when it is determined that the game ball has passed through the predetermined area, a random number (software random number count value) is obtained.

Here, in the gaming machine 100, a jackpot determination random number, a winning symbol random number, a reach group determination random number, a reach mode determination random number, a variable pattern random number, and a hit determination random number are provided as random numbers.

The jackpot determination random number is in the range of 0 to 65535, the winning symbol random number is in the range of 0 to 99, the reach group determination random number is in the range of 0 to 10006, the reach mode determination random number is in the range of 0 to 250, The varying pattern random numbers range from 0 to 238, and the winning random numbers range from 0 to 99.

In addition, when providing a plurality of normal winning symbols, it is necessary to provide a normal symbol random number, which ranges from 0 to 99, for example. Furthermore, when providing a plurality of normal symbol fluctuation patterns (variation times), it is necessary to provide a regular symbol fluctuation pattern random number, which ranges from 0 to 99, for example.

FIG. 190 is a diagram illustrating combinations of random number generators. For example, since it is necessary to generate a random number from 0 to 65,535 as the jackpot determining random number, a 16-bit random number generated by the maximum value setting random number generator 740 whose maximum value is set to 65,535 is used. Since it is necessary to generate a random number from 0 to 99 as the winning symbol random number, an 8-bit random number generated by a software random number generation unit with the maximum value set to 99 is used.

Since it is necessary to generate a random number from 0 to 10006 as the reach group determination random number, a 16-bit random number generated by the maximum value setting random number generator 740 whose maximum value is set to 10006 is used. Since it is necessary to generate a random number from 0 to 250, an 8-bit random number generated by a software random number generation unit with a maximum value of 250 is used as the reach mode determination random number. As the fluctuation pattern random number, it is necessary to generate random numbers from 0 to 238, so an 8-bit random number generated by a software random number generator whose maximum value is set to 238 is used.

Since it is necessary to generate a random number from 0 to 99 as the winning determination random number, an 8-bit random number generated by a maximum value setting random number generator 744 whose maximum value is set to 99 is used. Since it is necessary to generate a random number from 0 to 99, an 8-bit random number generated by a software random number generation unit with the maximum value set to 99 is used as the general pattern random number. Since it is necessary to generate a random number from 0 to 99 for the common pattern fluctuation pattern random number, an 8-bit random number generated by a software random number generation unit with the maximum value set to 99 is used.

Here, when using random numbers generated by a software random number generation unit, in step S100-61 of FIG. 23, step S400-17 of FIG. 26, and step S100-69 of FIG. 23, the initial value of the random number is determined, It is necessary to perform processing to update random numbers. In this case, there is a possibility that the capacity of the control area for performing game control processing will be compressed.

Therefore, as shown in FIGS. 190(b) and (c), for example, the jackpot determining random number is in the range of 0 to 65535, the winning symbol random number is in the range of 0 to 99, and the reach group determining random number is in the range of 0 to 10,006. The reach mode determination random number is in the range of 0 to 1000, the fluctuation pattern random number is in the range of 0 to 255, the winning determination random number is in the range of 0 to 65535, the normal pattern random number is in the range of 0 to 99, and the normal pattern random number is in the range of 0 to 99. The fluctuation pattern random number is in the range of 0 to 255. Note that the range of these random numbers is an example, and the maximum value is 65535, which is the maximum value of the maximum fixed random number generator 742, and the maximum value is 255, which is the maximum value of the maximum fixed random number generator 746. The random number may be set to any random number.

As shown in FIG. 190(b), the jackpot determination random number uses a 16-bit random number generated by the maximum value setting random number generator 740 whose maximum value is set to 65,535. The winning symbol determining random number uses an 8-bit random number generated by a maximum value setting random number generator 740 whose maximum value is set to 99. The reach group determination random number uses a 16-bit random number generated by the maximum value setting random number generator 740 whose maximum value is set to 10,006. The reach mode determination random number uses a 16-bit random number generated by a maximum value setting random number generator whose maximum value is set to 1000. As the variable pattern random number, an 8-bit random number generated by a maximum value fixed random number generator 746 whose maximum value is fixed to 255 is used.

The winning determination random number uses a 16-bit random number generated by the maximum value setting random number generator 740 whose maximum value is set to 65,535. An 8-bit random number generated by a maximum value setting random number generator 744 whose maximum value is set to 99 is used as the general pattern random number. An 8-bit random number generated by a maximum value fixed random number generator 746 whose maximum value is fixed to 255 is used as the general figure fluctuation pattern random number.

Further, as shown in FIG. 190(c), a 16-bit random number generated by a maximum value fixed random number generator 742 whose maximum value is fixed to 65535 may be used as the jackpot determination random number and the hit determination random number. The maximum value setting random number generator 740 can set the start value, random number update cycle, maximum value of random numbers, etc. as appropriate, but the random number update cycle is slower than the maximum value fixed random number generator 742. Therefore, for the random numbers that are directly connected to the player's profits (jackpot determining random numbers and winning determining random numbers), it is preferable to use the maximum value fixed random number generator 742, which has a fast random number update cycle and is difficult to read.

In this way, by using the random numbers generated by the random number generators 740 to 746 (hardware random number generation unit) as the plurality of random numbers used to proceed with the game, steps S100-61 in FIG. 23 and FIG. In step S400-17 of FIG. 23 and step S100-69 of FIG. 23, it is no longer necessary to determine the initial value of the random number or to execute the process of updating the random number. As a result, the capacity of the main ROM 300b can be reduced by about 35 bytes, and the capacity of the main RAM 300c can be reduced by about 4 bytes. In this way, it becomes possible to secure the capacity of the control area for performing game control processing.

<Command “OR”>
FIG. 191 is a flowchart showing specific processing of the SMC_ROT module. Here, as an arbitrary process, a process of compositing a phase flag indicating the position of the reel with an index flag, which is part of the SMC_ROT module that executes the steady rotation process, will be described. Here, the index flag is a flag represented by a 1-byte value that is turned ON when an index signal is acquired after the reels 410a, 410b, and 410c reach a steady rotation speed. For example, when the index signal of the left reel 410a is acquired, bit 0 of the index flag becomes 1, when the index signal of the middle reel 410b is acquired, bit 1 of the index flag becomes 1, and when the index signal of the right reel 410c is acquired, the index flag bit 0 becomes 1. Bit 2 becomes 1. By referring to this index flag, it is possible to confirm which reels 410a, 410b, and 410c have acquired index signals. Further, the phase flag is a one-byte flag that specifies the reels 410a, 410b, and 410c that are being processed. For example, while processing the left reel 410a, bit 0 of the phase flag becomes 1 (00000001B), while processing the middle reel 410b, bit 1 of the phase flag becomes 1 (00000010B), and while processing the right reel 410c, bit 1 of the phase flag becomes 1 (00000001B). Bit 2 becomes 1 (00000100B). The numerical values of step S in this figure will be used only in the explanation of this figure. Further, in the description of the SMC_ROT module, the first register is the C register, the second register is the HL register, and the register different from the first register and the second register is the A register.

It is assumed that at the stage of executing the SMC_ROT module, the value of the phase flag is already held in a predetermined register (eg, C register). Then, the main CPU 500a executes arbitrary processing as shown in FIG. 191. The main CPU 500a first sets in the HL register the address of the index flag (variable) to be subjected to the logical sum (S1). Then, in order to synthesize the phase flag with the index flag, the main CPU 500a calculates the logical sum of the already set value of the C register (phase flag) and the 1-byte value stored at the address indicated by the HL register. Then, in order to reflect the result of the logical sum in the index flag, it overwrites the value stored at the address indicated by the HL register (S2). Here, synthesis means that when any bit of the variable phase flag is set (if it is 1), the same bit of the index flag is also set (set to 1). Therefore, since the phase flags are set for the reels 410a, 410b, and 410c that are being processed, the corresponding bits of the index flags are set due to synthesis regardless of whether or not the index signal is acquired. Furthermore, when all index signals are acquired (all reels 410a, 410b, and 410c reach a steady rotational speed), all bits corresponding to each reel of the index flag will be set (00000111B) regardless of the phase flag. Become. Then, the SMC_ROT module is terminated by moving to the PRE_PLS module that executes excitation pattern update preprocessing (S3). In this way, it becomes possible to combine the phase flag with the index flag.

FIG. 192 is an explanatory diagram for explaining an example of a command for realizing the SMC_ROT module. The flowchart shown in FIG. 191 is realized, for example, by the program shown in FIG. 192.

The index “SMC_ROT:” in the first line of FIG. 192 indicates the start address of the SMC_ROT module. The command "LDQ HL, LOW _IDX_FND" on the second line reads the value of the Q register to the H register, and reads the value of the lower 1 byte of the address "_IDX_FND" to the L register. The command on the second line corresponds to step S1 in FIG. 191.

By the command "LD A, (HL)" on the third line in FIG. 192, the 1-byte value (index flag value) stored at the address indicated by the HL register is read into the A register. The command "OR A, C" on the fourth line calculates the logical sum of the value of the A register and the value of the C register, and the A register is updated with the result of the calculation. Then, the command "LD (HL), A" on the fifth line stores the value of the A register at the address indicated by the HL register. That is, the value of the A register is overwritten with the 1-byte value stored at the address indicated by the HL register, and the value of the index flag is updated. The commands on the third to fifth lines correspond to step S2 in FIG. 191.

The command "JP PRE_PLS" on the 6th line of FIG. 192 moves to the index "PRE_PLS:" indicating the start address of the PRE_PLS module. The command on the sixth line corresponds to step S3 in FIG. 191.

In this way, the total command size of the SMC_ROT module commands shown in Figure 192 is the command "LDQ HL, LOW _IDX_FND" on the second line, 2 bytes + the command "LD A, (HL)" on the third line, 1 byte + 4 lines. The second command “OR A, C” 1 byte + the 5th line command “LD (HL), A” 1 byte + the 6th line command “JP PRE_PLS” 3 bytes = 8 bytes, and the total execution cycle is as follows: 2 cycles + 2 cycles on the 3rd row + 1 cycle on the 4th row + 2 cycles on the 5th row + 3 cycles on the 6th row = 10 cycles. By providing the processing on the 3rd to 5th lines in the SMC_ROT module, it becomes possible to easily combine (logical OR) the index flag and phase flag stored as variables.

FIG. 193 is an explanatory diagram for explaining another example of commands for realizing the SMC_ROT module. Here, the command group of the SMC_ROT module in FIG. 192 is replaced with the command group of the SMC_ROT module in FIG. 193.

The index “SMC_ROT:” in the first line of FIG. 193 indicates the start address of the SMC_ROT module. The command "LDQ HL, LOW _IDX_FND" on the second line reads the value of the Q register to the H register, and reads the value of the lower 1 byte of the address "_IDX_FND" to the L register.

The command “OR (HL), C” on the third line in FIG. Store at the address indicated by the register. That is, the calculation result is overwritten on the 1-byte value stored at the address indicated by the HL register, and the value of the index flag is updated. The command on the third line corresponds to step S2 in FIG. 191.

The command "JP PRE_PLS" on the fourth line in FIG. 193 moves to the index "PRE_PLS:" indicating the start address of the PRE_PLS module. The command on the fourth line corresponds to step S3 in FIG. 191.

The total command size of the SMC_ROT module commands shown in FIG. JP PRE_PLS" 3 bytes = 7 bytes, and the total execution cycle is 2 cycles on the 2nd line + 5 cycles on the 3rd line + 3 cycles on the 4th line = 10 cycles. Therefore, compared to the case of FIG. 192, the total command size is reduced by 1 byte. With such an SMC_ROT module, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

In addition, as can be understood by comparing FIG. 192 and FIG. 193, the command group that occupied three lines (3rd to 5th lines) in FIG. ), which makes it possible to reduce the number of commands and reduce the design load.

Note that although the explanation has been given here using the command “OR (HL), C” that executes a logical sum, the command “AND (HL), C” that executes a logical product and the exclusive logic are not limited to such cases. Even the sum "XOR (HL), C" can be replaced in the same way as logical OR, and the total command size can be reduced by 1 byte. Furthermore, the register that stores the address of the variable is not limited to the HL register, but may be a DE register. Furthermore, the register to be subjected to the OR is not limited to the C register, but may also be an A register, a B register, a D register, an E register, an H register, or an L register.

Also, compared to the example in FIG. 192, the A register is not used here. Therefore, the value of the A register will not be updated unintentionally. Furthermore, in the example of FIG. 192, if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, there is no need for stack processing. In this way, resources can be used effectively.

<Command “LDF”>
FIG. 194 is a flowchart showing specific processing of the INITIAL module. Here, the built-in register area setting process, which is part of the INITIAL module that executes the CPU initialization process shown in step S2000 in FIG. 82, will be described as an arbitrary process. The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the description of the INITIAL module, the first register is the HL register.

The main CPU 500a executes arbitrary processing as shown in FIG. 194. The main CPU 500a first sets the start address of the CPU built-in register setting data table (data table) in the HL register (S1). Then, the main CPU 500a sets the number of setting data (S2).

Next, the main CPU 500a sets addresses and setting data of built-in registers accessible through the input/output unit in the C register and the A register, respectively (S3). Next, the value of the A register (setting data) is output to the built-in register indicated by the C register (S4). Next, the main CPU 500a decrements (subtracts by "1") the value of the B register (number of set data), and determines whether the decremented result is 0 (S5). Here, if the decremented result is not 0 (NO in S5), the process from step S3 is repeated, and if the decremented result is 0 (YES in S5), the process moves to the next process.

FIG. 195 is an explanatory diagram for explaining an example of a command for realizing an INITIAL module. Of these, FIG. 195(a) shows a command group of the INITIAL module, and FIG. 195(b) shows the arrangement of 1-byte data groups in the program data of the main ROM 500b. The flowchart shown in FIG. 194 is realized, for example, by the program shown in FIG. 195.

The index “INITIAL:” in the first line of FIG. 195(a) indicates the start address of the INITIAL module. The command "LD HL, T_CPU_REG" on the second line reads out the start address "T_CPU_REG" of the CPU built-in register setting data table to the HL register. The command on the second line corresponds to step S1 in FIG. 194. The command "LD B, @NUM_CPU_REG" on the third line reads the number of setting data stored in the address "@NUM_CPU_REG" to the B register. The command on the third line corresponds to step S2 in FIG. 194.

Note that, as can be understood with reference to the 22nd line of FIG. 195(b), the command "EQU ($-T_CPU_REG)/2" is written in the address "@NUM_CPU_REG". Here, "$" is the address next to the final address of the 1-byte data group that is the transfer source, that is, the address "@NUM_CPU_REG" itself, and "T_CPU_REG" is the first address of the 1-byte data group that is the transfer source. Therefore, the value of $-T_CPU_REG (1-byte value indicating the number of data) is the total number of bytes of the 1-byte value, and dividing that value by 2, which is the number of combinations of address and value, gives the number of setting data. is derived. For example, in the example of FIG. 195(b), the number of setting data is 20/2=10.

The index “INITIAL01:” in the fourth line of FIG. 195(a) indicates the start address of the repetitive process. The command "LDIN AC, (HL)" on the 5th line stores the value stored in the address indicated by the HL register in the C register, and then stores it in the address indicated by adding "1" to the HL register. The value is stored in the A register. The command on the fifth line corresponds to step S3 in FIG. 194. The command "OUT (C), A" on the sixth line outputs the value of the A register (setting data) to the value indicated by the C register (built-in register). The command on the sixth line corresponds to step S4 in FIG. 194.

For example, if the HL register has the value of the address "T_CPU_REG", the 1-byte value "@PT0PR___" in the second line of FIG. 195(b) is stored in the C register, and A value of "120" is stored in the A register. Then, the value of the A register, that is, the value of "120" is output to the value of the C register, that is, the address indicated by "@PT0PR__".

Next, the value of the B register is decremented (subtracted by 1) by the command "DJNZ INITIAL01" on the 7th line of FIG. , if the decremented result is 0, the process moves to the command next to the command in question. Here, the number of data is "10", so if the process from "INITIAL01" is repeated 10 times, the value of the B register becomes 0. The command on the seventh line corresponds to step S5 in FIG. 194.

In this way, the total command size of the INITIAL module commands shown in Figure 195(a) is 3 bytes for the command "LD HL, T_CPU_REG" on the second line + 2 bytes for the command "LD B, @NUM_CPU_REG" on the third line + 5 The command “LDIN AC, (HL)” on the 6th line 2 bytes + the command “OUT (C), A” on the 6th line 2 bytes + the command “DJNZ INITIAL01” on the 7th line 2 bytes = 11 bytes, and the total execution cycle is: 2nd row 3 cycles + 3rd row 2 cycles + 5th row 4 cycles + 6th row 3 cycles + 7th row 3 cycles (2 cycles) = 15 cycles (14 cycles). Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "DJNZ INITIAL01". Note that here, since the number of set data=10, the commands on the 5th to 7th lines will be repeated 10 times. Therefore, the actual total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + (4 cycles on the 5th line + 3 cycles on the 6th line + 3 cycles on the 7th line) x 9 loops + (4 cycles on the 5th line + 3 cycles on the 6th line) 3 cycles + 2 cycles on the 7th line) = 104 cycles. Such an INITIAL module allows configuration data to be set in internal registers.

FIG. 196 is an explanatory diagram for explaining another example of commands for implementing the INITIAL module. Here, the command group of the INITIAL module in FIG. 195(a) is replaced with the command group of the INITIAL module in FIG. 196(a), and the other 1-byte data in the program data of the main ROM 500b in FIG. 195(b) The group is used as is as shown in FIG. 196(b).

The index “INITIAL:” in the first line of FIG. 196(a) indicates the start address of the INITIAL module. The command "LDF HL, T_CPU_REG" on the second line reads out the start address "T_CPU_REG" of the CPU built-in register setting data table to the HL register. The command on the second line corresponds to step S1 in FIG. 194.

Here, the command "LDF HL, mn" is a command to store the value of "mn" in the HL register. The command size of such a command is "2" and the execution cycle is "2". On the other hand, the commonly used load command "LD HL, mn" is also a command that stores the value of "mn" in the HL register, but the command size of that command is "3" and the execution cycle is "3". It is. Therefore, if mn is in the range of 1200H to 1DFFH on the memory map and it is loaded into the HL register, by changing "LD" to "LDF", the command size is reduced by 1 byte and the execution The cycle is also reduced by one cycle.

In this way, the value of mn in the command "LDF HL, mn" must be one of 1200H to 1DFFH in the memory map. Therefore, in this embodiment, program data is placed in the range of 1200H to 1DFFH in the used area of the main ROM 500b, and the command "LDF HL, mn" is used only when reading data in this range. Note that the assembly code of "LDF HL, 1200H" is expressed as 6A00H, which is the addition of 5800H to the target address "1200H". Therefore, the assembly codes of "LDF HL, 1200H" to "LDF HL, 1DFFH" are 6A00H to 75FFH.

The number of setting data stored in the address "@NUM_CPU_REG" is read to the B register by the command "LD B, @NUM_CPU_REG" on the third line of FIG. 196(a). The command on the third line corresponds to step S2 in FIG. 194.

The index “INITIAL01:” in the fourth line of FIG. 196(a) indicates the start address of the repetitive process. The command "LDIN AC, (HL)" on the 5th line stores the value stored in the address indicated by the HL register in the C register, and then stores it in the address indicated by adding "1" to the HL register. The value is stored in the A register. The command on the fifth line corresponds to step S3 in FIG. 194. The command "OUT (C), A" on the sixth line outputs the value of the A register (setting data) to the value indicated by the C register (built-in register). The command on the sixth line corresponds to step S4 in FIG. 194.

Next, the value of the B register is decremented (subtracted by 1) by the command "DJNZ INITIAL01" on the 7th line of FIG. , if the decremented result is 0, the process moves to the command next to the command in question. Here, the number of data is "10", so if the process from "INITIAL01" is repeated 10 times, the value of the B register becomes 0. The command on the seventh line corresponds to step S5 in FIG. 194.

In this way, the total command size of the INITIAL module commands shown in FIG. 196(a) is 2 bytes of the command "LDF HL, T_CPU_REG" in the second line + 2 bytes of the command "LD B, @NUM_CPU_REG" in the third line + 5 2 bytes of the command “LDIN AC, (HL)” on the 6th line + 2 bytes of the command “OUT (C), A” on the 7th line + 2 bytes of the command “DJNZ INITIAL01” on the 7th line = 10 bytes, and the total execution cycle is: 2 cycles on the 2nd row + 2 cycles on the 3rd row + 4 cycles on the 5th row + 3 cycles on the 6th row + 3 cycles on the 7th row (2 cycles) = 14 cycles (13 cycles). Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "DJNZ INITIAL01". Note that here, since the number of set data=10, the commands on the 5th to 7th lines will be repeated 10 times. Therefore, the actual total execution cycle is 2 cycles on the 2nd line + 2 cycles on the 3rd line + (4 cycles on the 5th line + 3 cycles on the 6th line + 3 cycles on the 7th line) x 9 loops + (4 cycles on the 5th line + 4 cycles on the 6th line) 3 cycles + 2 cycles on the 7th line) = 103 cycles. Therefore, it can be seen that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle compared to the case of FIG. 195(a). By using such an INITIAL module, it is possible to further shorten the command, reduce the processing load, and secure the capacity of the control area for performing game control processing.

In the above embodiment, the INITIAL module is used, and in the process of setting configuration data in the internal register, the command "LD HL, T_CPU_REG" is replaced with the command "LDF HL, T_CPU_REG", thereby further shortening the command, and , an example was given to reduce the processing load. However, such commands are applicable not only to the INITIAL module but also to various modules.

For example, in the DGEXTRN module that executes display data conversion processing, the command "LD HL, T_SEG_PTN" also exists, and like the INITIAL module, the start address "T_SEG_PTN" of the main display display pattern data table is read out to the HL register. There is. Further, the start address "T_SEG_PTN" is included in the range of 1200H to 1DFFH. Therefore, in the DGEXTRN module as well, by changing the command "LD HL, T_SEG_PTN" to the command "LDF HL, T_SEG_PTN", it is possible to further shorten the command and reduce the processing load.

Also, in the GET_ARY module that executes the symbol array data acquisition process, the command "LD HL, T_FIG_LIN" exists, and like the INITIAL module, the start address "T_FIG_LIN" of the symbol array offset table for each valid line is read to the HL register. ing. Further, the start address "T_FIG_LIN" is included in the range of 1200H to 1DFFH. Therefore, in the GET_ARY module as well, by changing the command "LD HL, T_FIG_LIN" to the command "LDF HL, T_FIG_LIN", it is possible to further shorten the command and reduce the processing load.

In this way, by keeping the transfer source address within the range of 1200H to 1DFFH, most commands "LD HL, mn" can be replaced with the command "LDF HL, mn". By applying such replacement to all processes in this embodiment, it is possible to reduce the total command size by, for example, 80 to 90 bytes.

Such a command "LDF" can be employed not only in the above-mentioned INITIAL module but also in various modules, such as the RANKSET module. Further, the present invention can be adopted not only for slot machines but also for example, a PWRFAIL module or a DYM_OUT module in a pachinko machine.

FIG. 197 is an explanatory diagram for explaining the RANKSET module. The RANKSET module shown in step S2020 in FIG. 85 performs setting value switching processing, that is, switching setting values and updating setting value data. Here, the data table setting process at the time of setting value switching in step S2020-5 in the RANKSET module will be explained.

The index “RANKSET:” in the first line of FIG. 197(a) indicates the start address of the RANKSET module. By the command "LD HL, T_RNK_SET" on the second line, the start address "T_RNK_SET" of the data table at the time of setting value switching is read into the HL register. The command "RST TABLSET" on the third line calls the TABLSET module described using FIG. 138 as a subroutine. Since such a TABLSET module has already been explained, detailed explanation thereof will be omitted here. Here, two variables (_WIN_DAT, _EXT_REQ) in the setting value switching data table are set to predetermined values.

Here, by replacing the command with "LDF", the command group in FIG. 197(a) can be changed as shown in FIG. 197(b). The index “RANKSET:” in the first line of FIG. 197(b) indicates the start address of the RANKSET module. The command "LDF HL, T_RNK_SET" on the second line reads the start address "T_RNK_SET" of the data table at the time of setting value switching to the HL register. Note that the start address "T_RNK_SET" of the data table at the time of setting value switching is arranged in the range of 1200H to 1DFFH in the used area of the main ROM 500b. The command "RST TABLSET" on the third line calls the TABLSET module described using FIG. 138 as a subroutine. In this way, as in FIG. 197(a), the two variables (_WIN_DAT, _EXT_REQ) in the setting value switching data table are set to predetermined values.

Here, the total command size of the RANKSET module commands shown in FIG. 197(a) is 3 bytes for the command "LD HL, T_RNK_SET" on the second line + 1 byte for the command "RST TABLSET" on the third line = 4 bytes. The total execution cycle is 3 cycles on the second line + 4 cycles on the third line = 7 cycles. On the other hand, the total command size of the RANKSET module commands shown in Figure 197(b) is 2 bytes for the command "LDF HL, T_RNK_SET" on the second line + 1 byte for the command "RST TABLSET" on the third line = 3 bytes. The execution cycle is 2 cycles on the second line + 4 cycles on the third line = 6 cycles. Therefore, it can be seen that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle compared to the case of FIG. 197(a). By using such a RANKSET module, it is possible to further shorten the command, reduce the processing load, and secure the capacity of the control area for performing game control processing.

FIG. 198 is an explanatory diagram for explaining the PWRFAIL module. The PWRFAIL module shown in step S300 of FIG. 25 performs power-off saving processing, that is, switches setting values and updates setting value data. Note that the output port clearing process in step S300-11 in the PWRFAIL module will be explained here.

Here, it is assumed that 00H is set in advance in the A register as the initial value of the output port. The index "PWRFAIL:" in the first line of FIG. 198(a) indicates the start address of the PWRFAIL module. The command "LD HL, D_OUT_PRT" on the second line reads the first address "D_OUT_PRT" of the output port address table into the HL register. By the command "LD B, @PRT_CLR_LOP" on the third line, the output port initialization loop counter value (13 in this case) stored at the address "@PRT_CLR_LOP" is read into the B register as the loop count.

The index "PWRFAIL_20:" in the fourth line of FIG. 198(a) indicates the start address of the repeat process. The command "LD C, (HL)" on the fifth line reads the value (output port address) stored at the address indicated by the HL register into the C register. The command "OUT (C), A" on the sixth line outputs the value of the A register (here, 00H) to the value indicated by the C register (internal register), and clears the output port.

Subsequently, the value of the HL register is incremented by 1 by the command "INC HL" on the 7th line of FIG. 198(a). The command "DJNZ PWRFAIL_20" on the 8th line decrements the value of the B register (subtracts "1"), and if the decremented result is not 0, moves to the address "PWRFAIL_20", and if the decremented result is 0, , transfers processing to the command following the command. Here, the number of data is "13", so if the process from "PWRFAIL_20" is repeated 13 times, the value of the B register becomes 0. The output port is thus cleared.

Here, by replacing the command with "LDF", the command group in FIG. 198(a) can be changed as shown in FIG. 198(b). Here again, it is assumed that 00H is set in advance in the A register as the initial value of the output port. The index “PWRFAIL:” in the first line of FIG. 198(b) indicates the start address of the PWRFAIL module. The command "LDF HL, D_OUT_PRT" on the second line reads the first address "D_OUT_PRT" of the output port address table into the HL register. Note that the first address "D_OUT_PRT" of the output port address table is placed in the range of 1200H to 1DFFH in the used area of the main ROM 500b. By the command "LD B, @PRT_CLR_LOP" on the third line, the output port initialization loop counter value (13 in this case) stored at the address "@PRT_CLR_LOP" is read into the B register as the loop count.

The index "PWRFAIL_20:" in the fourth line of FIG. 198(b) indicates the start address of the repetitive process. The command "LD C, (HL)" on the fifth line reads the value (output port address) stored at the address indicated by the HL register into the C register. The command "OUT (C), A" on the sixth line outputs the value of the A register (here, 00H) to the value indicated by the C register (built-in register), and clears the output port.

Subsequently, the value of the HL register is incremented by 1 by the command "INC HL" on the 7th line of FIG. 198(b). The command "DJNZ PWRFAIL_20" on the 8th line decrements the value of the B register (subtracts "1"), and if the decremented result is not 0, moves to the address "PWRFAIL_20", and if the decremented result is 0, , transfers processing to the command following the command. Here, the number of data is "13", so if the process from "PWRFAIL_20" is repeated 13 times, the value of the B register becomes 0. The output port is thus cleared.

Here, the total command size of the PWRFAIL module commands shown in Figure 198(a) is 3 bytes for the command "LD HL, D_OUT_PRT" on the second line + 2 bytes for the command "LD B, @PRT_CLR_LOP" on the third line + 5 lines. 1st command “LD C, (HL)” 1 byte + 6th line command “OUT (C), A” 2 bytes + 7th line command “INC HL” 1 byte + 8th line command “DJNZ PWRFAIL_20” 2 bytes = 11 bytes, and the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 2 cycles on the 5th line + 3 cycles on the 6th line + 1 cycle on the 7th line + 3 cycles (2 cycles) on the 8th line = 14 cycles (13 cycles) ). Note that here, since the output port initialization loop counter value=13, the commands on the 5th to 8th lines will be repeated 13 times. Therefore, the actual total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + (2 cycles on the 5th line + 3 cycles on the 6th line + 1 cycle on the 7th line + 3 cycles on the 8th line) x 12 loops + (3 cycles on the 5th line) 2 cycles + 3 cycles on the 6th line + 1 cycle on the 7th line + 2 cycles on the 8th line) = 121 cycles.

On the other hand, the total command size of the PWRFAIL module commands shown in Figure 198(b) is: 2 bytes of the command "LDF HL, D_OUT_PRT" on the 2nd line + 2 bytes of the command "LD B, @PRT_CLR_LOP" on the 3rd line + 2 bytes of the command "LDB, @PRT_CLR_LOP" on the 5th line Command “LD C, (HL)” 1 byte + 6th line command “OUT (C), A” 2 bytes + 7th line command “INC HL” 1 byte + 8th line command “DJNZ PWRFAIL_20” 2 bytes = The total execution cycle is 10 bytes, and the total execution cycle is 2 cycles on the 2nd line + 2 cycles on the 3rd line + 2 cycles on the 5th line + 3 cycles on the 6th line + 1 cycle on the 7th line + 3 cycles on the 8th line (2 cycles) = 13 cycles (12 cycles) becomes. Note that here, since the output port initialization loop counter value=13, the commands on the 5th to 8th lines will be repeated 13 times. Therefore, the actual total execution cycle is 2 cycles on the 2nd line + 2 cycles on the 3rd line + (2 cycles on the 5th line + 3 cycles on the 6th line + 1 cycle on the 7th line + 3 cycles on the 8th line) x 12 loops + (5th line 2 cycles + 3 cycles on the 6th line + 1 cycle on the 7th line + 2 cycles on the 8th line) = 120 cycles. Therefore, it can be seen that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle compared to the case of FIG. 198(a). With such a PWRFAIL module, it is possible to further shorten the command, reduce the processing load, and secure the capacity of the control area for performing game control processing.

FIG. 199 is an explanatory diagram for explaining the DYM_OUT module. The DYM_OUT module shown in step S400-5 in FIG. Dynamic port output processing is executed to control the lighting of the display 168, the normal symbol hold display 170, the right hit notification display 172, and the performance display monitor 184.

The index “DYM_OUT:” in the first line of FIG. 199(a) indicates the start address of the DYM_OUT module. The command "LD HL, D_DYM_SEL" on the second line reads the start address "D_DYM_SEL" of the dynamic display selection table into the HL register. The command "RST WORDSEL" on the third line calls the WORDSEL module described using FIGS. 127 to 130 as a subroutine. Since such a WORDSEL module has already been explained, detailed explanation thereof will be omitted here. In this way, four pieces of 2-byte data in the dynamic display selection table are selected.

Here, by replacing the command with "LDF", the command group in FIG. 199(a) can be changed as shown in FIG. 199(b). The index “DYM_OUT:” in the first line of FIG. 199(b) indicates the start address of the DYM_OUT module. The command "LDF HL, D_DYM_SEL" on the second line reads the start address "D_DYM_SEL" of the dynamic display selection table to the HL register. Note that the start address "D_DYM_SEL" of the dynamic display selection table is placed in the range of 1200H to 1DFFH in the used area of the main ROM 500b. The command "RST WORDSEL" on the third line calls the WORDSEL module described using FIGS. 127 to 130 as a subroutine. In this way, four pieces of 2-byte data in the dynamic display selection table are selected.

Here, the total command size of the DYM_OUT module commands shown in FIG. 199(a) is 3 bytes for the command "LD HL, D_DYM_SEL" on the second line + 1 byte for the command "RST WORDSEL" on the third line = 4 bytes. The total execution cycle is 3 cycles on the second line + 4 cycles on the third line = 7 cycles. On the other hand, the total command size of the DYM_OUT module commands shown in Figure 199(b) is 2 bytes for the command "LDF HL, D_DYM_SEL" on the second line + 1 byte for the command "RST WORDSEL" on the third line = 3 bytes. The execution cycle is 2 cycles on the second line + 4 cycles on the third line = 6 cycles. Therefore, it can be seen that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle compared to the case of FIG. 199(a). With such a DYM_OUT module, it is possible to further shorten the command, reduce the processing load, and secure the capacity of the control area for performing game control processing.

<Command “SET”>
FIG. 200 is a flowchart showing specific processing of the IPT_PD module. Here, as an arbitrary process, in the CAL_MOD module for executing the state-specific module execution process shown in step S3100-21 in FIG. The process of setting the external signal 4, which is part of the IPT_PD module that selectively transitions (every 5.96 msec) and executes the external signal output control process, will be described. The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the description of the IPT_PD module, the predetermined register is the HL register.

The main CPU 500a executes arbitrary processing as shown in FIG. 200. The main CPU 500a first performs a subtraction process on a counter related to an external signal output holding timer (S1). Then, the main CPU 500a sets the address of the output port 3 image in the HL register (S2). Next, the main CPU 500a determines whether or not the security signal ON condition is satisfied by the subtraction process in step S1. If the ON condition is satisfied, the main CPU 500a selects the external signal 4, that is, the predetermined value of the address indicated by the HL register. Set the bit (set to 1) (S3). Then, the IPT_PD module is terminated and the routine returns to the next step higher (S4). In this way, it becomes possible to set the external signal 4.

FIG. 201 is an explanatory diagram for explaining an example of a command for realizing the IPT_PD module. The flowchart shown in FIG. 200 is realized, for example, by the program shown in FIG. 201.

The index “IPT_PD:” in the first line of FIG. 201 indicates the start address of the IPT_PD module. The command "RST RAM_DEC" on the second line is a command that calls a general-purpose module that decrements a variable by 1, and this command subtracts the counter related to the external signal output holding timer. Here, at least the zero flag is updated by the command "RST RAM_DEC". The command on the second line corresponds to step S1 in FIG. 200. The command "LDQ HL, LOW _OUT_PT3" on the third line reads the value of the Q register to the H register, and reads the value of the lower 1 byte of the address "_OUT_PT3" to the L register. The zero flag does not change depending on the command "LDQ HL, LOW_OUT_PT3". The command on the third line corresponds to step S2 in FIG. 200.

The command "JR Z, IPT_PD03" on the 4th line of FIG. 201 determines whether the subtraction result of the command "RST RAM_DEC" on the 2nd line is zero, and if it is zero (if the zero flag is set) That is, if the security signal ON condition is not satisfied, the index moves to the sixth line "IPT_PD03:", and if it is not zero (if the zero flag is not set), the next process is performed. The command "SET @EXT_SG4_POS, (HL)" on the fifth line sets the value defined by @EXT_SG4_POS (here, 2) in the output port 3 image, that is, the value stored at the address indicated by the HL register. Make the bit stand up. The index “IPT_PD03:” on the sixth line indicates the destination of the command “JR Z, IPT_PD03” on the fourth line. The commands on the 4th to 6th lines correspond to step S3 in FIG. 200. Then, the command "RET" on the 7th line in FIG. 201 returns to the routine one stage higher. The command on the seventh line corresponds to step S4 in FIG. 200.

In this way, the total command size of the IPT_PD module commands shown in Figure 201 is: 1 byte of the command "RST RAM_DEC" on the 2nd line + 2 bytes of the command "LDQ HL, LOW_OUT_PT3" on the 3rd line + 2 bytes of the command "LDQ HL, LOW_OUT_PT3" on the 4th line JR Z, IPT_PD03" 2 bytes + 5th line command "SET @EXT_SG4_POS, (HL)" 2 bytes + 7th line command "RET" 1 byte = 8 bytes, and the total execution cycle is the command "JR Z, IPT_PD03" If it is not moved by the command "JR Z, IPT_PD03", 4 cycles for the 2nd line + 2 cycles for the 3rd line + 2 cycles for the 4th line + 5 cycles for the 5th line + 3 cycles for the 7th line = 16 cycles, and if it is moved by the command "JR Z, IPT_PD03", 2 4 cycles on the row + 2 cycles on the 3rd row + 3 cycles on the 4th row + 3 cycles on the 7th row = 12 cycles. By providing the processing on the 4th to 6th lines in the IPT_PD module, it becomes possible to perform bit manipulation of the output port 3 image according to the subtraction result.

FIG. 202 is an explanatory diagram for explaining another example of commands for implementing the IPT_PD module. Here, the command group of the IPT_PD module in FIG. 201 is replaced with the command group of the IPT_PD module in FIG. 202.

The index “IPT_PD:” in the first line of FIG. 202 indicates the start address of the IPT_PD module. The command "RST RAM_DEC" on the second line is a command that calls a general-purpose module that decrements a variable by 1, and this command subtracts the counter related to the external signal output holding timer. Here, at least the zero flag is updated by the command "RST RAM_DEC". The command on the second line corresponds to step S1 in FIG. 200. The command "LDQ HL, LOW _OUT_PT3" on the third line reads the value of the Q register to the H register, and reads the value of the lower 1 byte of the address "_OUT_PT3" to the L register. The zero flag does not change depending on the command "LDQ HL, LOW_OUT_PT3". The command on the third line corresponds to step S2 in FIG. 200.

The command "SET NZ, @EXT_SG4_POS, (HL)" on the fourth line of FIG. If the signal ON condition is satisfied, the bit of the value defined by @EXT_SG4_POS (here, 2) in the output port 3 image, that is, the value of the address indicated by the HL register, is set. The command on the fourth line corresponds to step S3 in FIG. 200. Then, the command "RET" on the fifth line in FIG. 202 returns to the routine one level higher. The command on the fifth line corresponds to step S4 in FIG. 200.

Here, the command "SET cc, b, (HL)" sets the bth bit of the value (variable) at the address indicated by the HL register if the flag corresponding to cc (zero flag or carry flag) is true. It is a command. The command size of such a command is "2" and the execution cycle is "5" ("2"). Note that the number of cycles in parentheses indicates the execution cycle when the flag is not true in the command "SET cc, b, (HL)".

In this way, the total command size of the IPT_PD module commands shown in FIG. SET NZ, @EXT_SG4_POS, (HL)" 2 bytes + 5th line command "RET" 1 byte = 6 bytes, and the total execution cycle is 4 cycles on the 2nd line + 2 cycles on the 3rd line + 5 cycles on the 4th line (2 cycles ) + 3 cycles on the 5th line = 14 cycles (11 cycles). Therefore, compared to the case of FIG. 201, the total command size is reduced by 2 bytes, and the total execution cycle is reduced by at least 1 cycle. With such an IPT_PD module, it is possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing game control processing.

Also, in order to understand by comparing FIG. 201 and FIG. 202, the command group that occupied three lines (4th to 6th lines) in FIG. ), which makes it possible to reduce the number of commands and reduce the design load.

Note that although the command "SET cc, b, (HL)" for setting bits has been described here, the command "SET cc, b, r" for setting bits may also be used. can. Here, the command "SET cc, b, r" sets r (A register, B register, D register, E register, H register, L register) if the flag corresponding to cc (zero flag or carry flag) is true. ) is a command to set the b-th bit of the value. The command size of such a command is "2" and the execution cycle is "2".

Such a command "SET" can be employed not only in the above-mentioned IPT_PD module but also in various modules such as the DYNMOUT module. Furthermore, the present invention can be adopted not only for slot machines but also for pachinko machines, such as EXT_PRC modules.

FIG. 203 is an explanatory diagram for explaining the DYNMOUT module. In the DYNMOUT module shown in step S3100-7 in FIG. 98, the main CPU 500a outputs the set output image to the output port, and displays the main credit display section 430, main payout display section 432, input number of coins display, and start display. , a dynamic port output process (dynamic lighting control process) that controls the lighting of the indicators of the stop switches 420a, 420b, and 420c, the replay indicator, and the section indicator 460 is executed.

The index “DYNMOUT:” in the first line of FIG. 203(a) indicates the start address of the DYNMOUT module. The command "RESQ @CHN_DSP_BIT, (LOW _WIN_DAT+1)" on the second line sets the value of the Q register as the upper 1 byte of the address, and sets the value obtained by adding 1 to the lower 1 byte of the address "_WIN_DAT" as the lower 1 byte of the address. , sets (resets) the bit (bit 7 here) indicated by @CHN_DSP_BIT in the value stored at that address (main display data buffer 2) to 0. The command "LDQ A, (LOW_OUT_PT2)" on the third line sets the value of the Q register as the upper 1 byte of the address, and the value of the lower 1 byte of the address "_OUT_PT2" as the lower 1 byte of the address, and stores it at that address. Read the value (output port 2 image) to the A register. By the command "JAND Z, A, 00000011B, DYNMOUT02" on the 4th line, if the AND of the value of the A register and 00000011B is zero, move to the address "DYNMOUT02", and if it is not zero, the command on the 5th line process. The command "SETQ @CHN_DSP_BIT, (LOW _WIN_DAT+1)" on the fifth line sets the value of the Q register as the upper 1 byte of the address, and sets the value obtained by adding 1 to the lower 1 byte of the address "_WIN_DAT" as the lower 1 byte of the address. , sets (sets) the bit (here, bit 7) indicated by @CHN_DSP_BIT of the value stored at that address (main display data buffer 2) to 1. The index “DYNMOUT02:” on the sixth line indicates the destination of the command “JAND Z, A, 00000011B, DYNMOUT02” on the fourth line. In this way, it is possible to set bit 7 of main display data buffer 2 according to the value of the lower two bits of the output port 2 image.

Here, by replacing the command with "SET", the command group in FIG. 203(a) can be changed as shown in FIG. 203(b). The index “DYNMOUT:” in the first line of FIG. 203(b) indicates the start address of the DYNMOUT module. The command "LDQ HL, LOW _WIN_DAT+1" on the second line reads the value of the Q register to the H register, and reads the value obtained by adding 1 to the value of the lower 1 byte of the address "_WIN_DAT" to the L register. The command "RES @CHN_DSP_BIT, (HL)" on the third line sets 0 (resets) the bit indicated by @CHN_DSP_BIT (bit 7 here) in the value stored at the address indicated by the HL register. The command "LDQ A, (LOW_OUT_PT2)" on the fourth line sets the value of the Q register as the upper 1 byte of the address, sets the value of the lower 1 byte of the address "_OUT_PT2" as the lower 1 byte of the address, and stores it at that address. Read the value (output port 2 image) to the A register. The command "AND A, 00000011B" on the fifth line calculates the AND of the value of the A register and 00000011B, and masks the A register. By the command "SET NZ, @CHN_DSP_BIT, (HL)" on the 6th line, if the operation result of the command "AND A, 00000011B" on the 5th line is not zero (if the zero flag is not set), the HL register indicates The bit (here, bit 7) indicated by @CHN_DSP_BIT in the address value (main display data buffer 2) is set to 1. In this way, as in FIG. 203(a), it is possible to set bit 7 of main display data buffer 2 according to the value of the lower two bits of the output port 2 image.

Here, the total command size of the DYNMOUT module commands shown in FIG. 203(a) is 3 bytes of the command "RESQ @CHN_DSP_BIT, (LOW _WIN_DAT+1)" on the second line + the command "LDQ A, (LOW _OUT_PT2)" on the third line. )" 2 bytes + 4th line command "JAND Z, A, 00000011B, DYNMOUT02" 3 bytes + 5th line command "SETQ @CHN_DSP_BIT, (LOW _WIN_DAT+1)" 3 bytes = 11 bytes, and the total execution cycle is If the lower 2 bits of the 2nd image are not 0, 6 cycles of the 2nd row + 3 cycles of the 3rd row + 3 cycles of the 4th row + 6 cycles of the 5th row = 18 cycles, and the lower 2 bits of the output port 2 image are both 0. In this case, 6 cycles on the 2nd line + 3 cycles on the 3rd line + 4 cycles on the 4th line = 13 cycles.

On the other hand, the total command size of the DYNMOUT module commands shown in Figure 203(b) is 2 bytes for the command "LDQ HL, LOW _WIN_DAT+1" on the second line + 2 bytes for the command "RES @CHN_DSP_BIT, (HL)" on the third line. + 4th line command “LDQ A, (LOW _OUT_PT2)” 2 bytes + 5th line command “AND A, 00000011B” 2 bytes + 6th line command “SET NZ, @CHN_DSP_BIT, (HL)” 2 bytes = 10 bytes Therefore, if the lower two bits of the output port 2 image are not 0, the total execution cycle is 2 cycles on the 2nd line + 5 cycles on the 3rd line + 3 cycles on the 4th line + 2 cycles on the 5th line + 5 cycles on the 6th line = 17 cycles, When the lower two bits of the output port 2 image are both 0, 2 cycles on the 2nd row + 5 cycles on the 3rd row + 3 cycles on the 4th row + 2 cycles on the 5th row + 2 cycles on the 6th row = 14 cycles. Therefore, it can be seen that the total command size is reduced by 1 byte compared to the case of FIG. 203(a). With such a DYNMOUT module, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

FIG. 204 is an explanatory diagram for explaining the EXT_PRC module. In the EXT_PRC module shown in step S400-29 in FIG. 26, the main CPU 500a performs external information management processing, that is, sets output data for external information to be output from the game information output terminal board 312 to the outside.

The index “EXT_PRC:” in the first line of FIG. 204(a) indicates the start address of the EXT_PRC module. The command "LD BC, @D_SEC_LOP*256+0" on the second line sets @D_SEC_LOP (here 8), which is the number of rams to be checked (loop count), in the B register, and sets it in the C register as the initial value of the composite bit data. 0 is set. The command "JR Z, EXT_PRC_15" on the third line determines whether the AND of the target ram addresses calculated before executing that command is zero, and if it is zero (if the zero flag is set) ), moves to the index "EXT_PRC_15:" on the 5th line, and if it is not zero (unless the zero flag is set), performs the process on the 4th line. The command "SET @EXT_SEC_POS, C" on the fourth line sets the bit of the value defined by @EXT_SEC_POS (here, bit 6) of the value of the C register (synthetic bit data). The index “EXT_PRC_15:” on the fifth line indicates the destination of the command “JR Z, EXT_PRC_15” on the third line. In this way, it is possible to set bit 6 of the composite bit data in accordance with the result of the AND operation of the target RAM addresses.

Here, by replacing the command with "SET", the command group in FIG. 204(a) can be changed as shown in FIG. 204(b). The index “EXT_PRC:” in the first line of FIG. 204(b) indicates the start address of the EXT_PRC module. The command "LD BC, @D_SEC_LOP*256+0" on the second line sets @D_SEC_LOP (here 8), which is the number of rams to be checked (loop count), in the B register, and sets it in the C register as the initial value of the composite bit data. 0 is set. The command "SET NZ, @EXT_SEC_POS, C" on the third line determines whether the AND of the target ram addresses calculated before the command is executed is zero, and if it is not zero (if the zero flag is If it is not set), the bit of the value defined by @EXT_SEC_POS (here, bit 6) of the value of the C register (synthetic bit data) is set. In this way, as in FIG. 204(a), it is possible to set bit 6 of the composite bit data according to the result of the AND operation of the target RAM addresses.

Here, the total command size of the EXT_PRC module commands shown in Figure 204(a) is 2 bytes for the command "LD BC, @D_SEC_LOP*256+0" on the second line + 2 bytes for the command "JR Z, EXT_PRC_15" on the third line. +4th line command “SET @EXT_SEC_POS,C” 2 bytes = 6 bytes, and if the AND is not 0, the total execution cycle is 2 cycles on the 2nd line + 2 cycles on the 3rd line + 2 cycles on the 4th line = 6 cycles , if the logical product is 0, 2 cycles on the 2nd line + 3 cycles on the 3rd line = 5 cycles.

On the other hand, the total command size of the EXT_PRC module commands shown in FIG. 204(b) is the command "LD BC, @D_SEC_LOP*256+0" on the second line, 2 bytes + the command "SET NZ, @EXT_SEC_POS, C" on the third line. 2 bytes = 4 bytes, and the total execution cycle is 2 cycles for the 2nd line + 5 cycles for the 3rd line = 7 cycles if the AND is not 0, and 2 cycles for the 2nd line + 3 cycles if the AND is 0. 2nd cycle = 4th cycle. Therefore, it can be seen that the total command size is reduced by 2 bytes compared to the case of FIG. 204(a). With such an EXT_PRC module, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

<Command "JANDQ">
FIG. 205 is a flowchart showing specific processing of the STOPDCT module. Here, as an optional process, a process S2500-23 for checking the stop indicator, which is a part of the STOPDCT module that executes the rotating drum rotating process shown in step S2500 in FIG. 92, will be described. The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the description of the STOPDCT module, the predetermined register is the HL register.

The main CPU 500a executes arbitrary processing as shown in FIG. 205. The main CPU 500a first performs extraction processing of operation target bits (S1). Through this processing, the bit to be manipulated is set in the A register. Then, the main CPU 500a combines the operation target bit of the A register with the rotating flag set in advance in the D register (S2). Next, the main CPU 500a checks the stop indicator by performing a logical product with the value of the address indicating the stop indicator (S3), and if the stop indicator is lit in red (YES in S4), the corresponding STOPDCT The process is repeated from the beginning of the module, and if the stop indicator is not lit in red (NO in S4), the next process is executed. Then, by moving to the STP_REL module that executes rotation stop processing, the STOPDCT module ends (S5). In this way, it becomes possible to perform pressing processing according to the state of the stop indicator.

FIG. 206 is an explanatory diagram for explaining an example of a command for implementing the STOPDCT module. The flowchart shown in FIG. 205 is realized, for example, by the program shown in FIG. 206.

The index “STOPDCT:” in the first line of FIG. 206 indicates the start address of the STOPDCT module. The command "CALLF SMPLBIT" on the second line is a command that calls the SMPLBIT module that executes operation target bit extraction processing, and the bit corresponding to the stop switch that is the operation target (actually operated) by this command is A. Set in register. The command on the second line corresponds to step S1 in FIG. 205. The command "AND A, D" on the third line calculates the AND of the A register in which the operation target bit is set and the D register in which the rotation flag is set in advance, and stores the result in the A register. to hold. The command on the third line corresponds to step S2 in FIG. 205.

The command "ANDQ A, (LOW _OUT_PT4)" on the fourth line in FIG. The value of the display device) is ANDed with the value of the A register, and the result is held in the A register. The command on the fourth line corresponds to step S3 in FIG. 205. The command "JR Z, STOPDCT" on the 5th line determines whether the operation result of the command "ANDQ A, (LOW_OUT_PT4)" on the 4th line is zero, and if it is zero (if the zero flag is set) (e.g.), moves to the index "STOPDCT:" (second predetermined value) in the first line, and if it is not zero (if the zero flag is not set), the next process is performed. The command on the fifth line corresponds to step S4 in FIG. 205.

In this way, the total command size of the STOPDCT module commands shown in Figure 206 is: 2 bytes of the command "CALLF SMPLBIT" on the 2nd line + 1 byte of the command "AND A, D" on the 3rd line + 1 byte of the command "ANDQ" on the 4th line. A, (LOW _OUT_PT4)" 3 bytes + 5th line command "JR Z, STOPDCT" 2 bytes = 8 bytes, and the total execution cycle is 2nd line 4 cycles + 3rd line 1 cycle + 4th line 4 cycles + 5th line 3 cycles (2 cycles) = 12 cycles (11 cycles). Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "JR Z, STOPDCT". By providing the processes on the fourth and fifth lines in such a STOPDCT module, it becomes possible to perform press processing according to the state of the stop indicator.

FIG. 207 is an explanatory diagram for explaining another example of commands for realizing the STOPDCT module. Here, the command group of the STOPDCT module in FIG. 206 is replaced with the command group of the STOPDCT module in FIG. 207.

The index “STOPDCT:” in the first line of FIG. 207 indicates the start address of the STOPDCT module. The command "CALLF SMPLBIT" on the second line is a command that calls the SMPLBIT module that executes the operation target bit extraction process, and the bit corresponding to the stop switch that is the operation target is set in the A register by this command. The command on the second line corresponds to step S1 in FIG. 205. The command "AND A, D" on the third line calculates the AND of the A register in which the operation target bit is set and the D register in which the rotation flag is set in advance, and stores the result in the A register. to hold. The command on the third line corresponds to step S2 in FIG. 205.

The command "JANDQ Z, A, (LOW _OUT_PT4), STOPDCT" on the 4th line of FIG. The logical product of the value (stop indicator value) and the value of the A register is calculated, and it is determined whether or not the result is zero. If it is zero (if the zero flag is set), the first line index "STOPDCT:" (second predetermined value), and if it is not zero (if the zero flag is not set), the next process is performed. The command on the fourth line corresponds to steps S3 and S4 in FIG. 205.

Here, the command "JANDQ cc, A, (k), e" has the value of the Q register as the upper 1 byte and the value of the address indicated by k as the lower 1 byte (first predetermined value), The logical product of the values in the A register is calculated, and if the flag corresponding to cc (zero flag or carry flag) is true, move to the address indicated by e (second predetermined value) and move to cc. This is a command that moves to the next process if the corresponding flag is not true. The command size of such a command is "4" and the execution cycle is "6" ("5"). Note that the number of cycles in parentheses indicates the execution cycle when the flag is not true in the command "JANDQ cc, A, (k), e".

The total command size of the STOPDCT module commands shown in FIG. (LOW_OUT_PT4), STOPDCT" 4 bytes = 7 bytes, and the total execution cycle is 4 cycles on the 2nd line + 1 cycle on the 3rd line + 6 cycles (5 cycles) on the 4th line = 11 cycles (10 cycles). Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "JANDQ Z, A, (LOW_OUT_PT4), STOPDCT". Therefore, compared to the case of FIG. 206, the total command size is reduced by 1 byte, and the total execution cycle is reduced by at least 1 cycle. With such a STOPDCT module, it is possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing game control processing.

Also, in order to understand by comparing FIG. 206 and FIG. 207, the command group that occupied two lines (fourth and fifth lines) in FIG. ), which makes it possible to reduce the number of commands and reduce the design load.

<Command “CALLEX”>
The E_SETTM module is the ERRWAIT module that executes the error wait process shown in step S2200-11 in FIG. 89 and step S2800-39 in FIG. This is a module for Note that the E_SETTM module is arranged in a separate area (2000H to 3FBFH) of the main ROM 500b.

The main CPU 500a reads the program in the used area from the main ROM 500b, executes the read program, calls the E_SETTM module in another area as a subroutine in any process, and executes the E_SETTM module. The E_SETTM module sets the input abnormality non-monitoring timer.

FIG. 208 is a flowchart showing specific processing of the E_SETTM module. Here, we will list some of the optional processes in the ERRWAIT module that executes the error wait process shown in step S2200-11 in FIG. 89 and step S2800-39 in FIG. 95, and the BLKSHUT module that executes blocker blockage processing. explain. The numerical values of step S in this figure will be used only in the explanation of this figure.

The main CPU 500a executes arbitrary processing as shown in FIG. 208(a). The main CPU 500a checks the blocker status, and if bit 3 (blocker solenoid output bit number) of the output port 4 image is not 0, calls the E_SETTM module in another area. Therefore, the main CPU 500a first prohibits interrupts (S1), and calls the E_SETTM module in another area as a subroutine (S2).

As shown in FIG. 208(b), the main CPU 500a saves the general-purpose registers (A register, B register, C register, D register, E register, H register, L register, F register) in the E_SETTM module (S3). . Then, the main CPU 500a sets the input abnormality non-monitoring timer value as an initial value in the A register (S4), stores the value of the A register at the value indicated by the predetermined address (the input abnormality non-monitoring timer), A supply abnormality non-monitoring timer is set (S5). When this process is completed, the main CPU 500a restores the general-purpose register (S6), allows interrupts (S7), terminates the E_SETTM module, and returns to the routine one level higher (S8).

Here, the E_SETTM module is designed to satisfy all of the conditions (1) to (6) above, in order to ensure the fairness of the gaming machine and to appropriately divide the roles between the usage area and other areas. ing.

FIG. 209 is an explanatory diagram for explaining an example of a command for realizing the E_SETTM module. Of these, FIG. 209(a) shows a command group for arbitrary processing that calls the E_SETTM module, and FIG. 209(b) shows a command group for the E_SETTM module. The flowchart shown in FIG. 208 is realized, for example, by the program shown in FIG. 209.

Interrupts are prohibited by the command "DI" in the first line of FIG. 209(a). The command on the first line corresponds to step S1 in FIG. 208(a). The E_SETTM module is called as a subroutine by the command "CALL E_SETTM" on the second line. The command on the second line corresponds to step S2 in FIG. 208(a).

The index “E_SETTM:” in the first line of FIG. 209(b) indicates the start address of the E_SETTM module. The command "EX AF, AF'" on the second line exchanges the value of the pair register AF with the value of the pair register AF', which is the back register, and saves the value of the pair register AF. The command "EXX" on the third line swaps the values of the pair registers BC, DE, HL with the values of the pair registers BC', DE', HL', which are the back registers, and the values of the pair registers BC, DE, HL change. will be evacuated. The commands on the second and third lines correspond to step S3 in FIG. 208(b).

The command "LD A, @MDL_WAT_TMR" in the fourth line of FIG. 6+1) is read into the A register. The command on the fourth line corresponds to step S4 in FIG. 208(b). The command "LD (_EX_SLTM), A" on the fifth line stores the value of the A register in the variable "_EX_SLTM" as the input abnormality non-monitoring timer. The command on the fifth line corresponds to step S5 in FIG. 208(b). In this way, it becomes possible to set the input abnormality non-monitoring timer value to the input abnormality non-monitoring timer.

By the command "EXX" on the 6th line of FIG. 209(b), the values of the pair registers BC, DE, and HL and the values of the pair registers BC', DE', and HL', which are the back registers, are exchanged, and the values of the pair registers BC, DE, and HL are exchanged. DE and HL values are restored. By the command "EX AF, AF'" on the seventh line, the value of the pair register AF and the value of the pair register AF' which is the back register are exchanged, and the value of the pair register AF is restored. The commands on the 6th and 7th lines correspond to step S6 in FIG. 208(b). Interruption is permitted by the command "EI" on the 8th line of FIG. 209(b). Incidentally, here, even if the command "EI" is executed before returning from the subroutine, interrupts are appropriately permitted. Therefore, by writing the command "EI" in the subroutine, it is possible to secure the capacity of the usable area. The command on the eighth line corresponds to step S7 in FIG. 208(b). Then, the command "RET" on the 9th line returns to the routine one stage higher. The command on the ninth line corresponds to step S8 in FIG. 208(b). In this way, it becomes possible to set the input abnormality non-monitoring timer in a separate area.

In this way, the total command size of the BLKSHUT module shown in FIG. 209(a) and the E_SETTM module shown in FIG. 209(b) is 1 byte of the command "DI" in the first line of FIG. Command "CALL E_SETTM" 3 bytes + Command "EX AF, AF'" in the second line of Figure 209(b) 1 byte + Command "EXX" in the third line 1 byte + Command "LD A, @MDL_WAT_TMR" in the fourth line ” 2 bytes + 5th line command “LD (_EX_SLTM), A” 4 bytes + 6th line command “EXX” 1 byte + 7th line command “EX AF, AF'” 1 byte + 8th line command “EI” 1 byte + 1 byte of the command "RET" on the 9th line = 16 bytes, and the total execution cycle is 1 cycle on the 1st line in Figure 209(a) + 5 cycles on the 2nd line + 1 cycle on the 2nd line in Figure 209(b) Cycle + 1 cycle on the 3rd row + 2 cycles on the 4th row + 4 cycles on the 5th row + 1 cycle on the 6th row + 1 cycle on the 7th row + 1 cycle on the 8th row + 3 cycles on the 9th row = 20 cycles. By providing such an E_SETTM module, it is possible to use the command "CALL E_SETTM" with a command size of 3 bytes without setting the input abnormality non-monitoring timer in each of the above-mentioned modules. It becomes possible to secure the capacity of the control area for performing control processing.

FIG. 210 is an explanatory diagram for explaining another example of commands for realizing the E_SETTM module. Here, the command group of any process that calls the E_SETTM module in FIG. 209(a) is replaced with the command group of any process that calls the E_SETTM module in FIG. 210(a), and the command group of the E_SETTM module in FIG. 209(b) The group is replaced with the command group of the E_SETTM module shown in FIG. 210(b).

The E_SETTM module is called as a subroutine by the command "CALLEX E_SETTM" on the first line of FIG. 210(a). The command on the first line corresponds to step S2 in FIG. 208(a).

Here, the command "CALLEX mn", like the command "CALL mn", is a command that calls a subroutine having a start address indicated by a fixed value mn. However, the command "CALLEX mn" does not simply call a subroutine like the command "CALL mn", but has multiple functions. For example, by executing the command, non-maskable interrupts (NMI) and maskable interrupts (INT) are automatically disabled, the register bank is switched from the first register bank 726 to the second register bank 728, and then A subroutine having the start address indicated by the fixed value mn is called. Therefore, the interrupt-related command "DI" and the evacuation-related commands "EX AF, AF'" and "EXX" (or the command "PUSH") are not required. Therefore, the command "CALLEX E_SETTM" in the first line of FIG. 210(a) is applied not only to step S2 of FIG. 208(a) but also to step S1 of FIG. 208(a) and step S3 of FIG. 208(b). handle. The command size of such a command is "2" and the execution cycle is "4".

However, the command "CALLEX mn" has certain limitations. For example, if the call destination address is in the range of 2000H to 20FFH on the address map, the command size of the command is "2" and the execution cycle is "4", but in other ranges, the command size of the command is "2" and the execution cycle is "4". is "4", and the execution cycle is "6". Therefore, in order to shorten the command, in this embodiment, the call destination address, for example, "E_SETTM" is arranged to be included in 2000H to 20FFH.

The index “E_SETTM:” in the first line of FIG. 210(b) indicates the start address of the E_SETTM module. The command "LD A, @MDL_WAT_TMR" on the second line causes the fixed value "@MDL_WAT_TMR", that is, (252/6+1), which corresponds to 250.32 msec as the input abnormality non-monitoring timer value (initial value), to the A register. Read out. The command on the second line corresponds to step S4 in FIG. 208(b). The command "LD (_EX_SLTM), A" on the third line stores the value of the A register in the variable "_EX_SLTM" as the input abnormality non-monitoring timer. The command on the third line corresponds to step S5 in FIG. 208(b). In this way, it becomes possible to set the input abnormality non-monitoring timer value to the input abnormality non-monitoring timer.

The command "RETEX" on the fourth line in FIG. 210(b) returns to the routine one stage higher. The command on the fourth line corresponds to step S8 in FIG. 208(b). In this way, it becomes possible to set the input abnormality non-monitoring timer in a separate area.

Here, the command "RETEX", like the command "RET", is a command to return to the routine one level higher. However, the command "RETEX" is often used in pair with the command "CALLEX mn", and like the command "RET", it has multiple functions in addition to simply returning from a subroutine. For example, by executing the command, the register bank is automatically switched from the second register bank 728 to the first register bank 726, interrupts are enabled, and the routine returns to the next higher level. Therefore, the commands "EXX" and "EX AF, AF'" (or the command "POP") related to return and the command "EI" related to interruption are not required. Therefore, the command "RETEX" on the fourth line in FIG. 210(b) corresponds not only to step S8 in FIG. 208(b) but also to step S6 and step S7 in FIG. 208(b). The command size of such a command is "2" and the execution cycle is "5".

The total command size of the BLKSHUT module shown in FIG. 210(a) and the E_SETTM module shown in FIG. 210(b) is 2 bytes of the command "CALLEX E_SETTM" in the first line of FIG. 210(a) + FIG. 210(b) The second line command “LD A, @MDL_WAT_TMR” 2 bytes + the third line command “LD (_EX_SLTM), A” 4 bytes + the fourth line command “RETEX” 2 bytes = 10 bytes, and the total execution cycle is , 4 cycles in the first row in FIG. 210(a) + 2 cycles in the second row in FIG. 210(b) + 4 cycles in the third row + 5 cycles in the fourth row = 15 cycles. Therefore, compared to the case of FIG. 209, the total command size is reduced by 6 bytes, and the total execution cycle is also reduced by at least 5 cycles. With such an E_SETTM module, it is possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing game control processing.

In addition, as can be understood by comparing FIG. 209 and FIG. 210, 8 lines in FIG. 209 (lines 1 and 2 in FIG. ) can be expressed in two lines in FIG. 210 (the first line in FIG. 210(a) and the fourth line in FIG. 210(b)), which reduces the number of commands themselves. , it becomes possible to reduce the design load.

Such a command "CALLEX" can be employed not only in the above-mentioned BLKSHUT module but also in various modules. Moreover, it can be adopted not only for slot machines but also for example, DYM_OUT modules in pachinko machines.

211 and 212 are explanatory diagrams for explaining the DYM_OUT module. The DYM_OUT module shown in step S400-5 in FIG. A dynamic port output process is executed to control the lighting of the display 168, the normal symbol hold display 170, the right hit notification display 172, and the performance display monitor 184.

Interrupts are prohibited by the command "DI" in the first line of FIG. 211(a). The command "CALL E_DMOUT" on the second line calls the E_DMOUT module as a subroutine.

The index “E_DMOUT:” in the first line of FIG. 211(b) indicates the start address of the E_DMOUT module. The command "EX AF, AF'" on the second line exchanges the value of the pair register AF with the value of the pair register AF', which is the back register, and saves the value of the pair register AF. The command "EXX" on the third line swaps the values of the pair registers BC, DE, HL with the values of the pair registers BC', DE', HL', which are the back registers, and the values of the pair registers BC, DE, HL change. Evacuated. The address "R_ERW_IOB" of the identification segment output request buffer is set in the HL register by the command "LD HL, R_ERW_IOB" on the fourth line. The 1-byte value (common counter) stored at the address indicated by "R_COM_CNT" is read into the A register by the command "LD A, (R_COM_CNT)" on the fifth line. Here, the common counter is used to determine a common number for LED dynamic lighting control, and stores a value indicating the common number. The command "LD A, (HL+A)" on the 6th line causes the 1-byte value (display data) stored at the address indicated by the HL register to be added (offset) by the value of the A register to the A register. Read out. The command "OUT (@OTC_PRT),A" on the 7th line sets the value of the U register to the upper 1 byte of the address, and sets the fixed value " @OTC_PRT" as the lower 1 byte, and output the value of the A register to that address. By the command "EXX" on the 8th line, the values of pair registers BC, DE, HL and the values of pair registers BC', DE', HL' which are back registers are exchanged, and the values of pair registers BC, DE, HL are changed. Return. By the command "EX AF, AF'" on the ninth line, the value of the pair register AF and the value of the pair register AF' which is the back register are exchanged, and the value of the pair register AF is restored. Interruption is permitted by the command "EI" on the 10th line. Incidentally, here, even if the command "EI" is executed before returning from the subroutine, interrupts are appropriately permitted. Therefore, by writing the command "EI" in the subroutine, it is possible to secure the capacity of the usable area. Then, the command "RET" on the 11th line returns to the routine one stage higher. In this way, dynamic port output processing can be executed in a separate area.

Here, by replacing the command with "CALLEX", the command group in FIG. 211 can be changed as shown in FIG. 212. The E_DMOUT module is called as a subroutine by the command "CALLEX E_DMOUT" in the first line of FIG. 212(a). Here, the call destination address, for example, "E_DMOUT" is arranged to be included in 2000H to 20FFH.

The index “E_DMOUT:” in the first line of FIG. 212(b) indicates the start address of the E_DMOUT module. The address "R_ERW_IOB" of the identification segment output request buffer is set in the HL register by the command "LD HL, R_ERW_IOB" on the second line. The 1-byte value (common counter) stored at the address indicated by "R_COM_CNT" is read into the A register by the command "LD A, (R_COM_CNT)" on the third line. The command "LD A, (HL+A)" on the fourth line causes the 1-byte value (display data) stored at the address indicated by the HL register to be added (offset) by the value of the A register to the A register. Read out. The command "OUT (@OTC_PRT),A" on the 5th line sets the value of the U register to the upper 1 byte of the address, and sets the fixed value "OUT (@OTC_PRT),A" to the lower 1 byte of the address of output port 12 (internal register I/O port). @OTC_PRT" as the lower 1 byte, and output the value of the A register to that address. The command "RETEX" on the sixth line returns to the routine one step higher. In this way, similar to FIG. 211, dynamic port output processing can be executed in another area.

In this way, the total command size of the DYM_OUT module shown in FIG. 211(a) and the E_DMOUT module shown in FIG. 211(b) is the command "DI" 1 byte in the first line of FIG. 3 bytes of the command "CALL E_DMOUT" + 1 byte of the command "EX AF, AF'" on the 2nd line in Figure 211(b) + 1 byte of the command "EXX" on the 3rd line + 1 byte of the command "LD HL, R_ERW_IOB" on the 4th line 3 bytes + 5th line command “LD A, (R_COM_CNT)” 3 bytes + 6th line command “LD A, (HL+A)” 3 bytes + 7th line command “OUT (@OTC_PRT),A” 2 bytes + 8 lines 1 byte of the command “EXX” on the 9th line + 1 byte of the command “EX AF, AF’” on the 9th line + 1 byte of the command “EI” on the 10th line + 1 byte of the command “RET” on the 11th line = 21 bytes, total execution The cycle is 1 cycle on the 1st line in Figure 211(a) + 5 cycles on the 2nd line + 1 cycle on the 2nd line + 1 cycle on the 3rd line + 3 cycles on the 4th line + 4 cycles on the 5th line + 4 cycles on the 6th line in Figure 211(b) Cycle + 3 cycles on the 7th line + 1 cycle on the 8th line + 1 cycle on the 9th line + 1 cycle on the 10th line + 3 cycles on the 11th line = 28 cycles.

On the other hand, the total command size of the DYM_OUT module shown in FIG. 212(a) and the E_DMOUT module shown in FIG. 212(b) is 2 bytes of the command "CALLEX E_DMOUT" in the first line of FIG. b) 2nd line command “LD HL, R_ERW_IOB” 3 bytes + 3rd line command “LD A, (R_COM_CNT)” 3 bytes + 4th line command “LD A, (HL+A)” 3 bytes + 5th line 2 bytes of command “OUT (@OTC_PRT),A” + 2 bytes of command “RETEX” on the 6th line = 15 bytes, and the total execution cycle is 4 cycles on the 1st line in Figure 212(a) + 4 cycles in Figure 212(b) 2nd line 3 cycles + 3rd line 4 cycles + 4th line 4 cycles + 5th line 3 cycles + 6th line 5 cycles = 23 cycles. Therefore, compared to the case of FIG. 211, the total command size is reduced by 6 bytes, and the total execution cycle is also reduced by 5 cycles. With such an E_DMOUT module, it is possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing game control processing.

By the way, as explained using FIGS. 208 to 210, the command size of the command "CALLEX mn" is "2" if the call destination address is in the range of 2000H to 20FFH on the address map, The execution cycle is "4", but in other ranges, the command size of the command is "4" and the execution cycle is "6". Therefore, it is desirable that all call destination addresses be placed in the range of 2000H to 20FFH. However, from 2000H to 20FFH, the number of bytes that can be written is only 256 bytes, so if subroutines are written as they are in this range, the number of subroutines will be limited. For example, even with the E_SETTM module, which has a relatively small command size, the command “LD A, @MDL_WAT_TMR” on the second line in Figure 210(b) is 2 bytes + the command “LD (_EX_SLTM), A” on the third line is 4 bytes. Since the command "RETEX" on the +4th line occupies 2 bytes = 8 bytes, it becomes impossible to arrange a large number of subroutines.

Therefore, in this embodiment, substantially only the movement-related command "JP mn" is placed in the range from 2000H to 20FFH on the address map, and the main body of the subroutine is placed at the movement destination. Since the command size of the command "JP mn" is "3", by arranging the command "JP mn" in the range of 2000H to 20FFH on the address map, 256/3=86 modules can be called as subroutines. It becomes possible.

Note that it is also possible to use the command "CALL mn" with a command size of "3" instead of the command "JP mn", but in that case, the command "RETEX" with a command size of "2" can be used after the command "CALL mn". ”, the number of subroutines is more limited than the command “JP mn”. Therefore, it is desirable to employ the command "JP mn". The specific processing of the E_SETTM module that reflects this content will be described below.

FIG. 213 is a flowchart showing specific processing of the E_SETTM module. Here, as an arbitrary process, a part of the BLKSHUT module that executes the blocker blockage process will be described as in FIG. 208. The numerical values of step S in this figure will be used only in the explanation of this figure.

The main CPU 500a executes arbitrary processing as shown in FIG. 213(a). The main CPU 500a calls the RRE01 module as a subroutine in a separate area (S1).

Next, as shown in FIG. 213(b), the main CPU 500a moves to the E_SETTM module without performing any significant processing in the RRE01 module (S2). In this way, the RRE01 module is a module for moving to the E_SETTM module, and is placed in the range of 2000H to 20FFH on the address map. In this way, a large number of subroutines can be arranged.

As shown in FIG. 213(c), the main CPU 500a sets the value of the input abnormality non-monitoring timer in the A register in the E_SETTM module (S3), and sets the value of the A register to a predetermined address (the input abnormality non-monitoring timer). The input abnormality non-monitoring timer is set by storing the value as indicated (S4). When this process is completed, the main CPU 500a ends the E_SETTM module and returns to the routine one level higher (S5). Since this E_SETTM module is the destination of the RRE01 module, it is not subject to address map restrictions. Therefore, since it can be arbitrarily placed in the range of 2100H to 3FBFH in the separate area, it is permissible even if the total command size is large to some extent.

FIG. 214 is an explanatory diagram for explaining still another example of commands for realizing the E_SETTM module. Here, as shown in FIG. 214(b), a new RRE01 module is provided for moving to the E_SETTM module.

The command "CALLEX PRE01" in the first line of FIG. 214(a) calls the RRE01 module instead of the E_SETTM module as a subroutine. The command on the first line corresponds to step S1 in FIG. 213(a). Note that the command "CALLEX PRE01" also executes prohibition of interrupts and saving of general-purpose registers.

The index "PRE01:" in the first line of FIG. 214(b) indicates the start address of the PRE01 module. The command "JP E_SETTM" on the second line moves to the E_SETTM module body. Such a command corresponds to step S2 in FIG. 213(b).

Note that when calling multiple subroutines through the command "CALLEX mn", the index indicating the call address for the multiple subroutines (for example, "PRE01:" and the command "JP mn" must be consecutively placed in the range of 2000H to 20FFH). By doing so, the range from 2000H to 20FFH can be effectively used and a large number of subroutines can be arranged.

The index “E_SETTM:” in the first line of FIG. 214(c) indicates the start address of the E_SETTM module. The command "LD A, @MDL_WAT_TMR" on the second line causes the fixed value "@MDL_WAT_TMR", that is, (252/6+1), which corresponds to 250.32 msec as the input abnormality non-monitoring timer value (initial value), to the A register. Read out. The command on the second line corresponds to step S3 in FIG. 213(c). The command "LD (_EX_SLTM), A" on the third line stores the value of the A register in the variable "_EX_SLTM" as the input abnormality non-monitoring timer. The command on the third line corresponds to step S4 in FIG. 213(c). In this way, it becomes possible to set the input abnormality non-monitoring timer value to the input abnormality non-monitoring timer.

The command "RETEX" on the fourth line in FIG. 214(c) returns to the routine one stage higher. The command on the fourth line corresponds to step S5 in FIG. 213(c). In this way, it becomes possible to set the input abnormality non-monitoring timer in a separate area. Note that the command "RETEX" also executes restoration of general-purpose registers and permission of interrupts.

In the example of FIG. 214, the total command size and total execution cycle are larger by the amount of the command "JPE_SETTM" than in the case of FIG. 210. However, by configuring the command to move to the subroutine itself via the command "JP E_SETTM", it is possible to allocate many subroutines in the range of 2000H to 20FFH, expand the limit on the number of subroutines, and furthermore, the command of the subroutine itself Since the size restriction is relaxed, it is possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing game control processing.

Note that even if only the command "JP mn" is placed in the range of 2000H to 20FFH, if the number of subroutines that can be placed is insufficient, that is, if there are 86 or more subroutines, the module with a small total command size is placed in the range of 2100H to 217FH (range of 128 bytes), and instead of the command "JP mn" with command size "3", use the command "JR mn" with command size "2", which is suitable for short distance movement. It may be used. By doing this, it becomes possible to arrange more commands "JR mn" in the range of 2000H to 20FFH.

<Command “ICPLMQA”, “ICPLMQ”>
The RAM_INC module is a module for RAM addition processing, that is, for incrementing a 1-byte variable in the main RAM 500c by 1 up to a predetermined number. Note that the RAM_INC module not only increments, but also sets a carry flag as a result of the increment. Further, the RAM_INC module can also be used as a general-purpose module.

Such RAM_INC module is called as a subroutine from multiple modules. For example, in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, the EXE_SET module selectively transitions depending on the gaming state and performance state and executes the present precursory process (AT state = "3"). The HID_LOT module executes the execution flag setting process shown in step S2400-11 in FIG. 91, and the EXE_SET module executes the execution flag setting process shown in step S2400-11 in FIG. The FIN_LOT module that executes the execution flag setting process shown in step S2400-11 in FIG. 91 and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. ), and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. '') is called from the BIT_LOT module, etc.

The main CPU 500a reads a program from the main ROM 500b, executes the read program, and increments a 1-byte value held in the main RAM 500c in an arbitrary process.

FIG. 215 is a flowchart showing specific processing of the RAM_INC module. The numerical values of step S in this figure will be used only in the explanation of this figure. Furthermore, in the description of the RAM_INC module, the predetermined register is the A register, the predetermined number is the upper limit value, and the specific address is the address to be incremented.

As shown in FIG. 215(a), the main CPU 500a sets an address to be incremented in the HL register in an arbitrary process (S1). Then, the main CPU 500a increments the 1-byte value stored at the address indicated by the HL register (S2), stores the incremented value at the address indicated by the HL address, and updates the value (S3). However, here, an upper limit value (predetermined number) is set, and the result of incrementing does not exceed the upper limit value.

FIGS. 216 and 217 are explanatory diagrams for explaining examples of commands for implementing the RAM_INC module. The flowchart shown in FIG. 215 is realized, for example, by the program shown in FIG. 216.

The index “RAM_INC:” in the first line of FIG. 216 indicates the start address of the RAM_INC module. The command "LDQ HL, LOW _AT_SET" on the second line reads the value of the Q register to the H register, and reads the value of the lower 1 byte of the address "_AT_SET" to the L register. The command on the second line corresponds to step S1 in FIG. 215. As shown in FIG. 217, the command "LD A, (HL)" on the third line reads the 1-byte value (for example, 02H) stored at the address indicated by the HL register into the A register. By the command "INC A" on the fourth line in FIG. 216, the value of the A register is incremented by 1 from 02H to 03H, for example, as shown in FIG. 217. In addition, in order to provide versatility, the command "LD A, 1" and the command "ADD A, ( HL)" can also be used. In this case, by changing the value of "1" stored in the A register, the value to be incremented can be changed to a value other than 1.

The command "JCP C, A, 5, RAM_INC01" on the 5th line of Figure 216 compares the value of the A register with the upper limit "5", and if the result is less than 5 (if the carry flag is set ), moves to address “RAM_INC01”. In this way, if the value of the A register is less than the upper limit of 5, the next process can be omitted and the process can be moved to the index "RAM_INC01" on the 7th line. The upper limit value "5" is stored in the A register by the command "LD A,5" on the sixth line. This is because if the value of the A register exceeds 5 by the command "INC A" on the 4th line, the value of the A register will be forcibly overwritten to 5, so that the incremented result will be 5 or less. be. Note that here, if the value of the A register before incrementing is 4, that is, if the value of the A register is incremented from 4 to 5, the value of the A register is already 5, so it is necessary to update it to 5. However, adding processing to determine this will increase the processing load, so we prioritize versatility and forcefully update the value of the A register to 5, as in the case where the value exceeds 5. The commands on the 3rd to 6th lines correspond to step S2 in FIG. 215.

The index "RAM_INC01" on the 7th line of FIG. 216 indicates the destination address of the command "JCP C, A, 5, RAM_INC01" on the 5th line. The command "LD (HL), A" on the eighth line stores the value of the A register (for example, 03H) at the address indicated by the HL register, as shown in FIG. 217. The command on the eighth line corresponds to step S3 in FIG. 215. In this way, it is possible to increment the 1-byte variable in the main RAM 500c by 1 up to a predetermined number and hold the incremented value in the A register (use the value in the A register in subsequent processing). Become.

In this way, the total command size of the RAM_INC module commands shown in Figure 216 is the command "LDQ HL, LOW _AT_SET" on the second line, 2 bytes + the command "LD A, (HL)" on the third line, 1 byte + 4 lines. 1st command “INC A” 1 byte + 5th line command “JCP C, A, 5, RAM_INC01” 3 bytes + 6th line command “LD A,5” 2 bytes + 8th line command “LD (HL), A'' 1 byte = 10 bytes, and the total execution cycle is 2 cycles on the 2nd line + 2 cycles on the 3rd line + 1 cycle on the 4th line + 4 cycles on the 5th line + 2 cycles on the 6th line + 2 cycles on the 8th line = 13 cycles. By providing such a RAM_INC module, a 1-byte variable can be uniformly and easily incremented, making it possible to shorten commands and secure the capacity of the control area for performing game control processing.

FIG. 218 is an explanatory diagram for explaining another example of commands for implementing the RAM_INC module. Here, the command group of the RAM_INC module in FIG. 216 is replaced with the command group of the RAM_INC module in FIG. 218.

The index “RAM_INC:” in the first line of FIG. 218 indicates the start address of the RAM_INC module. The command "ICPLMQA (LOW _AT_SET), 5" on the second line sets the value of the Q register as the upper 1 byte of the address, sets the value of the lower 1 byte of the address "_AT_SET" as the lower 1 byte of the address, and sets that address (increment The 1-byte value stored at the target address) is compared with the upper limit value "5", and if the result is less than 5 (if the carry flag is set), the 1 byte value stored at the target address is incremented. The byte value is incremented by 1 and stored in the A register, and the 1-byte value stored at the address to be incremented is updated. Also, if the value after incrementing is 5 or more (if the carry flag is not set), the upper limit value "5" is stored in the A register, and the 1-byte value stored at the address to be incremented is set to the upper limit value. Update to "5". The command on the second line corresponds to steps S1 to S3 in FIG. 215. In this way, it is possible to increment the 1-byte variable in the main RAM 500c by 1 up to a predetermined number and hold the incremented value in the A register (use the value in the A register in subsequent processing). Become.

Here, the command "ICPLMQA (k), n" takes the value of the Q register as the upper 1 byte of the address, sets the value k as the lower 1 byte of the address, and sets the 1-byte value stored at the target address and the upper limit value. If the result is less than n, increment the 1-byte value stored at the target address by 1, store it in the A register, and update the 1-byte value stored at the target address. , n or more, this is a command that stores the upper limit value n in the A register and updates the 1-byte value stored at the target address to the upper limit value n. The command size is "4" and the execution cycle is "7".

The total command size of the commands of the RAM_INC module in FIG. 218 is 4 bytes of the command "ICPLMQA (LOW_AT_SET), 5" on the second line = 4 bytes, and the total execution cycle is 7 cycles = 7 cycles on the second line. Therefore, compared to the case of FIG. 216, the total command size is reduced by 6 bytes, and the total execution cycle is reduced by 6 cycles. With such a RAM_INC module, it is possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing game control processing.

Also, as can be understood by comparing FIG. 216 and FIG. 218, the command group that occupied seven lines (second to eighth lines) in FIG. It is possible to reduce the number of commands and reduce the design load.

FIG. 219 is an explanatory diagram for explaining still another example of commands for implementing the RAM_INC module. In the RAM_INC module described using FIG. 218, an example was given in which a 1-byte variable in the main RAM 500c is incremented by 1 up to a predetermined number, and the incremented value is held in the A register. However, depending on the process, it may be sufficient to increment a 1-byte variable in the main RAM 500c by 1 up to a predetermined number without leaving the result in the A register. Here, an example will be given in which a 1-byte variable is incremented by 1 without updating the A register.

The index “RAM_INC:” in the first line of FIG. 219 indicates the start address of the RAM_INC module. The command "ICPLMQ (LOW _AT_SET), 5" on the second line sets the value of the Q register as the upper 1 byte of the address, sets the value of the lower 1 byte of the address "_AT_SET" as the lower 1 byte of the address, and sets that address (increment The 1-byte value stored at the target address) is compared with the upper limit value "5", and if the result is less than 5 (if the carry flag is set), the 1 byte value stored at the target address is incremented. Update the byte value by incrementing it by 1. Further, if the incremented value is 5 or more (unless the carry flag is set), the 1-byte value stored at the address to be incremented is updated to the upper limit value "5". The command on the second line corresponds to steps S1 to S3 in FIG. 215. In this way, the 1-byte variable in the main RAM 500c can be incremented by 1 up to a predetermined number.

Here, the command "ICPLMQ (k), n" sets the value of the Q register as the upper 1 byte of the address, sets the value k as the lower 1 byte of the address, and sets the 1-byte value stored at the target address and the upper limit value. If the result is less than n, the 1-byte value stored at the target address is incremented by 1 and updated, and if it is greater than or equal to n, the 1-byte value stored at the target address is updated as the upper limit. This is a command to update to the value n. The command size is "4" and the execution cycle is "7".

The total command size of the commands of the RAM_INC module in FIG. 219 is 4 bytes of the command "ICPLMQ (LOW_AT_SET), 5" on the second line = 4 bytes, and the total execution cycle is 7 cycles = 7 cycles on the second line. Therefore, compared to the case of FIG. 216, the total command size is reduced by 6 bytes, and the total execution cycle is reduced by 6 cycles. With such a RAM_INC module, it is possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing game control processing.

Also, compared to the example in FIG. 216, the A register is not used here. Therefore, the value of the A register will not be updated unintentionally. Furthermore, in the example of FIG. 216, if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, there is no need for stack processing. In this way, resources can be used effectively.

Also, as can be understood by comparing FIG. 216 and FIG. 219, the command group that occupied seven lines (second to eighth lines) in FIG. It is possible to reduce the number of commands and reduce the design load.

<Command “LDINTQR”>
The TABLSET module is a general-purpose module for table set processing, that is, for setting predetermined values (initial values) to variables in the main RAM 500c. Here, an example will be described in which the TABLSET module is placed at 0030H on the memory map.

The main CPU 500a reads a program from the main ROM 500b, executes the read program, calls the TABLSET module as a subroutine in any process, and executes the TABLSET module. The TABLSET module transfers a plurality of one-byte values written in the program data of the main ROM 500b to an area in the work area of the main RAM 500c that holds a plurality of data treated as variables. In this way, the values of multiple variables are set. Here, the number of data to be transferred is simply referred to as the number of data.

FIG. 220 is a flowchart showing specific processing of the TABLSET module. Here, as an optional process, a part of the ERRWAIT module that executes the error wait process shown in step S2200-11 in FIG. 89 and step S2800-39 in FIG. List and explain. The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the explanation of the TABLSET module, the first register is the B register, the second register is the HL register, the register different from the first register and the second register is the A register, and the predetermined value is "1". be. Note that it goes without saying that the predetermined value can be set arbitrarily.

As shown in FIG. 220(a), the main CPU 500a sets the start address of a 1-byte data group to be a transfer source in the HL register in an arbitrary process (S1). Then, the TABLSET module is called as a subroutine (S2).

As shown in FIG. 220(b), the main CPU 500a saves the BC register in the TABLSET module (S3) and prohibits interrupts (S4). Then, the main CPU 500a reads the 1-byte value stored at the address indicated by the HL register into the B register (S5). This 1-byte value indicates the number of data. Next, the main CPU 500a stores the data at the address specified by adding "2" to the HL register to the address specified by the value stored at the address shown by adding "1" to the HL register. The next address to be transferred is set by adding "2" to the value of the HL register (S6). Next, the main CPU 500a decrements (subtracts by "1") the value of the B register, and determines whether the decremented result is 0 (S7). Here, if the decremented result is not 0 (NO in S7), the process from step S6 is repeated, and if the decremented result is 0 (YES in S7), interrupts are permitted (S8) and the BC register is (S9), the TABLSET module is terminated, and the routine returns to the next step higher (S10).

FIGS. 221 and 222 are explanatory diagrams for explaining an example of a command for implementing the TABLSET module. Of these, FIG. 221(a) shows a command group for arbitrary processing that calls the TABLSET module, FIG. 221(b) shows a command group for the TABLSET module, and FIG. 221(c) shows the program data of the main ROM 500b. FIG. 221(d) shows the arrangement of the 1-byte data group in the work area of the main RAM 500c. The flowchart shown in FIG. 220 is realized, for example, by the program shown in FIG. 221.

The command "LD HL, T_ERR_RCV" in the first line of FIG. 221(a) sets the start address "T_ERR_RCV" of the 1-byte data group to be the transfer source in the HL register. The command on the first line corresponds to step S1 in FIG. 220(a). Then, the TABLSET module is called as a subroutine by the command "RST TABLSET" on the second line. The command on the second line corresponds to step S2 in FIG. 220(a).

The index “TABLSET:” in the first line of FIG. 221(b) indicates the start address of the TABLSET module. The command "PUSH BC" on the second line saves the value of the BC register to the stack area. The command on the second line corresponds to step S3 in FIG. 220(b). Interrupts are prohibited by the command "DI" on the third line. The command on the third line corresponds to step S4 in FIG. 220(b).

The 1-byte value stored at the address indicated by the HL register is read into the B register by the command "LD B, (HL)" in the fourth line of FIG. 221(b). At this time, the address "T_ERR_RCV" is set in the HL register as shown in FIG. 221(a). Therefore, the 1-byte value "(T_ERR_RCV_-T_ERR_RCV)/2" in the second line of FIG. 221(c) is read into the B register as the data number (transfer repetition number). Note that "T_ERR_RCV_" is the address following the last address of the 1-byte data group that is the transfer source, and T_ERR_RCV is the first address of the 1-byte data group that is the transfer source, so the value of T_ERR_RCV_ - T_ERR_RCV (indicating the number of data The value of 1-byte value) is the total number of bytes of the 1-byte value, and by dividing that value by 2, which is the number of combinations of address and value, the number of data is derived. In the example of FIG. 221(c), the number of data is 9/2=4. The command on the fourth line of FIG. 221(b) corresponds to step S5 of FIG. 220(b).

The index “TABLSET10:” in the fifth line of FIG. 221(b) indicates the start address of the repetitive process. The command “INLD AC, (HL)” on the 6th line and the command “LDQ (C), A” on the 7th line specify the value stored at the address indicated by adding “1” to the HL register. The value stored in the address indicated by adding "2" to the HL register is stored in the address, and "2" is added to the value of the HL register to set the next address to be transferred. The commands on the 6th and 7th lines correspond to step S6 in FIG. 220(b).

For example, if the HL register has the value of the address "T_ERR_RCV", the lower 1 byte value of the 2-byte variable "_ERR_NUM" in the third line of FIG. 221(c) is stored in the C register, and The value of "0" in the third line is stored in the A register.

In addition, the command "LDQ (C), A" on the 7th line of FIG. , is a command to store the value of the A register.

For example, the value of the C register, that is, the value of the lower 1 byte of "_ERR_NUM" is set as the lower 1 byte of the address, and the value of the A register, that is, the value of "0" is stored in that address.

Here, in FIGS. 221(c) and 221(d), the variable "_ERR_NUM" indicates the error number, the variable "_CRE_TMR" indicates the credit button detection timer, and the variable "_CRE_FLG" indicates the credit button detection flag. , and the variable "_SNS_OLD" indicates the previous state of the medal passing sensor bit. Note that the arrangement of variables shown in FIG. 221(d) does not need to be continuous as shown in the figure, and may be spaced apart.

Next, the value of the B register is decremented (subtracted by "1") by the command "DJNZ TABLSET10" on the 8th line of FIG. , if the decremented result is 0, the process moves to the command next to the command in question. Here, the number of data is "4", so if the process from "TABLSET10" is repeated four times, the value of the B register becomes 0. The command on the 8th line corresponds to step S7 in FIG. 220(b).

Interruption is permitted by the command "EI" on the 9th line of FIG. 221(b). The command on the ninth line corresponds to step S8 in FIG. 220(b). The data saved in the stack area is returned to the BC register by the command "POP BC" on the 10th line. The command on the 10th line corresponds to step S9 in FIG. 220(b). Then, the command "RET" on the 11th line returns to the routine one level higher. The command on the 11th line corresponds to step S10 in FIG. 220(b).

In this way, as shown in FIG. 222, a plurality of 1-byte values (55H, 77H, 66H, 22H) written in the program data of the main ROM 500b are transferred to variables ("_ERR_NUM", "_CRE_TMR", "_CRE_TMR", etc.) in the work area of the main RAM 500c. "_CRE_FLG", "_SNS_OLD").

The TABLSET module is called as a subroutine by multiple modules. For example, in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, the EXE_SET module selectively transitions depending on the gaming state and performance state and executes the present precursory process (AT state = "3"). The HID_LOT module executes the execution flag setting process shown in step S2400-11 in FIG. 91, and the EXE_SET module executes the execution flag setting process shown in step S2400-11 in FIG. The FIN_LOT module that executes the execution flag setting process shown in step S2400-11 in FIG. 91 and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. ), and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. ”), and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 7"), the RANKSET module that executes the setting value switching process shown in step S2020 of FIG. 85, the FGSETUP module that executes the symbol code setting process shown in step S2400 of FIG. 91, and step S2900 of FIG. 96. It is called from the GAMESET module that executes the game transition process shown in , the JCGMSET module that executes the accessory operation process shown in step S2900-3 of FIG. 96, and the like.

In this way, the total command size of the TABLSET module commands shown in FIG. B, (HL)” 1 byte + 6th line command “INLD AC, (HL)” 2 bytes + 7th line command “LDQ (C), A” 2 bytes + 8th line command “DJNZ TABLSET10” 2 bytes + 9 1 byte of the command “EI” on the 10th line + 1 byte of the command “POP BC” on the 11th line + 1 byte of the command “RET” on the 11th line = 12 bytes, and the total execution cycle is 3 cycles on the 2nd line + 1 cycle on the 3rd line. + 2 cycles on the 4th line + 4 cycles on the 6th line + 3 cycles on the 7th line + 3 cycles (or 2 cycles) on the 8th line + 1 cycle on the 9th line + 3 cycles on the 10th line + 3 cycles on the 11th line = 23 cycles (or 22 cycles) . Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "DJNZ TABLSET10". By providing such a TABLSET module, it is possible to use the command "RST TABLSET" with a command size of 1 byte without having to perform table set processing in each of the above-mentioned modules, so the command can be shortened and the game control processing can be This makes it possible to secure the capacity of the control area for this purpose.

FIG. 223 is an explanatory diagram for explaining another example of commands for implementing the TABLSET module. Here, the command group of the TABLSET module in FIG. 221(b) is replaced with the command group of the TABLSET module in FIG. 223(b), and any other process command that calls the TABLSET module in FIG. 221(a) The 1-byte data group in the program data of the main ROM 500b in FIG. 221(c) and the 1-byte data group in the work area of the main RAM 500c in FIG. 221(d) are shown in FIGS. 223(a) and 223(c). , is used as is as shown in FIG. 223(d). Here, as in FIGS. 223(a), 223(c), and 223(d), processes that are substantially the same as those in FIGS. 221(a), 221(c), and 221(d) will be described. The explanation will be omitted and only the different processing in FIG. 223(b) will be explained.

The index “TABLSET:” in the first line of FIG. 223(b) indicates the start address of the TABLSET module. The command "PUSH BC" on the second line saves the value of the BC register to the stack area. The command on the second line corresponds to step S3 in FIG. 220(b). Interrupts are prohibited by the command "DI" on the third line. The command on the third line corresponds to step S4 in FIG. 220(b).

The 1-byte value stored at the address indicated by the HL register is read into the B register by the command "LD B, (HL)" in the fourth line of FIG. 223(b). At this time, the address "T_ERR_RCV" is set in the HL register as shown in FIG. 223(a). Therefore, the 1-byte value "(T_ERR_RCV_-T_ERR_RCV)/2" in the second line of FIG. 223(c) is read into the B register as the data number (transfer repetition number). In the example of FIG. 223(c), the number of data is 4. The command on the fourth line in FIG. 223(b) corresponds to step S5 in FIG. 220(b).

The value of the HL register is incremented by 1 by the command "INC HL" on the 5th line of FIG. 223(b). The command "LDINTQR (HL)" on the 6th line causes the value stored in the address specified by the value stored in the address shown in the HL register plus "1" in the HL register. is transferred, "2" is added to the value of the HL register to set the next transfer address, the value of the B register is decremented (subtracted by "1"), and the process continues until the decremented result becomes 0. Repeated. The commands on the 5th and 6th lines correspond to steps S6 and S7 in FIG. 220(b).

Here, the command "LDINTQR (HL)" sets the value of the Q register as the upper 1 byte of the address, sets the value stored at the address indicated by the HL register as the lower 1 byte of the address, and sets the value of the HL register to that address. The value stored in the address indicated by the value added by "1" is transferred, "2" is added to the value of the HL register to update the value of the HL register, and the value of the B register is decremented (subtracted by "1"). ) and repeats the value transfer until the decremented result becomes 0. The command size of such a command is "2" and the execution cycle is "5".

For example, if the HL register has the value of the address "T_ERR_RCV", the value of the Q register is the upper 1 byte of the address, and the value of the lower 1 byte of "_ERR_NUM" in the third line of FIG. 223(c) is the value of the address. The value "0" in the third line of FIG. 223(c) is transferred to that address, "2" is added to the value of the HL register, and the value of the B register is decremented ("1"). (subtraction), and the transfer is repeated four times until the decremented result becomes 0, that is, the transfer is repeated four times.

Subsequently, an interrupt is permitted by the command "EI" on the 7th line of FIG. 223(b). The command on the seventh line corresponds to step S8 in FIG. 220(b). The command "POP BC" on the 8th line causes the data saved in the stack area to be returned to the BC register. The command on the 8th line corresponds to step S9 in FIG. 220(b). Then, the command "RET" on the 9th line returns to the routine one stage higher. The command on the ninth line corresponds to step S10 in FIG. 220(b).

The total command size of the commands in the TABLSET module in Figure 223(b) is: 1 byte of the command “PUSH BC” on the 2nd line + 1 byte of the command “DI” on the 3rd line + 1 byte of the command “LD B, (HL)” on the 4th line 1 byte + 5th line command “INC HL” 1 byte + 6th line command “LDINTQR (HL)” 2 bytes + 7th line command “EI” 1 byte + 8th line command “POP BC” 1 byte + 9th line The command "RET" 1 byte = 9 bytes, and the total execution cycle is: 2nd line 3 cycles + 3rd line 1 cycle + 4th line 2 cycles + 5th line 1 cycle + 6th line 5 cycles + 7th line 1 cycle + 8th line 3 cycles + 3 cycles on the 9th row = 19 cycles. Therefore, compared to the case of FIG. 221(b), the total command size is reduced by 3 bytes, and the total execution cycle is also reduced by at least 4 cycles. In particular, in the example of FIG. 221(b), if the value of the B register in the command "DJNZ TABLSET10" is 2 or more, that value is applied for 10 cycles (4 cycles on the 6th line + 3 cycles on the 7th line + 3 cycles on the 8th line). Since the total execution cycles increase by the amount multiplied by , the amount of reduction in the total execution cycles in FIG. 221(b) also increases. By using such a TABLSET module, it is possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing game control processing.

Also, compared to the example of FIG. 221, the A register and C register are not used here. Therefore, the value of the A register or the C register will not be updated unintentionally. In addition, in the example in Figure 221, if the A register or C register was already in use, it was necessary to stack and save the values of the A register or C register, but here, the A register or C register is used. Therefore, there is no need for stack processing. In this way, resources can be used effectively.

Also, in order to understand by comparing FIG. 221(b) and FIG. 223(b), the command group that occupied four lines (5th to 8th lines) in FIG. 221(b) is 223(b) can be expressed in two lines (5th and 6th lines), making it possible to reduce the number of commands themselves and reduce the design load.

<DECWMQ>
FIG. 224 is a flowchart showing specific processing of the IPT_PC module. The IPT_PC module executes time monitoring processing that is read out once every four times in step S3100-21 of the timer interrupt processing (see FIG. 98). The numerical values of step S in this figure will be used only in the explanation of this figure.

The time monitoring process is a process of subtracting by one the timer (for example, one game timer, etc.) set in various steps in FIGS. 82 to 98.

As shown in FIG. 224(a), the main CPU 500a reads out the address where the timer is stored in the HL register (S1), executes the WORDDEC module shown in FIG. 224(b) (S2), and writes the address in the HL register. The value of the indicated address is subtracted by 1 (S3). Then, the command "RET" terminates the WORDDEC module and returns to the IPT_PC module (S4).

FIG. 225 is an explanatory diagram for explaining an example of a command for implementing the IPT_PC module. The flowchart shown in FIG. 224 is realized, for example, by the program shown in FIG. 225. In addition, in FIG. 225, a process of subtracting the one-game timer will be described as an example.

The index “IPT_PC:” in the first line of FIG. 225(a) indicates the start address of the IPT_PC module. Then, by the command "LDQ HL, (LOW_GAM_TMR)" on the second line of FIG. 225(a), the value of the Q register is read to the H register, and the value of the lower 1 byte of the address "_GAM_TMR" is read to the L register. The command on the second line corresponds to step S1 in FIG. 224(a).

Then, the WORDDEC module shown in FIG. 225(b) is called by the command "CALLF WORDDEC" on the third line of FIG. 225(a). The command on the second line corresponds to step S2 in FIG. 224(a).

The index “WORDDEC:” in the first line of FIG. 225(b) indicates the start address of the WORDDEC module. Then, by the command "DCPWLD (HL), 0" on the second line of FIG. The 2-byte length value (one game timer) is read out, and 1 is subtracted (updated) from the read value. If the carry flag is set to 1 by subtraction, that is, if the read value is 0 (predetermined value), then the address indicated in the HL register (more precisely, the address indicated in the HL register is A fixed value "0 (specific value)" is stored in the indicated address and the next address. On the other hand, if 1 is not set in the carry flag, that is, if the read value is 1 or more, the subtracted value is the address indicated in the HL register (more precisely, the address indicated in the HL register address and the next address). The command on the second line corresponds to step S3 in FIG. 224(b).

Then, the command "RET" on the third line in FIG. 225(b) terminates the WORDDEC module and returns to the IPT_PC module. The command on the third line corresponds to step S4 in FIG. 224(b). In this way, it is possible to decrement the 2-byte length value (one game timer) stored at the address indicated by the HL register by 1 in each process until it becomes 0.

Here, the command group in FIGS. 225(a) and 225(b) can be changed as shown in FIG. 225(c). Here, descriptions of processes that are substantially the same as those in FIGS. 225(a) and 225(b) will be omitted, and only the different processes in FIG. 225(c) will be described.

The command "DECWMQ (LOW_GAM_TMR)" on the second line of FIG. 225(c) sets the value of the Q register as the upper 1 byte of the address, sets the value of the lower 1 byte of the address "_GAM_TMR" as the lower 1 byte of the address, The value stored at that address is read. Then, 1 is subtracted (decremented) from the read value, and if 1 is set in the carry flag due to the subtraction, that is, if the read value is 0, the fixed value " 0" is stored. On the other hand, if the carry flag is not set to 1, that is, if the read value is 1 or more, the subtracted value is stored at that address.

Here, the total command size of the command group shown in FIGS. 225(a) and 225(b) is 2 bytes of the command "LDQ A, (LOW_GAM_TMR)" in the second line of FIG. 225(a) + The command “CALLF WORDDEC” on the third line in (a) 2 bytes + the command “DCPWLD (HL),0” on the second line in Figure 225(b) 4 bytes + the command on the third line in Figure 225(b) “ RET" 1 byte = 9 bytes, and the total execution cycle is 2 cycles on the 2nd line in Figure 225(a) + 4 cycles on the 3rd line in Figure 225(a) + 9 cycles on the 2nd line in Figure 225(b) + In the third row of FIG. 225(b), 3 cycles = 18 cycles.

On the other hand, the total command size of the command group shown in FIG. 225(c) is 3 bytes of the command "DECWMQ (LOW_GAM_TMR)" in the second line = 3 bytes, and the total execution cycle is 8 cycles in the second line = 8 cycles. becomes.

Therefore, by replacing the command group in FIGS. 225(a) and 225(b) with the command group in FIG. 225(c), the total command size is reduced by 6 bytes, and the total execution cycle is also reduced by 10 cycles. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

In addition, in order to understand by comparing FIG. 225(a) and FIG. 225(c), the command group that occupied two lines (second to third lines) in FIG. 225(a) is In H.225(c), it can be expressed in one line (second line), making it possible to reduce the number of commands themselves and reduce the design load.

Furthermore, in the example of FIG. 225(c), the WORDDEC module can also be deleted, making it possible to free up a valuable general-purpose module area and place other modules in that area. In this way, resources can be used effectively.

<RIBIT>
FIG. 226 is a flowchart showing specific processing of the CMDPROC module. The CMDPROC module executes the subcommand transmission process (see step S3100-11 in FIG. 98). The numerical values of step S in this figure will be used only in the explanation of this figure.

The main CPU 500a obtains the value of the interrupt wait monitor register, as shown in FIG. 226 (S1). Here, the interrupt wait monitor register is composed of 1 byte, and the power cutoff notice signal is inputted to the 6th bit. Then, when the power supply voltage of the slot machine 400 falls below a predetermined value, a power-off notice signal is input, and the 6th bit of the interrupt wait monitor register becomes 1, and otherwise becomes 0.

The main CPU 500a determines whether a power-off notice signal is input, that is, whether there is an external interrupt request, by referring to the 6th bit of the acquired interrupt wait monitor register (S2). If there is an external interrupt request (YES in S2), the relevant CMDPROC module is terminated and the routine returns to the next level higher. If there is no external interrupt request (NO in S2), the process moves to the next step and the subcommand is executed. It is transmitted to the sub control board 502.

FIG. 227 is an explanatory diagram for explaining an example of a command for realizing the CMDPROC module. The flowchart shown in FIG. 226 is realized, for example, by the program shown in FIG. 227.

The index “CMDPROC:” in the first line of FIG. 227(a) indicates the start address of the CMDPROC module. Then, by the command "IN A, (@IRR______)" on the second line of FIG. 227(a), the value of the U register is set to the upper 1 byte of the address, and a fixed value indicating the lower 1 byte of the address of the interrupt wait monitor register is set. Set "@IRR______" to the lower 1 byte of the address, and read the value stored at that address to the A register. The command on the second line corresponds to step S1 in FIG. 226.

Then, if the 6th bit of the value stored in the A register is not 0, that is, 1, by the command "RBIT NZ, 6, A" on the 3rd line of FIG. 227(a), the command "RET ”, the CMDPROC module is terminated and the routine returns to the next step higher. On the other hand, if the 6th bit of the value stored in the A register is 0, processing moves to the next command. The command on the third line corresponds to step S2 in FIG. 226.

Here, the command group in FIG. 227(a) can be changed as shown in FIG. 227(b). Here, descriptions of processes that are substantially the same as those in FIG. 227(a) will be omitted, and only processes that are different from those in FIG. 227(b) will be described.

The command "RIBIT NZ, 6, (@IRR______)" in the second line of FIG. 227(b) sets the value of the U register to the upper 1 byte of the address, and sets the value of the U register to a fixed value indicating the lower 1 byte of the address of the interrupt wait monitor register. "@IRR______" is the lower 1 byte of the address, and if the 6th bit of the value stored at that address is not 0, terminate the relevant CMDPROC module and execute the command "RET". Return to routine. On the other hand, if the 6th bit of the value stored at that address is 0, processing moves to the next command.

Here, the total command size of the command group shown in Figure 227(a) is 2 bytes for the command "IN A, (@IRR______)" on the second line + 2 bytes for the command "RBIT NZ, 6, A" on the third line. = 4 bytes, and the total execution cycle is 3 cycles on the second line + 5 (3) cycles on the third line = 8 (6) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "RBIT NZ, 6, A".

On the other hand, the total command size of the command group shown in FIG. 227(b) is 3 bytes = 3 bytes for the command "RIBIT NZ, 6, (@IRR______)" in the second line, and the total execution cycle is 7 bytes in the second line. (5) cycles = 7 (5) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by the command "RIBIT NZ, 6, (@IRR______)".

Therefore, by replacing the command group in FIG. 227(a) with the command group in FIG. 227(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

Furthermore, in the example of FIG. 227(b), the A register used in FIG. 227(a) is not used. Therefore, the value of the A register will not be updated unintentionally. In addition, in the example of FIG. 227(a), if the A register was already used, it was necessary to stack it and save the value of the A register, but here, since the A register is not used, the stack processing is also not necessary. unnecessary. In this way, resources can be used effectively.

In addition, in order to understand by comparing FIG. 227(a) and FIG. 227(b), the command group that occupied two lines (second to third lines) in FIG. 227(a) is In H.227(b), it can be expressed in one line (second line), making it possible to reduce the number of commands themselves and reduce the design load.

<AND+OR>
FIG. 228 is a flowchart showing specific processing of the SET_PLS module. The SET_PLS module executes the excitation pattern update process read in the stepping motor control process (see step S3100-13 in FIG. 98). The numerical values of step S in this figure will be used only in the explanation of this figure.

As shown in FIG. 228, the main CPU 500a acquires the top address of the excitation pattern table in which the excitation patterns of the stepping motor 452 are stored (S1). The main CPU 500a adds, or offsets, the offset value stored in the A register in advance to the obtained start address of the excitation pattern table (S2).

The main CPU 500a then obtains an output image stored in a predetermined output port (S3), and masks the upper 4 bits of the obtained output image (S4). Note that the output image obtained here has a length of 1 byte, and the excitation pattern of the stepping motor 452 is shown in the upper 4 bits. Therefore, here, the excitation pattern is cleared by masking the upper 4 bits of the output image.

After that, the main CPU 500a synthesizes an excitation pattern by taking the logical sum of the value indicated at the address offset in step S2 and the obtained output image (S5), and updates the synthesized excitation pattern as an output image. (S6), then ends the SET_PLS module and returns to the routine one step above (S7).

FIG. 229 is an explanatory diagram for explaining an example of a command for realizing the SET_PLS module. The flowchart shown in FIG. 228 is realized, for example, by the program shown in FIG. 229.

The index “SET_PLS:” in the first line of FIG. 229(a) indicates the start address of the SET_PLS module. Then, the address "T_PLS_PTN" of the excitation pattern table in which the excitation pattern of the stepping motor 452 is stored is read into the HL register by the command "LD HL, T_PLS_PTN" on the second line of FIG. 229(a). The command on the second line corresponds to step S1 in FIG. 228.

Then, by the command "ADDWB HL,A" on the third line of FIG. 229(a), the value of the A register (offset value) is added to the value of the HL register, and the value of the HL register is updated. The command on the third line corresponds to step S2 in FIG. 228.

Thereafter, the value (output image) stored at the output port address "IY+@OFS_OUT_PRT" is read into the A register by the command "LD A, (IY+@OFS_OUT_PRT)" on the fourth line of FIG. 229(a). The command on the fourth line corresponds to step S3 in FIG. 228.

Next, the command "AND A, 00001111B" on the 5th line of FIG. (The upper 4 bits are masked) and the operation result is stored in the A register. The command on the fifth line corresponds to step S4 in FIG. 228.

Then, the command "OR A, (HL)" on the 6th line of FIG. , second value), and the result of the operation is stored in the A register. The command on the sixth line corresponds to step S5 in FIG. 228.

Thereafter, the value of the A register is stored in the output port address "IY+@OFS_OUT_PRT" by the command "LD (IY+@OFS_OUT_PRT), A" on the 7th line of FIG. 229(a). The command on the seventh line corresponds to step S6 in FIG. 228. Then, the command "RET" on the 8th line in FIG. 229(a) terminates the SET_PLS module and returns to the routine one step above. The command on the eighth line corresponds to step S7 in FIG. 228.

Here, the command group in FIG. 229(a) can be changed as shown in FIG. 229(b). Here, descriptions of processes that are substantially the same as those in FIG. 229(a) will be omitted, and only processes that are different from those in FIG. 229(b) will be described.

The CALADRS module shown in FIG. 229(c) is called by the command "RST CALADRS" on the third line of FIG. 229(b). The index “CALADRS:” in the first line of FIG. 229(c) indicates the start address of the CALADRS module. Then, by the command "ADDWB HL,A" on the second line of FIG. 229(c), the value of the A register (offset value) is added to the value of the HL register, and the value of the HL register is updated. Then, by the command "LD A, (HL)" on the third line, the 1-byte value stored at the address indicated by the HL register is read into the A register. Then, the command "RET" on the fourth line in FIG. 229(c) terminates the CALADRS module and returns to the SET_PLS module.

After that, by the command "AND (IY+@OFS_OUT_PRT),00001111B" on the fourth line of FIG. The product is calculated (the upper 4 bits are masked), and the calculation result is stored at the address "IY+@OFS_OUT_PRT".

Then, by the command "OR (IY+@OFS_OUT_PRT), A" on the 5th line of FIG. excitation pattern) is calculated, and the calculation result is stored in the address "IY+@OFS_OUT_PRT".

Here, the total command size of the command group shown in Figure 229(a) is: 3 bytes of the command "LD HL, T_PLS_PTN" on the 2nd line + 1 byte of the command "ADDWB HL, A" on the 3rd line + 1 byte of the command on the 4th line “LD A, (IY+@OFS_OUT_PRT)” 3 bytes + 5th line command “AND A, 00001111B” 2 bytes + 6th line command “OR A, (HL)” 1 byte + 7th line command “LD (IY+@ OFS_OUT_PRT), A" 3 bytes + 8th line command "RET" 1 byte = 14 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 1 cycle + 4th line 4 cycles + 5th line 2 cycles + 6th line 2 cycles + 4 cycles on the 7th line + 3 cycles on the 8th line = 19 cycles.

On the other hand, the total command size of the command group shown in FIG. 229(b) is: 3 bytes of the command "LD HL, T_PLS_PTN" on the 2nd line + 1 byte of the command "RST CALADRS" on the 3rd line + 1 byte of the command "AND ( IY+@OFS_OUT_PRT), 00001111B" 4 bytes + 5th line command "OR (IY+@OFS_OUT_PRT), A" 3 bytes + 6th line command "RET" 1 byte = 12 bytes, and the total execution cycle is 2nd line 3 Cycle + 4 cycles on the 3rd row + 7 cycles on the 4th row + 6 cycles on the 5th row + 3 cycles on the 6th row = 23 cycles.

Therefore, by replacing the command group in FIG. 229(a) with the command group in FIG. 229(b), the total command size is reduced by 2 bytes. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing game control processing. Note that the CALADRS module, which is a general-purpose module, is read and executed by other modules, and is not newly added.

Also, as can be understood by comparing FIGS. 229(a) and 229(b), the command group in FIG. 229(b) can be reduced by two lines compared to the command group in FIG. 229(a), It is possible to reduce the number of commands and the design load.

<CPLBQ>
FIG. 230 is a flowchart showing specific processing of the OTM_ATK module. The numerical values of step S in this figure will be used only in the explanation of this figure.

Here, as another example of the slot machine 400, a so-called chance zone performance state is provided. The chance zone performance state is a state in which it is easier to win an AT lottery than the normal performance state, and is transferred over a predetermined game. For example, the chance zone performance state is transferred over eight games, and an AT lottery is performed for each game. In another example of the slot machine 400, the results of the AT lottery for each game in the chance zone production state are stored in one bit (winning = 1, non-winning = 0), so that the results of all AT lottery results are totaled. It is managed as 8-bit (1 byte length) validity information.

The OTM_ATK module executes processing for managing the results of such AT lottery. Note that the OTM_ATK module is called and executed in the execution flag setting process shown in step S2400-11 in FIG. 91 only when the AT lottery is won in each game.

As shown in FIG. 230, the main CPU 500a acquires the number of games in the chance zone production state (S1) and acquires the address of the number of games bit table (S2). In addition, as will be described in detail later, in the game number bit table, bit information corresponding to the 1st game to the 8th game in the chance zone production state is consecutively arranged, and each bit information is The bit corresponding to (1-bit information) is 1, and the other bits are 0, resulting in 1-byte length data.

The main CPU 500a acquires bit information corresponding to the acquired number of games from the number of games bit table (S3), and also acquires 1-byte long win/fail information (1-byte information) indicating the result of the AT lottery (S4). ). Then, the main CPU 500a updates (synthesizes) the validity information by calculating the logical sum of the obtained bit information and the validity information (S5), and saves the updated validity information (S6). The OTM_ATK module is terminated and the routine returns to the next step higher (S7).

FIG. 231 is an explanatory diagram for explaining an example of a command for realizing the OTM_ATK module. The flowchart shown in FIG. 230 is realized, for example, by the program shown in FIG. 231.

The index “OTM_ATK:” in the first line of FIG. 231(a) indicates the start address of the OTM_ATK module. Then, the command "LDQ A, (LOW _CZ_CNT)" on the second line of FIG. It is set to 1 byte, and the value (number of games) stored at that address is read to the A register. The command on the second line corresponds to step S1 in FIG. 230.

Then, by the command "LD HL, T_XXX_XXX" on the third line of FIG. 231(a), the start address "T_XXX_XXX" of the number of games bit table shown in FIG. 231(b) is read into the HL register. The command on the third line corresponds to step S2 in FIG. 230.

The index “T_XXX_XXX:” in the first line of FIG. 231(b) indicates the start address of the table “T_XXX_XXX”. The value "00000001B" in the second line of FIG. 231(b) corresponds to the first game in the chance zone performance state, and only the 0 bit is 1 and the other bits are 0. Similarly, the values in the 3rd to 9th lines of FIG. Bit is 0.

The CALADRS module is called by the command "RST CALADRS" on the fourth line of FIG. 231(a). In addition, in the CALADRS module, the value of the A register (number of games) is added to the value of the HL register, the value of the HL register is updated, and the value (number of games) stored at the address indicated in the updated HL register is added to the value of the HL register. bit information corresponding to ) is read out to the A register. The command on the fourth line corresponds to step S3 in FIG. 230.

The command "LDQ B, (LOW _ATW_BIT)" on the 5th line of FIG. 231(a) sets the value of the Q register as the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "_ATW_BIT" as the lower 1 byte of the address. and reads out the value (validity information) stored at that address to the B register. The command on the fifth line corresponds to step S4 in FIG. 230.

The command "OR A, B" on the 6th line of FIG. 231(a) calculates the logical sum of the value of the A register (bit information corresponding to the number of games) and the value of the B register (proper/false information). Here, when the AT lottery is won in the game, the bit corresponding to the number of games in the win/fail information becomes 1. The command on the sixth line corresponds to step S5 in FIG. 230.

The command "LDQ (LOW _ATW_BIT), A" on the 7th line of FIG. 231(a) sets the value of the Q register to the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "_ATW_BIT" to the lower 1 byte of the address. and stores the value of the A register (updated validity information) at that address. The command on the seventh line corresponds to step S6 in FIG. 230.

Then, by the command "RET" on the 8th line of FIG. 231(a), the OTM_ATK module ends and returns to the routine one stage higher. The command on the eighth line corresponds to step S7 in FIG. 230.

Here, the command group in FIG. 231(a) can be changed as shown in FIG. 231(c). Here, descriptions of processes that are substantially the same as those in FIG. 231(a) will be omitted, and only processes that are different from those in FIG. 231(c) will be described.

The command "CPLBQ A, (LOW _ATW_BIT)" on the third line of FIG. 231(c) sets the value of the Q register as the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "_ATW_BIT" as the lower 1 byte of the address. Then, the bit corresponding to the value of the A register (number of games) out of the value (win/fail information) stored at that address is inverted. Therefore, in the win/fail information, the bit corresponding to the game (number of games) won in the AT lottery is inverted and becomes 1 here.

Here, the total command size of the command group shown in Figure 231(a) is 2 bytes of the command "LDQ A, (LOW_CZ_CNT)" on the second line + 3 bytes of the command "LD HL, T_XXX_XXX" on the third line + 4 lines. 1st command “RST CALADRS” 1 byte + 5th line command “LDQ B, (LOW _ATW_BIT)” 3 bytes + 6th line command “OR A, B” 1 byte + 7th line command “LDQ (LOW _ATW_BIT),” A" 2 bytes + 8th line command "RET" 1 byte = 13 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 3 cycles + 4th line 4 cycles + 5th line 4 cycles + 6th line 2 cycles + 7 3 cycles on the row + 3 cycles on the 8th row = 22 cycles.

On the other hand, the total command size of the command group shown in FIG. 231(c) is 2 bytes for the command "LDQ A, (LOW _CZ_CNT)" on the second line + 3 bytes for the command "CPLBQ A, (LOW _ATW_BIT)" on the third line. +1 byte of the command "RET" on the 4th line = 6 bytes, and the total execution cycle is 3 cycles on the 2nd line + 6 cycles on the 3rd line + 3 cycles on the 4th line = 12 cycles.

Therefore, by replacing the command group in FIG. 231(a) with the command group in FIG. 231(c), the total command size is reduced by 7 bytes, and the total execution cycle is also reduced by at least 10 cycles. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

In addition, in order to be able to understand by comparing FIGS. 231(a) and 231(c), the command group that occupied 5 lines (3rd to 7th lines) in FIG. 231(a) is In 231(c), it can be expressed in one line (third line), which makes it possible to reduce the number of commands and reduce the design load.

Furthermore, by replacing the command group with the command group shown in FIG. 231(c), the number-of-games bit table becomes unnecessary, so the data capacity for the number-of-games bit table can also be reduced.

<LDSB>
FIG. 232 is an explanatory diagram for explaining an example of a command for realizing the KRS_JDG module.

Here, as another example of the gaming machine 100, in a predetermined round game in a big prize game, when a game ball enters a variable probability area (specific area) provided in the big prize opening, the game state after the big prize game is changed. Set to high probability gaming state. Then, in a big winning game in which a predetermined special symbol is determined, when a predetermined number of games pass through the big prize opening in a predetermined round game, the variable probability area is opened, and the game ball can enter the variable variable area. . Below, if 3 game balls enter the grand prize opening in the first round game, and if 5 game balls enter the grand prize opening in the 5th round game, the variable probability area will be opened. This will be explained using an example.

The KRS_JDG module executes processing for managing the release of such variable probability areas. Note that the KRS_JDG module is called and executed in the big prize opening control process shown in FIG. 47.

The index “KRS_JDG:” in the first line of FIG. 232(a) indicates the start address of the KRS_JDG module. Then, the command "LDQ A, (LOW R_ROU_CNT)" on the second line of FIG. 1 byte, and the value stored at that address (the number of consecutive special electric accessory operations, that is, the number of round games) is read into the A register.

Then, by the command "LD B, (HL)" on the third line of FIG. 232(a), the value of the address indicated by the value stored in the HL register is read into the B register. Note that the address "D_KRS_JDG_2" of the probability variable area determination table shown in FIG. 232(b) is read out in advance into the HL register.

The index “D_KRS_JDG_2:” in the first line of FIG. 232(b) indicates the start address of the table “D_KRS_JDG_2”. The value “(@D_KRS_JDG_2-D_KRS_JDG2-1)/2” in the second line of FIG. This is the value obtained by subtracting 1 and dividing it by 2, and indicates the number of determinations (the number of round games in which the variable probability area is opened).

The value “@KRS_TGT_ROU_01” in the third line of FIG. 232(b) is a value (target round value, here 1) indicating the first round game that opens the probability variable area, and the value “@KRS_TGT_ROU_01” in the third line of FIG. The value in the row "@KRS_JDG_01" is a value (opening identification value, Here, it is 3). Similarly, the value “@KRS_TGT_ROU_03” in the fifth line of FIG. ) is the value "@KRS_JDG_03" on the 6th line, which indicates how many game balls enter the big prize opening to open the variable probability area in the second round game in which the variable probability area is opened. The identification value is 5) here.

Therefore, the number of determinations is read into the B register by the command "LD B, (HL)" on the third line of FIG. 232(a).

The index “KRS_JDG_10:” in the fourth line of FIG. 232(a) indicates the address of the index “KRS_JDG_10”. The value of the HL register is added (incremented) by 1 by the command "INC HL" on the 5th line of FIG. 232(a). After that, the command "CP A, (HL)" on the 6th line of FIG. 232(a) compares the value of the A register with the value stored at the address indicated by the value of the HL register (target round value). If the value of the A register is the same as the value of the HL register, the zero flag is set and becomes 1; if it is different from the value of the HL register, the zero flag is not set and becomes 0.

Subsequently, the value of the HL register is again incremented by 1 by the command "INC HL" on the 7th line of FIG. 232(a). Thereafter, the value of the address (open identification value) indicated by the HL register is read into the C register by the command "LD C, (HL)" on the 8th line of FIG. 232(a).

If the zero flag is set by the command "RET Z" on the 9th line of FIG. 232(a), the KRS_JDG module is terminated and the process returns to the module one level above.

In addition, if the zero flag is not set, the value of the B register is decremented (subtracted by "1") by the command "DJNZ KRS_JDG_10" on the 10th line of FIG. 232(a), and if the decremented result is not 0, the address If the result of moving to "KRS_JDG_10" and decrementing is 0, the command "RET" on the 11th line in FIG. 232(a) ends the KRS_JDG module and returns to the module one level higher.

Here, in the gaming machine 100, the maximum number of round games is 10. Further, the number of balls entering the big winning hole for opening the variable probability area is set between 2 and 5 since the prescribed number for each round game is 10. That is, the target round value is a value of 10 or less and can be expressed with 4 bits. Therefore, although the value "@KRS_TGT_ROU_01" and the value "@KRS_TGT_ROU_03" indicating the target round value are configured with a length of 1 byte, they may actually be 4 bits long.

Further, the open identification value is a value of 5 or less and can be expressed with 3 bits. Therefore, although the value "@KRS_JDG_01" and the value "@KRS_JDG_03" indicating the open identification value are configured with a length of 1 byte, they may actually be 3 bits long.

Therefore, below, an example will be described in which two values, a target round value that can be expressed in 4 bits and an open identification value that can be expressed in 3 bits, are treated as one value (data) of 1 byte length.

FIG. 233 is an explanatory diagram for explaining another example of the command for realizing the KRS_JDG module. Note that the description of processes that are substantially the same as those in FIG. 232 will be omitted, and only the different processes in FIG. 233 will be described.

The command "LD B, (HL)" on the third line of FIG. 233(a) reads the value of the address indicated in the HL register into the B register. Note that the address "D_KRS_JDG_2" of the probability variable area determination table shown in FIG. 233(b) is read out in advance into the HL register.

The value "@KRS_TGT_ROU_01*8+@KRS_JDG_01" in the third line of FIG. 233(b) is a value (target round value) in which the upper 5 bits indicate the first round game that opens the probability variable area, and the lower 3 bits is a value (opening identification value) indicating how many game balls enter the big winning hole to open the variable probability area in the first round game in which the variable probability area is opened. Similarly, the value “@KRS_TGT_ROU_03*8+@KRS_JDG_03” in the fourth line of FIG. 233(b) is a value (target round value) in which the upper 5 bits indicate the second round game that opens the probability variable area, The lower 3 bits are a value (opening identification value) indicating how many game balls enter the grand prize opening to open the variable probability area in the second round game in which the variable probability area is opened.

The command "LDSB 2, DE, (HL)" on the 6th line of FIG. The upper 5 bits of the register value are shifted to the right by 3 bits and read into the D register (other bits are set to 0). That is, the target round value and the open identification value are separated, and the target round value is read out to the D register, and the open identification value is read out to the E register. Note that "2" in the command "LDSB 2, DE, (HL)" is a value indicating that the 3 bits from bit 0 to bit 2 are read to the E register, and the higher bits ( 5 bits) is shifted and read out to the D register.

The command "CP A, D" on the 7th line in Figure 233(a) compares the value of the A register with the value of the D register (target round value), and determines that the value of the A register is the same as the value of the D register. If so, the zero flag is set and becomes 1, and if it is different from the target round value, the zero flag is not set and becomes 0.

Here, the total command size of the command group shown in Figure 232(a) is 2 bytes for the command "LDQ A, (LOW R_ROU_CNT)" on the second line + 1 byte for the command "LD B, (HL)" on the third line. + 5th line command “INC HL” 1 byte + 6th line command “CP A, (HL)” 1 byte + 7th line command “INC HL” 1 byte + 8th line command “LD C, (HL)” 1 byte + command “RET Z” on the 9th line 1 byte + 2 bytes of the command “DJNZ KRS_JDG_10” on the 10th line + 1 byte of the command “RET” on the 11th line = 11 bytes, and the total execution cycle is 3 cycles on the 2nd line + 3 Row 2 cycles + 5th row 1 cycle + 6th row 2 cycles + 7th row 1 cycle + 8th row 1 cycle + 9th row 3 (1) cycles + 10th row 3 (2) cycles + 11th row 3 (1) cycles = 19 (14) It becomes a cycle. Further, the probability variable area determination table shown in FIG. 232(b) is 5 bytes. Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by a command.

On the other hand, the total command size of the command group shown in FIG. 233(a) is 2 bytes of the command "LDQ A, (LOW R_ROU_CNT)" on the second line + 1 byte of the command "LD B, (HL)" on the third line + 5 Command “INC HL” on the 6th line 1 byte + Command “LDSB 2, DE, (HL)” on the 6th line 2 bytes + Command “CP A, D” on the 7th line 1 byte + Command “RET Z” on the 8th line 1 Byte + 2 bytes of the command "DJNZ KRS_JDG_10" on the 9th line + 1 byte of the command "RET" on the 10th line = 11 bytes, and the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 1 cycle on the 5th line + 1 cycle on the 6th line. 3 cycles + 1 cycle on the 7th line + 3 (1) cycles on the 8th line + 3 (2) cycles on the 9th line + 3 (1) cycles on the 10th line = 19 (14) cycles. Further, the probability variable area determination table shown in FIG. 233(b) is 3 bytes. Note that the number of cycles in parentheses indicates the execution cycle when the movement is not performed by a command.

Therefore, by replacing the command group in FIG. 232(a) and the probability variable region determination table in FIG. 232(b) with the command group in FIG. 233(a) and the probability variable region determination table in FIG. 233(b), the total size can be reduced. 2 bytes are reduced. By such replacement, it is possible to shorten the commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

Note that the command "LDSB" can be used to treat two values (information) of a total of 8 bytes or less as one data of 1 byte length, and can be applied even in cases other than the above example. can.

<Management of register banks and register groups>
As described using FIG. 101, the register unit 716 of the CPU core 700 is provided with two register banks (a first register bank 726 and a second register bank 728) that can be exclusively switched and used. Further, each of the first register bank 726 (first register bank) and the second register bank 728 (second register bank) has two register groups (main register groups 726a and 728a) that can be accessed by switching exclusively. and sub-register groups 726b, 728b), each of which has 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY). include. Therefore, the register groups in which a plurality of registers are common are two register banks (first register bank 726, second register bank 728) and two register groups (main register group 726a, 728a, sub register group 726b). , 728b), it exists in four areas.

Such register groups are used exclusively between register banks and between register groups, and can store information independently, so that they are not affected by updates to registers in other areas. In other words, the main CPU 500a can update the contents of the registers of the currently targeted register bank and register group, but cannot access other register banks and register groups that are not targeted.

In this way, by taking advantage of the fact that register groups are independent between register banks and between register groups, each register group can be divided into multiple groups by its type (purpose, function, trigger, etc.). Consider making it compatible with each program. For example, in the memory space of this embodiment, as shown in the memory map of FIG. 102, a used area and another area are allocated in the main ROM 500b and main RAM 500c. As described above, the used area of the main ROM 500b stores programs and data for executing the game control process that controls the progress of the game, and the separate area of the main ROM 500b stores the programs and data that do not affect the progress of the game. Instruction codes and program data of a program that executes processing outside of game control are stored. As described above, since the used area and the separate area have different target processing contents, it is preferable to associate different register groups with each other.

Therefore, in this embodiment, the first register bank 726 is made to correspond to a register group used to execute gaming control processing in the used area, and the second register bank 728 is made to correspond to a register group used to execute processing outside of gaming control in another area. let In other words, the first register bank 726 is used as a register group used to execute gaming control processing in the used area, and the second register bank 728 is used as a register group used to execute processing outside gaming control in another area. . Then, the main CPU 500a refers to the program stored in 0000h to 1FFFh of the main ROM 500b, updates the register group of the first register bank 726, executes the game control process, and stores the program in 2000h to 3FFFh of the main ROM 500b. Referring to the program currently running, the register bank is switched, the register group of the second register bank 728 is updated, and processing outside of game control is executed. With this configuration, independence and exclusivity between the used area and another area can be ensured in both the memory and the register.

Moreover, in this embodiment, the programs executed in the game control process are divided into two. Here, for example, the processing is divided into main processing and timer interrupt processing. The main process (first process) includes the main loop, as shown in FIGS. 22 to 25 (gaming machine 100) and FIGS. 82 to 97 (slot machine 400), and includes the player's operations and their results. The timer interrupt process (second process) is a process that is executed sequentially according to This is a process that is executed by temporarily interrupting the main process in response to a timer interrupt that occurs every predetermined time (for example, 4ms, 1.49ms). Note that although the main process has been described as the first process, the present invention is not limited to this case, and any process for advancing the game can be applied. In addition, although the timer interrupt processing has been explained here as the second processing, it is not limited to this case. Any process can be applied as long as it is executed by a predetermined interrupt that is generated based on the establishment of (etc.).

In this embodiment, one of the two register groups 726a and 726b of the first register bank 726 is made to correspond to either the main processing or the timer interrupt processing, and the The other of the two register groups 726a and 726b of one register bank 726 is made to correspond. In other words, one of the two register groups 726a and 726b of the first register bank 726 is used as a register group for executing either the main processing or the timer interrupt processing, and the second register group of the first register bank 726 The other of the two register groups 726a and 726b is used as a register group used for executing the other process of main processing and timer interrupt processing. Hereinafter, in the first embodiment, an example in which the main register group 726a corresponds to main processing and the sub-register group 726b to correspond to timer interrupt processing will be explained, and in the second embodiment, the sub-register group 726a corresponds to main processing. An example in which the main register group 726b is made to correspond to the timer interrupt processing and the main register group 726a is made to correspond to the timer interrupt processing will be described.

(First embodiment)
Here, an example will be described in which the main register group 726a is associated with main processing, and the sub-register group 726b is associated with timer interrupt processing. Therefore, the main CPU 500a sequentially executes main processing by referring to the main register group 726a, and when a timer interrupt occurs, interrupts the main processing, temporarily switches from the main register group 726a to the sub register group 726b, and executes the timer interrupt. When the interrupt processing is executed and the timer interrupt processing ends, the sub register group 726b is switched to the main register group 726a, and the main processing is restarted.

By the way, as mentioned above, this embodiment uses a Q register. The value written in the Q register is referenced as part of an address in any command. By using such a Q register, a command that refers to the Q register can be written, and the command size and number of cycles can be reduced.

For example, regarding the load instruction "LD" that reads data from the memory space, if the command "LD A, (mn)" is written in the program, the value stored at the 16-bit address mn can be read to the A register. The command size of such a command is 3 bytes and the number of cycles is 4. On the other hand, if you write the command "LDQ A, (n)" that refers to the Q register in a program, the value of the Q register will be the upper 1 byte of the address, the address n will be the lower 1 byte of the address, and the 16-bit address will be The value stored at that address can be read to the A register so that it is treated as . Such a command has a command size of 2 bytes and a cycle count of 3 cycles. Therefore, both the command size and the number of cycles can be reduced.

These Q registers are managed for each register group, as described above. That is, there is a Q register (first register) of the main register group (first register group) 726a and a Q' register (second register) of the sub register group (second register group) 726b, which are independent of each other. and hold the value.

Also, when the main CPU 500a including the register unit 716 is powered on, initial values are set independently of each other for the Q register of the main register group 726a and the Q' register of the sub-register group 726b. For example, when the power is turned on, the Q register of the main register group 726a is set to one high-order byte value (for example, F0h to ), and the Q' register of the sub-register group 726b is set to "F0h" (first value), which is the same as that of the sub-register group 726b. , 1 (for example, F1h) is set to "F1h". This is based on the assumption that memory areas that are mutually referenced are divided into processes that use the main register group 726a and processes that use the sub-register group 726b.

However, in this embodiment, the main processing using the main register group 726a and the timer interrupt processing using the sub-register group 726b access variables associated with the same memory area. Therefore, it is better to hold the same value (for example, F0h) in both the Q register of the main register group 726a and the Q' register of the sub register group 726b, which are referred to as the upper byte of the address. Since this is not necessary, the command size can be reduced.

Therefore, in this embodiment, both the Q register of the main register group 726a and the Q' register of the sub-register group 726b are set to the same value (here, F0h). Note that the initial value of the Q register of the main register group 726a is F0h (first value), so there is no need to set another value. Therefore, here, only the Q' register of the sub-register group 726b is rewritten from F1h to F0h (second value). Note that the main CPU 500a needs to set a value in the Q' register before a command that refers to the Q' register is used. Therefore, for example, it is conceivable to initialize the Q' register in the initialization process of the main process (for example, the CPU initialization process in FIG. 82).

FIG. 234 is a diagram showing an example of a command for setting a value in the Q' register. Here, the main CPU 500a sets F0h in the Q' register in the initialization process of the main process. However, as described above, the main CPU 500a can update the contents of the Q register of the main register group 726a, which is the register group currently being targeted, but cannot access the Q' register of the sub register group 726b, which is another register group. Can not do it. Therefore, as shown in FIG. 234, the 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers in the main register group 726a are set by the command "EX ALL" on the first line. from the registers (IX, IY) to the 8-bit registers (Q', A', F', B', C', D', E', H', L') and the 16-bit registers in the sub-register group 726b. Switch to registers (IX', IY'). Then, the command "LD Q,0F0H" on the second line sets F0h in the Q' register, and the command "EX ALL" on the third line switches from the sub register group 726b to the main register group 726a.

The total command size of the command example shown in Figure 234 is: 1st line command “EX ALL” 2 bytes + 2nd line command “LD Q,0F0H” 1 byte + 3rd line command “EX ALL” 2 bytes = 5 The total execution cycle is 2 cycles for the 1st row + 1 cycle for the 2nd row + 2 cycles for the 3rd row = 5 cycles.

Note that although an example has been given here in which the command "EX ALL" is used to switch between the Q register of the main register group 726a and the Q' register of the sub register group 726b, this is not the only case; For example, the command "EX Q, Q'" may be used. Note that the command size of the command "EX Q, Q'" is 2 bytes and the cycle is 2 cycles, so even if it is replaced with the command "EX ALL", the total command size and total execution cycles will not change.

There are many types of commands that refer to the Q' register, not only the command "LDQ" exemplified above, and they are repeatedly described in a program. Therefore, each time a command that refers to the Q' register is used, the command size and number of cycles can be reduced. As the frequency of use of commands that refer to the Q' register increases, the number of times the Q register is referenced also increases. Therefore, the value of the Q' register should be set reliably. Therefore, instead of or in addition to setting the Q' register only once in the initialization process of the main process, it may be possible to repeatedly set the Q' register throughout the loop process of the main process. For example, the command group in FIG. 234 is executed in any one of FIGS. 88 to 97 (slot machine 400). By doing this, the Q' register can be set to F0h each time the main processing loop process is executed, so even if the Q' register becomes the initial value F1h, the Q' register can be set to F0h. The value of the 'register can be reliably set to F0h, and the value of the Q' register can be stably maintained.

However, since the Q' register is used in timer interrupt processing, F0h is set in the Q' register before allowing the timer interrupt.

Also, consider setting the Q' register only once during initialization processing of the main processing, or instead of or in addition to setting it repeatedly during the loop processing of the main processing, setting it repeatedly through timer interrupt processing. It will be done. By doing this, you can set F0h in the Q' register every time a timer interrupt occurs, so even if the Q' register becomes the initial value F1h, the value of the Q' register will not change. can be reliably set to F0h, and the value of the Q' register can be stably maintained. An example of repeatedly setting the Q' register through timer interrupt processing will be described in detail below.

FIG. 235 is a diagram showing an example of a command for setting a value in the Q' register. Here, first, normal timer interrupt processing will be explained using FIG. 235(a) without referring to the setting of the Q' register. Note that the main CPU 500a targets the main register group 726a until the timer interrupt processing occurs (in the main processing). The index "TMR_IPT:" in the first line of FIG. 235(a) indicates the start address of the timer interrupt process. The command “EX ALL” on the second line allows data to be read from the 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY) in the main register group 726a. , 8-bit registers (Q', A', F', B', C', D', E', H', L') and 16-bit registers (IX', IY') in the sub-register group 726b. Switch to . In this way, the target becomes the sub-register group 726b. After executing the necessary processing in the timer interrupt processing, the sub register group 726b is switched to the main register group 726a by the command "EX ALL" on the fifth line. Interruption is enabled by the command "EI" on the 6th line. Incidentally, here, even if the command "EI" is executed before returning from the subroutine to the main processing, interrupts are appropriately permitted. Then, the command "RETI" on the seventh line returns to the main processing.

The total command size of the commands shown in Figure 235(a) is: 2 bytes of the command “EX ALL” on the 2nd line + 2 bytes of the command “EX ALL” on the 5th line + 1 byte of the command “EI” on the 6th line + 1 byte of the command “EI” on the 7th line 2 bytes of the command "RETI" = 7 bytes, and the total execution cycle is 2 cycles on the 2nd line + 2 cycles on the 5th line + 1 cycle on the 6th line + 4 cycles on the 7th line = 9 cycles.

Here, a command to set the Q' register is written at any timing of the timer interrupt process in FIG. 235(a). When setting the Q' register in timer interrupt processing, it is sufficient to write only the command "LD Q, 0F0H" after the command "EX ALL", as shown in FIG. 235(b). In the case of timer interrupt processing, the command "EX ALL" is executed again at the end of the processing (fifth line), and switching is made to the main register group 726a.

Note that the position of the command "LD Q, 0F0H" must be before the command that refers to the Q' register in the timer interrupt processing. Therefore, as shown in FIG. 235(b), it is preferable to set the command immediately after the command "EX ALL" on the second line. This can also be achieved by writing a command other than the command that refers to the Q' register after the command "EX ALL", and writing a command that refers to the Q' register after writing the command "LD Q, 0F0H". .

The total command size of the commands shown in Figure 235(b) is 2 bytes for the command “EX ALL” on the 2nd line + 1 byte for the command “LD Q,0F0H” on the 3rd line + 2 bytes for the command “EX ALL” on the 5th line. + 1 byte of the command “EI” on the 6th line + 2 bytes of the command “RETI” on the 7th line = 8 bytes, and the total execution cycle is 2 cycles on the 2nd line + 1 cycle on the 3rd line + 2 cycles on the 5th line + 1 cycle on the 6th line +7th line 4 cycles = 10 cycles. As can be understood by comparing FIG. 235(a) and FIG. 235(b), even if the setting of the Q' register is added, the increase is within the total command size = 1 byte and total execution cycle = 1 cycle.

As explained using FIG. 234, when the Q' register is set in the initialization process of the main process, the total command size = 5 bytes and the total execution cycle = 5 cycles are required. Similarly, when repeating the process through the loop processing of the main process, the total command size = 5 bytes and the total execution cycle = 5 cycles are required. On the other hand, if the Q' register is set in the timer interrupt process, the description for two commands "EX ALL" can be omitted, so the total command size is 1 byte and the total execution cycle is only 1 cycle. Therefore, if the Q' register is set only by timer interrupt processing, it is possible to at least suppress the increase in memory.

(Second embodiment)
Next, an example will be described in which the sub-register group 726b is associated with main processing, and the main register group 726a is associated with timer interrupt processing. Therefore, the main CPU 500a first switches from the main register group 726a to the sub-register group 726b, executes main processing by referring to the sub-register group 726b, and when a timer interrupt occurs, interrupts the main processing and temporarily The sub-register group 726b is switched to the main register group 726a to execute timer interrupt processing, and when the timer interrupt processing is completed, the main register group 726a is switched to the sub-register group 726b to restart the main processing.

Also, since the initial value of the Q register in the main register group 726a is F0h, there is no need to set another value, and only the Q' register in the sub-register group 726b is rewritten to F0h. Note that, as described above, it is necessary to set the Q' register before the command that refers to it is used. Therefore, for example, it is conceivable to initialize the Q' register in the initialization process of the main process (for example, the CPU initialization process in FIG. 82).

FIG. 236 is a diagram showing an example of a command for setting a value in the Q' register. Here, the main CPU 500a sets F0h in the Q' register in the initialization process of the main process. However, as described above, the main CPU 500a can update the contents of the Q register of the main register group 726a, which is the register group currently being targeted, but cannot access the Q' register of the sub register group 726b, which is another register group. Can not do it. Therefore, similar to FIG. 234, as shown in FIG. 236, the 8-bit registers (Q, A, F, B, C, D, E, H, L) in the main register group 726a are ) and 16-bit registers (IX, IY) to 8-bit registers (Q', A', F', B', C', D', E', H', L') in sub-register group 726b. and switch to 16-bit registers (IX', IY').

Then, F0h is set in the Q' register by the command "LD Q,0F0H" on the second line. Thereafter, the main processing will be performed with reference to the sub-register group 726b.

The total command size of the commands shown in FIG. 236 is 2 bytes for the command "EX ALL" on the first line + 1 byte for the command "LD Q, 0F0H" on the second line = 3 bytes, and the total execution cycle is as follows: Cycle+2nd row 1 cycle=3 cycles.

As explained using FIG. 234, after making the main register group 726a correspond to the main process and making the sub-register group 726b correspond to the timer interrupt process, the Q' register is set in the initialization process of the main process. Therefore, total command size = 5 bytes and total execution cycle = 5 cycles are required. Similarly, when repeatedly setting the Q' register through the loop processing of the main processing, the total command size = 5 bytes and the total execution cycle = 5 cycles are required. On the other hand, if the sub-register group 726b is made to correspond to the main processing, the main register group 726a is made to correspond to the timer interrupt processing, and the Q' register is set in the initialization processing of the main processing, one command "EX ALL" will be issued. Since it is possible to omit the description of the number of minutes, the total command size can be suppressed to 3 bytes, and the total execution cycle can be suppressed to 3 cycles.

Furthermore, as described above, the Q' register is frequently used, so the value of the Q' register should be set reliably. Therefore, instead of or in addition to setting the Q' register only once in the initialization process of the main process, it may be possible to repeatedly set the Q' register throughout the loop process of the main process. For example, of the command group in Figure 236, only the command "EX ALL" on the first line is executed in the initialization process of the main process, and the command "LD Q, 0F0H" on the second line of the command group in Figure 236 is executed. , FIG. 88 to FIG. 97 (slot machine 400). By doing this, it is possible to set F0h in the Q' register each time according to the loop processing of the main processing, so even if the Q' register becomes the initial value F1h, the Q The value of the 'register can be reliably set to F0h, and the value of the Q' register can be stably maintained.

However, since a command that refers to the Q' register is used in the main processing, F0h is set in the Q' register before the command that refers to the Q' register is used.

Also, consider setting the Q' register only once during initialization processing of the main processing, or instead of or in addition to setting it repeatedly during the loop processing of the main processing, setting it repeatedly through timer interrupt processing. It will be done. By doing this, you can set F0h in the Q' register every time a timer interrupt occurs, so even if the Q' register becomes the initial value F1h, the value of the Q' register will not change. can be reliably set to F0h, and the value of the Q' register can be stably maintained.

FIG. 237 is a diagram showing an example of a command for setting a value in the Q' register. Here, the Q' register is set in timer interrupt processing. Note that the main CPU 500a targets the sub-register group 726b until the timer interrupt processing occurs (in the main processing). Specifically, the index “TMR_IPT:” in the first line of FIG. 237 indicates the start address of the timer interrupt process. The command "LD Q, 0F0H" on the second line sets F0h in the Q' register. Then, in order to save the values of the registers used in the main processing, the 8-bit registers (Q', A', F', B', C ', D', E', H', L') and 16-bit registers (IX', IY'), 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY). In this way, the target becomes the main register group 726a. Subsequently, after executing the necessary processing in the timer interrupt processing, the main register group 726a is switched to the sub-register group 726b by the command "EX ALL" on the fifth line. Interruption is enabled by the command "EI" on the 6th line. Incidentally, here, even if the command "EI" is executed before returning from the subroutine to the main processing, interrupts are appropriately permitted. Then, the command "RETI" on the seventh line returns to the main processing.

The total command size of the commands shown in Figure 237 is: 2nd line command “LD Q,0F0H” 1 byte + 3rd line command “EX ALL” 2 bytes + 5th line command “EX ALL” 2 bytes + 6th line 1 byte of the command "EI" + 2 bytes of the command "RETI" on the 7th line = 8 bytes, and the total execution cycle is 1 cycle on the 2nd line + 2 cycles on the 3rd line + 2 cycles on the 5th line + 1 cycle on the 6th line + 7th line 4 cycles = 10 cycles.

Note that the position of the command "LD Q, 0F0H" must be before the command "EX ALL" is executed in the timer interrupt processing. Therefore, it is preferable to set it immediately before the command "EX ALL" on the third line.

Here, the sub-register group 726b corresponds to the main processing, the main register group 726a corresponds to the timer interrupt processing, and the Q' register is set only once in the initialization processing of the main processing. It is performed repeatedly through loop processing, or it is performed repeatedly through timer interrupt processing. In either case, the command " Since you can omit the description of one "EX ALL", the total command size = 3 bytes and the total execution cycle = 3 cycles, but even if the Q' register becomes the initial value F1h, Also, the value of the Q' register can be reliably set to F0h, and the value of the Q' register can be stably maintained.

<Switching register group>
By the way, when a timer interrupt occurs during execution of main processing, the register continues to be used in the timer interrupt processing, regardless of the value of the register at the timing of the interrupt. Therefore, when a timer interrupt occurs, it is necessary to separately hold the contents of the register at the interrupt timing. For example, in order to smoothly restart main processing when returning from timer interrupt processing to main processing, the contents of the register at the interrupt timing must be saved to the stack area of main RAM 500c using a save command. However, the number of save commands increases depending on the number of registers to be saved, and not only the command size but also the number of cycles increases.

In this embodiment, as described above, the 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers in the main register group 726a are (IX, IY), 8-bit registers (Q', A', F', B', C', D', E', H', L') and 16-bit registers (Q', A', F', B', L') in sub-register group 726b. IX', IY'). With such a command, when switching between main processing and timer interrupt processing, the target register group can be saved at once, and the other saved register groups can be restored at once. The command "EX ALL" has a command size of 2 bytes and requires only 2 cycles.

Further, the command "CALLEX mn" and the command "RETEX" are used to switch between the first register bank 726 and the second register bank 728 in units of register banks including the main register group 726a and the sub-register group 726b. With such a command, the target register bank can be saved at once, and other saved register banks can be restored at once. For such a command "CALLEX mn", if the address mn is limited to 2000h to 20FFh, the command size can be suppressed to 2 bytes and the number of cycles is only 4. The command "RETEX" has a command size of 2 bytes and requires only 5 cycles. Hereinafter, such a switching command will be explained by applying it to the first embodiment and the second embodiment.

FIG. 238 is a diagram for explaining the transition of register banks and register groups. As described above, in the example (first embodiment) in which the main register group 726a corresponds to main processing and the sub-register group 726b corresponds to timer interrupt processing, the main CPU 500a refers to the main register group 726a. The main processing is executed sequentially, and when a timer interrupt occurs, the main processing is interrupted, the command "EX ALL" is used to temporarily switch from the main register group 726a to the sub register group 726b (1), and the timer interrupt processing is started. When the timer interrupt processing is completed, the sub register group 726b is switched to the main register group 726a by the command "EX ALL" (2), and the main processing is restarted. Furthermore, at a predetermined timing in the game control process, the main CPU 500a switches from the first register bank 726 to the second register bank 728 (3) using the command "CALLEX mn", executes the process outside the game control, and controls the game. When the external processing is completed, the second register bank 728 is switched to the first register bank 726 by the command "RETEX" (4), and the game control processing is restarted.

Furthermore, in the example (second embodiment) in which the sub-register group 726b corresponds to main processing and the main register group 726a corresponds to timer interrupt processing, the main CPU 500a first uses the command "EX ALL" to Switch from the group 726a to the sub-register group 726b (1), execute the main processing with reference to the sub-register group 726b, interrupt the main processing when a timer interrupt occurs, and use the command "EX ALL" to temporarily execute the main processing. Switch from the sub-register group 726b to the main register group 726a (2), execute timer interrupt processing, and when the timer interrupt processing is finished, switch from the main register group 726a to the sub-register group 726b using the command "EX ALL" ( 1) Restart main processing. Furthermore, at a predetermined timing in the game control process, the main CPU 500a switches from the first register bank 726 to the second register bank 728 (3) using the command "CALLEX mn", executes the process outside the game control, and controls the game. When the external processing is completed, the second register bank 728 is switched to the first register bank 726 by the command "RETEX" (4), and the game control processing is restarted.

In this way, regarding the two register banks, the first register bank 726 is made to correspond to the used area, the second register bank 728 is made to correspond to another area, and the main register group 726a and sub register group 726b of the first register bank 726 are made to correspond to the used area. By making one correspond to main processing and the other to correspond to timer interrupt processing, independence and exclusivity of each area can be ensured. In addition to these switches, by using a switch command to switch at least the entire register group, it is possible to reduce the command size and number of cycles while ensuring the independence and exclusivity of each area. . Note that, as described using FIG. 238, one of the main register group 726a and sub-register group 726b of the first register bank 726 is made to correspond to the main processing, the other is made to correspond to the timer interrupt processing, and the second Although the explanation has been given using an example in which one or both of the main register group 728a and the sub-register group 728b of the register bank 728 are made to correspond to processing outside of gaming control, for example, registers made to correspond to main processing, timer interrupt processing, processing outside of gaming control Banks and register groups can be set arbitrarily. For example, one of the main register group 728a and sub-register group 728b of the second register bank 728 is made to correspond to main processing, the other is made to correspond to timer interrupt processing, and the main register group 726a and sub-register group 726b of the first register bank 726 are made to correspond to the timer interrupt processing. The main register group 726a of the first register bank 726 is made to correspond to the main processing, the main register group 728a of the second register bank 728 is made to correspond to the timer interrupt processing, and the main register group 726a of the first register bank 726 is made to correspond to the One or both of the sub-register group 726b of the first register bank 726 and the sub-register group 728b of the second register bank 728 may be made to correspond to processing outside of game control.

Next, a case where the main CPU 500a is powered off will be described. When the main CPU 500a is powered off while executing main processing, the main CPU 500a inputs the register group of the register bank corresponding to the main processing (the main register group 726a or the sub register group 726b of the first register bank 726) using a command. The data is saved to the stack area of the main RAM 500c through "PUSH" (for example, command "PUSH ALL"), and then, for example, the power-off saving process shown in FIG. 97 is performed.

Here, the register group (main register group 726a or sub-register group 726b) corresponding to the main processing is saved, but the saving of the register group corresponding to the timer interrupt processing and processing outside game control is omitted. Necessary information is set in the registers corresponding to such timer interrupt processing after the timer interrupt processing is started. In other words, the contents of the registers are not inherited from the main processing and are referenced only within the timer interrupt processing. , when the timer interrupt processing ends, the contents of that register are no longer needed. Similarly, the necessary information is set in the register group corresponding to the processing outside of gaming control after the processing outside of gaming control is started. It is referenced only within the process, and once the non-gaming control process ends, the contents of that register are no longer needed. Therefore, there is no problem even if the register group corresponding to timer interrupt processing and non-gaming control processing is saved.

Furthermore, if the power is cut off not during the main processing but during the timer interrupt processing or processing outside of game control, the processing will be performed as follows. Timer interrupt processing has priority over interrupts caused by power-off. That is, even if a power-off interrupt occurs during timer interrupt processing, the power-off save processing is not executed immediately, but is executed only after the timer interrupt processing is completed. In other words, the timer interrupt process has been completed by the time the power-off save process starts. Note that, as described above, the timer interrupt process is referenced only within the timer interrupt process, and once the timer interrupt process is completed, the contents of the register are no longer needed. Therefore, even if the power is cut off during timer interrupt processing, no problem will occur because there is no need to save the contents of the registers related to the timer interrupt processing at the timing when the power-off saving processing starts. Similarly, processing outside of game control is given priority over interruptions due to power cutoff. That is, even if a power-off interruption occurs during a process outside game control, the save process at power-off is not executed immediately, but is executed only after the process outside game control ends. In other words, the timer interrupt process has been completed by the time the power-off save process starts. In addition, as mentioned above, the process outside game control is referenced only within the process outside game control, and when the process outside game control ends, the contents of the register become unnecessary. Therefore, even if the power is cut off during the non-gaming control process, no problem will occur because there is no need to save the contents of the register related to the non-gaming control process at the timing when the power-off saving process starts.

Note that when the power is turned off, information on the register bank and register group at the time of the power off is erased. When the power is restored after the power is turned off, the initial values of the register bank and register group are set to the first register bank 726 and its main register group 726a. Therefore, the first process executed when the power is restored is the main process, and the first register bank 726 and its main register group 726a are made to correspond to the main process. In this way, after the power is restored, the main processing will be started. Here, since the first register bank 726 and its main register group 726a are evacuated when the power is turned off, main processing can be performed stably and reliably.

In the embodiment described above, the first register group is the main register group, the first register is the Q register, the first value is F0h, the second register group is the sub-register group, and the second register is Q'. The explanation has been given using an example in which the first register group is a sub-register group, the first register is a Q' register, and the first value is a Q' register. F1h, the second register group may be the main register group, the second register may be the Q register, and the second value may be F1h. In such a configuration, F1h is rewritten to the Q register of the main register group. Further, in the above-described embodiment, the first register bank is the first register bank 726 and the second register bank is the second register bank 728. However, the first register bank is not limited to such a case. The register bank may be the second register bank 728, and the second register bank may be the first register bank 726.

<Register access method>
By the way, in a conventional microprocessor, there is an address space (memory space) to which the main ROM 500b and main RAM 500c are allocated, and an address space (I/O space) to which the input/output unit 704 (device corresponding to the input/output unit 704) is allocated. ) were managed independently. Here, the memory space to which the main ROM 500b and the main RAM 500c are allocated is sometimes called a memory map, and the I/O space to which the input/output unit 704 is allocated is sometimes called an I/O map.

Conventional microprocessors must access each memory space and I/O space using dedicated instructions. For example, when a conventional microprocessor uses instructions dedicated to the memory space of the main ROM 500b and main RAM 500c, access to the main ROM 500b and main RAM 500c becomes possible by enabling the memory request (MREQ) terminal. . Furthermore, when a conventional microprocessor uses an instruction dedicated to the I/O space of the input/output unit 704, the I/O request (IORQ) terminal is enabled (valid), allowing access to the input/output unit 704. becomes. Therefore, conventional microprocessors had to use different instructions depending on whether the target to be accessed was the main ROM 500b, main RAM 500c, or the input/output section 704. Here, an access method provided for a conventional microprocessor to access the input/output unit 704 (device) is called an I/O mapped I/O method. By commands based on the I/O mapped I/O method, the main CPU 500a can read information from the input/output unit 704 to the register or write information from the register to the input/output unit 704.

However, as described above, in this embodiment, the address space of the input/output section 704 and the address spaces of the main ROM 500b and main RAM 500c are integrated, and the input/output section 704 is allocated to memory spaces FE00h to FFFFh. Therefore, there is no concept of I/O space, and the main CPU 500a can access the input/output unit 704 assigned to FE00h to FFFFh of the memory space by using instructions dedicated to the memory space. Here, the access method provided for the main CPU (processor) 500a to access the main ROM (storage means) 500b and main RAM (storage means) 500c is called a memory mapped I/O method. The main CPU 500a can read information from the input/output unit 704 to the register or write information from the register to the input/output unit 704 using commands based on the memory mapped I/O method.

As described above, in this embodiment, the main CPU 500a accesses the input/output unit 704 using the memory mapped I/O method. On the other hand, from the viewpoint of versatility, such as the ability to use conventional microprocessor programs as they are, in this embodiment, access is also possible using the I/O mapped I/O method. Therefore, in addition to the memory mapped I/O method, the main CPU 500a can access the input/output unit 704 using the I/O mapped I/O method, using a part of the memory space as an I/O space. . Although it was possible for conventional microprocessors to access the input/output unit 704 using the memory mapped I/O method, If the memory mapped I/O method is selected, the I/O mapped I/O method cannot be used.

FIG. 239 is an explanatory diagram for explaining how the access method is used. The memory mapped I/O method has the advantage of being able to use a large number of commands prepared for accessing the main ROM 500b and the main RAM 500c, such as LD instructions and LDIR instructions. On the other hand, the memory mapped I/O method has a disadvantage that the command size is larger than the I/O mapped I/O method when simply reading and writing to the input/output unit 704 is performed. On the other hand, the I/O mapped I/O method has the advantage that when simply reading and writing to the input/output unit 704, the command size is smaller than the memory mapped I/O method. On the other hand, the I/O mapped I/O method has a drawback that only limited commands (commands) prepared for accessing the input/output unit 704 can be used, such as an IN command and an OUT command.

In a program, there is usually a lot of simple reading and writing of the input/output unit 704, so by using the I/O mapped I/O method instead of the memory mapped I/O method, it is possible to reduce the command size. . For example, if you want to read the value stored at a predetermined address of the input/output unit 704 to the A register, use the memory mapped I/O command "LD A, (mn)" (mn is a 2-byte integer). , the command size requires 3 bytes, but if you use the I/O mapped I/O method command "IN A, (g)" (g is a 1-byte integer), the command size only needs 2 bytes. . Therefore, the I/O mapped I/O method is usually used.

However, in some processes of a program, it is better to use memory mapped I/O method commands (instructions) than I/O mapped I/O method commands to perform game control processing. It may be possible to reduce the capacity of the control area for this purpose. Specifically, rather than accessing the same address of the input/output unit 704 allocated to the memory space with a command based on the I/O mapped I/O method such as an IN command or an OUT command, a memory mapped I/O command such as an LD command is used. Accessing with commands using the /O method may result in a smaller total command size. Therefore, an appropriate access method that reduces the total command size is used here, depending on the content of the processing.

FIG. 240 is a flowchart for explaining an example of a subcommand transmission process, and FIG. 241 is a diagram showing an example of a specific command for realizing the subcommand transmission process. Such subcommand transmission processing is executed in step S100-65 of FIG. 23 and step S3100-11 of FIG. 98, which are described above. In the sub-command transmission process, a command message (command) is transmitted to the sub-control boards 330 and 502 through the transmission buffer (FIFO). For convenience of explanation, here, an example will be given in which the main CPU 500a executes the subcommand transmission processing S3100-11, and processing related to subcommand accumulated data that is not related to this embodiment will be omitted. The numerical values in step S in the explanation of FIG. 240 will be used only in the explanation of this figure.

Note that here, message 1, message 2, message 3, and message 4 that constitute the 4-byte command message to be sent to the sub-control board 502 are set in the D register, E register, B register, and C register, respectively. . However, depending on the command message to be transmitted, messages 2 to 4 may be set after the fact. Further, if no message is set for messages 3 and 4, predetermined values may be set as messages 3 and 4.

As shown in FIG. 240, the main CPU 500a first saves the values of each register (S1), and determines whether messages 2 to 4 have already been set based on message 1 (S2). If the messages 2 to 4 have been set (YES in S2), the main CPU 500a moves to step S6; if not already set (NO in S2), the main CPU 500a sets the value acquired from the main RAM 500c in the message 2 ( S3), it is determined whether messages 3 and 4 have already been set based on message 1 (S4). If the messages 3 and 4 have been set (YES in S4), the main CPU 500a proceeds to step S6, and if they have not been set (NO in S4), the main CPU 500a sets predetermined values in the messages 3 and 4 (S5). ).

Next, the main CPU 500a sets the destination address (S6), sets message 2 as the augend (S7), and prohibits interrupts (S8). The main CPU 500a outputs the messages 1 to 4 (S9), calculates the checksums of the messages 1 to 4 (S10), and also outputs the calculated checksums (S11). Finally, the main CPU 500a allows interrupts (S12) and restores the saved values of each register (S13).

Specifically, the index "CMDPROC" in the first line of FIG. 241 indicates the start address of the subcommand transmission process. The subcommand transmission process is called by the index "CMDPROC". The command "PUSH HL" on the second line saves the value of the HL register to the stack area, and the command "PUSH BC" on the third line saves the value of the BC register to the stack area. The commands on the second and third lines correspond to step S1 in FIG. 240, which saves the register value.

The value of the D register, that is, the value of message 1, is set to the A register by the command "LD A, D" on the 4th line of FIG. , the value of the A register and the fixed value "B0H" are compared, and if the result is less than B0H (if the carry flag is set), the process moves to the index "CMDPROC01" on the 12th line. In this way, if the value of message 1 is less than B0H, it is possible to skip the next process and move to the index "CMDPROC01" on the 12th line. The commands on the fourth and fifth lines correspond to step S2 in FIG. 240, which moves to step S6 if messages 2 to 4 have already been set.

The command "LDQ A, (E)" on the 6th line of Figure 241 sets the value of the Q register as the upper 1 byte of the address, the value of the E register as the lower 1 byte of the address, and stores them in the memory area indicated by the address. The 1-byte value (telegram 2) is set in the A register, and the value of the A register, that is, the telegram 2, is set in the E register by the command "LD E, A" on the seventh line. The commands on the 6th and 7th lines correspond to step S3 in FIG. 240 for setting the message 2.

If bit 3 of the D register value (telegram 1) is 0 (if the zero flag is set) by the command "JBIT Z, 3, D, CMDPROC01" on the 8th line of Figure 241, the index on the 12th line Move to “CMDPROC01”. In this way, if bit 3 of message 1 is 0, it is possible to skip the next process and move to the index "CMDPROC01" on the 12th line. The command on the 8th line corresponds to step S4 in FIG. 240, which moves to step S6 if messages 3 and 4 have already been set.

The command "IN HL, (@CID______)" on the 9th line of FIG. The 2-byte value stored in the memory area indicated by is input to the HL register. Specifically, the 1-byte value stored in the memory area indicated by that address is input to the L register, and the 1-byte value stored in the memory area indicated by the value obtained by adding 1 to that address is input to the H register. is input. The command "LD B, H" on the 10th line sets the value of the H register to the B register, and the command "LD C, L" on the 11th line sets the value of the L register to the C register. The commands on the 9th to 11th lines correspond to step S5 in FIG. 240 for setting messages 3 and 4.

Subsequently, the value of the C register is set to the H register by the command "LD H, C" on the 13th line of FIG. Here, the C register used in the OUT command is released by transferring the message 4 stored in the C register to the H register. The symbol "@S1DT___" itself is set in the C register by the command "LD C, @S1DT___" on the 14th line. Note that the symbol "@S1DT___" indicates a transmission buffer (FIFO) of an asynchronous serial communication circuit dedicated to transmission. The commands on the 13th and 14th lines correspond to step S6 in FIG. 240 for setting the destination address.

The value of the E register (telegram 2) is set in the A register by the command "LD A, E" on the 15th line of FIG. 241. This is because the value of the A register is used as the augend when calculating the checksum in step S10 of FIG. The command on the 15th line corresponds to step S7 in FIG. 240, which sets message 2 in the A register. Then, the command "DI" on the 16th line disables interrupts. The command on the 16th line corresponds to step S8 in FIG. 240.

The command "OUT (C), D" on the 17th line of FIG. The value (telegram 1) is output. The command "OUT (C), A" on the 18th line sets the value of the U register to the upper 1 byte of the address, the value of the C register to the lower 1 byte, and stores the value of the A register (telegram) in the memory area indicated by the address. 2) is output. The command "OUT (C), B" on the 19th line sets the value of the U register as the upper 1 byte of the address, the value of the C register as the lower 1 byte, and stores the value of the B register (telegram) in the memory area indicated by the address. 3) is output. The command "OUT (C), H" on the 20th line sets the value of the U register as the upper 1 byte of the address, the value of the C register as the lower 1 byte, and stores the value of the H register (telegram) in the memory area indicated by the address. 4) is output. Here, data is stored in the symbol "@S1DT______" itself (address value) in the order of D register, A register (E register), B register, and H register (C register), that is, in the order of telegrams 1, 2, 3, and 4. is being output. The commands on lines 17 to 20 correspond to step S9 in FIG. 240, which outputs messages 1 to 4.

The command "ADD A, D" on the 21st line in FIG. 241 adds the value of the D register (telegram 1) to the value of the A register (telegram 2), and the result is held in the A register. The command "ADD A, B" on the 22nd line adds the value of the B register (telegram 3) to the value of the A register (checksum value), and the result is held in the A register. The command "ADD A,H" on the 23rd line adds the value of the H register (telegram 4) to the value of the A register (checksum value), and the result is held in the A register. The commands on the 21st to 23rd lines correspond to step S10 in FIG. 240, which calculates the checksums of the messages 1 to 4.

The command "OUT (C), A" on the 24th line of FIG. The value (checksum value) is output. In this way, a total of 5 bytes of command messages including messages 1 to 4 and the checksum value are output to the transmission buffer. The command on the 24th line corresponds to step S11 in FIG. 240, which outputs the calculated checksum. Then, the command "EI" on the 25th line permits interrupts. This command on the 25th line corresponds to step S12 in FIG. 240.

The command "POP BC" on the 26th line of FIG. 241 restores the data saved in the stack area to the BC register, and the command "POP HL" on the 27th line returns the data saved in the stack area to the HL register. Returned to register. The commands on the 26th and 27th lines correspond to step S13 in FIG. 240, which restores the register value. Then, the command "RET" on the 28th line returns to the calling process.

In FIG. 241, the subcommand transmission process in FIG. 240 is realized by an I/O mapped I/O method using IN commands and OUT commands. However, as described above, in some processes of a program, the command size may be smaller if memory-mapped I/O instructions are used. An example in which the memory mapped I/O method is applied to some processing will be described below.

FIG. 242 is a diagram illustrating an example of another command for realizing subcommand transmission processing. Here, as in FIG. 241, 4-byte telegrams 1, 2, 3, and 4 to be sent to the sub-control board 502 are set in the D register, E register, B register, and C register, respectively.

Comparing the command group in FIG. 241 and the command group in FIG. 242, the command group shown in (1) corresponding to step S5 and the command group shown in (2) corresponding to steps S6 to S11 are different. ing. Here, the difference in total command size will be explained by focusing on the command group (1) and the command group (2).

Regarding the command group in (1), the 2-byte value stored in the memory area indicated by the symbol "@CID______" is set in the BC register by the command "LD BC, (@CID______)" on the 9th line of FIG. Ru. Specifically, the 1-byte value stored in the memory area indicated by the symbol "@CID______" is input to the C register, and the 1-byte value stored in the memory area indicated by the symbol "@CID______" + 1 is input to the B register. is input. The command on the 9th line corresponds to step S5 in FIG. 240 for setting messages 3 and 4.

In the example of FIG. 241, since the I/O mapped I/O method is used, the HL register can be selected as the setting destination for the value input by the IN command, but the BC register cannot be selected. In other words, the command "IN BC, (mn)" (mn is a 2-byte integer) is not prepared as a command. Therefore, in the example of FIG. 241, the 2-byte value stored in the memory area indicated by the symbol "@CID______" must be temporarily held in the HL register, and then transferred to the B register and C register, respectively. On the other hand, in the memory mapped I/O method shown in FIG. 242, by using the LD instruction, the 2-byte value stored in the memory area indicated by the symbol "@CID______" is directly set in the BC register. be able to.

Here, the total command size of the command group in (1) in Figure 241 is 3 bytes for the command "IN HL, (@CID______)" on the 9th line + 1 byte for the command "LD B, H" on the 10th line + 1 byte for the command "LD B, H" on the 11th line. 1 byte = 5 bytes for the command "LD C,L" in Figure 242, whereas the total command size of the command group (commands) in (1) of Figure 242 is the command "LD BC, (@CID______)" on the 9th line. ” is 4 bytes. Therefore, it can be understood that the total command size can be reduced by 1 byte by changing the I/O mapped I/O method to the memory mapped I/O method.

Subsequently, regarding the command group (2), the 2-byte value of the symbol "@S2DT___" itself is set in the HL register by the command "LD HL, @S2DT___" on the 11th line of FIG. 242. Note that the symbol "@S2DT___" indicates an input buffer of the asynchronous serial communication circuit dedicated to transmission. The command on the 11th line corresponds to step S6 in FIG. 240 for setting the destination address. In the example of FIG. 241, since the I/O mapped I/O method is used, the C register had to be released in order to use the OUT instruction. In contrast, in the memory mapped I/O method, there is no need to release the C register, and the destination address can be held in the HL register. Therefore, in the example of FIG. 242, the command "LD H, C" on the 13th line of FIG. 241 can be deleted.

The value of the E register (telegram 2) is set to the A register by the command "LD A, E" on the 12th line of FIG. 242. The command on the 12th line corresponds to step S7 in FIG. 240, which sets message 2 in the A register. Then, the command "DI" on the 13th line disables interrupts. The command on the 13th line corresponds to step S8 in FIG. 240.

The command "LD (HL), D" on the 14th line of FIG. 242 stores the value of the D register (telegram 1) in the memory area indicated by the address of the HL register. The command "LD (HL), A" on the 15th line stores the value of the A register (telegram 2) in the memory area indicated by the address of the HL register. The command "LD (HL), B" on the 16th line stores the value of the B register (telegram 3) in the memory area indicated by the address of the HL register. The command "LD (HL), C" on the 17th line stores the value of the C register (telegram 4) in the memory area indicated by the address of the HL register. Here, data is stored in the symbol "@S1DT______" itself (address value) in the order of D register, A register (E register), B register, and C register, that is, in the order of telegrams 1, 2, 3, and 4, As a result, data will be output to the transmission buffer in the order of messages 1, 2, 3, and 4. The commands on lines 14 to 17 correspond to step S9 in FIG. 240, which outputs messages 1 to 4.

The command "ADD A, D" on the 18th line of FIG. 242 adds the value of the D register (telegram 1) to the value of the A register (telegram 2), and the result is held in the A register. The command "ADD A, B" on the 19th line adds the value of the B register (telegram 3) to the value of the A register (checksum value), and the result is held in the A register. The command "ADD A, C" on the 20th line adds the value of the C register (telegram 4) to the value of the A register (checksum value), and the result is held in the A register. The commands on the 18th to 20th lines correspond to step S10 in FIG. 240, which calculates the checksums of the messages 1 to 4.

The command "LD (HL), A" on the 21st line of FIG. 242 stores the value of the A register (checksum value) in the memory area indicated by the address of the HL register. In this way, a command message of a total of 5 bytes including messages 1 to 4 and the checksum value is stored in the transmission buffer, and as a result, the instruction message is output to the transmission buffer. The command on the 21st line corresponds to step S11 in FIG. 240, which outputs the calculated checksum.

In the example of FIG. 241, the OUT command is used to output to the input/output unit 704 using the I/O mapped I/O method. On the other hand, in the memory mapped I/O method, LD instructions can be used. Therefore, the command size can be reduced by holding the destination address in the HL register instead of the C register and storing the value of each register in the memory area indicated by the address of the HL register using the LD command.

Here, the total command size of the command group in (2) in Figure 241 is: 1 byte of the command "LD H, C" on the 13th line + 2 bytes of the command "LD C, @S1DT______" on the 14th line + 2 bytes of the command on the 15th line “LD A, E” 1 byte + 16th line command “DI” 1 byte + 17th line command “OUT (C), D” 2 bytes + 18th line command “OUT (C), A” 2 bytes + 19th line 2nd command “OUT (C), B” 2 bytes + 20th line command “OUT (C), H” 2 bytes + 21st line command “ADD A, D” 1 byte + 22nd line command “ADD A, B” 1 byte + 23rd line command “ADD A,H” 1 byte + 24th line command “OUT (C), A” 2 bytes = 18 bytes, whereas the command group in (2) in Figure 242 The total command size is 3 bytes for the command "LD HL, @S2DT______" on the 11th line + 1 byte for the command "LD A, E" on the 12th line + 1 byte for the command "DI" on the 13th line + 1 byte for the command "LD" on the 14th line. (HL), D” 1 byte + 15th line command “LD (HL), A” 1 byte + 16th line command “LD (HL), B” 1 byte + 17th line command “LD (HL), C ” 1 byte + 18th line command “ADD A, D” 1 byte + 19th line command “ADD A, B” 1 byte + 20th line command “ADD A, C” 1 byte + 21st line command “LD ( HL), A'' 1 byte = 13 bytes.

Therefore, for the command group (2), by changing the I/O mapped I/O method to the memory mapped I/O method, the total command size can be reduced by 5 bytes. As can be understood by comparing the command group in FIG. 241 (2) with the command group in FIG. 242 (2), the total command size can be reduced by 1 byte each time an OUT instruction is replaced with an LD instruction.

In this way, in this embodiment, the input/output unit 704 is accessed using the I/O mapped I/O method, and depending on the content of the process, the input/output unit is accessed using the memory mapped I/O method, which reduces the total command size. 704 is being accessed. In this way, by mixing the I/O mapped I/O method and the memory mapped I/O method in the same program and applying an access method that reduces the total command size depending on the processing content, the command It is possible to shorten the time and secure the capacity of the control area for performing game control processing.

<Usage example 1 of memory mapped I/O method>
As described above, conventional microprocessors access the input/output unit 704 using the I/O mapped I/O method. In this case, the I/O space that can be allocated to the input/output unit 704 is limited to 256 bytes. In other words, in the conventional microprocessor, the input/output unit 704 can be specified using only 1 byte of address information.

FIG. 243 is a diagram showing a part of a command group for implementing CPU initialization processing, and FIG. 244 is a diagram showing a table referred to in CPU initialization processing. Here, for convenience of explanation, the initial setting process (step S100-1 in FIG. 22 and step S2000-1 in FIG. 82) of the CPU initialization process described above will be explained. In the initial setting process, the input/output unit 704 is initialized by setting setting data in the input/output unit 704 (built-in register). Note that here, an example will be given in which the main CPU 500a executes the initial setting process S2000-1.

The command "LD HL, T_CPU_REG" in the first line of FIG. 243 sets the start address "T_CPU_REG" of the data group of the CPU built-in register setting data table, which is the read source, in the HL register. The symbol "@NUM_CPU_REG" itself is set in the B register by the command "LD B, @NUM_CPU_REG" on the second line.

Note that, as can be understood by referring to the 48th line of the CPU built-in register setting data table in FIG. 244, the command "EQU ($-T_CPU_REG)/2" is written in the symbol "@NUM_CPU_REG". Here, "$" is the address next to the final address of the data group that is the transfer source, that is, the symbol "@NUM_CPU_REG" itself, and "T_CPU_REG" is the first address of the data group that is the transfer source, so $- The value of T_CPU_REG (1-byte value indicating the number of data) is the total number of bytes of the 1-byte value, and by dividing that value by 2, which is the number of combinations of address and value, the number of setting data is derived. . For example, in the example of FIG. 244, the number of setting data is 30/2=15.

The index “INITIAL01” in the third line of FIG. 243 indicates the start address of the repetitive process. By the command "LDIN AC, (HL)" on the fourth line, the 1-byte value stored in the memory area indicated by the address of the HL register is stored in the C register, and the address of the value obtained by adding "1" to the HL register is stored. The 1-byte value stored in the memory area indicated by is stored in the A register. The command "OUT (C), A" on the fifth line outputs the value of the A register (setting data) to the memory area (built-in register) indicated by the address of the C register.

For example, if the HL register has the value of the address "T_CPU_REG", the 1-byte value "@PT0PR__" on the 3rd line of FIG. 244 is stored in the C register, and the 1-byte value "160" on the 4th line of FIG. is stored in the A register. Then, the value "160" of the A register is output to the memory area indicated by the symbol "@PT0PR__" of the C register.

Next, the value of the B register is decremented (subtracted by 1) by the command "DJNZ INITIAL01" on the 6th line of Figure 243, and if the decremented result is not 0, it moves to the index "INITIAL01" on the 3rd line. However, if the decremented result is 0, the process moves to the command next to the command in question. Here, since the number of data is "15", the value of the B register becomes 0 when the process starting from the index "INITIAL01" is repeated 15 times.

In this way, the total command size of the initial setting process commands shown in Figure 243 is: 3 bytes of the command "LD HL, T_CPU_REG" in the 1st line + 2 bytes of the command "LD B, @NUM_CPU_REG" in the 2nd line + 2 bytes of the command "LD B, @NUM_CPU_REG" in the 4th line. 2 bytes of the command "LDIN AC, (HL)" + 2 bytes of the command "OUT (C), A" in the 5th line + 2 bytes of the command "DJNZ INITIAL01" in the 6th line = 11 bytes.

As described above, in this embodiment, the address space of the input/output unit 704 is integrated with the address spaces of the main ROM 500b and the main RAM 500c. Therefore, the main CPU 500a accesses the input/output unit 704 through addresses FE00h to FFFFh in the memory space. In this case, the memory space to which the input/output unit 704 can be allocated is 512 bytes. By increasing the memory space in this way, the number of input/output units 704 that can be allocated can also be increased. On the other hand, since the memory space is larger than 256 bytes, 2 bytes are required as an address for specifying the input/output section 704. For example, in this embodiment, some input/output units 704 are allocated in advance to FE00h to FEFFh, which are 256-byte areas of the memory space, and other input/output units 704 are allocated to 256-byte areas of the memory space. It is assigned to FF00h to FFFFh. Therefore, the main CPU 500a must change the value of the U register between "FEH" and "FFH" every time the main CPU 500a accesses the input/output unit 704 whose address has a different upper byte. Here, another embodiment will be described in which the initial setting process shown in FIG. 243 is implemented using the U register.

FIG. 245 is a diagram showing another example of a part of a command group for realizing CPU initialization processing, and FIG. 246 is a diagram showing another example of a table referred to in CPU initialization processing. be. Here, as in FIGS. 243 and 244, for convenience of explanation, the main CPU 500a sets setting data in the input/output unit 704 (built-in register) using the I/O mapped I/O method.

By the command "LDF HL, T_CPU_REG" in the first line of FIG. 245, the start address "T_CPU_REG" of the data group in the CPU built-in register setting data table of FIG. 246 is set in the HL register. The symbol "@NUM_CPU_RG1" itself is set in the B register by the command "LD B, @NUM_CPU_RG1" on the second line.

Note that, as can be understood by referring to the 42nd line of the CPU built-in register setting data table in FIG. 246, the command "EQU ($-T_CPU_REG)/2" is written in the symbol "@NUM_CPU_RG1". Here, "$" is the symbol "@NUM_CPU_RG1" itself, and "T_CPU_REG" is the start address of the data group to be transferred, so the value of $-T_CPU_REG is the total number of bytes of the 1-byte value indicating the number of data. By dividing this value by 2, which is the number of combinations of addresses and values, the number of setting data is derived. For example, in the example of FIG. 246, the number of setting data is 26/2=13.

The command "LD U,0FEH" on the third line in FIG. 245 sets "FEH", which is the upper byte of the address indicating the input/output unit 704, in the U register. Here, two values "FEH" and "FFH" are prepared as the upper addresses of the addresses indicating the plurality of input/output units 704, and the main CPU 500a selects the values each time according to the input/output unit 704 to be accessed. , changes the value of the U register, which is the upper byte. Note that the initial value of the U register is "FFH". Here, first, "FEH" is set in the U register ("FFH" is changed to "FEH"), and setting data is set for the input/output unit 704 whose upper address is "FEH".

The index “INITIAL01” in the fourth line of FIG. 245 indicates the start address of the repetitive process. The command "LDIN AC, (HL)" on the fifth line stores the value stored in the memory area indicated by the address of the HL register in the C register, and the value indicated by the address of the value obtained by adding "1" to the HL register. The value stored in the memory area is stored in the A register. The command "OUT (C), A" on the sixth line outputs the value of the A register (setting data) to the memory area (built-in register) indicated by the address of the C register.

For example, if the HL register has the value of the address "T_CPU_REG", the 1-byte value "@PT0PR___" (for example, "01H") in the third line of FIG. 246 is stored in the C register, and A 1-byte value "160" is stored in the A register. Then, the value "160" of the A register is output to the memory area indicated by the symbol "@PT0PR__" of the C register.

The command "DJNZ INITIAL01" on the 7th line of FIG. 245 decrements the value of the B register (subtracts "1"), and if the decremented result is not 0, moves to the index "INITIAL01" on the 4th line and decrements it. If the result is 0, the process moves to the command next to the command in question. Here, since the number of data is "13", the value of the B register becomes 0 when the process from the index "INITIAL01" is repeated 13 times. In this way, setting data regarding the thirteen input/output units 704 in the first stage of FIG. 246 is completed.

The command "LD U,0FFH" on the 8th line in FIG. 245 sets "FFH", which is the upper byte of the address indicating the input/output section 704, in the U register. As mentioned above, setting data has been completed for the input/output unit 704 whose upper address is “FEH” among the two values “FEH” and “FFH” as addresses indicating the input/output unit 704. Here, "FFH" is set in the U register, and setting data is set for the input/output unit 704 whose upper address is "FFH". Note that by setting "FFH" to the U register, the U register is returned to its initial value.

The symbol "@NUM_CPU_RG2" itself is set in the B register by the command "LD B, @NUM_CPU_RG2" on the 9th line of FIG. 245. As can be understood by referring to the 50th line of the CPU built-in register setting data table in Figure 246, the command "EQU ($-T_CPU_REG)/2-@NUM_CPU_RG1" is written in the symbol "@NUM_CPU_RG2". There is. Here, "$" is the symbol "@NUM_CPU_RG2" itself, and "T_CPU_REG" is the start address of the 1-byte data group that is the transfer source, so the value of $-T_CPU_REG is 30/2 = 15, and "@ Since "NUM_CPU_RG1" is 13, in the example of FIG. 246, the number of setting data is 15-13=2.

The index "INITIAL02" on the 10th line of FIG. 245 indicates the start address of the repetitive process. The command "LDIN AC, (HL)" on the 11th line stores the value stored in the memory area indicated by the address of the HL register in the C register, and the value indicated by the address of the HL register with "1" added. The value stored in the memory area is stored in the A register. The command "OUT (C), A" on the 12th line outputs the value of the A register (setting data) to the memory area (built-in register) indicated by the address of the C register.

For example, if the HL register is the symbol "@NUM_CPU_RG1" itself, the 1-byte value "@S1CM______" (for example, "2CH") on the 44th line of FIG. A 1-byte value "10000000B" is stored in the A register. Then, the value "10000000B" of the A register is output to the memory area indicated by the symbol "@S1CM___" of the C register.

Next, the value of the B register is decremented (subtracted by "1") by the command "DJNZ INITIAL02" on the 13th line of FIG. 245, and if the decremented result is not 0, it moves to the index "INITIAL02" on the 10th line. However, if the decremented result is 0, the process moves to the command next to the command in question. Here, since the number of data is "2", the value of the B register becomes 0 when the process from the index "INITIAL02" is repeated twice. In this way, setting data regarding the second input/output unit 704 in the latter stage of FIG. 246 is completed.

In this way, the total command size of the commands for the initial setting process shown in FIG. 245 is: 2 bytes of the command "LDF HL, T_CPU_REG" in the 1st line + 2 bytes of the command "LD B, @NUM_CPU_RG1" in the 2nd line + 2 bytes of the command "LDB, @NUM_CPU_RG1" in the 3rd line Command “LD U, 0FEH” 3 bytes + 5th line command “LDIN AC, (HL)” 2 bytes + 6th line command “OUT (C), A” 2 bytes + 7th line command “DJNZ INITIAL01” 2 Byte + 8th line command “LD U, 0FFH” 3 bytes + 9th line command “LD B, @NUM_CPU_RG2” 2 bytes + 11th line command “LDIN AC, (HL)” 2 bytes + 12th line command “OUT” (C), A" 2 bytes + 13th line command "DJNZ INITIAL02" 2 bytes = 24 bytes.

Here, since the U register must be changed in order to access the plurality of input/output units 704, the total command size is correspondingly larger compared to the example of FIG. 243. However, as mentioned above, in some processes in a program, the command size may be smaller if you use instructions in the memory mapped I/O method rather than the I/O mapped I/O method. be. Therefore, an example in which the memory mapped I/O method is applied to some processing will be described.

FIG. 247 is a diagram showing another example of a part of the command group for realizing CPU initialization processing. Here, unlike FIGS. 243 and 245, the main CPU 500a sets setting data in the input/output unit 704 (built-in register) using the memory mapped I/O method. Note that as the CPU built-in register setting data table referred to in the CPU initialization process, the CPU built-in register setting data table shown in FIG. 246 can be used as is, and therefore will be explained using FIG. 246.

The command "LDF HL, T_CPU_REG" in the first line of FIG. 247 sets the start address "T_CPU_REG" of the data group of the CPU built-in register setting data table (table containing transfer information) in FIG. 246 to the HL register (second register). is set to The symbol "@NUM_CPU_RG1" itself (the number to be transferred) is set in the B register (first register) by the command "LD B, @NUM_CPU_RG1" on the second line.

Note that, as can be understood by referring to the 42nd line of the CPU built-in register setting data table in FIG. 246, the command "EQU ($-T_CPU_REG)/2" is written in the symbol "@NUM_CPU_RG1". Here, the value of $-T_CPU_REG is the total number of bytes of a 1-byte value indicating the number of data, and if that value is divided by 2, which is the number of combinations of address and value, the number of set data is 26/2 = 13 becomes.

The command "LD Q, HIGH @PTOPR__" on the third line of FIG. 247 sets the value of the upper byte ("FEH") of the symbol "@PTOPR__" in the Q register. Here, in order to access the input/output section 704 using the memory mapped I/O method, the upper byte of the input/output section 704 is set in the QH register instead of the U register. As described above, two values "FEH" and "FFH" are prepared as addresses indicating the input/output unit 704, and the main CPU 500a selects the upper byte each time depending on the input/output unit 704 to be accessed. The value of the Q register is changed. Note that the initial value of the Q register is "F0H", which corresponds to the start address of the main RAM 500c. Here, first, "FEH" is set in the Q register (third register), and setting data is set for the input/output unit 704 whose upper address is "FEH".

The command "LDINTQR (HL)" on the fourth line in Figure 247 sets the value of the Q register to the upper 1 byte of the transfer destination address, and sets the value stored in the memory area indicated by the address of the HL register to the lower order of the transfer destination address. The value stored in the memory area indicated by the address of the HL register value plus "1" is transferred to the memory area indicated by the transfer destination address, and the value of the HL register is set to "2". is added to update the address to be transferred next, the value of the B register is decremented (subtracted by "1"), and the process is repeated until the decremented result becomes 0, that is, 13 times, which is the setting data. In this way, setting data regarding the thirteen input/output units 704 in the first stage of FIG. 246 is completed. In such an LDINTQR instruction, processing is executed without using registers other than the B register, HL register, and Q register, for example, the A register.

The symbol "@NUM_CPU_RG2" itself (the number to be transferred) is set in the B register (first register) by the command "LD B, @NUM_CPU_RG2" on the fifth line of FIG. 247. As can be understood by referring to the 50th line of the CPU built-in register setting data table in Figure 246, the command "EQU ($-T_CPU_REG)/2-@NUM_CPU_RG1" is written in the symbol "@NUM_CPU_RG2". There is. Here, the value of $-T_CPU_REG (1-byte value indicating the number of data) is 30/2=15, and "@NUM_CPU_RG1" is 13, so in the example of FIG. 246, the number of set data is 15-13= It becomes 2.

The command “LD Q, HIGH @S2CMS__” on the 6th line in FIG. 247 sets the value of the upper byte (“FFH”) of the symbol “@S2CMS__” in the Q register (third register). Here, too, since the input/output section 704 is accessed using the memory mapped I/O method, the upper byte of the input/output section 704 is set in the QH register instead of the U register. Note that, as described above, setting data has been completed for the input/output unit 704 whose upper address is “FEH” among the two values “FEH” and “FFH” as addresses indicating the input/output unit 704. Therefore, here, "FFH" is set in the Q register, and setting data is set for the input/output section 704 whose upper address is "FFH".

The command "LDINTQR (HL)" on the 7th line of FIG. 247 sets the value of the Q register to the upper 1 byte of the transfer destination address, and sets the value stored in the memory area indicated by the address of the HL register (second register). The value stored in the memory area indicated by the address that is the lower 1 byte of the transfer destination address and the value of the HL register plus "1" is transferred to the memory area indicated by the transfer destination address, and the value stored in the memory area indicated by the transfer destination address is stored in the HL register. The address to be transferred next is updated by adding "2" to the value, and the value of the B register is decremented (subtracted by "1") until the decremented result becomes 0, that is, the setting data is transferred only twice. The process is repeated. In this way, setting data regarding the second input/output unit 704 in the latter stage of FIG. 246 is completed. In such an LDINTQR instruction, processing is executed without using registers other than the B register, HL register, and Q register, for example, the A register.

Then, the value of the upper byte of the symbol "@RAM_BGN_ADR" is set in the Q register by the command "LD Q, HIGH @RAM_BGN_ADR" on the 8th line of FIG. 247. In this way, the value of the Q register is returned to the initial value "F0H".

In this way, the total command size of the commands for the initial setting process shown in FIG. 247 is: 2 bytes of the command "LDF HL, T_CPU_REG" in the 1st line + 2 bytes of the command "LD B, @NUM_CPU_RG1" in the 2nd line + 2 bytes of the command "LDB, @NUM_CPU_RG1" in the 3rd line. Command “LD Q, HIGH @PTOPR___” 2 bytes + 4th line command “LDINTQR (HL)” 2 bytes + 5th line command “LD B, @NUM_CPU_RG2” 2 bytes + 6th line command “LD Q, HIGH @ S2CMS__" 2 bytes + command "LDINTQR (HL)" on the 7th line 2 bytes + command "LD Q, HIGH @RAM_BGN_ADR" 1 byte = 15 bytes.

Here, the I/O mapped I/O method in FIG. 245 is changed to the memory mapped I/O method as shown in FIG. 247, and accordingly, the LDINTQR instruction can be used. In this case, while the total command size of the commands for the initial setting process in FIG. 245 is 24 bytes, the total command size for the commands for the initial setting process in FIG. 247 is 15 bytes, which allows a reduction of 9 bytes. In this way, by using the LDINTQR command using the memory mapped I/O method, it is possible to shorten the command and secure the capacity of the control area for performing game control processing.

<Usage example 2 of memory mapped I/O method>
FIG. 248 is an explanatory diagram showing addresses of output ports, and FIG. 249 is a diagram showing a part of a command group for realizing the save process at power-off. Here, for convenience of explanation, the output port clearing process (step S300-11 in FIG. 25 and step S3000-11 in FIG. 97) of the power-off saving process S3000 will be described. In the output port clearing process, the output of the output port is cleared to 0. Note that here, an example will be given in which the main CPU 500a executes the output port clearing process S3000-11.

In this embodiment, a total of nine output ports, output ports 0 to 8, are prepared as the input/output unit 704. Output ports 0 to 8 can continuously output discrete signals (binary values of Hi (high level) and Low (low level)) in bit units. Note that the targets of the output port clearing process are limited to a total of six output ports, output ports 0 to 4, and 7 among output ports 0 to 8. Therefore, in the output port clearing process, output ports 0 to 4 and 7 are cleared.

Referring to FIG. 248, output port 4 is assigned to address "FFF0H" in the memory space, output port 3 is assigned to address "FFF1H", output port 2 is assigned to address "FFF2H", and output port 2 is assigned to address "FFF3H". Output port 1 is assigned to address "FFF4H", output port 0 is assigned to address "FFF5H", and output port 7 is assigned to address "FFF5H".

The output port clearing process in FIG. 249 is a process that is performed only when "0" is set in the A register, and when the output port clearing process is executed, "0" has already been set in the A register. This means that The command "LD BC, 6*256+@OUT_PRT_7" in the first line of FIG. 249 sets 6, which is the number of output ports, in the B register, and sets the address value of the lower 1 byte indicating output port 7 in the C register. Ru. Note that, as shown in FIG. 248, the value of the lower 1 byte indicating output port 7 is "F5H". The command "OUT (C), A" on the third line sets the value of the U register (the initial value "FFH" here) as the upper 1 byte of the address, the value of the C register as the lower 1 byte, and sets that address. The value of the A register (“0”) is output to the memory area indicated by .

The command "DEC C" on the fourth line in FIG. 249 decrements the value stored at the address indicated by the C register by one. The command "DJNZ PRFPROC02" on the 5th line decrements the value of the B register (subtracts "1"), and if the decremented result is not 0, moves to the index "PRFPROC02" on the 2nd line, and the decremented result is If it is 0, the process moves to the command next to the command in question. Here, since the number of output ports is "6", the value of the B register becomes 0 when the process starting from the index "PRFPROC02" is repeated six times.

In this way, the address of the input/output unit 704 is decremented as "FFF5H" → "FFF4H" → "FFF3H" → "FFF2H" → "FFF1H" → "FFF0H", and accordingly, output port 7 → output port 0 → output port 1 Each bit of the output port is set to 0 in the following order: → output port 2 → output port 3 → output port 4.

In this way, the total command size of the output port clear processing commands shown in FIG. ” 2 bytes + 4th line command “DEC C” 1 byte + 5th line command “DJNZ PRFPROC02” 2 bytes = 8 bytes.

As described above, in some processing of a program, the command size may be smaller if instructions of the memory mapped I/O method are used instead of the I/O mapped I/O method. Therefore, an example in which the memory mapped I/O method is applied to some processing will be described.

FIG. 250 is a diagram illustrating another example of a part of the command group for realizing the power-off saving process. Here, the main CPU 500a clears the output of the output port to 0 using the memory mapped I/O method.

The command "LD HL, @OUT_PRT_4" in the first line of FIG. 250 sets the 2-byte symbol "@OUT_PRT_4" itself (output port information) indicating output port 4 in the HL register (second register). Note that, as shown in FIG. 248, the value of the 2 bytes indicating output port 4 is "FFF0H". The command "LD B, 6" on the second line sets 6, which is the number of output ports to be cleared (the number to be cleared), in the B register (first register).

The command "CLRIRS" on the third line in Figure 250 stores "0" in the memory area indicated by the address of the HL register (clears the output port), adds "1" to the value of the HL register, and then The address to be cleared is updated, the value of the B register is decremented (subtracted by "1"), and the process is repeated 6 times, which is the number of output ports to be cleared, until the decremented result becomes 0. . In such a CLRIRS instruction, processing is executed without using registers other than the B register and the HL register, such as the A register.

In this way, the address of the input/output unit 704 is incremented as "FFF0H" → "FFF1H" → "FFF2H" → "FFF3H" → "FFF4H" → "FFF5H", and accordingly, output port 4 → output port 3 → output port 2 The outputs of the output ports are set to 0 in the following order: → output port 1 → output port 0 → output port 7.

In this way, the total command size of the output port clear processing commands shown in Figure 250 is: 1st line command "LD HL, @OUT_PRT_4" 3 bytes + 2nd line command "LD B, 6" 2 bytes + 3 lines The second command “CLRIRS” is 2 bytes = 7 bytes.

Here, the I/O mapped I/O method in FIG. 249 is changed to the memory mapped I/O method as shown in FIG. 250, and it becomes possible to use the CLRIRS instruction accordingly. In this case, the total command size of the output port clear processing command in Figure 249 is 8 bytes, whereas the total command size of the output port clear processing command in Figure 250 is 7 bytes, so a reduction of 1 byte is possible. Become. In this way, by using the CLRIRS command using the memory mapped I/O method, it is possible to shorten the command and secure the capacity of the control area for performing game control processing.

Note that in the example of FIG. 250, the use of the CLRIRS instruction eliminates the need to use the A register. Therefore, the value of the A register will not be updated unintentionally. For example, if the A register is already in use, it would normally be necessary to save it, but here, since the A register is not used, there is no need to save it. In this way, resources can be used effectively. Note that the example in Figure 249 assumes that the value "0" is set in the A register in advance, but since the command "CLRIRS" has a function to set the value "0", the value is set in advance. Processing to set "0" is also unnecessary. In this way, it is possible to further shorten the command and secure the capacity of the control area for performing game control processing.

Although preferred embodiments of the present invention have been described above with reference to the accompanying drawings, it goes without saying that the present invention is not limited to these embodiments. It is clear that those skilled in the art can come up with various changes and modifications within the scope of the claims, and it is understood that these naturally fall within the technical scope of the present invention. be done.

Furthermore, in the above-described embodiment, the main control boards 300, 500 and the sub-control boards 330, 502 are arranged so as to share the functional parts for proceeding with the game, but the functional parts of the main control boards 300, 500 are may be arranged on the sub-control boards 330, 502, the functional parts of the sub-control boards 330, 502 may be arranged on the main control boards 300, 500, or all functional parts can be combined into one control board. It can also be arranged.

Further, each process performed by the main control boards 300, 500 and sub-control boards 330, 502 described above does not necessarily have to be performed chronologically in the order described in the flowchart, and may include parallel or subroutine processing. But that's fine.

100 Gaming machines 300, 500 Main control board 300a, 500a Main CPU
300b, 500b main ROM
300c, 500c main RAM
330, 502 Sub control board 330a, 502a Sub CPU
330b, 502b sub ROM
330c, 502c, sub RAM
400 slot machine

Claims (1)

A gaming machine comprising a processor, a storage means for storing data, a predetermined device, and a random number generation section for generating random numbers on a predetermined board used for playing the game,
The random number generation unit includes a maximum value fixed random number generator in which a maximum value of random numbers is fixed, and a maximum value setting random number generator in which a maximum value of random numbers can be set,
Random numbers generated by the maximum value fixed random number generator or the maximum value setting random number generator are used as the plurality of random numbers used to proceed with the game,
The storage means and the device are respectively allocated to different address ranges in a memory space,
In the same program, the processor:
The device may be accessed by a command based on a memory mapped I/O method for accessing the storage means, and
A gaming machine in which the device may be accessed by a command based on an I/O mapped I/O method for accessing the device.

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