JP7495912B2 - Gaming Machines - Google Patents

Description

The present invention relates to a gaming machine that determines by lottery whether or not to award a gaming advantage to a player.

In pachinko machines, which are used as gaming machines, a gaming ball is launched into a gaming area within a gaming board by the player operating a handle, and if the gaming ball that flows down the gaming area enters the starting hole, a lottery for a special symbol is executed. Then, when a specific special symbol indicating a jackpot is displayed on the special symbol display, a big prize game that is more advantageous to the player than normal play begins, and the player can receive a large payout of prize balls (gaming media, gaming value).

In addition, in slot machines as gaming machines, a winning combination is drawn in response to the player's bet of medals (gaming media, gaming value) and the operation of a start switch, and multiple reels marked with various symbols spin. The reels are then stopped sequentially in response to the results of the lottery and the player's operation of a stop switch, and when a symbol combination corresponding to a winning combination is displayed on an active line, which is the line that is the subject of a payout, a predetermined number of medals is paid out, and a gaming profit (hereinafter simply referred to as gaming profit) is awarded to the player.

In addition, development is underway on managed gaming machines that use a sealed circulation system in which the player can play without touching the game balls (e.g., Patent Document 1), and medal-less gaming machines that allow the player to play without the need for medals (e.g., Patent Document 2).

JP 2020-156551 A JP 2015-134014 A

In such managed gaming machines and medalless gaming machines, there is no need to provide a path outside the gaming machine for circulating gaming media such as gaming balls and medals, and in medalless gaming machines, the physical gaming media themselves are not necessary. In this way, medalless gaming machines do not use gaming media themselves, and managed gaming machines use non-magnetic gaming balls, making it possible to prevent cheating that assumes the use of metallic gaming media. In addition, there is no need to provide a mechanism for inserting and paying out gaming media within the gaming machine, which reduces design and manufacturing costs.

Furthermore, by centrally managing the lending of gaming media to players and the counting of acquired gaming media, it is possible to prevent fraud and curb gambling.

On the other hand, for configurations that use electronic game media (game value) or non-magnetic game media instead of physical game media, a new mechanism is needed to manage the electronic game media while properly progressing the game.

In view of these problems, the present invention aims to provide a gaming machine that allows the game to proceed appropriately.

In order to solve the above problem, the gaming machine of the present invention capable of outputting a predetermined signal to the outside includes a betting means for betting a gaming value to be used in a game, a reel control means for controlling the rotation of a plurality of reels on which a plurality of types of symbols are arranged, based on the operation of a start switch after the gaming value has been bet, and for controlling the stop of each of the reels corresponding to the operated stop switch in response to the operation of a stop switch corresponding to the rotating reel, and a payout control means for paying out a gaming value corresponding to the stopping state of the reels, wherein the payout control means pays out the gaming value all at once in response to the stop of the reels, and then permits a bet for the next game by the betting means and outputs to the outside a first signal consisting of pulses corresponding to the number of the gaming value to be paid out, and then, when the output of the first signal is completed, a second signal indicating that the next game is possible is output to the outside, and the timing for permitting the bet for the next game is earlier than the timing for completing the output of the first signal .

The present invention makes it possible to progress through the game appropriately.

1 is an oblique view of a gaming machine showing the door in the open state in the simultaneous rotation reference example. FIG. 2 is a front view of a gaming machine relating to a simultaneous rotation reference example. A diagram explaining the second large prize slot in the simultaneous spinning reference example. A block diagram showing the internal configuration of a control means for controlling the progress of a game in the simultaneous rotation reference example. 13 is an address map of a memory area used by a main CPU according to a reference example of simultaneous rotation. This is a diagram explaining the random number judgment table for determining a jackpot at low probability in the simultaneous spin reference example. This is a diagram explaining the random number judgment table for determining a jackpot at high probability in the simultaneous spin reference example. A diagram explaining a winning pattern random number determination table and a small winning pattern random number determination table for a simultaneous spin reference example. A diagram explaining a reach group determination random number judgment table for the simultaneous rotation reference example. A figure explaining a reach mode determination random number judgment table for the simultaneous rotation reference example. A figure explaining a variation pattern random number determination table for a simultaneous rotation reference example. FIG. 13 is a diagram illustrating a variable time determination table according to a simultaneous rotation reference example. A diagram explaining the game state and variable time for the simultaneous spin reference example. This is the first diagram explaining the special electric role operation ram set table for the simultaneous rotation reference example. This is the second diagram explaining the special electric role operation ram set table for the simultaneous rotation reference example. A diagram explaining a game status setting table for a simultaneous rotation reference example. A diagram explaining a random number judgment table for determining a win in the simultaneous rotation reference example. 1A is a diagram explaining a normal pattern change time data table for a simultaneous rotation reference example, and FIG. 1B is a diagram explaining an opening/closing control pattern table for a simultaneous rotation reference example. A figure explaining the transition of game states in accordance with the original gameplay of the simultaneous spin reference example. A figure explaining the transition of game states when play is not performed properly in the simultaneous spin reference example. A figure explaining the gaming machine status flag for the simultaneous spin reference example. 11 is a first flowchart illustrating a CPU initialization process in a main control board according to a simultaneous rotation reference example. 13 is a second flowchart illustrating the CPU initialization process in the main control board according to the simultaneous rotation reference example. 13 is a flowchart illustrating a sub-command group set process in a main control board according to a simultaneous rotation reference example. 13 is a flowchart illustrating a power-off evacuation process in a main control board according to a simultaneous rotation reference example. 13 is a flowchart illustrating timer interrupt processing in a main control board in a simultaneous rotation reference example. 13 is a flowchart illustrating setting-related processing in a main control board according to a simultaneous rotation reference example. 13 is a flowchart illustrating a switch management process in a main control board according to a simultaneous rotation reference example. 13 is a flowchart illustrating a gate passing process in a main control board according to a simultaneous rotation reference example. 13 is a flowchart explaining the first starting port passing process in the main control board in the simultaneous rotation reference example. 13 is a flowchart explaining the second starting port passing process in the main control board in the simultaneous rotation reference example. A flowchart explaining the special pattern random number acquisition process in the main control board for the simultaneous rotation reference example. 13 is a flowchart illustrating the acquisition time performance determination process in the main control board for the simultaneous rotation reference example. A flowchart explaining the large prize opening passing processing in the main control board for the simultaneous rotation reference example. A figure explaining the special game management phase and the special electric device game management phase in the simultaneous spinning reference example. 13 is a flowchart explaining the special game management processing in the main control board for the simultaneous rotation reference example. A flowchart explaining the special pattern change waiting process in the main control board for the simultaneous rotation reference example. 13 is a flowchart explaining the special pattern winning determination process in the main control board for the simultaneous rotation reference example. 13 is a flowchart explaining the special pattern variable number determination process in the main control board for the simultaneous rotation reference example. 13 is a flowchart illustrating the number of times cutoff management processing in the main control board in the simultaneous rotation reference example. A flowchart explaining the processing during special pattern changes in the main control board for the simultaneous rotation reference example. 13 is a flowchart explaining the forced pattern stop processing in the main control board for the simultaneous rotation reference example. 13 is a flowchart explaining the special pattern stop pattern display processing in the main control board for the simultaneous rotation reference example. 13 is a flowchart explaining the special electric device play management processing in the main control board for the simultaneous rotation reference example. A flowchart explaining the processing before opening the large prize opening in the main control board for the simultaneous rotation reference example. A flowchart explaining the large prize opening/closing switching process in the main control board for the simultaneous rotation reference example. A flowchart explaining the large prize opening control processing in the main control board for the simultaneous rotation reference example. A flowchart explaining the large prize opening closure activation process in the main control board for the simultaneous rotation reference example. A flowchart explaining the large prize opening end wait processing in the main control board for the simultaneous rotation reference example. A diagram explaining the normal game management phase related to the simultaneous rotation reference example. 13 is a flowchart explaining the normal game management processing in the main control board for the simultaneous rotation reference example. A flowchart explaining the normal pattern change waiting process in the main control board for the simultaneous rotation reference example. A flowchart explaining the processing during normal pattern fluctuations on the main control board in the simultaneous rotation reference example. A flowchart explaining the normal pattern stop pattern display processing in the main control board for the simultaneous rotation reference example. This is a flowchart explaining the processing before opening of the winning opening of a normal electric device in the main control board for the simultaneous rotation reference example. This is a flowchart explaining the normal electric gimmick prize opening/closing switching process in the main control board for the simultaneous rotation reference example. This is a flowchart explaining the control processing for opening the winning port of a normal electric device in the main control board for the simultaneous rotation reference example. This is a flowchart explaining the normal electric device winning opening closure validity processing in the main control board for the simultaneous rotation reference example. This is a flowchart explaining the normal electric gimmick winning slot end wait processing in the main control board for the simultaneous rotation reference example. This is a diagram illustrating an example of a variable presentation of a no-reach variable pattern related to a reference presentation example. This is a diagram illustrating an example of a normal reach fluctuation pattern fluctuation presentation related to a presentation reference example. This is a diagram illustrating an example of a change in the development reach change pattern when a miss occurs in accordance with a reference example of the performance. This is a diagram illustrating an example of a change presentation of a development reach change pattern at the time of a jackpot, which is related to a reference presentation example. This is a diagram illustrating an example of a variable presentation when the reach development presentation relating to the presentation reference example is executed twice. 13 is a diagram illustrating an example of a pseudo-continuous reach fluctuation pattern fluctuation presentation relating to a presentation reference example. FIG. A diagram explaining a variable performance decision table related to a performance reference example. A figure explaining an example of a hold display presentation related to a reference presentation example. 1A is a diagram explaining a final hold display pattern determination table relating to a reference example of presentation, and FIG. 1B is a diagram explaining a previous hold display pattern determination table relating to a reference example of presentation. 13 is a flowchart explaining the sub-CPU initialization process in the sub-control board for the reference example performance. 13 is a flowchart explaining sub-timer interrupt processing in a sub-control board for a reference example of a performance. 13 is a flowchart explaining the pre-reading designation command reception processing in the sub-control board for the reference example performance. 13 is a flowchart explaining the variable command receiving processing in the sub-control board for the reference example performance. FIG. 1 is an external view for explaining a schematic mechanical configuration of a slot machine. 1 is an external view of the slot machine with the front door open, illustrating the general mechanical configuration of the slot machine. FIG. 1 is a diagram illustrating the arrangement of symbols on the reels and the winning lines. FIG. 2 is a block diagram showing a schematic electrical configuration of the slot machine. FIG. 13 is an explanatory diagram for explaining a winning combination. FIG. 13 is a diagram showing a winning type lottery table. FIG. 13 is a diagram showing a winning type lottery table. FIG. 11 is an explanatory diagram for explaining the transition of a game state. FIG. 11 is an explanatory diagram for explaining the transition of the presentation state. 11 is a flowchart illustrating a CPU initialization process in a main control board. 11 is a flowchart illustrating a cold start process in a main control board. 13 is a flowchart illustrating an error stop process in the main control board. 13 is a flowchart illustrating a setting value switching process in a main control board. 11 is a flowchart illustrating an initialization start process in the main control board. 13 is a flowchart illustrating a state restoration process in a main control board. 13 is a flowchart explaining game start processing on the main control board. 13 is a flowchart explaining the game medal insertion processing on the main control board. 13 is a flowchart illustrating an internal lottery process in the main control board. 13 is a flowchart illustrating a pattern code setting process in the main control board. 13 is a flowchart explaining the processing performed during reel rotation on the main control board. 13 is a flowchart explaining the reel stop processing in the main control board. 13 is a flowchart illustrating a display determination process in a main control board. 13 is a flowchart explaining the payout process in the main control board. 13 is a flowchart explaining game transition processing on the main control board. 11 is a flowchart illustrating a save process in the main control board when power is turned off. 11 is a flowchart illustrating a timer interrupt process in a main control board. FIG. 2 is a diagram for explaining electrical connections around a main CPU. FIG. 2 is a block diagram showing the internal configuration of a CPU core. FIG. 2 is a diagram illustrating a configuration of a register. FIG. 2 is an explanatory diagram showing a memory map. FIG. 2 is an explanatory diagram showing the appearance of a main control board. FIG. 13 is an explanatory diagram for explaining a display mode of a ratio display section. 13 is a flowchart showing a first example of calculation of the reel ratio. FIG. 11 is an explanatory diagram for explaining a first operation example using only an 8-bit MUL instruction; 11 is a flowchart showing a specific process for implementing a first calculation example. FIG. 11 is a diagram showing an example of a specific command for implementing the first calculation example. FIG. 11 is an explanatory diagram for explaining a second calculation example using a 16-bit multiplier. 10 is a flowchart showing a specific process for implementing the second calculation example. FIG. 11 is a diagram showing an example of a specific command for implementing the second calculation example. FIG. 11 is a diagram showing an example of a specific command for implementing the first calculation example. FIG. 11 is an explanatory diagram for explaining a third calculation example using repeated subtraction of a number multiplied by a power of 2; 13 is a flowchart showing a specific process for implementing the third calculation example. FIG. 13 is a diagram showing an example of a specific command for implementing the third calculation example. 13 is a flowchart showing a specific process for implementing the fourth calculation example. FIG. 13 is a diagram showing an example of a specific command for implementing the fourth calculation example. 13 is a flowchart showing a specific process for implementing the fifth calculation example. FIG. 13 is a diagram showing an example of a specific command for implementing the fifth calculation example. 13 is a flowchart showing a specific process for implementing the sixth calculation example. FIG. 13 is a diagram showing an example of a specific command for implementing the sixth calculation example. 11 is a flowchart showing a specific process of a BYTESEL module. FIG. 11 is an explanatory diagram for explaining an example of a command for realizing a BYTESEL module. FIG. 11 is an explanatory diagram for explaining an example of a command for realizing a BYTESEL module. FIG. 13 is an explanatory diagram for explaining another example of a command for implementing the BYTESEL module. FIG. 13 is an explanatory diagram for explaining still another example of a command for realizing a BYTESEL module. 11 is a flowchart showing a specific process of a WORDSEL module. FIG. 11 is an explanatory diagram for explaining an example of a command for realizing a WORDSEL module. FIG. 11 is an explanatory diagram for explaining an example of a command for realizing a WORDSEL module. FIG. 13 is an explanatory diagram for explaining another example of a command for implementing a WORDSEL module. FIG. 13 is an explanatory diagram for explaining still another example of a command for implementing a WORDSEL module. FIG. 11 is an explanatory diagram for explaining a CAL_MOD module. FIG. 2 is an explanatory diagram for explaining a HID_JUG module. 11 is a flowchart showing a specific process of a RAMSET module. FIG. 11 is an explanatory diagram for explaining an example of a command for realizing a RAMSET module. FIG. 11 is an explanatory diagram for explaining an example of a command for realizing a RAMSET module. FIG. 11 is an explanatory diagram for explaining another example of a command for realizing a RAMSET module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing a TABLESET module. FIG. 13 is an explanatory diagram for explaining another example of the command for implementing the TABLESET module. 11 is a flowchart showing a specific process of a BYTEDEC module. FIG. 11 is an explanatory diagram for explaining the decrement mode in the BYTEDEC module and the setting of the zero flag and the carry flag. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing a BYTEDEC module. FIG. 13 is an explanatory diagram for explaining another example of a command for implementing the BYTEDEC module. FIG. 2 is an explanatory diagram for explaining a RAM_DEC module. 11 is a flowchart showing a specific process of a WORDDEC module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing a WORDDEC module. FIG. 13 is an explanatory diagram for explaining another example of the command for implementing the WORDDEC module. FIG. 11 is an explanatory diagram for explaining an example of a process for returning from a subroutine. FIG. 2 is an explanatory diagram for explaining a PY_CMDA module. FIG. 2 is an explanatory diagram for explaining a GAT_PAS module. FIG. 2 is an explanatory diagram for explaining a TDN_PAS module. FIG. 2 is an explanatory diagram for explaining an FD_OPN module. FIG. 11 is an explanatory diagram for explaining a TZ_STA module. FIG. 11 is an explanatory diagram for explaining a TZ_RGET module. FIG. 1 is an explanatory diagram for explaining a TRSVSEL module. FIG. 13 is an explanatory diagram for explaining a TDOVCHK module. FIG. 11 is an explanatory diagram for explaining a BER_CHK module. FIG. 2 is an explanatory diagram for explaining a TEF_SEL module. FIG. 11 is an explanatory diagram for explaining a SET_RIG module. FIG. 11 is an explanatory diagram for explaining a PRE_LOT module. FIG. 11 is an explanatory diagram for explaining a REG_LOT module. FIG. 2 is an explanatory diagram for explaining a BIG_SLT module. FIG. 2 is an explanatory diagram for explaining a NAV_SET module. 11 is a flowchart showing specific processing of a TOK_PRC module. FIG. 11 is an explanatory diagram for explaining an example of a command for realizing a TOK_PRC module. 11 is a flowchart showing a specific process of a TEF_SEL module. FIG. 11 is an explanatory diagram for explaining an example of a command for realizing a TEF_SEL module. 11 is a flowchart showing specific processing of a SWI_PRC module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing a SWI_PRC module. 11 is a flowchart showing specific processing of a CPUINIT module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing a CPUINIT module. FIG. 2 is an explanatory diagram for explaining a TMR_IPT module. 11 is a flowchart showing a specific process of an FZ_SPN module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing an FZ_SPN module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing a CPUINIT module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing an EXE_SET module. 11 is a flowchart showing a specific process of the HPT_GRP module. 13A and 13B are explanatory diagrams for explaining an example of a command for realizing the HPT_GRP module, and FIG. 13C is an explanatory diagram for explaining an example of a reach group determination random number judgment table. FIG. 13 is an explanatory diagram for explaining an E_ILGER module. FIG. 2 is an explanatory diagram for explaining an E_LEVOT module. 11 is a flowchart showing a specific process of an SBC_OUT module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing an SBC_OUT module. FIG. 13 is an explanatory diagram for explaining an example of another command for implementing the SBC_OUT module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing an FZ_OPN module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing a TD_OPN module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing an HSY_PRC module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing an FDN_CHK module. FIG. 11 is an explanatory diagram for explaining an example of a command for realizing an FZ_STP module. FIG. 2 is a block diagram for explaining the configuration of a random number generator. FIG. 13 is a diagram for explaining a combination of random number generation units. 11 is a flowchart showing a specific process of an SMC_ROT module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing an SMC_ROT module. FIG. 11 is an explanatory diagram for explaining another example of a command for implementing the SMC_ROT module. 11 is a flowchart showing a specific process of an INITIAL module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing an INITIAL module. FIG. 13 is an explanatory diagram for explaining another example of the command for implementing the INITIAL module. FIG. 2 is an explanatory diagram for explaining a RANKSET module. FIG. 13 is an explanatory diagram for explaining a PWRFAIL module. FIG. 2 is an explanatory diagram for explaining a DYM_OUT module. 11 is a flowchart showing a specific process of an IPT_PD module. FIG. 11 is an explanatory diagram for explaining an example of a command for realizing an IPT_PD module. FIG. 11 is an explanatory diagram for explaining another example of the command for realizing the IPT_PD module. FIG. 2 is an explanatory diagram for explaining a DYNMOUT module. FIG. 11 is an explanatory diagram for explaining an EXT_PRC module. 11 is a flowchart showing a specific process of a STOPDCT module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing a STOPDCT module. FIG. 13 is an explanatory diagram for explaining another example of the command for implementing the STOPDCT module. 11 is a flowchart showing a specific process of an E_SETTM module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing an E_SETTM module. FIG. 11 is an explanatory diagram for explaining another example of a command for implementing the E_SETTM module. FIG. 2 is an explanatory diagram for explaining a DYM_OUT module. FIG. 2 is an explanatory diagram for explaining a DYM_OUT module. 11 is a flowchart showing a specific process of an E_SETTM module. FIG. 13 is an explanatory diagram for explaining yet another example of a command for implementing the E_SETTM module. 11 is a flowchart showing a specific process of a RAM_INC module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing a RAM_INC module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing a RAM_INC module. FIG. 13 is an explanatory diagram for explaining another example of the command for implementing the RAM_INC module. FIG. 13 is an explanatory diagram for explaining another example of the command for implementing the RAM_INC module. 11 is a flowchart showing a specific process of a TABLESET module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing a TABLESET module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing a TABLESET module. FIG. 13 is an explanatory diagram for explaining another example of the command for implementing the TABLESET module. 13 is a flowchart showing a specific process of an IPT_PC module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing an IPT_PC module. 11 is a flowchart showing specific processing of a CMDPROC module. FIG. 11 is an explanatory diagram for explaining an example of a command for implementing a CMDPROC module. 11 is a flowchart showing a specific process of the SET_PLS module. 11 is an explanatory diagram illustrating an example of a command for implementing a SET_PLS module. FIG. 11 is a flowchart showing a specific process of the OTM_ATK module. FIG. 11 is an explanatory diagram for explaining an example of a command for realizing an OTM_ATK module. FIG. 11 is an explanatory diagram illustrating an example of a command for implementing a KRS_JDG module. FIG. 13 is an explanatory diagram for explaining another example of the command for realizing the KRS_JDG module. FIG. 13 is a diagram showing an example of a command for setting a value in a Q′ register. FIG. 13 is a diagram showing an example of a command for setting a value in a Q′ register. FIG. 13 is a diagram showing an example of a command for setting a value in a Q′ register. FIG. 13 is a diagram showing an example of a command for setting a value in a Q′ register. FIG. 13 is a diagram for explaining the transition of register banks and register groups. FIG. 1 is an explanatory diagram for explaining a usage mode of an access method. 11 is a flowchart illustrating an example of a subcommand transmission process. FIG. 11 is a diagram showing an example of a specific command for implementing a sub-command transmission process. FIG. 13 is a diagram showing an example of another command for implementing a subcommand transmission process. FIG. 11 is a diagram showing a part of a command group for realizing a CPU initialization process. FIG. 13 shows a table referred to in the CPU initialization process. FIG. 13 is a diagram showing another example of a portion of the command group for implementing the CPU initialization process. FIG. 13 is a diagram showing another example of a table referred to in the CPU initialization process. FIG. 13 is a diagram showing another example of a portion of the command group for implementing the CPU initialization process. FIG. 11 is an explanatory diagram showing addresses of output ports. FIG. 11 is a diagram showing a part of a command group for implementing a save process at the time of power failure. FIG. 13 is a diagram showing another example of a portion of the command group for implementing the power-off save process. FIG. 2 is a functional block diagram showing the gaming system. 1 is an external view for explaining the general mechanical configuration of a medalless gaming machine and a dedicated unit. FIG. A block diagram showing a schematic electrical configuration of the medalless gaming machine and the dedicated unit. FIG. 11 is an explanatory diagram for explaining another substrate configuration. FIG. 2 is an explanatory diagram for explaining an enclosure mode of a case. An explanatory diagram for explaining the CPU and areas that execute each function of the medalless gaming machine. 11 is an explanatory diagram for explaining the format of a gaming machine information notification. FIG. 11 is an explanatory diagram for explaining the format of a gaming machine information notification. FIG. 11 is an explanatory diagram for explaining the format of a gaming machine information notification. FIG. 11 is an explanatory diagram for explaining the format of a gaming machine information notification. FIG. FIG. 11 is an explanatory diagram for explaining the format of a counting notification. 13 is an explanatory diagram for explaining the format of a loan acceptance result response. FIG. FIG. 13 is an explanatory diagram for explaining the format of a lending notice. 13 is a timing chart showing the timing of notification of gaming machine information, counting notification, loan notification, and loan receipt result response. 11 is an explanatory diagram for explaining the timing of transmitting a gaming machine information notification. FIG. 13 is a flowchart showing the flow of a counting switch monitoring process in the medal count control CPU. 13 is a flowchart showing the flow of counting processing in the medal number control CPU. 10 is a timing chart for explaining a counting process. 11 is a timing chart for explaining a display mode of the number of game medals. 13 is a flowchart showing the flow of count switch processing in the medal number control CPU. 13 is a time chart explaining the setting of the number of counted medals. 13 is a flowchart showing the flow of count switch processing according to a modified example in which all signals generated multiple times are effectively processed. 13 is a time chart explaining the setting of the number of counted medals in a modified example in which all multiple signals are effectively processed. 13 is a flowchart showing the flow of command reception processing in the medal count control CPU. 13 is a flowchart showing the flow of command reception processing in the medal count control CPU. 13 is a flowchart showing the flow of command reception processing in the medal count control CPU. 11 is a flowchart showing communication specifications when power is turned on. 11 is a flowchart showing communication specifications during operation. 13 is a flowchart showing communication specifications at the end of a game. 13 is a flowchart showing the flow of bet processing in the medal number control CPU. FIG. 13 is an explanatory diagram showing an example of actual calculation in the betting process. 13 is a flowchart showing a process of updating a setting change signal. 13 is a flowchart showing an update process of a setting confirmation signal. An explanatory diagram showing a comparison example of communication processing between a main CPU and a medal count control CPU. 11A and 11B are a flowchart showing the concept of transmitting one byte of a command and a diagram showing the command. An explanatory diagram showing communication processing between the main CPU and the medal count control CPU. FIG. 13 is an explanatory diagram for explaining a test shot test of a medalless gaming machine. FIG. 2 is an explanatory diagram for explaining the operation of the slot machine. FIG. 2 is an explanatory diagram for explaining the operation of the medalless gaming machine.

The preferred embodiment of the present invention will be described in detail below with reference to the attached drawings. The dimensions, materials, and other specific values shown in the embodiment are merely examples to facilitate understanding of the invention, and do not limit the present invention unless otherwise specified. In this specification and drawings, elements having substantially the same functions and configurations are given the same reference numerals to avoid duplicated explanations, and elements not directly related to the present invention are not illustrated.

In this embodiment of the present invention, a pachinko machine and a slot machine are given as examples of gaming machines, in that order, and then the specific processing is described in detail.

<Pachinko machine>
In order to facilitate understanding of the embodiments of the present invention, first, as a simultaneous rotation reference example, the mechanical and electrical configurations of the so-called simultaneous rotation machine and the specific processing on each board are explained. Then, as a performance reference example, specific performances that can be executed by the simultaneous rotation machine and specific processing related to the performance are explained. After that, as an embodiment of the present invention, the configurations that are different from each reference example are specifically explained.

<Simultaneous rotation example>
1 is a perspective view of a gaming machine 100 according to a simultaneous rotation reference example, showing a state in which the door is open. As shown in the figure, the gaming machine 100 includes an outer frame 102 having an enclosed space formed by four sides assembled into a substantially rectangular shape, a middle frame 104 attached to the outer frame 102 by a hinge mechanism so as to be freely opened and closed, and a front frame 106 attached to the middle frame 104 by a hinge mechanism so as to be freely opened and closed.

The middle frame 104, like the outer frame 102, has four sides arranged in a roughly rectangular shape to form an enclosed space, and the game board 108 is held in this enclosed space. The front frame 106 also holds a glass or resin transparent plate 110. When the middle frame 104 and the front frame 106 are closed against the outer frame 102, the game board 108 and the transparent plate 110 face each other roughly parallel, maintaining a predetermined distance between them, and the game board 108 can be seen through the transparent plate 110 from the front side of the gaming machine 100.

Figure 2 is a front view of a gaming machine 100 relating to a simultaneous rotation reference example. As shown in this figure, an operating handle 112 that protrudes toward the front side of the gaming machine 100 is provided at the bottom of the front frame 106. This operating handle 112 is provided so that it can be rotated by the player, and when the player rotates the operating handle 112 to perform a firing operation, a gaming ball is fired by a firing mechanism (not shown) with a strength according to the rotation angle of the operating handle 112. The gaming ball fired in this way rises between rails 114a, 114b provided on the gaming board 108 and is guided to the playing area 116.

The play area 116 is a space formed between the play board 108 and the transparent plate 110, and is an area in which the play balls can flow down or roll. The play board 108 is provided with numerous nails and windmills (not shown), and the play balls guided to the play area 116 collide with the nails and windmills, causing them to flow down and roll in irregular directions.

The play area 116 has a first play area 116a and a second play area 116b, in which the degree of entry of the play balls differs according to the launch strength of the launch mechanism, allowing the player to hit different game balls. The first play area 116a is located on the left side of the play area 116 as seen by a player facing the gaming machine 100, and the second play area 116b is located on the right side of the play area 116 as seen by a player facing the gaming machine 100. Since the rails 114a and 114b are on the left side of the play area 116, game balls launched by the launch mechanism with a launch strength less than a predetermined strength will enter the first play area 116a, and game balls launched with a launch strength equal to or greater than the predetermined strength will enter the second play area 116b.

The game area 116 is also provided with a general prize entry port 118 through which game balls can enter, a first fixed start port 120A, a first variable start port 120B, a second start port 122, and a general action port 125. When a game ball enters the general prize entry port 118, the first fixed start port 120A, the first variable start port 120B, the second start port 122, or the general action port 125, a predetermined prize ball is paid out to the player. In the following, the first fixed start port 120A and the first variable start port 120B are collectively referred to as the first start port 120.

As will be described in more detail later, a first starting area is provided within the first starting hole 120, and a second starting area is provided within the second starting hole 122. When a game ball enters the first starting hole 120 or the second starting hole 122 and enters the first starting area or the second starting area, a lottery is held to determine one of a number of special patterns that have been set up in advance. Each special pattern is associated with the possibility of executing a big prize game or a small prize game that is advantageous to the player. Therefore, when a game ball enters the first starting hole 120 or the second starting hole 122, the player not only acquires a predetermined prize ball, but also acquires the opportunity to acquire the right to receive various game benefits.

The first fixed starting port 120A, the second starting port 122 and the normal operating port 125 are configured as fixed starting ports that are always open to allow game balls to enter. On the other hand, the first variable starting port 120B is provided with a movable piece 120b that can be opened and closed, and is configured as a variable starting port in which the ease with which game balls can enter the first variable starting port 120B changes depending on the state of this movable piece 120b. Specifically, the movable piece 120b is normally maintained in a closed state, and during this time it is difficult or impossible for game balls to enter the first variable starting port 120B.

In response to this, when a game ball passes through the gate 124 provided in the game area 116 (second game area 116b) or enters the normal symbol operation port 125, a lottery for a normal symbol, which will be described later, is held, and if a winning symbol is selected in this lottery, the movable piece 120b is controlled to an open state for a predetermined time. When the movable piece 120b is in an open state, it becomes possible for the game ball to enter the first variable start port 120B. In this way, the movable piece 120b functions as a movable member (start variable winning device) that transitions between an open state that allows the game ball to enter the first variable start port 120B, and a closed state that makes it more difficult or impossible for the game ball to enter the first variable start port 120B than in the open state.

The first fixed starting port 120A is located at a position where only game balls flowing down the first game area 116a can enter, and the first variable starting port 120B and the second starting port 122 are located at a position where only game balls flowing down the second game area 116b can enter. The first fixed starting port 120A may be used to allow game balls flowing down the second game area 116b to enter, but in this case, it is desirable to place it at a position where game balls flowing down the first game area 116a can enter more easily than game balls flowing down the second game area 116b.

Similarly, the first variable starting port 120B and the second starting port 122 may be entered by game balls flowing down the first game area 116a, but in this case, it is desirable to arrange them in a position where game balls flowing down the second game area 116b can enter more easily than game balls flowing down the first game area 116a. In any case, it is desirable that the first fixed starting port 120A is arranged in a position where at least game balls flowing down the first game area 116a can enter, and the first variable starting port 120B and the second starting port 122 are arranged in a position where at least game balls flowing down the second game area 116b can enter.

Furthermore, the second game area 116b is provided with a first large prize opening 126 and a second large prize opening 128. The first large prize opening 126 and the second large prize opening 128 are positioned so that only game balls flowing down the second game area 116b can enter the opening. However, the first large prize opening 126 and the second large prize opening 128 may be positioned so that any game balls flowing down the first game area 116a and the second game area 116b can enter the opening.

The first large prize opening 126 is provided with an opening/closing door 126b that can be opened and closed. Normally, the opening/closing door 126b closes the first large prize opening 126, making it impossible for game balls to enter the first large prize opening 126. Specifically, when the opening/closing door 126b is closed, it is flush with the surface of the game board 108, and game balls flow down in front of the first large prize opening 126. In contrast, when the aforementioned big prize game is played, the opening/closing door 126b opens and functions as a tray that guides game balls to the first large prize opening 126, making it possible for game balls to enter the first large prize opening 126. Then, when a game ball enters the first large prize opening 126, a predetermined number of prize balls are paid out to the player.

The second large prize opening 128 is provided below the first large prize opening 126 in the second game area 116b. The second large prize opening 128 is equipped with a movable piece 128b, which is normally maintained in a closed state. In contrast, when a small prize game, which will be described later, is played, the movable piece 128b is controlled to an open state, allowing a game ball to enter the second large prize opening 128. In the following, the first large prize opening 126 and the second large prize opening 128 are collectively referred to simply as the large prize openings.

Figure 3 is a diagram illustrating the second large prize opening 128 in the simultaneous spin reference example. A structure 129 protruding from the front side of the game board 108 is provided in the second game area 116b. This structure 129 is surrounded on all four sides in the left-right and front-back directions of the gaming machine 100, as well as on the bottom side, and has an opening formed at the top. The opening formed at the top of this structure 129 becomes the second large prize opening 128. A movable piece 128b is provided at the top of the structure 129, and normally, as shown in Figure 3(a), the movable piece 128b is maintained in a closed state that closes the second large prize opening 128.

The movable piece 128b protrudes into the game area 116 where the game balls roll and flow down, facing above the game machine 100. Therefore, when the movable piece 128b is maintained in a closed state, the game balls flowing down the game area 116 (second game area 116b) fall onto the movable piece 128b. Here, the structure 129 has a base that is approximately parallel to the horizontal direction, and the right side of the game machine 100 is slightly longer in the height direction than the left side. Therefore, the second large winning opening 128 is slightly lower on the left side of the game machine 100 than the right side, and the movable piece 128b maintained in a closed state is inclined so that the left side of the game machine 100 is slightly lower than the right side. Therefore, when the movable piece 128b is in the closed state, the game ball that falls onto the movable piece 128b will roll slowly from right to left on the movable piece 128b, as shown by the arrow in Figure 3 (a).

When a small win game, which will be described later, is executed, the movable piece 128b transitions to an open state that opens the second large winning opening 128. Here, the movable piece 128b transitions from a closed state to an open state by sliding toward the rear side of the game board 108, as shown in FIG. 3(b). As a result, when transitioning from the closed state to the open state, the game ball rolling on the movable piece 128b falls under its own weight into the second large winning opening 128.

In this way, in the simultaneous rotation reference example, the movable piece 128b is slightly tilted to ensure a long time for the game ball to roll on the movable piece 128b. Then, the movable piece 128b transitions from a closed state to an open state, leading the game ball rolling on the movable piece 128b into the second large winning opening 128. With the above configuration, even if the time for which the movable piece 128b is kept in the open state is set to be short, a predetermined number of game balls can be led into the second large winning opening 128. In other words, the time for which the movable piece 128b is kept in the open state, which is necessary to allow a predetermined number of game balls to enter the second large winning opening 128, can be shortened. In addition, a hole that communicates with the back side of the game board 108 is formed on the back side of the structure 129, and the game balls that enter the second large winning opening 128 are discharged to the back side of the game board 108. When a game ball enters the second large prize opening 128, a certain number of prize balls are paid out to the player.

Here, the configuration of the second large winning opening 128 has been described, but the first variable starting opening 120B has the same configuration as the second large winning opening 128. That is, the movable piece 120b of the first variable starting opening 120B protrudes from the front side of the game board 108 in the closed state, and the game ball rolls on the movable piece 120b. And, when the movable piece 120b is in the open state, the movable piece 120b slides to the rear side of the game board 108, and the game ball can enter the first variable starting opening 120B. However, as shown in FIG. 2, the right side of the movable piece 128b is higher than the left side when viewed from the front of the gaming machine 100, whereas the left side of the movable piece 120b is higher than the right side when viewed from the front of the gaming machine 100.

Now, the board configuration of the second game area 116b will be described in detail. In the simultaneous spin reference example, the second start hole 122 and the gate 124 are arranged in parallel at the top of the second game area 116b. All game balls guided to the second game area 116b either enter the second start hole 122 or pass through the gate 124 and flow downward. In the simultaneous spin reference example, one game ball is paid out as a prize ball for each game ball that enters the second start hole 122.

When a game ball enters the second starting port 122, one game ball is paid out as a prize ball, and a lottery is held to determine whether a big prize game or a small prize game will be played. In addition, when the game ball passes through the gate 124, a lottery is held to determine whether the first variable starting port 120B (movable piece 120b) will be opened.

Directly below the second starting hole 122 and the gate 124 is a first large prize opening 126. When the first large prize opening 126 is open, it is positioned so that all game balls that pass through the gate 124 and flow downward enter the first large prize opening 126. In the simultaneous spin reference example, the first large prize opening 126 is only opened during the big prize game. In other words, the first large prize opening 126 can be said to be a large prize opening exclusively for the big prize game. When a game ball enters the first large prize opening 126 during the big prize game, a predetermined number of game balls (2 or more in number, 15 in this case) are paid out as prize balls for each game ball that enters.

A first variable start opening 120B is provided below the first large prize opening 126. In addition, an outlet 131 is provided between the first large prize opening 126 and the first variable start opening 120B. The outlet 131 is the entrance to a passage for discharging game balls from the game area 116, and even if a game ball enters the outlet 131, no prize balls will be paid out.

In the second game area 116b, nails are arranged so that most (e.g., 90% or more) of the game balls that flow down below the first large winning opening 126 fall onto the movable piece 120b. In addition, these nails guide a portion (e.g., 1% to 10%) of the game balls that flow down below the first large winning opening 126 to the outlet 131.

When the first variable start opening 120B is in a closed state, the game ball rolls on the movable piece 120b. If the movable piece 120b opens while the game ball is rolling on the movable piece 120b, all the game balls on the movable piece 120b are guided into the first variable start opening 120B. When a game ball enters the first variable start opening 120B, one game ball is paid out as a prize ball for each game ball that enters, and a lottery is held to determine whether or not a big prize game or a small prize game will be played.

Gaming balls that do not enter the first variable start opening 120B fall from above the movable piece 120b to the right side when viewed from the front of the gaming machine 100. Below the first variable start opening 120B, the second large prize opening 128 is provided, and most of the gaming balls that fall from above the movable piece 120b roll on the movable piece 128b of the second large prize opening 128. Due to the inclination of the movable piece 128b, the gaming balls on the movable piece 128b slowly roll from the right side to the left side when viewed from the front of the gaming machine 100.

In the simultaneous spin reference example, which will be described in more detail later, the second large prize opening 128 is only opened during small prize play. In other words, the second large prize opening 128 can be said to be a large prize opening exclusively for small prize play. When the movable piece 128b opens while a game ball is rolling on it, all game balls on the movable piece 128b are guided into the second large prize opening 128. When a game ball enters the second large prize opening 128 during a small prize play, a predetermined number of game balls (2 or more in number, 15 in this case) are paid out as prize balls for each game ball that enters.

The normal ball operation port 125 is provided to the lower left of the second large winning port 128. Here, nails are arranged in the second game area 116b so that almost all game balls that fall downward from above the second large winning port 128 enter the normal ball operation port 125. In the simultaneous spin reference example, the normal ball operation port 125 constitutes a "specific winning port" from which one game ball is paid out as a prize ball for each game ball that enters. In addition, when a game ball enters the normal ball operation port 125, a lottery is held to determine whether or not the first variable start port 120B (movable piece 120b) is opened, just as when a game ball passes through the gate 124.

At the bottom of the game area 116, there is a discharge port 130 that discharges game balls that do not enter the general winning hole 118, the first starting hole 120, the second starting hole 122, the general operation hole 125, or the big winning hole from the game area 116 to the back side of the game board 108.

The gaming machine 100 is equipped with a performance display device 200 consisting of a liquid crystal display device, a performance prop device 202 consisting of a movable device, a performance lighting device 204 consisting of lamps that can be controlled to various lighting modes and emission colors, a sound output device 206 consisting of a speaker, and a performance operation device 208 that accepts operations by the player, as performance devices that perform performances while the game is in progress.

The effect display device 200 is equipped with a main effect display section 200a consisting of an image display section that displays images, and this main effect display section 200a is arranged in the approximate center of the game board 108 so that it can be seen from the front side of the gaming machine 100. As shown in the figure, this main effect display section 200a executes various effects, such as the display of three effect patterns 210a, 210b, and 210c in a variable manner.

The performance device 202 is located in front of the main performance display unit 200a, and is usually separated into multiple components and stored at the origin position on the back side of the game board 108 so that it cannot be seen by the player. Then, when the actuator is driven to move each component to a movable position in front of the main performance display unit 200a during the changing display of the performance patterns 210a, 210b, 210c, the components combine in front of the main performance display unit 200a, giving the player a sense of anticipation of a big win.

The lighting device 204 is provided on the prop device 202, the game board 108, etc., and is controlled to light up in various ways in accordance with the images displayed on the main display unit 200a.

The audio output device 206 is provided at the top of the front frame 106 or at the bottom of the outer frame 102, and outputs various sounds toward the front of the gaming machine 100 in accordance with the images displayed on the main performance display section 200a.

The effect operation device 208 is composed of buttons that are pressed by the player, and is located in approximately the center of the gaming machine 100 in the width direction, and below the transparent plate 110. This effect operation device 208 is activated in accordance with the images displayed on the main effect display section 200a, and when a player's operation is received within the effective operation time, various effects are executed according to the operation.

The reference symbol 132 in the figure indicates an upper tray to which prize balls paid out from the gaming machine 100 and gaming balls dispensed from the gaming ball dispensing device are guided, and when this upper tray 132 is full of gaming balls, the gaming balls are guided to the lower tray 134. A ball ejection hole (not shown) is formed in the bottom surface of this lower tray 134 for ejecting gaming balls from the lower tray 134. This ball ejection hole is normally closed by an opening/closing plate (not shown), but by pressing down on the ball ejection knob 134a, the opening/closing plate slides together with the ball ejection knob 134a, making it possible to eject gaming balls from the ball ejection hole to below the lower tray 134.

The game board 108 is provided with a first special symbol display 160, a second special symbol display 162, a first special symbol reserved display 164, a second special symbol reserved display 166, a normal symbol display 168, a normal symbol reserved display 170, and a right hit notification display 172, located outside the game area 116 and in a position visible to the player. Each of these displays 160-172 is a device for displaying various game-related situations, and will be described in detail below.

(Internal configuration of control means)
FIG. 4 is a block diagram showing the internal configuration of a control means for controlling the progress of a game in the simultaneous spin reference example.

The main control board 300 controls the basic operations of the game. This main control board 300 is equipped with a main CPU 300a, a main ROM 300b, and a main RAM 300c. The main CPU 300a reads out the programs stored in the main ROM 300b and performs arithmetic processing based on input signals from each detection switch and timer, and also directly controls each device and display, or sends commands to other boards depending on the results of the arithmetic processing. The main RAM 300c functions as a work area for data during arithmetic processing by the main CPU 300a.

The main control board 300 includes a general winning hole detection switch 118s for detecting when a game ball has entered the general winning hole 118, a first fixed starting hole detection switch 120As for detecting when a game ball has entered the first fixed starting hole 120A, a first variable starting hole detection switch 120Bs for detecting when a game ball has entered the first variable starting hole 120B, a second starting hole detection switch 122s for detecting when a game ball has entered the second starting hole 122, and a second starting hole detection switch 122s for detecting when a game ball has passed through the gate 124. A gate detection switch 124s that detects when a ball has passed the gate, a normal operation port detection switch 125s that detects when a game ball has entered the normal operation port 125, a first large prize opening detection switch 126s that detects when a game ball has entered the first large prize opening 126, and a second large prize opening detection switch 128s that detects when a game ball has entered the second large prize opening 128 are connected, and detection signals are input from each of these detection switches to the main control board 300.

The main control board 300 is also connected to a normal electric device solenoid 120c that operates the movable piece 120b of the first variable start opening 120B, a first large prize opening solenoid 126c that operates the opening and closing door 126b that opens and closes the first large prize opening 126, and a second large prize opening solenoid 128c that operates the movable piece 128b that opens and closes the second large prize opening 128. The main control board 300 controls the opening and closing of the first variable start opening 120B, the first large prize opening 126, and the second large prize opening 128.

Furthermore, the first special pattern display 160, the second special pattern display 162, the first special pattern reserved display 164, the second special pattern reserved display 166, the normal pattern display 168, the normal pattern reserved display 170, and the right hit notification display 172 are connected to the main control board 300, and the display of each of these displays is controlled by the main control board 300.

Furthermore, a setting change switch 180s is provided on the back of the game board 108. The setting change switch 180s is configured to be accessible with a dedicated key. When the setting change switch 180s is turned on, the setting value can be changed and confirmed. As will be described in detail later, in the gaming machine 100 of the simultaneous rotation reference example, one of six setting values with different degrees of advantage is stored as a registered setting value in the setting value buffer, and the game progresses according to the stored registered setting value. Note that, although it is assumed here that there are six setting values, there may be only two setting values, a high setting and a low setting, or there may be multiple other settings. Furthermore, a setting value is not essential, and the degree of advantage does not have to be changed.

A RAM clear button is provided on the back of the game board 108 so that it can be pressed, and pressing this RAM clear button is detected by the RAM clear switch 182s. The RAM clear switch 182s is connected to the main control board 300, and a RAM clear operation signal is input from the RAM clear switch 182s to the main control board 300. If a RAM clear operation signal is input from the RAM clear switch 182s when the power is turned on, the main CPU 300a clears the main RAM 300c.

In addition, a performance display monitor 184 is provided on the back of the game board 108. The main control board 300 displays the registered setting values and base ratios on the performance display monitor 184.

The gaming machine 100 of the simultaneous spin reference example is broadly divided into special games that are started mainly by a game ball entering the first start port 120 or the second start port 122, and regular games that are started by a game ball passing through the gate 124 or entering the regular operation port 125. The main ROM 300b of the main control board 300 stores various programs for progressing the special games and regular games, as well as data and tables required for various games.

The main control board 300 is also connected to a payout control board 310 and a sub-control board 330. The payout control board 310 controls the launching of game balls and the payout of prize balls. This payout control board 310 also has a CPU, ROM, and RAM, and is connected to the main control board 300 so that it can communicate in both directions. A game information output terminal board 312 is connected to this payout control board 310, and various information on the progress of the game output from the main control board 300 is output to the hall computer of the gaming facility via the payout control board 310 and the game information output terminal board 312.

The payout control board 310 is also connected to a payout motor 314 for paying out the game balls stored in the storage section to the player as prize balls. The payout control board 310 controls the payout motor 314 based on a payout number designation command sent from the main control board 300 to control it so that a specified number of prize balls are paid out to the player. At this time, the number of paid out game balls is detected by a payout ball count switch 316s, and it is possible to know whether the prize balls to be paid out have been paid out to the player.

In addition, a tray full detection switch 318s that detects the full state of the lower tray 134 is connected to the payout control board 310. This tray full detection switch 318s is provided in a passage that guides the game balls paid out as prize balls to the lower tray 134, and a game ball detection signal is input to the payout control board 310.

When the lower tray 134 is filled to capacity with more than a predetermined amount of game balls, game balls become trapped in the passageway leading to the lower tray 134, and game ball detection signals are continuously input from the full tray detection switch 318s to the payout control board 310. If the game ball detection signals are continuously input for a predetermined period of time, the payout control board 310 determines that the lower tray 134 is full, and sends a full tray command to the main control board 300. On the other hand, if the continuous input of the game ball detection signals stops after sending the full tray command, it determines that the full tray state has been released, and sends a full tray release command to the main control board 300.

The payout control board 310 is also provided with a launch control circuit 320 that controls the launch of game balls. The payout control board 310 is connected to a touch sensor 112s that is provided on the operating handle 112 and detects when the player touches the operating handle 112, and an operating volume 112a that detects the operating angle of the operating handle 112. When signals are input from the touch sensor 112s and the operating volume 112a, the launch control circuit 320 controls the energization of a launch solenoid 112c provided on the game ball launching device to launch the game balls.

The sub-control board 330 mainly controls each presentation during play, standby, etc. This sub-control board 330 is equipped with a sub-CPU 330a, a sub-ROM 330b, and a sub-RAM 330c, and is connected to the main control board 300 so that it can communicate in one direction from the main control board 300 to the sub-control board 330. The sub-CPU 330a reads out the programs stored in the sub-ROM 330b and performs calculation processing based on commands sent from the main control board 300 and input signals from a timer, and also controls the execution of the presentation. At this time, the sub-RAM 330c functions as a work area for data during calculation processing by the sub-CPU 330a.

Specifically, in the sub-control board 330, the sub-CPU 330a, sub-ROM 330b, and sub-RAM 330c work together to function as a sub-main, image control unit, prop control unit, lighting control unit, and sound control unit. The sub-main determines the content of the performance to be executed in response to various input commands, and manages and coordinates the execution of the performance. The image control unit performs image display control to display images on the main performance display unit 200a. The sub-ROM 330b stores a large amount of image data such as designs, backgrounds, and subtitles to be displayed on the main performance display unit 200a, and the image control unit reads the image data from the sub-ROM 330b to a VRAM (not shown) to control the image display on the main performance display unit 200a.

The prop control unit drives actuators in accordance with the performance management by the sub-main, and controls the movement of the prop device 202. The lighting control unit controls the lighting of the performance lighting device 204. The audio control unit controls the audio output to output audio from the audio output device 206. Sub-ROM 330b stores a large amount of audio data, such as audio and music, that is output from the audio output device 206, and the audio control unit reads out the audio data from sub-ROM 330b and controls the audio output of the audio output device 206.

Furthermore, the sub-control board 330 executes a predetermined performance when an operation detection signal is input from the performance operation device detection switch 208s, which detects that the performance operation device 208 has been pressed or rotated.

A power supply board (not shown) is connected to each board, and power is supplied to each board from a commercial power source via the power supply board. The power supply board is also provided with a backup power supply consisting of a capacitor.

Figure 5 is an address map of the memory area used by the main CPU 300a in the simultaneous rotation reference example. Note that in Figure 5, addresses are shown in hexadecimal, with "H" indicating hexadecimal. As shown in Figure 5, the memory area used by the main CPU 300a includes the memory area (0000H to 2FFFH) allocated to the main ROM 300b and the memory area (F000H to F3FFH) allocated to the main RAM 300c.

The memory area of the main ROM 300b is divided into a used area (0000H to 1BF3H) that stores programs and data for controlling the progress of the game, and a non-used area (2000H to 2BFFH) that stores programs and data for executing processes for performing tests stipulated by gaming machine regulations and processes for displaying the performance display monitor 184 (including processes for calculating the base ratio to be displayed on the performance display monitor 184).

The used area of the main ROM 300b includes a program area (0000H-0A89H) in which programs for controlling the progress of the game are stored, an unused area (0A8AH-11FFH), and a data area (1200H-1BF3H) in which data other than programs are stored. Note that the used area does not necessarily have to include the unused area (0A8AH-0FFFH).

The unused area of the main ROM 300b includes a program area (2000H to 27FFH) that stores programs for executing processes for performing tests stipulated by gaming machine regulations and processes for displaying the performance display monitor 184, and a data area (2800H to 2BFFH) that stores data other than these programs.

In addition to the used area and unused area, the memory area of main ROM 300b also includes an unused area (1A7BH-1DFFH), a ROM comment area (1E00H-1EFFH) in which arbitrary data such as the program title and version is stored, an unused area (1F00H-1FFFH), an unused area (2C00H-2FBFH), and a program management area (2FC0H-2FFFH) in which information necessary for main CPU 300a to execute a program is stored.

The memory area of the main RAM 300c is divided into a used area (F000H to F1FFH) that is temporarily used when a program for controlling the progress of the game is being executed, and a non-used area (F210H to F228H) that is an area other than the used area and is temporarily used when a program for processing tests stipulated by the gaming machine regulations or processing for displaying the performance display monitor 184 is being executed.

The used area of the main RAM 300c includes a work area (F000H-F12AH) that is temporarily used when a program for controlling the progress of the game is being executed, an unused area (F12BH-F1D7H), and a stack area (F1D8H-F1FFH) where data is temporarily saved while a program for controlling the progress of the game is being executed. Note that the used area does not have to include the unused area (F12BH-F1D7H).

The unused area of the main RAM 300c includes a work area (F210H to F21FH) that is temporarily used when programs are being executed for processing tests stipulated by gaming machine regulations and processing for displaying the performance display monitor 184, and a stack area (F220H to F228H) that temporarily stores data when these programs are being executed.

In addition to the used area and unused area, the memory area of main RAM 300c also includes an unused area (F200H to F20FH) and an unused area (F229H to F3FFH).

In this way, main ROM 300b and main RAM 300c are provided with separate areas: a used area used to control the progress of the game, and a non-used area used to execute processes for performing tests stipulated by gaming machine regulations and processes for controlling the display of the performance display monitor 184.

The main RAM 300c has a 16-byte unused area (F200H-F20FH) between the used area and the unused area. This unused area (F200H-F20FH) is set as a boundary area that separates the used area and the unused area, making the boundary between the used area and the unused area clear, preventing the unused area from being used when a program for controlling the progress of the game is being executed, and preventing the used area from being used when a program for processing tests defined by the gaming machine regulations or processing for controlling the display of the performance display monitor 184 is being executed.

The unused area between the used area and the unused area only needs to be at least 1 byte, and from the viewpoint of preventing fraud, it is preferable that it be 4 bytes or more, and more preferably set to 16 bytes or more. Furthermore, writing and reading of data into the unused area is prohibited, but from the viewpoint of preventing fraud, it may be cleared at a specified time.

In addition, the memory space from FE00h to FFFFh is assigned to an input/output unit. This input/output unit will be described in detail later.

Next, we will explain how to play the simultaneous spin reference example gaming machine 100, along with the various tables stored in the main ROM 300b.

As mentioned above, the gaming machine 100 of the simultaneous spin reference example has two types of games, special game and normal game, progressing in parallel. The special game progresses in either a low probability game state or a high probability game state, while the normal game progresses in either a non-time-saving game state, a medium time-saving game state, or a time-saving game state.

Details of each game state will be described later, but the low probability game state is a game state in which the probability of acquiring the right to play the big prize game in which the big prize opening is opened is set low, and the high probability game state is a game state in which the probability of acquiring the right to play the big prize game is set high. In addition, the non-time-saving game state is a game state in which the movable piece 120b is less likely to be in the open state and the game ball is less likely to enter the first variable start opening 120B, and the intermediate time-saving game state is a game state in which the movable piece 120b is more likely to be in the open state than the non-time-saving game state and the game ball is more likely to enter the first variable start opening 120B. In addition, the time-saving game state is a game state in which the movable piece 120b is even more likely to be in the open state than the intermediate time-saving game state and the game ball is most likely to enter the first variable start opening 120B. In addition, in the time-saving game mode, if game balls continue to be shot toward the second game area 116b during play, the game balls are set to decrease slightly or not at all.

As described above, since the special game and the normal game proceed simultaneously in parallel, in the simultaneous spin reference example, the game state is a combination of a low probability game state or a high probability game state with either a non-time-saving game state, a medium time-saving game state, or a time-saving game state. In the following, for ease of understanding, the game states related to the special game, i.e., the low probability game state and the high probability game state, may be referred to as special game states, and the game states related to the normal game, i.e., the non-time-saving game state, the medium time-saving game state, and the time-saving game state, may be referred to as normal game states. The initial state of the gaming machine 100 is set to the low probability game state and the non-time-saving game state.

When a player operates the operating handle 112 to launch a game ball into the game area 116, and the game ball flowing down the game area 116 enters the first start port 120 or the second start port 122, a lottery (hereinafter referred to as the "big prize lottery") is held to determine whether or not the player will be awarded a game profit. In this big prize lottery, if a big win is won, a big prize opening is opened and a big prize game is executed in which the game ball can enter the big prize opening, and the game state after the big prize game ends is set to one of the game states described above. The big prize lottery method is explained below.

As will be described in more detail later, when a game ball enters the first start hole 120 or the second start hole 122, various random number values related to the big role lottery (jackpot determining random number, winning symbol random number, reach group determining random number, reach mode determining random number, variable pattern random number) are obtained, and each of these random number values is stored in the special symbol reserve memory area of the main RAM 300c. In the following, the various random numbers stored in the special symbol reserve memory area when a game ball enters the first start hole 120 are collectively referred to as special 1 reserve, and the various random numbers stored in the special symbol reserve memory area when a game ball enters the second start hole 122 are collectively referred to as special 2 reserve.

The special chart reservation memory area of the main RAM 300c includes a first special chart reservation memory area and a second special chart reservation memory area. The first special chart reservation memory area and the second special chart reservation memory area each have four memory sections (first to fourth memory sections). When a game ball enters the first starting hole 120, the special 1 reservation is stored in order starting from the first memory section of the first special chart reservation memory area, and when a game ball enters the second starting hole 122, the special 2 reservation is stored in order starting from the first memory section of the second special chart reservation memory area.

For example, when a game ball enters the first starting hole 120, if no reserve is stored in any of the first to fourth memory sections of the first special chart reserve memory area, a special 1 reserve is stored in the first memory section. Also, for example, if a game ball enters the first starting hole 120 while a special 1 reserve is stored in the first to third memory sections, the special 1 reserve is stored in the fourth memory section. Also, when a game ball enters the second starting hole 122, similar to the above, a special 2 reserve is stored in the memory section with the smallest number (ordinal number) among the first to fourth memory sections of the second special chart reserve memory area where a special 2 reserve is not stored.

However, the number of special 1 reservations (X1) and the number of special 2 reservations (X2) that can be stored in the first special chart reservation memory area and the second special chart reservation memory area are each set to four. Therefore, for example, if four special 1 reservations are already stored in the first special chart reservation memory area when a game ball enters the first starting hole 120, no new special 1 reservations will be stored by the game ball entering the first starting hole 120. Similarly, if four special 2 reservations are already stored in the second special chart reservation memory area when a game ball enters the second starting hole 122, no new special 2 reservations will be stored by the game ball entering the second starting hole 122.

Figure 6 is a diagram explaining the low probability jackpot determination random number judgment table for the simultaneous spin reference example. When a game ball enters the first start hole 120 or the second start hole 122, one jackpot determination random number is obtained from the range of 0 to 65535. Then, when the big win lottery starts, that is, according to the game state when the jackpot determination is made, a jackpot determination random number judgment table is selected, and the big win lottery is performed using the selected jackpot determination random number judgment table and the obtained jackpot determination random number.

When starting the big prize lottery for special 1 reserve and special 2 reserve in a low probability game state, the low probability jackpot determination random number judgment table is referenced. Here, in the simultaneous spin reference example, six setting values with different degrees of advantage are provided, and a low probability jackpot determination random number judgment table is provided for each setting value. During play, the setting value is set to one of the six levels, and the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table corresponding to the currently set setting value (registered setting value stored in the setting value buffer).

When the game is in a low probability game state and the setting value is set to 1 (registered setting value = 1), the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table a shown in FIG. 6 (a). According to this low probability jackpot determination random number judgment table a, if the jackpot determination random number is between 10001 and 10218, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/300.6, and the probability of a small jackpot is approximately 1/3.45.

When the game is in a low probability game state and the setting value is set to 2 (registered setting value = 2), the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table b shown in Figure 6 (b). According to this low probability jackpot determination random number judgment table b, if the jackpot determination random number is between 10001 and 10225, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/291.2, and the probability of a small jackpot is approximately 1/3.45.

When the game is in a low probability game state and the setting value is set to 3 (registered setting value = 3), the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table c shown in Figure 6 (c). According to this low probability jackpot determination random number judgment table c, if the jackpot determination random number is between 10001 and 10232, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/282.4, and the probability of a small jackpot is approximately 1/3.45.

When the game is in a low probability game state and the setting value is set to 4 (registered setting value = 4), the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table d shown in Figure 6 (d). According to this low probability jackpot determination random number judgment table d, if the jackpot determination random number is between 10001 and 10239, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/274.2, and the probability of a small jackpot is approximately 1/3.45.

When the game is in a low probability game state and the setting value is set to 5 (registered setting value = 5), the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table e shown in Figure 6 (e). According to this low probability jackpot determination random number judgment table e, if the jackpot determination random number is between 10001 and 10246, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/266.4, and the probability of a small jackpot is approximately 1/3.45.

When the game is in a low probability game state and the setting value is set to 6 (registered setting value = 6), the big prize lottery is performed by referring to the low probability jackpot determination random number judgment table f shown in Figure 6 (f). According to this low probability jackpot determination random number judgment table f, if the jackpot determination random number is between 10001 and 10253, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/259.0, and the probability of a small jackpot is approximately 1/3.45.

Figure 7 is a diagram explaining the random number judgment table for determining a high probability jackpot in the simultaneous spin reference example. When starting a lottery for a big prize for special 1 reserve and special 2 reserve in a high probability game state, the random number judgment table for determining a high probability jackpot is referenced. The random number judgment table for determining a high probability jackpot is also set for each setting value, just like the random number judgment table for determining a low probability jackpot.

When the game is in a high probability game state and the setting value is set to 1 (registered setting value = 1), the big prize lottery is performed by referring to the high probability jackpot determination random number judgment table a shown in Figure 7 (a). According to this high probability jackpot determination random number judgment table a, if the jackpot determination random number is between 10001 and 10620, it is judged to be a jackpot, if the jackpot determination random number is between 20001 and 38996, it is judged to be a small jackpot, and if it is any other jackpot determination random number, it is judged to be a miss. Therefore, in this case, the probability of a jackpot is approximately 1/105.7, and the probability of a small jackpot is approximately 1/3.45.

Similarly, when the game is in a high probability game state and the setting value is set to 2 to 6 (registered setting value = 2 to 6), the big prize lottery is performed by referring to high probability jackpot determination random number judgment tables b to f shown in Figures 7 (b) to (f). According to these high probability jackpot determination random number judgment tables b to f, a jackpot is judged to have occurred when the jackpot determination random number is the value shown. Therefore, when the setting value is 2 to 6, the jackpot probability is approximately 1/102.4 to 1/91.0, respectively, and the small jackpot probability is approximately 1/3.45.

As described above, the big prize lottery is held according to the registered setting value. At this time, the probability of winning a big prize differs according to the registered setting value, and it is easier to win a big prize when the registered setting value is large than when it is small. Note that here, even if the registered setting value differs, the probability of winning a small prize does not change, but the probability of winning a small prize may be different for each registered setting value. Also, a small prize is not required, and only either a big prize or a miss may be determined in the big prize lottery.

In addition, here, the probability of winning a jackpot in both the low-probability game state and the high-probability game state is set to differ depending on the registered setting value, but it is also possible to set it so that only the probability of winning a jackpot in either the low-probability game state or the high-probability game state differs depending on the registered setting value.

Figure 8 is a diagram explaining the winning symbol random number determination table and the small winning symbol random number determination table for the simultaneous spin reference example. When a game ball enters the first start hole 120 or the second start hole 122, one winning symbol random number within the range of 0 to 99 is obtained. Then, when a "big win" determination result is derived by the above-mentioned big role lottery, the type of special symbol is determined based on the obtained winning symbol random number and the winning symbol random number determination table. At this time, if the "big win" is won by the special 1 reservation, the winning pattern random number judgment table a for special 1 is selected as shown in FIG. 8(a), if the "big win" is won by the special 2 reservation, the winning pattern random number judgment table b for special 2 is selected as shown in FIG. 8(b), if the "small win" is won by the special 1 reservation, the small win pattern random number judgment table a for special 1 is selected as shown in FIG. 8(c), and if the "small win" is won by the special 2 reservation, the small win pattern random number judgment table b for special 2 is selected as shown in FIG. 8(d). In the following, the special pattern determined by the winning pattern random number, that is, the special pattern determined when the judgment result of the big win is obtained, is called the big win pattern, the special pattern determined when the judgment result of the small win is obtained is called the small win pattern, and the special pattern determined when the judgment result of the loss is obtained is called the loss pattern.

According to the special 1 winning symbol random number determination table a shown in FIG. 8(a) and the special 2 winning symbol random number determination table b shown in FIG. 8(b), a big winning symbol (special symbols A to J) is determined as the special symbol according to the value of the acquired winning symbol random number, as shown in the figure. Also, according to the special 1 small winning symbol random number determination table a shown in FIG. 8(c) and the special 2 small winning symbol random number determination table b shown in FIG. 8(d), a small winning symbol (special symbols Z1 to Z6) is determined as the special symbol according to the value of the acquired winning symbol random number, as shown in the figure.

When the result of the big prize lottery is a "miss", if the result is derived by special 1 reservation, special pattern X is determined as the missing pattern without drawing a lottery, and when the result is derived by special 2 reservation, special pattern Y is determined as the missing pattern without drawing a lottery. In other words, the winning pattern random number determination table is referenced only when the result of the big prize lottery is a "big prize", and is not referenced when the result of the big prize lottery is a "miss" or a "small prize". In addition, the small prize pattern random number determination table is referenced only when the result of the big prize lottery is a "small prize", and is not referenced when the result of the big prize lottery is a "big prize" or a "miss". In addition, the special patterns Z1 to Z6, which are the small prize patterns, are collectively referred to simply as special pattern Z.

Figure 9 is a diagram illustrating a reach group determination random number judgment table for the simultaneous spin reference example. A plurality of reach group determination random number judgment tables are provided, and a preset table is selected according to the reserved type, reserved number, game status, etc. When a game ball enters the first start hole 120 or the second start hole 122, one reach group determination random number is obtained from the range of 0 to 10006. As described above, when the big role lottery result is derived, a process is performed to determine a variable presentation pattern that notifies the big role lottery result. In the simultaneous spin reference example, when the big role lottery result is a "miss", in determining the variable presentation pattern, first, the group type is determined by the reach group determination random number and the reach group determination random number judgment table.

For example, when the game state is set to the normal state, which will be described in detail later, if a "miss" big role lottery result is derived based on the special 1 reservation, and the number of reserved special 1s (hereinafter simply referred to as the "reserved number") at the time of the big role lottery is 0, the reach group determination random number judgment table 1 is selected as shown in FIG. 9(a). Similarly, when the game state is set to the normal state, if a "miss" big role lottery result is derived based on the special 1 reservation, and the number of reserved special roles at the time of the big role lottery is 1 to 2, the reach group determination random number judgment table 2 is selected as shown in FIG. 9(b), and if the number of reserved special roles is 3, the reach group determination random number judgment table 3 is selected as shown in FIG. 9(c). In FIG. 9, the group x written in the group type column indicates an arbitrary group number. Therefore, various group numbers are determined as the group type depending on the acquired reach group determination random number and the type of reach group determination random number judgment table to be referenced.

Note that, here, we have explained the reach group determination random number judgment table that is referenced when a "miss" major role lottery result is derived based on the special 1 reserved in the normal state, but many other reach group determination random number judgment tables are stored in the main ROM 300b.

If the result of the big prize lottery is a "big prize" or a "small prize", the group type is not determined when deciding the variable presentation pattern. In other words, the reach group determination random number judgment table is only referenced when the result of the big prize lottery is a "miss", and is not referenced when the result of the big prize lottery is a "big prize" or a "small prize".

Figure 10 is a diagram explaining the reach mode determination random number judgment table for the simultaneous spin reference example. This reach mode determination random number judgment table is broadly divided into a miss reach mode determination random number judgment table that is selected when the big role lottery result is a "miss", a big win reach mode determination random number judgment table that is selected when the big role lottery result is a "big win", and a small win reach mode determination random number judgment table that is selected when the big role lottery result is a "small win". The miss reach mode determination random number judgment table is provided for each group type determined as described above, and the big win reach mode determination random number judgment table and the small win reach mode determination random number judgment table are provided for each game state and hold type.

In addition, each reach mode determination random number judgment table is also provided for each game state and type of pattern. Here, an example of a reach mode determination random number judgment table for group x when it is a miss, which is referenced in a specific game state and type of pattern, is shown in FIG. 10(a), an example of a reach mode determination random number judgment table for a special 1 big win is shown in FIG. 10(b), an example of a reach mode determination random number judgment table for a special 2 big win is shown in FIG. 10(c), an example of a reach mode determination random number judgment table for a special 1 small win is shown in FIG. 10(d), and an example of a reach mode determination random number judgment table for a special 2 small win is shown in FIG. 10(e).

When a game ball enters the first start hole 120 or the second start hole 122, one reach mode determination random number is obtained from the range of 0 to 250. If the result of the big role lottery is a "miss," as shown in FIG. 10(a), a reach mode determination random number judgment table at the time of a miss corresponding to the group type determined by the group type lottery is selected, and a variable mode number is determined based on the selected reach mode determination random number judgment table at the time of a miss and the reach mode determination random number. If the result of the big role lottery is a "jackpot," as shown in FIG. 10(b) and (c), a reach mode determination random number judgment table at the time of a jackpot win corresponding to the game state at the time of the jackpot win and the read-out reserve type is selected, and a variable mode number is determined based on the selected reach mode determination random number judgment table at the time of a jackpot win and the reach mode determination random number.

Furthermore, if the result of the big prize lottery is a "small win," as shown in Figures 10(d) and (e), a random number judgment table for determining the reach mode at the time of the small win corresponding to the game state at the time of the small win and the hold type that was read out is selected, and a variable mode number is determined based on the selected random number judgment table for determining the reach mode at the time of the small win and the reach mode determination random number.

In addition, in each reach mode determination random number judgment table, the reach mode determination random number is associated with a fluctuation pattern random number judgment table described later along with the fluctuation mode number, and the fluctuation pattern random number judgment table is determined at the same time as the fluctuation mode number is determined. In FIG. 10, the table x written in the fluctuation pattern random number judgment table column indicates an arbitrary table number. Therefore, the fluctuation mode number and the table number of the fluctuation pattern random number judgment table are determined according to the acquired reach group determination random number and the type of reach mode determination random number judgment table to be referenced. In the simultaneous rotation reference example, the fluctuation mode number and the fluctuation pattern number described later are set in hexadecimal. In the following, "H" is added to indicate hexadecimal numbers, but ○○H written in FIG. 10 to FIG. 12 indicates an arbitrary value expressed in hexadecimal numbers.

As described above, if the result of the big role lottery is a "miss," the group type is first determined by the reach group determination random number judgment table and reach group determination random number shown in Figure 9. Then, depending on the determined group type and game status, the fluctuation mode number and fluctuation pattern random number judgment table are determined by the reach mode determination random number judgment table at the time of a miss and the reach mode determination random number shown in Figure 10 (a).

On the other hand, if the result of the big prize lottery is a "big win" or a "small win," the system will refer to the big win reach mode determination random number judgment table shown in Figure 10, which corresponds to the determined big win or small win pattern (type of special pattern), the game state when the big win or small win is won, and use the reach mode determination random number to determine the fluctuation mode number and fluctuation pattern random number judgment table.

Figure 11 is a diagram explaining a fluctuation pattern random number determination table for a simultaneous rotation reference example. Here, fluctuation pattern random number determination table x for a specific table number x is shown, but in addition to this, many other fluctuation pattern random number determination tables are provided for each table number.

When a game ball enters the first starting hole 120 or the second starting hole 122, one fluctuation pattern random number is obtained from the range of 0 to 238. Then, based on the fluctuation pattern random number determination table determined at the same time as the above fluctuation mode number and the obtained fluctuation pattern random number, the fluctuation pattern number is determined as shown in the figure.

In this way, when the big prize lottery is held, the change mode number and change pattern number are determined according to the big prize lottery result, the determined symbol type, the game status, the number of reserved balls, the reserved ball type, etc. These change mode numbers and change pattern numbers specify the change presentation pattern, and each of them is associated with the mode and time of the change presentation.

Figure 12 is a diagram illustrating a variation time determination table for the simultaneous rotation reference example. Once the variation mode number is determined as described above, variation time 1 is determined according to the variation time 1 determination table shown in Figure 12 (a). According to this variation time 1 determination table, variation time 1 is associated with each variation mode number, and the corresponding variation time 1 is determined according to the determined variation mode number.

Once the fluctuation pattern number is determined as described above, the fluctuation time 2 is determined according to the fluctuation time 2 determination table shown in FIG. 12(b). According to this fluctuation time 2 determination table, a fluctuation time 2 is associated with each fluctuation pattern number, and the corresponding fluctuation time 2 is determined according to the determined fluctuation pattern number. The total time of the fluctuation times 1 and 2 determined in this way is the time of the fluctuation performance that notifies the result of the big role lottery, that is, the fluctuation time. This fluctuation time is the time until the determined special pattern is stopped and displayed on the first special pattern display device 160 or the second special pattern display device 162.

As will be described in more detail below, when a special pattern is determined based on the special 1 reservation and the change mode number and change pattern number, i.e., the change time, are determined, the change of the pattern is displayed on the first special pattern display 160 for the determined change time, and when the change time has elapsed, the determined special pattern is displayed stationary on the first special pattern display 160. Also, when a special pattern is determined based on the special 2 reservation and the change pattern number, i.e., the change time, are determined, the change of the pattern is displayed on the second special pattern display 162 for the determined change time, and when the change time has elapsed, the determined special pattern is displayed stationary on the second special pattern display 162. At this time, when a losing symbol is stopped and displayed on the first special symbol display 160, a loss is confirmed as a result of the big role lottery, and the big role lottery based on the next special 1 reservation can be executed, and when a losing symbol is stopped and displayed on the second special symbol display 162, a loss is confirmed as a result of the big role lottery, and the big role lottery based on the next special 2 reservation can be executed. On the other hand, when a big win symbol is stopped and displayed on the first special symbol display 160 or the second special symbol display 162, a big win is confirmed as a result of the big role lottery, and a big role game is executed, and when a small win symbol is stopped and displayed on the first special symbol display 160 or the second special symbol display 162, a small win is confirmed as a result of the big role lottery, and a small win game is executed.

In this way, the change time stipulates the time for which the pattern on the first special pattern display device 160 or the second special pattern display device 162 changes and displays, in other words, the time until the result of the big prize lottery is determined.

When the fluctuation mode number is determined in the above manner, a fluctuation mode command corresponding to the determined fluctuation mode number is sent to the sub-control board 330, and when the fluctuation pattern number is determined, a fluctuation pattern command corresponding to the determined fluctuation pattern number is sent to the sub-control board 330. In the sub-control board 330, the first half of the fluctuation performance is mainly determined based on the received fluctuation mode command, and the second half of the fluctuation performance is mainly determined based on the received fluctuation pattern command, but the details will be described later. Note that, below, the fluctuation mode number and the fluctuation pattern number are collectively referred to as fluctuation information, and the fluctuation mode command and the fluctuation pattern command are collectively referred to as fluctuation commands.

Figure 13 is a diagram explaining the game states and variable times in the simultaneous spin reference example. As described above, the special game state and the normal game state are combined to form one game state, and the progress of the game is controlled according to the game state being set. As already explained, there are two types of special game states, a low probability game state and a high probability game state, which differ in the probability of winning a jackpot. In addition, there are three types of normal game states, a non-time-saving game state, a medium time-saving game state, and a time-saving game state, which differ in the ease (ball-scoring frequency) of entering the first variable start hole 120B.

Here, in normal play, the ease with which a game ball can enter the first variable start port 120B is determined by three factors: winning probability, fluctuation time, and opening time. As will be described in detail later, in normal play, when a game ball passes through the gate 124 or enters the normal play operation port 125, a normal play reserve is stored. Then, based on the stored normal play reserve, a normal play lottery is held to determine whether or not to open the movable piece 120b. The result of this normal play lottery is determined after a predetermined fluctuation time has elapsed. When a win is determined as a result of the normal play lottery, the movable piece 120b is opened. At this time, the winning probability in the normal play lottery, the fluctuation time, and the opening time when opening the movable piece 120b are each set for each normal play state.

In the simultaneous spin reference example, as shown in FIG. 13(a), six types of game states are provided by combining special game states and normal game states. The initial state of the gaming machine 100 is a low probability game state and a non-time-saving game state. In the non-time-saving game state, the probability of winning in the normal drawing is low, the fluctuation time is long, and the opening time of the movable piece 120b is short. In the simultaneous spin reference example, a game state that combines a low probability game state and a non-time-saving game state is called a normal state.

In the simultaneous spin reference example, the game state may be set to a high probability game state and a non-time-saving game state, and the game state that combines these two is called the most advantageous state. This most advantageous state is the most advantageous of the six game states, and is set so that if the game balls are fired appropriately, the number of game balls will gradually increase during play, even if a jackpot is not won.

In addition, in the simultaneous spin reference example, the game may be set to a low probability game state and a time-saving game state. In the time-saving game state, the probability of winning in the regular drawing is high, the fluctuation time is short, and the opening time of the movable piece 120b is long. In the following, a game state that combines the low probability game state and the time-saving game state is called a low probability time-saving state.

In addition, in the simultaneous spin reference example, the game state may be set to a high probability game state and a time-saving game state. In the following, a game state in which a high probability game state and a time-saving game state are combined is referred to as a high probability time-saving state or a high probability precursor state. The high probability time-saving state and the high probability precursor state will be described in more detail later.

In the simultaneous spin reference example, the game may be set to a high probability game state and a medium time-saving game state. In the medium time-saving game state, the probability of winning in the normal drawing is higher than in the non-time-saving game state and lower than in the time-saving game state, the fluctuation time is short, and the opening time of the movable piece 120b is long. This game state can be set when an unforeseen event occurs, such as when the game ball is not launched appropriately. Hereinafter, a game state that combines a high probability game state and a medium time-saving game state is called a penalty state.

In addition, a presentation mode corresponding to the game state set on the main control board 300 is set on the sub-control board 330. The presentation mode specifies the background image and BGM displayed on the main presentation display section 200a, and the content of the presentation differs for each presentation mode. In other words, the player can identify the current game state by the presentation mode.

As described above, in the simultaneous spin reference example, six game states are provided. As described above, the change mode number and change pattern number, i.e., the change time, are determined according to the game state when the big role lottery is performed, the reserved type, the number of changes in that game state, and the type of pattern.

Here, in the gaming machine 100, an actual variable target is set for each gaming state. The actual variable target indicates the type of reserve for which the big prize lottery should be held, and for each gaming state, either the special 1 reserve or the special 2 reserve is set as the actual variable target. In the normal state, the special 1 reserve is set as the actual variable target. Also, in the normal state, since the normal gaming state is a non-time-saving gaming state, the first variable start port 120B is rarely opened. Therefore, in the normal state, the player needs to shoot the gaming ball toward the first gaming area 116a in order to make the gaming ball enter the first fixed start port 120A.

In the normal state, the special 1 reserved ball, which is the actual variable, is used to draw a big prize, and when a losing symbol or a small winning symbol is determined, the variable time is determined within a range of 3 to 100 seconds. Also, in the normal state, the special 1 reserved ball is used to draw a big prize, and when a winning symbol is determined, the variable time is determined within a range of 40 to 100 seconds.

On the other hand, in the normal state, when a big prize lottery is held based on the special 2 reserve, which is not actually subject to fluctuation, the fluctuation time is always set to 10 minutes regardless of the determined symbol type. In this way, by setting the fluctuation time to a long time such as 10 minutes, in the normal state, even if the player puts the game ball into the second starting hole 122, the opportunity to hold a big prize lottery based on the special 2 reserve becomes extremely low.

To be more specific, the second start hole 122 is provided in the second play area 116b, and is configured as a fixed start hole that game balls can always enter. Furthermore, due to the playability of the gaming machine 100, the second start hole 122 is located in a position where game balls can enter more easily than the first start hole 120. Therefore, if the fluctuation time for the special 2 reservation is set to a short time in the normal state, the player will be given more opportunities than necessary to win the big prize lottery. Therefore, in accordance with the original playability in the normal state, the fluctuation time is set to a long time, such as 10 minutes, in order to appropriately launch game balls toward the first play area 116a.

In the most advantageous state, the special 2 reserve is set as the actual variable. Therefore, in the most advantageous state, the player needs to shoot the game ball toward the second game area 116b in order to make the game ball enter the second starting hole 122. In the most advantageous state, when a big role lottery is performed by the special 1 reserve, which is not an actual variable, the variable time is always set to 10 seconds regardless of the determined pattern type. Note that the effect on playability is smaller when a big role lottery is performed by the special 1 reserve, which is not an actual variable, in the most advantageous state than when a big role lottery is performed by the special 2 reserve, which is not an actual variable, in the normal state. Therefore, in the most advantageous state, the variable time when a big role lottery is performed by the special 1 reserve, which is not an actual variable, is set to a short time of 10 seconds.

In the most advantageous state, a lottery for a big prize is held by the special 2 reserved symbol, which is the actual variable target, and when a losing symbol or a small winning symbol is determined, the variable time is determined within a range of 1 to 3 seconds. Also, in the most advantageous state, a lottery for a big prize is held by the special 2 reserved symbol, and when a big winning symbol is determined, the variable time is determined within a range of 3 to 10 seconds.

In both the low-probability time-saving state and the high-probability time-saving state, the special 1 reservation is set as the actual variable target. In addition, in the low-probability time-saving state and the high-probability time-saving state, the normal game state is set as the time-saving game state, and the first variable start port 120B is frequently controlled to the open state. Therefore, in these two game states, the player needs to launch the game ball toward the second game area 116b to make the game ball enter the first variable start port 120B. In both of these game states, the same variable pattern random number judgment table is selected, but these two game states have in common that the normal game state is a time-saving game state. In other words, when the normal game state is a time-saving game state, a big role lottery is performed by the special 1 reservation, which is the actual variable target, and when a losing pattern or a small winning pattern is determined, a variable time of 1 second is always determined. Also, in the low probability time-saving state or high probability time-saving state, a lottery for a big role is held by special 1 reservation, and when a big win pattern is determined, the fluctuation time is always set to 30 seconds.

In the high probability premonition state, the special 1 reserve is set as the actual variable target. Also, in the high probability premonition state, the normal game state is set as the time-saving game state, and the first variable start port 120B is frequently controlled to the open state. Therefore, in the high probability premonition state, the player needs to shoot the game ball toward the second game area 116b to make the game ball enter the first variable start port 120B. In the high probability premonition state, a big role lottery is performed using the special 1 reserve, which is the actual variable target, and when a losing pattern or a small winning pattern is determined, the variable time is determined within the range of 3 to 10 seconds. Also, in the high probability premonition state, a big role lottery is performed using the special 1 reserve, and when a big winning pattern is determined, the variable time is always determined to be 30 seconds.

On the other hand, in the low probability time-saving state, high probability time-saving state, and high probability premonition state, i.e., when the normal game state is a time-saving game state, if a big role lottery is held by a special 2 reserve that is not actually subject to change, the change time is always set to 10 minutes regardless of the type of pattern that is determined.

In the penalty state, the special 1 reserved ball is set as the actual variable object. Also, in the penalty state, the normal game state is set as the medium time shortening game state, and the first variable start port 120B is controlled to be in the open state at a certain frequency. Therefore, in the penalty state, the player needs to shoot the game ball toward the second game area 116b in order to make the game ball enter the first variable start port 120B. In the penalty state, a big role lottery is performed by the special 1 reserved ball, which is the actual variable object, and when a losing symbol or a small winning symbol is determined, the variable time is determined within a range of 3 to 100 seconds. Also, in the penalty state, a big role lottery is performed by the special 1 reserved ball, and when a big winning symbol is determined, the variable time is determined within a range of 40 to 100 seconds.

On the other hand, in a penalty state, if a big prize lottery is held by a special 2 reserve that is not actually subject to change, the change time is always set to 10 minutes, regardless of the type of symbol that is determined.

As described above, an actual change target is set for each game state, and when a big role lottery is held based on a reserved type that is an actual change target, the longest change time is 100 seconds. On the other hand, when a big role lottery is held based on a reserved type that is not an actual change target, the change time is approximately 10 minutes, so that games that go against the original gameplay are not played.

In the simultaneous spin reference example, a case is described in which the average fluctuation time of the high-probability time-saving state is shorter than the average fluctuation time of the high-probability precursor state, but the average fluctuation time of the high-probability time-saving state may be longer than the average fluctuation time of the high-probability precursor state. In other words, the average fluctuation time of the high-probability time-saving state and the average fluctuation time of the high-probability precursor state may be different.

Figure 14 is a first diagram explaining the special electric role operation ram set table relating to the simultaneous rotation reference example, and Figure 15 is a second diagram explaining the special electric role operation ram set table relating to the simultaneous rotation reference example. The special electric role operation ram set table stores various data for controlling the big role game or the small win game, and during the big role game and the small win game, the first big win port solenoid 126c or the second big win port solenoid 128c is controlled to be energized by referring to the special electric role operation ram set table. In reality, a plurality of special electric role operation ram set tables are provided for each type of special pattern (big win pattern and small win pattern), and the corresponding table is set at the start of the big role game or the small win game according to the type of special pattern determined, but here, for convenience of explanation, the control data of the special pattern is shown for each type of pattern.

As shown in FIG. 14, the big prize game consists of multiple rounds of play in which the big prize opening is opened and closed a predetermined number of times, while the small prize game consists of only one round of play. According to this special electric device operation ram set table, the opening time (waiting time until the first round of play begins), the maximum number of times the special electric device operates (the number of rounds of play executed during one big win play or small win play), the number of times the special electric device opens and closes (the number of times the large prize opening is opened during one round), the solenoid energization time (the energization time of the first large prize opening solenoid 126c or the second large prize opening solenoid 128c for each number of times the large prize opening is opened, i.e., the opening time of one large prize opening), the specified number (the maximum number of times a large prize opening can be won in one round of play), the effective time for closing the large prize opening (the closing time of the large prize opening between rounds of play, i.e., the interval time), and the ending time (the waiting time from the end of the last round of play until the normal special play (the variable display of the patterns described later) is resumed) are stored in advance as control data for each type of special pattern as shown in the figure.

If a jackpot is won by the special 1 reservation and the special symbols A, B, or D are determined as the jackpot symbol, a big prize game consisting of four rounds of play is executed. In this big prize game, the first big prize opening 126 is opened only once each in the first to fourth rounds of play. In each round of play, the first big prize opening 126 is opened for a maximum of 29.0 seconds, and when a specified number of game balls enter during this time or the maximum opening time (29.0 seconds) has elapsed, the first big prize opening 126 is closed and one round of play ends.

In addition, if a jackpot is won by the special 1 reservation and the special symbols C and E are determined as the jackpot symbols, a jackpot game consisting of 10 rounds of play is executed. In these jackpot games, the first jackpot opening 126 is opened only once each in the first to tenth rounds of play. In each round of play, the first jackpot opening 126 is opened for a maximum of 29.0 seconds, and when a specified number of game balls enter during this time or the maximum opening time (29.0 seconds) has elapsed, the first jackpot opening 126 is closed and one round of play ends.

In addition, if a small prize is won by the special 1 reservation and the special symbols Z1 to Z3 are determined as the small prize symbol, a small prize game consisting of one round of play is executed. In this small prize game, the second large prize opening 128 is opened once for 0.1 seconds during one round of play.

As shown in FIG. 15, if a jackpot is won by the special 2 reserve and the special symbols F, G, or I are determined as the jackpot symbol, a big prize game consisting of four rounds of play is executed. In this big prize game, the first big prize opening 126 is opened only once each in the first to fourth rounds of play. In each round of play, the first big prize opening 126 is opened for a maximum of 29.0 seconds, and when a specified number of game balls enter during this time or the maximum opening time (29.0 seconds) has elapsed, the first big prize opening 126 is closed and one round of play ends.

In addition, if a jackpot is won by the special 2 reserve and the special symbols H and J are determined as the jackpot symbols, a jackpot game consisting of 10 rounds of play is executed. In this jackpot game, the first jackpot opening 126 is opened only once each in the first to tenth rounds of play. In each round of play, the first jackpot opening 126 is opened for a maximum of 29.0 seconds, and when a specified number of game balls enter during this time or the maximum opening time (29.0 seconds) has elapsed, the first jackpot opening 126 is closed and one round of play ends.

In addition, if a small prize is won by the special 2 reservation and the special symbols Z4 to Z6 are determined as the small prize symbol, a small prize game consisting of one round of play is executed. Here, in the small prize game when the special symbol Z4 is determined as the small prize symbol, the second large prize opening 128 is opened twice for 0.1 seconds in one round of play. The interval time during the round, which is the pause time between the two openings of the second large prize opening 128, is set to 1.78 seconds. Since the game balls are shot at intervals of 0.6 seconds at the shortest, the probability that the game balls will enter the second large prize opening 128 during this small prize game is low, considering the opening time of the second large prize opening 128 and the shooting interval of the game balls.

However, in the simultaneous spinning reference example, the structure is such that game balls tend to remain on the movable piece 128b that keeps the second large prize opening 128 in a closed state, and when the movable piece 128b transitions to an open state, the game balls remaining on the movable piece 128b are guided into the second large prize opening 128. Therefore, when the second large prize opening 128 is opened twice for 0.1 seconds, an average of 2 to 3 game balls enter the second large prize opening 128.

In addition, in a small prize game in which the special symbol Z5 is determined as the small prize symbol, the second large prize opening 128 is opened 0.1 seconds x 3 times in one round of play. In this case, the interval time during the round is set to 0.84 seconds. In this small prize game, an average of 3 to 4 game balls enter the second large prize opening 128.

Furthermore, in a small prize game in which the special pattern Z6 is determined as the small prize pattern, the second large prize opening 128 is opened 0.1 seconds x 12 times in one round of play. In this case, the interval time during the round is set to 0.84 seconds. In this small prize game, by continuing to shoot game balls toward the second game area 116b, it is possible to almost certainly cause a specified number of game balls (e.g. 10 balls) to enter the second large prize opening 128.

In addition, during the design stage of the gaming machine 100, it is necessary to strictly manage and adjust the firing prize ball ratio, which is the ratio between the number of game balls fired and the number of prize balls paid out. For this reason, in the simultaneous spin reference example, special pattern Z4 is provided, which opens twice for 0.1 seconds in a small win game, and special pattern Z5 is provided, which opens three times for 0.1 seconds in a small win game, and the firing prize ball ratio can be easily adjusted and changed simply by changing the selection ratio of these.

Figure 16 is a diagram illustrating a game state setting table for setting the game state after the end of the big prize game in the simultaneous spin reference example. In the simultaneous spin reference example, when the big prize game is executed, the game state setting table is referenced and the game state after the big prize game ends is set according to the game state at the time of winning the big prize, the reserved type, and the type of special pattern (big prize pattern).

If the game state at the time of winning the jackpot is the normal state or the penalty state, when the jackpot is won by the special 1 reservation, which is the actual variable target, the game state after the big prize game is set according to the type of the jackpot pattern. Specifically, if the special pattern A is determined as the jackpot pattern, it is set to a low probability time-saving state (the special game state is a low probability game state, and the normal game state is a time-saving game state). At this time, the number of times the time-saving game state continues (hereinafter referred to as the "time-saving number of times") is set to 100. This means that the time-saving game state continues until the big prize lottery is performed 100 times. However, the above-mentioned time-saving number of times indicates the maximum number of times that it continues in the time-saving game state of 1, and if a jackpot is won before the above-mentioned number of times of continuation is reached, the game state will be set again. Therefore, if the time-saving game state is set after the big win game ends, and a lottery result other than a jackpot is drawn 100 times without a jackpot result being drawn in the time-saving game state, the game state will change to a non-time-saving game state (normal state).

In addition, if special patterns B or D are determined as the jackpot pattern, the machine will be set to a high-probability time-saving state (the special game state is a high-probability game state, and the normal game state is a time-saving game state). At this time, "next" is set as the high-probability number of times, and the high-probability game state will continue until the next jackpot is won. In addition, "next" is set as the number of time-saving times, and the time-saving game state will continue until the next jackpot is won. Therefore, if special patterns B or D are determined, the high-probability time-saving state will continue after the big win game until the next jackpot is won.

In addition, if special patterns C or E are determined as the jackpot pattern, the game will be set to a high probability precursor state (the special game state is a high probability game state, and the normal game state is a time-saving game state). At this time, "next time" is set as the high probability number of times, and the time-saving number of times is set to 100. If special patterns C or E are determined, the high probability game state will continue until the next jackpot is won, while the time-saving game state will end after 100 times. Therefore, if special patterns C or E are determined, after the big prize game, the game state will transition to the most advantageous state when the results of the big prize lottery have been derived 100 times.

In addition, if the game state at the time of winning the jackpot is the normal state or the penalty state, if the jackpot is won by the special 2 reserve, which is not actually subject to change, the game state after the big win is set as follows. That is, if special pattern F is determined as the jackpot pattern, it is set to the normal state (special game state is a low probability game state, normal game state is a non-time-saving game state). In addition, if special patterns G to J are determined as the jackpot pattern, it is set to the penalty state (special game state is a high probability game state, normal game state is a medium time-saving game state). At this time, the number of high probability wins and the number of time-saving wins are both set to "next time".

In addition, if the game state at the time of winning the jackpot is the most advantageous state, when the jackpot is won by a special 1 reserve that is not actually subject to change, the game state after the big win is set as follows. That is, if special pattern A is determined as the jackpot pattern, it is set to a low probability time-saving state (the special game state is a low probability game state, and the normal game state is a time-saving game state). At this time, the number of time-saving times is set to 100. In addition, if special patterns B to E are determined as the jackpot pattern, the game state after the big win is set to the same as the normal state and penalty state.

On the other hand, if the game state at the time of winning the jackpot is the most advantageous state, when a jackpot is won by the special 2 reserve, which is essentially subject to change, the game state after the big win is set as follows. That is, if the special pattern F is determined as the jackpot pattern, it is set to a low-probability time-saving state (the special game state is a low-probability game state, and the normal game state is a time-saving game state). At this time, the number of time-saving times is set to 100. Also, if the special pattern G or I is determined as the jackpot pattern, it is set to a high-probability time-saving state (the special game state is a high-probability game state, and the normal game state is a time-saving game state). At this time, the high-probability number of times and the number of time-saving times are set to "next time".

In addition, if the special symbols H or J are determined as the jackpot symbols, the high probability premonition state is set (the special game state is a high probability game state, and the normal game state is a time-saving game state). At this time, the number of high probability times is set to "next time," and the number of time-saving times is set to 100.

In addition, if the game state at the time of winning the jackpot is a low probability time-saving state, a high probability time-saving state, or a high probability premonition state, in other words, if the normal game state is a time-saving game state, the game state after the big win is set to the same as the normal state or the penalty state.

Figure 17 is a diagram explaining a winning decision random number judgment table for the simultaneous spin reference example. When the game ball flowing down the game area 116 passes through the gate 124 or enters the normal symbol operating port 125, a normal symbol judgment process (hereinafter referred to as "normal symbol lottery") is performed, which corresponds to whether or not to control the flow of electricity to the movable piece 120b of the first variable start port 120B.

As will be described in detail later, when a game ball passes through gate 124 or enters normal map operation port 125, one winning determination random number is obtained from the range of 0 to 99, and this random number value is stored in the normal map reserve memory area of main RAM 300c, up to a maximum of four. In other words, the normal map reserve memory area has four memory sections for saving winning determination random numbers. Therefore, if a game ball passes through gate 124 or enters normal map operation port 125 with winning determination random numbers stored in all four memory sections of the normal map reserve memory area, no winning determination random number will be stored based on the passage of the game ball. In the following, the winning determination random number stored in the normal map reserve memory area when a game ball passes through gate 124 or enters normal map operation port 125 is referred to as a normal map reserve.

When the normal game state is a non-time-saving game state and a normal symbol lottery is started, the non-time-saving game state winning random number judgment table is referenced as shown in FIG. 17(a). According to this non-time-saving game state winning random number judgment table, if the winning random number is 0, a winning symbol is determined as the type of normal symbol, and if the winning random number is 1 to 99, a losing symbol is determined as the type of normal symbol. Therefore, the probability of a winning symbol being determined in a non-time-saving game state, that is, the probability of winning, is 1/100. As will be described in detail later, when a winning symbol is determined in this normal symbol lottery, the movable piece 120b of the first variable start opening 120B is controlled to the open state, and when a losing symbol is determined, the movable piece 120b of the first variable start opening 120B is maintained in the closed state.

When starting the normal symbol lottery in the intermediate time-saving play state, the winning symbol determination random number judgment table for the intermediate time-saving play state is referenced, as shown in FIG. 17(b). According to this winning symbol determination random number judgment table for the intermediate time-saving play state, if the winning symbol determination random number is between 0 and 49, a winning symbol is determined as the type of normal symbol, and if the winning symbol determination random number is between 50 and 99, a losing symbol is determined as the type of normal symbol. Therefore, the probability of a winning symbol being determined in the intermediate time-saving play state, i.e., the probability of winning, is 50/100.

In addition, when starting the regular symbol lottery in the time-saving play state, the time-saving play state win determination random number judgment table is referenced, as shown in FIG. 17(c). According to this time-saving play state win determination random number judgment table, if the win determination random number is 0-98, a winning symbol is determined as the type of regular symbol, and if the win determination random number is 99, a losing symbol is determined as the type of regular symbol. Therefore, the probability of a winning symbol being determined in the time-saving play state, i.e., the probability of winning, is 99/100.

18(a) is a diagram explaining the normal symbol variation time data table relating to the simultaneous spin reference example, and FIG. 18(b) is a diagram explaining the opening/closing control pattern table relating to the simultaneous spin reference example. As described above, when the normal symbol lottery is performed, the variation time of the normal symbol is determined. The normal symbol variation time data table is referenced when determining the variation time of the normal symbol when a winning symbol or a losing symbol is determined by the normal symbol lottery. According to this normal symbol variation time data table, when the game state is set to a non-time-saving game state or a medium time-saving game state, the variation time is determined to be 10 seconds, and when the game state is set to a time-saving game state, the variation time is determined to be 1 second. When the variation time is determined in this way, the normal symbol display 168 is displayed (blinking) for the determined time. Then, when a winning symbol is determined, the normal symbol display 168 is turned on, and when a losing symbol is determined, the normal symbol display 168 is turned off.

When the winning symbol is determined by the normal symbol lottery and the normal symbol display 168 is lit, the movable piece 120b of the first variable start port 120B is controlled to energize by referring to the opening/closing control pattern table, as shown in FIG. 18(b). Note that, in reality, an opening/closing control pattern table is provided for each game state, and the corresponding table is set when the normal electric role solenoid 120c starts energizing, depending on the game state when the normal symbol is determined.

Once the winning pattern is determined, the first variable starting port 120B is controlled to open and close by referring to the opening and closing control pattern table, as shown in Figure 18 (b). According to this opening/closing control pattern table, the time before normal power opening (waiting time until the first variable start port 120B starts opening), the maximum number of normal electric role opening/closing switching times (number of times the first variable start port 120B is opened), the solenoid energization time (the energization time of the normal electric role solenoid 120c for each number of times the first variable start port 120B is opened, i.e., the opening time of the first variable start port 120B once), the specified number (the maximum number of winnings that can be won into the first variable start port 120B during the full opening of the first variable start port 120B), the normal power closing effective time (the closing time between each opening of the first variable start port 120B, i.e., the pause time), the normal power effective state time (waiting time from the end of the last opening of the first variable start port 120B), and the normal power end wait time (waiting time until the variable display of the normal pattern described later is resumed after the normal power effective state time has elapsed) are stored in advance for each game state as shown in the figure as control data for the first variable start port 120B.

In this way, by setting the winning probability of the normal symbol, the variable time and the opening time, as shown in the lower part of Figure 18 (b), the fired prize ball ratio (the ratio of the number of prize balls that enter the first variable start port 120B, the second start port 122, the normal symbol operating port 125 and the large prize entry port and are paid out to the player relative to the number of game balls fired into the game area 116) is the number of fired balls:number of prize balls = 100:20 in the non-time-saving game state, the number of fired balls:number of prize balls = 100:40 in the intermediate time-saving game state, and the number of fired balls:number of prize balls = 100:99 in the time-saving game state.

The opening and closing conditions of the first variable start port 120B stipulate three elements: the probability of winning a normal symbol, the time for which the normal symbol is displayed in a variable manner, and the opening time of the first variable start port 120B. In other words, by combining the three elements of the probability of winning a normal symbol, the time for which the normal symbol is displayed in a variable manner, and the opening time of the first variable start port 120B, it is possible to set the frequency of game balls entering the first variable start port 120B and the ratio of prize balls fired in each of the non-time-saving game state, intermediate time-saving game state, and time-saving game state. In any case, the combination of the three elements shown here is merely one example, and it is sufficient to combine the three elements so that the ratio of prize balls fired is higher in the time-saving game state than in the non-time-saving game state.

Figure 19 is a diagram explaining the transition of game states according to the original gameplay of the simultaneous spin reference example. With the above configuration, the game machine 100 realizes the following gameplay. Note that here, the case where the registration setting value is set to "1" is explained. First, in the initial state of the game machine 100, it is set to the normal state shown in Figure 19 (a). In the normal state, the actual variable target is set to special 1 reservation, so the player launches the game ball toward the first game area 116a to make the game ball enter the first fixed start hole 120A. Since the first game area 116a is located on the left side of the game board 108, the player will perform what is called a "left shot" in the normal state.

When a game ball enters the first fixed starting hole 120A, the special 1 reserve is stored in the first special chart reserve memory area. The special 1 reserves stored in the first special chart reserve memory area are read out sequentially when the starting conditions are met, and a big prize lottery is held based on the read special 1 reserves. At this time, the probability of winning a big prize is set to approximately 1/300.6. Under normal conditions, the game is played with the aim of winning a big prize in the big prize lottery based on this special 1 reserve. Note that the prize ball ratio when a game ball is fired toward the first game area 116a is set to 100:20, and the game balls will decrease during play.

In the normal state, if a jackpot is won in the big prize lottery using the special 1 reservation, a big prize game is executed. In this big prize game, the first big prize opening 126 is opened and a round game is executed four or ten times, allowing the player to win four or ten rounds of prize balls. If a jackpot is won using the special 1 reservation, one of the special patterns A to E is determined as the jackpot pattern.

In the normal state, if the jackpot symbol stopped and displayed on the first special symbol display 160 is special symbol A, the game state after the big win will be the low-probability time-saving state shown in FIG. 19(b). When a jackpot is won with special 1 reserved, there is a 30% probability that special symbol A will be determined as the jackpot symbol. Therefore, when a jackpot is won in the normal state, there is a 30% probability that the game state will transition to the low-probability time-saving state. In the low-probability time-saving state, the actual variable target is set to special 1 reserved, but since the normal game state is the time-saving game state, the player will hit the ball to the right, aiming at the second game area 116b, in order to get the game ball to enter the first variable start hole 120B.

In other words, in this low-probability time-saving state, just like in the normal state, the player plays with the goal of winning the jackpot in the big prize lottery based on the special 1 reserve. In the low-probability time-saving state, the probability of winning the jackpot is approximately 1/300.6, but since the normal game state is a time-saving game state, the movable piece 120b frequently opens. Therefore, the ratio of fired prize balls is 100:99, and the player can aim for a jackpot while reducing the consumption of game balls.

When the game transitions to the low probability time-saving state, the number of time-saving times is set to 100, and if no jackpot is won in the 100 big prize draws, the game state will transition back to the normal state (time-saving time ...

In addition, in the normal state, if the jackpot pattern displayed on the first special pattern display 160 is the special pattern B or D, the game state after the big win will be the high probability time-saving state shown in FIG. 19(c). When a jackpot is won with the special 1 reserved, there is a 35% probability that the special pattern B or D will be determined as the jackpot pattern. Therefore, when a jackpot is won in the normal state, there is a 35% probability that the game state will transition to the high probability time-saving state. In the high probability time-saving state, the actual variable target is set to the special 1 reserved, but since the normal game state is the time-saving game state, the player will hit the ball to the right, aiming at the second game area 116b, in order to get the game ball into the first variable start hole 120B.

In other words, in this high-probability time-saving state, just like in the normal state, the player plays with the goal of winning the jackpot in the lottery for the big prize based on the special 1 reservation. In the high-probability time-saving state, the probability of winning the jackpot is approximately 1/105.7, and since the normal game state is a time-saving game state, the movable piece 120b frequently opens. Therefore, the ratio of fired prize balls is 100:99, and the player can play the lottery for the big prize while reducing the consumption of game balls. Therefore, in the high-probability time-saving state, it can be said that the next jackpot is essentially guaranteed to be won.

In addition, in the normal state, if the jackpot pattern displayed on the first special pattern display 160 is the special pattern C or E, the game state after the big win game will be the high probability premonition state shown in FIG. 19(d). When a jackpot is won with the special 1 reserved, there is a 35% probability that the special patterns C or E will be determined as the jackpot pattern. Therefore, when a jackpot is won in the normal state, there is a 35% probability that the game state will transition to the high probability premonition state. In the high probability premonition state, the actual variable target is set to the special 1 reserved, but since the normal game state is the time-saving game state, the player will hit the ball to the right, aiming at the second game area 116b, in order to get the game ball to enter the first variable start hole 120B.

When the special symbols C or E are selected, the game is set to a high probability premonition state and the time-saving count is set to 100. When the number of changes after the big win reaches 100, the time-saving game state ends and the normal game state becomes a non-time-saving game state. As a result, the game state transitions to the most advantageous state shown in FIG. 19(e) due to the time-saving end. As will be described in detail later, in the most advantageous state, the number of game balls can be increased simply by continuing to fire game balls toward the second game area 116b. Therefore, in the high probability premonition state, the objective of the game is not to win a jackpot, but to end the time-saving state without winning a jackpot.

According to the special 1 reserve that is the actual variable target in the high probability premonition state, high probability time-saving state, and low probability time-saving state described above, when a jackpot is won, special patterns A to E are determined as the jackpot pattern. When special pattern A is determined, four rounds of play are executed in the big prize game, and the game state after the big prize game becomes the low probability time-saving state shown in FIG. 19(b). Also, when special patterns B or D are determined, four or ten rounds of play are executed in the big prize game, and the game state after the big prize game becomes the high probability time-saving state. Also, when special patterns C or E are determined, four or ten rounds of play are executed in the big prize game, and the game state after the big prize game becomes the high probability premonition state.

In the most advantageous state, when a game ball enters the second starting hole 122, the special 2 reserve is stored in the second special chart reserve memory area. The special 2 reserves stored in the second special chart reserve memory area are read out sequentially when the starting conditions are met, and a lottery for a big prize is held based on the read special 2 reserves. At this time, the probability of winning a big prize is set to approximately 1/105.7, and the probability of winning a small prize is set to approximately 1/3.45. In the most advantageous state, the main objective of the game is to win a small prize in the lottery for a big prize based on this special 2 reserve.

Specifically, when a game ball is shot into the second game area 116b, the ratio of prize balls paid out by the game ball entering the second start hole 122 to the number of shot balls is set to about 100:60 to 80. In the most advantageous state, the probability of winning a small prize in the large role lottery by the special 2 reservation is about 1/3.45, so small prize games are frequently played. Here, when a small prize is won by the special 2 reservation, small prize patterns Z4 to Z6 are determined. As described above, in a small prize game when the small prize pattern Z4 is stopped and displayed on the second special pattern display 162, an average of 2 to 3 game balls enter the second large prize hole 128. In a small prize game when the small prize pattern Z5 is stopped and displayed on the second special pattern display 162, an average of 3 to 4 game balls enter the second large prize hole 128. Furthermore, in a small win game in which the small win symbol Z6 is stopped and displayed on the second special symbol display 162, approximately the specified number of game balls enter the second large winning hole 128.

When a game ball enters the second large prize opening 128, for example, 15 prize balls are paid out for each game ball that enters. As a result, in the most advantageous state, the fired prize ball ratio, which is the ratio of the number of all prize balls to the number of fired balls, is 100:120, and the number of game balls can be increased simply by continuing to fire game balls toward the second game area 116b.

In addition, in this most advantageous state, the normal game state is a non-time-saving game state, and the movable piece 120b is almost never in the open state. Also, in the most advantageous state, the special game state is a high probability game state, and since the probability of winning a jackpot in the most advantageous state is approximately 1 in 105.7, in the most advantageous state, it can be said that the next jackpot is essentially guaranteed to be won.

According to the special 2 reserve that is the actual variable target in this most advantageous state, when a jackpot is won, special symbols F to J are determined as the jackpot symbol. When special symbol F is determined, four rounds of play are executed in the big prize game, and the game state after the big prize game becomes a low-probability time-saving state as shown in FIG. 19(b). When special symbols G or I are determined, four or ten rounds of play are executed in the big prize game, and the game state after the big prize game becomes a high-probability time-saving state. When special symbols H or J are determined, four or ten rounds of play are executed in the big prize game, and the game state after the big prize game becomes a high-probability precursor state.

The most advantageous state is much more advantageous than other game states, so the main objective of playing on the gaming machine 100 is to transition the game state to the most advantageous state. As described above, the game first starts in the normal state, but there is no immediate transition from this normal state to the most advantageous state. Therefore, the transition route to the most advantageous state on the gaming machine 100 is the transition route that transitions to the most advantageous state via the high probability precursor state.

Furthermore, in the simultaneous spin reference example, aside from the time-saving feature escaping in the high probability premonition state, the condition for transitioning from the high probability premonition state to the most advantageous state is set to be the winning of a specific small win symbol. Specifically, when a small win is won by the special 1 reserve, which is the actual variable subject in the high probability premonition state, the small win symbol is determined to be special symbol Z1 with a probability of 1%, special symbol Z2 with a probability of 69%, and special symbol Z3 with a probability of 30% (see Figure 8 (c)).

At this time, if the special pattern Z1 is determined as the small win pattern, the time-saving game state ends with the end of the small win game, and as a result, the game state transitions to the most advantageous state.

In this way, the player transitions to the most advantageous state upon winning a specific small jackpot, which creates a constant sense of expectation and tension for the player, compared to a situation where the most advantageous state is only reached when the number of fluctuations reaches a specified number (100 times).

In addition, in the high probability premonition state, high probability time-saving state, and low probability time-saving state, there is a probability of about 1 in 3.45 of winning a small jackpot. Therefore, in the high probability premonition state, high probability time-saving state, and low probability time-saving state, small jackpot play is frequently executed, just like in the most advantageous state. However, in the high probability premonition state, high probability time-saving state, and low probability time-saving state, the normal play state is a time-saving play state. Also, as will be described in detail later, the normal play state is maintained in the time-saving play state even during a small jackpot play. Therefore, although the second large prize winning port 128 is opened during a small jackpot play, the first variable start port 120B is also opened during this time.

As described above, the first variable start port 120B is located above the second large winning port 128, and in the time-saving game state, the opening time of the first variable start port 120B is much longer than the opening time of the second large winning port 128. Therefore, in the high probability premonition state, high probability time-saving state, and low probability time-saving state, most of the game balls flowing down the second game area 116b enter the first variable start port 120B, and almost no game balls enter the second large winning port 128. As a result, in the high probability premonition state, high probability time-saving state, and low probability time-saving state, unlike the most advantageous state, the game balls will gradually decrease even if a right hit is made during play.

As described above, when the game progresses according to the actual variable object in accordance with the original gameplay, if a jackpot is won, the game state after the big win is set to either a low-probability time-saving state, a high-probability time-saving state, or a high-probability premonition state. The high-probability time-saving state and the high-probability premonition state have in common that the special game state is a high-probability game state, and the normal game state is a time-saving game state. On the other hand, the high-probability time-saving state continues until the next jackpot is won, whereas the high-probability premonition state differs in that the game state transitions to the most advantageous state when a specific small jackpot (special pattern Z1) is won or the time-saving state ends.

Also, in the high-probability time-saving state, the fluctuation time for small wins and misses is set to 1 second, whereas in the high-probability premonition state, the fluctuation time for small wins and misses is set within the range of 3 to 10 seconds (see Figure 13 (b)). In other words, the average fluctuation time in the high-probability time-saving state is set shorter than the average fluctuation time in the high-probability premonition state.

Therefore, in the high probability time-saving state, the time of change during small wins and misses is relatively short, so that the actual change target can be consumed at high speed until a big win is won. Although detailed explanation is omitted, during the change time of the special pattern, the change display of the performance patterns 210a, 210b, and 210c is performed on the sub-control board 330. In the high probability time-saving state, the change display of the performance patterns 210a, 210b, and 210c also becomes relatively short. Therefore, in the high probability time-saving state, as long as the special 1 reservation continues to be stored, the special 1 reservation (the change display of the performance patterns 210a, 210b, and 210c) continues to be consumed at high speed, so that the time until a big win can be shortened, and the player can play until the next big win without feeling (reducing) stress.

On the other hand, in the high probability premonition state, the fluctuation time during small wins and misses is relatively long, but the sub-control board 330 performs a presentation to see whether or not the most advantageous state will be entered. Therefore, the player can play while hoping that the most advantageous state will be entered.

In this way, in the high-probability time-saving state, even if a specific small jackpot (special pattern Z1) is won, there will be no transition to the most advantageous state, but by setting the average fluctuation time to a short value, the time until the next big jackpot is won can be shortened, reducing stress for the player. Also, in the high-probability precursor state, the average fluctuation time is set to be longer than in the high-probability time-saving state, but during that fluctuation time, it is possible to perform a presentation as to whether or not the most advantageous state will be entered, creating a sense of expectation and tension for the player.

As described above, a high-probability time-saving state and a high-probability precursor state are provided, which have in common that the special game state is a high-probability game state and the normal game state is a time-saving game state, and by making the average fluctuation time of the high-probability time-saving state shorter than the average fluctuation time of the high-probability precursor state, new gameplay can be provided.

Figure 20 is a diagram explaining the transition of the game state when the game is not played properly in the simultaneous spin reference example. As described above, in the gaming machine 100, the display of the changing patterns on the first special pattern display 160 and the display of the changing patterns on the second special pattern display 162 are performed simultaneously in parallel. At this time, if a large role lottery is performed based on a reservation other than the actual change target, and there is a possibility that the player may suffer a disadvantage as a result, the change time is set to a long time such as 10 minutes. However, after a large role lottery is performed based on a reservation other than the actual change target, for example, if the game is interrupted, a large win based on a reservation other than the actual change target may be confirmed. In this case, the game state will transition as shown in Figure 20.

The main processing of the main control board 300 to achieve the above gameplay characteristics is explained below.

Figure 21 is a diagram explaining the gaming machine status flag for the simultaneous spin reference example. In the main control board 300, the gaming machine status flag manages whether or not the game can proceed. The gaming machine status flag is set to one of six flag values from 00H to 05H. A flag value of 00H for the gaming machine status flag indicates a playable state. When the gaming machine status flag is 00H, the game is controlled to proceed, and when the gaming machine status flag is other than 00H, the game is stopped.

The flag value of the gaming machine status flag = 01H indicates a setting change state, and when the gaming machine status flag is 01H, the registered setting value can be changed. The flag value of the gaming machine status flag = 02H indicates a setting confirmation state, and when the gaming machine status flag is 02H, the registered setting value can be confirmed by displaying it on the performance display monitor 184, for example. The flag value of the gaming machine status flag = 03H indicates a setting abnormal state, and when the gaming machine status flag is 03H, the registered setting value is considered abnormal and play is stopped. The flag value of the gaming machine status flag = 04H indicates a RAM abnormal state, and when the gaming machine status flag is 04H, play is stopped. The flag value of the gaming machine status flag = 05H indicates a checksum abnormal state, and when the gaming machine status flag is 05H, play is stopped. When the power is turned on, the gaming machine status flag is set to one of the flag values, and processing according to the gaming machine status flag is performed.

(CPU Initialization Processing of Main Control Board 300)
FIG. 22 is a first flowchart explaining the CPU initialization processing in the main control board 300 relating to the simultaneous rotation reference example, and FIG. 23 is a second flowchart explaining the CPU initialization processing in the main control board 300 relating to the simultaneous rotation reference example.

When power is supplied from the power supply board, a system reset occurs in the main CPU 300a, and the main CPU 300a performs the following CPU initialization process (S100).

(Step S100-1)
When the power is turned on, the main CPU 300a reads a startup program from the main ROM 300b as an initial setting process, and also performs setting processes required for executing various processes.

(Step S100-3)
The main CPU 300a sets a wait processing time in a timer counter.

(Step S100-5)
The main CPU 300a judges whether a power-off warning signal has been detected. The main control board 300 is provided with a power-off detection circuit, which outputs a power-off warning signal when the power supply voltage falls below a predetermined value. If a power-off warning signal has been detected, the process proceeds to step S100-3, and if a power-off warning signal has not been detected, the process proceeds to step S100-7.

(Step S100-7)
The main CPU 300a judges whether the wait time set in step S100-3 has elapsed or not. If it is judged that the wait time has elapsed, the process proceeds to step S100-9, and if it is judged that the wait time has not elapsed, the process proceeds to step S100-5.

(Step S100-9)
The main CPU 300a executes the processes required to permit access to the main RAM 300c.

(Step S100-11)
The main CPU 300a loads the flag value of the gaming machine status flag before the power is turned off into the D register.

(Step S100-13)
The main CPU 300a calculates the checksum and determines whether the calculated checksum matches the checksum saved when the power was turned off (is normal) and whether the backup flag is normal. If it is determined that the backup flag and the checksum are normal, the process proceeds to step S100-15, and if it is determined that either one or both are not normal, the process proceeds to step S100-25.

(Step S100-15)
The main CPU 300a sets an address that does not include a setting value or a gaming machine status flag as the first address to be cleared in the main RAM 300c.

(Step S100-17)
The main CPU 300a judges whether a RAM clear operation signal has been input from the RAM clear switch 182s (whether the RAM clear button has been pressed down). If it is judged that a RAM clear operation signal has been input, the process proceeds to step S100-31, and if it is judged that a RAM clear operation signal has not been input, the process proceeds to step S100-19.

(Step S100-19)
The main CPU 300a judges whether the flag value of the gaming machine status flag loaded in step S100-11 is 00H (playable state), the setting change switch 180s is on, and the middle frame 104 is open. If it is judged that all three conditions are met, the process proceeds to step S100-21, and if it is judged that any one of the three conditions is not met, the process proceeds to step S100-23.

(Step S100-21)
The main CPU 300a sets the gaming machine status flag to 02H (setting confirmation status). That is, when the power is normally turned on in a state where the middle frame 104 is open, the setting change switch 180s is on, and the RAM clear button is not pressed, the gaming machine enters the setting confirmation status.

(Step S100-23)
The main CPU 300a executes an initialization process to clear the areas of the main RAM 300c subsequent to the top address set in step S100-15 that are to be cleared when the power is restored, and then proceeds to step S100-49.

(Step S100-25)
The main CPU 300a sets 05H (checksum abnormal state) in the D register.

(Step S100-27)
The main CPU 300a performs an outside area read/write check process for checking and clearing the read/write memory in the unused area.

(Step S100-29)
The main CPU 300a sets an address including a setting value and a gaming machine status flag as the first address to be cleared in the main RAM 300c.

(Step S100-31)
The main CPU 300a checks and clears the read/write memory of the used area.

(Step S100-33)
The main CPU 300a judges whether the check result of the read/write memory in the above step S100-31 is normal or not. If it is judged as normal, the process proceeds to step S100-37, and if it is judged as not normal, the process proceeds to step S100-35.

(Step S100-35)
The main CPU 300a sets 04H (RAM abnormal state) in the D register, and moves the process to step S100-45.

(Step S100-37)
The main CPU 300a judges whether 02H (setting confirmation state) is set in the D register. If it is judged that 02H is set, the process proceeds to step S100-39, and if it is judged that 02H is not set, the process proceeds to step S100-41.

(Step S100-39)
The main CPU 300a sets the D register to 00H (playable state).

(Step S100-41)
The main CPU 300a judges whether the setting change conditions are satisfied. If it is judged that the setting change conditions are satisfied, the process proceeds to step S100-43, and if it is judged that the setting change conditions are not satisfied, the process proceeds to step S100-45. Note that the setting change conditions here include at least that the setting change switch 180s is turned on, that the middle frame 104 is open, and that a RAM clear operation signal is input from the RAM clear switch 182s.

(Step S100-43)
The main CPU 300a sets the D register to 01H (setting changed state).

(Step S100-45)
The main CPU 300a saves the value set in the D register in the gaming machine status flag.

(Step S100-47)
The main CPU 300a executes an initialization process for clearing the items in the main RAM 300c that are to be cleared when the RAM is cleared, and moves the process to step S100-49.

(Step S100-49)
The main CPU 300a performs a transmission process (storing the RAM clear designation command in a transmission buffer) of a payout command (RAM clear designation command) to inform the payout control board 310 that the main RAM 300c has been cleared.

(Step S100-51)
The main CPU 300a loads the gaming machine status flag.

(Step S100-53)
The main CPU 300a judges whether the gaming machine status flag loaded in step S100-51 is 00H (playable state). If it is judged to be 00H, the process proceeds to step S110, and if it is judged not to be 00H, the process proceeds to step S100-55.

(Step S110)
The main CPU 300a performs a sub-command group set process, which will be described later.

(Step S100-55)
The main CPU 300 a performs a sub-command group setting process for transmitting a predetermined command to the sub-control board 330 .

(Step S100-57)
The main CPU 300a sets the timer interrupt period.

(Step S100-59)
The main CPU 300a performs processing to disable interrupts.

(Step S100-61)
The main CPU 300a updates the initial value update random number for the winning symbol random number. The initial value update random number for the winning symbol random number is for determining the initial value and the end value of the winning symbol random number. In other words, when the winning symbol random number goes through one cycle from the initial value update random number for the winning symbol random number to the initial value update random number for the winning symbol random number - 1 by the updating process of the winning symbol random number described later, the winning symbol random number is updated to the initial value update random number for the winning symbol random number at that time.

(Step S100-63)
The main CPU 300a analyzes the received data (main commands) received from the payout control board 310 and executes various processes according to the received data.

(Step S100-65)
The main CPU 300 a performs processing to transmit the sub-commands stored in the transmission buffer to the sub-control board 330 .

(Step S100-67)
The main CPU 300a performs processing to permit an interrupt.

(Step S100-69)
The main CPU 300a updates the reach group determination random number, the reach mode determination random number, and the change pattern random number, and thereafter repeats the process from step S100-59. Note that, hereinafter, the reach group determination random number, the reach mode determination random number, and the change pattern random number for determining the change presentation pattern are collectively referred to as the change presentation random number.

Figure 24 is a flowchart explaining the sub-command group set process (S110) in the main control board 300 in the simultaneous rotation reference example.

(Step S110-1)
The main CPU 300a loads the flag value of the gaming machine status flag.

(Step S110-3)
The main CPU 300 a performs a sub-command group setting process for transmitting a predetermined command to the sub-control board 330 .

(Step S110-5)
The main CPU 300a performs a model command setting process to set a model command indicating model information of the gaming machine 100 in a transmission buffer.

(Step S110-7)
The main CPU 300a performs a setting value designation command setting process for setting a setting value designation command indicating a registered setting value in a transmission buffer.

(Step S110-9)
The main CPU 300a performs a special chart 1 reservation designation command setting process that sets a special chart 1 reservation designation command indicating the special chart 1 reservation number in a transmission buffer.

(Step S110-11)
The main CPU 300a performs a special chart 2 reservation designation command setting process that sets a special chart 2 reservation designation command indicating the special chart 2 reservation number in a transmission buffer.

(Step S110-13)
The main CPU 300a performs a count command setting process for setting a count command indicating the remaining number of times in the time-shortened gaming state in a transmission buffer.

(Step S110-15)
The main CPU 300a performs a variation pattern selection state designation command setting process that sets a variation pattern selection state designation command indicating the variation pattern selection state in a transmission buffer.

(Step S110-17)
The main CPU 300a performs a special game phase designation command setting process for setting a special game phase designation command indicating a special game management phase in a transmission buffer. The special game management phase will be described later.

(Step S110-19)
The main CPU 300a judges whether the special game management phase is in a special symbol change waiting state. If it is judged that the special symbol change waiting state is in effect, the process proceeds to step S110-21, and if it is judged that the special symbol change waiting state is not in effect, the sub-command group set process is terminated.

(Step S110-21)
The main CPU 300a sets the customer waiting designation command in the transmission buffer, and ends the sub-command group setting process.

Next, we will explain the interrupt processing in the main control board 300. Here, we will explain the power-off evacuation processing (XINT interrupt processing) and timer interrupt processing.

(Power off save process of main control board 300 (XINT interrupt process))
25 is a flow chart for explaining the power-off save process (XINT interrupt process) in the main control board 300 according to the simultaneous rotation reference example. The main CPU 300a monitors the power-off detection circuit, and when the power supply voltage falls below a predetermined value, it interrupts the CPU initialization process and executes the power-off save process.

(Step S300-1)
When the power-off warning signal is input, the main CPU 300a saves the registers.

(Step S300-3)
The main CPU 300a checks the power-off warning signal.

(Step S300-5)
The main CPU 300a judges whether a power-off warning signal has been detected. If it is judged that a power-off warning signal has been detected, the process proceeds to step S300-11. If it is judged that a power-off warning signal has not been detected, the process proceeds to step S300-7.

(Step S300-7)
The main CPU 300a restores the register.

(Step S300-9)
The main CPU 300a performs processing to permit an interrupt, and ends the power-off save processing.

(Step S300-11)
The main CPU 300a executes an output port clear process to stop the output of the output port.

(Step S300-13)
The main CPU 300a executes a checksum setting process that calculates and stores a checksum.

(Step S300-15)
The main CPU 300a executes a RAM protect setting process required to prohibit access to the main RAM 300c.

(Step S300-17)
In order to set the power interruption occurrence monitoring time, the main CPU 300a sets the counter value of a loop counter to a predetermined number of times the power interruption detection signal has been detected.

(Step S300-19)
The main CPU 300a checks the power-off warning signal.

(Step S300-21)
The main CPU 300a judges whether a power-off warning signal has been detected. If it is judged that a power-off warning signal has been detected, the process proceeds to step S300-17. If it is judged that a power-off warning signal has not been detected, the process proceeds to step S300-23.

(Step S300-23)
The main CPU 300a subtracts 1 from the value of the loop counter set in step S300-17.

(Step S300-25)
The main CPU 300a judges whether the counter value of the loop counter is 0. If it is judged that the counter value is not 0, the process proceeds to step S300-19, and if it is judged that the counter value is 0, the process proceeds to the above-mentioned CPU initialization process (step S100).

If a power outage actually occurs, operation of the gaming machine 100 will stop while steps S300-17 to S300-25 are looping.

(Timer interrupt processing of main control board 300)
26 is a flow chart for explaining the timer interrupt process in the main control board 300 according to the simultaneous rotation reference example. The main control board 300 is provided with a reset clock pulse generating circuit that generates a clock pulse every predetermined period (4 milliseconds in the simultaneous rotation reference example, hereinafter referred to as "4 ms"). When a clock pulse is generated by the reset clock pulse generating circuit, the CPU initialization process (step S100) is interrupted and the following timer interrupt process is executed.

(Step S400-1)
The main CPU 300a saves the registers.

(Step S400-3)
The main CPU 300a performs processing to permit an interrupt.

(Step S400-5)
The main CPU 300a outputs the common data set in the common output buffer to the output port, and executes dynamic port output processing which controls the lighting of the first special pattern display 160, the second special pattern display 162, the first special pattern reserved indicator 164, the second special pattern reserved indicator 166, the normal pattern display 168, the normal pattern reserved indicator 170, the right hit notification indicator 172, and the performance display monitor 184.

(Step S400-7)
The main CPU 300a reads various types of input port information and executes a port input process to accurately obtain the latest switch states.

(Step S400-9)
The main CPU 300a loads the flag value of the gaming machine status flag.

(Step S400-11)
The main CPU 300a judges whether the flag value loaded in step S400-9 is 00H (playable state). If it is judged to be 00H, the process proceeds to step S400-15, and if it is judged not to be 00H, the process proceeds to step S400-13.

(Step S400-13)
The main CPU 300a judges whether the flag value loaded in step S400-9 is equal to or greater than 03H (abnormal setting). If it is judged to be equal to or greater than 03H, the process proceeds to step S400-29. If it is judged to be equal to or greater than 03H, the process proceeds to step S450.

(Step S450)
The main CPU 300a executes a setting-related process, and moves the process to step S400-29. The setting-related process will be described later.

(Step S400-15)
The main CPU 300a performs a timer update process to update various timer counters. Here, unless otherwise specified, the timer counters are decremented every time the timer interrupt process of the main control board 300 is performed, and the decrement stops when the timer counters reach 0.

(Step S400-17)
The main CPU 300a executes an update process for the initial value update random number for the winning symbol random number, similar to step S100-61 described above.

(Step S400-19)
The main CPU 300a performs a process of updating the winning symbol random number. Specifically, the random number counter is updated by adding 1, and if the result of the addition exceeds the maximum value of the random number range, the random number counter is reset to 0, and if the random number counter has completed one cycle, the random number is updated from the value of the initial value update random number for the winning symbol random number at that time.

Although a detailed explanation will be omitted, in the simultaneous spin reference example, the jackpot determination random number and the win determination random number use hardware random numbers updated by a hardware random number generation unit built into the main control board 300. The hardware random number generation unit updates both the jackpot determination random number and the win determination random number according to certain rules, automatically changing the random number sequence each time the random number sequence goes through one cycle, and changing the start value each time the system is reset.

(Step S500)
The main CPU 300a executes a switch management process to determine whether or not a signal has been input from the first fixed start hole detection switch 120As, the first variable start hole detection switch 120Bs, the second start hole detection switch 122s, the gate detection switch 124s, the normal operation hole detection switch 125s, the first large prize hole detection switch 126s, and the second large prize hole detection switch 128s. Details of this switch management process will be described later.

(Step S600)
The main CPU 300a executes a special game management process for controlling the progress of the variable display of the special symbols based on the special 2 reservation in the special game. The details of this special game management process will be described later.

(Step S600)
The main CPU 300a executes a special game management process for controlling the progress of the variable display of the special symbol based on the special 1 reservation in the special game. Here, the same program (module) as the special game management process for controlling the progress of the variable display of the special symbol based on the special 2 reservation is read out, and the special game management process for controlling the progress of the variable display of the special symbol based on the special 1 reservation is executed.

(Step S700)
The main CPU 300a executes a special electric accessory game management process for controlling the progress of the big prize game and the small prize game in the special game. The details of this special electric accessory game management process will be described later.

(Step S800)
The main CPU 300a executes a normal game management process for controlling the progress of the normal game. The details of this normal game management process will be described later.

(Step S400-21)
The main CPU 300a executes an error management process for determining various errors and making settings according to the error determination results.

(Step S400-23)
The main CPU 300a checks the general prize hole detection switch 118s, the first start hole detection switch 120s, the second start hole detection switch 122s, the first large prize hole detection switch 126s, and the second large prize hole detection switch 128s, and executes prize hole switch processing to increment the corresponding counters for prize ball control, etc.

(Step S400-25)
The main CPU 300a executes a payout control management process to create and transmit a payout command based on the counter value of the counter for controlling the winning balls set in the above step S400-23.

(Step S400-27)
The main CPU 300a executes a launch position designation management process for transmitting a launch position designation command to the sub-control board 330, which designates the launch position of the game ball, i.e., whether the game ball is to be launched into the first game area 116a or the second game area 116b.

(Step S400-29)
The main CPU 300a executes an external information management process for setting output data for external information to be output from the game information output terminal board 312 to the outside.

(Step S400-31)
The main CPU 300a executes an LED display setting process which sets display data for controlling the lighting of various indicators (LEDs), such as the first special pattern display 160, the second special pattern display 162, the first special pattern reserved indicator 164, the second special pattern reserved indicator 166, the normal pattern display 168, the normal pattern reserved indicator 170, and the right hit notification indicator 172, in an output buffer corresponding to each common.

(Step S400-33)
The main CPU 300a executes a solenoid output image synthesis process to synthesize the solenoid output images of the normal electric role solenoid 120c, the first large prize opening solenoid 126c, and the second large prize opening solenoid 128c, and store them in an output port buffer.

(Step S400-35)
The main CPU 300a executes a port output process for outputting the values of the common output buffers stored in the respective output port buffers to the output ports.

(Step S400-37)
The main CPU 300a performs processing to disable interrupts.

(Step S400-39)
The main CPU 300a uses the unused area of the main RAM 300c to perform processing for calculating a base ratio to be displayed on the performance display monitor 184, and executes a performance display monitor control processing for setting common data for displaying the calculated base ratio on the performance display monitor 184 in a common output buffer. In the performance display monitor control processing, the base ratio is calculated for each predetermined period. Here, the performance display monitor 184 may switch between displaying the base ratio for the current period and the base ratio for the previous period at predetermined time intervals. Also, the base ratio displayed on the performance display monitor 184 may be switched in response to a predetermined operation.

(Step S400-41)
The main CPU 300a restores the registers and ends the timer interrupt process.

Figure 27 is a flowchart explaining the setting-related process (S450) for the simultaneous rotation reference example.

(Step S450-1)
The main CPU 300a judges whether the flag value of the gaming machine state flag is 01H (setting change state). If it is judged to be 01H, the process proceeds to step S450-3, and if it is judged not to be 01H, the process proceeds to step S450-15.

(Step S450-3)
The main CPU 300a loads the registered setting values stored in the setting value buffer into a predetermined processing area.

(Step S450-5)
The main CPU 300a judges whether the RAM clear switch 182s has been pressed (whether a RAM clear operation signal has been input). If it is judged that the RAM clear switch 182s has been pressed, the process proceeds to step S450-7, and if it is judged that the RAM clear switch 182s has not been pressed, the process proceeds to step S450-9.

(Step S450-7)
The main CPU 300a adds 1 to the setting value of the processing area.

(Step S450-9)
The main CPU 300a judges whether the setting value of the processing area is in the range of 1 to 6. As a result, if it is judged that the setting value is in the range of 1 to 6, the process proceeds to step S450-13, and if it is judged that the setting value is not in the range of 1 to 6, the process proceeds to step S450-11.

(Step S450-11)
The main CPU 300a sets the setting value of the processing area to 1.

(Step S450-13)
The main CPU 300a sets the setting value of the processing area in the setting value buffer.

(Step S450-15)
The main CPU 300a judges whether the setting change switch 180s is on. If it is judged that the setting change switch 180s is on, the setting-related process is terminated, and if it is judged that the setting change switch 180s is not on, the process proceeds to step S450-17.

(Step S450-17)
The main CPU 300a sets a setting-related end designation command, which indicates the end of the setting-related processing, in the transmission buffer.

(Step S110)
The main CPU 300a executes the sub-command group set process of Fig. 24. That is, when the setting related process is executed, at the end of the process, the model command, the setting value designation command, the special chart 1 reservation designation command, the special chart 2 reservation designation command, the number of times command, the variation pattern selection state designation command, the special chart phase designation command, and the customer waiting designation command are transmitted to the sub-control board 330.

(Step S450-19)
The main CPU 300a sets the gaming machine state flag to 00H (playable state), and ends the setting-related processing.

As described above, according to the simultaneous rotation reference example, when the power is turned on normally with the middle frame 104 open, the setting change switch 180s on, and the RAM clear button pressed, the gaming machine status flag is set to 01H (setting change state) in the CPU initialization process (Figure 22). After that, the timer interrupt process is executed, but because the gaming machine status flag is set to 01H (setting change state), all processes related to the progress of the game (steps S400-15 to S400-27 in Figure 26) are stopped, and setting-related processes are executed.

The setting-related process is executed repeatedly while the setting change switch 180s is on, and during this setting-related process, pressing the RAM clear button is accepted as a setting change operation for the registered setting value. In other words, during the setting change process (S450-1 to S450-13) that accepts setting change operations, the registered setting value stored in the setting value buffer is switched to one of multiple setting values in response to the setting change operation.

When the setting change switch 180s is switched off while the gaming machine status flag is set to 01H (setting change state), the setting change process ends and the gaming machine status flag is set to 00H (playable state). This makes it possible to execute processes related to the progress of the game, starting with the next timer interrupt process.

Here, in the setting-related processing of the simultaneous rotation reference example, after the RAM clear button is pressed, i.e., after the acceptance of the setting change operation of the registered setting value has ended, a setting value designation command corresponding to the registered setting value is sent to the sub-control board 330 in the sub-command group set processing. On the other hand, while the setting change operation is being accepted, the setting value designation command is not sent to the sub-control board 330. In this way, while the setting change operation is being accepted, the setting value designation command is not sent, and when the acceptance of the setting change operation has ended and the game transitions to a state in which it is possible to proceed, the setting value designation command is sent, thereby reducing the risk of the registered setting value being obtained illegally.

In addition, in the simultaneous rotation reference example, multiple flag values including at least 01H (setting change state) are switched. Then, when the gaming machine state flag is set to 01H (setting change state), setting-related processing can be executed, and the progress of the game is stopped. In this way, since setting-related processing is not executed while the game is in progress, setting value designation commands are not sent while the game is in progress, and the risk of registered setting values being obtained illegally is reduced.

Next, among the timer interrupt processes described above, the switch management process in step S500, the special game management process in step S600, the special electric role game game management process in step S700, and the regular game management process in step S800 will be described in detail.

Figure 28 is a flowchart explaining the switch management process (step S500) in the main control board 300 in the simultaneous rotation reference example.

(Step S500-1)
The main CPU 300a judges whether the gate detection switch is ON, that is, whether the game ball has passed through the gate 124 and the detection signal from the gate detection switch 124s has been turned ON. If it is judged that the gate detection switch is ON, the process proceeds to step S510, and if it is judged that the gate detection switch is not ON, the process proceeds to step S500-7.

(Step S510)
The main CPU 300a executes a gate passing process based on the passage of the gaming ball through the gate 124. The gate passing process will be described in detail later.

(Step S500-3)
The main CPU 300a judges whether the normal operation port detection switch is ON, that is, whether a game ball has entered the normal operation port 125 and the detection signal from the normal operation port detection switch 125s has been turned ON. If it is judged that the normal operation port detection switch is ON, the process proceeds to step S510, and if it is judged that the normal operation port detection switch is not ON, the process proceeds to step S500-5.

(Step S510)
The main CPU 300a executes gate passing processing based on the entry of a game ball into the normal operation port 125.

(Step S500-5)
The main CPU 300a judges whether the first fixed start hole detection switch is ON, that is, whether a game ball has entered the first fixed start hole 120A and a detection signal has been input from the first fixed start hole detection switch 120As. If it is judged that the first fixed start hole detection switch is ON, the process proceeds to step S520, and if it is judged that the first fixed start hole detection switch is not ON, the process proceeds to step S500-7.

(Step S520)
The main CPU 300a executes a first start hole passing process based on the entry of the game ball into the first fixed start hole 120A. The first start hole passing process will be described in detail later.

(Step S500-7)
The main CPU 300a judges whether the first variable start hole detection switch is ON, that is, whether a game ball has entered the first variable start hole 120B and a detection signal has been input from the first variable start hole detection switch 120Bs. If it is determined that the first variable start hole detection switch is ON, the process proceeds to step S520, and if it is determined that the first variable start hole detection switch is not ON, the process proceeds to step S500-11.

(Step S520)
The main CPU 300a executes a first start hole passing process based on the entry of the gaming ball into the first variable start hole 120B. The first start hole passing process will be described in detail later.

(Step S500-9)
The main CPU 300a determines whether the game ball has entered the first variable start opening 120B properly, and if it determines that the game ball has not entered properly, executes a normal electric device winning confirmation process to send a normal electric illegal winning error occurrence designation command to the sub-control board 330, indicating that the game ball has entered the first variable start opening 120B illegally.

(Step S500-11)
The main CPU 300a judges whether the second start hole detection switch is ON, that is, whether a game ball has entered the second start hole 122 and a detection signal has been input from the second start hole detection switch 122s. If it is determined that the second start hole detection switch is ON, the process proceeds to step S530, and if it is determined that the second start hole detection switch is not ON, the process proceeds to step S500-13.

(Step S530)
The main CPU 300a executes a second start hole passing process based on the entry of the gaming ball into the second start hole 122. The second start hole passing process will be described in detail later.

(Step S500-13)
The main CPU 300a judges whether the time has come when the large prize opening detection switch is detected as being on, that is, whether a game ball has entered the first large prize opening 126 or the second large prize opening 128 and a detection signal has been input from the first large prize opening detection switch 126s or the second large prize opening detection switch 128s. If it is determined that the time has come when the large prize opening detection switch is detected as being on, the process proceeds to step S540, and if it is determined that the time has not come when the large prize opening detection switch is detected as being on, the switch management process is terminated.

(Step S540)
The main CPU 300a judges whether the game ball has entered the first large prize opening 126 or the second large prize opening 128 properly, and if it judges that the game ball has entered properly, it executes a large prize opening passing process for transmitting a large prize opening entry command, which indicates that the game ball has entered the first large prize opening 126 or the second large prize opening 128, to the sub-control board 330. The details of this large prize opening passing process will be described later.

Figure 29 is a flowchart explaining the gate passage process (step S510) in the main control board 300 in the simultaneous rotation reference example.

(Step S510-1)
The main CPU 300a loads the winning determination random number updated by the hardware random number generator.

(Step S510-3)
The main CPU 300a judges whether the counter value of the normal pattern reserved ball counter is equal to or greater than the maximum value, that is, whether the counter value of the normal pattern reserved ball counter is equal to or greater than 4. If it is judged that the counter value of the normal pattern reserved ball counter is equal to or greater than the maximum value, the gate passing process is terminated, and if it is judged that the normal pattern reserved ball counter is not equal to or greater than the maximum value, the process proceeds to step S510-5.

(Step S510-5)
The main CPU 300a updates the counter value of the normal symbol reserved ball count counter to a value obtained by adding "1" to the current counter value.

(Step S510-7)
The main CPU 300a determines which of the four memory sections in the general reserve memory area is to be the target memory section in which to save the acquired winning determination random number.

(Step S510-9)
The main CPU 300a saves the winning determination random number obtained in the above step S510-1 in the target memory calculated in the above step S510-7.

(Step S510-11)
The main CPU 300a sets a regular map reservation designation command indicating the number of regular map reservations stored in the regular map reservation memory area in the transmission buffer, and terminates the gate passing process.

Figure 30 is a flow chart explaining the first starting port passing process (step S520) in the main control board 300 in the simultaneous rotation reference example.

(Step S520-1)
The main CPU 300a sets "00H" as the special symbol identification value. The special symbol identification value is used to identify whether the reserved type is special 1 reserved or special 2 reserved, and the special symbol identification value (00H) indicates special 1 reserved, and the special symbol identification value (01H) indicates special 2 reserved.

(Step S520-3)
The main CPU 300a sets the address of the reserved ball count counter for special pattern 1.

(Step S535)
The main CPU 300a executes the special symbol random number acquisition process and ends the first start hole passing process. This special symbol random number acquisition process is executed using a module common to the second start hole passing process (step S530). Therefore, the details of the special symbol random number acquisition process will be explained after the explanation of the second start hole passing process.

Figure 31 is a flow chart explaining the second starting port passing process (step S530) in the main control board 300 in the simultaneous rotation reference example.

(Step S530-1)
The main CPU 300a sets "01H" as the special symbol identification value.

(Step S530-3)
The main CPU 300a sets the address of the special pattern 2 reserved ball count counter.

(Step S535)
The main CPU 300a executes the special pattern random number acquisition process described later, and ends the second starting port passing process.

Figure 32 is a flow chart explaining the special symbol random number acquisition process (step S535) in the main control board 300 relating to the simultaneous rotation reference example. This special symbol random number acquisition process is executed using a common module in the first start hole passing process (step S520) and the second start hole passing process (step S530) described above.

(Step S535-1)
The main CPU 300a loads the special symbol identification value set in step S520-1 or step S530-1.

(Step S535-3)
The main CPU 300a loads the number of reserved balls for the target special symbol. Here, if the special symbol identification value loaded in the above step S535-1 is "00H", the counter value of the reserved ball counter for the special symbol 1, i.e., the reserved number for special 1, is loaded. Also, if the special symbol identification value loaded in the above step S535-1 is "01H", the counter value of the reserved ball counter for the special symbol 2, i.e., the reserved number for special 2, is loaded.

(Step S535-5)
The main CPU 300a loads the jackpot determination random number updated by the hardware random number generating unit.

(Step S535-7)
The main CPU 300a judges whether the number of reserved balls for the target special symbol loaded in step S535-3 is equal to or greater than the upper limit. If it is judged to be equal to or greater than the upper limit, the main CPU 300a ends the special symbol random number acquisition process. If it is judged to be equal to or greater than the upper limit, the process proceeds to step S535-9.

(Step S535-9)
The main CPU 300a updates the counter value of the target special pattern reserved ball count counter to a value obtained by adding "1" to the current counter value.

(Step S535-11)
The main CPU 300a calculates the target memory section among the memory sections of the special chart reserved memory area into which the acquired jackpot determination random number is to be saved.

(Step S535-13)
The main CPU 300a obtains the jackpot determination random number loaded in step S535-5, the winning symbol random number updated in step S400-19, and the variation pattern random number updated in step S100-69, and stores them in the target memory section calculated in step S535-11.

(Step S535-15)
The main CPU 300a loads the counter values of the special pattern 1 reserved ball count counter and the special pattern 2 reserved ball count counter.

(Step S535-17)
The main CPU 300a sets the special reserved command in the transmission buffer based on the counter value loaded in step S535-15. Here, the special reserved command is set based on the counter value (special reserved number of special 1) of the special reserved ball number counter, and the special reserved command is set based on the counter value (special reserved number of special 2) of the special reserved ball number counter. As a result, the special reserved number of special 1 and the special reserved number of special 2 are transmitted to the sub-control board 330 every time the special reserved number of special 1 or special reserved number of special 2 is stored.

(Step S536)
The main CPU 300a performs the acquisition time performance determination process and ends the special symbol random number acquisition process. In this acquisition time performance determination process, the result of the big role lottery and the variable pattern number are provisionally determined, and a pre-reading designation command according to the provisional determination result is transmitted to the sub-control board 330. This acquisition time performance determination process will be described with reference to FIG.

Figure 33 is a flowchart explaining the performance determination process (step S536) at the time of acquisition in the main control board 300 in the simultaneous rotation reference example.

(Step S536-1)
The main CPU 300a selects a corresponding jackpot determination random number judgment table based on the currently set value. Specifically, the main CPU 300a selects a corresponding jackpot determination random number judgment table based on the current game state and the currently set value. Then, the main CPU 300a performs a provisional special symbol win judgment process to provisionally judge whether the winning combination is a jackpot, a small win, or a miss, based on the selected table and the jackpot determination random number stored in the target memory unit in step S535-13.

(Step S536-3)
The main CPU 300a executes a special symbol provisional determination process for provisionally determining a special symbol. Here, if the result of the provisional big role lottery in the above step S536-1 (the result derived by the special symbol provisional win determination process) is a big win or a small win, the winning symbol random number, the winning type (whether it is a big win or a small win), and the reserved type stored in the target memory in the above step S535-13 are loaded, the corresponding winning symbol random number determination table is selected to extract the special symbol determination data, and the extracted special symbol determination data (type of big win symbol or small win symbol) is saved. Also, if the result of the provisional big role lottery in the above step S536-1 is a loss, a predetermined special symbol determination data for a loss (type of loss symbol) is saved.

(Step S536-5)
The main CPU 300a sets in the transmission buffer a look-ahead symbol type designation command (look-ahead designation command) corresponding to the special symbol determination data saved in step S536-3.

(Step S536-7)
The main CPU 300a judges whether the result derived by the special symbol winning provisional judgment process in the above step S536-1 is a big win or a small win. If it is judged to be a big win or a small win, the process proceeds to step S536-9, and if it is judged not to be a big win or a small win (miss), the process proceeds to step S536-11.

(Step S536-9)
The main CPU 300a sets the random number judgment table for determining the reach mode at the time of a big win (see Figures 10(b) and (c)) or the random number judgment table for determining the reach mode at the time of a small win (see Figures 10(d) and (e)), and transfers the processing to step S536-19.

(Step S536-11)
The main CPU 300a loads the reach group determination random number stored in the target memory section in step S535-13.

(Step S536-13)
The main CPU 300a judges whether the reach group determination random number loaded in step S536-11 is a fixed value (9000 or more). Here, the group type is determined by referring to the reach group determination random number judgment table, and this reach group determination random number judgment table is selected according to the number of reserved items stored. At this time, the reach group determination random number is acquired from a range of 0 to 10006, and if the value of the reach group determination random number is 9000 or more, the same reach group determination random number judgment table is selected regardless of the number of reserved items, and if the value of the reach group determination random number is less than 9000, a different reach group determination random number judgment table is selected depending on the number of reserved items. Hereinafter, the value of the reach group determination random number in the range of 0 to 8999, where a different reach group determination random number judgment table is selected depending on the number of reserved items, is referred to as an indefinite value, and the value in the range of 9000 to 10006, where the same reach group determination random number judgment table is selected regardless of the number of reserved items, is referred to as a fixed value. If it is determined that the reach group determination random number loaded in step S536-11 above is a fixed value (9000 or more), processing proceeds to step S536-15, and if it is determined that the reach group determination random number loaded in step S536-11 above is not a fixed value (9000 or more), processing proceeds to step S536-27.

(Step S536-15)
The main CPU 300a sets a reach group determination random number judgment table (see FIG. 9). Note that, although there are multiple types of reach group determination random number judgment tables provided according to the reserved number, here, a table to be used when the reserved number is 0 is selected. Then, a reach group (group type) is provisionally determined based on the set reach group determination random number judgment table and the reach group determination random number stored in the target memory unit in step S535-13.

(Step S536-17)
The main CPU 300a sets the miss-time reach mode determination random number judgment table (see FIG. 10(a)) corresponding to the group type provisionally determined in step S536-15, and moves the process to step S536-19.

(Step S536-19)
The main CPU 300a provisionally determines a variation mode number based on the reach mode determination random number judgment table set in the above step S536-9 or step S536-17 and the reach mode determination random number stored in the target memory unit in the above step S535-13. Here, a variation pattern random number judgment table is provisionally determined together with the variation mode number.

(Step S536-21)
The main CPU 300a sets in the transmission buffer a read-ahead designation fluctuation mode command (read-ahead designation command) corresponding to the fluctuation mode number tentatively determined in step S536-19.

(Step S536-23)
The main CPU 300a provisionally determines a fluctuation pattern number based on the fluctuation pattern random number determination table provisionally determined in the above step S536-19 and the fluctuation pattern random number stored in the target memory unit in the above step S535-13.

(Step S536-25)
The main CPU 300a sets in the transmission buffer a look-ahead specified variable pattern command (look-ahead specification command) corresponding to the variable pattern number provisionally determined in step S536-23 above, and terminates the performance determination process at the time of acquisition.

(Step S536-27)
The main CPU 300a sets in the transmission buffer an indefinite value command (look-ahead specified variable mode command and look-ahead specified variable pattern command = 7FH) indicating that the group type, i.e., the variable presentation pattern, will change depending on the number of holds when the holds are read out for the holds newly stored in the target memory unit, and terminates the presentation determination process at the time of acquisition.

Figure 34 is a flowchart explaining the large prize opening passage process (step S540) in the main control board 300 in the simultaneous rotation reference example.

(Step S540-1)
When the main CPU 300a determines in step S500-13 that the big prize opening detection switch is ON, it loads a special electric accessory game management phase, which will be described later in detail. Note that, as will be described later in detail, the special electric accessory game management phase indicates the stage of the execution process of the big prize game or the small prize game, that is, the progress of the big prize game or the small prize game, and is updated according to the stage of the execution process of the big prize game or the small prize game.

(Step S540-3)
The main CPU 300a judges whether the special electric role game management phase loaded in the above step S540-1 indicates a stage of execution processing of the large prize opening pre-processing or higher. The special electric role game management phase has nine stages from 00H to 08H, of which 01H to 08H correspond to the stage of execution processing of the large prize opening pre-processing or higher. Since the large role game or the small prize game is executed when the special electric role game management phase is 01H to 08H, here, it is judged whether the large role game or the small prize game is currently being played. If it is judged that the special electric role game management phase indicates a stage of execution processing of the large prize opening pre-processing or higher, the process proceeds to step S540-5, and if it is judged that the special electric role game management phase does not indicate a stage of execution processing of the large prize opening pre-processing or higher, the process proceeds to step S540-7.

(Step S540-5)
The main CPU 300a sets a large prize opening ball entry command, indicating that the game ball has properly entered the first large prize opening 126 or the second large prize opening 128, in the transmission buffer, and ends the large prize opening passage process.

(Step S540-7)
The main CPU 300a determines that the entry of the game ball into the first large prize opening 126 or the second large prize opening 128 is inappropriate, executes a prescribed error process, and terminates the large prize opening passage process.

Figure 35 is a diagram explaining the special game management phase in the simultaneous spin reference example. As already explained, in the simultaneous spin reference example, a special game triggered by the entry of a game ball into the first start port 120 or the second start port 122 and a normal game triggered by the passage of a game ball through the gate 124 or the entry of a game ball into the normal operation port 125 proceed simultaneously in parallel. The processing related to the special game is executed stepwise and repeatedly, and the main control board 300 manages each processing related to such special games by the special game management phase and the special electric device game management phase.

As shown in FIG. 35, the main ROM 300b stores a number of special game control modules for controlling the execution of the display of changing special symbols in special games, and each of these special game control modules is associated with a special game management phase. Specifically, when the special game management phase is "00H", a module for executing "special symbol change waiting process" is called, when the special game management phase is "01H", a module for executing "special symbol changing process" is called, and when the special game management phase is "02H", a module for executing "special symbol stop symbol display process" is called.

In addition, the main ROM 300b stores a plurality of special electric role control modules for controlling the execution of the big prize game and the small prize game among the special games, and each of these special electric role control modules is associated with a special electric role game management phase. Specifically, when the special electric role game management phase is "01H" or "05H", a module for executing "large prize opening pre-processing" is called, when the special electric role game management phase is "02H" or "06H", a module for executing "large prize opening control processing" is called, when the special electric role game management phase is "03H" or "07H", a module for executing "large prize opening closing valid processing" is called, and when the special electric role game management phase is "04H" or "08H", a module for executing "large prize opening end wait processing" is called. In addition, when the special electric role play management phase is "00H", none of the special electric role play control modules are called.

Figure 36 is a flowchart explaining the special game management process (step S600) in the main control board 300 in the simultaneous rotation reference example.

(Step S600-1)
The main CPU 300a loads the special electric role play management phase.

(Step S600-3)
The main CPU 300a judges whether the special electric role game management phase loaded in the above step S600-1 is other than "00H". That is, here, it judges whether the big role game or the small role game is currently being played. If it is judged that the special electric role game management phase is other than "00H", the special game management process is terminated, and if it is judged that the special electric role game management phase is not other than "00H", the process proceeds to step S600-5.

(Step S600-5)
The main CPU 300a loads a special game special symbol determination flag. The special game special symbol determination flag is for determining whether the reserved type to be the target of the special game management process is special 1 reserved or special 2 reserved, and the special game special symbol determination flag (00H) indicates special 1 reserved, and the special game special symbol determination flag (01H) indicates special 2 reserved.

(Step S600-7)
The main CPU 300a inverts the special game special symbol determination flag loaded in the above step S600-5. Here, if the special game special symbol determination flag is "00H", it is inverted to "01H", and if the special game special symbol determination flag is "01H", it is inverted to "00H". Since the initial value of the special game special symbol determination flag is set to "00H", in the first special game management process S600 of the two special game management processes S600 shown in FIG. 26, the special game special symbol determination flag is set to "01H" and the subsequent process is executed for the special 2 reservation, and in the second special game management process S600, the special game special symbol determination flag is set to "00H" and the subsequent process is executed for the special 1 reservation. In other words, the special 2 reservation is processed preferentially.

(Step S600-9)
The main CPU 300a saves the special game special symbol determination flag that was inverted in step S600-7.

(Step S600-11)
The main CPU 300a loads the special game management phase.

(Step S600-13)
The main CPU 300a selects the special game control module corresponding to the special game management phase loaded in step S600-11.

(Step S600-15)
The main CPU 300a calls the special game control module selected in step S600-13 and starts processing.

(Step S600-17)
The main CPU 300a loads a special game timer that manages the control time of the special game, and ends the special game management process.

Figure 37 is a flowchart explaining the special symbol change waiting process in the main control board 300 in the simultaneous spin reference example. This special symbol change waiting process is executed when the special game management phase is "00H".

(Step S610-1)
The main CPU 300a judges whether the number of reserved balls with special symbols in the reserved balls (special 1 reserved or special 2 reserved, hereinafter referred to as the target reserved balls) that are the subject of the special game management process is 1 or more. If it is judged that the number of reserved balls with special symbols is 1 or more, the process proceeds to step S610-3, and if it is judged that the number of reserved balls with special symbols is not 1 or more, the process of waiting for the change of the special symbols is terminated.

(Step S610-3)
The main CPU 300a judges whether a special symbol (hereinafter referred to as a non-target special symbol) based on a reserve that is not the target of the special game management process (special reserve 2 or special reserve 1, hereinafter referred to as a non-target reserve) is being determined. If it is determined that a non-target special symbol is being determined, the process proceeds to step S610-5, and if it is determined that a special symbol based on a non-target special symbol is not being determined, the process proceeds to step S610-9.

(Step S610-5)
The main CPU 300a judges whether the non-target special symbol is a big win symbol. If it is judged to be a big win symbol, the process of waiting for the special symbol change is terminated. If it is judged not to be a big win symbol, the process proceeds to step S610-7.

(Step S610-7)
The main CPU 300a judges whether the non-target special symbol is a small win symbol. If it is judged to be a small win symbol, the main CPU 300a ends the special symbol variation waiting process, and if it is judged not to be a small win symbol, the process proceeds to step S610-9.

(Step S610-9)
The main CPU 300a transfers the target reservation stored in the first to fourth storage sections of the special symbol reservation storage area corresponding to the target reservation in a block to a storage section with a smaller ordinal number by one. Specifically, the target reservation stored in the second to fourth storage sections is transferred to the first to third storage sections. The main RAM 300c is also provided with a 0th storage section to be processed, and the target reservation stored in the 1st storage section is block transferred to the 0th storage section. In addition, in this special symbol storage area shift process, the counter value of the target special symbol reservation ball number counter corresponding to the target reservation is subtracted by "1", and a reservation subtraction designation command indicating that the target reservation has been subtracted by "1" is set in the transmission buffer.

(Step S611)
The main CPU 300a executes a special symbol winning determination process for performing a lottery for a big win. This special symbol winning determination process will be described later.

(Step S610-11)
The main CPU 300a executes a special symbol pattern determination process to determine a special symbol. Here, if the result of the big role lottery in the step S611 is a big win or a small win, the winning symbol random number and reserved type transferred to the 0th memory unit are loaded, the corresponding winning symbol random number determination table or small win symbol random number determination table is selected to extract special symbol determination data, and the extracted special symbol determination data (type of big win symbol) is saved. Also, if the result of the big role lottery in the step S611 is a loss, the special symbol determination data for loss is saved. Then, after the special symbol determination data is saved, a symbol type designation command corresponding to the special symbol determination data is set in the transmission buffer.

(Step S610-13)
The main CPU 300a saves the special symbol stop symbol number corresponding to the special symbol determination data extracted in step S610-11. The first special symbol display 160 and the second special symbol display 162 are each composed of 7 segments, and each segment constituting the 7 segments is associated with a number (counter value). The special symbol stop symbol number determined here indicates the number (counter value) of the segment that will finally be lit up.

(Step S612)
The main CPU 300a executes a special symbol variable number determination process for determining a variable mode number and a variable pattern number. The details of this special symbol variable number determination process will be described later.

(Step S610-15)
The main CPU 300a loads the fluctuation mode number and the fluctuation pattern number determined in step S612, and refers to the fluctuation time determination table to determine the fluctuation time 1 and the fluctuation time 2. Then, the total time of the determined fluctuation times 1 and 2 is set in the special symbol fluctuation timer.

(Step S610-17)
The main CPU 300a judges whether the result of the big prize lottery is a big prize or not, and if it is a big prize, loads the special symbol judgment data saved in the above step S610-11 and checks the type of the big prize symbol. Then, referring to the game state setting table and the current game state, it judges the game state, the high probability number of times, and the time-saving number of times to be set after the big prize game ends, and saves the judgment results in the special symbol probability state reserve flag, the time-saving state reserve flag, the high probability number cut reserve counter, and the time-saving number cut reserve counter. Note that if a losing symbol is saved, the process proceeds to the next process without executing the process.

(Step S610-19)
The main CPU 300a executes a process of setting a special symbol display counter in order to start the variable display of the special symbol in the first special symbol display 160 or the second special symbol display 162. A counter value is associated with each segment of the 7-segment that constitutes the first special symbol display 160 and the second special symbol display 162, and the segment corresponding to the counter value set in the special symbol display counter is controlled to light up. Here, the counter value corresponding to the segment to be lit at the start of the variable display of the special symbol is set in the special symbol display counter. Note that the special symbol display counter is provided separately as a special symbol 1 display counter corresponding to the first special symbol display 160 and a special symbol 2 display counter corresponding to the second special symbol display 162, and here, a counter value is set in the counter corresponding to the reserved type.

(Step S613)
The main CPU 300a executes a number-of-plays management process. Here, a process for ending the time-limited gaming state according to the number of times of fluctuation is performed. This number-of-plays management process will be described later.

(Step S610-21)
The main CPU 300a sets in the transmission buffer a number command indicating the number of times remaining (actual remaining number of times) until the high probability number of times and the time-saving number of times reach 0.

(Step S610-23)
The main CPU 300a sets in the transmission buffer a game state change designation command indicating the game state at the start of the variable display of the special symbol.

(Step S610-25)
The main CPU 300a updates the special game management phase to "01H" and ends the special symbol change waiting process.

Figure 38 is a flowchart explaining the special symbol winning determination process (S611) for the simultaneous spin reference example.

(Step S611-1)
The main CPU 300a loads the special symbol probability state flag.

(Step S611-3)
The main CPU 300a loads the registered setting values in the setting value buffer.

(Step S611-5)
The main CPU 300a judges whether the registered setting value loaded in step S611-3 is within the normal range. If it is judged to be within the normal range, the process proceeds to step S611-11. If it is judged to be not within the normal range, the process proceeds to step S611-7.

(Step S611-7)
The main CPU 300a sets the gaming machine status flag to 03H (abnormal setting status).

(Step S611-9)
The main CPU 300a sets the setting abnormal state command (sub-command) in the transmission buffer and ends the special symbol winning determination process. When this setting abnormal state command is transmitted to the sub-control board 330, a notification that a setting abnormality has occurred is issued.

(Step S611-11)
The main CPU 300a refers to the big win determination random number judgment table corresponding to the information loaded in the above steps S611-1 and S611-3, and sets the lower limit and upper limit for determining whether a big win or a small win has occurred.

(Step S611-13)
The main CPU 300a compares the jackpot determination random number transferred to the 0th memory unit with the above-mentioned lower limit value and upper limit value, and performs a determination process (big prize lottery) to determine whether a jackpot or small jackpot has been won.

(Step S611-15)
The main CPU 300a judges whether the non-target special symbol is a big win symbol. If it is judged to be a big win symbol, the process proceeds to step S611-17. If it is judged not to be a big win symbol, the process proceeds to step S611-21.

(Step S611-17)
The main CPU 300a judges whether the result of the big role lottery in the step S611-13 is a small win or a miss. If it is judged to be a small win or a miss, the process proceeds to step S611-21, and if it is not a small win or a miss, the process proceeds to step S611-19.

(Step S611-19)
The main CPU 300a changes the result of the big role lottery in the above step S611-13 to a loss.

(Step S611-21)
The main CPU 300a sets the result of the determination process in the above step S611-13 or the result changed in the above step S611-19 as determination information, and ends the special symbol winning determination process.

Figure 39 is a flowchart explaining the special pattern variable number determination process (step S612) in the main control board 300 for the simultaneous rotation reference example.

(Step S612-1)
The main CPU 300a judges whether the result of the big prize lottery in the step S611 is a big win or a small win. If it is judged to be a big win or a small win, the process proceeds to step S612-3, and if it is judged to be neither a big win nor a small win (a miss), the process proceeds to step S612-5.

(Step S612-3)
The main CPU 300a sets a reach mode determination random number judgment table corresponding to the current game status and reserved type.

(Step S612-5)
When the hold type of the read-out hold is special 2 hold, the main CPU 300a checks the counter value of the special pattern 2 hold ball count counter, and when the hold type of the read-out hold is special 1 hold, the main CPU 300a checks the counter value of the special pattern 1 hold ball count counter.

(Step S612-7)
The main CPU 300a sets the corresponding reach group determination random number judgment table based on the current game state, the reserved number and reserved type confirmed in the above step S612-5, and determines the reach group (group type) based on the set reach group determination random number judgment table and the reach group determination random number transferred to the 0th memory unit in the above step S610-9.

(Step S612-9)
The main CPU 300a sets a random number judgment table for determining a losing reach mode corresponding to the group type determined in step S612-7.

(Step S612-11)
The main CPU 300a determines a variation mode number based on the reach mode determination random number judgment table set in the above step S612-3 or step S612-9 and the reach mode determination random number transferred to the 0th memory unit in the above step S610-9. Here, a variation pattern random number judgment table is also determined together with the variation mode number.

(Step S612-13)
The main CPU 300a sets in the transmission buffer a fluctuation mode command corresponding to the fluctuation mode number determined in step S612-11 above.

(Step S612-15)
The main CPU 300a determines a variation pattern number based on the variation pattern random number determination table determined in the above step S612-11 and the variation pattern random number transferred to the 0th memory unit in the above step S610-9.

(Step S612-17)
The main CPU 300a sets the variation pattern command corresponding to the variation pattern number determined in step S612-15 in the transmission buffer, and ends the special pattern variation number determination process.

Figure 40 is a flowchart explaining the cutoff number management process (step S613) in the main control board 300 in the simultaneous rotation reference example.

(Step S613-1)
The main CPU 300a judges whether the time-saving count, i.e., the counter value of the time-saving count cut-off counter, is greater than 0. As a result, if it is judged that the time-saving count is greater than 0, the process proceeds to step S613-3, and if it is judged that the time-saving count is 0, the time-cut-off management process is terminated.

(Step S613-3)
The main CPU 300a decrements the time-saving cut counter.

(Step S613-5)
In the above step S613-3, the main CPU 300a judges whether the counter value (time-saving count) has been updated to 0. As a result, if it is judged that the time-saving count is 0, the process proceeds to step S613-7, and if it is judged that the time-saving count is not 0, the process for managing the number of times the game has been cut is terminated.

(Step S613-7)
The main CPU 300a sets the time-saving state flag to set the normal game state to a non-time-saving game state. As a result, after the normal game state is set to the time-saving game state, the normal game state is changed to the non-time-saving game state at the start of the change when the change count reaches the time-saving count (here, 50 or 100 times). For example, if it is set to the high probability premonition state, it is set to the most advantageous state.

(Step S613-9)
The main CPU 300a turns on the time-saving end flag and ends the number-of-times-cut management process.

Figure 41 is a flowchart explaining the processing during special pattern change on the main control board 300 in the simultaneous rotation reference example.

(Step S620-1)
The main CPU 300a judges whether the interruption flag is on. In addition, although details will be described later, in the simultaneous rotation reference example, a small winning pattern may be displayed in a stopped state on the second special pattern display 162 during the variable display of the pattern on the first special pattern display 160. In this case, when the small winning pattern is displayed in a stopped state on the second special pattern display 162, a small winning game is executed, during which the subtraction of the variable time of the special pattern on the first special pattern display 160 is suspended, and after the small winning game ends, the variable display of the pattern on the first special pattern display 160 is resumed. The interruption flag is turned on if the variable display of the pattern is being performed on the first special pattern display 160 when the small winning pattern is displayed in a stopped state on the second special pattern display 162. Here, if it is determined that the interruption flag is on, the special pattern variable process is terminated, and if it is determined that the interruption flag is not on, the process is moved to step S620-3.

(Step S620-3)
The main CPU 300a executes a process of updating the special symbol variation base counter. The special symbol variation base counter is set to a counter value that completes one revolution in a predetermined cycle (e.g., 100 ms). Specifically, when the counter value of the special symbol variation base counter is "0", a predetermined counter value (e.g., 25) is set, and when the counter value is "1" or more, the counter value is updated to a value obtained by subtracting "1" from the current counter value.

(Step S620-5)
The main CPU 300a judges whether the counter value of the special symbol variation base counter updated in step S620-3 is "0". If the counter value is "0", the process proceeds to step S620-7. If the counter value is not "0", the process proceeds to step S620-11.

(Step S620-7)
The main CPU 300a performs a special symbol fluctuation timer update process to subtract a predetermined value from the timer value of the special symbol fluctuation timer set in the above step S610-15.

(Step S620-9)
The main CPU 300a judges whether the timer value of the special symbol fluctuation timer updated in the above step S620-7 is "0". If the timer value is "0", the process proceeds to step S620-17, and if the timer value is not "0", the process proceeds to step S620-11.

(Step S620-11)
The main CPU 300a updates the special symbol display timer that measures the lighting time of each of the 7-segment segments that make up the first special symbol display device 160 and the second special symbol display device 162. Specifically, if the timer value of the special symbol display timer is "0", a predetermined timer value is set, and if the timer value is "1" or greater, the timer value is updated to a value obtained by subtracting "1" from the current timer value.

(Step S620-13)
The main CPU 300a judges whether the timer value of the special symbol display timer is "0". If it judges that the timer value of the special symbol display timer is "0", the process proceeds to step S620-15, and if it judges that the timer value of the special symbol display timer is not "0", the process during the special symbol variation is terminated.

(Step S620-15)
The main CPU 300a updates the counter value of the special symbol display symbol counter to be updated, and ends the special symbol variation process. As a result, each segment constituting the 7-segment display is sequentially lit at predetermined time intervals.

(Step S620-17)
The main CPU 300a judges whether the non-target special symbols are being displayed variably. If it is judged that the non-target special symbols are being displayed variably, the process proceeds to step S621. If it is judged that the non-target special symbols are not being displayed variably, the process proceeds to step S620-19.

(Step S621)
The main CPU 300a executes a symbol forcible stop process, which will be described later with reference to FIG.

(Step S620-19)
The main CPU 300a updates the special game management phase to "02H".

(Step S620-21)
The main CPU 300a saves the special symbol stop symbol number (counter value) determined in step S610-13 in the target special symbol display symbol counter. As a result, the determined special symbol is stopped and displayed on the first special symbol display device 160 or the second special symbol display device 162.

(Step S620-23)
The main CPU 300a sets in the transmission buffer a special symbol stop designation command indicating that a special symbol has been stopped and displayed on the first special symbol display device 160 or the second special symbol display device 162.

(Step S620-25)
The main CPU 300a sets the special pattern variation stop time, which is the time for which the special pattern is stopped and displayed, in the special game timer, and ends the special pattern variation process.

Figure 42 is a flowchart explaining the forced pattern stop process (step S621) in the main control board 300 in the simultaneous rotation reference example.

(Step S621-1)
The main CPU 300a judges whether the currently displayed special symbol is a small win symbol. If it is judged to be a small win symbol, the process proceeds to step S621-3. If it is judged not to be a small win symbol, the process proceeds to step S621-11.

(Step S621-3)
The main CPU 300a judges whether the special game special symbol determination flag is 00H, that is, whether the small win symbol is stopped and displayed on the first special symbol display 160. If it is judged that the special game special symbol determination flag is 00H, the process proceeds to step S621-11, and if it is judged that the special game special symbol determination flag is not 00H, the process proceeds to step S621-5.

(Step S621-5)
The main CPU 300a judges whether the special symbol being changed (the other) is a big win symbol. If it is judged to be a big win symbol, the process proceeds to step S621-11. If it is judged not to be a big win symbol, the process proceeds to step S621-7.

(Step S621-7)
The main CPU 300a turns on the interruption flag.

(Step S621-9)
The main CPU 300a executes a variation interruption process to interrupt the variable display of the special symbols, and ends the symbol forced stop process. Here, the main CPU 300a executes a process to temporarily save the remaining time of the variation time and information related to the special symbols in a predetermined memory area.

(Step S621-11)
The main CPU 300a forcibly stops the losing pattern on the first special pattern display 160 or the second special pattern display 162 on which the pattern is being displayed in a changing manner, and performs processing to turn on a special stop flag for the changing time to forcibly end the remaining changing time, and then ends the forced pattern stop processing.

When the small win symbol is displayed as a stopped symbol on the first special symbol display 160 by the above process, a losing symbol is forcibly displayed as a stopped symbol on the second special symbol display 162. Also, when a small win symbol is displayed as a stopped symbol on the second special symbol display 162, if a big win symbol is being displayed as a stopped symbol on the first special symbol display 160 during a variable display in which the big win symbol is finally displayed as a stopped symbol on the first special symbol display 160, a losing symbol is forcibly displayed as a stopped symbol on the first special symbol display 160. On the other hand, when a small win symbol is displayed as a stopped symbol on the second special symbol display 162, if a small win symbol or a losing symbol is being displayed as a stopped symbol on the first special symbol display 160 during a variable display in which the small win symbol or a losing symbol is finally displayed as a stopped symbol on the first special symbol display 160, the variable display on the first special symbol display 160 is temporarily interrupted.

Figure 43 is a flowchart explaining the special symbol stop symbol display process on the main control board 300 in the simultaneous rotation reference example.

(Step S630-1)
The main CPU 300a judges whether the timer value of the special game timer set in the above step S620-25 is "0". If it is judged that the timer value of the special game timer is not "0", the main CPU 300a ends the special symbol stop symbol display process, and if it is judged that the timer value of the special game timer is "0", the process proceeds to step S630-3.

(Step S630-3)
The main CPU 300a judges whether the variable time special stop flag is on. If it is judged that the variable time special stop flag is on, the process proceeds to step S630-5, and if it is judged that the variable time special stop flag is not on, the process for displaying the special symbol stop symbol is terminated.

(Step S630-5)
The main CPU 300a checks the result of the big role lottery.

(Step S630-7)
The main CPU 300a judges whether the result of the big role lottery is a miss. If it is judged to be a miss, the process proceeds to step S630-27, and if it is judged not to be a miss, the process proceeds to step S630-9.

(Step S630-9)
The main CPU 300a performs a game state update process to update the game state. Here, if the special symbol currently being stopped is a big win symbol, the game state is set to the initial state, and if the special symbol currently being stopped is a small win symbol, the game state proceeds directly to the next process.

(Step S630-11)
The main CPU 300a sets data in the special electric accessory operation RAM set table according to the type of the determined special symbol. Note that the main CPU 300a turns off the variable time special stop flag if it is on.

(Step S630-13)
The main CPU 300a performs a process for setting the maximum number of times that the special electric role is operated. Specifically, the data set in step S630-11 is referred to, and a predetermined number (counter value corresponding to the type of special symbol=number of rounds) is set as a counter value in the maximum number of times that the special electric role is operated. The maximum number of times that the special electric role is operated indicates the number of rounds that can be executed in the big role game that is about to start. Meanwhile, the main RAM 300c is provided with a counter for the number of consecutive times that the special electric role is operated, and the current number of rounds is managed by adding "1" to the counter value of the counter for the number of consecutive times that the special electric role is operated at the start of each round game. Here, a process for resetting (updating to "0") the counter value of the counter for the number of consecutive times that the special electric role is operated is also executed with the start of the big role game.

(Step S630-15)
The main CPU 300a refers to the data set in step S630-11 and saves a predetermined opening time as a timer value in the special electric role play timer.

(Step S630-17)
The main CPU 300a sets an opening designation command in the transmission buffer to transmit the start of the big prize game to the sub-control board 330.

(Step S630-19)
The main CPU 300a updates the special electric role game management phase to "01H" when starting a big win game, and updates the special electric role game management phase to "05H" when starting a small win game.

(Step S630-21)
The main CPU 300a updates the special game management phase to "00H".

(Step S630-23)
The main CPU 300a judges whether the special electric role game management phase updated in the above step S630-19 is "01H", that is, whether a jackpot has been reached. If it is judged that the special electric role game management phase is "01H", the process proceeds to step S630-25, and if it is judged that the special electric role game management phase is not "01H", the process proceeds to step S630-27.

(Step S630-25)
The main CPU 300a performs a jackpot signal output start process for outputting a jackpot signal from the game information output terminal board 312, and ends the special symbol stop symbol display process. This process causes a jackpot signal to be output with the start of the big win game (opening). Note that although multiple signals are provided to be output from the game information output terminal board 312, only a specific jackpot signal will be described here.

(Step S630-27)
The main CPU 300a sets in the transmission buffer a game state confirmation command at the time of special symbol determination, which indicates the game state when the special symbol is determined.

(Step S630-29)
The main CPU 300a judges whether the time-saving end flag is on. As described above, the time-saving end flag is turned on in step S613-9 in FIG. 40 at the start of the fluctuation when changing from the time-saving game state to the non-time-saving game state. That is, the time-saving end flag is turned on here when the normal game state is changed from the time-saving game state to the non-time-saving game state due to the time-saving exit at the start of the 50th or 100th fluctuation in the high probability premonition state. That is, here, the time-saving end flag is judged to be on only when the fluctuation at the time of the time-saving exit ends. If it is judged that the time-saving end flag is on, the process moves to step S630-31, and if it is judged that the time-saving end flag is not on, the process moves to step S630-35.

(Step S630-31)
The main CPU 300a performs a jackpot signal output stop process for stopping the jackpot signal output from the game information output terminal board 312. That is, the jackpot signal is output during a big win game or a time-saving game state.

(Step S630-33)
The main CPU 300a turns off the time-saving end flag.

(Step S630-35)
The main CPU 300a updates the special game management phase to "00H" and ends the special symbol stop symbol display process.

Figure 44 is a flowchart explaining the special electric role play management process (step S700) in the main control board 300 in the simultaneous rotation reference example.

(Step S700-1)
The main CPU 300a loads the special electric role play management phase.

(Step S700-3)
The main CPU 300a judges whether the special electric role game management phase loaded in the above step S700-1 is "00H". That is, here, it is judged whether the big role game or the small role game is currently being played. If it is judged that the special electric role game management phase is "00H", the special electric role game management process is terminated, and if it is judged that the special electric role game management phase is not "00H", the process proceeds to step S700-5.

(Step S700-5)
The main CPU 300a selects the special electric role game control module corresponding to the special electric role game management phase loaded in the above step S700-1.

(Step S700-7)
The main CPU 300a calls the special electric role game control module selected in step S700-5 and starts processing.

(Step S700-9)
The main CPU 300a loads a special electric feature game timer that manages the control time of the special electric feature game, and ends the special electric feature game management process.

Figure 45 is a flow chart explaining the processing before the opening of the large prize opening in the main control board 300 in the simultaneous rotation reference example. This processing before the opening of the large prize opening is executed when the special electric role play management phase is "01H" or "05H".

(Step S710-1)
The main CPU 300a judges whether the timer value of the special electric feature game timer set in the above step S630-15 is not "0". If it judges that the timer value of the special electric feature game timer is not "0", it ends the pre-opening process of the big prize opening, and if it judges that the timer value of the special electric feature game timer is "0", it moves the process to step S710-3.

(Step S710-3)
The main CPU 300a updates the counter value of the special electric device continuous operation number counter to a value obtained by adding "1" to the current counter value.

(Step S710-5)
The main CPU 300a sets in the transmission buffer a command to specify opening of the large prize opening to transmit the start of opening of the large prize opening (start of a round of play) to the sub-control board 330.

(Step S711)
The main CPU 300a executes a special prize opening/closing switching process, which will be described later.

(Step S710-7)
The main CPU 300a updates the special electric device play management phase to a value obtained by adding 01H to the current value ("02H" or "06H"), and ends the pre-opening process for the large prize opening.

Figure 46 is a flowchart explaining the large prize opening/closing switching process (S711) in the main control board 300 in the simultaneous rotation reference example.

(Step S711-1)
The main CPU 300a judges whether the counter value of the special electric device opening/closing switching counter is the upper limit of the special electric device opening/closing switching count (the number of times the special winning hole is opened and closed during one round of play). If it is judged that the counter value is the upper limit, the special winning hole opening/closing switching process is terminated, and if it is judged that the counter value is not the upper limit, the process proceeds to step S711-3.

(Step S711-3)
The main CPU 300a refers to the data in the special electric device operation RAM set table and extracts solenoid control data for controlling the energization of the first large prize opening solenoid 126c and the second large prize opening solenoid 128c, and time data which is the energization time or the de-energization time, based on the counter value of the special electric device opening/closing switching count counter.

(Step S711-5)
The main CPU 300a executes a large prize opening solenoid energization control process to start or stop energization of the first large prize opening solenoid 126c or the second large prize opening solenoid 128c based on the solenoid control data extracted in step S711-3. By executing this large prize opening solenoid energization control process, the start or stop of energization of the first large prize opening solenoid 126c or the second large prize opening solenoid 128c is controlled in steps S400-33 and S400-35.

(Step S711-7)
The main CPU 300a saves the timer value based on the time data extracted in step S711-3 in the special electric accessory game timer. The timer value saved in the special electric accessory game timer here is the maximum opening time of the big prize opening once.

(Step S711-9)
The main CPU 300a judges whether the first large prize opening solenoid 126c or the second large prize opening solenoid 128c is in the energization start state, that is, whether the control process to start energization of the first large prize opening solenoid 126c or the second large prize opening solenoid 128c has been performed in the above step S711-5. If it is judged to be in the energization start state, the process proceeds to step S711-11, and if it is judged not to be in the energization start state, the large prize opening opening opening/closing switching process is terminated.

(Step S711-11)
The main CPU 300a updates the counter value of the special electric device opening/closing switching count counter to a value obtained by adding "1" to the current counter value, and ends the large prize opening opening/closing switching process.

Figure 47 is a flowchart explaining the large prize opening control process in the main control board 300 in the simultaneous spin reference example. This large prize opening control process is executed when the special electric role play management phase is "02H" or "06H".

(Step S720-1)
The main CPU 300a judges whether the timer value of the special electric feature game timer saved in the above step S711-7 is 0. If it is judged that the timer value of the special electric feature game timer is not 0, the process proceeds to step S720-5, and if it is judged that the timer value of the special electric feature game timer is 0, the process proceeds to step S720-3.

(Step S720-3)
The main CPU 300a judges whether the counter value of the special electric role opening/closing switching counter is the upper limit value of the special electric role opening/closing switching count. If it is judged that the counter value is the upper limit value, the process proceeds to step S720-7, and if it is judged that the counter value is not the upper limit value, the process proceeds to step S711.

(Step S711)
In the above step S720-3, if it is determined that the counter value of the special electric role opening/closing switching count counter is not the upper limit value of the special electric role opening/closing switching count, the main CPU 300a executes the processing of the above step S711.

(Step S720-5)
The main CPU 300a judges whether the counter value of the large prize opening winning ball counter updated in the above step S500-9 has reached a specified number, that is, whether the number of game balls equal to the maximum number of winnings in one round has entered the large prize opening. If it is determined that the specified number has not been reached, the main CPU 300a ends the large prize opening opening opening control process, and if it is determined that the specified number has been reached, the process proceeds to step S720-7.

(Step S720-7)
The main CPU 300a executes a large prize opening closing process required to close the large prize opening by stopping the energization of the first large prize opening solenoid 126c or the second large prize opening solenoid 128c. As a result, the large prize opening becomes closed.

(Step S720-9)
The main CPU 300a saves the effective time (interval time) for closing the large prize opening in the special electric device play timer.

(Step S720-11)
The main CPU 300a updates the special electric role play management phase to a value obtained by adding 01H to the current value ("03H" or "07H").

(Step S720-13)
The main CPU 300a sets a special prize opening closure command, indicating that the special prize opening has been closed, in the transmission buffer, and ends the special prize opening opening control process.

Figure 48 is a flow chart explaining the large prize opening closure validity process in the main control board 300 in the simultaneous spin reference example. This large prize opening closure validity process is executed when the special electric role play management phase is "03H" or "07H".

(Step S730-1)
The main CPU 300a judges whether the timer value of the special electric feature game timer saved in the above step S720-9 is 0. If it is judged that the timer value of the special electric feature game timer is not 0, the main CPU 300a ends the large prize opening closure valid processing, and if it is judged that the timer value of the special electric feature game timer is 0, the processing proceeds to step S730-3.

(Step S730-3)
The main CPU 300a judges whether the counter value of the special electric device continuous operation counter matches the counter value of the special electric device maximum operation counter, that is, whether a preset number of rounds of play have been completed. If it is judged that the counter value of the special electric device continuous operation counter matches the counter value of the special electric device maximum operation counter, the process proceeds to step S730-9, and if it is judged that they do not match, the process proceeds to step S730-5.

(Step S730-5)
The main CPU 300a updates the special electric accessory game management phase to "01H". In addition, when the special electric accessory game management phase is 07H, that is, during the control of the small win game, the number of rounds of the small win game is "1", so that the result is always YES in the above step S730-3, and the process does not proceed to the step.

(Step S730-7)
The main CPU 300a saves the predetermined special prize opening closing time in the special game timer and ends the special prize opening closing validity process, thereby starting the next round of games.

(Step S730-9)
The main CPU 300a executes an ending time setting process for saving the ending time in a special electric role play timer.

(Step S730-11)
The main CPU 300a updates the special electric role play management phase to a value obtained by adding 01H to the current value ("04H" or "08H").

(Step S730-13)
The main CPU 300a sets an ending designation command indicating the start of the ending in the transmission buffer, and ends the large prize opening closure activation process.

Figure 49 is a flow chart explaining the large prize opening end wait process in the main control board 300 in the simultaneous rotation reference example. This large prize opening end wait process is executed when the special electric role play management phase is "04H" or "08H".

(Step S740-1)
The main CPU 300a judges whether the timer value of the special electric feature game timer saved in the above step S730-9 is not "0". As a result, if it is judged that the timer value of the special electric feature game timer is not "0", the main CPU 300a ends the large prize opening end wait process, and if it is judged that the timer value of the special electric feature game timer is "0", the process proceeds to step S740-3.

(Step S740-3)
The main CPU 300a judges whether the special electric role game management phase is "08H", that is, whether the small win game has ended. If it is judged that the special electric role game management phase is "08H", the process proceeds to step S740-11, and if it is judged that the special electric role game management phase is not "08H", the process proceeds to step S740-5.

(Step S740-5)
The main CPU 300a executes a state setting process to set the game state after the big win game ends. Here, the game state, the number of high probability games, and the number of time-saving games set in the preliminary area in the above step S610-17 are loaded, and the settings of each flag and the counter value are set as the game state after the big win game.

(Step S740-7)
In step S740-5, the main CPU 300a judges whether the normal game state has been set to the non-time-saving game state. If it is judged that the normal game state has been set to the non-time-saving game state, the process proceeds to step S740-9. If it is judged that the normal game state has not been set to the non-time-saving game state, the process proceeds to step S740-21.

(Step S740-9)
The main CPU 300a performs a big win signal output stop process to stop the big win signal output from the game information output terminal board 312. That is, when the most advantageous state is set after the big win game, the output of the big win signal is stopped when the big win game ends.

(Step S740-11)
The main CPU 300a judges whether the current game state is a high probability premonition state (high probability game state and time-saving game state). If it is judged to be a high probability premonition state, the process proceeds to step S740-13, and if it is judged not to be a high probability premonition state, the process proceeds to step S740-21.

(Step S740-13)
The main CPU 300a judges whether the stopped small winning symbol is the special symbol Z1. If it is judged to be the special symbol Z1, the process proceeds to step S740-15. If it is judged not to be the special symbol Z1, the process proceeds to step S740-21.

(Step S740-15)
The main CPU 300a sets the time-saving state flag to change the normal game state to a non-time-saving game state. As a result, when the special symbol Z1 is determined in the high probability premonition state, the game state is changed to the most advantageous state at the end of the small win game.

(Step S740-17)
The main CPU 300a performs a counter reset process to reset the time-saving number counter.

(Step S740-19)
The main CPU 300a performs a big win signal output stop process to stop the big win signal output from the game information output terminal board 312. That is, when the special symbol Z1 is won and the most advantageous state is set after the small win game, the output of the big win signal is stopped when the small win game ends.

(Step S740-21)
The main CPU 300a sets in the transmission buffer a game state change designation command for transmitting the game state to be set after the big win game ends.

(Step S740-23)
The main CPU 300a sets a number command corresponding to the number of high probability times and the number of time reduction times in a transmission buffer.

(Step S740-25)
The main CPU 300a updates the special electric role play management phase to "00H" and ends the waiting process for the end of the special winning slot. As a result, if the special 1 reserve or special 2 reserve is stored, the variable display of the symbols will be resumed.

Figure 50 is a diagram explaining the normal game management phase in the simultaneous play reference example. As already explained, in the simultaneous play reference example, the processing related to the normal game, which is triggered by the passage of the game ball through the gate 124 or the entry of the game ball into the normal play opening 125, is executed step by step and repeatedly, and the main control board 300 manages each processing related to such normal games by the normal game management phase.

As shown in FIG. 50, the main ROM 300b stores multiple normal game control modules for controlling the execution of normal games, and each of these normal game control modules is associated with a normal game management phase. Specifically, when the normal game management phase is "00H", a module for executing "normal symbol change waiting process" is called, when the normal game management phase is "01H", a module for executing "normal symbol change process" is called, when the normal game management phase is "02H", a module for executing "normal symbol stop symbol display process" is called, when the normal game management phase is "03H", a module for executing "normal electric role winning opening pre-processing" is called, when the normal game management phase is "04H", a module for executing "normal electric role winning opening opening control process" is called, when the normal game management phase is "05H", a module for executing "normal electric role winning opening closing valid process" is called, when the normal game management phase is "06H", a module for executing "normal electric role winning opening end wait process" is called.

Figure 51 is a flowchart explaining the normal game management process (step S800) in the main control board 300 in the simultaneous rotation reference example.

(Step S800-1)
The main CPU 300a loads the normal game management phase.

(Step S800-3)
The main CPU 300a selects the normal game control module corresponding to the normal game management phase loaded in step S800-1.

(Step S800-5)
The main CPU 300a calls the normal game control module selected in step S800-3 above and starts processing.

(Step S800-7)
The main CPU 300a loads a normal game timer that manages the control time of the normal game.

Figure 52 is a flowchart explaining the normal symbol change waiting process in the main control board 300 in the simultaneous rotation reference example. This normal symbol change waiting process is executed when the normal game management phase is "00H".

(Step S810-1)
The main CPU 300a loads the counter value of the normal symbol reserved ball number counter and judges whether the counter value is "0", that is, whether the normal symbol reserved is "0". If it is judged that the counter value is "0", the normal symbol change waiting process is terminated, and if it is judged that the counter value is not "0", the process proceeds to step S810-3.

(Step S810-3)
The main CPU 300a transfers the regular reserved balls (win-determining random numbers) stored in the first to fourth storage sections of the regular reserved ball storage area in blocks to the storage section with the next smaller ordinal number. Specifically, the regular reserved balls stored in the second to fourth storage sections are transferred to the first to third storage sections. The main RAM 300c is also provided with a 0th storage section to be processed, and the regular reserved balls stored in the 1st storage section are transferred to the 0th storage section. In addition, in this regular pattern storage area shift process, the counter value of the regular pattern reserved ball count counter is decremented by "1," and a regular reserved reduction command indicating that the regular reserved balls have been decremented by "1" is set in the transmission buffer.

(Step S810-5)
The main CPU 300a loads the winning determination random number transferred to the 0th memory unit, selects a winning determination random number judgment table corresponding to the current game state, performs a regular symbol lottery, and executes a regular symbol winning determination process that stores the lottery result.

(Step S810-7)
The main CPU 300a saves the normal symbol stop symbol number corresponding to the result of the normal symbol lottery in step S810-5. In the simultaneous spin reference example, the normal symbol display 168 is composed of one LED lamp, and in the case of a win, the normal symbol display 168 is turned on, and in the case of a loss, the normal symbol display 168 is turned off. The normal symbol stop symbol number determined here indicates whether or not the normal symbol display 168 is ultimately turned on. For example, in the case of a win, "0" is determined as the normal symbol stop symbol number, and in the case of a loss, "1" is determined as the normal symbol stop symbol number.

(Step S810-9)
The main CPU 300a checks the current game state, and selects and sets the corresponding normal symbol variation time data table.

(Step S810-11)
The main CPU 300a determines the normal symbol variation time based on the winning determination random number transferred to the 0th memory unit in step S810-3 and the normal symbol variation time data table set in step S810-9.

(Step S810-13)
The main CPU 300a saves the normal symbol variation time determined in the above step S810-11 in the normal game timer.

(Step S810-15)
The main CPU 300a executes a process of setting a normal pattern display pattern counter in order to start the variable display of normal patterns in the normal pattern display 168. When the counter value is set to, for example, "0" in the normal pattern display pattern counter, the normal pattern display 168 is controlled to be turned on, and when the counter value is set to "1", the normal pattern display 168 is controlled to be turned off. Here, a predetermined counter value is set in the normal pattern display pattern counter at the start of the variable display of normal patterns.

(Step S810-17)
The main CPU 300a sets a regular map reservation designation command indicating the number of regular map reservations stored in the regular map reservation memory area in a transmission buffer.

(Step S810-19)
The main CPU 300a sets a normal pattern designation command in the transmission buffer based on the normal pattern stopping pattern number determined in step S810-7 above, i.e., the pattern type (winning pattern or losing pattern) determined by the normal pattern winning judgment process.

(Step S810-21)
The main CPU 300a updates the normal game management phase to "01H" and ends the normal pattern change waiting process.

Figure 53 is a flowchart explaining the processing during normal symbol fluctuation in the main control board 300 in the simultaneous rotation reference example. This processing during normal symbol fluctuation is executed when the normal game management phase is "01H".

(Step S820-1)
The main CPU 300a judges whether the timer value of the normal game timer saved in step S810-13 is "0". If the timer value is "0", the process proceeds to step S820-9. If the timer value is not "0", the process proceeds to step S820-3.

(Step S820-3)
The main CPU 300a updates the normal symbol display timer that measures the light-on and light-off times of the normal symbol display 168. Specifically, if the timer value of the normal symbol display timer is "0", a predetermined timer value is set, and if the timer value is "1" or more, the timer value is updated to a value obtained by subtracting "1" from the current timer value.

(Step S820-5)
The main CPU 300a judges whether the timer value of the normal symbol display timer is "0". As a result, if it is judged that the timer value of the normal symbol display timer is "0", the process proceeds to step S820-7, and if it is judged that the timer value of the normal symbol display timer is not "0", the process during the normal symbol variation is terminated.

(Step S820-7)
The main CPU 300a updates the counter value of the normal symbol display symbol counter. Here, if the counter value of the normal symbol display symbol counter is a counter value indicating that the normal symbol display 168 is turned off, it is updated to a counter value indicating that the normal symbol display 168 is turned on, and if the counter value is a counter value indicating that the normal symbol display 168 is turned on, it is updated to a counter value indicating that the normal symbol display 168 is turned off, and the normal symbol variation process is terminated. As a result, the normal symbol display 168 is turned on and off (blinks) at predetermined intervals over the normal symbol variation time.

(Step S820-9)
The main CPU 300a saves the normal symbol stop symbol number (counter value) determined in step S810-7 in the normal symbol display symbol counter. As a result, the normal symbol display 168 is finally controlled to be turned on or off, and the result of the normal symbol lottery is announced.

(Step S820-11)
The main CPU 300a sets a normal pattern variation stop time, which is the time for stopping and displaying the normal pattern, in a normal game timer.

(Step S820-13)
The main CPU 300a sets a normal symbol stop command, which indicates that the stopped display of the normal symbols has begun, in the transmission buffer.

(Step S820-15)
The main CPU 300a updates the normal game management phase to "02H" and ends the normal pattern variation processing.

Figure 54 is a flowchart explaining the normal symbol stop symbol display process in the main control board 300 in the simultaneous rotation reference example. This normal symbol stop symbol display process is executed when the normal game management phase is "02H".

(Step S830-1)
The main CPU 300a judges whether the timer value of the normal game timer set in the above step S820-11 is not "0". As a result, if it is judged that the timer value of the normal game timer is not "0", the normal symbol stop symbol display process is terminated, and if it is judged that the timer value of the normal game timer is "0", the process proceeds to step S830-3.

(Step S830-3)
The main CPU 300a checks the result of the regular drawing.

(Step S830-5)
The main CPU 300a judges whether the result of the regular drawing is a win or not. If it is judged to be a win, the process proceeds to step S830-9, and if it is judged to be a no win (no win), the process proceeds to step S830-7.

(Step S830-7)
The main CPU 300a updates the normal game management phase to "00H" and ends the normal stop symbol display process. This ends the normal game management process based on one normal symbol reservation, and if a normal symbol reservation is stored, processing is performed to start the variable display of the next reserved normal symbol.

(Step S830-9)
The main CPU 300a refers to the data in the opening/closing control pattern table, and saves the time before normal power opening in the normal game timer as a timer value.

(Step S830-11)
The main CPU 300a updates the normal game management phase to "03H" and ends the normal symbol stop symbol display process. This starts the opening and closing control of the first variable start opening 120B.

Figure 55 is a flow chart explaining the processing before the opening of the winning opening of the normal electric device in the main control board 300 in the simultaneous rotation reference example. This processing before the opening of the winning opening of the normal electric device is executed when the normal game management phase is "03H".

(Step S840-1)
The main CPU 300a judges whether the timer value of the normal game timer set in the above step S830-9 is "0". As a result, if it is judged that the timer value of the normal game timer is not "0", the normal electric role winning opening pre-opening process is terminated, and if it is judged that the timer value of the normal game timer is "0", the process proceeds to step S841.

(Step S841)
The main CPU 300a executes a normal electric device prize opening opening/closing switching process, which will be described later.

(Step S840-3)
The main CPU 300a updates the normal game management phase to "04H" and ends the processing before opening the normal electric device winning opening.

Figure 56 is a flowchart explaining the normal electric role winning opening/closing switching process in the main control board 300 for the simultaneous rotation reference example.

(Step S841-1)
The main CPU 300a judges whether the counter value of the normal electric role opening/closing switching counter is the upper limit value of the normal electric role opening/closing switching count (the number of times the movable piece 120b of the first variable start port 120B is opened and closed during one opening/closing control). If it is judged that the counter value is the upper limit value, the normal electric role winning port opening/closing switching process is terminated, and if it is judged that the counter value is not the upper limit value, the process proceeds to step S841-3.

(Step S841-3)
The main CPU 300a refers to the data in the opening/closing control pattern table and extracts solenoid control data (energization control data or energization stop control data) for controlling the energization of the normal electric role solenoid 120c based on the counter value of the normal electric role opening/closing switching count counter, and time data which is the energization time (solenoid energization time) or energization stop time (normal electric closing effective time = pause time) of the normal electric role solenoid 120c.

(Step S841-5)
The main CPU 300a executes a normal electric role solenoid energization control process to start energizing the normal electric role solenoid 120c or to stop energizing the normal electric role solenoid 120c based on the solenoid control data extracted in the above step S841-3. By executing this normal electric role solenoid energization control process, the normal electric role solenoid 120c is controlled to start or stop energizing in the above step S400-33 and step S400-35.

(Step S841-7)
The main CPU 300a saves the timer value based on the time data extracted in step S841-3 in the normal game timer. The timer value saved in the normal game timer here is the maximum opening time of the first variable start port 120B once.

(Step S841-9)
The main CPU 300a judges whether the normal electric role solenoid 120c is in the energization start state, that is, whether the control process to start energization of the normal electric role solenoid 120c has been performed in the above step S841-5. As a result, if it is judged to be in the energization start state, the process proceeds to step S841-11, and if it is judged not to be in the energization start state, the normal electric role winning port opening/closing switching process is terminated.

(Step S841-11)
The main CPU 300a updates the counter value of the normal electric role opening/closing switching count counter to a value obtained by adding "1" to the current counter value.

Figure 57 is a flowchart explaining the normal electric device prize opening control process in the main control board 300 for the simultaneous rotation reference example. This normal electric device prize opening control process is executed when the normal game management phase is "04H".

(Step S850-1)
The main CPU 300a judges whether the timer value of the normal game timer saved in the above step S841-7 is not "0". As a result, if it is judged that the timer value of the normal game timer is not "0", the process proceeds to step S850-5, and if it is judged that the timer value of the normal game timer is "0", the process proceeds to step S850-3.

(Step S850-3)
The main CPU 300a judges whether the counter value of the normal electric role opening/closing switching counter is the upper limit value of the normal electric role opening/closing switching count. If it is judged that the counter value is the upper limit value, the process proceeds to step S850-7, and if it is judged that the counter value is not the upper limit value, the process proceeds to step S841.

(Step S841)
In the above step S850-3, if it is determined that the counter value of the normal electric role opening/closing switching count counter is not the upper limit value of the normal electric role opening/closing switching count, the main CPU 300a executes the processing of the above step S841.

(Step S850-5)
The main CPU 300a judges whether the counter value of the normal electric device winning ball counter updated in the above step S530-9 has reached a specified number, that is, whether the first variable start opening 120B has received the same number of game balls as the maximum number of winning balls during one opening/closing control. If it is determined that the specified number has not been reached, the normal electric device winning opening opening control process is terminated, and if it is determined that the specified number has been reached, the process proceeds to step S850-7.

(Step S850-7)
The main CPU 300a executes a normal electric role closing process required to stop the power supply to the normal electric role solenoid 120c and close the first variable start port 120B. This causes the first variable start port 120B to be in a closed state.

(Step S850-9)
The main CPU 300a saves the normal power effective state time in the normal game timer.

(Step S850-11)
The main CPU 300a updates the normal game management phase to "05H" and ends the normal electric device winning port opening control process.

Figure 58 is a flow chart explaining the normal electric device prize opening closure enable processing in the main control board 300 relating to the simultaneous rotation reference example. This normal electric device prize opening closure enable processing is executed when the normal game management phase is "05H".

(Step S860-1)
The main CPU 300a judges whether the timer value of the normal game timer saved in the above step S850-9 is not "0". As a result, if it is judged that the timer value of the normal game timer is not "0", the normal electric role winning port closure valid processing is terminated, and if it is judged that the timer value of the normal game timer is "0", the processing proceeds to step S860-3.

(Step S860-3)
The main CPU 300a saves the normal power end wait time in the normal game timer.

(Step S860-5)
The main CPU 300a updates the normal game management phase to "06H" and ends the normal electric device winning port closure validation processing.

Figure 59 is a flow chart explaining the normal electric role winning slot end wait process in the main control board 300 in the simultaneous rotation reference example. This normal electric role winning slot end wait process is executed when the normal game management phase is "06H".

(Step S870-1)
The main CPU 300a judges whether the timer value of the normal game timer saved in the above step S860-3 is not "0". As a result, if it is judged that the timer value of the normal game timer is not "0", the normal electric role winning port end wait process is terminated, and if it is judged that the timer value of the normal game timer is "0", the process proceeds to step S870-3.

(Step S870-3)
The main CPU 300a updates the normal game management phase to "00H" and ends the normal electric role winning port end wait process. As a result, if a normal symbol reservation is stored, the variable display of the normal symbol will be resumed. Next, as a reference example of the performance, specific performances that can be executed in the above-mentioned one-type gaming machine, one-type two-type gaming machine, and simultaneous spinning machine and specific processing related to the performance will be described.

<Example of performance>
FIG. 60 is a diagram for explaining an example of a variation performance of a no-reach variation pattern according to a reference performance example. As described above, when the main control board 300 performs a big role lottery, a variation performance is executed to notify the result of the big role lottery during the variation display of the special symbol, that is, during the variation time of the special symbol. In this variation performance, various background images are displayed on the main performance display unit 200a, and the performance symbols 210a, 210b, and 210c are displayed superimposed on the background images. During the variation performance, sound is output from the audio output device 206 in accordance with the image displayed on the main performance display unit 200a, and the performance lighting device 204 is controlled to light up, and the performance role device 202 is controlled to move, but detailed explanations are omitted here.

The variable performances in the reference performance examples are broadly divided into a no-reach variable pattern and a reach variable pattern. In the variable performance of the no-reach variable pattern, a background image (not shown) is displayed on the main performance display unit 200a, and the performance patterns 210a, 210b, and 210c are displayed in a variable manner superimposed on this background image. For example, as shown in FIG. 60(a), the performance patterns 210a, 210b, and 210c are displayed stationary in a combination that indicates that the big role lottery result was a miss. In this state, when a new special pattern is displayed, as the display of the special pattern starts, the three performance patterns 210a, 210b, and 210c start to display (scroll) as shown in FIG. 60(b). Note that the downward white arrow in the figure indicates that the performance patterns 210a, 210b, and 210c are displayed scrolling in the vertical direction.

Then, as shown in FIG. 60(c), first, the effect pattern 210a is displayed as a stopped pattern, and then, as shown in FIG. 60(d), the effect pattern 210c, which is different from the effect pattern 210a, is displayed as a stopped pattern. Then, at approximately the same timing as the special pattern stops being displayed as a stopped pattern on the first special pattern display device 160 or the second special pattern display device 162 after the variable display of the special pattern, the effect pattern 210b is displayed as a stopped pattern, as shown in FIG. 60(e), and the result of the big prize lottery is notified to the player based on the final stopped display state of the three effect patterns 210a, 210b, and 210c at this time.

Figure 61 is a diagram for explaining an example of a normal reach fluctuation pattern fluctuation performance according to a performance reference example. In the performance reference example, the reach fluctuation pattern is broadly divided into a normal reach fluctuation pattern, an advanced reach fluctuation pattern, and a pseudo-continuous reach fluctuation pattern. In the normal reach fluctuation pattern fluctuation performance, similar to the non-reach fluctuation pattern fluctuation performance, the fluctuation display of the performance patterns 210a, 210b, and 210c begins with the start of the fluctuation display of the special pattern, and as shown in Figure 61 (a), the performance pattern 210a is first displayed frozen. After that, as shown in Figure 61 (b), the performance pattern 210c, which is the same as the performance pattern 210a, is displayed frozen.

In this way, when the same performance symbols 210a, 210c are displayed in a reach state in the main performance display section 200a, as shown in FIG. 61(c), "reach" is displayed superimposed on the performance symbols 210a, 210c in the main performance display section 200a. Note that there are multiple types of reach states, and the same performance symbols 210a, 210c with any of the numbers "1" to "9" written on them are displayed in a stopped state. After that, as shown in FIG. 61(d), the shape of the performance symbols 210a, 210c is changed from that before the reach state and the variable display continues. Then, as shown in FIG. 61(e), finally, a performance symbol 210b different from the performance symbols 210a, 210c is displayed in a stopped state, and the player is notified that the result of the big role lottery was a miss.

Figure 62 is a diagram for explaining an example of the variation presentation of the development reach variation pattern at the time of a miss according to the performance reference example, and Figure 63 is a diagram for explaining an example of the variation presentation of the development reach variation pattern at the time of a big win according to the performance reference example. As shown in Figures 62(a)-(d) and 63(a)-(d), the variation presentation of the development reach variation pattern is similar to the variation presentation of the normal reach variation pattern, in which the performance patterns 210a and 210c are displayed in a reach state in the main performance display section 200a, and then a reach development presentation in which a predetermined development image (video) is played and displayed is executed. In this reach development presentation, for example, as shown in Figures 62(e) and 63(e), a mission is displayed on the main performance display section 200a, and as shown in Figures 62(f), (g) and 63(f), (g), an image toward the achievement of the mission is displayed.

Here, the development images for reach development effects are broadly divided into miss patterns and big win patterns, and in the development image for the miss pattern, as shown in FIG. 62(h), an image indicating failure of the mission is finally displayed, and then, as shown in FIG. 62(i), the performance patterns 210a, 210b, and 210c are displayed in a stopped combination to indicate a miss. On the other hand, in the development image for the big win pattern, as shown in FIG. 63(h), an image indicating success of the mission is finally displayed, and then, as shown in FIG. 63(i), the performance patterns 210a, 210b, and 210c are displayed in a stopped combination to indicate a big win.

The reach development effects include, for example, mission effects in which development images of mission challenges are displayed, and battle effects in which development images of friendly characters and enemy characters battling each other are displayed, as described above. The mission effects have multiple execution patterns with different mission contents, and the battle effects have multiple execution patterns with different characters appearing and fighting methods. As described above, the execution patterns of the mission effects are broadly divided into big win patterns in which the mission is accomplished and failure patterns in which the mission is failed, and the execution patterns of the battle effects are similarly broadly divided into big win patterns in which the friendly character triumphs over the enemy character and failure patterns in which the friendly character is defeated by the enemy character.

The big win pattern and the losing pattern are composed of the same content until the end of the performance, and differ in whether the friendly character ultimately wins or loses, or whether the mission is accomplished or not. Therefore, during the reach development performance, the player cannot distinguish the result of the big role lottery until the end of the variable performance, which gives the player a sense of expectation of a big win.

The big win pattern is selected only if the big win lottery result is a big win, and the miss pattern is selected only if the big win lottery result is a miss. However, the reach development effect may be executed twice in one variable performance, in which case the first reach development effect is executed in a miss pattern, and the second reach development effect is executed in either a miss pattern or a big win pattern. The flow of the performance when the reach development effect is executed twice in one variable performance is explained below.

Figure 64 is a diagram illustrating an example of a variable performance when the reach development performance relating to the reference performance example is executed twice. For example, after performance patterns 210a, 210c are displayed in a reach state, a mission performance is executed as shown in Figures 64(a) and (b). Up to this point, there is no difference from the case where the reach development performance is executed only once in one variable performance, but immediately after it is notified that the mission has not been completed, "REACH UP" is displayed on the main performance display section 200a as shown in Figure 64(c).

Then, as shown in FIG. 64(d), the main performance display section 200a displays a battle performance development image, and the second reach development performance starts. This battle performance development image shows a battle between an ally character and an enemy character, and when a jackpot is won, as shown in FIG. 64(e), the ally character finally wins against the enemy character, and as shown in FIG. 64(f), the performance symbols 210a, 210b, and 210c are displayed in a stopped combination to indicate a jackpot. On the other hand, when a loss occurs, as shown in FIG. 64(g), the ally character finally loses to the enemy character, and as shown in FIG. 64(h), the performance symbols 210a, 210b, and 210c are displayed in a stopped combination to indicate a loss.

Figure 65 is a diagram for explaining an example of the pseudo-successive reach fluctuation pattern fluctuation performance according to the performance reference example. As shown in Figure 65 (a), when the display of the fluctuation of the performance patterns 210a, 210b, and 210c starts, the performance patterns 210a, 210b, and 210c are temporarily stopped and displayed in one of multiple types of pseudo patterns that have been set up in advance, as shown in Figure 65 (b). In this pseudo pattern, for example, the same performance patterns 210a and 210b and the performance pattern 210c with a number "2" larger than these performance patterns 210a and 210b are temporarily stopped and displayed.

When the performance symbols 210a, 210b, and 210c are temporarily stopped in a pseudo mode, the display of the changing performance symbols 210a, 210b, and 210c is resumed, as shown in FIG. 65(c). In other words, the pseudo mode can be said to indicate a re-changing display of the performance symbols 210a, 210b, and 210c. After that, the performance symbols 210a, 210b, and 210c are temporarily stopped again in a pseudo mode, as shown in FIG. 65(d).

Then, as shown in FIG. 65(e), when the display of the varying effect symbols 210a, 210b, and 210c resumes, as shown in FIG. 65(f), the effect symbols 210a and 210c are displayed in a reach state, and thereafter, as shown in FIG. 65(g)-(i), the reach development effect is executed in the same manner as the developed reach variation pattern, and the result of the big prize lottery is notified to the player.

In this way, the pseudo-continuous reach fluctuation pattern's fluctuation performance differs from that of the developed reach fluctuation pattern in the content until the performance patterns 210a, 210c reach the state, and after the state is reached, the fluctuation performance proceeds in the same way as the developed reach fluctuation pattern.

In addition, in the pseudo-continuous reach fluctuation pattern, a plurality of fluctuation display patterns of the performance symbols 210a, 210b, and 210c until the reach state is reached are provided, and the number of tentative stop displays of the performance symbols 210a, 210b, and 210c, in other words, the number of times that the performance symbols 210a, 210b, and 210c are displayed, differs for each fluctuation display pattern. This fluctuation display pattern is determined by the fluctuation mode command, and the selection ratio of the fluctuation mode command when the jackpot is won and when it is lost is set so that the more the number of tentative stop displays (fluctuation displays) of the performance symbols 210a, 210b, and 210c, the higher the possibility (hereinafter referred to as "reliability") that a jackpot will ultimately be announced.

Specifically, if the result of the big role lottery is a big win, the selection ratio of the variable mode command with a large number of variable display counts is set higher than the selection ratio of the variable mode command with a small number of variable display counts, and if the result of the big role lottery is a loss, the selection ratio of the variable mode command with a small number of variable display counts is set higher than the selection ratio of the variable mode command with a large number of variable display counts.

In addition, the main control board 300 is set so that the reliability of the pseudo-successive reach fluctuation pattern is higher than the reliability of the extended reach fluctuation pattern. Therefore, the reliability is indicated by the number of tentative stop displays (fluctuating displays) of the performance symbols 210a, 210b, and 210c, and the player will watch the progress of the performance while hoping for more tentative stop displays (fluctuating displays) of the performance symbols 210a, 210b, and 210c.

The execution pattern of the above-mentioned variable performance is determined and controlled by the sub-control board 330 based on the variable command determined by the main control board 300. In other words, it can be said that the execution pattern of the variable performance is determined in cooperation between the main control board 300 and the sub-control board 330.

Figure 66 is a diagram explaining the variable performance determination table related to the performance reference example, in which Figure 66 (a) shows the first half variable performance determination table, and Figure 66 (b) shows the second half variable performance determination table. As described above, when the main control board 300 performs a big role lottery, a variable command is determined based on the result of the big role lottery, and each determined command is sent to the sub-control board 330. When the sub-control board 330 receives a variable mode command, it obtains a random number of 1 from the range of 0 to 249, and refers to the first half variable performance determination table to determine the execution pattern of the variable performance of the first half based on the obtained random number and the received variable mode command. Also, when it receives a variable pattern command, it obtains a random number of 1 from the range of 0 to 249, and refers to the second half variable performance determination table to determine the execution pattern of the variable performance of the second half based on the obtained random number and the received variable pattern command. Note that Figure 66 shows only a part of the first half variable performance determination table and the second half variable performance determination table.

As shown in FIG. 66, according to the first half variable performance decision table, a selection ratio for the execution pattern of the first half variable performance is set for each variable mode number (variation mode command), and according to the second half variable performance decision table, a selection ratio for the execution pattern of the second half variable performance is set for each variable pattern number (variation pattern command). Then, one variable performance is executed by combining and executing the execution patterns of the first and second half variable performances that have been determined.

The no-reach fluctuation pattern fluctuation performance is executed when "none" is determined as the execution pattern of the first half, indicating that the first half fluctuation performance is not executed, and "normal miss 1", "normal miss 2", "special miss 1", or "special miss 2" corresponding to the no-reach fluctuation pattern is determined as the execution pattern of the second half. For example, when a fluctuation mode command corresponding to the fluctuation mode number "01H", indicating that the first half fluctuation performance is not executed, is received, the sub-control board 330 always determines "none" as the execution pattern of the first half. In addition, at this time, the selection ratio is set in the second half fluctuation performance determination table so that only one of "normal miss 1", "normal miss 2", "special miss 1", or "special miss 2" is determined as the fluctuation pattern command that can be received at the same time. Therefore, by determining "none" as the execution pattern of the first half and determining "normal miss 1", "normal miss 2", "special miss 1", or "special miss 2" as the execution pattern of the second half, the execution pattern of the fluctuation performance is determined to be the no-reach fluctuation pattern described above.

On the other hand, the reach fluctuation pattern fluctuation performance is executed when a pattern other than "none" is determined as the execution pattern for the first half, and one of the reach development performances (shown as developments 1 to 5 in the figure) is determined as the execution pattern for the second half. In other words, when the reach fluctuation pattern fluctuation performance is executed in the main performance display unit 200a, a fluctuation mode command corresponding to a fluctuation mode number other than the fluctuation mode number = 01H is always received, and a fluctuation pattern command corresponding to a fluctuation pattern number that determines one of developments 1 to 5 is received.

Here, in FIG. 66(a), "Normal Reach 1" and "Normal Reach 2" in the execution pattern of the first half respectively indicate the background image and the variable display pattern of the performance symbols 210a, 210b, 210c displayed on the main performance display section 200a until the performance symbols 210a, 210b, 210c reach the reach state, or more specifically, until the reach development performance begins, among the variable performances of the normal reach variable pattern. These image patterns are designed in advance to match the variable display time of the special symbol associated with the variable mode number, and for example, when "Normal Reach 1" is determined, the images shown in FIG. 61(a)-(d) will be displayed on the main performance display section 200a.

In addition, in FIG. 66(a), "pseudo 2a" and the like in the execution pattern in the first half indicate the display pattern of the main change performance image displayed on the main performance display unit 200a until the reach development performance starts, among the change performances of the pseudo continuous reach change pattern, that is, the execution pattern of the pattern display performance in which the performance patterns 210a, 210b, and 210c are displayed changeably. For example, "pseudo 2a" indicates that the pseudo continuous reach change pattern of "pseudo 2" in which the change display number of the performance patterns 210a, 210b, and 210c is two, and the main change performance image is display pattern a. Also, "pseudo 3b" indicates that the pseudo continuous reach change pattern of "pseudo 3" in which the change display number of the performance patterns 210a, 210b, and 210c is three, and the main change performance image is display pattern b.

In the first half variation presentation decision table and second half variation presentation decision table shown in FIG. 66, the selection ratio is set so that the variation presentation of the no-reach variation pattern and the normal reach variation pattern is executed only when the result of the big role lottery is a miss. Also, the developed reach variation pattern and the pseudo-continuous reach variation pattern are determined both when there is a miss and when there is a jackpot, but the selection ratio of the developed reach variation pattern is set higher when there is a miss and lower when there is a jackpot than the pseudo-continuous reach variation pattern. In this way, by setting the selection ratio when there is a miss and when there is a jackpot, the pseudo-continuous reach variation pattern is set to have a higher reliability than the developed reach variation pattern.

Furthermore, within the pseudo-sequential reach fluctuation pattern, the more the number of pseudos, the higher the selection rate for a big win and the lower the selection rate for a miss, so that the more the number of pseudos, the higher the reliability.

As described above, the general flow of the variable performance is determined by the variable performance determination table, but at the start of the variable performance, the possibility of executing various element performances that make up the variable performance and the execution pattern are further determined based on the variable mode command or the variable pattern command. Here, element performance refers to all performances that make up the variable performance, such as the variable display of performance patterns 210a, 210b, and 210c on the main performance display unit 200a, the development image displayed on the main performance display unit 200a in the reach development performance, and even the performance that moves the performance role device 202, as described above. In the embodiment, preview performances (suggested performances) are executed at various times during the variable performance as element performances that make up the variable performance.

This preview performance is a performance in which a predetermined image is displayed on the main performance display unit 200a and the performance role device 202 is moved at a predetermined timing when the fluctuation performance starts, when the fluctuation patterns 210a, 210b, 210c are displayed again in the fluctuation performance of the pseudo continuous reach fluctuation pattern, and even during the reach development performance, and the possibility of execution and the execution pattern are determined for each preview performance. Each preview performance has multiple types of execution patterns, and for each of the multiple types of execution patterns, a selection ratio is set for each fluctuation pattern command or fluctuation mode command, in other words, for each possibility of winning the jackpot, and an expected value is set for each execution pattern based on this selection ratio.

As explained above, when the sub-control board 330 receives a variation command, it determines the execution pattern of the variation performance, whether each element performance can be executed, and the execution pattern, and the variation performance is executed while the special pattern is being displayed. In this way, the variation performance is executed once for each special pattern variable display, but in the embodiment, a performance spanning multiple special pattern variable displays is also executed.

Figure 67 is a diagram for explaining an example of a reserved display effect according to the reference example. A reserved display area 211 is provided at the bottom of the main effect display section 200a. Although not shown in Figures 60 to 65, the reserved display area 211 is always displayed on the main effect display section 200a even during variable effects and while waiting for a game. During variable effects, a reserved display effect is performed in this reserved display area 211. In the reserved display effect, the reserved display 212a indicating the reserved item read out to the processing area (zeroth memory section) during the big role lottery, the first reserved display 212b, the second reserved display 212c, the third reserved display 212d, and the fourth reserved display 212e indicating the reserved items stored in the first memory section to the fourth memory section of the first special chart reserved memory area, respectively, are displayed in the reserved display area 211. In the following, the reserved display 212a and the first reserved display 212b to the fourth reserved display 212e are collectively referred to as reserved display 212.

For example, when the special symbol is being displayed in a variable manner and four special 1 reserved symbols are stored in the main RAM 300c, the reserved symbol 212a and the first reserved symbol 212b to the fourth reserved symbol 212e, a total of five reserved symbols 212, are displayed in the reserved symbol display area 211 as shown in FIG. 67(a). Then, when the display of the special symbol is terminated from this state, the special 1 reserved symbol stored in the first memory unit is read into the processing area (the 0th memory unit) and a large role lottery is performed, and the reserved symbol shift processing of the main RAM 300c is executed, the reserved symbol 212a is erased and the first reserved symbol 212b to the fourth reserved symbol 212e are moved one position to the left as shown in FIG. 67(b). Furthermore, when the next special 1 reserved symbol is read from this state, each reserved symbol 212 is further moved as shown in FIG. 67(c). In this way, the reserved symbol display is a display that notifies the player of the number of special 1 reserved symbols stored in the main RAM 300c.

In addition, multiple display patterns of the reserved display 212 are provided, and the display color is different for each display pattern. In the main control board 300, when a reserved is stored, the acquisition time performance determination process (step S536) is executed, and a look-ahead designation command indicating the variable information to be determined when the newly stored reserved is read out to the 0th storage unit is sent to the sub-control board 330. When the sub-control board 330 receives the look-ahead designation command, it determines the display pattern of the reserved display 212 corresponding to the newly stored reserved based on the received command. At this time, the selection ratio of each display pattern is set for each look-ahead designation command, that is, for each variable information to be determined when the newly stored reserved is read out in the big role lottery. In other words, since the selection ratio of each display pattern is set according to the possibility of winning a jackpot and the execution pattern of the variable performance, the display pattern of the reserved display 212 suggests the reliability (expected value) of the jackpot.

Figure 68 (a) is a diagram explaining the final pending display pattern determination table, and Figure 68 (b) is a diagram explaining the previous pending display pattern determination table. As described above, in the acquisition time performance determination process in the main control board 300, a look-ahead designation command indicating the variation mode number and variation pattern number to be determined when the newly stored pending is read out is sent to the sub-control board 330. In other words, the look-ahead designation command is a command that transmits the variation mode number and variation pattern number to be determined when the pending is read out to the sub-control board 330. According to the final pending display pattern determination table, the selection ratio of the display pattern of the pending display 212 is set for each look-ahead designation command (variation pattern number), and when a look-ahead designation command is received, the final display pattern of the pending display 212, i.e., the final display pattern of the pending display 212a, is determined.

According to the final hold display pattern determination table shown in FIG. 68(a), one of eight display patterns is determined: "default (white)", "flashing", "blue", "yellow", "green", "black", "red", and "premium (rainbow)". Then, once the final display pattern of the hold display 212a is determined, the display pattern of the hold display 212 displayed before that is determined by referring to the previous hold display pattern determination table shown in FIG. 68(b). According to this previous hold display pattern determination table, a selection ratio of the display pattern of the hold display 212 to be displayed before the moving display is set for each display pattern of the hold display 212.

For example, when a hold is stored in the second memory section of the first special chart hold memory area in the main control board 300, the final display pattern of the hold display 212a is determined by referring to the final hold display pattern determination table. In this case, the display pattern of the first hold display 212b is then determined by referring to the previous hold display pattern determination table. At this time, the display pattern of the first hold display 212b is determined based on the previously determined final display pattern of the hold display 212a. For example, if the final display pattern of the hold display 212a is "blue," then according to the previous hold display pattern determination table, the display pattern of the first hold display 212b is determined to be "blinking" with a probability of 200/250, and "blue" with a probability of 50/250.

Once the display pattern of the first hold display 212b is determined in this manner, the display pattern of the second hold display 212c is then determined based on the previously determined display pattern of the first hold display 212b, again by referring to the previous hold display pattern determination table.

As described above, when a hold is stored, first the final display pattern of the hold display 212a is determined, and then the display pattern of the first hold display 212b is determined based on the determined final display pattern of the hold display 212a, and so on, in a manner that works backwards in the display order to determine the display patterns. Note that, according to the previous hold display pattern determination table, the selection ratio is set so that only a display pattern that is the same as the previously determined hold display 212 display pattern or one with a low reliability is determined.

As described above, in the hold display presentation, multiple display patterns are provided for the hold display 212, each of which has a different expected value for the award of a predetermined gaming profit. From the time the hold display 212 is first displayed on the main presentation display section 200a until it is finally erased, the hold display 212 may be displayed in one display pattern, or the display pattern may change during the display period.

In the reference example, the timing when the display pattern of the hold display 212 changes can be broadly divided into when the newly stored special hold 1 (hereinafter also referred to as the target hold) is moved to the first hold display 212b to the third hold display 212d, and when the target change display related to the target hold is in progress.

Next, we will explain the processing in the sub-control board 330 to execute the above-mentioned variable performance. Note that, in the following, we will omit explanations of the processing in the sub-control board 330 that is not related to the variable performance.

(Sub-CPU Initialization Processing of the Sub-Control Board 330)
FIG. 69 is a flowchart explaining the sub-CPU initialization process (S1000) of the sub-control board 330 relating to the reference example of performance.

(Step S1000-1)
When the power is turned on, the sub-CPU 330a reads a CPU initialization processing program from the sub-ROM 330b, and initializes and sets flags and the like stored in the sub-RAM 330c.

(Step S1000-3)
Next, the sub-CPU 330a performs a process of updating each effect random number, and thereafter repeats the process of step S1000-3 until an interrupt process is performed. Note that multiple types of effect random numbers are provided, and here, each effect random number is updated asynchronously.

(Sub-timer interrupt processing of the sub-control board 330)
70 is a flow chart for explaining the sub timer interrupt process (S1100) of the sub control board 330 according to the reference example. The sub control board 330 is provided with a reset clock pulse generating circuit (not shown) that generates a clock pulse at a predetermined cycle (30 times per second). When the reset clock pulse generating circuit generates a clock pulse, the sub CPU 330a reads a timer interrupt process program and starts the sub timer interrupt process.

(Step S1100-1)
The sub CPU 330a saves the registers.

(Step S1100-3)
The sub-CPU 330a performs processing for permitting an interrupt.

(Step S1100-5)
The sub-CPU 330a performs update processing of various timer counters used in the sub-control board 330. Here, unless otherwise specified, the various timer counters are decremented by 1 each time the sub-timer interrupt processing of the sub-control board 330 is performed, and the decrement stops when the counter reaches 0.

(Step S1200)
The sub-CPU 330a analyzes the command stored in the receive buffer of the sub-RAM 330c, and performs various processes according to the received command. When a command is transmitted from the main control board 300, the sub-control board 330 performs a command reception interrupt process, and the command transmitted from the main control board 300 is stored in the receive buffer. Here, the command stored in the receive buffer is analyzed by the command reception interrupt process.

(Step S1100-7)
The sub-CPU 330a performs a time schedule management process that refers to a time table and executes a process corresponding to the corresponding time stored in the time table. Here, based on the time data set in the time table, various flags are turned on or off, or commands are sent to each performance device, thereby controlling the execution of each performance, including the variable performance and the major role performance.

(Step S1100-9)
The sub-CPU 330a restores the registers and ends the sub-timer interrupt process.

Figure 71 is a flowchart explaining the look-ahead designation command reception process for the reference performance example that is executed when a look-ahead designation command is received, part of the command analysis process. As described above, the look-ahead designation command (look-ahead designation variable pattern command) is set in the main control board 300 in the performance determination process at the time of acquisition (steps S536-21, S536-25, and S536-27 in Figure 33), and then transmitted to the sub-control board 330 by the sub-command transmission process (step S100-65 in Figure 23).

(Step S1210-1)
The sub-CPU 330a first analyzes the received read-ahead designation command.

(Step S1210-3)
The sub-CPU 330a stores the advance judgment information based on the analysis result of the above step S1210-1. The sub-RAM 330c of the sub-control board 330 is provided with a first advance judgment information storage unit corresponding to the first special chart reserved storage area of the main control board 300, and a second advance judgment information storage unit corresponding to the second special chart reserved storage area. The first advance judgment information storage unit has four storage units, the first storage unit to the fourth storage unit. The first storage unit to the fourth storage unit of the first advance judgment information storage unit correspond to the first storage unit to the fourth storage unit of the first special chart reserved storage area, respectively. Similarly, the second advance judgment information storage unit has four storage units, the first storage unit to the fourth storage unit, and the first storage unit to the fourth storage unit of the second advance judgment information storage unit correspond to the first storage unit to the fourth storage unit of the second special chart reserved storage area, respectively. Here, the pre-determination information is stored in the memory section among the first to fourth memory sections of the first special chart reservation memory area or the second special chart reservation memory area of the main control board 300, which corresponds to the memory section in which the newly reserved data is stored.

(Step S1210-5)
The sub-CPU 330a performs a final hold display pattern determination process to determine the final display pattern of the hold display 212. Here, based on the received look-ahead designation command, the final hold display pattern determination table (FIG. 68(a)) is referenced, and the final display pattern of the hold display 212a is determined and stored.

(Step S1210-7)
The sub-CPU 330a derives the number of times to determine the display pattern of the reserved display 212, i.e., the change timing of the reserved display 212, based on the storage unit in which the reserved is stored, and determines the display pattern of the reserved display 212 by referring to the previous reserved display pattern determination table (FIG. 68(b)) for the derived number of times. Then, the display pattern information of the reserved display 212 thus determined is stored in a predetermined storage unit, and the process proceeds to step S1210-9.

(Step S1210-9)
Based on the determinations in steps S1210-5 and S1210-7, the sub-CPU 330a performs a hold display start process to start displaying the hold display 212, and ends the read-ahead designation command reception process. As a result, when the hold is stored, the display of the corresponding hold display 212 is started.

Figure 72 is a flowchart explaining the variable command receiving process executed when a variable command is received, which is part of the command analysis process for the reference example. As described above, the variable command is set in the special symbol variable number determination process (steps S612-13, S612-17 in Figure 39) in the main control board 300, and then transmitted to the sub-control board 330 by the sub-command transmission process (step S100-65 in Figure 23).

(Step S1220-1)
When a variation command is received, the sub-CPU 330a first analyzes and stores the received variation pattern command.

(Step S1220-3)
The sub-CPU 330a acquires the performance random number (0 to 249) updated in the above step S1000-3, and determines and stores the execution pattern of the variable performance in the latter half based on the acquired performance random number and the analysis result in the above step S1220-1.

(Step S1220-5)
The sub-CPU 330a analyzes and stores the received variation mode command.

(Step S1220-7)
The sub-CPU 330a acquires the performance random number (0 to 249) updated in the above step S1000-3, and determines and stores the execution pattern of the variable performance for the first half based on the acquired performance random number and the analysis result in the above step S1220-5.

(Step S1220-9)
The sub-CPU 330a obtains the performance random number (0 to 249) updated in step S1000-3 for each preview performance, and based on the obtained performance random number and the analysis results in steps S1220-1 and S1220-5, refers to each preview performance decision table to determine whether or not to execute each preview performance and the execution pattern, and stores the same.

(Step S1220-11)
The sub-CPU 330a executes a shift process to shift the pre-determination information stored in the pre-determination information storage unit. Here, when starting a variable performance based on the special 1 reservation, the pre-determination information stored in the fourth storage unit to the second storage unit of the first pre-determination information storage unit is shifted to the third storage unit to the first storage unit of the first pre-determination information storage unit, respectively, and when starting a variable performance based on the special 2 reservation, the pre-determination information stored in the fourth storage unit to the second storage unit of the second pre-determination information storage unit is shifted to the third storage unit to the first storage unit of the second pre-determination information storage unit, respectively.

(Step S1220-13)
The sub-CPU 330a performs a reservation display shift process to move and display the reservation display 212. In addition, here, when the display pattern of the reservation display 212 is to be changed, execution data for changing the display pattern at a predetermined timing is set.

(Step S1220-15)
The sub-CPU 330a sets the time data of the time table based on the determination of each step above, and ends the variable command receiving process. Based on the time table set here, in the above step S1100-7, the process of displaying the image for the variable performance on the main performance display unit 200a, the sound output process, the lighting control process of the performance lighting device 204, and other performance execution control are performed.

<Slot Machine 400>
As shown in the external views of Figures 73 and 74, a slot machine 400 as a gaming machine is provided with a housing 402 with an open front, and an upper front door 404 and a lower front door 406 which are rotatably arranged vertically side by side at one end of the front of the housing 402. A colorless and transparent symbol display window 408 made of a glass plate, a transparent resin plate or the like is provided at approximately the center of the lower part of the upper front door 404, and three reels 410 (left reel 410a, center reel 410b, right reel 410c) are provided at positions corresponding to the symbol display window 408 in the housing 402 so as to be rotatable independently of each other. As shown in the pattern arrangement in Figure 75 (a), multiple types of patterns are arranged in each of 20 equal areas on the outer peripheral surfaces of the left reel 410a, center reel 410b, and right reel 410c, and the player can view a total of nine patterns, three consecutive patterns located on the top, middle, and bottom rows of the left reel 410a, center reel 410b, and right reel 410c, through the pattern display window 408.

An operation unit installation stand 412 is formed on the top of the front lower door 406, and is provided with a medal insertion unit 414, a bet switch 416, a start switch 418, a stop switch 420, a performance switch 422, and the like. The medal insertion unit 414 accepts medals inserted as game value through a medal insertion port 414a. The bet switch 416 inserts (bet) a specified number of medals required for one game from among the medals electrically stored inside the slot machine 400 (hereinafter simply referred to as credits).

The start switch 418 is, for example, a lever that can detect tilting operation, and detects the start operation of the game by the player. The stop switches 420 (stop switch 420a, stop switch 420b, stop switch 420c) are provided corresponding to the left reel 410a, the center reel 410b, and the right reel 410c, respectively, and detect the stop operation by the player. Note that when the stop switch 420 can be stopped, the first stop is when the player operates one of the stop switches 420a, 420b, and 420c to stop, and after the first stop, the second stop is when the player operates one of the two stop switches 420 that have not been stopped, and after the second stop, the third stop is when the player operates the last remaining stop switch 420 to stop. The effect switch 422 is, for example, a push switch and a jog dial switch arranged around it so that it can rotate freely, and detects the push operation and rotation operation by the player.

A liquid crystal display unit 424 that displays various images associated with the performance is provided approximately in the center of the top of the upper front door 404. Performance lamps 426, for example consisting of high-brightness light-emitting diodes (LEDs), are provided at the top and left and right of the upper front door 404. Speakers 428 that provide auditory performances using sound effects, musical tones, etc. are provided at the left and right positions of the liquid crystal display unit 424 on the back surface of the upper front door 404 and at the left and right positions on the back surface of the lower front door 406.

The operation unit installation stand 412 is provided with a main credit display unit 430 and a main payout display unit 432. In addition, a sub-credit display unit 434 and a sub-payout display unit 436 are provided between the symbol display window 408 and the operation unit installation stand 412. The main credit display unit 430 and the sub-credit display unit 434 display the number of medals credited (number of credits), and the main payout display unit 432 and the sub-payout display unit 436 display the number of medals paid out.

Below the reels 410 in the housing 402, a medal payout device (medal hopper) 442 is provided for paying out medals from a medal discharge port 440a. In addition, at the lower front part of the front lower door 406, a receiving tray 440 is provided for storing medals paid out from the medal discharge port 440a. Also, a power switch 444 is provided inside the housing 402. The power switch 444 is operated by an administrator who manages the slot machine 400, and is used to switch between two states: a power-off state and a power-on state.

In addition, in the housing 402, a setting door key and a setting change switch (together referred to as a setting value setting means) (not shown) are provided on the main control board 500 described later. In the slot machine 400, when a predetermined key (operation key) is inserted into the setting door key and turned from the OFF position to the ON position, and the power is turned on via the power switch 444, the slot machine 400 transitions to a setting change mode, and the setting value can be changed (also simply referred to as a setting change). The setting value indicates the degree of advantage (machine odds) of the player in stages, and is expressed in six stages from 1 to 6, for example. In general, the setting value is set so that the higher the numerical value of the setting value, the higher the advantage in the game as a whole (the higher the expected number of coins to be won). Then, each time the setting change switch is pressed in a state in which the setting can be changed, the setting value is incremented by one, and the setting value is changed to one of the six setting values, for example, and when the start switch 418 is operated, the setting value is confirmed, and the setting door key is returned to its original position (OFF position), ending the setting change mode and allowing play. Note that settings can only be changed for a certain period of time after the power switch 444 is operated to turn on the power.

In the slot machine 400, when a game can be started and a specified number of medals are bet, the active line A is activated and the operation of the start switch 418 is activated. Here, the bet includes the case where the medals credited through the operation of the bet switch 416 are inserted, the case where the medals are inserted through the medal insertion section 414, and the case where the medals are automatically inserted based on the replay role displayed on the active line A, which will be described in detail later. The active line A is a line for determining the winning of the winning role, and in this embodiment, there is one line. As shown in FIG. 75(b), the active line A is set to a line connecting the positions corresponding to the symbols stopped in the middle row of the left reel 410a, the middle row of the middle reel 410b, and the top row of the right reel 410c among the nine symbols (three reels x three rows: top, middle, and bottom) facing the symbol display window 408. Invalid lines are lines other than the valid line A that are not used to determine whether a winning combination has been won, and which display other symbol combinations that make it easier to determine the winning combination when it is difficult to determine the winning combination based on the symbol combination displayed on the valid line A alone. In this embodiment, the five invalid lines B1, B2, B3, C1, and C2 shown in FIG. 75(b) are assumed.

When the player operates the start switch 418, the game begins, the left reel 410a, the center reel 410b, and the right reel 410c are spun, and a lottery for a winning type is executed. After that, the left reel 410a, the center reel 410b, and the right reel 410c are stopped according to the operation of the stop switches 420a, 420b, and 420c. Then, if a winning combination that can receive a medal payout is won based on the result of the lottery for a winning type and the combination of the symbols displayed on the active line A, the medal is paid out. If a winning combination that can receive a medal payout is not won or if a winning type that can receive a medal payout is won but not won, the game ends when the left reel 410a, the center reel 410b, and the right reel 410c all stop.

In this embodiment, the above-mentioned one game refers to a game from when a medal is inserted through the medal insertion section 414, when a credited medal is inserted through the operation of the bet switch 416, or when a medal is automatically inserted based on a replay role being displayed on the active line A, until the left reel 410a, middle reel 410b, and right reel 410c are controlled to rotate and a winning type lottery is executed in response to the player's operation of the start switch 418, and the left reel 410a, middle reel 410b, and right reel 410c corresponding to the operated stop switch 420a, 420b, 420c are controlled to stop in response to the result of the winning type lottery and the player's operation of the multiple stop switches 420a, 420b, and 420c, and if a winning role that may be awarded with a medal is won, the medal is paid out. In addition, if a player does not win a prize type that can receive a medal payout, or if a player wins but does not win a prize, one game ends when the left reel 410a, center reel 410b, and right reel 410c all come to a halt. However, the start of one game may be interpreted as the player operating the start switch 418 instead of the insertion of a medal or winning a replay role. The number of times such a game is repeated is defined as the number of games.

Figure 76 is a block diagram showing the schematic electrical configuration of the slot machine 400. As shown in Figure 76, the slot machine 400 is provided with a control board including a main control board 500 (main control unit) that controls the progress of the game, and a sub-control board 502 (sub-control unit) that controls the presentation according to the progress of the game. In addition, the transmission of electrical signals between the main control board 500 and the sub-control board 502 is limited to one direction only, from the main control board 500 to the sub-control board 502, from the viewpoint of preventing fraud, etc.

(Main control board 500)
The main control board 500 has semiconductor integrated circuits including a main CPU 500a which is a central processing unit, a main ROM 500b in which programs and the like are stored, and a main RAM 500c which functions as a work area, and generally controls the entire slot machine 400. Note that even if the power is cut off, the main RAM 500c retains data without erasing it, unless a setting change is made and the RAM is cleared.

The main control board 500 also has functional units such as an initialization means 600, a betting means 602, a winning type selection means 604, a reel control means 606, a determination means 608, a payout control means 610, a game status control means 612, a presentation status control means 614, and a command transmission means 616, which function when the main CPU 500a cooperates with the main RAM 500c based on a program stored in the main ROM 500b.

The main control board 500 receives various detection signals from the medal insertion detection unit 414b, which detects the insertion of medals into the medal insertion slot 414a, the bet switch 416, the start switch 418, and the stop switches 420a, 420b, and 420c, and the main CPU 500a executes various processes based on the received detection signals.

The initialization means 600 executes initialization processing on the main control board 500. The betting means 602 bets medals to be used in the game. The winning type selection means 604 performs a winning type selection based on the operation of the start switch 418, as will be described in detail later, to determine whether or not a winning role has been won, and more specifically, whether or not a winning type that includes a winning role has been won.

The reel control means 606 controls the rotation of the left reel 410a, middle reel 410b, and right reel 410c in response to the operation of the start switch 418, and controls the stopping of the corresponding left reel 410a, middle reel 410b, and right reel 410c in response to the operation of the stop switches 420a, 420b, and 420c corresponding to the rotating left reel 410a, middle reel 410b, and right reel 410c, respectively. In addition, the reel control means 606 may extend the time from enabling the operation of the stop switches 420a, 420b, 420c in the previous game to enabling the operation of the stop switches 420a, 420b, 420c by the player to display the lottery result of the winning type lottery (disabled by completing the operation of the stop switches 420a, 420b, 420c in the previous game) to a specified time in response to the operation of the start switch 418, and during that time, perform a reel effect (freeze effect) in which the reels 410a, 410b, 410c are rotated in various ways. The reel effect can be realized by not enabling any switch that should be enabled for a specified time, suspending a process that should be executed for a specified time, or not transmitting or receiving a signal of any switch that should be transmitted or received for a specified time.

The reel drive control unit 450 is also connected to the main control board 500. This reel drive control unit 450 drives the stepping motor 452 based on the rotation start signal for the left reel 410a, center reel 410b, and right reel 410c sent from the reel control means 606 in response to the operation signal of the start switch 418. The reel drive control unit 450 also stops the driving of the stepping motor 452 based on the stop signal for each of the left reel 410a, center reel 410b, and right reel 410c and the detection signal of the rotation position detection circuit 454 sent from the reel control means 606 in response to the operation signal of the stop switch 420.

The determination means 608 determines whether or not a symbol combination corresponding to a winning role has been displayed on the pay line A. Here, the display of a symbol combination corresponding to a winning role on the pay line A may simply be referred to as winning. The payout control means 610 pays out medals in the number (value amount) corresponding to the winning role based on the fact that a symbol combination corresponding to a winning role has been displayed on the pay line A (winning). In addition, the medal payout device 442 is connected to the main control board 500, and the payout control means 610 dispenses medals while counting the number of medals paid out.

The game state control means 612 refers to the result of the winning type lottery and the judgment result of the judgment means 608, and transitions the game state to one of multiple game states. The presentation state control means 614 refers to the result of the winning type lottery, the judgment result of the judgment means 608, and transition information of the game state, and transitions the presentation state to one of multiple presentation states.

The command transmission means 616 sequentially determines game-related commands associated with the operation of the betting means 602, the winning type selection means 604, the reel control means 606, the determination means 608, the payout control means 610, the game state control means 612, the presentation state control means 614, etc., and sequentially transmits the determined commands to the sub-control board 502.

The main control board 500 is also provided with a random number generator (random number generating means) 500d. The random number generator 500d sequentially increments the count value, loops it within a predetermined numerical range, and extracts the count value at a predetermined point in time to obtain a random number. The random number generated by the random number generator 500d of the main control board 500 (hereinafter referred to as the winning type lottery random number) is used to determine the gaming benefit to be awarded to the player, for example, the winning type by the winning type lottery means 604.

(Sub-control board 502)
Similarly to the main control board 500, the sub-control board 502 has various semiconductor integrated circuits including a sub-CPU 502a which is a central processing unit, a sub-ROM 502b which stores programs and the like, and a sub-RAM 502c which functions as a work area, and controls the performance, in particular, based on commands from the main control board 500. Similarly to the main RAM 500c, the sub-RAM 502c is also connected to a backup power supply (not shown), so that data is retained without being erased even if the power supply is cut off. Similarly to the main control board 500, the sub-control board 502 is also provided with a random number generator (random number generating means) 502d, and the random numbers generated by the random number generator 502d (hereinafter referred to as performance lottery random numbers) are mainly used to determine the mode of the performance.

In addition, the sub-control board 502 has functional units such as an initialization determination means 630, a command receiving means 632, and a performance control means 634, which function in cooperation with the sub-RAM 502c based on the program stored in the sub-ROM 502b.

The initialization determination means 630 executes the initialization process in the sub-control board 502. The command receiving means 632 receives commands from other control boards such as the main control board 500, and processes the commands. The performance control means 634 receives a detection signal from the performance switch 422, and determines the performance of the game performed by each device of the liquid crystal display unit 424, the speaker 428, and the performance lamp 426 based on the received command. Specifically, the performance control means 634 determines image data to be displayed on the liquid crystal display unit 424, lighting data for the performance through lighting devices such as the performance lamp 426, the sub-credit display unit 434, and the sub-payout display unit 436, and determines audio data constituting the sound to be output from the speaker 428. Then, the performance control means 634 executes the performance of the determined game. In addition, the performance also includes auxiliary performance. The auxiliary effect is an effect that notifies the player of the correct operation mode of the stop switches 420a, 420b, and 420c, which is the winning condition for the correct role, when a selected winning type in which a correct role (specific role) and an incorrect role overlap in a winning type lottery is won. This auxiliary effect allows the player to easily display the symbol combination corresponding to the correct role on the pay line A. The performance state in which this auxiliary effect is executed is called an AT (assist time) performance state. In addition, a so-called ART game state in which the AT performance state and an RT (replay time) game state, in which the probability of winning a replay role is high, are carried out in parallel, may also be used.

In the following, notification means managed by boards other than the main control board 500, including the sub-control board 502, such as the LCD display unit 424, performance lamps 426, speaker 428, sub-credit display unit 434, and sub-payout display unit 436, may be referred to as other notification means. In contrast, notification means managed by the main control board 500, such as the main credit display unit 430 and main payout display unit 432, may be referred to as main notification means (instruction monitor). In addition, the main notification means and other notification means capable of executing auxiliary performances may be collectively referred to as auxiliary performance execution means. The performance state control means 614 causes the auxiliary performance execution means to execute the auxiliary performance in the AT performance state.

(Table used in main control board 500)
FIG. 77 is an explanatory diagram for explaining a winning combination, and FIG. 78 and FIG. 79 are explanatory diagrams for explaining a winning type selection table.

As described in detail below, the slot machine 400 has multiple game states and presentation states, and the game states and presentation states are changed according to the progress of the game. In the main control board 500, multiple winning type lottery tables and the like corresponding to the game states managed and controlled by the game state control means 612 are stored in the main ROM 500b. The winning type lottery means 604 extracts the corresponding winning type lottery table from the main ROM 500b according to the current setting value (which indicates the easiness of obtaining a game profit in stages) stored in the main RAM 500c and the current game state, and determines which winning type in the winning type lottery table corresponds to the winning type lottery random number obtained according to the operation signal of the start switch 418 based on the extracted winning type lottery table.

Here, the winning roles that make up the winning types extracted in the winning type lottery table include a replay role, a small role, and a bonus role. A replay role is a role that allows the player to play again without placing a new medal bet when a symbol combination corresponding to the replay role is displayed on the active line A. A small role is a role that allows the player to receive a predetermined number of medals according to the symbol combination when a symbol combination corresponding to the small role is displayed on the active line A. A bonus role is a role that allows the game state managed by the game state control means 612 to transition to a bonus game state (a game state during RBB operation described later) when a symbol combination corresponding to the bonus role is displayed on the active line A.

As shown in FIG. 77, the winning roles in this embodiment include replay roles "Replay 1" to "Replay 7". In addition, the winning roles "Small Role 1" to "Small Role 39" are provided as small roles. In addition, the winning role "RBB" is provided as a bonus role. In FIG. 77, one or more symbols constituting each winning role are associated with the left reel 410a, the center reel 410b, and the right reel 410c.

Here, in this embodiment, when the stop switch 420 is operated by the player, if the symbols constituting the symbol combination corresponding to a possible winning combination are on the active line A, the reel control means 606 performs stop control so that the symbols stop on the active line A. Also, when the stop switch 420 is operated, if the symbols constituting the symbol combination corresponding to a possible winning combination are not on the active line A but are within a range equivalent to four symbol frames in the opposite direction to the rotation direction of the reel 410 (pulling-in range), the reel control means 606 performs stop control so that the number of separated symbols becomes the number of sliding frames, and the symbols constituting the symbol combination corresponding to the winning combination are pulled onto the active line A and then stopped after maintaining rotation for the number of sliding frames. In addition, when there are multiple symbols corresponding to winning combinations that can win prizes on the reel 410 and all of them are within the reel-in range of the reel 410, it is determined which symbol to reel in to the pay line A according to a predetermined priority order, and the stop control is performed so that the prioritized symbol is stopped after maintaining rotation for the number of sliding frames so as to reel in the winning line A. In addition, when the stop switch 420 is pressed, if a symbol constituting a symbol combination corresponding to a winning combination other than a winning combination that can win prizes is on the winning line A, the reel control means 606 also executes a so-called kicking process in parallel to prevent the symbol from stopping on the winning line A. In addition, as described later, when an operation mode (operation order or operation timing) is set as a winning condition for a winning combination included in a winning type, the reel control means 606 controls the stop so that the symbol combination corresponding to the winning combination can be displayed on the winning line A according to the operation mode of the player.

For example, the symbols constituting the symbol combinations corresponding to the winning roles "Replay 1" to "Replay 4", "Small Role 1" to "Small Role 6", and "Small Role 35" to "Small Role 39" are arranged on each reel 410 so that they can always be displayed on the pay line A by the above-mentioned stop control. Such a winning role may be expressed as PB=1. On the other hand, for example, the symbols constituting the symbol combinations corresponding to the winning roles "Replay 5" to "Replay 7", "Small Role 7" to "Small Role 34", and "RBB" are not always arranged on each reel 410 so that they can always be displayed on the pay line A by the above-mentioned stop control, so so-called missed wins may occur. Such a winning role may be expressed as PB≠1.

As shown in Figures 78 and 79, the winning type lottery table divides multiple winning areas, and the winning types that are the subject of the lottery vary depending on each game state, and the presence or absence of non-winning (missing) varies. In Figures 78 and 79, the winning areas (winning types) assigned to each game state (non-internal game state (non-internal), game state while inside RBB (while inside RBB), game state while RBB is operating (RBB operating)) are represented by "◎" or "○", but in reality, a winning type lottery table corresponding to each of the multiple game states is stored in the main ROM 500b. Note that "◎" indicates a winning type that allows the lottery of an advantageous zone for which a lottery for moving to an advantageous zone can be held, and "○" indicates a winning type that does not allow the lottery of moving to an advantageous zone for which a lottery for moving to an advantageous zone cannot be held.

In the winning type lottery table, each partitioned winning area is associated with a predetermined number of entries (winning range value), which is a numerical value indicating the winning range, and a winning type. The total number of entries in all winning areas assigned to each game state is the total number of winning type lottery random numbers (65536). Therefore, the probability of each winning type being determined is the value obtained by dividing the number of entries associated with the winning area by the total number of winning type lottery random numbers. The winning type lottery means 604 sequentially obtains the number of entries from the multiple winning areas in the winning type lottery table starting with the highest number based on the game state at that time, subtracts the number of entries from the winning type lottery random number, and if the value after subtraction is less than 0, the winning type associated with the winning area at that time is the lottery result of the winning type lottery. Also, if the number of entries in all winning areas 1 or more are subtracted from the winning type lottery random number and the value after subtraction is 0 or more, the winning type "miss" of winning area 0 is the lottery result of the winning type lottery.

Here, we will add some details about the winning role "RBB" that constitutes the winning type "RBB". The specified first-class special role RB is a role that increases the number of combinations of symbols related to winning for each specified number, or increases the probability of the condition device related to winning for each specified number activating, and is activated in a predetermined case and can continue to operate until the result of the game is obtained not more than 12 times. Here, the condition device is a device whose operation is a necessary condition for the display of a combination of symbols related to winning, replay, the operation of a role, or the operation of a role continuous operation device, and is activated when a winning type lottery (a lottery by a computer performed in the gaming machine) is won, that is, it means a winning flag. And the role continuous operation device related to the first-class special role that constitutes the winning type "RBB" (winning role "RBB") is a device that can continuously operate the first-class special role RB, and is activated when a specific combination of symbols is displayed and ends its operation in a predetermined case.

According to the winning type lottery table in FIG. 78, for example, winning area 0 is associated with the winning type "miss", and when this winning type is won, the symbol combination corresponding to any of the winning roles shown in FIG. 77 will not be displayed on the active line A, and no medals will be paid out. However, as described below, if the RBB internal winning flag is carried over to the next game, winning the winning type "miss" makes it possible to display the symbol combination corresponding to the winning role "RBB" on the active line A.

In addition, winning area 1 is associated with a winning type "small win ALL" which includes overlapping winning roles "small win 1" to "small win 39", winning area 2 is associated with a winning type "1 coin ALLA" which includes overlapping winning roles "small win 11" to "small win 39", and winning area 3 is associated with a winning type "1 coin ALLB" which includes overlapping winning roles "small win 12" to "small win 27". In addition, winning area 4 is associated with a winning type "1 choice 1" which includes the overlapping winning roles "small role 12" and "small role 20", winning area 5 is associated with a winning type "1 choice 2" which includes the overlapping winning roles "small role 13" and "small role 21", winning area 6 is associated with a winning type "1 choice 3" which includes the overlapping winning roles "small role 14" and "small role 22", and winning area 7 is associated with a winning type "1 choice 4" which includes the overlapping winning roles "small role 15" and "small role 23". In addition, the winning area 8 is associated with a winning type "weak cherry" which includes the overlapping winning roles "small role 35" and "small role 36", the winning area 9 is associated with a winning type "strong cherry" which includes the overlapping winning roles "small role 37" to "small role 39", the winning area 10 is associated with a winning type "watermelon A" which includes the overlapping winning roles "small role 7", "small role 8", and "small role 11", the winning area 11 is associated with a winning type "watermelon B" which includes the overlapping winning roles "small role 7" to "small role 10", and the winning area 12 is associated with a winning type "strong bell" which includes the overlapping winning roles "small role 1", "small role 3", and "small role 5". In addition, winning area 13 is associated with a winning type "common bell A" that includes the winning roles "small role 1" to "small role 6" in overlapping fashion, and winning area 14 is associated with a winning type "common bell B" that includes the winning roles "small role 1" to "small role 6" and "small role 11" in overlapping fashion.

In addition, winning regions 15 to 26 are associated with selected winning types (winning types "Batting Order Bell 1A" to "Batting Order Bell 6A" and "Batting Order Bell 1B" to "Batting Order Bell 6B") that overlap correct roles with a payout of 11 coins (winning roles "Small Role 1" to "Small Role 6") and incorrect roles with a payout of 1 coin (winning roles "Small Role 12" to "Small Role 34").

According to the winning type selection table in FIG. 79, winning areas 27 to 39 are associated with winning types "Symbol Replay A1" to "Symbol Replay A7" and "Symbol Replay B1" to "Symbol Replay B6", which include overlapping winning roles "Replay 1" to "Replay 7". Furthermore, winning area 40 is associated with the winning type "Normal Replay", which includes overlapping winning roles "Replay 1" and "Replay 2".

In addition, winning regions 41 to 46 are associated with winning types "RBB1" to "RBB6" that include the winning combination "RBB" alone or in combination with other minor combinations.

When a winning type that includes multiple overlapping winning combinations is won, the winning conditions for which symbol combination corresponding to each winning combination is preferentially displayed on the pay line A are set, for example, the order in which the stop switches 420a, 420b, and 420c are operated.

In the following description, the operation of the stop switches 420a, 420b, and 420c that stop the reels in the order of left reel 410a, center reel 410b, and right reel 410c is referred to as "batting order 1", the operation of the stop switches 420a, 420b, and 420c that stop the reels in the order of left reel 410a, right reel 410c, and center reel 410b is referred to as "batting order 2", and the operation of the stop switches 420a, 420b, and 420c that stop the reels in the order of center reel 410b, left reel 410a, and right reel 410c is referred to as "batting order 3". " The operation of the stop switches 420a, 420b, 420c that stop the reels in the order of center reel 410b, right reel 410c, and left reel 410a is "batting order 4", the operation of the stop switches 420a, 420b, 420c that stop the reels in the order of right reel 410c, left reel 410a, and center reel 410b is "batting order 5", and the operation of the stop switches 420a, 420b, 420c that stop the reels in the order of right reel 410c, center reel 410b, and left reel 410a is "batting order 6".

For example, in a non-internal game state, when the winning type "batting order bell 1A" in the winning area 15 is won and an operation is performed according to the correct operation mode (batting order 1), the stop control is performed so that the symbol combination corresponding to the winning role "small role 1", which is a correct role with a payout of 11 coins, is preferentially displayed on the valid line A. Also, when an operation is performed according to batting order 2, the stop control is performed so that the symbol combination corresponding to the winning role "small role 28", which is an incorrect role with a payout of 1 coin, is preferentially displayed on the valid line A. When an operation is performed according to batting orders 3 and 4, the stop control is performed so that the symbol combination corresponding to the winning role "small role 12", which is an incorrect role with a payout of 1 coin, is preferentially displayed on the valid line A with a probability of 1/4. When an operation is performed according to batting orders 5 and 6, the stop control is performed so that the symbol combination corresponding to the winning role "small role 16", which is an incorrect role with a payout of 1 coin, is preferentially displayed on the valid line A with a probability of 1/4.

The probability of winning (number of pieces placed) for each winning type in winning areas 15-26 is set to be equal. Since players usually cannot know which winning type they have won, providing winning areas 15-26 as described above makes it difficult for correct combinations to win. Also, as described above, even if stop switches 420a, 420b, 420c are operated in a hitting order that prioritizes the display of incorrect combinations, it is not necessarily possible to display the symbol combination corresponding to the incorrect combination on the pay line A, so depending on the manner of operation, a miss may occur (PB ≠ 1).

When any of the above winning types is won, the internal winning flag corresponding to the winning type is established (ON), and the stop control of each reel 410 is performed according to the establishment status of the internal winning flag. At this time, if a winning type including a small role is won, but the symbol combination corresponding to the winning role cannot be displayed on the active line A during the game, the internal winning flag is turned OFF after the game ends. In other words, the right to win a small role is limited only to the game in which the winning type including a small role is won, and the right cannot be carried over to the next game. On the other hand, when a winning type including the winning role "RBB" is won, the RBB internal winning flag is established (ON), and the RBB internal winning flag is carried over across games until the symbol combination corresponding to the winning role "RBB" is displayed on the active line A. In addition, when an internal win flag corresponding to a win type that includes a replay role is established, a symbol combination corresponding to one of the replay roles included in that win type is always displayed on the active line A, and after the processing required to play the next game without requiring a medal is performed, the internal win flag is turned OFF.

(Game state transition)
Here, the transition of the game state will be explained using FIG. 80. Here, a plurality of game states are prepared, such as a non-internal game state, an internal RBB game state, and an RBB operation game state. As described later, each game state is transitioned according to the winning of a bonus role, winning (operation), and ending.

The non-internal game state is a game state that corresponds to the initial state among multiple game states. In such a non-internal game state, the probability of winning a replay role is set to approximately 1/7.3. In addition, in the non-internal game state, the winning role "RBB" is determined with a predetermined probability (for example, approximately 1/30).

The game state control means 612 transitions the game state in response to the winning combination "RBB". For example, in a game in which the winning combination "RBB" is won, when a symbol combination corresponding to the winning combination "RBB" is displayed on the active line A, the game state control means 612 transitions the game state to a game state in which RBB is active (1).

In the RBB-activated game state, the probability of winning a replay role is set to 0. In this RBB-activated game state, the possible winning types are set as "small role ALL" in the winning area 1, and "1-piece ALLA" and "1-piece ALLB" in the winning areas 2 and 3. When the "small role ALL" winning type is won, a symbol combination corresponding to one of the winning roles "small role 1" to "small role 39" is displayed on the active line A, and when the "1-piece ALL" winning type is won, the game is stopped and controlled so that a symbol combination corresponding to one of the winning roles "small role 11" to "small role 39" is displayed on the active line A. Here, the expected number of coins per unit of play in the RBB-activated game state is lowered by the configuration of the small roles.

When the conditions for terminating the RBB-operated game state are met, i.e., when the number of coins won reaches a predetermined number, the game state control means 612 transitions the game state to a non-internal game state (2).

On the other hand, in a game in which the winning combination "RBB" is won, if the symbol combination corresponding to the winning combination "RBB" cannot be displayed on the active line A, the game state control means 612 transitions the game state to an RBB internal game state (special game state) (3).

In the RBB internal game state, the probability of winning a replay role is set to approximately 1/5.9. Also, in the RBB internal game state, the winning type "miss" cannot be won. In other words, if the symbol combination corresponding to the winning role "RBB" cannot be displayed on the active line A in the winning game of the winning role "RBB", the symbol combination corresponding to the winning role "RBB" cannot be displayed on the active line A after that, since the minor role and the replay role are controlled to stop on the active line A in priority to the winning role "RBB". Therefore, once the game state transitions to the RBB internal game state, the RBB internal game state is maintained without any transition of the game state. Here, while maintaining such an RBB internal game state, the AT performance state is realized in the RBB internal game state.

Here, in the RBB internal game state, multiple types of correct roles are won without overlapping with each other, so the chances of winning a correct role can be increased, and as a result, for example, by performing an auxiliary performance in the AT performance state in the RBB internal game state, medals can be easily won. On the other hand, in the RBB operation game state, multiple types of correct roles are won in overlapping, so there are fewer chances of winning a correct role, and therefore there are fewer chances of winning a correct role than in the AT performance state in other game states, making it difficult for the player to increase the medals he owns. Therefore, it is possible to realize a specification (accelerator RBB) in which the RBB operation game state is inferior to the RBB internal game state in terms of medal winning performance, while having the function of the RBB operation game state in which the winning role related to winning is higher than in the RBB internal game state.

(Transition of performance state)
81 is an explanatory diagram for explaining the transition of the presentation state. Below, the presentation state (non-AT presentation state, AT presentation state) that is transitioned by the presentation state control means 614 in the main control board 500 will be described in detail. In addition, the following will explain the case where the game state is the game state inside the RBB.

Here, in order to comprehensively and uniformly determine whether or not the game state with high medal acquisition performance is biased, a game area that has a performance related to the instruction function, that is, a game area that is advantageous to the player, including a game area that executes an auxiliary performance (instruction function), is defined as an advantageous area (specific area). Note that the advantageous area is a game area in which instruction information may be sent to a peripheral board such as the sub-control board 502 only when the instruction content is displayed on the main notification means, for example, so that the main control board 500 can identify the instruction content when the auxiliary performance is activated as a result of a lottery or the like related to the activation of the auxiliary performance on the main control board 500. In addition, a game area different from the advantageous area is defined as a non-advantageous area. Therefore, multiple performance states (non-AT performance state, AT performance state) belong to either the advantageous area or the non-advantageous area, which are game areas. In this embodiment, almost all performance states belong to the advantageous area, and a non-advantageous area is realized in some performance states of the non-AT performance state (here, the non-advantageous performance state).

In addition, in the advantageous zone, among the winning modes in which the correct combination would be missed without the auxiliary effect, in the selected winning type in which the payout for the correct combination is the maximum (here, 11 coins), when an auxiliary effect that assists in winning the correct combination (an auxiliary effect that can obtain the maximum payout number) is performed, this must be notified, for example, by lighting up the zone indicator 460.

In addition, in non-advantageous zones, the probability of winning a type of win can be made different for each setting value, but the probability of deciding to transition to a presentation state with auxiliary effects (AT presentation state) for the same winning type must not be made different for each setting value. On the other hand, in advantageous zones, both the probability of winning a type of win and the probability of deciding to transition (or add) to a presentation state with auxiliary effects (AT presentation state) for the same winning type can be made different for each setting value.

Therefore, the presentation state control means 614 manages the transition of the presentation state, as well as the transition between the non-advantageous zone and the advantageous zone. Regardless of this management, the advantageous zone is forcibly terminated when the following termination conditions are met. For example, the zone is forcibly terminated when the value counted in the advantageous zone reaches a predetermined value (for example, the number of games played during the zone (number of games played) reaches 1,500 games, or the number of coins won (net increase in number of coins) exceeds 2,400). In either case, the presentation state control means 614 resets all information updated in the advantageous zone (all variables that affect the performance related to the instruction function) by transitioning from the advantageous zone to the non-advantageous zone.

(Non-AT performance state, AT performance state)
In the non-AT performance state, the frequency of execution of the auxiliary performance is extremely low compared to the AT performance state, and the auxiliary performance is almost not performed, so the number of medals that can be acquired is limited. Here, six performance states are provided as the non-AT performance state, such as a normal performance state, a non-advantageous performance state, a preparation performance state, a first interval performance state, a continuous lottery performance state, and a second interval performance state.

In the AT performance state, by having the auxiliary performance execution means execute the auxiliary performance when all selected winning types are won, it is possible to win many medals while reducing medal consumption. Therefore, by transitioning to the AT performance state, the player can play more advantageously than in a non-AT performance state. Here, a pseudo bonus performance state is provided as the AT performance state. Each performance state (normal performance state, pseudo bonus performance state, non-advantageous performance state, preparation performance state, first interval performance state, continuous lottery performance state, second interval performance state) will be explained individually below.

(Each performance state)
The normal presentation state is a presentation state corresponding to the initial state among a plurality of presentation states. The presentation state control means 614 performs an AT lottery in the normal presentation state. The AT lottery is a lottery that determines the transition to the AT presentation state, and the presentation state control means 614 performs an AT lottery with a different probability for each winning type determined by the winning type lottery. Then, when the AT lottery is won, the presentation state control means 614 transitions the presentation state to a pseudo bonus presentation state, which is an AT presentation state, after a predetermined number of premonition games have elapsed (1). Also, when a predetermined ceiling condition (for example, a predetermined number of games are played continuously in the normal presentation state) is satisfied in the normal presentation state without transitioning to the pseudo bonus presentation state (so-called reaching the ceiling), the presentation state control means 614 transitions the presentation state to a pseudo bonus presentation state (1).

In the pseudo bonus presentation state, the auxiliary presentation is executed until a predetermined end condition (for example, the number of games played reaches a predetermined number of games) is met, and the player can obtain, for example, 3.5 expected coins in the pseudo bonus presentation state. In the pseudo bonus presentation state, two main end conditions are prepared. For example, if the end condition is that the number of games played reaches a predetermined number of games, two stages are set as the predetermined number of games, 30 and 80, and one of them is determined by lottery. In the pseudo bonus presentation state, the more games played, the more gaming profits the player will obtain. Therefore, the player will want the predetermined number of games to be 80, not 30. However, even if 30 is determined as the predetermined number of games, a promotion lottery is also held to increase the predetermined number of games of the auxiliary presentation from 30 to 80 during the number of games. Note that, in this example, the condition for ending the pseudo bonus presentation state is that the number of plays played reaches a predetermined number of plays, but instead, it may be that the number of times the auxiliary presentation that can win the maximum payout number reaches a predetermined number, or that the number of coins won (net increase in number of coins) reaches a predetermined number.

When a predetermined end condition is satisfied in the pseudo-bonus presentation state, the presentation state control means 614 may transition the presentation state to a non-advantageous presentation state (2). At this time, the presentation state control means 614 transitions the advantageous section to a non-advantageous section once, and resets all information updated in the advantageous section. For example, if the previous pseudo-bonus presentation state was the first pseudo-bonus presentation state, that is, if it is a pseudo-bonus presentation state immediately after transition from a normal presentation state, the presentation state control means 614 transitions the presentation state to a non-advantageous presentation state and transitions the advantageous section to a non-advantageous section once. Also, if the previous pseudo-bonus presentation state was a pseudo-bonus presentation state that is a multiple of three (3rd, 6th, ...) without passing through the normal presentation state, the presentation state control means 614 transitions the advantageous section to a non-advantageous section once, and transitions the advantageous section to a non-advantageous section once.

Then, the presentation state control means 614 draws a lottery for a transition to the advantageous zone with a high probability (for example, 1/2), and after the number play is completed, returns to the advantageous zone and transitions the presentation state to the preparation presentation state (3). This is to avoid the pseudo bonus presentation state being forcibly terminated when the value counted in the advantageous zone reaches a predetermined value.

On the other hand, if the previous pseudo-bonus presentation state is not the first time, or is not a pseudo-bonus presentation state that is a multiple of three and does not pass through a normal presentation state, the presentation state control means 614 transitions the presentation state directly to the preparation presentation state without transitioning to a non-advantageous presentation state (4). This is to avoid the pseudo-bonus presentation state being forcibly terminated when the value counted in the advantageous zone reaches a predetermined value, while also preventing the advantageous zone from being terminated unnecessarily.

In the preparation performance state, the performance state control means 614 draws a lottery for transition to the first interval performance state with a high probability (e.g., 1/2), and transitions the performance state to the first interval performance state based on the decision to transition to the first interval performance state (5).

The first interval presentation state continues until a predetermined end condition (for example, 40 plays are played) is met, during which time a lottery is held to continue the pseudo bonus presentation state. Unlike the pseudo bonus presentation state, the first interval presentation state has a smaller expected number of coins per unit play, and may even be a negative value. In this embodiment, if a favorable zone is won in a non-favorable zone, the presentation state is set to always become the first interval presentation state. Therefore, after the pseudo bonus presentation state ends, the presentation state will transition to the first interval presentation state even if the favorable zone continues, or even if the zone transitions to a non-favorable zone as described above. Then, when a predetermined end condition in the first interval presentation state is met, the presentation state control means 614 transitions the presentation state to a continuation lottery presentation state (6).

The continuation lottery presentation state continues until a predetermined end condition (e.g., five plays are completed) is met, and finally, the result of the lottery for continuing the pseudo bonus presentation state in the first interval presentation state is announced. Unlike the pseudo bonus presentation state, the continuation lottery presentation state also has a small expected number of coins to be won per unit play in this continuation lottery presentation state, and may even be a negative value. If a transition (continuation) to the pseudo bonus presentation state has been determined in the first interval presentation state, the presentation state control means 614 transitions the presentation state to the pseudo bonus presentation state (7), and if a transition to the pseudo bonus presentation state has not been determined, the presentation state control means 614 returns the presentation state to the normal presentation state (8).

In this way, in this embodiment, once the pseudo bonus presentation state is entered, the player can accumulate medals by repeating the transition from the pseudo bonus presentation state → preparation presentation state → first interval presentation state → continuation selection presentation state, unless the player misses the continuation selection selection state.

In addition, in the preparation performance state, the performance state control means 614 draws a lottery for transition to the second interval performance state in addition to drawing a lottery for transition to the first interval performance state. However, the probability of transition to the second interval performance state (e.g., 1/20) is set smaller than the probability of transition to the first interval performance state (e.g., 1/2). In the preparation performance state, if a transition to the second interval performance state is determined before a transition to the first interval performance state is determined, the performance state control means 614 transitions the performance state to the second interval performance state based on the decision to transition to the second interval performance state (9). Note that, although an example of drawing a lottery for transition to the second interval performance state in the preparation performance state is given here, a lottery for transition to the second interval performance state may also be drawn in a non-advantageous performance state in a similar manner.

The second interval presentation state, like the first interval presentation state, continues until a predetermined end condition (e.g., 40 plays are played) is met, during which time a lottery is held to continue the pseudo bonus presentation state. Like the first interval presentation state, the second interval presentation state differs from the pseudo bonus presentation state in that the expected number of coins to be won per unit of play is small, and may even be a negative value.

However, the pseudo bonus presentation state is determined with a higher probability in the second interval presentation state than in the first interval presentation state. For example, in the first interval presentation state, the pseudo bonus presentation state is determined every 1/58 of a game for 40 games (50% chance of winning), and in the second interval presentation state, the pseudo bonus presentation state is determined every 1/25 of a game for 40 games (80% chance of winning). Then, when a predetermined end condition is met, the presentation state control means 614 transitions the presentation state to a continuous lottery presentation state (10). Once the transition to the second interval presentation state is determined, thereafter, there will be no transition to a non-advantageous presentation state, preparation presentation state, or first interval presentation state until the continuous lottery presentation state is missed, and the pseudo bonus presentation state will only transition to the second interval presentation state (11). Therefore, the player can always receive a continuation lottery with a high probability. In addition, once a transition to the second interval presentation state is determined, even if a transition to the pseudo bonus presentation state is not determined in the continuous lottery presentation state, the presentation state control means 614 immediately transitions the presentation state to a non-advantageous presentation state without returning the presentation state to the normal presentation state (12). Therefore, if a transition to the pseudo bonus presentation state is not determined in the continuous lottery presentation state, the transition from the pseudo bonus presentation state to the preparation presentation state to the first interval presentation state to the continuous lottery presentation state can be repeated until the continuation lottery for the continuous lottery presentation state is missed again. In this way, once a transition to the second interval presentation state is made, the transition from the pseudo bonus presentation state to the second interval presentation state to the continuous lottery presentation state can be repeated with a high probability, and further, even if a transition to the pseudo bonus presentation state is not determined in the continuous lottery presentation state, the transition from the pseudo bonus presentation state to the preparation presentation state to the first interval presentation state to the continuous lottery presentation state can at least be repeated again, so that the player can accumulate more medals. In other words, the second interval presentation state can be said to be a more advantageous state than the first interval presentation state.

As described above, when transitioning from the pseudo bonus presentation state to the second interval presentation state, the presentation state control means 614 does not transition to a non-advantageous zone, unlike the transition to the first interval presentation state. In this embodiment, if the pseudo bonus presentation state is the initial pseudo bonus presentation state, the presentation state control means 614 does not transition to the second interval presentation state, but transitions the advantageous zone to a non-advantageous zone once, and always transitions to the first interval presentation state. In this way, the advantageous zone is reset once. Therefore, even if the advantageous zone is not reset when transitioning to the second interval presentation state, the pseudo bonus presentation state that passes through the second interval presentation state will not end in a short period due to the limitation of the advantageous zone, and the player can obtain many medals by looping the pseudo bonus presentation state → second interval presentation state → continuous lottery presentation state.

The specific processing on the main control board 500 and the sub-control board 502 is explained below based on the flowchart.

(CPU Initialization Processing of Main Control Board 500)
82 is a flowchart explaining the CPU initialization process in the main control board 500. When power is supplied from the power supply board, a system reset occurs in the main CPU 500a, and the main CPU 500a performs the following CPU initialization process (S2000).

(Step S2000-1)
When the power is turned on, the main CPU 500a reads a startup program from the main ROM 500b as an initial setting process, and performs setting processes required for executing various processes.

(Step S2000-3)
The main CPU 500a sets a wait processing time in a timer counter.

(Step S2000-5)
The main CPU 500a judges whether a power-off warning signal has been detected. The main control board 500 is provided with a power-off detection circuit, which outputs a power-off warning signal when the power supply voltage falls below a predetermined value. If a power-off warning signal has been detected, the process proceeds to step S2000-3, and if a power-off warning signal has not been detected, the process proceeds to step S2000-7.

(Step S2000-7)
The main CPU 500a judges whether the wait processing time set in step S2000-3 has elapsed or not. If it is judged that the wait processing time has elapsed, the process proceeds to step S2000-9, and if it is judged that the wait time has not elapsed, the process proceeds to step S2000-5.

(Step S2000-9)
The main CPU 500a executes the processes required to permit access to the main RAM 500c.

(Step S2000-11)
The main CPU 500a executes a checksum confirmation process. Here, the main CPU 500a calculates a checksum and judges whether the calculated checksum does not match the checksum saved at the time of power off (is abnormal) and whether the backup is abnormal. If the main CPU 500a judges that either or both of the backup and the checksum are abnormal, it turns on the backup abnormality flag, and if it judges that neither the backup nor the checksum are abnormal, it turns off the backup abnormality flag.

(Step S2000-13)
The main CPU 500a determines whether the backup abnormality flag is on. If it is determined that the backup abnormality flag is on, the process proceeds to step S2010, and if it is determined that the backup abnormality flag is not on, the process proceeds to step S2020.

(Step S2010)
The main CPU 500a executes a cold start process, which will be described later.

(Step S2020)
The main CPU 500a executes a setting value switching process for switching the setting value, which will be described later.

(Step S2030)
The main CPU 500a executes a state restoration process to restore the state immediately before the power was turned off, as will be described later.

Figure 83 is a flowchart explaining the cold start processing (S2010) in the main control board 500.

(Step S2010-1)
The main CPU 500a clears the used area in the main RAM 500c and executes a used area RAM check process to detect any abnormalities in the used area.

(Step S2010-3)
The main CPU 500a clears the separate area (unused area) in the main RAM 500c and executes a separate area RAM check process to detect an abnormality in the separate area. If an abnormality is detected in the separate area in the separate area RAM check process, the main CPU 500a turns on a RAM read/write error flag.

(Step S2010-5)
The main CPU 500a sets an error code "EA" indicating an abnormality in the main RAM 500c.

(Step S2010-7)
The main CPU 500a judges whether an abnormality has been detected in the above step S2010-1. If it is judged that an abnormality has been detected in the above step S2010-1, the process proceeds to step S2011, and if it is judged that an abnormality has not been detected in the above step S2010-1, the process proceeds to step S2010-9.

(Step S2010-9)
The main CPU 500a acquires a RAM read/write error flag that is turned on when an abnormality is detected in step S2010-3.

(Step S2010-11)
The main CPU 500a judges whether the RAM read/write error flag is on. If it is judged that the RAM read/write error flag is on, the process proceeds to step S2011, and if it is judged that the RAM read/write error flag is not on, the process proceeds to step S2020.

(Step S2020)
The main CPU 500a executes a setting value switching process for switching the setting value, which will be described later.

(Step S2010-13)
The main CPU 500a sets an error code "E7" indicating a backup error.

(Step S2011)
The main CPU 500a executes an error stop process for stopping the progress of the game due to an error, which will be described later.

Figure 84 is a flowchart explaining the error stop processing (S2011) in the main control board 500.

(Step S2011-1)
The main CPU 500a sets an initial stack pointer value as the address of the stack pointer.

(Step S2011-3)
The main CPU 500a executes an error setting process for displaying an error and setting an alarm sound.

(Step S2011-5)
The main CPU 500a sets the external signal 1-3 output bit OFF, which turns off the output image of the bits corresponding to the external signals 1-3.

(Step S2011-7)
The main CPU 500a executes an output port image set process to update the output image for the bit set in step S2011-5.

(Step S2011-9)
The main CPU 500a goes into a permanent loop, which stops the progress of the game.

Figure 85 is a flowchart explaining the setting value switching process (S2020) in the main control board 500.

(Step S2020-1)
The main CPU 500a acquires a signal from the input port 1, and judges whether the setting value switching condition is satisfied based on the acquired signal from the input port 1. As a result, if it is judged that the setting value switching condition is not satisfied, the setting value switching process is terminated, and if it is judged that the setting value switching condition is satisfied, the process proceeds to step S2020-3. Here, the signal from the input port 1 includes a signal indicating whether the front upper door 404 and the front lower door 406 are opened or not, and a signal indicating whether the setting door key is turned on or not. Here, it is judged that the setting value switching condition is satisfied when a signal indicating that the front upper door 404 and the front lower door 406 are opened and a signal indicating that the setting door key is turned on are acquired.

(Step S2020-3)
The main CPU 500a executes a RAM clear process to clear areas in the main RAM 500c that should be cleared when the settings are changed.

(Step S2020-5)
The main CPU 500a executes a table content setting process for transferring the table data of the setting value switching data table to the main RAM 500c.

(Step S2020-7)
The main CPU 500a sets in the transmission buffer a setting change start command, which indicates the start of changing the setting value.

(Step S2020-9)
The main CPU 500a executes edge check processing to detect the rising edge (on edge) and falling edge (off edge) of the signal at the input port.

(Step S2020-11)
The main CPU 500a obtains setting value data indicating the current setting value.

(Step S2020-13)
The main CPU 500a judges whether the on-edge of the setting change switch has been detected in the above step S2020-9. If it is judged that the on-edge of the setting change switch has not been detected, the process proceeds to step S2020-17, and if it is judged that the on-edge of the setting change switch has been detected, the process proceeds to step S2020-15.

(Step S2020-15)
The main CPU 500a increments the setting value data by one.

(Step S2020-17)
The main CPU 500a judges whether the set value data is within the range (1 to 6) that can be set as a set value. If it is judged that the set value data is within the range, the process proceeds to step S2020-21, and if it is judged that the set value data is not within the range, the process proceeds to step S2020-19.

(Step S2020-19)
The main CPU 500a sets the setting value data to 0.

(Step S2020-21)
The main CPU 500a updates the setting value data to the value incremented or set in step S2020-15 or step S2020-19.

(Step S2020-23)
The main CPU 500 a executes a display data conversion process for displaying the set value in the main credit display section 430 .

(Step S2020-25)
The main CPU 500a judges whether the on-edge of the setting change switch is detected. If it is judged that the on-edge of the setting change switch is not detected, the process proceeds to step S2020-31, and if it is judged that the on-edge of the setting change switch is detected, the process proceeds to step S2020-27.

(Step S2020-27)
The main CPU 500a judges whether the setting change switch is on. If it is judged that the setting change switch is on, the process proceeds to step S2020-27, and if it is judged that the setting change switch is not on, the process proceeds to step S2020-29.

(Step S2020-29)
The main CPU 500a sets a setting change switch interval timer.

(Step S2020-31)
The main CPU 500a executes a timer wait process to wait until the setting change switch interval timer counts down to 0.

(Step S2020-33)
The main CPU 500a judges whether it has detected an on-edge of the start switch 418. As a result, if it is judged that an on-edge of the start switch 418 has not been detected, the process proceeds to step S2020-9, and if it is judged that an on-edge of the start switch 418 has been detected, the process proceeds to step S2020-35.

(Step S2020-35)
The main CPU 500a judges whether the set door key is OFF. If it is judged that the set door key is OFF, the process proceeds to step S2020-35, and if it is judged that the set door key is not OFF, the process proceeds to step S2020-37.

(Step S2020-37)
The main CPU 500a judges whether the set door key is on. If it is judged that the set door key is on, the process proceeds to step S2020-37, and if it is judged that the set door key is not on, the process proceeds to step S2021.

(Step S2021)
The main CPU 500a executes an initialization start process to start the initialization start, which will be described later.

Figure 86 is a flowchart explaining the initialization start process (S2021) in the main control board 500.

(Step S2021-1)
The main CPU 500a sets in the transmission buffer a setting change end command indicating that the change of the setting value has been completed.

(Step S2021-3)
The main CPU 500a sets in the transmission buffer a setting change state command indicating the state when the setting value change is completed.

(Step S2021-5)
The main CPU 500a sets a wait timer at the start of initialization.

(Step S2021-7)
The main CPU 500a executes a timer wait process to wait until the wait timer reaches 0 at the start of initialization.

(Step S2021-9)
The main CPU 500a executes a setting change RAM clear process to clear a separate area of the main RAM 500c.

(Step S2021-11)
The main CPU 500a executes a RAM clear process to clear areas in the main RAM 500c that should be cleared when the settings are changed.

(Step S2021-13)
The main CPU 500a sets a game status command indicating the current game status in a transmission buffer.

(Step S2100)
The main CPU 500a executes a game start process to start a game, which will be described later.

Figure 87 is a flowchart explaining the state restoration process (S2030) in the main control board 500.

(Step S2030-1)
The main CPU 500a restores the stack pointer.

(Step S2030-3)
The main CPU 500a executes an unused area clearing process to clear unused areas in the main RAM 500c.

(Step S2030-5)
The main CPU 500a clears the stack pointer storage buffer.

(Step S2030-7)
The main CPU 500a sets (ON) the post-power-off recovery flag.

(Step S2030-9)
The main CPU 500a executes a port input process to update the image of the input port.

(Step S2030-11)
The main CPU 500a executes an operation target bit extraction process for extracting information on the operation target bit based on the image of the input port updated in step S2030-9.

(Step S2030-13)
The main CPU 500a sets the operation target bit extracted in step S2030-11 as the operation target bit of the previous state.

(Step S2030-15)
The main CPU 500a acquires the motor phases of the reels 410a, 410b, and 410c. Here, the motor phase is set as the state of the reels 410a, 410b, and 410c. The motor phase indicates the operation state of the reels 410a, 410b, and 410c, i.e., accelerating, rotating steadily, stopped, and waiting. Specifically, a variable of 1 byte (storage unit) assigned to the motor phase changes to a value such as accelerating = 3, rotating steadily = 2, stopped = 1, and waiting = 0 according to the operation state of the stepping motor 452.

(Step S2030-17)
The main CPU 500a determines whether any of the reels 410a, 410b, 410c are rotating steadily or accelerating based on the motor phase acquired in step S2030-15. If it is determined that any of the reels 410a, 410b, 410c are not rotating steadily or accelerating, the process proceeds to step S2030-21, and if it is determined that any of the reels 410a, 410b, 410c are rotating steadily or accelerating, the process proceeds to step S2030-19.

(Step S2030-19)
The main CPU 500a executes a rotation error process that performs settings when an error is detected in the reels 410a, 410b, and 410c.

(Step S2030-21)
The main CPU 500a restores the saved register group.

(Step S2030-23)
The main CPU 500a then permits the interrupt and ends the state restoration process, thereby restoring the main CPU 500a to the state it was in immediately before the power was turned off.

Figure 88 is a flowchart explaining the game start processing (S2100) on the main control board 500.

(Step S2100-1)
The main CPU 500a executes a re-play state identification signal output setting process for outputting a re-play state identification signal indicating whether or not a re-play is being performed.

(Step S2100-3)
The main CPU 500a sets an inserted number indicator output bit OFF to turn off (light off) the bit corresponding to the inserted number indicator that displays the number of inserted medals (number of bets).

(Step S2100-5)
The main CPU 500a executes an output port image set process to update the output image for the bit set in step S2100-3.

(Step S2100-7)
The main CPU 500a sets a game start wait timer.

(Step S2100-9)
The main CPU 500a executes a timer wait process to wait until the game start wait timer counts down to 0.

(Step S2100-11)
The main CPU 500a executes a one-game RAM clear process to clear an area in the main RAM 500c that should be cleared for each game.

(Step S2100-13)
The main CPU 500a executes a bonus signal setting process for setting a bonus signal.

(Step S2100-15)
The main CPU 500a executes an edge clear process to clear edge information of the input port image.

(Step S2200)
The main CPU 500a executes a medal insertion process for receiving insertion of medals, which will be described later.

Figure 89 is a flowchart explaining the medal insertion process (S2200) on the main control board 500.

(Step S2200-1)
The main CPU 500a executes an error checking process to check the detection results of various errors.

(Step S2200-3)
The main CPU 500a executes edge check processing to detect the rising edge (on edge) and falling edge (off edge) of the signal at the input port.

(Step S2200-5)
The main CPU 500a acquires a door open error detection flag that is set to 1 when the front upper door 404 or the front lower door 406 is open.

(Step S2200-7)
The main CPU 500a judges whether the front upper door 404 and the front lower door 406 are closed based on the door open error detection flag acquired in the above step S2200-5. If it is judged that the front upper door 404 and the front lower door 406 are closed, the process proceeds to step S2200-17, and if it is judged that at least one of the front upper door 404 and the front lower door 406 is not closed, the process proceeds to step S2200-9.

(Step S2200-9)
The main CPU 500a sets an error code "E8" which indicates that at least one of the front upper door 404 or the front lower door 406 is open.

(Step S2200-11)
The main CPU 500a executes an error wait process to display an error, request an alarm sound, and wait for recovery from the error.

(Step S2200-13)
The main CPU 500a executes a setting value confirmation process to confirm the setting value.

(Step S2200-15)
The main CPU 500a executes an edge clear process to clear edge information of the input port image.

(Step S2200-17)
When a credit switch (not shown) for paying back accumulated (credited) medals is pressed, the main CPU 500a executes a credit button check process for paying back the accumulated medals.

(Step S2200-19)
The main CPU 500a executes a process related to the medal insertion button for betting medals. When the bet switch 416 is pressed, the reserved (credited) medals are bet up to a specified number, and the number of reserved medals is subtracted by the number of medals bet. When medals are inserted through the medal insertion slot 414a, medals are bet up to a specified number, and when more medals are inserted than the specified number, the number of medals is added to the number of reserved medals.

(Step S2200-21)
The main CPU 500a executes a medal acquisition process to check whether the number of inserted medals is a specified number.

(Step S2200-23)
The main CPU 500a judges whether the number of inserted coins is equal to the specified number based on the result of the check in step S2200-21. If the number of inserted coins is equal to the specified number, the process proceeds to step S2200-1. If the number of inserted coins is equal to the specified number, the process proceeds to step S2200-25.

(Step S2200-25)
The main CPU 500a sets a start indicator output bit for turning on (illuminating) a start indicator (not shown) which indicates whether or not the operation of the start switch 418 has been validated.

(Step S2200-27)
The main CPU 500a judges whether or not it has detected a falling edge (pressing) of the start switch 418. As a result, if it is judged that the falling edge of the start switch 418 has not been detected, the process proceeds to step S2200-1, and if it is judged that the falling edge of the start switch 418 has been detected, the process proceeds to step S2200-29.

(Step S2200-29)
The main CPU 500a clears the main payout display section buffer to clear the display of the main payout display section 432.

(Step S2200-31)
The main CPU 500a executes a re-play state identification signal clearing process for clearing the re-play state identification signal.

(Step S2200-33)
The main CPU 500a executes blocker blocking pre-processing to turn off (extinguish) the start indicator.

(Step S2200-35)
The main CPU 500a sets a lever press command, which indicates that the start switch 418 has been pressed, in the transmission buffer.

(Step S2300)
The main CPU 500a executes an internal lottery process for carrying out a lottery for determining the type of winning. This internal lottery process will be described later.

Figure 90 is a flowchart explaining the internal lottery process (S2300) in the main control board 500.

(Step S2300-1)
The main CPU 500a acquires the setting value data.

(Step S2300-3)
The main CPU 500a sets an error code "EC" indicating an abnormal setting error.

(Step S2300-5)
The main CPU 500a judges whether the setting value data acquired in step S2300-1 is abnormal. If it is judged that the setting value data is abnormal, the process proceeds to step S2011, and if it is judged that the setting value data is not abnormal, the process proceeds to step S2300-7.

(Step S2300-7)
The main CPU 500a obtains the winning type lottery random number updated by the random number generator 500d.

(Step S2300-9)
The main CPU 500a executes a state offset acquisition process to acquire an offset value related to a game state.

(Step S2300-11)
The main CPU 500a sets the address of the internal lottery area definition table (winning type lottery table).

(Step S2300-13)
The main CPU 500a adds the offset value acquired in step S2300-9 to the address set in step S2300-11, and sets the value indicated by the address as the initial value of the winning area. Here, the first winning area in the winning type lottery table for the current game state is set as the initial value.

(Step S2300-15)
The main CPU 500a acquires lottery data, which is a numerical value indicating the winning range of the winning area, and executes a lottery data acquisition process to shift the winning area by one.

(Step S2300-17)
The main CPU 500a determines whether or not to hold a prize type lottery. If it determines that a prize type lottery will not be held, the process proceeds to step S2300-21. If it determines that a prize type lottery will be held, the process proceeds to step S2300-19.

(Step S2300-19)
The main CPU 500a subtracts the lottery data from the random number value.

(Step S2300-21)
The main CPU 500a judges whether the subtraction result in step S2300-19 is negative, i.e., whether the winning area has been won by the winning type lottery. If it is judged that the winning type lottery has been won, the process proceeds to step S2400, and if it is judged that the winning type lottery has not been won, the process proceeds to step S2300-23.

(Step S2300-23)
The main CPU 500a judges whether the winning type lottery has ended. If it is judged that the winning type lottery has not ended, the process proceeds to step S2300-15, and if it is judged that the winning type lottery has ended, the process proceeds to step S2300-25.

(Step S2300-25)
The main CPU 500a clears the trigger role type.

(Step S2400)
The main CPU 500a executes a symbol code setting process for setting a symbol code based on the winning area and the game state. This symbol code setting process will be described later.

Figure 91 is a flowchart explaining the pattern code setting process (S2400) on the main control board 500.

(Step S2400-1)
The main CPU 500a acquires the winning area acquired in step S2300, and executes a game state setting process to set the game state to an internal game state if the acquired winning area includes a bonus role.

(Step S2400-3)
The main CPU 500a sets the winning area acquired in step S2400-1 as the stop control number.

(Step S2400-5)
The main CPU 500a determines (sets) the type of win based on the win area acquired in step S2400-1.

(Step S2400-7)
The main CPU 500a executes a symbol code initial setting process for setting symbol codes indicating symbols that can be displayed and symbols to be drawn in, based on the stop control number set in step S2400-3.

(Step S2400-9)
The main CPU 500a executes a display symbol bit initial value setting process to set a display symbol bit.

(Step S2400-11)
The main CPU 500a executes an execution flag setting process, which performs various processes related to the performance state, and processes related to auxiliary performance.

(Step S2400-13)
The main CPU 500a sets a presentation command, which is a command related to the advantageous zone, in the transmission buffer.

(Step S2400-15)
The main CPU 500a sets a winning information command indicating the type of winning in the transmission buffer.

(Step S2400-17)
The main CPU 500a checks the one-game timer.

(Step S2400-19)
The main CPU 500a sets a pre-reel spin command, which indicates that the reels 410a, 410b, and 410c have not yet spun, in the transmission buffer.

(Step S2400-21)
The main CPU 500a executes an excitation release waiting process for waiting for the excitation release of the stepping motor 452.

(Step S2400-23)
The main CPU 500a judges whether the 1-game timer is not 0. As a result, if it is judged that the 1-game timer is not 0, the process proceeds to step S2400-23, and if it is judged that the 1-game timer is 0, the process proceeds to step S2400-25.

(Step S2400-25)
The main CPU 500a executes a reel start process for starting the rotation of the reels 410a, 410b, and 410c. Here, the motor phases of the reels 410a, 410b, and 410c are set to accelerating to start the rotation of each reel, and the one-game timer is set to a value equivalent to 4.1 seconds.

(Step S2400-27)
The main CPU 500a sets a reel start command, which indicates that the reels 410a, 410b, and 410c have started to rotate, in the transmission buffer.

(Step S2500)
The main CPU 500a executes a process during the rotation of the reels 410a, 410b, and 410c. This process will be described later.

Figure 92 is a flowchart explaining the processing during reel rotation (S2500) in the main control board 500.

(Step S2500-1)
The main CPU 500a sets the stop indicator output bit off (output image) to turn off (turn off) the bit corresponding to the indicator (not shown) of the stop switches 420a, 420b, 420c. Here, the stop indicator output bit is composed of a bit string of 3 bits, each bit corresponding to the light emission color of the three stop switches 420a, 420b, 420c, respectively, and is represented by blue=1 and red=0.

(Step S2500-3)
The main CPU 500a executes an output port image set process to update the output image for the bit set in step S2500-1 above.

(Step S2500-5)
The main CPU 500a executes an error checking process to check the detection results of various errors.

(Step S2500-7)
The main CPU 500a refers to the index flag and obtains the index of the spinning reels 410a, 410b, and 410c. Note that the index flag is set only after the reels 410a, 410b, and 410c have reached a constant rotation speed. In other words, the fact that the index flag is set indicates that the reels 410a, 410b, and 410c have reached a constant rotation speed.

(Step S2500-9)
The main CPU 500a judges whether all index flags of the reels 410a, 410b, and 410c have been detected. If it is determined that all index flags have not been detected, the process proceeds to step S2500-1. If it is determined that all index flags have been detected, the process proceeds to step S2500-11.

(Step S2500-11)
The main CPU 500a acquires the stopped reel bit indicating the reels 410a, 410b, and 410c that have stopped or are starting to stop. Here, the stopped reel bit is composed of a bit string of 3 bits, each bit corresponding to one of the three reels 410a, 410b, and 410c, and is represented as a constant speed state = 1, and an accelerating state, decelerating state, or stopped state = 0.

(Step S2500-13)
The main CPU 500a stores the stopped reel bit acquired in step S2500-11 as a reel rotation in progress flag.

(Step S2500-15)
The main CPU 500a sets a stop indicator output bit on (output image) to turn on (turn off) the bit corresponding to the indicator (not shown) of the stop switches 420a, 420b, 420c.

(Step S2500-17)
The main CPU 500a acquires an image of the input port 0, and executes an operation target bit extraction process to extract an operation target bit from the acquired image. Here, the operation target bit is composed of a bit string of 3 bits, each bit corresponding to one of the three stop switches 420a, 420b, 420c, and is represented as 1 if it is operated and 0 if it is not operated.

(Step S2500-19)
The main CPU 500a calculates the logical product of the reel spinning flag acquired in step S2500-13 and the bit to be operated extracted in step S2500-17. If the reel 410 is spinning and the stop switch 420 corresponding to that reel is operated, that is, if the operated stop switch 420 corresponds to the reel 410 that is spinning effectively, the logical product will be 1.

(Step S2500-21)
The main CPU 500a determines whether the logical product calculated in step S2500-19 is 0, i.e., whether the stop switch 420 corresponding to the spinning reel 410 has not been operated. If it is determined that the stop switch 420 corresponding to the spinning reel 410 has not been operated, the process proceeds to step S2500-3, and if it is determined that the stop switch 420 corresponding to the spinning reel 410 has been operated, the process proceeds to step S2500-23.

(Step S2500-23)
The main CPU 500a obtains an output image including the stop indicator output bit, and calculates the logical product of the obtained output image and the logical product calculated in the above step S2500-19. Here, if the operated stop switch 420 is lit in red, the bit of the logical product becomes 0, and if the operated stop switch 420 is lit in blue, the bit of the logical product becomes 1.

(Step S2500-25)
The main CPU 500a judges whether the logical product calculated in the above step S2500-23 is 0, that is, whether the operated stop switch 420 is lit in red. If it is judged that the operated stop switch 420 is lit in red, the process proceeds to step S2500-1, and if it is judged that the operated stop switch 420 is not lit in red, the process proceeds to step S2500-27.

(Step S2500-27)
The main CPU 500a judges whether the operated stop switch 420 is valid. As a result, if it is judged that the operated stop switch 420 is not valid, the process proceeds to step S2500-1, and if it is judged that the operated stop switch 420 is valid, the process proceeds to step S2500-29. Note that here, it is judged whether or not the number of operated stop switches 420 is one. Then, if it is judged that the number of operated stop switches 420 is one, the process proceeds to step S2500-29, and if it is judged that the number of operated stop switches 420 is not one, that is, that there are two or more, the process proceeds to step S2500-1.

(Step S2500-29)
The main CPU 500a executes a stop control reel setting process to acquire various parameters for stopping the reel 410 corresponding to the operated stop switch 420.

(Step S2500-31)
The main CPU 500a disables interrupts.

(Step S2500-33)
The main CPU 500a executes a touch reference position acquisition process to derive the symbol number of the symbol located on the pay line A as the touch reference position.

(Step S2500-35)
The main CPU 500a executes a sliding frame number acquisition process for determining the number of sliding frames on the reel 410.

(Step S2600)
The main CPU 500a executes a reel stop process for stopping the reel 410 corresponding to the operated stop switch 420. This reel stop process will be described later.

Figure 93 is a flowchart explaining the reel stop processing (S2600) in the main control board 500.

(Step S2600-1)
The main CPU 500a obtains the pressed reference position derived in step S2500-35 above.

(Step S2600-3)
The main CPU 500a calculates a stop request number by correcting the number of sliding symbols determined in step S2500-37 above with respect to the pressed reference position acquired in step S2600-1 above.

(Step S2600-5)
The main CPU 500a sets a stop request flag (sets it to 1). The stop request flag is a flag for requesting a program operating in parallel to perform a stop process for the target reel 410, and by setting the stop request flag to 1, it becomes possible to stop the symbol corresponding to the stop request number on the activated line A. The stop request flag and the stop request number are read out by the program operating in parallel, and the reel 410 is stopped. When the stop process is completed, the stop request flag is reset to 0 (OFF) by that program.

(Step S2600-7)
The main CPU 500a permits interrupts.

(Step S2600-9)
The main CPU 500a sets a stop information command indicating the stopping order of the reels 410 in the transmission buffer.

(Step S2600-11)
The main CPU 500a sets the stop indicator output bit off (output image) to turn off (turn off) the bit corresponding to the indicator (not shown) of the stop switch 420.

(Step S2600-13)
The main CPU 500a executes an output port image set process to update the output image for the bit set in step S2600-11.

(Step S2600-15)
The main CPU 500a executes a display symbol bit setting process to set a display symbol bit.

(Step S2600-17)
The main CPU 500a executes a next cylinder setting pre-processing for stopping the next reel 410.

(Step S2600-19)
The main CPU 500a judges whether or not the stop processing has been completed for all of the reels 410. As a result, if it is judged that the stop processing has not been completed for all of the reels 410, the process proceeds to step S2500, and if it is judged that the stop processing has been completed for all of the reels 410, the process proceeds to step S2600-21.

(Step S2600-21)
The main CPU 500a determines whether the stop request flag is on for any of the reels 410, i.e., whether all of the reels 410 have stopped. If it is determined that all of the reels 410 have not stopped, the process proceeds to step S2600-21, and if it is determined that all of the reels 410 have stopped, the process proceeds to step S2600-23.

(Step S2600-23)
The main CPU 500a executes an error checking process to check the detection results of various errors.

(Step S2600-25)
The main CPU 500a executes an operation target bit extraction process for extracting information on operation target bits.

(Step S2600-27)
The main CPU 500a judges whether the stop switch 420 is pressed based on the operation target bit acquired in the above step S2600-25. If it is judged that the stop switch 420 is pressed, the process proceeds to step S2600-23, and if it is judged that the stop switch 420 is not pressed, the process proceeds to step S2700.

(Step S2700)
The main CPU 500a executes a display determination process for determining the winning combination that has been achieved. This display determination process will be described later.

Figure 94 is a flowchart explaining the display determination process (S2700) in the main control board 500.

(Step S2700-1)
The main CPU 500a clears the buffer of the main payout display section 432.

(Step S2700-3)
The main CPU 500a executes a display judgment abnormality detection process to determine whether a display judgment abnormality has occurred based on whether or not the pattern combination displayed on the active line A matches the pattern combination permitted to be displayed on the active line A.

(Step S2700-5)
The main CPU 500a sets an error code "EE" which indicates a display determination abnormality (error).

(Step S2700-7)
The main CPU 500a judges whether or not there is a display judgment abnormality based on the judgment result of the above step S2700-3. As a result, if it is judged that there is a display judgment abnormality, the process proceeds to step S2011, and if it is judged that there is no display judgment abnormality, the process proceeds to step S2700-9.

(Step S2700-9)
The main CPU 500a executes a display symbol identification generation process for determining a winning combination based on the symbol combination stopped (displayed) on the pay line A.

(Step S2700-11)
The main CPU 500a sets the initial value of the payout number to 0.

(Step S2700-13)
The main CPU 500a judges whether or not a small win has been won. If it is judged that a small win has been won, the process proceeds to step S2700-15. If it is judged that a small win has not been won, the process proceeds to step S2700-35.

(Step S2700-15)
The main CPU 500a turns on a winning flag indicating that a small winning combination has been achieved.

(Step S2700-17)
The main CPU 500a executes a payout number setting process for setting the payout number according to the small winning combination.

(Step S2700-19)
The main CPU 500a judges whether the time is within an advantageous zone. If it is judged that the time is within an advantageous zone, the process proceeds to step S2800. If it is judged that the time is within an advantageous zone, the process proceeds to step S2700-21.

(Step S2700-21)
The main CPU 500a obtains the value of the advantageous zone MY counter, which counts the net increase in the number of coins during the advantageous zone.

(Step S2700-23)
The main CPU 500a adds the number of payout coins to the value of the advantageous zone MY counter obtained in step S2700-23 above.

(Step S2700-25)
The main CPU 500a acquires the number of coins inserted for the game.

(Step S2700-27)
The main CPU 500a subtracts the number of inserted coins from the value added in step S2700-23.

(Step S2700-29)
The main CPU 500a judges whether the result of the subtraction in the above step S2700-27 is negative. If it is judged that the result of the subtraction is not negative, the process proceeds to step S2700-33, and if it is judged that the result of the subtraction is negative, the process proceeds to step S2700-31.

(Step S2700-31)
The main CPU 500a clears the value of the advantageous zone MY counter (sets it to 0).

(Step S2700-33)
The main CPU 500a updates the value of the favorable zone MY counter to the value subtracted in step S2700-27 or the value cleared in step S2700-31.

(Step S2700-35)
The main CPU 500a judges whether or not the replay role has been won. If it is judged that the replay role has not been won, the process proceeds to step S2800. If it is judged that the replay role has been won, the process proceeds to step S2700-37.

(Step S2700-37)
The main CPU 500a sets the number of coins inserted as the number of coins to be paid out.

(Step S2700-39)
The main CPU 500a turns on the re-play operation flag.

(Step S2700-41)
The main CPU 500a sets the number of coins to be automatically inserted.

(Step S2800)
The main CPU 500a executes a payout process for paying out medals, which will be described later.

Figure 95 is a flowchart explaining the payout process (S2800) in the main control board 500.

(Step S2800-1)
The main CPU 500a acquires a re-play operation flag.

(Step S2800-3)
The main CPU 500a sets in the transmission buffer a payout start command indicating that the payout of medals has started.

(Step S2800-5)
The main CPU 500a judges whether or not a replay has been won based on the replay operation flag acquired in step S2800-1. If it is judged that a replay has been won, the process proceeds to step S2800-41. If it is judged that a replay has not been won, the process proceeds to step S2800-7.

(Step S2800-7)
The main CPU 500 a executes a main display display process to display 0 on the main payout display section 432 .

(Step S2800-9)
The main CPU 500a determines whether or not a payout has been made (the number of payout coins is 0). If it determines that no payout has been made, the process proceeds to step S2800-35. If it determines that a payout has been made, the process proceeds to step S2800-11.

(Step S2800-11)
The main CPU 500a judges whether the number of stored sheets is 50 or more. If it is judged that the number of stored sheets is 50 or more, the process proceeds to step S2800-13, and if it is judged that the number of stored sheets is not 50 or more, the process proceeds to step S2800-15.

(Step S2800-13)
The main CPU 500a executes a medal payout device control process to cause the medal payout device 442 to pay out one medal, and then moves to step S2800-23.

(Step S2800-15)
The main CPU 500a sets a payout start interval timer.

(Step S2800-17)
The main CPU 500a judges whether the payout start timer is not 0, i.e., whether it is the first payout time. If it is judged that it is the first payout time, the process proceeds to step S2800-21, and if it is judged that it is not the first payout time, the process proceeds to step S2800-19.

(Step S2800-19)
The main CPU 500a executes a timer wait process to wait until the payout start interval timer counts down to 0.

(Step S2800-21)
The main CPU 500a increments the number of stored coins by one.

(Step S2800-23)
The main CPU 500a sets in the transmission buffer a payout execution command indicating that one medal has been paid out.

(Step S2800-25)
The main CPU 500a executes a main display pre-display process for displaying the number of coins already paid out on the main payout display section 432.

(Step S2800-27)
The main CPU 500a judges whether or not the bonus game state is in effect. If it is judged that the bonus game state is not in effect, the process proceeds to step S2800-31. If it is judged that the bonus game state is in effect, the process proceeds to step S2800-29.

(Step S2800-29)
The main CPU 500a increments by one the number of medals acquired during bonus operation, which is the number of medals paid out in the bonus game state.

(Step S2800-31)
The main CPU 500a judges whether or not the payout of the payout number of medals has been completed. If it is judged that the payout has not been completed, the process proceeds to step S2800-11. If it is judged that the payout has been completed, the process proceeds to step S2800-33.

(Step S2800-33)
The main CPU 500a executes a payout end process to end the payout of medals.

(Step S2800-35)
The main CPU 500a judges whether an over error has been detected. If it is judged that an over error has not been detected, the process proceeds to step S2800-41, and if it is judged that an over error has been detected, the process proceeds to step S2800-37.

(Step S2800-37)
The main CPU 500a sets an error code "E5" indicating an over error.

(Step S2800-39)
The main CPU 500a executes an error wait process to display an error, request an alarm sound, and wait for recovery from the error.

(Step S2800-41)
The main CPU 500a sets in the transmission buffer a payout end command indicating that the payout of medals has been completed.

(Step S2900)
The main CPU 500a executes a game transition process for transitioning the game state, managing advantageous zones, etc. This game transition process will be described later.

Figure 96 is a flowchart explaining the game transition process (S2900) on the main control board 500.

(Step S2900-1)
The main CPU 500a acquires a replay operation flag, and based on the acquired replay operation flag, executes a replay display control process which sets a stop display output bit off (output image) to turn on or off a bit corresponding to a replay display (not shown) indicating that the next play is a replay, and updates the output bit of the set output image.

(Step S2900-3)
When a bonus combination is won, the main CPU 500a executes a combination operation symbol display process for setting various parameters for controlling the bonus game state.

(Step S2900-5)
When the number of coins acquired during the bonus operation reaches a predetermined number in the bonus game state, the main CPU 500a executes a bonus operation end process for shifting the game state to a non-internal game state.

(Step S2900-7)
The main CPU 500a executes advantageous zone update processing to manage advantageous zones.

(Step S2900-9)
The main CPU 500a judges whether the next game is in an AT presentation state. If it is judged that the next game is not in an AT presentation state, the process proceeds to step S2900-15. If it is judged that the next game is in an AT presentation state, the process proceeds to step S2900-11.

(Step S2900-11)
The main CPU 500a judges whether or not the bonus game state is in effect. If it is judged that the bonus game state is not in effect, the process proceeds to step S2900-15. If it is judged that the bonus game state is in effect, the process proceeds to step S2900-13.

(Step S2900-13)
The main CPU 500a sets the advantageous lamp flag on to turn on the section indicator 460.

(Step S2900-15)
The main CPU 500a executes a performance command setting process that sets a performance command, which is a command related to the advantageous zone, in a transmission buffer.

(Step S2900-17)
The main CPU 500a sets a game end command, which indicates that one game has ended, in the transmission buffer.

(Step S2900-19)
The main CPU 500a executes a terminal board signal output process for outputting an external signal.

(Step S2900-21)
The main CPU 500a judges whether the effect wait timer, which is set when the advantageous zone is ended in the above step S2900-7, is 0. As a result, if it is judged that the effect wait timer is not 0, the process proceeds to step S2900-21, and if it is judged that the effect wait timer is 0, the process proceeds to step S2900-23.

(Step S2900-23)
The main CPU 500a sets a game status command indicating the game status in a transmission buffer.

(Step S2900-25)
The main CPU 500a sets a game start command indicating the start of the next game in the transmission buffer, and transfers the process to step S2100.

One game is executed through a series of processes from step S2100 to step S2900. After that, steps S2100 to S2900 are repeated.

Next, we will explain the power-off evacuation process and timer interrupt process on the main control board 500.

(Evacuation process when power is turned off for the main control board 500)
97 is a flow chart explaining the power-off save processing in the main control board 500. The main CPU 500a monitors the power-off detection circuit, and when the power supply voltage falls below a predetermined value, it interrupts and executes the power-off save processing.

(Step S3000-1)
When the power-off warning signal is input, the main CPU 500a saves the registers.

(Step S3000-3)
The main CPU 500a checks the power-off warning signal.

(Step S3000-5)
The main CPU 500a judges whether a power-off warning signal has been detected. If it is judged that a power-off warning signal has been detected, the process proceeds to step S3000-11. If it is judged that a power-off warning signal has not been detected, the process proceeds to step S3000-7.

(Step S3000-7)
The main CPU 500a restores the registers.

(Step S3000-9)
The main CPU 500a performs processing to permit an interrupt, and ends the power-off save processing.

(Step S3000-11)
The main CPU 500a executes an output port clear process to stop the output of the output port.

(Step S3000-13)
The main CPU 500a executes a save process for another area when power is turned off.

(Step S3000-15)
The main CPU 500a executes a RAM protect setting process required to prohibit access to the main RAM 300c.

(Step S3000-17)
In order to set the power interruption occurrence monitoring time, the main CPU 500a sets the counter value of a loop counter to a predetermined number of times the power interruption detection signal has been detected.

(Step S3000-19)
The main CPU 500a decrements the value of the loop counter set in step S3000-17 above by one.

(Step S3000-21)
The main CPU 500a judges whether the counter value of the loop counter is 0. If it is judged that the counter value is not 0, the process proceeds to step S3000-19, and if it is judged that the counter value is 0, the process proceeds to the above-mentioned CPU initialization process (step S1000).

If a power outage actually occurs, operation of the slot machine 400 will stop while steps S3000-19 to S3000-21 are being looped.

(Timer interrupt processing of main control board 500)
98 is a flow chart explaining the timer interrupt process in the main control board 500. The main control board 500 is provided with a reset clock pulse generating circuit that generates a clock pulse every predetermined period (1.49 milliseconds in the simultaneous rotation reference example, hereinafter referred to as "1.49 ms"). When a clock pulse is generated by the reset clock pulse generating circuit, an interrupt occurs and the following timer interrupt process is executed.

(Step S3100-1)
The main CPU 500a saves the registers.

(Step S3100-3)
The main CPU 500a clears the interrupt flag.

(Step S3100-5)
The main CPU 500a reads various input port images and executes port input processing to accurately obtain the latest switch states.

(Step S3100-7)
The main CPU 500a outputs the set output image to the output port and executes a dynamic port output process which controls the lighting of the main credit display section 430, the main payout display section 432, the number of inserted coins indicator, the start indicator, the indicators of the stop switches 420a, 420b, 420c, the replay indicator, and the section indicator 460.

(Step S3100-9)
The main CPU 500a updates the timer interrupt phase. The timer interrupt phase can be any of 0 to 3. In this example, if the timer interrupt phase is 0, 1, or 2, 1 is added, and if the timer interrupt phase is 3, it is changed to 0.

(Step S3100-11)
The main CPU 500 a performs a sub-command transmission process to transmit the commands stored in the transmission buffer to the sub-control board 502 .

(Step S3100-13)
The main CPU 500 a executes a stepping motor control process for controlling the stepping motor 452 .

(Step S3100-15)
The main CPU 500 a executes an output port image output process that outputs an output image to be output to the medal payout device 442 .

(Step S3100-17)
The main CPU 500a executes a random number update process to update various random numbers.

(Step S3100-19)
The main CPU 500a executes fraud monitoring processing to detect errors in order to output external signals (external signals 4 and 5) corresponding to the errors to the outside.

(Step S3100-21)
The main CPU 500a executes a module (subroutine) corresponding to the timer interrupt processing phase updated in step S3100-9. Here, the timer interrupt processing phase is set to any one of 0 to 3, and one module is provided corresponding to each of the timer interrupt processing phases 0 to 3 (four in total), so that one module is executed once every four timer interrupt processing times (every 5.96 ms). For example, a module that executes a time monitoring process that subtracts from various timers is associated with one timer interrupt processing phase.

(Step S3100-23)
The main CPU 500a executes a test signal output process for outputting a test signal to the outside.

(Step S3100-25)
The main CPU 500a reads various input port images and executes port input processing to accurately obtain the latest switch states.

(Step S3100-27)
The main CPU 500a restores the registers.

(Step S3100-29)
The main CPU 300a permits the interrupt and ends the timer interrupt process.

In addition, in the above-described embodiment, the main control board 500 and the sub-control board 502 are arranged to share the functional parts for progressing the game, but the functional parts of the main control board 500 may be arranged on the sub-control board 502, or the functional parts of the sub-control board 502 may be arranged on the main control board 500, or all the functional parts may be arranged together on a single control board.

In addition, in the above-described embodiment, only one type of AT presentation state is provided, but multiple types of AT presentation states may be provided, such as a specialized zone for adding the number of continuous plays in the AT presentation state.

In the above embodiment, the game is played using medals as the game value, but the game value may be electrical information (it may be so-called medalless). In this case, when a winning combination is achieved, the amount of value corresponding to the winning combination may be given to the player in the form of electrical information.

Furthermore, each process performed by the main control board 500 and the sub-control board 502 described above does not necessarily have to be performed in chronological order according to the order described in the flowchart, and may include parallel or subroutine processing.

Furthermore, each process performed by the main control board 500 and the sub-control board 502 described above does not necessarily have to be performed in chronological order according to the order described in the flowchart, and may include parallel or subroutine processing.

<Main control board CPU peripheral configuration>
FIG. 99 is a diagram for explaining electrical connections around the main CPU 300a. The main CPU 300a includes a CPU core 700 and a bus controller 702. The CPU core 700 controls the bus controller 702 through a bus control signal (Bus Cont) output from the BC terminal, and reads data from the main ROM 300b, the main RAM 300c, or the input/output unit 704, or writes data to the main RAM 300c or the input/output unit 704. Here, a microprocessor based on a Z80 series CPU and sold by LETech is used as the main CPU 300a. Here, the main CPU 300a, main ROM 300b, and main RAM 300c of a pachinko machine are described, but it goes without saying that they can be replaced with the main CPU 500a, main ROM 500b, and main RAM 500c of a slot machine 400.

For example, when reading data from main ROM 300b, main RAM 300c, or input/output unit 704, the bus controller 702 outputs a 16-bit address (A[16]) signal, identifies either main ROM 300b, main RAM 300c, or input/output unit 704 through decoders 706a, 706b, 706c, and controls the read (RD) signal to read a data (D[8]) signal from main ROM 300b, main RAM 300c, or input/output unit 704. Furthermore, when writing data to the main RAM 300c or the input/output unit 704, the bus controller 702 outputs an address (A[16]) signal and a data (D[8]) signal, and identifies either the main RAM 300c or the input/output unit 704 via the decoders 706b and 706c, and controls the write (WR) signal to write the data (D[8]) signal to the main RAM 300c or the input/output unit 704.

As described below, the address space of the input/output unit 704 is integrated with the address spaces of the main ROM 300b and the main RAM 300c. Therefore, unlike the conventional technology, there is no memory request (MREQ) terminal or I/O request (IORQ) terminal that outputs a signal to specify whether to access memory or I/O. By reassigning these two terminals to any other signal, the degree of freedom in program development can be increased.

The CPU core 700 also receives external signals such as an interrupt/wait (INT/WAIT) signal that triggers the start of interrupt processing, a non-maskable interrupt (NMI) signal that allows interrupt processing to be executed with the highest priority, and a bus request (BUSREQ) signal that can transition a bus signal to high impedance.

Figure 100 is a block diagram showing the internal configuration of a CPU core 700. The CPU core 700 includes an external input unit 710, a state control unit 712, a central control unit 714, a register unit 716, and an arithmetic logic unit (ALU) 718. The external input unit 710 receives an external signal and outputs control information based on the external signal to the state control unit 712 and the central control unit 714.

The state control unit 712 manages and transitions the internal state (RESET, instruction fetch, instruction decode, operation, memory load, memory store, HALT, etc.) based on the input control information to determine the operating state of the CPU core 700, and outputs control information based on that operating state to the central control unit 714.

The central control unit 714 extracts an opcode (instruction) from the input data (DI[8]) input via the bus controller 702, and controls the ALU 718 based on the command decoded by the instruction decoder. The central control unit 714 also obtains necessary information from each register of the register unit 716 and updates each register based on the decoded command.

The register unit 716 includes selector ports 722a, 722b, and 722c, an input bank selector 724, a first register bank 726, a second register bank 728, an output bank selector 730, an address port 732, and individual registers 734. The individual registers 734 include a 16-bit program counter (PC) that indicates the address of the program to be executed next, an 8-bit interrupt (I) register that is used in interrupt mode, an 8-bit refresh (R) register that counts opcode fetch cycles, and an 8-bit interrupt enable (IFF) register that controls whether interrupts are enabled or disabled.

The register unit 716 is also associated with a random number generator (not shown) for obtaining various random number values related to the big prize lottery (jackpot determining random number, winning symbol random number, reach group determining random number, reach mode determining random number, variation pattern random number, winning random number), and the random number values latched via the input ports (FE73h to FE9Ch) are obtained.

The random number generator operates on the system clock (a clock obtained by dividing the external input by two) and generates random numbers less than a predetermined maximum value. The random number generator is a random number generator that can set the maximum value of the random number. Four channels of random number generators that can set a 16-bit maximum value and eight channels of random number generators that can set an 8-bit maximum value are prepared as maximum value setting random number generators that can set the maximum value of the random number. Here, the 16-bit maximum value setting random number generators can select a random number update period in the range of 32 to 47 clocks, and the maximum value setting range can be set in the range of 256 to 65535. The 8-bit maximum value setting random number generators can select a random number update period in the range of 16 to 31 clocks, and the maximum value setting range can be set in the range of 16 to 255 in four channels and in the range of 64 to 255 in the other four channels. The random number generators that have a fixed maximum value are a random number generator that can set a 16-bit maximum value and eight channels of random number generators that can set an 8-bit maximum value. Here, the 16-bit maximum value fixed random number generator has a random number update period of 1 clock and a maximum value fixed to 65535. Also, the 8-bit maximum value fixed random number generator has a random number update period of 1 clock and a maximum value fixed to 255.

If there are not enough random numbers, it is possible to generate other random numbers (software random number generator) by multiplying or dividing the random number obtained from the hardware random number generator (random number generator) by a specified number within the program.

Figure 101 is a diagram explaining the configuration of the register. The register unit 716 is provided with a first register bank (bank 0) 726 and a second register bank (bank 1) 728 that is paired with the first register bank 726. The first register bank 726 is provided with a main register group (front register group) 726a and a sub-register group (back register group) 726b that is paired with the main register group 726a, and the second register bank 728 is provided with a main register group 728a and a sub-register group 728b that is paired with the main register group 728a. The main register group 726a and the sub-register group 726b of the first register bank 726, and the main register group 728a and the sub-register group 728b of the second register bank 728 each include 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY). However, unlike the sub-register groups 726b and 728b, the main register groups 726a and 728a further include an 8-bit register (U) and a 16-bit register (SP). The main CPUs 300a and 500a switch between the first register bank 726 and the second register bank 728, and can only access one of the register banks indicated by the register bank designation register RB in the F register (described later), and cannot simultaneously access the other register bank that is paired with that register bank.

Of the registers shown in FIG. 101, the Q register is an 8-bit register that is provided as an extended register in two sets in each register bank and stores the upper byte of an address used in some commands. When, for example, F0h is set as the value of the Q register, the main CPU 300a, 500a can use the Q register to access F000h to F0FFh in the main RAM 300c. The U register is an 8-bit register that is provided as an extended register in one set in each register bank and stores the upper byte of an address used in some commands. When, for example, FEh is set as the value of the U register, the main CPU 300a, 500a can use the U register to access built-in devices (timers, random number generators, external input/output circuits, etc.) connected to the input/output unit 704 at FE00h to FFFFh. The A register is a general-purpose register that also functions as an 8-bit accumulator used for arithmetic processing and data transfer. The F register is an 8-bit flag register that holds various arithmetic results. Here, as shown in FIG. 101, from the most significant bit (MSB) to the least significant bit (LSB), S is a sign flag that is set to 1 when the result of the operation is negative, Z is a zero flag (first zero flag) that is set to 1 when all bits are 0 as a result of the operation, TZ is a specific bit flag (second zero flag) of the gaming machine expansion specification that is set to 1 (value changes) when all bits are 0 by execution of a data transfer instruction (LD; load), and is sometimes called a TZ flag. H is a half carry flag that cannot be controlled by the programmer, RB (register bank designation register) is a register bank monitor that indicates the current register bank (first register bank 726 = 0, second register bank 728 = 1), P/V is a parity overflow flag, N is an addition/subtraction flag that cannot be controlled by the programmer, and C is a carry flag that is set to 1 when a carry or borrow occurs as a result of the operation. The F register and the A register form a pair register AF.

The B, C, D, E, H, and L registers are 8-bit general-purpose registers, two sets of which are provided in each register bank, and are used as 16-bit pair registers with predefined combinations (for example, registers BC, DE, HL, and several other combinations exist). The IX and IY registers are 16-bit general-purpose registers used for index addressing. The SP (stack pointer) register is 16 bits and stores the address that serves as the stack pointer. The Q', A', F', B', C', D', E', H', L', IX', and IY' registers are sub-registers 726b and 728b that can exchange or transfer data (contents) with the main registers 726a and 728a of the Q, A, F, B, C, D, E, H, L, IX, and IY registers, by exchange or transfer instructions. The A' and F' registers form a pair register AF', the B' and C' registers form a pair register BC', the D' and E' registers form a pair register DE', and the H' and L' registers form a pair register HL'. Note that the pair registers are not limited to BC', DE', and HL', and there are several other combinations. On the other hand, one set of the U and SP registers is provided in each register bank.

As described above, in the main control boards 300 and 500, the main CPU 300a controls the progress of the game in cooperation with the main RAM 300c based on the programs stored in the main ROM 300b. The programs for executing these functional parts are stored in designated areas (usage areas) of the main ROM 300b and the main RAM 300c.

Figure 102 is an explanatory diagram showing a memory map. Note that the memory map in a pachinko machine has already been explained using Figure 5, so here, the memory map of the slot machine 400 will be explained. The main ROM 500b is assigned a memory space of 0000h to 3FFFh (12 kbytes), the main RAM 500c is assigned a memory space of F000h to F3FFh (1 kbyte), and the input/output unit 704 is assigned a memory space of FE00h to FFFFh (512 bytes). Note that the instruction codes of the program are written in assembler language. Here, a program is composed of instruction codes, and is read by a computer to realize a specified process in cooperation with data and a work area.

A usage area is allocated to the memory space from 0000h to 1DF3h of the main ROM 500b. The usage area is an area for storing programs and data for executing game control processing that controls the progress of the game. Specifically, the memory space (control area) limited to 0000h to 11FFh (4.5 kbytes) stores instruction codes for a program for executing game control processing that controls the progress of the game by operating the initialization means 600, betting means 602, winning type lottery means 604, reel control means 606, judgment means 608, payout control means 610, game status control means 612, presentation status control means 614, and command transmission means 616, and the memory space (data area) limited to 1200h to 1DF3h (3.0 kbytes) stores data used in the game control processing program. In addition, a comment area is assigned to the memory space from 1E00h to 1FFFh, and a program management area is assigned to the memory space from 3FC0h to 3FFFh. In addition, another area (non-used area) is assigned to the memory space from 2000h to 3FBFh. The other area is an area for storing programs and data that are not specified to be stored in the used area, as described later. Specifically, the memory space from 2000h to 3FBFh stores instruction codes and program data of programs that perform part or all of the gaming machine test processing and security-related processing (hereinafter, sometimes simply referred to as non-game control processing) that do not affect the progress of the game. Here, the gaming machine test processing is the test processing of the slot machine 400 described in the Connection Specifications (4th Edition) of the Test Machine for Slot Machines. The security-related processing is a process for identifying an abnormal state for the purpose of preventing fraud by a third party and discovering defects, and includes, for example, the determination of the backup flag and the execution of a checksum as described above. There is no limit to the storage capacity of the separate areas, and in the example of Figure 102, they can be freely assigned to storage areas other than the usage area, comment area, and program management area.

As described above, the main CPU 500a may perform not only game control processing, but also game machine test processing and security-related processing (game control non-processing). However, the storage capacity of the usage area is predetermined; for example, as shown in FIG. 102, the control area is limited to 4.5 kbytes, and the data area is limited to 3.0 kbytes. Therefore, if not only game control processing but also programs and data for game machine test processing and security-related processing are placed in the usage area, the storage area for performing game control processing will be limited accordingly. Here, programs (usage programs) and data for executing game control processing must be stored in the usage area, but programs (separate programs) and data for executing game control non-processing (game machine test processing, security-related processing, etc.) that do not affect the progress of the game other than game control processing can be stored in either the usage area or the separate area. Therefore, at least some of the programs and data for executing the security-related processes, such as the backup flag determination process and the checksum execution process, are written in a separate area that is part of a memory area different from the used area (other than the used area).

In this way, when there is a mixture of processing that is performed in the use area (here, game control processing) and processing that does not necessarily have to be performed in the use area (here, security-related processing), it is desirable to store the program (use program) and data for executing the game control processing in the use area, and store the program (separate program) and data for executing non-game control processing (security-related processing) that does not have to be performed in the use area and does not affect the progress of the game other than the game control processing in a separate area. By dividing the memory area into multiple areas in this way, there is more space in the memory area (capacity) of the use area by the amount of the programs moved to the separate area. This makes it possible to allocate that much of the use area to game control processing (use program).

However, even if the memory area is divided into a usage area and a separate area as described above, the fairness of the gaming machine must be guaranteed. Therefore, in order to ensure the fairness of the gaming machine while appropriately dividing the roles between the usage area and the separate area, the following conditions (1) to (6) are stipulated.

Condition (1): The programs to be placed in the separate area are used for the purpose of outputting signals required for testing the gaming machine (gaming machine test processing) and preventing fraud (security-related processing), and do not impair (or impair) the fairness of the game. Condition (2): The control area and data area of the use area and the separate area are placed in areas that are explicitly distinguished from each other. Condition (3): The programs to be placed in the separate area (separate programs) are executed after being statically called from the program in the use area (use program). In addition, the call destination address is clearly stated in the program list at that time. Condition (4): The programs to be placed in the separate area are modularized by function, and when called, the contents of all registers used in the use area are protected. Condition (5): Access to the RAM in each area from the use area or the separate area is only possible for reference, and cannot be updated. Condition (6): It is not possible to call a subroutine in the control area of the use area from the control area of the separate area. Since a subroutine that performs interrupt processing is provided in the use area, it becomes necessary to prohibit interrupts when using the control area of the separate area. In order to properly execute the game control process, the time from when the interrupt is prohibited to when it is released must be within the interval of the interrupt process in the game control process (e.g., 1.49 msec). Therefore, when calling a subroutine that uses a control area in another area, the total time required for that one call is set to be within the interval of the interrupt process in the game control process.

In addition, the memory space from F000h to F1FFh in the main RAM 500c is allocated as a usage area. Specifically, the memory space from F000h to F13Fh is allocated as a work area for the game control process, and is used to manage variables such as timers, counters, and flags. The memory space from F1C0h to F1FFh is allocated as a stack area for the game control process. In addition, another area is allocated to the memory space from F200h to F3FFh in the main RAM 500c. Specifically, the memory space from F210h to F22Fh is allocated as a work area for some or all of the security-related processes, and is used to manage variables such as timers, counters, and flags. The memory space from F230h to F246h is allocated as a stack area for some or all of the security-related processes.

Also, the input/output unit 704 is assigned to the memory space from FE00h to FFFFh. Conventionally, a 512-byte I/O space was provided independent of the memory space to access the device corresponding to the input/output unit 704. In contrast, in this embodiment, the MREQ and IORQ signals are eliminated, and access to the memory and the input/output unit 704 is shared and performed by the RD and WR signals. Also, a U register is provided as hardware to specify the upper 8 bits of the address to access the device connected to the input/output unit 704, and the upper 8 bits of the address are specified in advance here. As a result, the I/O space that was provided independently of the memory space is integrated into the memory space to form a single address space, and when the IN command or the OUT command is executed, the input/output unit 704 assigned to the memory space can be accessed by specifying the upper 8 bits with the U register and the lower 8 bits with the lower 8 bits specified by the operand of the IN command or the OUT command.

In this embodiment, a program can be written so that the LDQ instruction uses the value of the Q register to access memory space (mainly data areas and work areas), and the IN and OUT instructions use the U register to access I/O of devices (timers, random number generators, external input/output circuits, etc.). This configuration makes it easier to understand the program at the time of design. Also, memory and I/O that were previously accessed by specifying 16-bit addresses can now be accessed by lower 8-bit operands, making it possible to compress program capacity. Furthermore, by having multiple upper specification registers, the Q register, Q' register, and U register, the number of times that upper registers need to be replaced due to reuse is reduced compared to when there is only one upper register, making it possible to further compress program capacity.

In the above example, the memory space corresponding to the I/O space was accessed with the IN and OUT instructions, but the memory space may also be accessed directly with the IN and OUT instructions. For example, when accessing three 256-byte areas in memory, this can be achieved by specifying the upper 8 bits of each in the Q register, Q' register, and U register, and then accessing each area with the LDQ instruction, IN instruction, and OUT instruction.

(Display of Game Information)
Incidentally, in a gaming machine, for example, a slot machine 400, there is a concern that the risk of riskiness will be excessively increased if the frequency of transitions to the bonus game state or the AT performance state as described above is biased. Therefore, in order to comprehensively and uniformly determine whether or not the game state with high medal acquisition performance is biased, judgment criteria such as an advantageous zone ratio, a role with instruction ratio, a continuous role ratio, a role ratio, and a role etc. state ratio are set. The advantageous zone ratio is a value expressed as a percentage obtained by dividing the number of staying games, which is the number of games staying in the advantageous zone from the time of the first startup, by the total number of games, which is the total number of games. The instruction-included role ratio is a value expressed as a percentage obtained by dividing the instruction-included role payout number, which is the number of medals paid out by the payout control means 610 based on the operation of the role and the instruction function operation, such as a bonus game, during a specified standard counting period from the time of the first startup, by the total payout number, which is the total number of medals paid out by the payout control means 610. The continuous role ratio is a value expressed as a percentage obtained by dividing the number of medals paid out by the payout control means 610 based on the operation of the first type special role, such as a regular bonus game, during a specified standard counting period from the time of the first startup. The consecutive payout number, which is the number of medals paid out by the payout control means 610, is divided by the total payout number, which is the total number of medals paid out by the payout control means 610, and the ratio of the medals is calculated as a percentage by dividing the number of medals paid out by the payout control means 610 based on the operation of the medals, such as bonus games, during a specified reference counting period from the first start-up, by the total payout number, which is the total number of medals paid out by the payout control means 610, and the ratio of the state of the medals, etc. is calculated as a percentage by dividing the number of games in operation, which is the number of games in which the medals, such as bonus games, are operated, during a specified reference counting period from the first start-up, by the total number of games, which is the total number of games. Note that the advantageous zone ratio, the ratio of the medals with instructions, the ratio of the consecutive medals with instructions, the ratio of the medals with instructions, and the ratio of the state of the medals, etc. are not cleared by changing the settings.

Such displays of advantageous zone ratios, instructed role ratios, continuous role ratios, role ratios, and role etc. status ratios are executed in the dynamic port output process (SYNMOUT module) S3100-7 of the timer interrupt process S3100 shown in FIG. 98, in which the role ratio display acquisition process for the used area (E_SDPST module) is executed.

Here, the advantageous section refers to a section in which the player remains in all presentation states except for some of the non-AT presentation states (here, non-advantageous presentation states). Note that in contrast to advantageous sections, non-advantageous presentation states may also be called non-advantageous sections. However, advantageous sections are not limited to AT presentation states or non-AT presentation states, and any game state or presentation state in which the game progresses advantageously for the player may be set as desired.

The role is a device for making it easier to win, and includes the regular bonus (RB), challenge bonus (CB), single bonus (SB), etc. Among these roles, the regular bonus (RB) corresponds to the first type special role. The regular big bonus (RBB) is a role in which the regular bonus (RB) is activated continuously regardless of the display of the symbol combination that indicates the winning form of the regular bonus (RB), which is the first type special role, and the challenge big bonus (CBB) is a role in which the challenge bonus (CB), which is the second type special role (one of the roles), is activated continuously regardless of the display of the symbol combination that indicates the winning form of the challenge bonus (CB). Therefore, the consecutive role ratio represents the ratio of the number of consecutive role payouts paid out by the operation of the first type special role to the total number of payouts paid out in a specified reference collection period, and the role ratio represents the ratio of the number of role payouts paid out by the operation of the role to the total number of payouts paid out in a specified reference collection period.

The standard counting period is the period for which the payout control means 610 accumulates the number of medals paid out. In this embodiment, for example, there are two possible values: 6000 games, which is a finite value, and the entire period since the slot machine 400 was installed in the game center (hall) (hereinafter referred to as the "total cumulative total"). Therefore, the consecutive feature ratio is derived as the consecutive feature ratio for 6000 games and the consecutive feature ratio for the total cumulative total, and the feature ratio is derived as the feature ratio for 6000 games and the feature ratio for the total cumulative total. However, it goes without saying that any number of games can be set as the standard counting period.

In order to obtain such advantageous zone ratio, instruction-based feature ratio, continuous feature ratio, feature ratio, and feature etc. state ratio, the accumulation means (not shown) accumulates the total number of games, the number of stay games, the number of games in operation, the total number of payouts, the number of instruction-based feature payouts, the number of continuous feature payouts, and the number of feature payouts. At this time, a counter is associated with each of the total number of games, the number of stay games, the number of games in operation, the total number of payouts, the number of instruction-based feature payouts, the number of continuous feature payouts, and the number of feature payouts. Specifically, when one game is started, the accumulation means increments the total number of games counter indicating the total number of games by 1. Then, it determines whether the current game is a game in an advantageous zone, and if it is a game in an advantageous zone, it increments the number of stay games counter indicating the number of stay games by 1. Note that the update of the stay number of games counter is started from the next game after the game that won the advantageous zone (the game in which the transition process to the advantageous zone was performed) when it is a non-advantageous zone. However, if a player enters the advantageous zone based on winning the Regular Big Bonus (RBB) or Challenge Big Bonus (CBB), the game will start from the game following the game in which the bonus was won (the game in which the transition process to the advantageous zone was performed). In addition, it is determined whether the current game is a game in which a special feature has been activated, and if so, the activated game number counter, which indicates the number of activated games, is incremented by 1.

When medals are paid out in a game, the accumulation means increments the total payout counter, which indicates the total number of medals paid out, by the number of medals paid out. If the payout of the medals is based on the operation of the reel and the instruction function, the accumulation means increments the instruction-based reel payout counter, which indicates the instruction-based reel payout number, by the number of medals paid out. If the payout of the medals is based on the reel, the accumulation means increments the reel payout counter, which indicates the number of reel payouts, by the number of medals paid out. If the payout of the medals is based on the first type special reel, the accumulation means increments the continuous reel payout counter, which indicates the number of continuous reel payouts, by the number of medals paid out.

The total cumulative total can be counted using only this counter, but the consecutive feature ratio and feature ratio must be calculated not only based on the total cumulative total but also on the reference counting period, which is a limited period of 6000 games in this case. Therefore, the 6000 games are divided equally into groups of 400 games, for example, and multiple counters (for example, 15) that count 400 games each are provided and used as a ring buffer. Note that, although an example is given here in which 6000 games are divided into groups of 400 games and counted, it goes without saying that any number of games to be divided can be set as long as it is a factor (divisor) of 6000.

Specifically, when medals are paid out in a game, the accumulation means performs a process of updating the total payout counter, the consecutive feature payout counter, and the feature payout counter up to 400 games, and when 400 games are reached, the total payout number, the consecutive feature payout number, and the feature payout number are added together with the 14 counters counted in the past to derive the total payout number, the consecutive feature payout number, and the feature payout number. Then, the counter counted in the oldest game among the 14 counters is initialized, and the total payout number counter, the consecutive feature payout number counter, and the feature payout number counter for 400 games are updated by the initialized counter. In this way, since it is possible to refer to the game information for the new 400 games and the game information for the past 5600 games every 400 games, it is possible to derive the total payout number, the consecutive feature payout number, and the feature payout number for the most recent 6000 games. Note that the counting by such counters is always performed regardless of the prescribed number or set value. In this way, the total number of games, number of remaining games, number of active games, total number of payouts, number of instructed feature payouts, number of consecutive feature payouts, and number of feature payouts are all accumulated.

Next, the ratio derivation means (not shown) derives the advantageous zone ratio, the instructed feature ratio, the consecutive feature ratio, the feature ratio, and the feature etc. state ratio based on the total number of plays, the number of stay plays, the number of activated plays, the total number of payouts, the number of instructed feature payouts, the number of consecutive feature payouts, and the number of feature payouts accumulated by the accumulation means. Specifically, the ratio derivation means divides the number of stay games by the total number of games and converts it to a percentage to derive the advantageous zone ratio, divides the total cumulative number of instruction-included feature payouts by the total cumulative total payouts and converts it to a percentage to derive the total cumulative instruction-included feature ratio, divides the total cumulative number of consecutive feature payouts by the total cumulative total payouts and converts it to a percentage to derive the total cumulative consecutive feature ratio, divides the total cumulative feature payouts by the total cumulative total payouts and converts it to a percentage to derive the total cumulative feature ratio, divides the number of activated games by the total number of games and converts it to a percentage to derive the feature etc. state ratio. In addition, the ratio derivation means divides the number of consecutive payouts for 6000 games by the total number of payouts for 6000 games for every 400 games, converts this to a percentage, and derives the consecutive payout ratio for 6000 games, and divides the number of payouts for 6000 games by the total number of payouts for 6000 games, and converts this to a percentage, and derives the payout ratio for 6000 games.

Next, the ratio display means (not shown) displays the advantageous zone ratio, the instructed feature ratio, the consecutive feature ratio for 6000 plays, the feature ratio for 6000 plays, the total cumulative consecutive feature ratio, the total cumulative feature ratio, and the feature etc. state ratio derived by the ratio derivation means on the ratio display unit 860 based on a predetermined display command.

Figure 103 is an explanatory diagram showing the appearance of the main control board 500. As shown in Figure 103 (a), a plurality of connectors 870 are provided on the end side of the main control board 500, and a ratio display unit 860 is provided near the center of the main control board 500. The ratio display unit 860 is composed of four 7-segment juxtapositions, each of which is made up of seven segments that can represent decimal Arabic numerals and a dot segment (DP) located to the lower right of the seven segments. When the main control board 500 is incorporated into the slot machine 400, as shown in Figure 103 (b), the main control board 500 is housed in a board case 872 and fixed to the front part 872a of the board case 872 from the back of the main control board 500 with a screw 874. At the position of the front part 872a of the board case 872 corresponding to the ratio display unit 860, a transparent window 872b through which the ratio display unit 860 can be seen is provided. Therefore, as shown in FIG. 74, the administrator can view the display content of the ratio display unit 860 through the transparent window 872b with the front upper door 404 open. Note that instead of the transparent window 872b, the entire board case 872 may be made of a transparent or semi-transparent material.

Here, in order to display five pieces of game information such as advantageous zone ratio, consecutive feature ratio for 6000 plays, feature ratio for 6000 plays, total cumulative consecutive feature ratio, and total cumulative feature ratio using only the four seven-segment display unit 860, an identifier is associated with each ratio, and the identifier and each ratio are displayed sequentially on the ratio display unit 860. Each ratio is displayed in the range of 0 to 99. Therefore, of the four seven-segment display unit 860, the two seven-segment display on the left side indicate the identifier, and the two seven-segment display on the right side indicate the ratio.

104 is an explanatory diagram for explaining the display mode of the ratio display unit 860. When the power switch 444 is turned on, as shown in FIG. 104(a), the ratio display means displays the identifier "7U" corresponding to the advantageous zone ratio and its ratio, for example, "70"% at once (so-called 7U type). Depending on the slot machine 400, the instruction-included feature ratio can also be displayed instead of the advantageous zone ratio. In this case, the ratio display means displays the identifier "7P" corresponding to the instruction-included feature ratio and its ratio, for example, "70"% at once (so-called 7P type). Here, in the 7U type, it is possible to perform a lottery to move to an advantageous zone by referring to a winning type with a setting difference, but it is not possible to perform a lottery to move to an advantageous zone by directly referring to a setting value. On the other hand, in the 7P type, it is possible to perform a lottery to move to an advantageous zone by referring to both a winning type with a setting difference and a setting value. The ratio display means separates the identifier and the ratio by lighting up the second 7-segment dot segment of the ratio display unit 860.

In this state, when a predetermined time (for example, 5.0 sec) has elapsed, the ratio display means displays the identifier "6Y" corresponding to the consecutive feature ratio of 6000 games and its ratio "60"% at once, as shown in Fig. 104(b). Then, each time a predetermined time has elapsed, the following combinations are displayed in sequence: the combination of the identifier "7Y" corresponding to the feature ratio of 6000 games and its ratio "70"% as shown in Fig. 104(c), the combination of the identifier "6A" corresponding to the consecutive feature ratio of the total cumulative feature ratio and its ratio "60"% as shown in Fig. 104(d), the combination of the identifier "7A" corresponding to the feature ratio of the total cumulative feature ratio and its ratio "70"% as shown in Fig. 104(e), and the combination of the identifier "5H" corresponding to the feature etc. state ratio and its ratio "50"% as shown in Fig. 104(f). Also, as shown in FIG. 104(f), when the combination of the identifier "5H" corresponding to the reel state ratio and its ratio "50"% is displayed, if a predetermined time further elapses, the identifier "7U" corresponding to the advantageous zone ratio and its ratio "70"% shown in FIG. 104(a) will be displayed again, and thereafter, each time the predetermined time elapses, the display will switch in the following order: advantageous zone ratio (reel ratio with instruction), consecutive reel ratio for 6000 plays, reel ratio for 6000 plays, total cumulative consecutive reel ratio, total cumulative reel ratio, reel state ratio.

Note that, although an example in which an identifier and a ratio are simultaneously displayed using four seven-segment displays has been given here, it is also possible to use only two seven-segment displays and switch between displaying the identifier and the ratio. In this case, the ratio display means switches the display in the ratio display unit 860 every time a predetermined time has elapsed, for example, in the following order: "7U" → "70" → "6Y" → "60" → "7Y" → "70" → "6A" → "60" → "7A" → "70" → "5H" → "50".

The ratio display means may also display the identifier and ratio by switching them on the existing display units (main credit display unit 430 and main payout display unit 432) corresponding to the four 7-segment displays instead of the ratio display unit 860 of the main control board 500. In this case, after the result of one game is notified, the front upper door 404 is opened before the start of the next game, and in that state, an existing switch, for example, a switch that executes an operation to set or change a set value, is operated to display the identifier corresponding to the advantageous zone ratio and its ratio, and thereafter, each time a predetermined time has passed, the display is repeatedly switched in the following order: advantageous zone ratio (instruction-included role ratio) → 6000-game continuous role ratio → 6000-game role ratio → total cumulative continuous role ratio → total cumulative role ratio → instruction-included role ratio. In addition, even if the ratio display means is displaying the advantageous zone ratio (indicated feature ratio), consecutive feature ratio for 6000 plays, feature ratio for 6000 plays, total cumulative consecutive feature ratio, total cumulative feature ratio, and feature etc. status ratio on the existing display section, if there is a change in the status of the slot machine 400, such as the insertion of a medal, the display will be deleted.

Through this ratio display unit 860 or an existing display unit, the administrator can visually check game information such as the advantageous zone ratio, the instructed feature ratio, the consecutive feature ratio for 6000 plays, the feature ratio for 6000 plays, the total cumulative consecutive feature ratio, the total cumulative feature ratio, and the feature etc. state ratio. It is then possible to determine whether the game information is within an appropriate range and judge whether the slot machine 400 is operating properly.

Such appropriate ranges are set, for example, as follows: favorable zone ratio < 70%, instructed feature ratio < 70%, consecutive feature ratio for 6000 plays < 60%, feature ratio for 6000 plays < 70%, total cumulative consecutive feature ratio < 60%, total cumulative feature ratio < 70%, feature etc. state ratio < 50%. If the appropriate range is exceeded, the ratio display means may blink each segment of the ratio display unit 860 for the applicable ratio at a cycle of, for example, 0.6 sec. Such a blinking display allows the administrator to quickly grasp the identifier that is out of the appropriate range and the ratio.

As described above, the ratio deriving means divides the number of stay games by the total number of games to derive the advantageous zone ratio, divides the total cumulative number of instruction-based payouts by the total cumulative total payouts to derive the total cumulative number of instruction-based payouts, divides the total cumulative number of consecutive payouts by the total cumulative total payouts to derive the total cumulative number of consecutive payouts, divides the total cumulative payouts by the total cumulative total payouts to derive the total cumulative number of payouts, and divides the number of active games by the total number of games to derive the ratio of the status of the game. However, the main CPU 500a in the main control board 500 has low processing power, and the multiplication and division commands available to the main CPU 500a are limited in the range of values that become the multiplicand, multiplier, dividend, and divisor. For example, in the DIV command for performing division, which is prepared in advance as an arithmetic command for the main CPU 500a, the numeric range for both the dividend and the divisor may be limited to 2 bytes, meaning that only the range of 0 to 65535 can be handled. In that case, if the total number of games is, for example, 175,000 games or more, the numeric range will be exceeded and it is simply not possible to use a 2-byte DIV command. In this case, a separate program must be prepared that repeats addition and subtraction, just as a person would do division by long division, resulting in an increase in the processing load. Therefore, in this embodiment, the objective is to appropriately obtain game information while suppressing the increase in processing load.

In the above, an example was given of the slot machine 400, where game information such as the advantageous zone ratio, the instructed feature ratio, the consecutive feature ratio for 6000 plays, the feature ratio for 6000 plays, the total cumulative consecutive feature ratio, the total cumulative feature ratio, and the feature state ratio are displayed on the ratio display unit 860. In a pachinko machine, for example, the number of winning balls (the number of low-probability payouts, which is the number of payouts when there is low probability and no time reduction) during a specified reference counting period may be divided by the number of outs (the number of low-probability outs, which is the number of outs when there is low probability and no time reduction), and the base value expressed as a percentage may be displayed on the performance display monitor (ratio display unit 860). Note that the base value in a pachinko machine is rounded off, not truncated to the nearest whole number, as in the slot machine 400.

(Derivation of each ratio)
Here, several examples of processing for deriving each ratio (advantageous zone ratio, instruction-included role ratio, continuous role ratio, role ratio, role etc. state ratio) will be described, but first, the common part of the several processing will be described in detail. In this embodiment, the advantageous zone ratio, instruction-included role ratio, continuous role ratio, role ratio, role etc. state ratio are finally converted into %. This means that only two decimal places are required for the division result. Also, in the slot machine 400, the value after the decimal point when converted into % is rounded down. This means that if only two decimal places can be derived for the division result, no calculation is required after the third decimal place. Therefore, in this embodiment, the division result is multiplied by a predetermined multiplier (here, 100) to carry over two digits. In this example, since only two decimal places are required, the multiplier "100" is used, but if three decimal places are required, the multiplier "1000" can be used, and the multiplier can be changed according to the number of digits required.

Here, the "game ratio" is described as the subject of the derivation process, but it goes without saying that the same process can be applied to the advantageous zone ratio, the instructed game ratio, the continuous game ratio, and the game state ratio. As described above, the game ratio is derived by dividing the number of game payouts by the total number of payouts and converting it to a percentage. This "percentage conversion" point corresponds to multiplying by the multiplier "100". Therefore, it can be expressed as a formula such as: Game ratio = number of game payouts / total number of payouts x 100. However, since the number of game payouts is ≦ total number of payouts, unless the number of game payouts = total number of payouts, this formula will always result in a value below the decimal point at the point where the number of game payouts / total number of payouts is reached, and for example, it will be impossible to calculate on the main CPU 500a.

Therefore, the calculation order is changed to: feature ratio = feature payout number x 100 ÷ total payout number. In other words, the calculation is performed in the following order: first, the feature payout number is multiplied by the multiplier (100), and then the result of multiplying the multiplier (dividend) is divided by the total payout number. By doing this, it is possible to complete the calculation result using only integers without performing calculations after the decimal point, and as a result, truncation after the decimal point can be easily achieved.

Figure 105 is a flowchart showing an example of calculating the reel ratio. In the example of Figure 105, the reel ratio is derived assuming that the reel payout number is "7123" and the total payout number is "10000". Here, for example, division is replaced with subtraction to achieve division of a number that exceeds the numerical range (0 to 65535). The numerical values in step S in this figure will be used only in the explanation of this figure.

First, the ratio derivation means judges whether the number of payouts of the reels is greater than the total number of payouts (S1). As a result, if it is judged that the number of payouts of the reels is greater than the total number of payouts (YES in S1), it derives the result that the number of payouts of the reels or the total number of payouts is not an appropriate value, derives the result that the reels ratio is abnormal, and ends the calculation process (S2). If it is judged that the number of payouts of the reels is less than the total number of payouts (NO in S1), the ratio derivation means judges whether the total number of payouts is 0 (S3). As a result, if the total number of payouts is 0, that is, if no medals have been paid out yet (YES in S3), it determines that the reels ratio is 0% and ends the calculation process (S4). If it is judged that the total number of payouts is not 0 (NO in S3), the ratio derivation means judges whether the number of payouts of the reels and the total number of payouts are equal (S5). As a result, if it is determined that the number of payouts of the reels is equal to the total number of payouts (YES in S5), the reel ratio is determined to be 99% and the calculation process is terminated (S6). In this way, in this embodiment, when the number of payouts of the reels is equal to the total number of payouts, the reel ratio is expressed as 99%, rather than the usual 100%. In this way, it is possible to express all reel ratios in two digits.

If it is determined that the number of payouts of the reels is not equal to the total number of payouts (NO in S5), the ratio deriving means multiplies the number of payouts of the reels "7123" by the multiplier "100" (= "712300") and holds this as the dividend (variable) (S7). Next, the ratio deriving means divides the dividend "712300" by the divisor, the total number of payouts "10000", to obtain a quotient (= "71") (S8). This quotient "71" becomes the reels ratio. This corresponds to the integer part of 71.23%, which is the percentage of the result of dividing the number of payouts of the reels "7123" by the total number of payouts "10000", and therefore it can be understood that this calculation is correct.

With these examples of calculating the ratio of game parts, it is possible to achieve division using only simple calculations such as addition, subtraction, and multiplication, and using only integers.

In the above, it is assumed that the decimal points of the bonus ratio are rounded down, but this is not the only case. When rounding off the decimal points of the bonus ratio, if the absolute value of the final negative dividend value (here, "-7700") is greater than 1/2 of the divisor (total payout amount, here "10000"), it is rounded down, and if it is less than 1/2, it is rounded up.

Here, we further divide the calculation procedure into two steps when calculating the reel ratio, namely, the calculation of the reel payout number x multiplier (S7 in FIG. 105) and the multiplication result ÷ total payout number (S8 in FIG. 105), and explore effective calculation procedures. Specifically, we first consider the effectiveness of multiple calculation procedures that execute the reel payout number x multiplier, and then consider the effectiveness of multiple calculation procedures that execute the multiplication result ÷ total payout number.

(Number of payouts x multiplier)
When the payout number of the reels is expressed as a numerical value, the maximum value is 3 bytes from the numerical range, and 3 bytes (24 bits) are required as memory capacity. In addition, the multiplier is 100 in this case, so it can be expressed in 1 byte (8 bits). In this case, the calculation of the payout number of the reels x the multiplier is a 24-bit x 8-bit calculation. Here, the main CPU 500a can execute a 24-bit x 8-bit calculation using an 8-bit MUL instruction that obtains a 16-bit calculation result by multiplying 8 bits x 8 bits.

As described above, the main CPU 500a has a built-in multiplier and divider that can perform calculations independently and in parallel with the main CPU 500a as built-in devices. Here, the multiplier performs, for example, 16-bit x 16-bit multiplication in parallel with command processing. When the multiplicand is written to a specified address (multiplicand setting register) of the built-in register and the multiplier is written to another specified address (multiplier setting register), multiplication is performed in the multiplier, and after a predetermined time, a different specified address (multiplication result register) is set to, for example, a 32-bit multiplication result. The divider performs, for example, 32-bit ÷ 32-bit division in parallel with command processing. When the dividend is written to a specified address (dividend setting register) of the built-in register and the divisor is written to another specified address (divisor setting register), division is performed in the divider, and after a predetermined time, a different specified address (division result register) is set to, for example, a 32-bit division result. Therefore, in addition to the 8-bit MUL instruction described above, the main CPU 500a can also use a 16-bit x 16-bit multiplier (hereafter simply referred to as a 16-bit multiplier).

Here, we present a first calculation example using only an 8-bit MUL instruction and a second calculation example using a 16-bit multiplier, and compare their effectiveness.

(First calculation example of executing the number of payouts of the reels x multiplier)
Fig. 106 is an explanatory diagram for explaining a first calculation example using only the 8-bit MUL instruction. In the first calculation example using only the 8-bit MUL instruction, in order to perform a calculation of the multiplicand (3 bytes) x the multiplier (1 byte), as shown in Fig. 106, the multiplicand is stored in the BCD register (BC register and D register), and the 8-bit MUL instruction is used to multiply the value of the D register, the value of the C register, and the value of the B register separated into 1 byte units by the multiplier (100) in that order. Then, by adding (accumulating) each of the multiplication results, the value of the D register x 100, the value of the C register x 100, and the value of the B register x 100, the calculation result (4 bytes) of the value of the BCD register x 100 can be obtained.

Figure 107 is a flowchart showing a specific process for implementing the first calculation example, and Figure 108 is a diagram showing an example of a specific command for implementing the first calculation example. The numerical values of step S in the explanation of Figure 107 will be used only in the explanation of this figure.

As shown in FIG. 107, first, the value of the cumulative reel counter is read into the BCD register (S1). Specifically, the command "LD A, (_EX_YAKR)" on the second line of FIG. 108 reads the one-byte value stored at address "_EX_YAKR" into the A register, the command "LD D, A" on the third line copies the value of the A register into the D register, and the command "LD BC, (_EX_YAKR+1)" on the fourth line reads the two-byte value stored at address "_EX_YAKR+1" into the BC register.

Next, as shown in FIG. 107, it is determined whether the value of the cumulative gambling counter stored in the BCD register is 0 (S2), and if it is 0 (YES in S2), the result will not change even if the multiplier is multiplied (because it is 0), so the first calculation example is terminated. Specifically, the command "OR A, B" on the fifth line of FIG. 108 calculates the logical sum of the value of the A register, which is equal to the value of the D register, and the value of the B register, and the command "OR A, C" on the sixth line of FIG. 108 calculates the logical sum of the value of the A register, which is the result of the calculation on the fifth line, and the value of the C register, and if the logical sum of the BCD register is 0, the command "JR Z, E_PYSAV28" on the seventh line moves to the index "E_PYSAV28" (not shown) indicating another process. Note that if the process differs depending on the contents of the F register, such as the command "JR Z, E_PYSAV28", the number of cycles will also differ. For example, the command "JR Z, E_PYSAV28" will take 3 cycles if movement is involved, as shown to the left of the cycle count slash in Figure 108, and will take 2 cycles if no movement is involved, as shown to the right of the cycle count slash. The following commands are also displayed in a similar manner if their processing differs depending on the contents of the F register.

Next, as shown in Fig. 107, the value of the D register, which is the least significant byte of the multiplicand, is multiplied by the multiplier (100) (S3), and the result of the calculation is set in the DE register (S4). Specifically, the command "LD A,D" on line 8 of Fig. 108 copies the value of the D register to the A register, the command "MUL HL,A,100" on line 9 stores the result of multiplying the value of the A register by 100 in the HL register, and the command "EX DE,HL" on line 10 sets the value of the HL register in the DE register.

Next, as shown in FIG. 107, the value of the C register, which is the middle byte of the multiplicand, is multiplied by the multiplier (100) (S5), and the result of the calculation is added to the value of the D register, and the result is returned to the D register (S6) and set in the main RAM 500c (S7). Specifically, the command "LD A,C" on line 11 of FIG. 108 copies the value of the C register to the A register, the command "MUL HL,A,100" on line 12 stores the result of multiplying the value of the A register by 100 in the HL register, the command "ADDWB HL,D" on line 13 adds only the most significant byte (the value of the D register) of the DE register set by the command "EX DE,HL" on line 10 to the HL register of the multiplication result, the command "LD D,L" on line 14 returns the least significant byte of the addition result to the D register, the command "EX DE,HL" on line 15 moves the value of the DE register corresponding to the least significant 2 bytes of the multiplication result to the HL register, and the command "LD (_EX_WRK2),HL" on line 16 stores the 2-byte value of the HL register in address "_EX_WRK2".

Next, as shown in FIG. 107, the value of the B register, which is the most significant byte of the multiplicand, is multiplied by the multiplier (100) (S8), and the most significant byte of the calculation result of step S6 (the value of the H register) is added to the result of the calculation (S9), and the result is set in the main RAM 500c (S10). Specifically, the command "LD A,B" on line 17 of FIG. 108 copies the value of the B register to the A register, the command "MUL HL,A,100" on line 18 stores the result of multiplying the value of the A register by 100 in the HL register, the command "ADDWB HL,D" on line 19 adds only the most significant byte (the value of the D register) of the DE register (the operation result of the command "ADDWB HL,D" on line 13) set by the command "EX DE,HL" on line 15 to the HL register of the multiplication result, and the command "LD (_EX_WRK2+2),HL" on line 20 stores the 2-byte value of the HL register in the address "_EX_WRK2+2". In this way, the operation result of the 4-byte BCD register value x 100 can be obtained in the address "_EX_WRK2".

Here, in this command example, as shown in FIG. 108, the total command size is 38 bytes, and the simple total number of cycles (simply adding up the number of cycles without taking into account the movement commands) is 49/48 cycles.

(Second calculation example of executing the number of payouts of the reels x multiplier)
Fig. 109 is an explanatory diagram for explaining a second operation example using a 16-bit multiplier. In the second operation using a 16-bit multiplier, in order to perform an operation of multiplicand (3 bytes) x multiplier (1 byte), as shown in Fig. 109, the multiplicand is stored in the BCD register (BC register and D register), the value of the BC register (2-byte value) is multiplied by the multiplier (100) using a 16-bit multiplier, and each value of the D register is multiplied by the multiplier (100) using an 8-bit MUL instruction. Then, by adding the value of the BC register x 100 and the value of the D register x 100 as a result of the multiplication, an operation result of the value of the 4-byte BCD register x 100 can be obtained.

Figure 110 is a flow chart showing a specific process for implementing the second calculation example, and Figure 111 is a diagram showing an example of a specific command for implementing the second calculation example. The numerical values of step S in the explanation of Figure 110 will be used only in the explanation of this figure.

As shown in FIG. 110, first, the value of the cumulative reel counter is read into the BCD register (S1). Specifically, the command "LD A, (_EX_YAKR)" on the second line of FIG. 111 reads the one-byte value stored at address "_EX_YAKR" into the A register, the command "LD D, A" on the third line copies the value of the A register into the D register, and the command "LD BC, (_EX_YAKR+1)" on the fourth line reads the two-byte value stored at address "_EX_YAKR+1" into the BC register.

Next, as shown in FIG. 110, it is determined whether the value of the cumulative reel counter stored in the BCD register is 0 (S2), and if it is 0 (YES in S2), the result will not change even if it is multiplied by the multiplier (because it is 0), so the second calculation example is terminated. Specifically, the command "OR A, B" on the fifth line of FIG. 111 calculates the logical sum of the value of the A register, which is equal to the value of the D register, and the value of the B register, and the command "OR A, C" on the sixth line of FIG. 111 calculates the logical sum of the value of the A register, which is the result of the calculation on the fifth line, and the value of the C register, and if the logical sum of the BCD register is 0, the command "JR Z, E_PYSAV28" on the seventh line moves to the index "E_PYSAV28" (not shown) indicating another process.

Next, as shown in FIG. 110, the upper two bytes of the multiplicand are set in the multiplicand setting register (S3), the multiplier (100) is set in the multiplier setting register, and the multiplication is performed (S4). Specifically, the command "LD (@MULA16_), BC" on the 8th line of FIG. 111 sets the value of the BC register to the multiplicand setting register "@MULA16_", the command "LD A, 100" on the 9th line sets the multiplier "100" in the A register, and the command "OUT (LOW @MULB16_), A" on the 10th line sets the value of the U register to the upper byte of the address, the address "@MULB16_" to the lower byte, and outputs the value of the A register to the multiplier setting register indicated by that address. The upper byte of the multiplier setting register "@MULB16_" is set to "00H" as the default value. In this way, the 16-bit multiplier is operated and the multiplication result is stored in the multiplication result register.

Next, as shown in FIG. 110, the value of the D register, which is the least significant byte of the multiplier, is multiplied by the multiplier (100) (S5). Specifically, the command "LD A, D" on line 11 of FIG. 111 copies the value of the D register to the A register, and the command "MUL HL, A, 100" on line 12 stores the result of multiplying the value of the A register by 100 in the HL register.

Next, as shown in FIG. 110, the lower 3 bytes of the multiplication result stored in the multiplication result register are read into the DEA register (S6), the value of the A register is added to the upper byte of the multiplication result of step S5 (the value of the H register) (S7), and the result is set in the main RAM 500c (S8). Specifically, the command "IN A, (LOW @MUL32_ __ + 0" on line 13 of FIG. 111 sets the value of the U register as the most significant byte of the address, and the address "@MULB32_ __ + 0" as the least significant byte, and reads the value of the multiplication result register indicated by that address into the A register. The command "LD ED, (LOW @MUL32_ __ + 1" on line 14 reads the second and third bytes from the lowest of the multiplication result register into the DE register. The command "ADD A, H" on line 15 adds the most significant byte of the multiplication result (the value of the H register) set by the command "MUL HL, A, 100" on line 12 to the value of the A register. The command "LD H, A" on line 16 returns the addition result (the value of the A register) to the H register. The command "OUT (LOW @DIVA32_+0), HL" sets the value of the U register to the upper byte of the address, and the address "@DIVA32_" to the lower byte, outputting the value of the HL register to the dividend setting register "@DIVA32_" indicated by that address.

Next, as shown in FIG. 110, the value of the DE register set in step S6 is copied to the HL register (S9), and it is determined whether the value was carried up in the addition in step S7 (S10). If the value was carried up (YES in S10), the carried amount is added to the HL register (S11) and set in the main RAM 500c (S12). Specifically, the command "EX DE,HL" on line 18 of FIG. 111 sets the value of the DE register to the HL register, the command "JR NC,E_PYSAVX1" on line 19 determines whether the carry flag is set by the command "ADD A,H" on line 15, and if the carry flag is not set, it moves to the index "E_PYSAVX1" on line 21. If the carry flag is set, the command "INC HL" on line 20 increments the value of the HL register by 1, and the command "OUT (LOW @DIVA32_+2),HL" on line 22 sets the value of the U register to the upper byte of the address and the address "@DIVA32_+2" to the lower byte, and outputs the value of the HL register to the divisor setting register indicated by that address.

Here, in this command example, as shown in FIG. 111, the total command size is 43 bytes, and the simple total number of cycles is 59/57 cycles.

As explained above, when comparing the first calculation example that executes the number of reel payouts times the multiplier with the second calculation example that executes the number of reel payouts times the multiplier, the first calculation example has a smaller total command size and a smaller simple total number of cycles. Therefore, when executing the number of reel payouts times the multiplier in the slot machine 400, it is preferable to execute it using only the 8-bit MUL command, as explained using Figures 106 to 108.

In the first calculation example described above, the command "LD" is used as the command on lines 16 and 20 of FIG. 108, but depending on the processing mode thereafter, the command "OUT" may be used instead as the command on lines 16 and 20 as shown in FIG. 112. In the case of FIG. 112, as in FIG. 108, the total command size is 38 bytes, and the simple total number of cycles is 49/48 cycles.

(Multiplication result / total number of payouts)
Next, among the multiple steps of the calculation procedure when calculating the ratio of the bonus items, the effectiveness of the multiplication result (the number of bonus items paid out × the multiplier) ÷ the total number of bonus items paid out will be examined. As described above, the multiplication result of the number of bonus items paid out (3 bytes) × the multiplier (1 byte) is a maximum of 4 bytes, so 4 bytes or more are required as memory capacity. Therefore, the multiplication result is expressed in 4 bytes (32 bits). The total number of bonus items also requires 3 bytes or more as memory capacity, so the maximum value is 3 bytes. Therefore, the total number of bonus items is also expressed in 4 bytes. In this case, the calculation of the multiplication result ÷ the total number of bonus items is a 32-bit ÷ 32-bit calculation. The main CPU 500a repeatedly subtracts the total number of bonus items from the multiplication result, and the number of subtractions can realize the 32-bit ÷ 32-bit calculation.

However, in the method of simply repeatedly subtracting the total payout number from the multiplication result, the total payout number must be repeatedly subtracted from the multiplication result the number of times corresponding to the ratio of the reel. In that case, the subtraction process will be performed up to 100 times. Therefore, it is possible to reduce the number of subtraction processes by multiplying the total payout number, which is the divisor, by an integer and subtracting it. For example, if the number of reel payouts is "7123" and the total payout number is "10000", the total payout number "10000" is multiplied by the integer "10" by the multiplication result "712300", which is the dividend, and "100000" is subtracted, which is the total payout number "10000" multiplied by the integer "10", to derive "7", which corresponds to the second digit (tens digit) of the reel ratio. In addition, by subtracting the original total payout number "10000" from the updated (subtracted) multiplication result, "1" which corresponds to the first digit (ones digit) of the reel ratio can be derived. In this way, by multiplying the total payout number (divisor) by an integer, it is possible to reduce the number of subtraction processes to a maximum of 20.

However, since the main CPU 500a performs calculations in binary, the number "2" corresponding to a carry in a binary number is used here instead of the number "10" corresponding to a carry in a decimal number. Therefore, here, the total payout number "10,000" multiplied by a predetermined integer "64 (2 to the 6th power)" which is a power of 2 is subtracted from the multiplication result "712,300", and the integer is then changed in the order of "32 (2 to the 5th power)" → "16 (2 to the 4th power)" → "8 (2 to the 3rd power)" → "4 (2 to the 2nd power)" → "2 (2 to the 1st power)" → "1 (2 to the 0th power)" to multiply the total payout number, and subtracted from the multiplication result. Here, the integer multiplied by the total payout number starts from 64, which is a power of 2, because the ratio of the roles falls within the range of 0 to 99, so there is no need to subtract a number greater than "128 (2 to the 7th power)".

As described above, the main CPU 500a has a built-in 32-bit/32-bit divider (hereinafter simply referred to as a 32-bit divider). Therefore, the main CPU 500a can use a 32-bit divider instead of repeatedly subtracting a number obtained by multiplying the total payout number by a power of 2 from the above multiplication result (hereinafter simply referred to as repeatedly subtracting a number multiplied by a power of 2).

Here, we present a third calculation example using repeated subtraction of a number multiplied by a power of 2, and a fourth calculation example using a 32-bit divider, and compare their effectiveness.

(Third calculation example of multiplication result divided by total payout amount)
FIG. 113 is an explanatory diagram for explaining a third calculation example using repeated subtraction of a number multiplied by a power of 2. In the third calculation example using repeated subtraction of a number multiplied by a power of 2, a calculation example of a multiplicand (4 bytes) which is the multiplication result divided by a divisor (4 bytes) which is the total payout number is shown. Here, it is assumed that the dividend is "712300" and the divisor is "64 x 10000" which is the original divisor "10000" multiplied by 64.

As shown in FIG. 113, if it is determined in the first judgment that the dividend is greater than or equal to the divisor, the divisor can be subtracted from the multiplicand, so the ratio derivation means subtracts the divisor "64 x 10000" from the dividend "712300" to update the dividend to "72300", and adds "64" to the quotient "0" to update the quotient to "64 (1000000B in binary)". In the second to fourth judgments, the dividend is less than the divisor, so no subtraction of the divisor is performed. If it is determined in the fifth judgment that the dividend is greater than or equal to the divisor, the ratio derivation means subtracts the divisor "4 x 10000" from the dividend "72300" to update the dividend to "32300", and adds "4" to the quotient "64" to update the quotient to "68 (1000100B in binary)". Similarly, if it is determined in the sixth judgment that the dividend is greater than or equal to the divisor, the ratio derivation means subtracts the divisor "2 x 10,000" from the dividend "32,300" to update the dividend to "12,300" and adds "2" to the quotient "68" to update the quotient to "70 (1,000,110B in binary)". If it is determined in the seventh judgment that the dividend is greater than or equal to the divisor, the ratio derivation means subtracts the divisor "1 x 10,000" from the dividend "12,300" to update the dividend to "2,300" and adds "1" to the quotient "70" to update the quotient to "71 (1,000,111B in binary)".

When the subtraction and addition steps are repeated seven times from the integer "64", the integer is rounded down to 0 (<1), the calculation process ends, and the reel ratio becomes the quotient "71" at that point. This corresponds to the integer part of 71.23%, which is the percentage result of dividing the reel payout number "7123" by the total payout number "10000", so it can be seen that this calculation is correct.

Figure 114 is a flow chart showing specific processing for realizing the third calculation example, and Figure 115 is a diagram showing an example of a specific command for realizing the third calculation example. The numerical values of step S in the explanation of Figure 114 will be used only in the explanation of this figure. Note that here, it is assumed that the address "_EX_WRK1" storing the 4-byte divisor and the address "_EX_WRK2" storing the 4-byte dividend are arranged consecutively.

As shown in Figure 114, first, the quotient is initialized to 0 and the integer (power of 2) is initialized to 64 (S1), the most significant 2 bytes of the dividend and the most significant 2 bytes of the divisor are read (S2), and it is determined whether the most significant 2 bytes of the dividend are less than the most significant 2 bytes of the divisor (S3). If the most significant 2 bytes of the dividend are less than the most significant 2 bytes of the divisor (YES in S3), the process moves to step S10. Specifically, the command "XOR A, A" on the first line of FIG. 115 sets "0" to the A register, which indicates the quotient, the command "LD C, 64" on the second line sets "64" to the C register, which indicates an integer, the command "LD HL, _EX_WRK2+2" on the fourth line reads the value (the upper 2 bytes) obtained by adding 2 to the value of the address "_EX_WRK2" storing the dividend (the multiplication result of the number of payouts of the reel x the multiplier) into the HL register, the command "LD DE, (HL-4)" on the fifth line reads the upper 2 bytes of the divisor stored in the address "_EX_WRK1", which is 4 bytes below the address "_EX_WRK2" storing the dividend, into the DE register, and the command "JCP "C, (HL), DE, E_PYSAV27" compares the value of the address indicated by the HL register (the most significant two bytes of the dividend) with the value of the DE register (the most significant two bytes of the divisor), and if the carry flag is set, i.e., if the most significant two bytes of the dividend are less than the most significant two bytes of the divisor, it moves to the index "E_PYSAV27" on the 20th line.

Next, as shown in Fig. 114, if the upper two bytes of the dividend are equal to or greater than the upper two bytes of the divisor (NO in S3), the lower two bytes of the dividend and the lower two bytes of the divisor are read for the subsequent calculation (S4), and it is determined whether the upper two bytes of the dividend are not equal to the upper two bytes of the divisor, i.e., whether the upper two bytes of the dividend are greater than the upper two bytes of the divisor (S5). If the upper two bytes of the dividend are not equal to the upper two bytes of the divisor (YES in S5), the process moves to step S8. Specifically, the command "LD HL, _EX_WRK1" on line 7 of FIG. 115 reads the two lowest bytes of the address "_EX_WRK1" storing the divisor into the HL register, the command "LD DE, (HL+4)" on line 8 reads the two lowest bytes of the dividend stored in address "_EX_WRK2," which is four bytes higher than the address "_EX_WRK1" storing the divisor, into the DE register, and the command "JR NZ, E_PYSAV26" on line 9 moves to the index "E_PYSAV26" on line 12 if the zero flag is not set by executing the command on line 6.

Next, as shown in FIG. 114, it is determined whether the two least significant bytes of the dividend read in step S4 are greater than the two least significant bytes of the divisor (S6). If the two least significant bytes of the dividend are greater than the two least significant bytes of the divisor (YES in S6), the process proceeds to step S8. If the two least significant bytes of the divisor are equal to or less than the two least significant bytes of the divisor (NO in S6), it is determined in step S6 whether the two least significant bytes of the dividend are not equal to the two least significant bytes of the divisor, i.e., whether the two least significant bytes of the dividend are less than the two least significant bytes of the divisor (S7). If the two least significant bytes of the dividend are not equal to the two least significant bytes of the divisor (YES in S7), the process proceeds to step S10. Specifically, the command "JCP C, (HL), DE, E_PYSAV26" on line 10 of FIG. 115 compares the value of the address indicated by the HL register (the lowest 2 bytes of the divisor) with the value of the DE register (the lowest 2 bytes of the dividend). If the carry flag is set, i.e., if the lowest 2 bytes of the dividend are greater than the lowest 2 bytes of the dividend, it moves to the index "E_PYSAV26" on line 12. The command "JR NZ, E_PYSAV27" on line 11 moves to the index "E_PYSAV27" on line 20 if the zero flag is not set by executing the command on line 10.

Next, as shown in FIG. 114, if the dividend is greater than or equal to the divisor, the current integer is added to the quotient (S8), the divisor is subtracted from the dividend, and the subtraction result is updated as the new dividend (S9). Specifically, the command "ADD A, C" on line 13 of FIG. 115 adds the value of the C register, which indicates an integer, to the A register, which indicates the quotient. The command "SUB DE, (HL)" on line 14 subtracts the value of the lower two bytes of the divisor stored at the address indicated by the HL register from the value of the DE register in which the lower two bytes of the dividend are stored, thereby updating the DE register. The command "LD (HL+4), DE" on line 15 stores the lower two bytes of the updated dividend, which is the result of the subtraction, in the address indicating the dividend located four bytes higher than the address in which the divisor indicated by the HL register is stored. The command "LD DE, (HL+2)" on line 16 reads the upper two bytes of the divisor stored at the address indicated by the HL register into the DE register. The command "HL, (HL+6)" reads the upper two bytes of the dividend, located 6 bytes above the address storing the divisor indicated by the HL register, into the HL register, and the command "SBC HL,DE" on line 18 subtracts the value of the DE register, in which the upper two bytes of the divisor are stored, from the value of the HL register, in which the upper two bytes of the dividend are stored, to update the HL register, and the command "LD (_EX_WRK2+2), HL" on line 19 stores the upper two bytes of the updated dividend, which is the result of the subtraction, in the upper two bytes of the dividend indicated by the address "_EX_WRK2".

Next, as shown in FIG. 114, the divisor is divided by 2 (bit shifted to the right) and updated as a new divisor (S10), the integer is divided by 2 (bit shifted to the right) and updated as a new integer (S11), it is determined whether the integer is not 0 (S12), and if it is not 0 (YES in S12), the process from step S2 is repeated, and if it is 0 (NO in S12), the role ratio is set in the main RAM 500c (S13), and the process of repeatedly subtracting the number multiplied by the power of 2 is terminated. Specifically, the command "LD HL, _EX_WRK1+3" on line 21 of FIG. 115 reads the address "_EX_WRK1+3" indicating the most significant byte of the divisor into the HL register, the command "SRL (HL)" on line 22 bit-shifts the value of the address indicated by the HL register (the fourth byte of the divisor) to the right by one bit, the command "DEC HL" on line 23 decrements the value of the HL register by one, the command "RR (HL)" on line 24 bit-shifts the value of the address indicated by the HL register (the third byte from the lowest order of the divisor) to the right by one bit, the command "DEC HL" on line 25 decrements the value of the HL register by one, the command "RR (HL)" on line 26 bit-shifts the value of the address indicated by the HL register (the second byte from the lowest order of the divisor) to the right by one bit, and the command "DEC The command "RR (HL)" on line 28 decrements the value of the HL register by 1, the command "RR (HL)" on line 28 bit-shifts the value of the address indicated by the HL register (the least significant byte of the divisor) to the right by 1, the command "SRL C" on line 29 bit-shifts the value of the C register, which indicates an integer, to the right by 1, the command "JR NZ, E_PYSAV25" on line 30 moves it to the index "E_PYSAV25" on line 3 if the zero flag is not set by executing the command on line 29, and the "LD (_EX_DPA7), A" on line 32 stores the value of the A register, which is the quotient, in address "_EX_DPA7".

This third calculation example makes it possible to realize division using only simple calculations such as addition, subtraction, and multiplication, and using only integers. Here, it is sufficient to repeat the subtraction and addition process seven times, so the calculation process can be performed quickly. Furthermore, assuming that the decimal points of the reel ratio are truncated, no error occurs, making it possible to accurately derive the reel ratio.

In this example command, as shown in FIG. 115, the total command size is 59 bytes, and the simple total number of cycles is 95/90 cycles. The actual number of cycles is as follows. That is, in this process, the command from the next command (line 4) of index "E_PYSAV25" to the command immediately before index "E_PYSAV28" (line 30) is looped 7 times. In this case, if the command "JCP C, (HL), DE, E_PYSAV27" on line 6 is used to move to index "E_PYSAV27" in all 7 loops, the commands on lines 7 to 19 are not executed, so the number of cycles is the minimum of 321 (3 + 45 (first 6 loops) x 6 + 44 (seventh loop) + 4) cycles. On the other hand, if the command on line 6, "JCP C, (HL), DE, E_PYSAV27," does not move to the index "E_PYSAV27" in all loops, the number of cycles will be at its maximum. However, considering that the role ratio never exceeds 100% and that the processing load is at its maximum when it is 95% and 63%, the maximum number of cycles will be 566 (3 + 61 (first loop) + 83 (remaining 6 loops) x 6 + 4). Therefore, the actual total number of cycles will be in the range of 321 to 566 cycles.

Note that, even here, it is assumed that the decimal points of the reel ratio are truncated, but this is not the only case. When rounding off the decimal points of the reel ratio, subtraction and addition processes are repeated eight times, and if it is determined in the eighth judgment that the dividend is greater than or equal to the divisor, this can be achieved by adding 1 to the quotient.

(Fourth calculation example of multiplication result divided by total payout amount)
Fig. 116 is a flow chart showing a specific process for realizing the fourth calculation example, and Fig. 117 is a diagram showing an example of a specific command for realizing the fourth calculation example. The numerical value of step S in the explanation of Fig. 116 is used only in the explanation of this figure. It is assumed here that the dividend, which is the multiplication result of the number of payouts of the reels multiplied by the multiplier, has already been set in the dividend setting register "DIVA32" as explained using Fig. 112.

As shown in FIG. 116, first, the value of the cumulative feature counter is read into a register and set in the divisor setting register "DIVB32" (S1). Specifically, the command "LD HL, (_EX_PRZR)" on the first line of FIG. 117 reads the value stored in the address "_EX_PRZR" indicating the cumulative feature counter into the HL register, the command "LD A, (_EX_PRZR+2)" on the second line reads the value stored in the address "_EX_PRZR+2" indicating the upper byte of the cumulative feature counter into the A register, the command "OUT (LOW @DIVB32_+0),HL" on the third line sets the value of the U register to the upper byte of the address and the address "@DIVB32_" to the lower byte, and outputs the value of the HL register to that address, and the command "OUT (LOW By "@DIVB32_+2), A", the value of the U register is set as the upper byte of the address, and the address "@DIVB32_+2" is set as the lower byte, and the value of the A register is output to that address. Note that the upper byte of the divisor setting register "@DIVB32_" is set to "00H" as the default value.

Next, as shown in FIG. 116, the division waits for a certain amount of time (S2), and after a certain amount of time has elapsed, the result of the operation is set in the main RAM 500c (S3). Specifically, the "NOP" command on lines 5 to 8 of FIG. 117 consumes four cycles of time, and the "IN A, (LOW @DIV32___+0)" command on line 9 sets the value of the U register to the upper byte of the address and the address "@DIV32___+0" to the lower byte, reading the value of the division result register indicated by that address into the A register, and the "LD (_EX_DPA7), A" command on line 11 stores the quotient, or the value of the A register, in the address "_EX_DPA7".

Here, in this command example, as shown in FIG. 117, the total command size is 20 bytes, and the total number of cycles is 28 cycles.

As explained above, when comparing the third calculation example, which executes multiplication result ÷ total payout number, with the fourth calculation example, which executes multiplication result ÷ total payout number, the fourth calculation example has a smaller total command size and a smaller total number of cycles. Therefore, when executing multiplication result ÷ total payout number in slot machine 400, it is preferable to execute it using a 32-bit divider, as explained using Figures 116 and 117.

Above, the first to fourth calculation examples were given to explain the calculation mode of the feature ratio in the slot machine 400. Below, the base value in the pachinko machine will be explained. Note that the advantageous zone ratio, the feature ratio with instruction, the consecutive feature ratio, the feature ratio, and the feature etc. state ratio in the slot machine 400 are all rounded down to the nearest whole number, but the base value (number of prize balls/number of outs) in the pachinko machine is rounded up to the nearest whole number. Therefore, in the pachinko machine, "200" is used as the multiplier for the number of prize balls instead of "100", and whether the decimal point is 0.5 or more is converted to an integer (least significant bit) to determine whether it is. Therefore, the base value is calculated by multiplying the number of prize balls by the multiplier (200), and then dividing the result of multiplying the multiplier (dividend) by the number of outs, and rounding up or down is determined according to the least significant bit (MLB).

Here, we present a fifth calculation example using an 8-bit MUL instruction and repeated subtraction of a number multiplied by a power of 2, and a sixth calculation example using a 16-bit multiplier and a 32-bit divider, and compare their effectiveness.

(Fifth example of calculation: Number of winning balls × multiplier ÷ number of outs)
Fig. 118 is a flow chart showing a specific process for implementing the fifth calculation example using an 8-bit MUL command and repeated subtraction of a number multiplied by a power of 2, and Fig. 119 is a diagram showing an example of a specific command for implementing the fifth calculation example. The numerical values of step S in the explanation of Fig. 118 are used only in the explanation of this figure. Here, it is assumed that an address "R_ERW_BF1" storing a 3-byte dividend (the calculation result of multiplying the number of winning balls by a multiplier) and an address "R_ERW_BF2" storing a 3-byte divisor (the number of outs) are consecutively arranged.

As shown in FIG. 118, first, the value of the normal prize ball counter is read into the BC register (S1), the value of the normal out counter is read into the HL register (S2), and it is determined whether the HL register is 0 (S3). If it is 0 (YES in S3), the process proceeds to step S23. Specifically, the command "XOR A, A" on line 2 of FIG. 119 initializes the value of the A register, which will be used later to calculate the divisor, the command "LD BC, (R_ERW_TJS)" on line 3 reads the value of the normal prize ball counter (number of prize balls) indicated by the address "R_ERW_TJS" into the BC register, the command "LD HL, (R_ERW_TJO)" on line 4 reads the value of the normal out counter (number of outs) indicated by the address "R_ERW_TJO" into the HL register, and the command "JR TZ, E_SHYMT_60" on line 5 moves the value of the HL register to the index "E_SHYMT_60" on line 49 if it is 0.

Next, as shown in FIG. 118, the out number is multiplied by an integer (a power of 2, here 128) (S4), and the result of the calculation is stored in the main RAM 500c as a divisor buffer (S5). Specifically, the command "SRL H" on the sixth line of FIG. 119 shifts the value of the H register one bit to the right, the command "RR L" on the seventh line shifts the value of the L register, including the carrier from the H register, one bit to the right, and the command "RRA" on the eighth line shifts the value of the A register, including the carrier from the L register, one bit to the right. Here, if we judge the numerical value in units of the HLA register, we can consider the value of the HL register to be multiplied by 256 and then bit-shifted one bit to the right, so the out number is multiplied by 128 (256/2), which becomes the divisor. Then, the command "LD (R_ERW_BF2), A" on line 9 of Figure 119 stores the value of the A register, which is the lower byte of the divisor, in address "R_ERW_BF2," and the command "LD (R_ERW_BF2+1), HL" on line 10 stores the value of the HL register, which is the upper two bytes of the divisor, in address "R_ERW_BF2+1."

Next, as shown in Fig. 118, the value of the C register, which is the lower byte of the multiplicand (number of prize balls), is multiplied by the multiplier (200) (S6), and the result of the calculation is set in the DE register (S7). Specifically, the command "LD A, C" on line 11 of Fig. 119 copies the value of the C register to the A register, the command "MUL HL, A, 200" on line 12 stores the result of multiplying the value of the A register by 200 in the HL register, and the command "EX DE, HL" on line 13 sets the value of the HL register in the DE register.

Next, as shown in FIG. 118, the value of the B register, which is the upper byte of the multiplicand, is multiplied by the multiplier (200) (S8), the value of the D register is added to the result of the calculation to update the result of the calculation (S9), and the result of the calculation is stored in the main RAM 500c as a dividend buffer (S10). Specifically, the command "LD A,B" on line 14 of FIG. 119 copies the value of the B register to the A register, the command "MUL HL,A,200" on line 15 stores the result of multiplying the value of the A register by 200 in the HL register, the command "ADDWB HL,D" on line 16 adds only the most significant byte (the value of the D register) of the DE register set by the command "EX DE,HL" on line 13 to the HL register containing the multiplication result, the command "LD A,E" on line 17 sets the least significant byte of the DE register set by the command "EX DE,HL" on line 13 in the A register, the command "LD (R_ERW_BF1),A" on line 18 stores the value of the A register, which is the least significant byte of the dividend, in the address "R_ERW_BF1", and the command "LD (R_ERW_BF1+1),HL" stores the value of the HL register, which is the upper two bytes of the dividend, in address "R_ERW_BF1+1".

Next, as shown in Fig. 118, the loop count is initialized to 8 and the quotient to 0 (S11), the quotient is doubled (S12), the most significant 2 bytes of the dividend and the most significant 2 bytes of the divisor are read (S13), and it is determined whether the most significant 2 bytes of the dividend are less than the most significant 2 bytes of the divisor (S14). If the most significant 2 bytes of the dividend are less than the most significant 2 bytes of the divisor (YES in S14), the process moves to step S20. Specifically, the command "LD BC, 8*256+0" on line 20 of FIG. 119 sets 8 to the B register, which indicates the number of loops, and 0 to the C register, which indicates the quotient; the command "SLA C" on line 22 shifts the value of the C register one bit to the left (0 is entered in the MSB); the command "LD HL, R_ERW_BF1+1" on line 23 adds 1 to the value of the address "R_ERW_BF1" storing the dividend (the product of the number of prize balls multiplied by the multiplier) and reads the value into the HL register; the command "LD DE, (HL+3)" on line 24 reads the upper two bytes of the divisor stored in the address "R_ERW_BF2," which is three bytes higher than the address "R_ERW_BF1" storing the dividend, into the DE register; and the command "JCP "C, (HL), DE, E_SHYMT_55" compares the value of the address indicated by the HL register (the most significant two bytes of the dividend) with the value of the DE register (the most significant two bytes of the divisor), and if the carry flag is set, i.e., if the most significant two bytes of the dividend are less than the most significant two bytes of the divisor, it moves to the index "E_SHYMT_55" on line 38.

Next, as shown in FIG. 118, if the upper two bytes of the dividend are equal to or greater than the upper two bytes of the divisor (NO in S14), the lower byte of the divisor and the lower byte of the dividend are read for the calculation in the subsequent stage (S15), and in step S14, it is determined whether the upper two bytes of the dividend are not equal to the upper two bytes of the divisor, that is, whether the upper two bytes of the dividend are greater than the upper two bytes of the divisor (S16). If the upper two bytes of the dividend are not equal to the upper two bytes of the divisor (YES in S16), the process moves to step S18, and if the upper two bytes of the dividend are equal to the upper two bytes of the divisor (NO in S16), the process moves to step S18. If the lower byte of the dividend is less than the lower byte of the divisor (YES in S17), the process moves to step S20, and if the lower byte of the dividend is equal to or greater than the lower byte of the divisor (NO in S17), the process moves to step S18. Specifically, the command "LD L, LOW R_ERW_BF2" on line 26 of FIG. 119 reads the lowest byte of the address "R_ERW_BF2" storing the divisor into the L register (note that the highest byte of "R_ERW_BF2" has already been stored in the H register by the command "LD HL, R_ERW_BF1+1" on line 23), the command "LD A, (HL-3)" on line 27 reads the lowest byte of the dividend stored in the address "R_ERW_BF1", which is three bytes lower than the address "R_ERW_BF2" storing the divisor, into the A register, and the command "JR NZ, E_SHYMT_50" on line 28 moves to the index "E_SHYMT_50" on line 31 if the zero flag has not been set by the execution of the command on line 25, and the command "CP A, (HL)" compares the value of the A register (the lowest byte of the dividend) with the value of the address indicated by the HL register (the lowest byte of the divisor), and the command "JR C, E_SHYMT_55" on line 30 moves to the index "E_SHYMT_55" on line 38 if the carry flag is set, i.e., if the lowest byte of the dividend is less than the lowest byte of the divisor.

Next, as shown in FIG. 118, if the dividend is greater than or equal to the divisor, the divisor is subtracted from the dividend, the subtraction result is updated as the new dividend (S18), and 1 is added to the quotient (S19). Specifically, the command "SUB A, (HL)" on line 32 of FIG. 119 subtracts the value of the lowest byte of the divisor indicated by the HL register from the value of the A register in which the lowest byte of the dividend is stored, the command "LD (HL-3), A" on line 33 stores the lowest byte of the updated dividend, which is the result of the subtraction, in the address indicating the dividend located three bytes below the address in which the divisor indicated by the HL register is stored, the command "LD HL, (HL-2)" on line 34 reads into the HL register the address indicating the highest 2 bytes of the dividend located two bytes below the address in which the divisor indicated by the HL register is stored, the command "SBC HL, DE" on line 35 subtracts the value of the DE register in which the highest 2 bytes of the divisor are stored from the value of the HL register in which the highest 2 bytes of the dividend are stored, and the command "LD (R_ERW_BF1+1),HL" stores the upper two bytes of the updated dividend, which is the result of the subtraction, in the upper two bytes of the dividend indicated by the address "R_ERW_BF1", and the command "INC C" on line 37 increments the value of the C register, which indicates the quotient, by 1.

Next, as shown in FIG. 118, the divisor is divided by 2 (bit shift to the right) and updated as a new divisor (S20), the loop count is subtracted, and it is determined whether the loop count is not 0 (S21). If it is not 0 (YES in S21), the processing from step S12 is repeated; if it is 0 (NO in S21), rounding is performed (S22), the base value is set in the main RAM 500c (S23), and the processing ends. Specifically, the command "LD HL, R_ERW_BF2+2" on line 39 of FIG. 119 reads the address "R_ERW_BF2+2" indicating the most significant byte of the divisor into the HL register, the command "SRL (HL)" on line 40 bit-shifts the value of the address indicated by the HL register (the third byte of the divisor) to the right by one bit, the command "DEC HL" on line 41 decrements the value of the HL register by one, the command "RR (HL)" on line 42 bit-shifts the value of the address indicated by the HL register (the second byte of the divisor) to the right by one bit, the command "DEC HL" on line 43 decrements the value of the HL register by one, the command "RR (HL)" on line 44 bit-shifts the value of the address indicated by the HL register (the first byte of the divisor) to the right by one bit, and the command "DJNZ" on line 45 The value of the B register, which indicates the number of loops, is decremented by 1 by "E_SHYMT_45", and if the value is not 0, it moves to the index "E_SHYMT_45" on the 21st line. On the other hand, when the loop count becomes 0, the command "LD A, C" on line 46 of FIG. 119 copies the value of the C register indicating the quotient to the A register, the command "SRL A" on line 47 bit-shifts the value of the address indicated by the A register by 1, the command "ADC A, 0" on line 48 adds 1 to the A register if the carry flag is set by the command "SRL A" on line 47, that is, if the decimal point is 0.5 or more, the command "LD HL, R_ERW_BAS" on line 50 sets the address "R_ERW_BAS" indicating the base value in the HL register, and the command "LD (HL), A" on line 51 stores the value of the A register indicating the base value in the address "R_ERW_BAS".

This fifth calculation example makes it possible to derive a base value using only simple calculations such as addition, subtraction, and multiplication, and by repeatedly subtracting a number multiplied by a power of 2.

In this command example, as shown in FIG. 119, the total command size is 97 bytes, and the simple total number of cycles is 136/131 cycles. The actual number of cycles is as follows. That is, in this process, eight loops are performed from the next command (line 22) after the index "E_SHYMT_45" to the command "DJNZ E_SHYMT_45" on line 45. In this case, if the command "JCP C, (HL), DE, E_SHYMT_55" on line 25 is used to move to the index "E_SHYMT_55" in all eight loops, the commands on lines 26 to 37 are not executed, so the number of cycles is the minimum of 367 (54 + 38 (first 7 loops) x 7 + 37 (8th loop) + 10). On the other hand, if the command "JCP C, (HL), DE, E_SHYMT_55" on the 25th line does not move to the index "E_SHYMT_55" in all loops, the number of cycles is maximum. However, due to the possible values, in the first and second loops, the command "JCP C, (HL), DE, E_SHYMT_55" on line 25 does not move, but the command "JR NZ, E_SHYMT_50" on line 28 does, and in the third to eighth loops, the command "JCP C, (HL), DE, E_SHYMT_55" on line 25, the command "JR NZ, E_SHYMT_50" on line 28, and the command "JR C, E_SHYMT_55" on line 30 do not move at most. Taking this into consideration, the maximum number of cycles is 601 (54 + 65 (first two loops) x 2 + 68 (subsequent five loops) x 5 + 67 (eighth loop) + 10). Therefore, the actual total number of cycles is in the range of 367 to 601 cycles.

(Sixth example of calculation: Number of winning balls × multiplier ÷ number of outs)
Fig. 120 is a flow chart showing a specific process for implementing the sixth operation example using a 16-bit multiplier and a 32-bit divider, and Fig. 121 is a diagram showing an example of a specific command for implementing the sixth operation example. The numerical values of step S in the explanation of Fig. 120 are used only in the explanation of this figure.

As shown in FIG. 120, first, the number of prize balls is set in the multiplicand register (S1), and the multiplier "200" is set in the multiplier register (S2). Specifically, the command "LD HL, (R_ERW_TJS)" on the first line of FIG. 121 reads the value of the normal prize ball counter (number of prize balls) indicated by the address "R_ERW_TJS" into the HL register, the command "OUT (LOW @MULA16_)" on the second line makes the value of the U register the upper byte of the address and the address "@MULA16_" the lower byte, and outputs the value of the HL register to the multiplier setting register indicated by that address, the command "EX DE,HL" on the third line copies the value of the HL register to the DE register, the command "LD A, 200" on the fourth line sets the multiplier "200" in the A register, and the command "OUT (LOW By "@MULB16_), A", the value of the U register is set as the upper byte of the address, and the address "@MULB16_" is set as the lower byte, and the value of the A register is output to the multiplier setting register indicated by that address. Note that the upper byte of the multiplier setting register "@MULB16_" is set to "00H" as the default value.

Next, as shown in FIG. 120, assuming that the prize ball counter is normally 0, the initial value of the base value is set to 0 (S3), and it is determined whether the number of outs is 0 or not (S4). If it is 0 (YES in S4), the result will not change even if it is multiplied by the multiplier (it is 0), so it moves to step S13; if it is not 0 (NO in S4), the base value is set to 100 (S5), and it is determined whether the number of outs is less than the number of prize balls (S6), and if the number of outs is less than the number of prize balls (YES in S6), it moves to step S13. Specifically, the command "XOR A, A" on line 6 of FIG. 121 sets the value of the A register, which indicates the base value, to 0, the command "LD HL, (R_ERW_TJO)" on line 7 reads the value of the normal out counter (number of outs) indicated by the address "R_ERW_TJO" into the HL register, the command "JR TZ, E_SHYMT_60" on line 8 moves the value of the HL register to the index "E_SHYMT_60" on line 23 if it is 0, the command "LD A, 100" on line 9 sets the A register, which indicates the base value, to an initial value of 100, and the command "JCP "C,HL,DE,E_SHYMT_60" compares the value of the HL register (number of outs) with the value of the DE register (number of winning balls), and if the carry flag is set, i.e., if the number of outs is less than the number of winning balls, it moves to the index "E_SHYMT_60" on the 23rd line.

Next, as shown in FIG. 120, the out number is set in the divisor setting register (S7), the multiplication result by the 16-bit multiplier is read into the HLA register (HL register and A register) (S8), and it is set in the dividend setting register (S9). Specifically, the command "OUT (LOW @DIVB32_), HL" on line 11 of FIG. 121 sets the value of the U register to the most significant byte of the address, the address "@DIVB32_" to the least significant byte, and outputs the value of the HL register to the divisor setting register "@DIVB32_" indicated by that address. The command "IN A, (LOW @MUL32__" on line 12 sets the value of the U register to the most significant byte of the address, the address "@MULB32__" to the least significant byte, and reads the 1-byte value of the multiplication result register indicated by that address into the A register. The command "IN HL, (LOW @MUL32__+1" on line 13 sets the value of the U register to the most significant byte of the address, the address "@MULB32__+1" to the least significant byte, and reads the 2-byte value of the multiplication result register indicated by that address into the HL register. The command "OUT The command "OUT (LOW @DIVA32_+0), A" sets the value of the U register as the most significant byte of the address, the address "@DIVA32_" as the least significant byte, and outputs the value of the A register to the dividend setting register "@DIVA32_" indicated by that address, and the command on line 15, "OUT (LOW @DIVA32_+1), HL" sets the value of the U register as the most significant byte of the address, the address "@DIVA32_+1" as the least significant byte, and outputs the value of the HL register to the dividend setting register "@DIVA32_+1" indicated by that address. In this way, the 16-bit multiplier is operated and the multiplication result is stored in the multiplication result register.

Next, as shown in FIG. 120, the division is waited for (S10), and after a predetermined time has elapsed, the calculation result is read into the A register (S11), rounding is performed (S12), the base value is set in the main RAM 500c (S13), and the process is terminated. Specifically, the "NOP" command on lines 16 to 19 of FIG. 121 consumes four cycles of time, the "IN A, (LOW @DIV32___+0)" command on line 20 reads the result of the calculation from the divider into the A register, the "SRL A" command on line 21 bit-shifts the value of the address indicated by the A register by one to the right, the "ADC A,0" command on line 22 adds 1 to the A register if the carry flag is set by the "SRL A" command on line 21, i.e., if the decimal point is 0.5 or more, the "LD HL,R_ERW_BAS" command on line 24 sets the address "R_ERW_BAS" indicating the base value in the HL register, and the "LD (HL),A" command on line 25 stores the value of the A register indicating the base value in the address "R_ERW_BAS".

Here, in this command example, as shown in FIG. 121, the total command size is 49 bytes, and the simple total number of cycles is 68/66 cycles.

As explained above, when comparing the fifth calculation example for deriving a base value with the sixth calculation example for deriving a base value, both the total command size and the simple total number of cycles are smaller in the sixth calculation example using a 16-bit multiplier and a 32-bit divider. Therefore, when calculating the base value in a pachinko machine, it is preferable to use a 16-bit multiplier and a 32-bit divider, as explained using Figures 120 and 121.

As explained above, according to this embodiment, by suppressing the increase in processing load, it is possible to shorten the prohibited period of timer interrupts, and it is possible to stabilize the operation of the gaming machine while properly obtaining gaming information.

In the above-described embodiment, in the fourth and sixth calculation examples, "NOP", which consumes one cycle of time while waiting for division by a 32-bit divider, is used four times in succession. However, this is not limited to the above case, and other commands may be used as long as four cycles are secured. For example, a two-cycle command with a command size of one byte may be used two times in succession, or a four-cycle command with a command size of one byte, or a four-cycle command with a command size of two bytes may be used. In this way, the command size can be reduced.

In the above-mentioned embodiment, the first calculation example using only an 8-bit MUL command and the second calculation example using a 16-bit multiplier are given as calculation examples for executing the number of payouts of the reel × the multiplier, and the third calculation example using repeated subtraction of a number multiplied by a power of 2 and the fourth calculation example using a 32-bit divider are given as calculation examples for executing the multiplication result ÷ total payout. In the above-mentioned embodiment, after performing the number of payouts of the reel × the multiplier, the multiplication result ÷ total payout is executed using the multiplication result, so that the first or second calculation example is combined with the third or fourth calculation example to perform the calculation. The combination of such calculation examples can be set arbitrarily. For example, the combination of the first and third calculation examples, the combination of the first and fourth calculation examples, the combination of the second and third calculation examples, and the combination of the second and fourth calculation examples can be adopted. In addition, both the fifth and sixth calculation examples can be divided into the number of payouts of the reel × multiplier and the multiplication result ÷ total payouts, and the combination of such calculation examples can be set arbitrarily. For example, in addition to the combination of the number of payouts of the reel × multiplier of the fifth calculation example and the multiplication result ÷ total payouts of the fifth calculation example, and the combination of the number of payouts of the reel × multiplier of the sixth calculation example and the multiplication result ÷ total payouts of the sixth calculation example, the combination of the number of payouts of the reel × multiplier of the fifth calculation example and the multiplication result ÷ total payouts of the sixth calculation example, and the combination of the number of payouts of the reel × multiplier of the sixth calculation example and the multiplication result ÷ total payouts of the fifth calculation example can be adopted.

In the above embodiment, various calculations (first to fourth calculation examples) were performed using the role ratio of the slot machine 400 as an example, but it goes without saying that the present invention can be applied to other ratios of the slot machine 400 (advantageous zone ratio, role ratio with instruction, consecutive role ratio for 6000 plays, role ratio for 6000 plays, consecutive role ratio for total cumulative, role ratio for total cumulative, role etc. state ratio). In addition, the present invention can be applied not only to the slot machine 400 but also to the base value of a pachinko machine, as explained using the fifth and sixth calculation examples.

<Module and command description>
Hereinafter, for each of the above-mentioned processes (modules), specific instruction codes (command groups) for implementing the processes will be explained in units of commands that are primarily used within the modules.

<Command "ADDALD">
The BYTESEL module is a general-purpose module for byte data selection processing, i.e., offsetting the selected address and reading out a 1-byte value stored at the offset address. A general-purpose module is a subroutine of the same processing used in executing a program, and is a module that is frequently called by other modules. General-purpose modules are often placed near the lowest address 0000H on the memory map shown in FIG. 5 (or FIG. 102). This is because by placing a general-purpose module that is frequently called near 0000H, it can be called using not only the command "CALL" used for calling, but also another command "RST". Here, an example is given of placing the BYTESEL module at 0008H on the memory map.

Here, the command "RST" is a command that can call one of multiple addresses (0008H, 0010H, 0018H, 0020H, 0028H, 0030H, 0038H, 0040H) that are low-numbered addresses near 0000H in the memory map and are spaced 8 bytes apart. The command "RST" has the same execution cycle of "4" as the normal command "CALL" used for calling, but the command size of the normal command "CALL" is "3", while the command size of the command "RST" is "1". Therefore, using the command "RST" can shorten the length of a program.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, and in any process, calls the BYTESEL module as a subroutine and executes the BYTESEL module. The BYTESEL module offsets the selected address by a specified value and holds the one-byte value stored at the offset address. In this way, a value according to the offset can be set.

Figure 122 is a flow chart showing the specific processing of the BYTESEL module. Here, as an optional process, a part of the LED_PRC module that executes the LED display setting process shown in S400-31 of Figure 26 will be explained. The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the explanation of this BYTESEL module, the first register is the HL register and the second register is the A register.

As shown in FIG. 122(a), in any process, the main CPU 300a sets an offset in the A register (S1), and sets the first address of the address group to be read in the HL register (S2). Then, it calls the BYTESEL module as a subroutine (S3).

As shown in FIG. 122(b), in the BYTESEL module, the main CPU 300a adds the value of the A register to the value of the HL register to update the HL register, and reads the one-byte value stored in the address indicated by the HL register into the A register (S4). Next, the main CPU 300a sets a zero flag (first zero flag) depending on whether the value of the A register is 0 (zero) or not (S5). Then, the BYTESEL module is terminated and the process returns to the routine one level above (S6).

Figures 123 and 124 are explanatory diagrams for explaining an example of commands for implementing the BYTESEL module. Of these, Figure 123(a) shows a group of commands for an arbitrary process that calls the BYTESEL module, Figure 123(b) shows a group of commands for the BYTESEL module, and Figure 123(c) shows the arrangement of a group of 1-byte data in the program data of main ROM 300b. The flowchart shown in Figure 122 is implemented, for example, by the program shown in Figure 123.

The command "LDQ A, (LOW R_TZ1_DSP)" on the first line of FIG. 123(a) sets the value of the Q register to the upper byte of the address, the value of the lower byte of the address "R_TZ1_DSP" to the lower byte of the address, and reads the value stored at that address (counter value of the special symbol 1 display symbol counter) to the A register. This command on the first line corresponds to step S1 in FIG. 122(a). The command "LD HL, D_DSP_TZ" on the second line sets the top address "D_DSP_TZ" of the data group of the special symbol display LED output data table from which the data is read, in the HL register. This command on the second line corresponds to step S2 in FIG. 122(a). Then, the command "RST BYTESEL" on the third line calls the BYTESEL module as a subroutine. The command on the third line corresponds to step S3 in Figure 122 (a).

The index "BYTESEL:" on the first line of FIG. 123(b) indicates the starting address of the BYTESEL module. The command "ADDWB HL,A" on the second line adds the value of the A register to the value of the HL register, updating the value of the HL register. Then, the command "LD A,(HL)" on the third line reads one byte value stored at the address indicated by the HL register into the A register. These commands on the second and third lines correspond to step S4 in FIG. 122(b). The command "OR A,A" on the fourth line calculates the logical sum of the value of the A register and the value of the A register. Since this command "OR A,A" is the logical sum of the values of the A register, the value of the A register does not change. On the other hand, the zero flag (first zero flag and second zero flag) can be changed by the logical sum. That is, in this BYTESEL module, it is possible to determine whether the value of the A register that has been read is zero or not by the zero flag. The command on line 4 corresponds to step S5 in FIG. 122(b). The command "RET" on line 5 returns to the routine one level above. The command on line 5 corresponds to step S6 in FIG. 122(b).

The table starting from the index "D_DSP_TZ" in FIG. 123(c) shows, for example, information on the special 1 big win symbol and the special 2 big win symbol. For example, when the variable "R_TZ1_DSP", i.e., the counter value of the special symbol 1 display symbol counter, is "02H", as shown in FIG. 124, the value (A8H) stored in the address (the third address from the lowest) obtained by adding the value of the A register (e.g., 02H) to the selected address (e.g., 1250H) in the table (2AH, A2H, A8H, 36H...5DH, FDH) described in the program data of the main ROM 300b can be read into the A register. In this way, it is possible to obtain the desired 1-byte value in a table in which multiple values of the same byte length are arranged in succession.

The BYTESEL module is called as a subroutine from multiple modules. For example, the SBCMDST module executes the subcommand group set process shown in step S100-55 of FIG. 23, the LED_PRC module executes the LED display setting process shown in step S400-31 of FIG. 26, the SOL_SET module executes the solenoid data setting process (solenoid output image synthesis process) shown in step S400-33 of FIG. 26, the MEM_DAT module executes the reserved ball count bit data synthesis process, which is a subroutine of the LED display setting process shown in step S400-31 of FIG. 26, the TDN_PAS module executes the count switch passing process (second start port passing process, large prize port passing process) shown in steps S530 and S540 of FIG. 28, the TZ_STP module executes the special pattern stop pattern display process shown in step S630 of FIG. 43, and the large prize port shown in step S720 of FIG. 47. It is called from the TD_OPN module which executes the opening control process, the FSPNTMR module which executes the normal symbol change time setting process (normal symbol change time determination process) shown in step S810-11 of FIG. 52, the THPTSEL module which executes the special symbol change pattern determination process (special symbol change number determination process) shown in step S612 of FIG. 39, the TRSVSEL module which executes the reserve area setting process shown in step S610-17 of FIG. 37, the TENDTMR module which executes the ending time setting process shown in step S730-9 of FIG. 48, the ZUGOFFS module which executes the symbol offset acquisition process (not shown) which is executed in step S630-13 of FIG. 43 (special electric role maximum number of times operation setting process), the RGETCHK module which executes the acquisition time performance determination process shown in step S536 of FIG. 33, etc.

In this way, the total command size of the BYTESEL module commands shown in FIG. 123(b) is 1 byte of the command "ADDWB HL, A" on the second line + 1 byte of the command "LD A, (HL)" on the third line + 1 byte of the command "OR A, A" on the fourth line + 1 byte of the command "RET" on the fifth line = 4 bytes, and the total execution cycle is 1 cycle on the second line + 2 cycles on the third line + 1 cycle on the fourth line + 3 cycles on the fifth line = 7 cycles. By providing such a BYTESEL module, it is possible to cover the command size of 1 byte with the command "RST BYTESEL" without performing byte data selection processing within each of the above-mentioned modules, so it is possible to shorten the command and ensure the capacity of the control area for performing game control processing.

Figure 125 is an explanatory diagram for explaining another example of commands for implementing the BYTESEL module. Here, the commands of the BYTESEL module in Figure 123(b) are replaced with the commands of the BYTESEL module in Figure 125(b), and the commands of any other process that calls the BYTESEL module in Figure 123(a) and the 1-byte data group in the program data of main ROM 300b in Figure 123(c) are used as is as in Figures 125(a) and 125(c). Here, as in Figures 125(a) and 125(c), explanations of processes that are substantially the same as those in Figures 123(a) and 123(c) are omitted, and only the different processes in Figure 125(b) are explained.

The index "BYTESEL:" on the first line of FIG. 125(b) indicates the starting address of the BYTESEL module. The command "ADDALD A, (HL)" on the second line adds the value of the A register to the value of the HL register, and the one-byte value stored at the address indicated by the HL register after the addition is read into the A register. This command on the second line corresponds to step S4 in FIG. 122(b). The command "OR A, A" on the third line calculates the logical sum of the value of the A register and the value of the A register. This logical sum can change the zero flags (the first zero flag and the second zero flag). In other words, in the BYTESEL module, it becomes possible to determine whether the value of the A register that has been read is zero or not by the zero flag. This command on the third line corresponds to step S5 in FIG. 122(b). Then, the command "RET" on the fourth line returns to the routine one step above. The command on the fourth line corresponds to step S6 in Figure 122 (b).

The command "ADDALD A, (HL)" updates the HL register by adding the value in the A register to the value in the HL register, and reads the value stored in the address indicated by the HL register into the A register. The command size of this command is "1", and the execution cycle is "3".

The total command size of the commands in the BYTESEL module in Figure 125(b) is 1 byte of the command "ADDALD A, (HL)" on line 2 + 1 byte of the command "OR A, A" on line 3 + 1 byte of the command "RET" on line 4 = 3 bytes, and the total execution cycles are 3 cycles on line 2 + 1 cycle on line 3 + 3 cycles on line 4 = 7 cycles. Therefore, it can be seen that the total command size has been reduced by 1 byte compared to the case in Figure 123(b). This BYTESEL module makes it possible to further shorten commands and ensure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing FIG. 123(b) with FIG. 125(b), a group of commands that occupies two lines (lines 2 and 3) in FIG. 123(b) can be represented in one line (line 2) in FIG. 125(b), making it possible to reduce the number of commands and lighten the design load.

Figure 126 is an explanatory diagram for explaining yet another example of commands for implementing the BYTESEL module. Here, the command group for any process that calls the BYTESEL module in Figure 125(a) and the command group for the BYTESEL module in Figure 125(b) are replaced with the command group for any process in Figure 126(a), and the other 1-byte data group in the program data of main ROM 300b in Figure 125(c) is used as is as in Figure 126(b). Here, as in Figure 126(b), the description of the process that is substantially the same as Figure 125(c) is omitted, and only the different process in Figure 126(a) is described.

The command "LDQ A, (LOW R_TZ1_DSP)" on the first line of FIG. 126(a) sets the value of the Q register to the upper byte of the address, the value of the lower byte of the address "R_TZ1_DSP" to the lower byte of the address, and the value stored at that address is read into the A register. This command on the first line corresponds to step S1 in FIG. 122(a). The command "LD HL, D_DSP_TZ" on the second line sets the top address "D_DSP_TZ" of the 1-byte data group to be read from in the HL register. This command on the second line corresponds to step S2 in FIG. 122(a). Then, the command "ADDALD A, (HL)" on the third line adds the value of the A register to the value of the HL register, and the 1-byte value stored at the address indicated by the HL register after the addition is read into the A register. The command on the third line corresponds to step S4 in Figure 122 (b).

In the example of FIG. 126, the command "RST BYTESEL" corresponding to step S3 in FIG. 122(a), the command "OR A,A" corresponding to step S5 in FIG. 122(b), and the command "RET" corresponding to step S6 in FIG. 122(b) are omitted.

The total command size of the command group for any process in FIG. 126(a) is 2 bytes for the command "LDQ A, (LOW R_TZ1_DSP)" on the first line + 3 bytes for the command "LD HL, D_DSP_TZ" on the second line + 1 byte for the command "ADDALD A, (HL)" on the third line = 6 bytes, and the total execution cycles are 2 cycles for the first line + 3 cycles for the second line + 3 cycles for the third line = 8 cycles.

In contrast, the total command size of any processing and the BYTESEL module commands in Figures 125(a) and 125(b) is 2 bytes of the command "LDQ A, (LOW R_TZ1_DSP)" on the first line of Figure 125(a) + 3 bytes of the command "LD HL, D_DSP_TZ" on the second line + 1 byte of the command "RST BYTESEL" on the third line + 1 byte of the command "ADDALD A, (HL)" on the second line of Figure 125(b) + 1 byte of the command "OR A, A" on the third line + 1 byte of the command "RET" on the fourth line = 9 bytes, and the total execution cycles are 2 cycles on the first line of Figure 125(a) + 3 cycles on the second line + 4 cycles on the third line + 3 cycles on the second line + 1 cycle on the third line + 3 cycles on the fourth line of Figure 125(b) = 16 cycles. Therefore, in the example of FIG. 126, the total command size is reduced by 3 bytes and the total execution cycles are reduced by 8 cycles compared to the case of FIG. 125. In this way, by embedding the BYTESEL module itself as a command in any process, it is possible to further shorten the command and reduce the processing load, and to ensure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 125 and 126, the command group that occupies four lines (lines 1 to 4) in Figure 125(b) does not need to be described in Figure 126, making it possible to reduce the number of commands themselves and lighten the design load.

The BYTESEL module is also a general-purpose module that is the target of the "RST" command, but by omitting this general-purpose module, valuable general-purpose module space can be freed up and other modules can be placed in that space. This allows for more efficient use of resources.

However, in the example of FIG. 126, by omitting the command "OR A, A", it becomes impossible to change the first zero flag. In other words, it becomes impossible to determine whether the value of the A register that has been read is zero or not using the first zero flag. However, if there is no need to determine whether the value of the A register is zero or not after the byte data selection process, this function is not required in the first place. Also, the command "ADDALD A, (HL)" can change the second zero flag simply by executing that command. Therefore, if it is necessary to determine whether the value of the A register is zero or not, it is possible to determine whether the value of the A register is zero or not by referring to the second zero flag.

This BYTESEL module is used not only in pachinko machines, but also in slot machines, for example, as a module for performing register addition processing.

<Command "ADDALDW">
The WORDSEL module is a general-purpose module for word data selection processing, i.e., offsetting the selected address and setting the 2-byte value stored in the offset address. Here, an example will be given in which the WORDSEL module is placed at 0018H on the memory map.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, and in any process, calls the WORDSEL module as a subroutine and executes the WORDSEL module. The WORDSEL module offsets the selected address by a specified value and holds the 2-byte value stored at the offset address. In this way, a value according to the offset can be set.

Figure 127 is a flow chart showing the specific processing of the WORDSEL module. Here, as an optional process, a part of the FUT_PRC module that executes the normal game management process shown in step S800 of Figure 51 will be explained. The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the explanation of this WORDSEL module, the first register is the HL register and the second register is the A register.

As shown in FIG. 127(a), in any process, the main CPU 300a sets an offset in the A register (S1), and sets the first address of the address group to be read in the HL register (S2). Then, it calls the WORDSEL module as a subroutine (S3).

As shown in FIG. 127(b), in the WORDSEL module, the main CPU 300a updates the HL register by adding the value of the A register twice to the value of the HL register, or by adding twice the value of the A register (S4), and reads the 2-byte value stored at the address indicated by the HL register into the HL register (S5). Next, the main CPU 300a sets the value of the L register into the A register (S6). Then, the WORDSEL module is terminated and the process returns to the routine one level above (S7).

When a 2-byte value is set in the HL register by the WORDSEL module, the main CPU 300a uses the value in the HL register to carry out various processes. For example, here, as shown in FIG. 127(a), the address indicated by the HL register is called as a subroutine (S8).

Figures 128 and 129 are explanatory diagrams for explaining an example of commands for implementing a WORDSEL module. Of these, Figure 128(a) shows a group of commands for an arbitrary process that calls the WORDSEL module, Figure 128(b) shows a group of commands for the WORDSEL module, and Figure 128(c) shows the arrangement of a 2-byte data group in the program data of main ROM 300b. The flowchart shown in Figure 127 is implemented, for example, by the program shown in Figure 128.

The command "LDQ A, (LOW R_FUT_PHS)" on the first line of FIG. 128(a) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_TZ1_DSP" to the lower byte of the address, and reads the value stored at that address into the A register. This command on the first line corresponds to step S1 in FIG. 127(a). The command "LD HL, J_JMP_FUT" on the second line sets the top address "J_JMP_FUT" of the 2-byte data group to be read from in the HL register. This command on the second line corresponds to step S2 in FIG. 127(a). And the command "RST WORDSEL" on the third line calls the WORDSEL module as a subroutine. This command on the third line corresponds to step S3 in FIG. 127(a).

The index "WORDSEL:" on the first line of FIG. 128(b) indicates the starting address of the WORDSEL module. The command "ADDWB HL,A" on the second line adds the value of the A register to the value of the HL register, updating the HL register. Furthermore, the command "ADDWB HL,A" on the third line adds the value of the A register to the value of the HL register, updating the HL register. The reason why the value of the A register is added twice to the HL register is because the value from which it is read is a 2-byte value. In other words, because data is assigned in 2-byte units to the table, it is necessary to offset the address by 2 in order to read the data. Note that here, the command "ADDWB HL,A" is executed twice to add the value of the A register to the HL register twice, but this can also be achieved by using the command "ADD A,A" instead of the command "ADDWB HL,A" on the second line, doubling the value of the A register before adding it to the HL register. The commands on the second and third lines correspond to step S4 in Figure 127 (b).

Then, the command "LD HL, (HL)" on the fourth line of FIG. 128(b) reads the two-byte value stored in the address indicated by the HL register into the HL register. This command on the fourth line corresponds to step S5 in FIG. 127(b). The command "LD A, L" on the fifth line sets the value of the L register in the A register of the HL register. In this way, the lowest byte of the value of the HL register is set in advance in the A register. This command on the fifth line corresponds to step S6 in FIG. 127(b). Then, the command "RET" on the sixth line returns to the routine one level above. This command on the sixth line corresponds to step S7 in FIG. 127(b).

The table starting from the index "J_JMP_FUT" in FIG. 128(c) indicates, for example, an address indicating the state of normal play. For example, when the value of the variable "R_FUT_PHS", i.e., the normal play management phase, is "02H", as shown in FIG. 129, the value stored in the address (fifth and sixth addresses from the lowest) obtained by adding the value obtained by multiplying the value of the A register by two (e.g., 04H) to the selected address (e.g., 1270H) in the table (FZ_STA, FZ_SPN, FZ_STP, FD_PRE, FD_OPN, FD_END) described in the program data of the main ROM 300b, here 0832H (FZ_STP), can be held in the HL register. In this way, it is possible to obtain the desired 2-byte value in a table in which multiple values of the same byte length are consecutively arranged.

Here, FZ_STA indicates the address value of the normal symbol change waiting process shown in step S810 of FIG. 52, FZ_SPN indicates the address value of the normal symbol change processing shown in step S820 of FIG. 53, FZ_STP indicates the address value of the normal symbol stop symbol display processing shown in step S830 of FIG. 54, FD_PRE indicates the address value of the normal electric device prize opening pre-processing shown in step S840 of FIG. 55, FD_OPN indicates the address value of the normal electric device prize opening opening control processing shown in step S850 of FIG. 57, FD_CLS indicates the address value of the normal electric device prize opening closing enable processing shown in step S860 of FIG. 58, and FD_END indicates the address value of the normal electric device prize opening end wait processing shown in step S870 of FIG. 59.

Then, the command "CALL (HL)" on the fourth line of FIG. 128(a) calls the acquired 2-byte value, i.e., the address value corresponding to the normal game state. For example, as described above, when 0832H (FZ_STP) is read into the HL register in the table, the command "CALL (HL)" calls the address indicated by "FZ_STP", and the normal stop symbol display process is executed. This command on the fourth line corresponds to step S8 in FIG. 127(a).

The WORDSEL module is called as a subroutine from multiple modules. For example, the DBLBYTE module executes the double byte selection process (not shown) executed in the special symbol stop symbol display process shown in step S630 of FIG. 43, the SBC_OUT module executes the subcommand transmission process shown in step S100-65 of FIG. 23, the DYM_OUT module executes the dynamic port output process shown in step S400-5 of FIG. 26, the FUT_PRC module executes the normal game management process shown in step S800 of FIG. 51, the TOK_PRC module executes the special game management process shown in step S600 of FIG. 36, and the TDN_PRC module executes the special electric role play management process in step S700 of FIG. 44. 31, a STA_PAS module which executes the second start gate passing process shown in step S530 of FIG. 31, a TDN_PAS module which executes the count switch passing process (large prize gate passing process) shown in step S540 of FIG. 34, a TZ_RGET module which executes the special symbol random number acquisition process shown in step S535 of FIG. 32, an FSPNTMR module which executes the normal symbol fluctuation time setting process, an FDNCHG module which executes the normal electric role prize gate opening/closing switching process shown in step S841 of FIG. 56, a TMEMSFT module which executes the special symbol memory area shift process shown in step S610-9 of FIG. THPTSEL module for executing pattern change pattern determination processing, TSPNTM module for executing special pattern change time setting processing shown in step S610-15 of the special pattern change waiting processing shown in step S610 of FIG. 37, TSTATMR module for executing opening time setting processing shown in step S630-15 of FIG. 43, TDNCHG module for executing large prize opening opening/closing switching processing shown in step S711 of FIG. 46, TCLSTMR module for executing large prize opening closing time setting processing shown in step S730-7 of FIG. 48, TENDTMR module for executing ending time setting processing shown in step S730-9 of FIG. It is called from the HPT_MOD module which executes the fluctuation pattern selection 2 process (fluctuation pattern number determination process) shown in 612-15, the HPT_PAT module which executes the fluctuation pattern selection 3 process (fluctuation pattern number determination process) shown in S612-15 of FIG. 39, the WORDJDG module which executes the word data determination process (not shown) executed in step S810-5 of FIG. 52, the RGETCHK module which executes the acquisition time performance determination process shown in step S536 of FIG. 33, the TEF_SEL module which executes the large prize opening closure effective time selection process which is a subroutine of the large prize opening closure effective time setting process shown in step S720-9 of FIG. 47, etc.

In this way, the total command size of the WORDSEL module commands shown in FIG. 128(b) is 1 byte of the command "ADDWB HL, A" on the second line + 1 byte of the command "ADDWB HL, A" on the third line + 2 bytes of the command "LD HL, (HL)" on the fourth line + 1 byte of the command "LD A, L" on the fifth line + 1 byte of the command "RET" on the sixth line = 6 bytes, and the total execution cycle is 1 cycle on the second line + 1 cycle on the third line + 4 cycles on the fourth line + 1 cycle on the fifth line + 3 cycles on the sixth line = 10 cycles. By providing such a WORDSEL module, it is possible to cover the command size of 1 byte with the command "RST WORDSEL" without performing word data selection processing in each of the above-mentioned modules, so it is possible to shorten the command and secure the capacity of the control area for performing game control processing.

Figure 130 is an explanatory diagram for explaining another example of commands for implementing the WORDSEL module. Here, the commands of the WORDSEL module in Figure 128(b) are replaced with the commands of the WORDSEL module in Figure 130(b), and the commands of any other process that calls the WORDSEL module in Figure 128(a) and the 2-byte data group in the program data of main ROM 300b in Figure 128(c) are used as is as in Figures 130(a) and 130(c). Here, as in Figures 130(a) and 130(c), explanations of processes that are substantially the same as those in Figures 128(a) and 128(c) are omitted, and only the different processes in Figure 130(b) are explained.

The index "WORDSEL:" on the first line of FIG. 130(b) indicates the starting address of the WORDSEL module. The command "ADDALDW HL, (HL)" on the second line adds the value of the A register to the value of the HL register twice, and the two-byte value stored at the address indicated by the HL register after the addition is read into the HL register. This command on the second line corresponds to steps S4 and S5 in FIG. 127(b). The command "LD A,L" on the third line sets the value of the L register in the A register of the HL register. In this way, the lowest byte of the value of the HL register is set in advance in the A register. This command on the third line corresponds to step S6 in FIG. 127(b). Then, the command "RET" on the fourth line returns to the routine one step above. This command on the sixth line corresponds to step S7 in FIG. 127(b).

Here, the command "ADDALDW HL, (HL)" updates the HL register by adding the value of the A register twice to the value of the HL register, and reads the value stored in the address indicated by the HL register after the addition into the HL register. The command size of this command is "2", and the execution cycle is "6".

Then, the command "CALL (HL)" on the fourth line of FIG. 130(a) calls the acquired 2-byte value, i.e., the address value corresponding to the normal game state. This command on the fourth line corresponds to step S8 in FIG. 127(a).

The total command size of the WORDSEL module commands in Figure 130(b) is 2 bytes of the command "ADDALDW HL, (HL)" on line 2 + 1 byte of the command "LD A,L" on line 3 + 1 byte of the command "RET" on line 4 = 4 bytes, and the total execution cycles are 6 cycles on line 2 + 1 cycle on line 3 + 3 cycles on line 4 = 10 cycles. Therefore, compared to the case in Figure 128(b), the total command size is reduced by 2 bytes. This WORDSEL module makes it possible to further shorten commands and ensure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing FIG. 128(b) with FIG. 130(b), a group of commands that occupies three lines (lines 2, 3, and 4) in FIG. 128(b) can be represented in one line (line 2) in FIG. 130(b), making it possible to reduce the number of commands and lighten the design load.

Figure 131 is an explanatory diagram for explaining yet another example of commands for implementing a WORDSEL module. Here, the command group for any process that calls the WORDSEL module in Figure 130(a) and the command group for the WORDSEL module in Figure 130(b) are replaced with the command group for any process in Figure 131(a), and the other 2-byte data group in the program data of main ROM 300b in Figure 130(c) is used as is as in Figure 131(b). Here, as in Figure 131(b), the description of the process that is substantially the same as in Figure 130(c) is omitted, and only the different process in Figure 131(a) is described.

The command "LDQ A, (LOW R_FUT_PHS)" on the first line of FIG. 131(a) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_FUT_PHS" to the lower byte of the address, and reads the value stored in that address into the A register. This command on the first line corresponds to step S1 in FIG. 127(a). The command on the second line, "LD HL
, J_JMP_FUT" sets the top address "J_JMP_FUT" of the 1-byte data group to be read in the HL register. This command on the second line corresponds to step S2 in FIG. 127(a). Then, the command on the third line "ADDALDW HL, (HL)" adds the value of the A register twice to the value of the HL register, and the 2-byte value stored in the address indicated by the HL register after the addition is read into the HL register. This command on the third line corresponds to steps S4 and S5 in FIG. 127(b). The command on the fourth line "CALL (HL)" calls the acquired 2-byte value, that is, the address value according to the normal game state. This command on the fourth line corresponds to step S8 in FIG. 127(a).

In the example of FIG. 131, the command "RST WORDSEL" corresponding to step S3 in FIG. 127(a), the command "LD A,L" corresponding to step S6 in FIG. 127(b), and the command "RET" corresponding to step S7 in FIG. 127(b) are omitted.

The total command size of any process in Figure 131(a) and the WORDSEL module command is 2 bytes of the command "LDQ A, (LOW R_FUT_PHS)" on the first line + 3 bytes of the command "LD HL, J_JMP_FUT" on the second line + 2 bytes of the command "ADDALDW HL, (HL)" on the third line + 2 bytes of the command "CALL (HL)" on the fourth line = 9 bytes, and the total execution cycles are 2 cycles on the first line + 3 cycles on the second line + 6 cycles on the third line + 5 cycles on the fourth line = 16 cycles.

In contrast, the total command size of any processing and WORDSEL module commands in Figures 130(a) and 130(b) is 2 bytes of the command "LDQ A, (LOW R_FUT_PHS)" on the first line of Figure 130(a) + 3 bytes of the command "LD HL, J_JMP_FUT" on the second line + 1 byte of the command "RST WORDSEL" on the third line + 2 bytes of the command "CALL (HL)" on the fourth line + 2 bytes of the command "ADDALDW HL, (HL)" on the second line of Figure 130(b) + 2 bytes of the command "LD A, L" 1 byte + command "RET" 1 byte on line 4 = 12 bytes, and the total execution cycles are 2 cycles on line 1 in FIG. 130(a) + 3 cycles on line 2 + 4 cycles on line 3 + 5 cycles on line 4 + 6 cycles on line 2 + 1 cycle on line 3 + 3 cycles on line 4 in FIG. 130(b) = 24 cycles. Therefore, in the example of FIG. 131, the total command size is reduced by 3 bytes and the total execution cycles are reduced by 8 cycles compared to the case of FIG. 130. In this way, by embedding the WORDSEL module itself as a command in any process, it is possible to further shorten the command and reduce the processing load, and to ensure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 130 and 131, the command group that occupies four lines (lines 1 to 4) in Figure 130(b) does not need to be described in Figure 131, making it possible to reduce the number of commands and lighten the design load.

The WORDSEL module is also a general-purpose module that is the target of the "RST" command, but by omitting such a general-purpose module, valuable general-purpose module space can be freed up and other modules can be placed in that space. This allows for more efficient use of resources.

However, in the example of Figure 131, the command "LD A, L" is omitted. Therefore, if it is necessary to set the value of the L register in the A register, it is necessary to add the command "LD A, L" separately. However, since the command "LD A, L" has a command size of "1" and an execution cycle of "1", the impact of adding such a command is small.

This WORDSEL module is used not only in pachinko machines, but also in slot machines, for example, in the CAL_MOD module for executing the state-specific module execution process shown in step S3100-21 of FIG. 98, and the HID_JUG module that transitions from the CAL_MOD module and executes the premonition start determination process.

Figure 132 is an explanatory diagram for explaining the CAL_MOD module. The CAL_MOD module shown in Figure 132 executes state-specific module execution processing, i.e., executes a module corresponding to the state.

At the stage of executing such a CAL_MOD module, the offset value is already held in a specified register (for example, the A register). The index "CAL_MOD:" on the first line of FIG. 132(a) indicates the start address of the CAL_MOD module. The command "LD HL, T_INT_PHASE" on the second line sets the start address "T_INT_PHASE" of the 2-byte data group to be read in the HL register. The command "ADD A, A" on the third line adds the value of the A register to the value of the A register, doubling the value of the A register. The value of the A register is doubled here because the value to be read is a 2-byte value. In other words, because data is assigned in units of 2 bytes to the table, it is necessary to offset the address by 2 in order to read the data. The command "ADDWB HL, A" on the fourth line adds the value of the A register to the value of the HL register, updating the HL register.

Then, the command "LD HL, (HL)" on the fifth line of Figure 132(a) reads the two-byte value stored at the address indicated by the HL register into the HL register. The command "JP (HL)" on the sixth line moves to the address indicated by the HL address.

Now, by replacing it with the command "ADDALDW", the command group in FIG. 132(a) can be changed to that in FIG. 132(b). The index "CAL_MOD:" on the first line of FIG. 132(b) indicates the starting address of the CAL_MOD module. The command "LD HL, T_INT_PHASE" on the second line sets the starting address "T_INT_PHASE" of the 2-byte data group to be read from in the HL register. The command "ADDALDW HL, (HL)" on the third line adds the value of the A register twice to the value of the HL register, and the 2-byte value stored in the address indicated by the HL register after the addition is read into the HL register. Then, the command "JP (HL)" on the fourth line moves to the address indicated by the HL address.

Here, the total command size of the commands of the CAL_MOD module shown in FIG. 132(a) is 3 bytes of the command "LD HL,T_INT_PHASE" on line 2 + 1 byte of the command "ADD A,A" on line 3 + 1 byte of the command "ADDWB HL,A" on line 4 + 2 bytes of the command "LD HL,(HL)" on line 5 + 2 bytes of the command "JP (HL)" on line 6 = 9 bytes, and the total execution cycles are 3 cycles on line 2 + 1 cycle on line 3 + 1 cycle on line 4 + 4 cycles on line 5 + 2 cycles on line 6 = 11 cycles. On the other hand, the total command size of the CAL_MOD module commands shown in FIG. 132(b) is 3 bytes of the command "LD HL, T_INT_PHASE" on the second line + 2 bytes of the command "ADDALDW HL, (HL)" on the third line + 2 bytes of the command "JP (HL)" on the fourth line = 7 bytes, and the total execution cycle is 3 cycles on the second line + 6 cycles on the third line + 2 cycles on the fourth line = 11 cycles. Therefore, by replacing the command group in FIG. 132(a) with the command group in FIG. 132(b), the total command size is reduced by 2 bytes. This replacement makes it possible to further shorten the commands and secure the capacity of the control area for performing game control processing.

Figure 133 is an explanatory diagram for explaining the HID_JUG module. The HID_JUG module shown in Figure 133 executes this precursor start determination process.

The index "HID_JUG:" on the first line of Figure 133 (a) indicates the starting address of the HID_JUG module. The command "LDQ A, (LOW _NMD_KND)" on the second line sets the value of the Q register to the most significant byte of the address, and the value of the least significant byte of the address "_NMD_KND" to the least significant byte of the address, and reads the value stored at that address (normal mode type) into the A register. The command "LD HL, T_DAT_PGM-2" on the third line sets the starting address of the 2-byte data group to be read (the value obtained by subtracting 2 from "T_DAT_PGM") into the HL register. The command "ADD A, A" on the fourth line adds the value of the A register to the value of the A register, doubling the value of the A register. The value of the A register is doubled here because the value to be read is a 2-byte value. That is, because data is assigned to the table in units of two bytes, the address must be offset by two to read the data. The command "ADDWB HL, A" on line 5 adds the value of the A register to the value of the HL register, updating the HL register. Then, the command "LD HL, (HL)" on line 6 of Figure 133(a) reads the 2-byte value stored at the address indicated by the HL register into the HL register.

If the command "ADDALDW" is substituted here, the command group in FIG. 133(a) can be changed to that in FIG. 133(b). The index "HID_JUG:" on the first line of FIG. 133(b) indicates the starting address of the HID_JUG module. The command "LDQ A, (LOW _NMD_KND)" on the second line sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "_NMD_KND" to the lower byte of the address, and reads the value stored at that address (normal mode type) into the A register. The command "LD HL, T_DAT_PGM-2" on the third line sets the starting address of the 2-byte data group to be read (the value obtained by subtracting 2 from "T_DAT_PGM") into the HL register. The command on the fourth line, "ADDALDW HL, (HL)," adds the value of the A register twice to the value of the HL register, and the two-byte value stored in the address indicated by the HL register after the addition is read into the HL register.

Here, the total command size of the commands of the HID_JUG module shown in FIG. 133(a) is 2 bytes of the command "LDQ A, (LOW _NMD_KND)" on line 2 + 3 bytes of the command "LD HL, T_DAT_PGM-2" on line 3 + 1 byte of the command "ADD A, A" on line 4 + 1 byte of the command "ADDWB HL, A" on line 5 + 2 bytes of the command "LD HL, (HL)" on line 6 = 9 bytes, and the total execution cycles are 2 cycles on line 2 + 3 cycles on line 3 + 1 cycle on line 4 + 1 cycle on line 5 + 4 cycles on line 6 = 11 cycles. On the other hand, the total command size of the HID_JUG module commands shown in FIG. 133(b) is 2 bytes of the command "LDQ A, (LOW _NMD_KND)" on the second line + 3 bytes of the command "LD HL, T_DAT_PGM-2" on the third line + 2 bytes of the command "ADDALDW HL, (HL)" on the fourth line = 7 bytes, and the total execution cycle is 2 cycles on the second line + 3 cycles on the third line + 6 cycles on the fourth line = 11 cycles. Therefore, by replacing the command group in FIG. 133(a) with the command group in FIG. 133(b), the total command size is reduced by 2 bytes. This replacement makes it possible to further shorten the commands and secure the capacity of the control area for performing game control processing.

<Command "INLD", "INLDTQR">
The RAMSET module is a general-purpose module for RAM set processing, that is, for setting a predetermined value (initial value) to a variable in the main RAM 300c. Here, an example in which the RAMSET module is located at 0020H on the memory map will be described.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, and in any process, calls the RAMSET module as a subroutine and executes the RAMSET module. The RAMSET module transfers multiple 1-byte values written in the program data in the main ROM 300b to an area in the work area of the main RAM 300c that holds multiple pieces of data treated as variables. In this way, the values of multiple variables are set. Here, the number of pieces of data to be transferred is simply referred to as the number of pieces of data.

Figure 134 is a flow chart showing the specific processing of the RAMSET module. Here, as an optional process, a part of the CPUINIT module that executes the CPU initialization process shown in step S100 of Figure 22 will be described. The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the explanation of this RAMSET module, the first register is the B register, the second register is the HL register, the first value is "1", and the second value is "2". It goes without saying that the first value and the second value can be set arbitrarily.

As shown in FIG. 134(a), in any process, the main CPU 300a sets the first address of a 1-byte data group that is to be transferred in the HL register (S1). Then, it calls the RAMSET module as a subroutine (S2).

As shown in FIG. 134(b), the main CPU 300a reads the 1-byte value stored in the address indicated by the HL register in the RAMSET module into the B register (S3). This 1-byte value indicates the number of data. Next, the main CPU 300a transfers the value stored in the address indicated by the value added by the HL register plus "2" to the address specified by the value stored in the address indicated by the value added by the HL register plus "1", and adds "2" to the value of the HL register to set the next address to be transferred (S4). Next, the main CPU 300a decrements (subtracts "1") the value of the B register and determines whether the result of the decrement is 0 or not (S5). If the result of the decrement is not 0 (NO in S5), the process from step S4 is repeated, and if the result of the decrement is 0 (YES in S5), the RAMSET module is terminated and the process returns to the routine one step above (S6).

Figures 135 and 136 are explanatory diagrams for explaining an example of commands for implementing a RAMSET module. Of these, Figure 135(a) shows a group of commands for an arbitrary process that calls the RAMSET module, Figure 135(b) shows a group of commands for the RAMSET module, Figure 135(c) shows the arrangement of a 1-byte data group in the program data of main ROM 300b, and Figure 135(d) shows the arrangement of a 1-byte data group in the work area of main RAM 300c. The flowchart shown in Figure 134 is implemented, for example, by the program shown in Figure 135.

The command "LD HL, D_RAM_RST_INI" on the first line of Fig. 135(a) sets the first address "D_RAM_RST_INI" of the 1-byte data group that is the transfer source in the HL register. This command on the first line corresponds to step S1 in Fig. 134(a). Then, the command "RST RAMSET" on the second line calls the RAMSET module as a subroutine. This command on the second line corresponds to step S2 in Fig. 134(a).

The index "RAMSET:" on the first line of Figure 135(b) indicates the starting address of the RAMSET module. The command "LD B, (HL)" on the second line causes the one-byte value stored at the address indicated by the HL register to be read into the B register. At this time, the address "D_RAM_RST_INI" is set in the HL register, as shown in Figure 135(a). Therefore, the one-byte value "(@D_RAM_RST_INI-D_RAM_RST_INI-1)/2" on the second line of Figure 135(c) is read into the B register as the number of data (number of transfer repetitions). Note that "@D_RAM_RST_INI" is the address next to the final address of the 1-byte data group that is the source of transfer, and D_RAM_RST_INI is the first address of the 1-byte data group that is the source of transfer, so the value of @D_RAM_RST_INI-D_RAM_RST_INI-1 (the 1-byte value indicating the number of data) is the total number of 1-byte values, and the number of data is derived by dividing this value by 2, which is the number of combinations of addresses and values. In the example of FIG. 135(c), the number of data is (11-1)/2=5. The command on the second line of FIG. 135(c) corresponds to step S3 in FIG. 134(b).

The index "RAMSET_10:" on the third line of Figure 135(b) indicates the start address of the repeat process. The command "INLD AC, (HL)" on the fourth line and the command "LDQ (C), A" on the fifth line store the value stored in the address indicated by adding "2" to the HL register into the address specified by the value stored in the address indicated by adding "1" to the HL register, and "2" is added to the value of the HL register to set the address to be transferred next. These commands on the fourth and fifth lines correspond to step S4 in Figure 134(b).

Here, the command "INLD AC, (HL)" stores the value stored at the address indicated by adding "1" to the HL register in the C register, stores the value stored at the address indicated by adding "2" to the HL register in the A register, and updates the value of the HL register by adding "2" to it. The command size of this command is "2", and the execution cycle is "4".

For example, if the HL register contains the value of the address "D_RAM_RST_INI", the value of the lowest byte of the 2-byte variable "R_TZ1_STP" on the third line of Figure 135(c) is stored in the C register, and the value of "@DSP_HAZ" on the third line of Figure 135(c) is stored in the A register.

The command "LDQ (C), A" on the fifth line of Figure 135(b) is a command that stores the value of the A register at the address with the value of the Q register as the most significant byte of the address and the value of the C register as the least significant byte of the address. The command size of this command is "2" and the execution cycle is "3".

For example, the value of the C register, i.e., the value of the lowest byte of "R_TZ1_STP", is set as the lowest byte of the address, and the value of the A register, i.e., the value of "@DSP_HAZ", is stored in that address.

Here, in FIG. 135(c) and FIG. 135(d), the variable "R_TZ1_STP" indicates the special symbol 1 stop symbol number, the variable "R_TZ2_STP" indicates the special symbol 2 stop symbol number, the variable "R_TZ1_DSP" indicates the counter value of the special symbol 1 display symbol counter, the variable "R_TZ2_DSP" indicates the counter value of the special symbol 2 display symbol counter, and the variable "R_EXT_SEC_TMR" indicates the security external signal timer value. Note that the arrangement of the variables shown in FIG. 135(d) does not need to be contiguous as shown in the figure, and they may be spaced apart.

Next, the command "DJNZ RAMSET_10" on line 6 of Fig. 135(b) decrements the value of the B register (subtracts "1"), and if the result of the decrement is not 0, it moves to address "RAMSET_10", and if the result of the decrement is 0, it moves to the next command after that command. In this case, the number of data items is "5", so the value of the B register becomes 0 after repeating the process from "RAMSET_10" five times. This command on line 6 corresponds to step S5 in Fig. 134(b). Then, the command "RET" on line 7 returns to the routine one level above. This command on line 7 corresponds to step S6 in Fig. 134(b).

In this way, as shown in FIG. 136, it becomes possible to transfer multiple 1-byte values (55H, 77H, 66H, 22H, AAH) written in the program data of main ROM 300b to variables ("R_TZ1_STP", "R_TZ2_STP", "R_TZ1_DSP", "R_TZ2_DSP", "R_EXT_SEC_TMR") in the work area of main RAM 300c.

The RAMSET module is called as a subroutine from multiple modules. For example, a CPUINIT module that executes the CPU initialization process shown in step S100 of FIG. 22, a SEC_SET module that executes the security setting process, an STC_PRC module that executes the state management process (error management process) shown in step S400-21 of FIG. 26, an FZ_STA module that executes the normal symbol change waiting process shown in step S810 of FIG. 52, an FZ_SPN module that executes the normal symbol change during process shown in step S820 of FIG. 53, an FZ_STP module that executes the normal symbol stop symbol display process shown in step S830 of FIG. 54, an FD_PRE module that executes the normal electric role opening pre-opening process shown in step S840 of FIG. 55, an FD_OPN module that executes the normal electric role opening control process shown in step S850 of FIG. 57, a TZ_STA module that executes the special symbol change waiting process shown in step S610 of FIG. It is called from the TZ_SPN module which executes the special symbol change processing shown in step S620 of FIG. 43, the TZ_STP module which executes the special symbol stop symbol display processing shown in step S630 of FIG. 43, the TD_PRE module which executes the large prize opening pre-opening processing shown in step S710 of FIG. 45, the TD_OPN module which executes the large prize opening opening control processing shown in step S720 of FIG. 47, the TD_EFF module which executes the large prize opening closing enable processing shown in step S730 of FIG. 48, the TD_END module which executes the large prize opening end wait processing shown in step 740 of FIG. 49, the TOKZERO module which executes the special symbol change waiting state transition processing (not shown) executed in step S630 of FIG. 43, the CHGSTS module which executes the number cut management processing shown in step S613 of FIG. 40, the RNK_PRC module which executes the setting related processing shown in step S450 of FIG. 27, etc.

Thus, the total command size of the commands of the RAMSET module shown in Fig. 135(b) is 1 byte of the command "LD B, (HL)" on line 2 + 2 bytes of the command "INLD AC, (HL)" on line 4 + 2 bytes of the command "LDQ (C), A" on line 5 + 2 bytes of the command "DJNZ RAMSET_10" on line 6 + 1 byte of the command "RET" on line 7 = 8 bytes, and the total execution cycles are 2 cycles on line 2 + 4 cycles on line 4 + 3 cycles on line 5 + 3 cycles (or 2 cycles) on line 6 + 3 cycles on line 7 = 15 cycles (or 14 cycles). Note that the number of cycles in parentheses indicates the execution cycles when there is no movement by the command "DJNZ RAMSET_10". By providing such a RAMSET module, it is possible to use the 1-byte command "RST RAMSET" without having to perform RAMset processing within each of the above-mentioned modules, shortening the command and making it possible to secure the capacity of the control area for performing game control processing.

Figure 137 is an explanatory diagram for explaining another example of commands for realizing the RAMSET module. Here, the commands of the RAMSET module in Figure 135(b) are replaced with the commands of the RAMSET module in Figure 137(b), and the commands of any other process that calls the RAMSET module in Figure 135(a), the 1-byte data group in the program data of the main ROM 300b in Figure 135(c), and the 1-byte data group in the work area of the main RAM 300c in Figure 135(d) are used as they are in Figures 137(a), 137(c), and 137(d). Here, as in Figures 137(a), 137(c), and 137(d), the description of the processes that are substantially the same as those in Figures 135(a), 135(c), and 135(d) is omitted, and only the different processes in Figure 137(b) are described.

The index "RAMSET:" on the first line of Figure 137(b) indicates the starting address of the RAMSET module. The command "LD B, (HL)" on the second line causes the one-byte value stored in the address indicated by the HL register to be read into the B register. At this time, the address "D_RAM_RST_INI" is set in the HL register, as shown in Figure 137(a). Therefore, the one-byte value "(@D_RAM_RST_INI-D_RAM_RST_INI-1)/2" on the second line of Figure 137(c) is read into the B register as the number of data. This command on the second line of Figure 137(b) corresponds to step S3 in Figure 134(b).

The command "INLDTQR AC, (HL)" on the third line of Figure 137(b) transfers the value stored in the address indicated by the value stored in the address indicated by the value stored in the HL register plus "1" to the address specified by the value stored in the address indicated by the value stored in the HL register plus "1", adds "2" to the value of the HL register to set the next transfer address, decrements the value of the B register (subtracts "1"), and repeats this process until the decrement result becomes 0. This command on the third line corresponds to steps S4 and S5 in Figure 134(b).

Here, the command "INLDTQR AC, (HL)" sets the value of the Q register to the upper byte of the address, sets the value stored at the address indicated by adding "1" to the HL register to the lower byte of the address, transfers the value stored at the address indicated by adding "2" to the HL register to that address, updates the HL register by adding "2", decrements the value of the B register (subtracts "1"), and repeats the value transfer until the decrement result becomes 0. The command size of this command is "2", and the execution cycle is "5".

For example, if the HL register contains the value of the address "D_RAM_RST_INI", the value of the Q register becomes the most significant byte of the address, the value of the least significant byte of "R_TZ1_STP" on the third line of Figure 137(c) becomes the most significant byte of the address, the value of "@DSP_HAZ" on the third line of Figure 137(c) is transferred to that address, "2" is added to the value of the HL register, and the value of the B register is decremented ("1" is subtracted), and the transfer is repeated until the result of the decrement becomes 0, that is, five times.

Then, the "RET" command on the fourth line of FIG. 137(b) returns to the routine one level above. This command on the fourth line corresponds to step S6 in FIG. 134(b).

The total command size of the commands in the RAMSET module in FIG. 137(b) is 1 byte of the command "LD B, (HL)" on the second line + 2 bytes of the command "INLDTQR AC, (HL)" on the third line + 1 byte of the command "RET" on the fourth line = 4 bytes, and the total execution cycles are 2 cycles on the second line + 5 cycles on the third line + 3 cycles on the fourth line = 10 cycles. Therefore, compared to the case of FIG. 135(b), the total command size is reduced by 4 bytes, and the total execution cycles are also reduced by at least 4 cycles. In particular, in the example of FIG. 135(b), if the value of the B register in the command "DJNZ RAMSET_10" is 2 or more, the total execution cycles increase by 10 cycles (4 cycles on the fourth line + 3 cycles on the fifth line + 3 cycles on the sixth line), so the reduction in the total execution cycles in FIG. 137(b) is also large. This RAMSET module makes it possible to further shorten commands and reduce processing load, while ensuring sufficient control area capacity for game control processing.

In addition, unlike the example in Figure 135, the A register and C register are not used here. Therefore, the values in the A register and C register will not be updated unintentionally. Also, in the example in Figure 135, if the A register or C register was already in use, it was necessary to save the values in the A register and C register by stacking them, but here, since the A register and C register are not used, stack processing is not required. In this way, resources can be used efficiently.

In addition, as can be seen by comparing FIG. 135(b) with FIG. 137(b), the command group that occupies four lines (lines 3 to 6) in FIG. 135(b) can be represented in one line (line 3) in FIG. 137(b), making it possible to reduce the number of commands and lighten the design load.

This RAMSET module is used not only in pachinko machines but also in slot machines as a TABLESET module (general-purpose module) that executes table set processing to set predetermined values (initial values) to variables in the main RAM 500c.

Figure 138 is an explanatory diagram for explaining an example of a command for implementing a TABLESET module. Of these, Figure 138(a) shows a command group for an arbitrary process that calls the TABLESET module, Figure 138(b) shows a command group for the TABLESET module, Figure 138(c) shows the arrangement of a 1-byte data group in the program data of main ROM 500b, and Figure 138(d) shows the arrangement of a 1-byte data group in the work area of main RAM 500c.

Note that the optional processing here includes the error wait processing shown in step S2200-11 in FIG. 89 and step S2800-39 in FIG. 95, i.e., a part of the ERRWAIT module that displays an error, requests an alarm sound, and waits for recovery from an error.

The command "LD HL, T_ERR_RCV" on the first line of Figure 138(a) sets the starting address "T_ERR_RCV" of the 1-byte data group that will be the transfer source in the HL register. Then, the command "RST TABLESET" on the second line calls the TABLESET module as a subroutine.

The index "TABLESET:" on the first line of Figure 138(b) indicates the starting address of the TABLESET module. The command "PUSH BC" on the second line saves the value of the BC register to the stack area. The command "DI" on the third line disables interrupts.

The command "LD B, (HL)" on the fourth line of Fig. 138(b) reads the one-byte value stored in the address indicated by the HL register into the B register. At this time, the address "T_ERR_RCV" is set in the HL register as shown in Fig. 138(a). Therefore, the one-byte value "(T_ERR_RCV_-T_ERR_RCV)/2" on the second line of Fig. 138(c) is read into the B register as the number of data (number of transfer iterations). Note that "T_ERR_RCV_" is the address next to the last address of the one-byte data group that is the transfer source, and T_ERR_RCV is the first address of the one-byte data group that is the transfer source, so the value of T_ERR_RCV_-T_ERR_RCV (the one-byte value indicating the number of data) is the total number of bytes of the one-byte value, and the number of data is derived by dividing this value by 2, which is the number of combinations of addresses and values. In the example of Figure 138 (c), the number of data items is 9/2 = 4.

The index "TABLESET10:" on the fifth line of Figure 138(b) indicates the start address of the repeat process. The command "INLD AC, (HL)" on the sixth line and the command "LDQ (C), A" on the seventh line store the value stored in the address indicated by adding "2" to the HL register into the address specified by the value stored in the address indicated by adding "1" to the HL register, and "2" is added to the value of the HL register to set the address to be transferred next.

For example, if the HL register contains the value of address "T_ERR_RCV", the value of the lowest byte of the 2-byte variable "_ERR_NUM" on the third line of Figure 138(c) is stored in the C register, and the value "0" on the third line of Figure 138(c) is stored in the A register.

The command "LDQ (C), A" on line 7 of Figure 138(b) is a command that stores the value of the A register at the address with the value of the Q register as the upper byte of the address and the value of the C register as the lower byte of the address.

For example, the value of the C register, i.e., the value of the lowest byte of "_ERR_NUM", is set as the lowest byte of the address, and the value of the A register, i.e., the value "0", is stored at that address.

Here, in Figures 138(c) and 138(d), the variable "_ERR_NUM" indicates the error number, the variable "_CRE_TMR" indicates the credit button detection timer, the variable "_CRE_FLG" indicates the credit button detection flag, and the variable "_SNS_OLD" indicates the previous state of the medal passage sensor bit. Note that the arrangement of the variables shown in Figure 138(d) does not need to be contiguous as shown in the figure, and they may be spaced apart.

Next, the command "DJNZ TABLESET10" on line 8 of Figure 138(b) decrements the value of the B register (subtracts "1"), and if the result of the decrement is not 0, it moves to address "TABLESET10", and if the result of the decrement is 0, it moves to the next command after that command. In this case, the number of data items is "4", so if the process from "TABLESET10" is repeated four times, the value of the B register will become 0.

The command "EI" on line 9 of Figure 138(b) allows interrupts. The command "POP BC" on line 10 restores the data saved in the stack area to the BC register. Then, the command "RET" on line 11 returns to the routine one level above.

If you replace it with the command "INLDTQR", the command group can be written as follows.

Figure 139 is an explanatory diagram for explaining another example of commands for realizing the TABLESET module. Here, the commands of the TABLESET module in Figure 138(b) are replaced with the commands of the TABLESET module in Figure 139(b), and the commands of any other process that calls the TABLESET module in Figure 138(a), the 1-byte data group in the program data of the main ROM 500b in Figure 138(c), and the 1-byte data group in the work area of the main RAM 500c in Figure 138(d) are used as they are in Figures 139(a), 139(c), and 139(d). Here, as in Figures 139(a), 139(c), and 139(d), the description of the processes that are substantially the same as those in Figures 138(a), 138(c), and 138(d) is omitted, and only the different processes in Figure 139(b) are described.

The index "TABLESET:" on the first line of Figure 139(b) indicates the starting address of the TABLESET module. The command "PUSH BC" on the second line saves the value of the BC register to the stack area. The command "DI" on the third line disables interrupts.

The command "LD B, (HL)" on the fourth line of Figure 139(b) reads a one-byte value stored in the address indicated by the HL register into the B register. At this time, the address "T_ERR_RCV" is set in the HL register, as shown in Figure 139(a). Therefore, the one-byte value "(T_ERR_RCV_-T_ERR_RCV)/2" on the second line of Figure 139(c) is read into the B register as the number of data (number of transfer repetitions). In the example of Figure 139(c), the number of data is 4.

The command "INLDTQR (HL)" on the fifth line of Figure 139 (b) transfers the value stored in the address indicated by the value stored in the address indicated by the value stored in the HL register plus "1" to the address specified by the value stored in the address indicated by the value stored in the HL register plus "1", adds "2" to the value of the HL register to set the next transfer address, decrements the value of the B register (subtracts "1"), and repeats this process until the result of the decrement becomes 0.

Next, interrupts are permitted by the command "EI" on line 6 of Figure 139(b). The command "POP BC" on line 7 restores the data saved in the stack area to the BC register. Then, the command "RET" on line 8 returns to the routine one level above.

Here, the total command size of the commands in the TABLESET module shown in FIG. 138(b) is: 1 byte of the command "PUSH BC" on the second line + 1 byte of the command "DI" on the third line + 1 byte of the command "LD B, (HL)" on the fourth line + 2 bytes of the command "INLD AC, (HL)" on the sixth line + 2 bytes of the command "LDQ (C), A" on the seventh line + 2 bytes of the command "DJNZ TABLESET10" on the eighth line + 1 byte of the command "EI" on the ninth line + 1 byte of the command "POP The total number of execution cycles is 3 cycles on line 2 + 1 cycle on line 3 + 2 cycles on line 4 + 4 cycles on line 6 + 3 cycles on line 7 + 3 cycles (or 2 cycles) on line 8 + 1 cycle on line 9 + 3 cycles on line 10 + 3 cycles on line 11 = 23 cycles (or 22 cycles). On the other hand, the total command size of the commands of the TABLESET module shown in Fig. 139(b) is 1 byte of the command "PUSH BC" on the second line + 1 byte of the command "DI" on the third line + 1 byte of the command "LD B, (HL)" on the fourth line + 2 bytes of the command "INLDTQR (HL)" on the fifth line + 1 byte of the command "EI" on the sixth line + 1 byte of the command "POP BC" on the seventh line + 1 byte of the command "RET" on the eighth line = 8 bytes, and the total execution cycles are 3 cycles on the second line + 1 cycle on the third line + 2 cycles on the fourth line + 5 cycles on the fifth line + 1 cycle on the sixth line + 3 cycles on the seventh line + 3 cycles on the eighth line = 18 cycles. Therefore, compared with the case of Fig. 138(b), the total command size is reduced by 4 bytes, and the total execution cycles are also reduced by at least 5 cycles. In particular, in the example of FIG. 138(b), if the value of the B register in the command "DJNZ TABLESET10" is 2 or more, the total execution cycles increase by 10 cycles (4 cycles on line 6 + 3 cycles on line 7 + 3 cycles on line 8) multiplied by that value, so the reduction in the total execution cycles in FIG. 139(b) also increases. This TABLESET module shortens commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

In addition, unlike the example in FIG. 138, the A register and C register are not used here. Therefore, the values in the A register and C register will not be updated unintentionally. Also, in the example in FIG. 138, if the A register or C register was already in use, it was necessary to save the values in the A register and C register by stacking them, but here, since the A register and C register are not used, stack processing is not required. In this way, resources can be used efficiently.

In addition, as can be seen by comparing FIG. 138(b) and FIG. 139(b), the command group that occupies four lines (lines 5 to 8) in FIG. 138(b) can be represented in one line (line 5) in FIG. 139(b), making it possible to reduce the number of commands and lighten the design load.

The TABLESET module is called as a subroutine not only by the ERRWAIT module, but also by multiple other modules. For example, the EXE_SET module, which executes the execution flag setting process shown in step S2400-11 in FIG. 91, selectively transitions depending on the game state and presentation state in the EXE_SET module, which executes the execution flag setting process shown in step S2400-11 in FIG. 91, and executes the premonition process (AT state = "3"); the FIN_LOT module, which executes the execution flag setting process shown in step S2400-11 in FIG. 91, selectively transitions depending on the game state and presentation state in the EXE_SET module, which executes the execution flag setting process shown in step S2400-11 in FIG. 91, and executes the end screen process (AT state = "4"); the PRE_LOT module, which executes the execution flag setting process shown in step S2400-11 in FIG. 91, selectively transitions depending on the game state and presentation state in the EXE_SET module, which executes the execution flag setting process shown in step S2400-11 in FIG. 91, and executes the preparation process (AT state = "5"); It is called from the REG_LOT module, which selectively transitions in accordance with the game state and presentation state in the EXE_SET module, and executes REG processing (AT state = "6"); the BIG_LOT module, which selectively transitions in accordance with the game state and presentation state in the EXE_SET module, which executes the execution flag setting process shown in step S2400-11 in FIG. 91, and executes BIG processing (AT state = "7"); the RANKSET module, which executes the setting value switching process shown in step S2020 in FIG. 85; the FGSETUP module, which executes the symbol code setting process shown in step S2400 in FIG. 91; the GAMESET module, which executes the game transition process shown in step S2900 in FIG. 96; and the JCGMSET module, which executes the role-operating symbol display process shown in step S2900-3 in FIG. 96.

<Command "DECM", "DECWM">
The BYTEDEC module is a general-purpose module for byte counter subtraction processing, that is, for decrementing a 1-byte variable in the main RAM 300c by 1. Note that the BYTEDEC module not only decrements, but also sets a zero flag and a carry flag as a result of the decrement.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, and in any process, calls the BYTEDEC module as a subroutine and executes the BYTEDEC module. The BYTEDEC module decrements a one-byte value stored in the main RAM 300c.

Figure 140 is a flow chart showing the specific processing of the BYTEDEC module. Here, as an optional process, a part of the TZ_STP module that executes the special symbol stop symbol display process shown in step S630 of Figure 43 will be explained. The numerical values of step S in this figure will be used only in the explanation of this figure. Also, in the explanation of this BYTEDEC module, the specified register is the HL register.

The main CPU 300a executes an arbitrary process as shown in FIG. 140(a). The main CPU 300a first sets the address of the variable to be decremented in the HL register (S1). Then, it calls the BYTEDEC module as a subroutine (S2).

As shown in FIG. 140(b), the main CPU 300a decrements the 1-byte value stored in the address indicated by the HL register in the BYTEDEC module by 1, and sets the zero flag and the carry flag (S3). Then, the BYTEDEC module is terminated and the process returns to the routine one step above (S4). The decrement mode and flag settings are described in detail below.

Figure 141 is an explanatory diagram for explaining the decrement mode in the BYTEDEC module and the setting of the zero flag and carry flag. Here, if the value before the decrement is 1 or more (1 or 2 or more), the value after the decrement is decremented by 1. However, if the value before the decrement was 0, the value after the decrement will not be -1, but 0. In other words, the lower limit is 0, and it will never be a negative value. This maintenance of 0 can be achieved by decrementing and then incrementing, or forcibly reading out 0, if the value before the decrement was 0, or by not decrementing at all.

Also, if the value before the decrement was 2 or greater, it will be 1 or greater after the decrement, so the zero flag will not be set and it will be 0, but if the value before the decrement was 1 or 0, it will be 0 after the decrement, so the zero flag will be set and it will be 1. Also, in the BYTEDEC module, if the value before the decrement was 1, it will be 0 after the decrement, in which case the carry flag will be set and it will be 1. And if the value before the decrement was 2 or greater or 0, the carry flag will not be set and it will be 0.

Returning to FIG. 140(a), when the zero flag and carry flag are set by the BYTEDEC module, the main CPU 300a uses the values of the flags to carry out various processes. For example, here, it is determined that the decrement is not a process of subtracting 1 to make 0 (S5), and as a result, if it is not a process of subtracting 1 to make 0 (YES in S5), it moves to a predetermined address (TZ_STP_10) that performs special symbol winning flag check processing (S6), and if it is a process of subtracting 1 to make 0 (NO in S5), it carries out the next process without moving.

Figure 142 is an explanatory diagram for explaining an example of commands for implementing the BYTEDEC module. Of these, Figure 142(a) shows a command group for an arbitrary process that calls the BYTEDEC module, and Figure 142(b) shows a command group for the BYTEDEC module. The flowchart shown in Figure 140 is implemented, for example, by the program shown in Figure 142.

The command "LDQ HL, LOW R_EXT_HCT" on the first line of Figure 142(a) reads the value of the Q register into the H register, and reads the value of the lowest byte of the address "R_EXT_HCT" into the L register. This command on the first line corresponds to step S1 in Figure 140(a). Then, the command "CALLF BYTEDEC" on the second line calls the BYTEDEC module as a subroutine. This command on the second line corresponds to step S2 in Figure 140(a).

Here, the command "CALLF BYTEDEC" can only call the range of 0000H to 11FFH in the memory map. The command "CALLF" used for calling has the same execution cycle of "4" as the normal command "CALL", but the command size of the normal command "CALL" is "3", whereas the command size of the command "CALLF" is "2". This makes it possible to shorten the program. Note that instead of the command "CALLF BYTEDEC", the BYTEDEC module can be called by "RST BYTEDEC" like the generic module mentioned above. By doing so, the command size can be made "1".

The index "BYTEDEC:" on the first line of FIG. 142(b) indicates the starting address of the BYTEDEC module. The command "LD A, (HL)" on the second line reads a byte value stored in the address indicated by the HL register into the A register. Execution of this command "LD A, (HL)" changes the second zero flag. Then, the command "RT Z, A" on the third line returns to the routine one level above if the value of the A register is 0 (if the second zero flag is 1). At this time, if the value of the A register is 0, the command "RT Z, A" sets the zero flag (first zero flag) to 1 and the carry flag to 0. In this way, if the value stored in the address indicated by the HL register is 0, the zero flag can be set to 1 and the carry flag to 0 without performing a decrement.

The command "CP A,2" on the fourth line of FIG. 142(b) compares the value of the A register with 2. If the A register is 2 or greater, the carry flag is not raised and becomes 0, and if the A register is 1, the carry flag is raised and becomes 1. Note that the command "CP A,2" is a command that raises the carry flag when the A register is less than 2, but since the value of the A register is either 1 or 2 or greater (it is not 0) at the execution stage of the command "CP A,2", raising the carry flag when it is less than 2 results in the carry flag being raised when it is 1. In this way, if the value of the A register is 1, the carry flag = 1. The command "DEC (HL)" on the fifth line decrements the 1-byte value stored at the address indicated by the HL register by 1, updating the value stored at the address indicated by the HL register. Here, if the value stored in the address indicated by the HL register is 2 or more, the decremented value is 1 or more, so the zero flag is not set and becomes 0, and if it is 1, the decremented value is 0, so the zero flag is set and becomes 1. Note that the carry flag does not change with the command "DEC (HL)". In this way, if the value stored in the address indicated by the HL register is 2 or more, the zero flag = 0 and the carry flag = 0, and if it is 1, the zero flag = 1 and the carry flag = 1. The commands on lines 2 to 5 correspond to step S3 in FIG. 140(b). Then, the command "RET" on line 6 returns to the routine one step above. The command on line 6 corresponds to step S4 in FIG. 140(b). In this way, it is possible to decrement the value stored in the address indicated by the HL register by 1 and set the zero flag and the carry flag.

Next, the command "JR NC, TZ_STP_10" on the third line of FIG. 142(a) moves to TZ_STP_10 if the carry flag is 0 (NC). This command on the third line corresponds to steps S5 and S6 in FIG. 140(a). In this way, processing based on the results of the BYTEDEC module becomes possible.

The BYTEDEC module is called as a subroutine from multiple modules. For example, it is called from the TMR_NEW module that executes the timer update process shown in step S400-15 of FIG. 26, the STC_PRC module that executes the state management process (error management process) shown in step S400-21 of FIG. 26, the TZ_STP module that executes the special symbol stop symbol display process shown in step S630 of FIG. 43, the CHGSTS module that executes the number of times cut management process shown in step S613 of FIG. 40, the TDOVCHK module that executes the large prize opening excessive winning monitoring process that is executed after setting the large prize opening ball entry command (step S540-3) in the count switch passing process (large prize opening passing process) shown in step S540 of FIG. 34, and the BER_CHK module that executes the base abnormal error monitoring process, which is a subroutine of the state management process (error management process) shown in step S400-21 of FIG. 26.

Thus, the total command size of the BYTEDEC module commands shown in Fig. 142(b) is 1 byte of the command "LD A, (HL)" on line 2 + 1 byte of the command "RT Z, A" on line 3 + 2 bytes of the command "CP A, 2" on line 4 + 1 byte of the command "DEC (HL)" on line 5 + 1 byte of the command "RET" on line 6 = 6 bytes, and the total execution cycles are 2 cycles on line 2 + 4 cycles (or 2 cycles) on line 3 + 2 cycles on line 4 + 4 cycles on line 5 + 3 cycles on line 6 = 15 cycles (or 13 cycles). Note that the number of cycles in parentheses indicates the execution cycles when the command "RT Z, A" does not move to the routine above. By providing this BYTEDEC module, it is possible to use the 2-byte command "CALLF BYTEDEC" without having to perform byte counter subtraction processing within each of the above-mentioned modules, shortening the command and making it possible to secure the capacity of the control area for performing game control processing.

Figure 143 is an explanatory diagram for explaining another example of commands for implementing the BYTEDEC module. Here, the commands of the BYTEDEC module in Figure 142(b) are replaced with the commands of the BYTEDEC module in Figure 143(b), and the commands of any other process that calls the BYTEDEC module in Figure 142(a) are used as is, as in Figure 143(a). Here, as in Figure 143(a), explanations of processes that are essentially the same as those in Figure 142(a) are omitted, and only the different processes in Figure 143(b) are explained.

The index "BYTEDEC:" on the first line of Figure 143(b) indicates the starting address of the BYTEDEC module. The command "DECM (HL)" on the second line decrements the value stored in the address indicated by the HL register by 1 if it is 1 or greater, and maintains it at 0 if it is 0.

Here, the command "DECM (HL)" decrements the one-byte value stored at the address indicated by the HL register, and if the carry flag is set (-1), it forcibly stores 0 in the one-byte value stored at the address indicated by the HL register. Then, if the value stored at the address indicated by the HL register is 1 or greater, it is decremented by 1, and if it is 0, it remains 0. By executing this command "DECM (HL)", if the value after decrement is zero (if the value before decrement is 1 or 0), the zero flags (first zero flag and second zero flag) are set to 1, and if the value before decrement is zero, the carry flag is set to 1. The command size of this command is "2", and the execution cycle is "5".

The command "RET NZ" on the third line of Figure 143(b) returns to the routine one level higher if the zero flag is not 1 (if the value after decrement is not zero). In this case, since the command "DECM (HL)" has already performed the decrement, the fact that the zero flag is not 1 indicates that the value before the decrement was 2 or more. In that case, the zero flag is not set and is 0, and the carry flag is also not set and is 0, so it is possible to return to the routine one level higher. Note that "NZ" is given here to refer to the first zero flag, but since normally when the first zero flag is changed, the second zero flag also changes, "NTZ" can also be used instead of "NZ" in all processing.

In the command "DECM (HL)", if the value stored in the address indicated by the HL register before the decrement is 1, it becomes 0 after the decrement, and the zero flag = 1 and the carry flag = 0. If the value is 0, the decrement is not performed and the value remains 0, and the zero flag = 1 and the carry flag = 1. In other words, the specifications for the carry flag are the opposite of those shown in FIG. 141. Therefore, the command "CCF" on the fourth line of FIG. 143(b) inverts the carry flag (1 → 0, 0 → 1). Note that the command "CCF" does not change the zero flag. In this way, if the value stored in the address indicated by the HL register before the decrement is 1, the zero flag = 0 and the carry flag = 1, and if the value is 0, the zero flag = 1 and the carry flag = 0. The commands on the second to fourth lines correspond to step S3 in FIG. 140(b). Then, the command "RET" on the fifth line returns to the routine one step above. The command on the fifth line corresponds to step S4 in FIG. 140(b). In this way, it is possible to decrement the value stored at the address indicated by the HL register by 1 and set the zero flag and carry flag.

Next, the command "JR NC, TZ_STP_10" on the third line of FIG. 143(a) moves to TZ_STP_10 if the carry flag is 0 (NC). This command on the third line corresponds to steps S5 and S6 in FIG. 140(a). In this way, processing based on the results of the BYTEDEC module becomes possible.

The total command size of the BYTEDEC module commands in FIG. 143(b) is 2 bytes of the command "DECM (HL)" on the second line + 1 byte of the command "RET NZ" on the third line + 2 bytes of the command "CCF" on the fourth line + 1 byte of the command "RET" on the fifth line = 6 bytes, and the total execution cycles are 5 cycles on the second line + 3 cycles (1 cycle) on the third line + 2 cycles on the fourth line + 3 cycles on the sixth line = 13 cycles (11 cycles). The number of cycles in parentheses indicates the execution cycles when the command "RET NZ" does not move to the next higher routine. Therefore, the total execution cycles are reduced by at least 2 cycles compared to the case in FIG. 142(b). This BYTEDEC module makes it possible to secure the capacity of the control area for performing game control processing while reducing the processing load.

In addition, unlike the example in FIG. 142, the A register is not used here. Therefore, the value of the A register will not be updated unintentionally. Also, in the example in FIG. 142, if the A register was already in use, it was necessary to save the value of the A register by stacking it, but here, since the A register is not used, stack processing is not required. In this way, resources can be used efficiently.

In addition, as can be seen by comparing FIG. 142(b) and FIG. 143(b), the command group that occupies four lines (lines 2 to 5) in FIG. 142(b) can be represented in three lines (lines 2 to 4) in FIG. 143(b), making it possible to reduce the number of commands and lighten the design load.

In addition, such a BYTEDEC module is used not only in pachinko machines but also in slot machines, in the EXE_SET module which executes the execution flag setting process shown in step S2400-11 in FIG. 91, selectively transitions depending on the game state and the presentation state in the EXE_SET module which executes the execution flag setting process shown in step S2400-11 in FIG. 91, and executes the REG during processing (AT state = "6"); the BIG_LOT module which selectively transitions depending on the game state and the presentation state in the EXE_SET module which executes the execution flag setting process shown in step S2400-11 in FIG. 91, and executes the BIG during processing (AT state = "7"); the JCGMSET module which executes the role activation pattern display process shown in step S2900-3 in FIG. 96; the TMR_IPT module which executes the timer interrupt process shown in step S3100 in FIG. 98; and the CAL_MOD module for executing the state-specific module execution process shown in step S3100-21 in FIG. 98. In the CAL_MOD module for executing the state-specific module execution process shown in step S3100-21 of FIG. 98, it is used as an IPT_PA module that selectively transitions once every four times (every 5.96 msec) according to the timer interrupt processing phase (0 to 3) and executes terminal board output control processing, an IPT_PC module that selectively transitions once every four times (every 5.96 msec) according to the timer interrupt processing phase (0 to 3) and executes time monitoring processing, and a RAM_DEC module (general-purpose module) that executes counter decrement processing and is called by the command "RST" from the IPT_PD module that selectively transitions once every four times (every 5.96 msec) according to the timer interrupt processing phase (0 to 3) and executes external signal output control processing in the CAL_MOD module for executing the state-specific module execution process shown in step S3100-21 of FIG. 98.

Figure 144 is an explanatory diagram for explaining the RAM_DEC module. Like the BYTEDEC module described above, the RAM_DEC module shown in Figure 144 is a general-purpose module for counter decrement processing, i.e., decrementing a 1-byte variable in the main RAM 500c by 1. Note that, like the BYTEDEC module, the RAM_DEC module not only decrements, but also sets the zero flag and carry flag shown in Figure 141 as a result of the decrement.

The index "RAM_DEC:" on the first line of FIG. 144(a) indicates the starting address of the RAM_DEC module. The command "LD A, (HL)" on the second line reads a one-byte value stored in the address indicated by the HL register into the A register. Execution of this command "LD A, (HL)" changes the second zero flag. Then, the command "RT Z, A" on the third line returns to the routine one level above if the value of the A register is 0 (if the second zero flag is 1). At this time, if the value of the A register is 0, the command "RT Z, A" sets the zero flag (first zero flag) to 1 and the carry flag to 0. In this way, if the value stored in the address indicated by the HL register is 0, the zero flag can be set to 1 and the carry flag to 0 without performing a decrement.

The command "CP A,2" on the fourth line of FIG. 144(a) compares the value of the A register with 2. If the A register is 2 or more, the carry flag is not set and becomes 0, and if the A register is 1, the carry flag is set and becomes 1. Note that the command "CP A,2" sets the carry flag when the A register is less than 2, but since the value of the A register is either 1 or 2 or more (it is not 0) at the execution stage of the command "CP A,2", setting the carry flag when it is less than 2 results in the carry flag being set when it is 1. In this way, if the value of the A register is 1, the carry flag = 1. The command "DEC A" on the fifth line decrements the 1-byte value stored at the address indicated by the A register by 1. The command "LD (HL),A" on the sixth line stores the value of the A register at the address indicated by the HL register. Here, if the value stored at the address indicated by the HL register is 2 or greater, the decremented value is 1 or greater, so the zero flag is not set and the value becomes 0; if it is 1, the decremented value is 0, so the zero flag is set and the value becomes 1. Note that the carry flag does not change with the command "DEC A." In this way, if the value stored at the address indicated by the HL register is 2 or greater, the zero flag = 0 and the carry flag = 0; if it is 1, the zero flag = 1 and the carry flag = 1. Then, the command "RET" on the seventh line returns to the routine one level above. In this way, it is possible to decrement the value stored at the address indicated by the HL register by 1 and set the zero flag and carry flag.

Now, by replacing it with the command "DECM", the command group in FIG. 144(a) can be changed to that in FIG. 144(b). The index "RAM_DEC:" on the first line of FIG. 144(b) indicates the starting address of the RAM_DEC module. The command "DECM (HL)" on the second line decrements the value stored in the address indicated by the HL register by 1 if it is 1 or greater, and maintains the value at 0 if it is 0.

The command "RET NZ" on the third line of Fig. 144(b) returns to the routine one level above if the zero flag is not 1 (if the value after decrement is not zero). In this case, since the command "DECM (HL)" has already performed decrement, the fact that the zero flag is not 1 indicates that the value before decrement was 2 or more. In that case, the zero flag is not set and becomes 0, and the carry flag is also not set and becomes 0, so it is possible to return to the routine one level above. Next, the command "CCF" on the fourth line inverts the carry flag (1 → 0, 0 → 1). Note that the command "CCF" does not change the zero flag. In this way, if the value stored at the address indicated by the HL register before decrement is 1, the zero flag = 0 and the carry flag = 1, and if it is 0, the zero flag = 1 and the carry flag = 0. Then, the command "RET" on the fifth line returns to the routine one level above. In this way, it is possible to decrement the value stored at the address indicated by the HL register by one and set the zero flag and carry flag.

Here, the total command size of the commands of the RAM_DEC module shown in FIG. 144(a) is 1 byte of the command "LD A, (HL)" on the second line + 1 byte of the command "RT Z, A" on the third line + 2 bytes of the command "CP A, 2" on the fourth line + 1 byte of the command "DEC A" on the fifth line + 1 byte of the command "LD (HL), A" on the sixth line + 1 byte of the command "RET" on the seventh line = 7 bytes, and the total execution cycle is 2 cycles on the second line + 4 cycles (or 2 cycles) on the third line + 2 cycles on the fourth line + 1 cycle on the fifth line + 2 cycles on the sixth line + 3 cycles on the seventh line = 14 cycles (or 12 cycles). The number of cycles in parentheses indicates the execution cycle when the command "RT Z, A" does not move to the routine above. On the other hand, the total command size of the commands of the RAM_DEC module shown in FIG. 144(b) is 2 bytes of the command "DECM (HL)" on the second line + 1 byte of the command "RET NZ" on the third line + 2 bytes of the command "CCF" on the fourth line + 1 byte of the command "RET" on the fifth line = 6 bytes, and the total execution cycle is 5 cycles on the second line + 3 cycles (1 cycle) on the third line + 2 cycles on the fourth line + 3 cycles on the sixth line = 13 cycles (11 cycles). The number of cycles in parentheses indicates the execution cycle when the command "RET NZ" does not move to the next higher routine. Therefore, by replacing the command group in FIG. 144(a) with the command group in FIG. 144(b), the total command size is reduced by 1 byte and the total execution cycle is reduced by at least 1 cycle. Such replacement shortens the command and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

The WORDDEC module is a general-purpose module for word counter subtraction processing, i.e., decrementing a 2-byte variable in main RAM 300c by 1. Note that the WORDDEC module not only decrements, but also sets the zero flag and carry flag as a result of the decrement.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, and in any process, calls the WORDDEC module as a subroutine and executes the WORDDEC module. The WORDDEC module decrements the 2-byte data stored in the main RAM 300c.

Figure 145 is a flow chart showing the specific processing of the WORDDEC module. Here, as an optional process, a part of the NHI_CHK module that executes the winning frequency abnormality error determination process, which is a subroutine of the status management process (error management process) shown in step S400-21 of Figure 26, is given as an explanation. The numerical values of step S in this figure are used only in the explanation of this figure. Also, in the explanation of this WORDDEC module, the specified register is the HL register.

The main CPU 300a executes an arbitrary process as shown in FIG. 145(a). The main CPU 300a first sets the address of the variable to be decremented in the HL register (S1). Then, it calls the WORDDEC module as a subroutine (S2).

As shown in FIG. 145(b), in the WORDDEC module, the main CPU 300a decrements the 2-byte value stored at the address indicated by the HL register by 1 and sets the zero flag and carry flag (S3). Then, the WORDDEC module is terminated and the process returns to the subroutine one level above (S4). Note that the decrement mode and flag settings are explained in FIG. 141, as with the BYTEDEC module.

When the zero flag and carry flag are set by the WORDDEC module, the main CPU 300a performs various processes using the value of the HL register. For example, here, it is determined that the decrement result is not 0 (S5), and if the result is not 0 (YES in S5), the process returns from the subroutine (S6), and if the result is 0 (NO in S5), the process performs the next process without moving on.

Figure 146 is an explanatory diagram for explaining an example of commands for implementing the WORDDEC module. Of these, Figure 146(a) shows a group of commands for an arbitrary process, and Figure 146(b) shows a group of commands for the WORDDEC module. The flowchart shown in Figure 145 is implemented, for example, by the program shown in Figure 146.

The command "POP HL" on the first line of FIG. 146(a) restores the address value of the winning frequency abnormality error monitoring timer that was saved in the stack area to the HL register. This command on the first line corresponds to step S1 in FIG. 145(a). Then, the command "CALLF WORDDEC" on the second line calls the WORDDEC module as a subroutine. This command on the second line corresponds to step S2 in FIG. 145(a).

The index "WORDDEC:" on the first line of FIG. 146(b) indicates the top address of the WORDDEC module. The command "JTW Z, (HL), WORDDEC_99" on the second line determines whether the 2-byte value stored in the address indicated by the HL register is 0, and if it is 0, moves to the index "WORDDEC_99:". The execution of this command "JTW Z, (HL), WORDDEC_99" changes the zero flag. For example, if the value stored in the address indicated by the HL register is 0, the zero flag becomes 1 and the carry flag becomes 0. Also, if the value stored in the address indicated by the HL register is 0, moves to the index "WORDDEC_99:", and the command "RET" on the seventh line returns to the subroutine one level above. In this way, if the value stored in the address indicated by the HL register is 0, the zero flag can be set to 1 and the carry flag to 0 without performing a decrement.

The command "DECW (HL)" on the third line of FIG. 146(b) decrements the 2-byte value stored at the address indicated by the HL register by 1, updating the value stored at the address indicated by the HL register. If the value stored at the address indicated by the HL register is 2 or more, the decremented value is 1 or more, so the zero flag is not set and becomes 0, and if it is 1, the decremented value becomes 0, so the zero flag (second zero flag) is set and becomes 1. Then, the command "RET NTZ" on the fourth line returns to the subroutine one level above if the zero flag is not 1. The reason "NTZ" is used here is because the command "DECW (HL)" changes the second zero flag but not the first zero flag. Note that the command "RET NTZ" does not change either the zero flag or the carry flag. At this time, the zero flag does not become 1 (returns to the subroutine one level above) if the value stored at the address indicated by the HL register before the decrement is 2 or more. Therefore, if the value before the decrement is 2 or greater, the zero flag = 0 and the carry flag = 0, so there is no problem in returning to the subroutine one level above.

Also, if the zero flag is 1, the value stored in the address indicated by the HL register before the decrement is 1, and the zero flag = 1 and the carry flag = 0. In other words, the specifications for the carry flag are the opposite of those shown in FIG. 141. Therefore, the command "SCF" on the fifth line forces the carry flag to be set to 1. Thus, if the value stored in the address indicated by the HL register before the decrement is 1, the zero flag = 1 and the carry flag = 1. Note that the zero flag does not change due to the command "SCF". The commands on the second to sixth lines correspond to step S3 in FIG. 145(b). Then, the command "RET" on the seventh line returns to the subroutine one level above. The command on the seventh line corresponds to step S4 in FIG. 145(b). Thus, it is possible to decrement the value stored in the address indicated by the HL register by 1 and set the zero flag and the carry flag.

Next, the command "RET NTZ" on the third line of Fig. 146(a) causes the program to return to the subroutine one level higher if the zero flag (second zero flag) is not 1 (if it is 0). This command on the third line corresponds to steps S5 and S6 in Fig. 145(a). In this way, processing based on the results of the WORDDEC module becomes possible.

The WORDDEC module is called as a subroutine from multiple modules. For example, it is called from the TMR_NEW module which executes the timer update process shown in step S400-15 of FIG. 26, the TZ_SPN module which executes the special symbol change process shown in step S620 of FIG. 41, and the NHI_CHK module which executes the winning frequency abnormality error determination process, which is a subroutine of the status management process (error management process) shown in step S400-21 of FIG. 26.

Thus, the total command size of the WORDDEC module commands shown in Fig. 146(b) is 3 bytes of the command "JTW Z, (HL), WORDDEC_99" on line 2 + 2 bytes of the command "DECW (HL)" on line 3 + 1 byte of the command "RET NTZ" on line 4 + 2 bytes of the command "SCF" on line 5 + 1 byte of the command "RET" on line 7 = 9 bytes, and the total execution cycles are 6 cycles (or 5 cycles) on line 2 + 7 cycles (or 1 cycle) on line 3 + 3 cycles (or 1 cycle) on line 4 + 2 cycles on line 5 + 3 cycles on line 7 = 21 cycles (or 18 cycles). The number of cycles in parentheses indicates the execution cycles when the routine is not moved to the next higher routine by the command "JTW Z, (HL), WORDDEC_99" or the command "RET NTZ". By providing such a WORDDEC module, it is possible to use the 2-byte command "CALLF WORDDEC" without having to perform word counter subtraction processing within each of the above-mentioned modules, shortening the command and making it possible to secure the capacity of the control area for performing game control processing.

Figure 147 is an explanatory diagram for explaining another example of commands for implementing the WORDDEC module. Here, the commands of the WORDDEC module in Figure 146(b) are replaced with the commands of the WORDDEC module in Figure 147(b), and the commands of any other process that calls the WORDDEC module in Figure 146(a) are used as is, as in Figure 147(a). Here, as in Figure 147(a), explanations of processes that are essentially the same as those in Figure 146(a) are omitted, and only the different processes in Figure 147(b) are explained.

The index "WORDDEC:" on the first line of Figure 147(b) indicates the starting address of the WORDDEC module. The command "DECWM (HL)" on the second line decrements the value stored in the address indicated by the HL register by 1 if it is 1 or greater, and maintains it at 0 if it is 0.

Here, the command "DECWM (HL)" decrements the 2-byte value stored at the address indicated by the HL register, and if the carry flag is set (-1), it forcibly stores 0 in the 2-byte value stored at the address indicated by the HL register. Then, if the value stored at the address indicated by the HL register is 1 or greater, it is decremented by 1, and if it is 0, it remains 0. By executing this command "DECWM (HL)", if the value after decrement is zero (if the value before decrement is 1 or 0), the zero flags (first zero flag and second zero flag) are set to 1, and if the value before decrement is zero, the carry flag is set to 1. The command size of this command is "2", and the execution cycle is "7".

The command "RET NZ" on the third line of Figure 147(b) causes the program to return to the subroutine one level higher if the zero flag is not 1 (if the value after decrement is not zero). In this case, the command "DECWM (HL)" has already performed a decrement, so the fact that the zero flag is not 1 indicates that the value before the decrement was 2 or greater. In this case, the zero flag is not set and is 0, and the carry flag is also not set and is 0, so the program can return to the subroutine one level higher.

In the command "DECWM (HL)", if the value stored in the address indicated by the HL register before the decrement is 1, it becomes 0 after the decrement, and the zero flag = 1 and the carry flag = 0. If the value is 0, the decrement is not performed and the zero flag remains 0, and the zero flag = 1 and the carry flag = 1. In other words, the specifications for the carry flag are the opposite of those shown in FIG. 141. Therefore, the command "CCF" on the fourth line of FIG. 147(b) inverts the carry flag (1 → 0, 0 → 1). Note that the command "CCF" does not change the zero flag. In this way, if the value stored in the address indicated by the HL register before the decrement is 1, the zero flag = 1 and the carry flag = 1, and if the value is 0, the zero flag = 1 and the carry flag = 0. The commands on the second to fourth lines correspond to step S3 in FIG. 145(b). Then, the command "RET" on the fifth line returns to the subroutine one level above. The command on the fifth line corresponds to step S4 in FIG. 145(b). In this way, it is possible to decrement the value stored at the address indicated by the HL register by 1 and set the zero flag and carry flag.

Next, the command "RET NTZ" on the third line of Fig. 147(a) causes the program to return to the subroutine one level higher if the zero flag (second zero flag) is not 1 (if it is 0). This command on the third line corresponds to steps S5 and S6 in Fig. 145(a). In this way, processing based on the results of the WORDDEC module becomes possible.

The total command size of the command of the WORDDEC module in FIG. 147(b) is 2 bytes on line 2 + 1 byte on line 3 + 2 bytes on line 4 + 1 byte on line 5 = 6 bytes, and the total execution cycles are 7 cycles on line 2 + 3 cycles on line 3 (1 cycle) + 2 cycles on line 4 + 3 cycles on line 6 = 15 cycles (13 cycles). The number of cycles in parentheses indicates the execution cycles when the command "RET NZ" does not move to the next higher routine. Therefore, compared to the case in FIG. 146(b), the total command size is reduced by 3 bytes and the total execution cycles are reduced by at least 6 cycles. This WORDDEC module makes it possible to further shorten the command and secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing FIG. 146(b) and FIG. 147(b), the command group that occupies five lines (lines 2 to 6) in FIG. 146(b) can be represented in three lines (lines 2 to 4) in FIG. 147(b), making it possible to reduce the number of commands and lighten the design load.

<Command "RCP">
Fig. 148 is an explanatory diagram for explaining an example of a process for returning from a subroutine. The command "CP A,n" in Fig. 148(a) is a command for comparing the value of the A register with a predetermined value n, and when A=n, the zero flag is set to 1, and when A<n, the carry flag is set to 1. The command size of this command "CP A,n" is "2", and the execution cycle is "2".

The command "RET cc" in FIG. 148(a) refers to the zero flag or carry flag, and if the target flag is 1, returns from a subroutine to the routine one level higher. The command size of this command "RET cc" is "1", and the execution cycle is "3" (or "1"). Note that the number of cycles in parentheses indicates the execution cycle when the command "RET cc" does not move to the routine one level higher (does not return from the subroutine).

Here, as shown in Fig. 148(a), the command "CP A,n" on the first line compares the value of the A register with a specified value n, and the command "RET cc" on the second line determines whether to return from the subroutine depending on the comparison result. Here, these two commands can be combined (replaced) into a single command "RCP cc,A,n" as shown in Fig. 148(b).

The command "RCP cc, A, n" in FIG. 148(b) is a command that compares the value of the A register with a specified value n, and returns from a subroutine to a routine one level higher depending on the result of the comparison. The command size of this command "RCP cc, A, n" is "2", and the execution cycle is "5" (or "3"). Note that the number of cycles in parentheses indicates the execution cycle when the command "RCP cc, A, n" does not move to the routine one level higher.

Here, the total command size of the command group shown in FIG. 148(a) is 2 bytes of the command "CP A,n" on the first line + 1 byte of "RET cc" on the second line = 3 bytes, and the total execution cycle is 2 cycles on the first line + 3 cycles on the second line (1 cycle) = 5 cycles (3 cycles). On the other hand, the command size of the command "RCP cc,A,n" shown in FIG. 148(b) is 2 bytes, and the execution cycle is 5 cycles (3 cycles). Therefore, by replacing the command group in FIG. 148(a) with the command in FIG. 148(b), the total command size is reduced by 1 byte. This replacement makes it possible to further shorten the command and secure the capacity of the control area for performing game control processing. Below, we will explain each of the multiple modules that can be replaced in this way.

Figure 149 is an explanatory diagram for explaining the PY_CMDA module. The PY_CMDA module shown in Figure 149 executes the main command analysis process shown in step S100-63 in Figure 23, that is, the process of analyzing the main command and detecting any abnormalities in the main command.

The index "PY_CMDA:" on the first line of Figure 149(a) indicates the starting address of the PY_CMDA module. The command "LDQ A, (LOW R_BCR_BUF)" on the second line sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_BCR_BUF" that stores the buffer value of the main command to the lower byte of the address, and reads the value stored at that address (main command) into the A register.

Then, after clearing the buffer and executing the payout start command confirmation process, the received data confirmation process uses the command "SUB A, @BCR_PAY_CLR" on the third line of Figure 149 (a) to subtract a fixed value indicated by "@BCR_PAY_CLR", here 20H, from the value of the A register. Then, the command "CP A, 00CH" on the fourth line compares the subtracted value of the A register with 0CH. Here, it is confirmed that the main command is within the range of 20H to 2BH. In other words, if the value of the A register is less than 20H, the command "SUB A, @BCR_PAY_CLR" makes the value of the A register negative, and as a byte value it becomes greater than 0CH. Therefore, if the value of the A register after subtraction is less than 0CH, the command "CP A, 00CH" sets the carry flag to 1. Then, the "RET NC" on line 5 causes the program to return to the routine one level above if the carry flag is not 1. If the carry flag is 1 (if it is in the range of 20H to 2BH), the program executes the payout error command set process and the payout radio wave error flag setting process, and then returns to the routine one level above.

Now, by making the substitutions in FIG. 148, the group of commands in FIG. 149(a) can be changed to those in FIG. 149(b). The index "PY_CMDA:" on the first line of FIG. 149(b) indicates the starting address of the PY_CMDA module. The command "LDQ A, (LOW R_BCR_BUF)" on the first line sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_BCR_BUF" that stores the buffer value of the main command to the lower byte of the address, and reads the value stored at that address (main command) into the A register.

Then, after clearing the buffer and executing the prescribed processing for the payout start command, the command "SUB A, @BCR_PAY_CLR" on the third line of Fig. 149(b) subtracts the fixed value indicated by "@BCR_PAY_CLR", here 20H, from the value of the A register. The command "RCP NC, A, 00CH" on the fourth line compares the subtracted value of the A register with 0CH, and if the carry flag is not 1, returns to the routine one level higher. Here, it is confirmed that the main command is within the range of 20H to 2BH, and if it is not within that range, no further processing is performed and the routine returns to the routine one level higher. Note that if the carry flag is 1, the payout error command set processing and payout radio wave error flag setting processing are executed, and the routine returns to the routine one level higher.

Here, the total command size of the command group shown in FIG. 149(a) is 2 bytes of the command "LDQ A, (LOW R_BCR_BUF)" on line 2 + 2 bytes of the command "SUB A, @BCR_PAY_CLR" on line 3 + 2 bytes of the command "CP A, 00CH" on line 4 + 1 byte of "RET NC" on line 5 = 7 bytes, and the total execution cycles are 3 cycles on line 2 + 2 cycles on line 3 + 2 cycles on line 4 + 3 cycles (1 cycle) on line 5 = 10 cycles (8 cycles). On the other hand, the total command size of the command group shown in FIG. 149(b) is 2 bytes of the command "LDQ A, (LOW R_BCR_BUF)" on the second line + 2 bytes of the command "SUB A, @BCR_PAY_CLR" on the third line + 2 bytes of the command "RCP NC, A, 00CH" on the fourth line = 6 bytes, and the total execution cycle is 3 cycles on the second line + 2 cycles on the third line + 5 cycles on the fourth line (3 cycles) = 10 cycles (8 cycles). Therefore, by replacing the command group in FIG. 149(a) with the command group in FIG. 149(b), the total command size is reduced by 1 byte. This replacement makes it possible to further shorten the commands and ensure the capacity of the control area for performing game control processing.

Figure 150 is an explanatory diagram for explaining the GAT_PAS module. The GAT_PAS module shown in Figure 150 performs the gate switch passing process (gate passing process) shown in step S510 of Figure 29, that is, adds the number of reserved balls with normal symbols according to the passing of a winning ball through the gate detection switch 124s, and executes processing related to normal symbols.

For the memory count check process, the index "GAT_PAS:" on the first line of FIG. 150(a) indicates the starting address of the GAT_PAS module. The command "LDQ DE, LOW R_FZ_MEM" on the second line sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "R_FZ_MEM" as the lower byte of the address, and reads the 2-byte value stored at that address (the address of the regular symbol reserved ball count counter) into the DE register. The command "LD A, (DE)" on the third line reads the value stored at the address indicated by the DE register (i.e., R_FZ_MEM) (the counter value of the regular symbol reserved ball count counter) into the A register.

Then, the command "CP A, @FZ_MEM_MAX" on line 4 of FIG. 150(a) compares the value of the A register with the fixed value "@FZ_MEM_MAX", which is "4" in this case. That is, if the value of the A register is less than 4, the carry flag is set to 1. Then, the "RET NC" on line 5 returns to the routine one step above if the carry flag is not 1. That is, if the counter value of the normal symbol reserved ball counter is 4 or more, the normal symbol reserved ball counter will not be counted any further, so the GAT_PAS module is terminated. Note that if the carry flag is 1, the random number value acquisition process, memory number addition process, winning determination random number acquisition process, transfer destination address calculation process, and memory area storage process are executed, and the routine returns to the routine one step above.

Now, by making the replacement in FIG. 148, the command group in FIG. 150(a) can be changed to that in FIG. 150(b). The index "GAT_PAS:" on the first line of FIG. 150(b) indicates the starting address of the GAT_PAS module. The command "LDQ DE, LOW R_FZ_MEM" on the first line sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "R_FZ_MEM" as the lower byte of the address, and reads the 2-byte value stored at that address (the address of the regular symbol reserved ball counter) into the DE register. The command "LD A, (DE)" on the third line reads the value stored at the address indicated by the DE register (i.e., R_FZ_MEM) (the counter value of the regular symbol reserved ball counter) into the A register.

Then, the command "RCP NC, A, @FZ_MEM_MAX" on the fourth line of Figure 150 (b) compares the value of the A register with @FZ_MEM_MAX, and if the value of the A register is equal to or greater than @FZ_MEM_MAX, the process returns to the routine one level higher. In other words, if the counter value of the normal symbol reserved ball count counter is 4 or greater, the normal symbol reserved ball count counter will not be counted any further, so the GAT_PAS module is terminated. Note that if the carry flag is 1, the memory count addition process, the win determination random number acquisition process, the transfer destination address calculation process, and the memory area storage process are executed, and the process returns to the routine one level higher.

Here, the total command size of the command group shown in Figure 150 (a) is 2 bytes of the command "LDQ DE, LOW R_FZ_MEM" on line 2 + 1 byte of the command "LD A, (DE)" on line 3 + 2 bytes of the command "CP A, @FZ_MEM_MAX" on line 4 + 1 byte of "RET NC" on line 5 = 6 bytes, and the total execution cycles are 2 cycles on line 2 + 2 cycles on line 3 + 2 cycles on line 4 + 3 cycles (1 cycle) on line 5 = 9 cycles (7 cycles). On the other hand, the total command size of the command group shown in FIG. 150(b) is 2 bytes of the command "LDQ DE,LOW R_FZ_MEM" on the second line + 1 byte of the command "LD A, (DE)" on the third line + 2 bytes of the command "RCP NC,A,@FZ_MEM_MAX" on the fourth line = 5 bytes, and the total execution cycle is 2 cycles on the second line + 2 cycles on the third line + 5 cycles (3 cycles) on the fourth line = 9 cycles (7 cycles). Therefore, by replacing the command group in FIG. 150(a) with the command group in FIG. 150(b), the total command size is reduced by 1 byte. This replacement makes it possible to further shorten the commands and ensure the capacity of the control area for performing game control processing.

Figure 151 is an explanatory diagram for explaining the TDN_PAS module. The TDN_PAS module shown in Figure 151 executes the count switch passing process (large prize opening passing process) shown in step S540 of Figure 34, that is, the process of managing the winning of the large prize opening based on the count switch judgment value.

The indicator "TDN_PAS:" on the first line of FIG. 151(a) indicates the starting address of the TDN_PAS module. Then, when the count switch determination value confirmation process, the special electric device continuous operation count determination process, the large prize slot winning designation command set process, and the large prize slot excessive winning monitoring process are executed, the special electric device operation check process uses the command "LDQ A, (LOW R_TDN_PHS)" on the second line to set the value of the Q register as the upper byte of the address, set the value of the lower byte of the address "R_TDN_PHS" as the lower byte of the address, and read the value stored at that address (special electric device play management phase) into the A register.

The command "JCP Z, A, @TD_OPN_BHT, TDN_PAS_10" on the third line of FIG. 151(a) compares the value of the A register with the fixed value "@TD_OPN_BHT", here 2, and if the results are equal, moves to the address "TDN_PAS_10". In this way, if the value of the A register is the big win large prize opening control state designation value (special electric role game play management phase is 02H), the subsequent processing can be omitted and it can move to the index "TDN_PAS_10:" on the sixth line. The command "CP A, @TD_OPN_SHT" on the fourth line compares the value of the A register with the fixed value "@TD_OPN_SHT", here 6, which indicates the small win large prize opening control state designation value, and if they are equal (special electric role game play management phase is 06H), the zero flag is set to 1. Then, by "RET NZ" on the fifth line, if the zero flag is not 1, it returns to the routine one step above. In other words, if the value of the A register is not the large jackpot large prize opening control state designation value or the small jackpot large prize opening control state designation value, the TDN_PAS module is terminated. Note that if the zero flag is 1, it executes the special electric device winning ball count process, the special electric illegal winning detection condition confirmation process, and the special electric illegal winning error process, and then returns to the routine one step above.

Now, by making the replacement in FIG. 148, the command group in FIG. 151(a) can be changed to that in FIG. 151(b). The indicator "TDN_PAS:" on the first line of FIG. 151(b) indicates the starting address of the TDN_PAS module. Then, when the count switch determination value confirmation process, the special electric device continuous operation count determination process, the large prize opening winning designation command set process, and the large prize opening excessive winning monitoring process are executed, the command "LDQ A, (LOW R_TDN_PHS)" on the second line sets the value of the Q register to the upper byte of the address, and the value of the lower byte of the address "R_TDN_PHS" to the lower byte of the address, and the value stored in that address (special electric device play management phase) is read into the A register.

The command "JCP Z, A, @TD_OPN_BHT, TDN_PAS_10" on the third line of Figure 151 (b) compares the value of the A register with a fixed value "@TD_OPN_BHT", here 2, and if the results are equal, moves to address "TDN_PAS_10". In this way, if the value of the A register is the large prize opening control state designation value for the big win, the subsequent processing can be omitted and the program can move to the index "TDN_PAS_10:" on the fifth line. The command "RCP NZ, A, @TD_OPN_SHT" on the fourth line compares the value of the A register with the fixed value "@TD_OPN_SHT", here 6, which indicates the small prize opening control state designation value, and if they are equal, returns to the routine one level above. In other words, if the value of the A register is not the large jackpot opening control state designation value or the small jackpot opening control state designation value, the TDN_PAS module is terminated. If the zero flag is 0, the special electric device winning ball count process, the special line illegal winning detection condition confirmation process, and the special line illegal winning error process are executed, and the routine returns to the next higher level.

Here, the total command size of the command group shown in Figure 151 (a) is 2 bytes of the command "LDQ A, (LOW R_TDN_PHS)" on line 2 + 3 bytes of the command "JCP Z, A, @TD_OPN_BHT, TDN_PAS_10" on line 3 + 2 bytes of the command "CP A, @TD_OPN_SHT" on line 4 + 1 byte of "RET NZ" on line 5 = 8 bytes, and the total execution cycles are 3 cycles on line 2 + 4 cycles (or 3 cycles) on line 3 + 2 cycles on line 4 + 3 cycles (1 cycle) on line 5 = 12 cycles (9 cycles). On the other hand, the total command size of the command group shown in FIG. 151(b) is 2 bytes of the command "LDQ A, (LOW R_TDN_PHS)" on the second line + 3 bytes of the command "JCP Z, A, @TD_OPN_BHT, TDN_PAS_10" on the third line + 2 bytes of the command "RCP NZ, A, @TD_OPN_SHT" on the fourth line = 7 bytes, and the total execution cycle is 3 cycles on the second line + 4 cycles (or 3 cycles) on the third line + 5 cycles (3 cycles) on the fourth line = 12 cycles (9 cycles). Therefore, by replacing the command group in FIG. 151(a) with the command group in FIG. 151(b), the total command size is reduced by 1 byte. Such replacement makes it possible to further shorten the commands and secure the capacity of the control area for performing game control processing.

Figure 152 is an explanatory diagram for explaining the FD_OPN module. The FD_OPN module shown in Figure 152 executes the normal electric device winning opening opening control process shown in step 850 of Figure 57, that is, the opening and closing control process of the first variable start opening 120B for the number of winnings and operation time related to the normal electric device.

The indicator "FD_OPN:" on the first line of FIG. 152(a) indicates the starting address of the FD_OPN module. Then, when the normal electric device winning opening/closing operation switching process is executed, the command "LDQ A, (LOW R_FDN_CNT)" on the second line is used as the specified winning number confirmation process, and the value of the Q register becomes the upper byte of the address, and the value of the lower byte of the address "R_FDN_CNT" becomes the lower byte of the address, and the value stored at that address (the counter value of the normal electric device winning ball count counter) is read into the A register.

The command "CP A, @FDN_CNT" on the third line of Fig. 152(a) compares the value of the A register with the fixed value "@FDN_CNT" (8 in this case) which indicates the maximum number of winning balls in the winning slot for normal electric roles, and if it is less than 8, the carry flag is set to 1. Then, "RET C" on the fourth line returns to the routine one level higher if the carry flag is 1. In other words, if the value of the A register is less than the number of winning balls in the winning slot for normal electric roles, the FD_OPN module is terminated. Note that if the carry flag is 0, the normal electric role operation end setting process is executed and the routine returns to the routine one level higher.

Now, by making the substitutions in FIG. 148, the group of commands in FIG. 152(a) can be changed to those in FIG. 152(b). The indicator "FD_OPN:" on the first line of FIG. 152(b) indicates the starting address of the FD_OPN module. Then, when the normal electric device winning opening/closing operation switching process is executed, the command "LDQ A, (LOW R_FDN_CNT)" on the second line is used as the specified number of winning confirmation process, and the value of the Q register is made the upper byte of the address, and the value of the lower byte of the address "R_FDN_CNT" is made the lower byte of the address, and the value stored at that address (the counter value of the normal electric device winning ball count counter) is read into the A register.

The command "RCP C, A, @FDN_CNT" on the third line of Fig. 152 (b) compares the value of the A register with the fixed value "@FDN_CNT" (8 in this case) which indicates the maximum number of winning balls that can enter the winning slot for normal electric devices, and if it is less than 8, it returns to the routine one level higher. In other words, if the value of the A register is less than the number of winning balls that can enter the winning slot for normal electric devices, the FD_OPN module is terminated. Note that if the carry flag is 0, the normal electric device operation end setting process is executed and the routine returns to the routine one level higher.

Here, the total command size of the command group shown in FIG. 152(a) is 2 bytes of the command "LDQ A, (LOW R_FDN_CNT)" on the second line + 2 bytes of the command "CP A, @FDN_CNT" on the third line + 1 byte of "RET C" on the fourth line = 5 bytes, and the total execution cycle is 3 cycles on the second line + 2 cycles on the third line + 3 cycles (1 cycle) on the fourth line = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 152(b) is 2 bytes of the command "LDQ A, (LOW R_FDN_CNT)" on the second line + 2 bytes of the command "RCP C, A, @FDN_CNT" on the third line = 4 bytes, and the total execution cycle is 3 cycles on the second line + 5 cycles (3 cycles) on the third line = 8 cycles (6 cycles). Therefore, by replacing the command group in FIG. 152(a) with the command group in FIG. 152(b), the total command size is reduced by 1 byte. This replacement makes it possible to further shorten the commands and ensure the capacity of the control area for performing game control processing.

Figure 153 is an explanatory diagram for explaining the TZ_STA module. The TZ_STA module shown in Figure 153 executes the special symbol change waiting process shown in step S610 of Figure 37, that is, the preparation process for the special symbol change based on the number of balls reserved for the special symbol.

The index "TZ_STA:" on the first line of Figure 153 (a) indicates the starting address of the TZ_STA module. Then, when the special symbol reserved ball count confirmation process is executed, the command "RST DATSEL" on the second line calls the DATSEL module, which is a general-purpose module, as a process to confirm the status of the special symbol that is not subject to processing, and the selection result of the control data is stored in the A register.

The command "CP A, @TZ_BHT" on the third line of FIG. 153(a) compares the value of the A register with the fixed value "@TZ_BHT" indicating the special symbol big win information, here 01H, and if it is equal to 01H, the zero flag is set to 1. Then, the "RET Z" on the fourth line returns to the routine one step above if the zero flag is 1. In other words, if the big win is confirmed, the TZ_STA module is terminated. The command "CP A, @TZ_SHT" on the fifth line compares the value of the A register with the fixed value "@TZ_SHT" indicating the special symbol small win information, here 02H, and if it is equal to 02H, the zero flag is set to 1. Then, the "RET Z" on the sixth line returns to the routine one step above if the zero flag is 1. In other words, if the small win is confirmed, the TZ_STA module is terminated. If the zero flag is not 1, the special symbol change start setting process, the number of times command set process, and the special symbol change preparation process are executed, and the process returns to the routine one step above.

Now, by making the replacement in FIG. 148, the group of commands in FIG. 153(a) can be changed to that in FIG. 153(b). The index "TZ_STA:" on the first line of FIG. 153(b) indicates the starting address of the TZ_STA module. Then, when the process to check the number of reserved balls for a special symbol is executed, the command "RST DATSEL" on the second line calls the DATSEL module as a process to check the status of special symbols not subject to processing, and the selection result of the control data is stored in the A register.

The command "RCP Z, A, @TZ_BHT" on the third line of FIG. 153(b) compares the value of the A register with the fixed value "@TZ_BHT" indicating the special symbol big win information, here 01H, and if it is equal to 01H, returns to the routine one step above. In other words, if the big win is confirmed, the TZ_STA module is terminated. The command "RCP Z, A, @TZ_SHT" on the fourth line compares the value of the A register with the fixed value "@TZ_SHT" indicating the special symbol small win information, here 02H, and if it is equal to 02H, returns to the routine one step above. In other words, if the small win is confirmed, the TZ_STA module is terminated. Note that if the zero flag is not 1, the special symbol change start time setting process, the number of times command set process, and the special symbol change preparation process are executed, and the routine one step above is returned to.

Here, the total command size of the command group shown in Figure 153 (a) is 1 byte of the command "RST DATSEL" on line 2 + 2 bytes of the command "CP A, @TZ_BHT" on line 3 + 1 byte of the command "RET Z" on line 4 + 2 bytes of the command "CP A, @TZ_SHT" on line 5 + 1 byte of "RET Z" on line 6 = 7 bytes, and the total execution cycles are 4 cycles on line 2 + 2 cycles on line 3 + 3 cycles (1 cycle) on line 4 + 2 cycles on line 5 + 3 cycles (1 cycle) on line 6 = 14 cycles (10 cycles). On the other hand, the total command size of the command group shown in FIG. 153(b) is 1 byte of the command "RST DATSEL" on the second line + 2 bytes of the command "RCP Z, A, @TZ_BHT" on the third line + 2 bytes of the command "RCP Z, A, @TZ_SHT" on the fourth line = 5 bytes, and the total execution cycle is 4 cycles on the second line + 5 cycles (3 cycles) on the third line + 5 cycles (3 cycles) on the fourth line = 14 cycles (10 cycles). Therefore, by replacing the command group in FIG. 153(a) with the command group in FIG. 153(b), the total command size is reduced by 2 bytes. This replacement makes it possible to further shorten the commands and ensure the capacity of the control area for performing game control processing.

Figure 154 is an explanatory diagram for explaining the TZ_RGET module. The TZ_RGET module shown in Figure 154 executes the special symbol random number acquisition process shown in step S535 of Figure 32, that is, the process of inputting a random number value into a register and storing the random number value in the register in the transfer buffer only if the number of reserved balls is not the upper limit number.

The indicator "TZ_RGET:" on the first line of Figure 154 (a) indicates the starting address of the TZ_RGET module. The jackpot determination random number acquisition process is executed, and the value stored at the address indicated by the DE register (the counter value of the target special pattern reserved ball count counter) is read into the A register by the command "LD A, (DE)" on the second line as the special pattern reserved ball count update process. Note that when the TZ_RGET module is called, the DE register already stores an address indicating the counter value of the target special pattern reserved ball count counter.

Then, the command "CP A, @TZ_MEM_MAX" on the third line of FIG. 154(a) compares the value of the A register with the fixed value "@TZ_MEM_MAX" indicating the upper limit of the number of reserved balls for special symbols, which is "4" here. That is, if the value of the A register is less than 4, the carry flag is set to 1. Then, the "RET NC" on the fourth line returns to the routine one step above if the carry flag is not 1. That is, if the counter value of the target special reserved ball counter is 4 or more, the target special reserved ball counter will not be counted any further, so the TZ_RGET module is terminated. Note that if the carry flag is 1, the variable pattern random number acquisition process, reach group determination random number acquisition process, reach mode determination random number acquisition process, transfer destination address calculation process, memory area storage process, acquisition time performance judgment process, and special reserved designation command set process are executed, and the routine returns to the routine one step above.

Now, by making the substitutions in FIG. 148, the group of commands in FIG. 154(a) can be changed to that in FIG. 154(b). The index "TZ_RGET:" on the first line of FIG. 154(b) indicates the starting address of the TZ_RGET module. The jackpot determination random number acquisition process is executed, and as the special symbol reserved ball count update process, the value stored at the address indicated by the DE register (i.e., the counter value of the target special symbol reserved ball count counter) is read into the A register by the command "LD A, (DE)" on the second line.

Then, the command "RCP NC, A, @TZ_MEM_MAX" on the third line of FIG. 154(b) compares the value of the A register with the fixed value "@TZ_MEM_MAX" indicating the upper limit of the number of reserved balls for special symbols, "4" in this case, and if the value of the A register is 4 or more, the process returns to the routine one step above. In other words, if the counter value of the reserved ball count counter for the target special symbol is 4 or more, the target reserved ball count counter will not be counted any further, so the TZ_RGET module is terminated. Note that if the value of the A register is less than 4, the process executes the variable pattern random number acquisition process, reach group determination random number acquisition process, reach mode determination random number acquisition process, transfer destination address calculation process, memory area storage process, acquisition time performance judgment process, and special symbol reserved designation command set process, and returns to the routine one step above.

Here, the total command size of the command group shown in FIG. 154(a) is 1 byte of the command "LD A, (DE)" on the second line + 2 bytes of the command "CP A, @TZ_MEM_MAX" on the third line + 1 byte of "RET NC" on the fourth line = 4 bytes, and the total execution cycle is 2 cycles on the second line + 2 cycles on the third line + 3 cycles on the fourth line (1 cycle) = 7 cycles (5 cycles). On the other hand, the total command size of the command group shown in FIG. 154(b) is 1 byte of the command "LD A, (DE)" on the second line + 2 bytes of the command "RCP NC, A, @TZ_MEM_MAX" on the third line = 3 bytes, and the total execution cycle is 2 cycles on the second line + 5 cycles on the third line (3 cycles) = 7 cycles (5 cycles). Therefore, by replacing the command group in FIG. 154(a) with the command group in FIG. 154(b), the total command size is reduced by 1 byte. This replacement makes it possible to further shorten commands and secure the capacity of the control area for carrying out game control processing.

Figure 155 is an explanatory diagram for explaining the TRSVSEL module. The TRSVSEL module shown in Figure 155 executes the preliminary area setting process shown in step S610-17 of Figure 37, that is, checks the special symbol win and executes preliminary setting process for the special symbol probability state and special symbol state.

The indicator "TRSVSEL:" on the first line of Figure 155 (a) indicates the starting address of the TRSVSEL module. Then, when the state offset check flag setting process is executed, the command "RST DATSEL" on the second line calls the DATSEL module, which is a general-purpose module, as a special symbol winning confirmation process, and the selection result of the control data is stored in the A register.

The command "CP A, @TZ_BHT" on the third line of Fig. 155(a) compares the value of the A register with the fixed value "@TZ_BHT" indicating the special symbol jackpot information, here 01H, and if it is equal to 01H, the zero flag is set to 1. Then, the "RET NZ" on the fourth line returns to the routine one level higher if the zero flag is not 1. In other words, if the jackpot is not confirmed, the TRSVSEL module is terminated. Note that if the zero flag is 1, the special symbol probability state preliminary setting process and the special symbol state preliminary setting process are executed, and the routine one level higher is returned to.

Now, by making the substitutions in FIG. 148, the command group in FIG. 155(a) can be changed to that in FIG. 155(b). The indicator "TRSVSEL:" on the first line of FIG. 155(b) indicates the starting address of the TRSVSEL module. Then, when the state offset check flag setting process is executed, the DATSEL module is called by the command "RST DATSEL" on the second line as a special symbol winning confirmation process, and the selection result of the control data is stored in the A register.

The command "RCP NZ, A, @TZ_BHT" on the third line of Fig. 155 (b) compares the value of the A register with the fixed value "@TZ_BHT" indicating the special symbol jackpot information, here 01H, and if it is not equal to 01H, it returns to the routine one level higher. In other words, if the jackpot is not confirmed, the TRSVSEL module is terminated. Note that if it is equal to 01H, the special symbol probability state preliminary setting process and the special symbol state preliminary setting process are executed, and the routine returns to the routine one level higher.

Here, the total command size of the command group shown in FIG. 155(a) is 1 byte of the command "RST DATSEL" on the second line + 2 bytes of the command "CP A, @TZ_BHT" on the third line + 1 byte of "RET NZ" on the fourth line = 4 bytes, and the total execution cycle is 4 cycles on the second line + 2 cycles on the third line + 3 cycles on the fourth line (1 cycle) = 9 cycles (7 cycles). On the other hand, the total command size of the command group shown in FIG. 155(b) is 1 byte of the command "RST DATSEL" on the second line + 2 bytes of the command "RCP NZ, A, @TZ_BHT" on the third line = 3 bytes, and the total execution cycle is 4 cycles on the second line + 5 cycles on the third line (3 cycles) = 9 cycles (7 cycles). Therefore, by replacing the command group in FIG. 155(a) with the command group in FIG. 155(b), the total command size is reduced by 1 byte. This replacement makes it possible to further shorten commands and secure the capacity of the control area for carrying out game control processing.

Figure 156 is an explanatory diagram for explaining the TDOVCHK module. The TDOVCHK module shown in Figure 156 executes the large prize opening excess winning monitoring process, which is executed after the large prize opening ball entry command is set (step S540-5) in the count switch passing process (large prize opening passing process) shown in step S540 in Figure 34, i.e., the large prize opening winning ball count counter and the large prize opening excess winning count counter are updated.

The index "TDOVCHK:" on the first line of FIG. 156(a) indicates the starting address of the TDOVCHK module. Then, as a special electric role play management phase confirmation process, the command "LDQ A, (LOW R_TDN_PHS)" on the second line sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "R_TDN_PHS" as the lower byte of the address, and reads the value stored at that address (special electric role play management phase) into the A register.

The command "JCP NC, A, @TD_PRE_SHT, TDOVCHK_10" on the third line of FIG. 156(a) compares the value of the A register with the fixed value "@TD_PRE_SHT", here 05H, and if the result is 05H or higher, moves to the address "TDOVCHK_10". In this way, if the value of the A register is a specified value after the small win big prize opening pre-opening state specified value, the subsequent processing can be omitted and it can move to the index "TDOVCHK_10" on the sixth line. The command "CP A, @TD_OPN_BHT" on the fourth line compares the value of the A register with the fixed value "@TD_OPN_BHT", which indicates the big prize opening control state specified value, here 2, and if they are equal, the zero flag is set to 1. Then, if the zero flag is 1, the "RET Z" on the fifth line returns to the routine one step above. That is, if the value of the A register is the jackpot opening control state designated value, the TDOVCHK module is terminated. If the zero flag is not 1, the process executes the process of updating the large prize opening winning ball count counter, the process of updating the large prize opening excess winning count counter, and the process of processing when the large prize opening excess winning error occurs, and then returns to the routine one step above.

Now, by making the substitutions in FIG. 148, the group of commands in FIG. 156(a) can be changed to those in FIG. 156(b). The index "TDOVCHK:" on the first line of FIG. 156(b) indicates the starting address of the TDOVCHK module. Then, as a special electric role play management phase confirmation process, the command "LDQ A, (LOW R_TDN_PHS)" on the second line sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "R_TDN_PHS" as the lower byte of the address, and reads the value stored at that address (special electric role play management phase) into the A register.

The command "JCP NC, A, @TD_PRE_SHT, TDOVCHK_10" on the third line of Figure 156 (b) compares the value of the A register with a fixed value "@TD_PRE_SHT", here 05H, and if the result is 05H or greater, it moves to address "TDOVCHK_10". In this way, if the value of the A register is a specified value after the small win big prize opening pre-open state specified value, it is possible to skip subsequent processing and move to the index "TDOVCHK_10" on the fifth line. The command "RCP Z, A, @TD_OPN_BHT" on the fourth line compares the value of the A register with a fixed value "@TD_OPN_BHT", here 2, which indicates the big prize opening control state specified value, and if they are equal, it returns to the routine one level above. That is, if the value of the A register is the jackpot opening control state designated value, the TDOVCHK module is terminated. If the zero flag is not 1, the process executes the process of updating the large prize opening winning ball count counter, the process of updating the large prize opening excess winning count counter, and the process of processing when the large prize opening excess winning error occurs, and then returns to the routine one step above.

Here, the total command size of the command group shown in FIG. 156 (a) is 2 bytes of the command "LDQ A, (LOW R_TDN_PHS)" on line 2 + 3 bytes of the command "JCP NC, A, @TD_PRE_SHT, TDOVCHK_10" on line 3 + 2 bytes of the command "CP A, @TD_OPN_BHT" on line 4 + 1 byte of "RET Z" on line 5 = 8 bytes, and the total execution cycles are 3 cycles on line 2 + 4 cycles (or 3 cycles) on line 3 + 2 cycles on line 4 + 3 cycles (1 cycle) on line 5 = 12 cycles (9 cycles). On the other hand, the total command size of the command group shown in FIG. 156(b) is 2 bytes of the command "LDQ A, (LOW R_TDN_PHS)" on the second line + 3 bytes of the command "JCP NC, A, @TD_PRE_SHT, TDOVCHK_10" on the third line + 2 bytes of the command "RCP Z, A, @TD_OPN_BHT" on the fourth line = 7 bytes, and the total execution cycle is 3 cycles on the second line + 4 cycles (or 3 cycles) on the third line + 5 cycles (3 cycles) on the fourth line = 12 cycles (9 cycles). Therefore, by replacing the command group in FIG. 156(a) with the command group in FIG. 156(b), the total command size is reduced by 1 byte. Such a replacement makes it possible to further shorten the commands and secure the capacity of the control area for performing game control processing.

Figure 157 is an explanatory diagram for explaining the BER_CHK module. The BER_CHK module shown in Figure 157 executes the base abnormality error monitoring process, which is a subroutine of the state management process (error management process) shown in step S400-21 in Figure 26, that is, the process of monitoring the counter value of the base abnormality confirmation counter.

For the out switch confirmation process, the index "BER_CHK:" on the first line of FIG. 157(a) indicates the starting address of the BER_CHK module. The command "LDQ HL, LOW R_BAS_CNT" on the second line reads the value of the Q register into the H register, and reads the value of the lowest byte of the address "R_BAS_CNT" into the L register. The command "LD A, (HL)" on the third line reads the value stored at the address indicated by the HL register (i.e., R_BAS_CNT) (the counter value of the base abnormality confirmation counter) into the A register.

Then, the command "CP A, @BAS_CHK_CNT" on line 4 of Figure 157(a) compares the value of the A register with the fixed value "@BAS_CHK_CNT" indicating the number of balls detected with a base abnormality, which is 20 in this case. That is, if the value of the A register is less than 20, the carry flag is set to 1. Then, the "RET C" on line 5 returns to the routine one level higher if the carry flag is 1. That is, if the counter value of the base abnormality confirmation counter is less than 20, the BER_CHK module is terminated. Note that if the carry flag is not 1, security setting processing is executed and the routine returns to the routine one level higher.

Now, by making the substitutions in FIG. 148, the command group in FIG. 157(a) can be changed to that in FIG. 157(b). The index "BER_CHK:" on the first line of FIG. 157(b) indicates the starting address of the BER_CHK module. The command "LDQ HL, LOW R_BAS_CNT" on the second line reads the value of the Q register into the H register, and reads the value of the lowest byte of the address "R_BAS_CNT" (the address that stores the base abnormality confirmation counter) into the L register. The command "LD A, (HL)" on the third line reads the value stored at the address indicated by the HL register (i.e., R_BAS_CNT) (the counter value of the base abnormality confirmation counter) into the A register.

Then, the command "RCP C, A, @BAS_CHK_CNT" on the fourth line of Figure 157 (b) compares the value of the A register with a fixed value "@BAS_CHK_CNT" indicating the number of balls detected as having base abnormalities (here, 20), and if the value of the A register is less than 20, the program returns to the routine one level higher. However, if the value of the A register is 20 or greater, the security setting process is executed and the program returns to the routine one level higher.

Here, the total command size of the command group shown in FIG. 157(a) is 2 bytes of the command "LDQ HL, LOW R_BAS_CNT" on line 2 + 1 byte of the command "LD A, (HL)" on line 3 + 2 bytes of the command "CP A, @BAS_CHK_CNT" on line 4 + 1 byte of the command "RET C" on line 5 = 6 bytes, and the total execution cycles are 2 cycles on line 2 + 2 cycles on line 3 + 2 cycles on line 4 + 3 cycles (1 cycle) on line 5 = 9 cycles (7 cycles). On the other hand, the total command size of the command group shown in FIG. 157(b) is 2 bytes of the command "LDQ HL,LOW R_BAS_CNT" on the second line + 1 byte of the command "LD A, (HL)" on the third line + 2 bytes of the command "RCP C,A,@BAS_CHK_CNT" on the fourth line = 5 bytes, and the total execution cycle is 2 cycles on the second line + 2 cycles on the third line + 5 cycles (3 cycles) on the fourth line = 9 cycles (7 cycles). Therefore, by replacing the command group in FIG. 157(a) with the command group in FIG. 157(b), the total command size is reduced by 1 byte. This replacement makes it possible to further shorten the commands and secure the capacity of the control area for performing game control processing.

Figure 158 is an explanatory diagram for explaining the TEF_SEL module. The TEF_SEL module shown in Figure 158 executes the large prize opening closure effective time selection process, which is a subroutine of the large prize opening closure effective time setting process shown in step S720-9 of Figure 47, that is, the process of selecting the effective time until the large prize opening is closed from a table.

The indicator "TEF_SEL:" on the first line of FIG. 158(a) indicates the starting address of the TEF_SEL module. Then, as a process for selecting the effective time data for closing the large prize opening, the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the second line sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "R_ZUG_CHK_FIX" as the lower byte of the address, and reads the value stored at that address (special symbol determination flag) into the A register.

The command "CP A, @ZUG_SML1" on the third line of Figure 158 (a) compares the value of the A register with the fixed value "@ZUG_SML1" indicating the small win symbol 1 designation data, 07H in this case, and if it is less than 07H, the carry flag is set to 1. Then, the "RET NC" on the fourth line returns to the routine one level higher if the carry flag is not 1. In other words, if the value of the A register is equal to or greater than the small win symbol 1 designation data, the TEF_SEL module is terminated. Note that if the carry flag is 1, the word data selection process is executed and the routine returns to the routine one level higher.

Now, by making the replacement in FIG. 148, the group of commands in FIG. 158(a) can be changed to that in FIG. 158(b). The indicator "TEF_SEL:" on the first line of FIG. 158(b) indicates the starting address of the TEF_SEL module. Then, as a process for selecting the effective time data for closing the large prize opening, the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the second line sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_ZUG_CHK_FIX" to the lower byte of the address, and reads the value stored at that address (special symbol determination flag) into the A register.

The command "RCP NC, A, @ZUG_SML1" on the third line of Figure 158 (b) compares the value of the A register with the fixed value "@ZUG_SML1" indicating the small win symbol 1 designation data, 07H in this case, and if it is 07H or greater, it returns to the routine one level higher. In other words, if the value of the A register is equal to or greater than the small win symbol 1 designation data, the TEF_SEL module is terminated. Note that if the value of the A register is less than the small win symbol 1 designation data, the word data selection process is executed and the routine returns to the routine one level higher.

Here, the total command size of the command group shown in FIG. 158(a) is 2 bytes of the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the second line + 2 bytes of the command "CP A, @ZUG_SML1" on the third line + 1 byte of "RET NC" on the fourth line = 5 bytes, and the total execution cycle is 3 cycles on the second line + 2 cycles on the third line + 3 cycles (1 cycle) on the fourth line = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 158(b) is 2 bytes of the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the second line + 2 bytes of the command "RCP NC, A, @ZUG_SML1" on the third line = 4 bytes, and the total execution cycle is 3 cycles on the second line + 5 cycles (3 cycles) on the third line = 8 cycles (6 cycles). Therefore, by replacing the command group in FIG. 158(a) with the command group in FIG. 158(b), the total command size is reduced by 1 byte. This replacement makes it possible to further shorten the commands and ensure the capacity of the control area for performing game control processing.

The replacement shown in FIG. 148 is called as a subroutine from multiple modules not only in pachinko machines but also in slot machines. For example, the SET_RIG module which executes the reverse push data setting process in the sliding frame number acquisition process in step S2500-35 in FIG. 92, the EXE_SET module which executes the execution flag setting process shown in step S2400-11 in FIG. 91, which selectively transitions depending on the game state and presentation state and executes the preparation process (AT state = "5"), the EXE_SET module which executes the execution flag setting process shown in step S2400-11 in FIG. 91, which selectively transitions depending on the game state and presentation state, It is called from the REG_LOT module which executes REG processing (AT state = "6"), the EXE_SET module which executes the execution flag setting process shown in step S2400-11 in FIG. 91, the BIG_SLT module which executes the BIG stock number lottery process in the BIT_LOT module which executes BIG processing (AT state = "7"), the NAV_SET module which executes the instruction information setting process in the execution flag setting process shown in step S2400-11 in FIG. 91, etc.

Figure 159 is an explanatory diagram for explaining the SET_RIG module. The SET_RIG module shown in Figure 159 executes the reverse push data setting process, i.e., the process of setting the data required for stop control.

The index "SET_RIG:" on the first line of Figure 159(a) indicates the starting address of the SET_RIG module. The command "LDQ A, (LOW _HIT_NUM)" on the second line sets the value of the Q register to the most significant byte of the address, sets the value of the least significant byte of the address "_HIT_NUM" that stores the stop control number to the least significant byte of the address, and reads the value stored at that address (stop control number) into the A register.

Then, as the second stop operation use bit data update process, the command "SUB A, 10" on the third line of FIG. 159(a) subtracts a fixed value "10" from the value of the A register. Then, the command "CP A, 57-10+1" on the fourth line compares the subtracted value of the A register with 48 (57-10+1). Here, it is confirmed that the stop control number is within the range of 10 to 57. In other words, if the value of the A register is less than 10, the command "SUB A, 10" makes the value of the A register a negative value, which is greater than 48 when viewed as a byte value. Therefore, if the subtracted value of the A register is less than 10, the command "CP A, 57-10+1" sets the carry flag to 1. Then, if the carry flag is not 1, the "RET NC" on the fifth line returns to the routine one step above. Note that if the carry flag is 1 (if the stop control number is within the range of 10 to 57), the next process is executed.

Next, the command "LDQ A, (LOW _HIT_NUM)" on line 6 of FIG. 159(a) sets the value of the Q register to the upper byte of the address, the value of the lower byte of the address "_HIT_NUM" that stores the stop control number to the lower byte of the address, and reads the value stored at that address (stop control number) into the A register. The command "CP A, 34" on line 7 compares the value of the A register with a fixed value of "34." Here, it is confirmed that the stop control number is less than 34. If the value of the A register is less than 34, the command "CP A, 34" sets the carry flag to 1. Then, if the carry flag is not 1, the "RET NC" on line 8 returns to the routine one level above. Note that if the carry flag is 1 (if the stop control number is less than 34), the remaining processing is executed and the routine returns to the routine one level above.

Now, by making the substitutions in FIG. 148, the group of commands in FIG. 159(a) can be changed to those in FIG. 159(b). The index "SET_RIG:" on the first line of FIG. 159(b) indicates the starting address of the SET_RIG module. The command "LDQ A, (LOW _HIT_NUM)" on the second line sets the value of the Q register to the most significant byte of the address, sets the value of the least significant byte of the address "_HIT_NUM" that stores the stop control number to the least significant byte of the address, and reads the value stored at that address (stop control number) into the A register.

Then, as a process for updating the bit data used during the second stop operation, the command "SUB A, 10" on the third line of Figure 159 (b) subtracts a fixed value of "10" from the value in the A register. The command "RCP NC, A, 57-10+1" on the fourth line compares the subtracted value in the A register with 48 (57-10+1), and if the carry flag is not 1, returns to the routine one level higher. Here, it is confirmed that the stop control number is within the range of 10 to 57, and if it is not within that range, the process returns to the routine one level higher without performing any further processing. Note that if the carry flag is 1 (if the stop control number is within the range of 10 to 57), the next process is executed.

Next, the command "LDQ A, (LOW _HIT_NUM)" on line 5 of Figure 159 (b) sets the value of the Q register to the upper byte of the address, the value of the lower byte of the address "_HIT_NUM" that stores the stop control number to the lower byte of the address, and reads the value stored at that address (stop control number) into the A register. The command "RCP NC, A, 34" on line 6 compares the value of the A register with a fixed value of "34", and if the carry flag is not 1, returns to the routine one level higher. Here, it is confirmed that the stop control number is less than 34, and if it is 34 or greater, it returns to the routine one level higher without performing any further processing. Note that if the carry flag is 1 (if the stop control number is less than 34), the remaining processing is performed and then the routine one level higher is returned to.

Here, the total command size of the command group shown in FIG. 159(a) is 2 bytes of the command "LDQ A, (LOW _HIT_NUM)" on line 2 + 2 bytes of the command "SUB A, 10" on line 3 + 2 bytes of the command "CP A, 57-10+1" on line 4 + 1 byte of "RET NC" on line 5 + 2 bytes of the command "LDQ A, (LOW _HIT_NUM)" on line 6 + 2 bytes of the command "CP A, 34" on line 7 + 1 byte of "RET NC" on line 8 = 12 bytes, and the total execution cycles are 3 cycles on line 2 + 2 cycles on line 3 + 2 cycles on line 4 + 3 cycles (1 cycle) on line 5 + 3 cycles (1 cycle) on line 6 + 2 cycles on line 7 + 3 cycles (1 cycle) on line 8 = 18 cycles (14 cycles). On the other hand, the total command size of the command group shown in Fig. 159(b) is 2 bytes of the command "LDQ A, (LOW_HIT_NUM)" on the second line + 2 bytes of the command "SUB A, 10" on the third line + 2 bytes of the command "RCP NC, A, 57-10+1" on the fourth line + 2 bytes of the command "LDQ A, (LOW_HIT_NUM)" on the fifth line + 2 bytes of the command "RCP NC, A, 34" on the sixth line = 10 bytes, and the total execution cycles are 3 cycles on the second line + 2 cycles on the third line + 5 cycles (3 cycles) on the fourth line + 3 cycles on the fifth line + 5 cycles (3 cycles) on the sixth line = 18 cycles (14 cycles). Therefore, by replacing the command group in Fig. 159(a) with the command group in Fig. 159(b), the total command size is reduced by 2 bytes. This replacement makes it possible to further shorten commands and secure the capacity of the control area for carrying out game control processing.

Figure 160 is an explanatory diagram for explaining the PRE_LOT module. The PRE_LOT module shown in Figure 160 selectively transitions depending on the game state and presentation state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in Figure 91, and executes preparation processing, i.e., lottery processing when the AT state is a predetermined value (for example, 5).

The index "PRE_LOT:" on the first line of Figure 160 (a) indicates the starting address of the PRE_LOT module. The command "LDQ A, (LOW _TRG_KND)" on the second line sets the value of the Q register to the most significant byte of the address, sets the value of the least significant byte of the address "_TRG_KND" to the least significant byte of the address, and reads the value stored at that address (trigger role type) into the A register.

The command "CP A, @LOT_OFS_1FK" on the third line of Fig. 160(a) compares the value of the A register with the fixed value "@LOT_OFS_1FK" (3 in this case) which indicates "1 fake" as the trigger role type, and if it is less than 3, the carry flag is set to 1. Then, "RET C" on the fourth line returns to the routine one level higher if the carry flag is 1. In other words, if the value of the A register is less than the fixed value indicating "1 fake", the PRE_LOT module is terminated. Note that if the carry flag is 0, the REG start time setting process, BIG start time BIG stock lottery process, and BIG start time setting process are executed, and then the routine one level higher is returned to.

Now, by making the substitutions in FIG. 148, the group of commands in FIG. 160(a) can be changed to those in FIG. 160(b). The index "PRE_LOT:" on the first line of FIG. 160(b) indicates the starting address of the PRE_LOT module. The command "LDQ A, (LOW _TRG_KND)" on the second line makes the value of the Q register the most significant byte of the address, the value of the least significant byte of the address "_TRG_KND" the least significant byte of the address, and reads the value stored at that address (trigger role type) into the A register.

The command "RCP C, A, @LOT_OFS_1FK" on the third line of Fig. 160(b) compares the value of the A register with the fixed value "@LOT_OFS_1FK" (3 in this case) which indicates "1 fake" as the trigger role type, and if it is less than 3, it returns to the routine one level above. In other words, if the value of the A register is less than the fixed value which indicates "1 fake", the PRE_LOT module is terminated.

Here, the total command size of the command group shown in FIG. 160(a) is 2 bytes of the command "LDQ A, (LOW _TRG_KND)" on the second line + 2 bytes of the command "CP A, @LOT_OFS_1FK" on the third line + 1 byte of "RET C" on the third line = 5 bytes, and the total execution cycle is 3 cycles on the second line + 2 cycles on the third line + 3 cycles (1 cycle) on the fourth line = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 160(b) is 2 bytes of the command "LDQ A, (LOW _TRG_KND)" on the second line + 2 bytes of the command "RCP C, A, @LOT_OFS_1FK" on the third line = 4 bytes, and the total execution cycle is 3 cycles on the second line + 5 cycles (3 cycles) on the third line = 8 cycles (6 cycles). Therefore, by replacing the command group in FIG. 160(a) with the command group in FIG. 160(b), the total command size is reduced by 1 byte. This replacement makes it possible to further shorten the commands and ensure the capacity of the control area for performing game control processing.

Figure 161 is an explanatory diagram for explaining the REG_LOT module. The REG_LOT module shown in Figure 161 selectively transitions depending on the game state and presentation state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in Figure 91, and executes processing during REG, that is, lottery processing when the AT state is a predetermined value (for example, 6).

The index "REG_LOT:" on the first line of Figure 161 (a) indicates the starting address of the REG_LOT module. The command "LDQ A, (LOW _TRG_KND)" on the second line sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "_TRG_KND" to the lower byte of the address, and reads the value stored at that address (trigger role type) into the A register.

The command "CP A, @LOT_OFS_PDJ" on the third line of Fig. 161(a) compares the value of the A register with the fixed value "@LOT_OFS_PDJ" (5 in this case) which indicates the trigger role type "batting order bell", and if it is 5, the zero flag is raised and becomes 1. Then, the "RET NZ" on the fourth line returns to the routine one level higher if the zero flag is not 1. In other words, if the value of the A register is not the fixed value which indicates "batting order bell", the REG_LOT module is terminated. Note that if the zero flag is 0, the REG remaining number of navigations is subtracted and the REG end time setting process is executed, and then the routine one level higher is returned to.

Now, by making the substitutions in FIG. 148, the group of commands in FIG. 161(a) can be changed to those in FIG. 161(b). The index "REG_LOT:" on the first line of FIG. 161(b) indicates the starting address of the REG_LOT module. The command "LDQ A, (LOW _TRG_KND)" on the second line makes the value of the Q register the most significant byte of the address, the value of the least significant byte of the address "_TRG_KND" the least significant byte of the address, and reads the value stored at that address (trigger role type) into the A register.

The command "RCP NZ, A, @LOT_OFS_PDJ" on the third line of FIG. 161(b) compares the value of the A register with the fixed value "@LOT_OFS_PDJ" (5 in this case) that indicates the "batting order bell" as the trigger role type, and if it is not 5, returns to the routine one level above. In other words, if the value of the A register is not the fixed value that indicates the "batting order bell", the REG_LOT module is terminated.

Here, the total command size of the command group shown in FIG. 161(a) is 2 bytes of the command "LDQ A, (LOW _TRG_KND)" on the second line + 2 bytes of the command "CP A, @LOT_OFS_PDJ" on the third line + 1 byte of "RET NZ" on the fourth line = 5 bytes, and the total execution cycle is 3 cycles on the second line + 2 cycles on the third line + 3 cycles (1 cycle) on the fourth line = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 161(b) is 2 bytes of the command "LDQ A, (LOW _TRG_KND)" on the second line + 2 bytes of the command "RCP NZ, A, @LOT_OFS_PDJ" on the third line = 4 bytes, and the total execution cycle is 3 cycles on the second line + 5 cycles (3 cycles) on the third line = 8 cycles (6 cycles). Therefore, by replacing the command group in FIG. 161(a) with the command group in FIG. 161(b), the total command size is reduced by 1 byte. This replacement makes it possible to further shorten the commands and ensure the capacity of the control area for performing game control processing.

Figure 162 is an explanatory diagram for explaining the BIG_SLT module. The BIG_SLT module shown in Figure 162 executes the BIG stock number lottery process.

The index "BIG_SLT:" on the first line of FIG. 162(a) indicates the starting address of the BIG_SLT module. The command "LDQ A, (LOW _TRG_KND)" on the second line sets the value of the Q register to the most significant byte of the address, sets the value of the least significant byte of the address "_TRG_KND" to the least significant byte of the address, and reads the value stored at that address (trigger role type) into the A register.

The command "CP A, @LOT_OFS_LCY" on the third line of Fig. 162(a) compares the value of the A register with the fixed value "@LOT_OFS_LCY" (6 in this case) which indicates the trigger role type of "weak cherry", and if it is less than 6, the carry flag is set to 1. Then, the "RET C" on the fourth line returns to the routine one level higher if the carry flag is 1. In other words, if the value of the A register is less than the fixed value indicating "weak cherry", the BIG_SLT module is terminated. Note that if the carry flag is 0, the BIG stock drawing process is executed and the routine returns to the routine one level higher.

Now, by making the substitutions in FIG. 148, the group of commands in FIG. 162(a) can be changed to those in FIG. 162(b). The index "BIG_SLT:" on the first line of FIG. 162(b) indicates the starting address of the BIG_SLT module. The command "LDQ A, (LOW _TRG_KND)" on the second line sets the value of the Q register to the most significant byte of the address, sets the value of the least significant byte of the address "_TRG_KND" to the least significant byte of the address, and reads the value stored at that address (trigger role type) into the A register.

The command "RCP C, A, @LOT_OFS_LCY" on the third line of Fig. 162(b) compares the value of the A register with the fixed value "@LOT_OFS_LCY" (6 in this case) which indicates the trigger role type "Weak Cherry", and if it is less than 6, it returns to the routine one level above. In other words, if the value of the A register is less than the fixed value which indicates "Weak Cherry", the BIG_SLT module is terminated.

Here, the total command size of the command group shown in FIG. 162(a) is 2 bytes of the command "LDQ A, (LOW _TRG_KND)" on the second line + 2 bytes of the command "CP A, @LOT_OFS_LCY" on the third line + 1 byte of "RET C" on the fourth line = 5 bytes, and the total execution cycle is 3 cycles on the second line + 2 cycles on the third line + 3 cycles (1 cycle) on the fourth line = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 162(b) is 2 bytes of the command "LDQ A, (LOW _TRG_KND)" on the second line + 2 bytes of the command "RCP C, A, @LOT_OFS_LCY" on the third line = 4 bytes, and the total execution cycle is 3 cycles on the second line + 5 cycles (3 cycles) on the third line = 8 cycles (6 cycles). Therefore, by replacing the command group in FIG. 162(a) with the command group in FIG. 162(b), the total command size is reduced by 1 byte. This replacement makes it possible to further shorten the commands and ensure the capacity of the control area for performing game control processing.

Figure 163 is an explanatory diagram for explaining the NAV_SET module. The NAV_SET module shown in Figure 163 executes the instruction information setting process, i.e., the process of setting the instruction information type.

The index "NAV_SET:" on the first line of Figure 163 (a) indicates the starting address of the NAV_SET module. The command "LDQ A, (LOW _YRI_LMP)" on the second line sets the value of the Q register to the most significant byte of the address, sets the value of the least significant byte of the address "_YRI_LMP" to the least significant byte of the address, and reads the value stored at that address (valid lamp flag) into the A register.

The command "CP A, @AT_MOD_PRE" on the third line of Figure 163 (a) compares the value of the A register with the fixed value "@AT_MOD_PRE" (5 in this case) which indicates that the AT state definition is "in preparation", and if it is less than 5, the carry flag is raised and becomes 1. Then, the "RET C" on the fourth line returns to the routine one level higher if the carry flag is 1. In other words, if the value of the A register is less than the fixed value indicating "in preparation", the NAV_SET module is terminated. Note that if the carry flag is 0, the remaining processing is executed and the routine returns to the routine one level higher.

Now, by making the substitutions in FIG. 148, the command group in FIG. 163(a) can be changed to that in FIG. 163(b). The index "NAV_SET:" on the first line of FIG. 163(b) indicates the starting address of the NAV_SET module. The command "LDQ A, (LOW _YRI_LMP)" on the second line makes the value of the Q register the most significant byte of the address, the value of the least significant byte of the address "_YRI_LMP" the least significant byte of the address, and reads the value stored at that address (valid lamp flag) into the A register.

The command "RCP C, A, @AT_MOD_PRE" on the third line of Fig. 163(b) compares the value of the A register with the fixed value "@AT_MOD_PRE" (5 in this case) which indicates that the AT state definition is "in preparation", and if it is less than 5, returns to the routine one level above. In other words, if the value of the A register is less than the fixed value indicating "in preparation", the NAV_SET module is terminated.

Here, the total command size of the command group shown in FIG. 163(a) is 2 bytes of the command "LDQ A, (LOW _YRI_LMP)" on the second line + 2 bytes of the command "CP A, @AT_MOD_PRE" on the third line + 1 byte of "RET C" on the fourth line = 5 bytes, and the total execution cycles are 3 cycles on the second line + 2 cycles on the third line + 3 cycles (1 cycle) on the fourth line = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 163(b) is 2 bytes of the command "LDQ A, (LOW _YRI_LMP" on the second line + 2 bytes of the command "RCP C, A, @AT_MOD_PRE" on the third line = 4 bytes, and the total execution cycles are 3 cycles on the second line + 5 cycles on the third line (3 cycles) = 8 cycles (6 cycles). Therefore, by replacing the command group in FIG. 163(a) with the command group in FIG. 163(b), the total command size is reduced by 1 byte. Such a replacement makes it possible to further shorten the commands and ensure the capacity of the control area for performing game control processing.

<XORQ>
164 is a flow chart showing the specific processing of the TOK_PRC module. The TOK_PRC module executes the special game management processing of step S600 (see FIG. 36). The numerical values of step S in this figure are used only in the explanation of this figure.

As shown in FIG. 164, the main CPU 300a loads the special game special symbol determination flag (S1), inverts the loaded special game special symbol determination flag (S2), and saves the inverted special game special symbol determination flag (S3). Note that step S1 corresponds to step S600-5 in FIG. 36, step S2 corresponds to step S600-7 in FIG. 36, and step S3 corresponds to step S600-9 in FIG. 36.

Figure 165 is an explanatory diagram for explaining an example of a command for implementing the TOK_PRC module. The flowchart shown in Figure 164 is implemented, for example, by the program shown in Figure 165.

The index "TOK_PRC:" on the first line of FIG. 165(a) indicates the starting address of the TOK_PRC module. Then, as a special game management process, the command "LDQ A, (LOW R_STA_TZ)" on the second line of FIG. 165(a) sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "R_STA_TZ" as the lower byte of the address, and reads the value stored at that address (special game special symbol determination flag) into the A register. This command on the second line corresponds to step S1 in FIG. 164. The command "XOR 001H" on the third line calculates the exclusive OR of the read value (special game special symbol determination flag) and a fixed value (here, 001H). This inverts the special game special symbol determination flag. This command on the second line corresponds to step S2 in FIG. 164. Then, the command on line 4, "LDQ (LOW R_STA_TZ), A," sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_STA_TZ" to the lower byte of the address, and stores the value of the A register at that address. This command on line 4 corresponds to step S3 in FIG. 164.

Here, the group of commands in FIG. 165(a) can be changed to that in FIG. 165(b). The index "TOK_PRC:" on the first line of FIG. 165(b) indicates the starting address of the TOK_PRC module. Then, when the special game management process is executed, the command on the second line "XORQ (LOW R_STA_TZ), 001H" sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_STA_TZ" to the lower byte of the address, calculates the exclusive OR of the value stored at that address (special game special symbol determination flag) and a fixed value (here, 001H), and stores the calculation result at the same address.

Here, the total command size of the command group shown in FIG. 165(a) is 2 bytes of the command "LDQ A, (LOW R_STA_TZ)" on the second line + 2 bytes of the command "XOR 001H" on the third line + 2 bytes of the command "LDQ (LOW R_STA_TZ), A" on the fourth line = 6 bytes, and the total execution cycle is 3 cycles on the second line + 2 cycles on the third line + 3 cycles on the fourth line = 8 cycles. On the other hand, the total command size of the command group shown in FIG. 165(b) is 4 bytes of "XORQ (LOW R_STA_TZ), 001H" = 4 bytes, and the total execution cycle is 7 cycles on the second line = 7 cycles. Therefore, by replacing the command group in FIG. 165(a) with the command group in FIG. 165(b), the total command size is reduced by 2 bytes and the total execution cycle is also reduced by at least 1 cycle. This replacement shortens commands and reduces processing load, making it possible to secure control area capacity for game control processing.

In addition, as can be seen by comparing Figures 165(a) and 165(b), the command group that occupies three lines (lines 2 to 4) in Figure 165(a) can be represented in one line (line 2) in Figure 165(b), making it possible to reduce the number of commands and lighten the design load.

In addition, in the example of FIG. 165(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. Also, in the example of FIG. 165(a), if the A register was already in use, it was necessary to save the value of the A register by stacking, but here, since the A register is not used, stack processing is not necessary. In this way, resources can be used efficiently.

<CPQ>
Fig. 166 is a flow chart showing the specific processing of the TEF_SEL module. The TOK_PRC module is executed when the special electric device play timer is set to the special winning hole closing effective time (step S720-9) in the special winning hole opening control process (see Fig. 47). The numerical values of step S in this figure are used only in the explanation of this figure.

As shown in FIG. 166, the main CPU 300a sets the effective time for closing the large prize opening for small prize play (S1), loads the special symbol determination flag (S2), and compares the loaded special symbol determination flag with a predetermined value (here, 007H) indicating a small prize symbol (S3). The special symbol determination flag is set to 00H if the symbol is a losing symbol, one of 01H to 06H if the symbol is a large prize symbol, and one of 07H to 09H if the symbol is a small prize symbol.

If the comparison result is a small win symbol (YES in S4), the TEF_SEL module is terminated (S6); if the comparison result is not a small win symbol (NO in S4), that is, if it is a big win symbol, the large win opening closure effective time table for the big prize game is set (S5), and the TEF_SEL module is terminated (S6).

Figure 167 is an explanatory diagram for explaining an example of a command for implementing the TEF_SEL module. The flowchart shown in Figure 166 is implemented, for example, by the program shown in Figure 167.

The index "TEF_SEL:" on the first line of FIG. 167(a) indicates the starting address of the TEF_SEL module. The command "LD HL, @TMR_TDN_EF3" on the second line of FIG. 167(a) stores the value of "@TMR_TDN_EF3" in the HL register. Note that "@TMR_TDN_EF3" is set to the effective time for closing the large prize opening for small prize games. This command on the first line corresponds to step S1 in FIG. 166.

The command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the third line of FIG. 167(a) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_ZUG_CHK_FIX" to the lower byte of the address, and reads the value stored at that address (special symbol determination flag) into the A register. This command on the third line corresponds to step S2 in FIG. 166.

The command "CP A, @ZUG_SML1" on the fourth line of Figure 167(a) compares the value of the A register with the fixed value "@ZUG_SML1" indicating the small win pattern 1 designation data (small win pattern), here 07H, and if the value of the A register is less than 07H, the carry flag is set to 1. This command on the fourth line corresponds to step S3 in Figure 166.

Then, the command "RET NC" on the fifth line of FIG. 167(a) returns to the routine one step above if the carry flag is not 1. In other words, if the value of the A register is equal to or greater than the data specifying small win pattern 1, the TEF_SEL module is terminated. This command on the fifth line corresponds to YES in step S4 and step S6 in FIG. 166.

On the other hand, if the carry flag is 1, the command "LDQ A, (LOW R_TDN_FLG)" on line 6 of Fig. 167(a) sets the value of the Q register to the upper byte of the address, the value of the lower byte of the address "R_TDN_FLG" to the lower byte of the address, the value stored at that address (special electric feature designation flag) is read into the A register, and the command "LD HL, D_EFF_TMR-2" on line 7 of Fig. 167(a) sets the top address "D_EFF_TMR-2" of the 1-byte data group to be transferred in the HL register.

The command "RST WORDSEL" on line 8 of Fig. 167(a) calls the WORDSEL module as a subroutine, adds the value of the A register to the HL register twice, and reads the value of the lower byte of the address indicated in the HL register into the A register. Then, the command "RET" on line 9 of Fig. 167(a) returns to the routine one level higher. In the subsequent routine one level higher (in subsequent processing), the effective time for closing the large prize opening for the large prize game is set in the timer. Lines 6 to 8 correspond to step S5 in Fig. 166.

The command group in FIG. 167(a) can be changed to that in FIG. 167(b). Here, we will omit the explanation of the processing that is essentially the same as in FIG. 167(a), and only explain the different processing in FIG. 167(b).

The command "CPQ (LOW R_ZUG_CHK_FIX), @ZUG_SML1" on the third line of Figure 167 (b) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_ZUG_CHK_FIX" to the lower byte of the address, and compares the value stored at that address (special pattern determination flag) with the fixed value "@ZUG_SML1" indicating the small win pattern 1 designation data (small win pattern), here 07H, and if it is less than 07H, the carry flag is set to 1. This command on the third line corresponds to steps S2 and S3 of Figure 166. The command size of this command is "3", and the execution cycle is "4".

Here, the total command size of the command group shown in FIG. 167(a) is the following: 3 bytes of the command "LD HL, @TMR_TDN_EF3" on the second line + 2 bytes of the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the third line + 2 bytes of the command "CP A, @ZUG_SML1" on the fourth line + 1 byte of "RET NC" on the fifth line + 2 bytes of the command "LDQ A, (LOW R_TDN_FLG)" on the sixth line + 3 bytes of the command "LD HL, D_EFF_TMR-2" on the seventh line + 3 bytes of the command "RST" on the eighth line 1 byte of "WORDSEL" + 1 byte of "RET" on line 9 = 15 bytes, and the execution cycles are 3 cycles on line 2 + 2 cycles on line 3 + 2 cycles on line 4 + 3 cycles on line 5 (1 cycle) + 2 cycles on line 6 + 3 cycles on line 7 + 4 cycles on line 8 + 3 cycles on line 9 = 22 cycles (20 cycles). Note that the number of cycles in parentheses indicates the execution cycles if the "RET NC" command is not used to move to the next higher routine.

On the other hand, the total command size of the command group shown in FIG. 167(b) is 3 bytes of the command "LD HL, @TMR_TDN_EF3" on line 2 + 3 bytes of the command "CPQ (LOW R_ZUG_CHK_FIX), @ZUG_SML1" on line 3 + 1 byte of the command "RET NC" on line 4 + 2 bytes of the command "LDQ A, (LOW R_TDN_FLG)" on line 5 + 3 bytes of the command "LD HL, D_EFF_TMR-2" on line 6 + 1 byte of the command "RST WORDSEL" on line 7 + 1 byte of the command "RET" on line 8 = 14 bytes, and the execution cycles are 3 cycles on line 2 + 4 cycles on line 3 + 3 cycles on line 4 (1 cycle) + 2 cycles on line 5 + 3 cycles on line 6 + 4 cycles on line 7 + 3 cycles on line 8 = 22 cycles (20 cycles). Note that the number of cycles in parentheses indicates the execution cycles if the "RET NC" command is not used to move to the next higher routine.

Therefore, by replacing the command group in FIG. 167(a) with the command group in FIG. 167(b), the total command size is reduced by 1 byte. This replacement shortens the commands and makes it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 167(a) and 167(b), the command group that occupies two lines (third and fourth lines) in Figure 167(a) can be represented in one line (third line) in Figure 167(b), making it possible to reduce the number of commands and lighten the design load.

In addition, in the example of FIG. 167(b), the A register is not used in the command on line 3. Therefore, the value of the A register will not be updated unintentionally. Also, in the example of FIG. 167(a), if the A register was already in use when executing the command on line 3, it would have been necessary to stack and save the value of the A register, but here, since the A register is not used, stack processing is not required. In this way, resources can be used efficiently.

<JTANDQ>
168 is a flow chart showing the specific processing of the SWI_PRC module. The SWI_PRC module executes the switch management processing of step S500 (see FIG. 28). The numerical values of step S in this figure are used only in the explanation of this figure.

As shown in FIG. 168, the main CPU 300a determines whether the first variable start hole detection switch 120Bs is detected (S1), and if the first variable start hole detection switch 120Bs is detected (YES in S1), it executes the first start hole passing process (S2) and the normal electric role winning confirmation process (S3). On the other hand, if the first variable start hole detection switch 120Bs is not detected (NO in S1), the first start hole passing process (S2) and the normal electric role winning confirmation process (S3) are skipped. Note that step S1 corresponds to step S500-7 in FIG. 28, step S2 corresponds to step S520 in FIG. 28, and step S3 corresponds to step S500-9 in FIG. 28.

Figure 169 is an explanatory diagram for explaining an example of a command for implementing the SWI_PRC module. The flowchart shown in Figure 168 is implemented, for example, by the program shown in Figure 169.

The index "SWI_PRC:" on the first line of FIG. 169(a) indicates the starting address of the SWI_PRC module. Then, the command "LDQ A, (LOW R_IN3_PON)" on the second line of FIG. 169(a) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_IN3_PON" to the lower byte of the address, and reads the value stored at that address into the A register. Note that here, for example, the value stored at the same address holds the detection result of the first fixed start port detection switch 120As (input section) in the lowest bit, holds the detection result of the second start port detection switch 122s (input section) in the lowest 2 bits, and holds the detection result of the first variable start port detection switch 120Bs (input section) in the lowest 3 bits. Each of these bits becomes "1" when the detection switch detects that a game ball has entered the machine, and becomes "0" when the detection switch does not detect that a game ball has entered the machine.

The command on the third line, "AND A, @IN3_ST2_BIT", calculates the logical product of the read value and the fixed value "@IN3_ST2_BIT (here, 00000100b)". As a result, all bits except the 3rd lowest bit of the read value are set to 0 (masked), and if the 3rd lowest bit of the read value is 0, the zero flag = 1, and if the 3rd lowest bit of the read value is 1, the zero flag = 0. In other words, if the detection result of the first variable start hole detection switch 120Bs is 1 (if a game ball has been detected), the zero flag = 0, and if the detection result of the first variable start hole detection switch 120Bs is 0 (if a game ball has not been detected), the zero flag = 0.

Then, the command on line 4, "JR Z, SWI_PRC_20", moves to SWI_PRC_20 (line 7) if the zero flag is 1 (Z). The commands on lines 2 to 4 correspond to step S1 in FIG. 168.

On the other hand, if the zero flag is not 1 by the command "JR Z,SWI_PRC_20" on the fourth line, the command "CALLF STA_PAS" on the fifth line calls the STA_PAS module as a subroutine, and the STA_PAS module executes the first starting gate passing process. This command on the fifth line corresponds to step S2 in FIG. 168. Also, the command "CALLF FDN_CHK" on the sixth line calls the FDN_CHK module as a subroutine, and the FDN_CHK module executes the confirmation process when a normal electric role wins. This command on the sixth line corresponds to step S3 in FIG. 168.

The command group in FIG. 169(a) can be changed to that in FIG. 169(b). Here, we will omit the explanation of the processing that is essentially the same as in FIG. 169(a), and only explain the different processing in FIG. 169(b).

The command "JTANDQ Z, (LOW R_IN3_PON), @IN3_ST2_BIT, SWI_PRC_20" on the second line of Figure 169 (b) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_IN3_PON" to the lower byte of the address, calculates the logical product of the value stored at that address and the fixed value "@IN3_ST2_BIT", and if the zero flag is 1, moves to SWI_PRC_20. This command on the second line corresponds to step S1 in Figure 168. The command size of this command is "4", and the execution cycle is "5 (6)". Note that the number of cycles in parentheses indicates the execution cycle when the zero flag is 1 and moves to SWI_PRC_20.

The total command size of the command group shown in FIG. 169(a) is 2 bytes of the command "LDQ A, (LOW R_IN3_PON)" on the second line + 2 bytes of the command "AND A, @IN3_ST2_BIT" on the third line + 2 bytes of the command "JR Z, SWI_PRC_20" on the fourth line + 2 bytes of the command "CALLF STA_PAS" on the fifth line + 2 bytes of the command "CALLF FDN_CHK" on the sixth line = 10 bytes, and the total execution cycles are 3 cycles on the second line + 2 cycles on the third line + 2 (3) cycles on the fourth line + 4 cycles on the fifth line + 4 cycles on the sixth line = 15 (16) cycles. The number of cycles in parentheses indicates the execution cycles when the zero flag is 1 and it moves to SWI_PRC_20.

On the other hand, the total command size of the command group shown in FIG. 169(b) is 4 bytes of the command "JTANDQ Z, (LOW R_IN3_PON), @IN3_ST2_BIT, SWI_PRC_20" on line 2 + 2 bytes of the command "CALLF STA_PAS" on line 3 + 2 bytes of the command "CALLF FDN_CHK" on line 4 = 8 bytes, and the total execution cycles are 5 (6) cycles on line 2 + 4 cycles on line 3 + 4 cycles on line 4 = 13 (14) cycles.

Therefore, by replacing the command group in FIG. 169(a) with the command group in FIG. 169(b), the total command size is reduced by 2 bytes, and the total execution cycles are also reduced by at least 2 cycles. This replacement shortens the commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 169(a) and 169(b), the command group that occupies three lines (lines 2 to 4) in Figure 169(a) can be represented in one line (line 2) in Figure 169(b), making it possible to reduce the number of commands and lighten the design load.

In addition, in the example of FIG. 169(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. Also, in the example of FIG. 169(a), if the A register was already in use, it was necessary to save the value of the A register by stacking, but here, since the A register is not used, stack processing is not required. In this way, resources can be used efficiently.

<OUT>
170 is a flow chart showing the specific processing of the CPUINIT module. The CPUINIT module executes the CPU initialization processing (see FIG. 22). The numerical values of step S in this figure are used only in the explanation of this figure.

The main CPU 300a executes access permission processing to permit access to the RAM 300c (S1), as shown in FIG. 170. Note that step S1 corresponds to step S100-9 in FIG. 22.

Figure 171 is an explanatory diagram for explaining an example of a command for implementing the CPUINIT module. The flowchart shown in Figure 170 is implemented, for example, by the program shown in Figure 171.

The index "CPUINIT:" on the first line of FIG. 171(a) indicates the start address of the CPUINIT module. The command "LD A, (@RAMENBL)" on the second line of FIG. 171(a) reads the fixed value "@RAMENBL" (here, 1) indicating that access is permitted into the A register. The command "OUT (@RAP___), A" on the third line of FIG. 171(a) sets the value of the U register to the upper byte of the address, sets the fixed value "@RAP___" indicating the lower byte of the address of the RAM access protection register port (internal register I/O port) to the lower byte, and outputs the value of the A register (1) to that address. The upper byte (for example, "FEH") of the address of the RAM access protection register port (internal register I/O port) is preset in the U register.

The command group in FIG. 171(a) can be changed to that in FIG. 171(b). Here, we will omit the explanation of the processing that is essentially the same as in FIG. 171(a), and only explain the different processing in FIG. 171(b).

The command "OUT (@RAP___), @RAMENBL" on the second line of Figure 171 (b) sets the value of the U register to the upper byte of the address, sets the fixed value "@RAP___" indicating the lower byte of the address of the RAM access protect register port (internal register I/O port) to the lower byte, and outputs the fixed value "@RAMENBL", i.e., 1, to that address. The command size of this command is "3", and the execution cycle is "4".

The total command size of the command group shown in FIG. 171(a) is 2 bytes for the command "LD A, (@RAMENBL)" on the second line + 2 bytes for the command "OUT (@RAP____), A" on the third line = 4 bytes, and the total execution cycles are 2 cycles on the second line + 3 cycles on the third line = 5 cycles.

On the other hand, the total command size of the command group shown in FIG. 171(b) is the command "OUT (@RAP_____), @RAMENBL" on line 2, which is 3 bytes = 3 bytes, and the total execution cycles are line 2, which is 4 cycles = 4 cycles.

Therefore, by replacing the command group in FIG. 171(a) with the command group in FIG. 171(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. This replacement shortens the commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 171(a) and 171(b), a group of commands that occupy two lines (lines 2 and 3) in Figure 171(a) can be represented in one line (line 2) in Figure 171(b), making it possible to reduce the number of commands and lighten the design load.

In addition, in the example of FIG. 171(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. Also, in the example of FIG. 171(a), if the A register was already in use, it was necessary to save the value of the A register by stacking it, but here, since the A register is not used, stack processing is not required. In this way, resources can be used efficiently.

Figure 172 is an explanatory diagram for explaining the TMR_IPT module. The TMR_IPT module shown in Figure 172 executes the timer interrupt processing shown in Figure 98.

The index "TMR_IPT:" on the first line of FIG. 172(a) indicates the start address of the TMR_IPT module. The command "LD A, @TOCRVAL" on the second line of FIG. 172(a) reads the fixed value "@TOCRVAL" (here, 1) indicating that access is permitted into the A register. The command "OUT (@PTOCR_), A" on the third line of FIG. 172(a) sets the value of the U register to the upper byte of the address, sets the fixed value "@PTOCR_" indicating the lower byte of the address of the RAM access protect register port (internal register I/O port) to the lower byte of the address, and outputs the value of the A register (1) to that address. The upper byte (e.g. "FEH") of the address of the RAM access protect register port (internal register I/O port) is preset in the U register.

The command group in FIG. 172(a) can be changed to that in FIG. 172(b). Here, we will omit the explanation of the processing that is essentially the same as in FIG. 172(a), and only explain the different processing in FIG. 172(b).

The command "OUT (@PTOCR_), @TOCRVAL" on the second line of Figure 172 (b) sets the value of the U register to the upper byte of the address, sets the fixed value "@PTOCR_" indicating the lower byte of the address of the RAM access protect register port (internal register I/O port) to the lower byte of the address, and outputs the fixed value "@TOCRVAL", i.e., 1, to that address. The command size of this command is "3", and the execution cycle is "4".

The total command size of the command group shown in FIG. 172(a) is 2 bytes of the command "LD A, @TOCRVAL" on the second line + 2 bytes of the command "OUT (@PTOCR___), A" on the third line = 4 bytes, and the total execution cycles are 2 cycles on the second line + 3 cycles on the third line = 5 cycles.

On the other hand, the total command size of the command group shown in FIG. 172(b) is the command "OUT (@PTOCR___), @TOCRVAL" on the second line, 3 bytes = 3 bytes, and the total execution cycles are 4 cycles on the second line = 4 cycles.

Therefore, by replacing the command group in FIG. 172(a) with the command group in FIG. 172(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. This replacement shortens the commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 172(a) and 172(b), a group of commands that occupy two lines (lines 2 and 3) in Figure 172(a) can be represented in one line (line 2) in Figure 172(b), making it possible to reduce the number of commands and lighten the design load.

In addition, in the example of FIG. 172(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. Also, in the example of FIG. 172(a), if the A register was already in use, it was necessary to save the value of the A register by stacking, but here, since the A register is not used, stack processing is not required. In this way, resources can be used efficiently.

<LDQ>
Fig. 173 is a flow chart showing the specific processing of the FZ_SPN module. The FZ_SPN module executes the above-mentioned normal pattern variation processing (see Fig. 53). The numerical values of step S in this figure are used only in the explanation of this figure.

The main CPU 300a saves the normal symbol stop symbol number (counter value) in the normal symbol display symbol counter as shown in FIG. 173 (S1). Note that step S1 corresponds to step S820-9 in FIG. 53.

Figure 174 is an explanatory diagram for explaining an example of a command for implementing the FZ_SPN module. The flowchart shown in Figure 173 is implemented, for example, by the program shown in Figure 174.

The index "FZ_SPN:" on the first line of Fig. 174(a) indicates the starting address of the FZ_SPN module. Then, the command "LDQ A, (LOW R_FZ_STP)" on the second line of Fig. 174(a) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_FZ_STP" to the lower byte of the address, and reads the value stored at that address (normal symbol stop symbol number) into the A register.

Then, the command "LDQ (LOW R_FZ_DSP), A" on the second line of Figure 174 (a) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_FZ_DSP" to the lower byte of the address, and stores the value of the A register in that address (the address of the normal symbol display symbol counter).

The commands in FIG. 174(a) can be changed to those in FIG. 174(b). Here, we will omit the explanation of the processes that are essentially the same as those in FIG. 174(a), and only explain the different processes in FIG. 174(b).

The command "LDQ (LOW R_FZ_DSP), (LOW R_FZ_STP)" on the second line of Figure 174 (b) sets the value of the Q register to the most significant byte of the address, the value of the least significant byte of the address "R_FZ_STP" to the least significant byte of the address, and the value stored at that address is stored at that address, with the value of the Q register set to the most significant byte of the address and the value of the least significant byte of the address "R_FZ_DSP" set to the least significant byte of the address.

The total command size of the command group shown in FIG. 174(a) is 2 bytes of the command "LDQ A, (LOW R_FZ_STP)" on the second line + 2 bytes of the command "LDQ (LOW R_FZ_DSP), A" on the third line = 4 bytes, and the total execution cycles are 3 cycles on the second line + 3 cycles on the third line = 6 cycles.

On the other hand, the total command size of the command group shown in FIG. 174(b) is the command "LDQ (LOW R_FZ_DSP), (LOW R_FZ_STP)" on the second line, which is 4 bytes = 4 bytes, and the total execution cycles are 6 cycles on the second line = 6 cycles.

Therefore, as can be seen by comparing Figures 174(a) and 174(b), the command group that occupies two lines (lines 2 and 3) in Figure 174(a) can be represented in one line (line 2) in Figure 174(b) without changing the total command size or total execution cycles, making it possible to reduce the number of commands and lighten the design load.

In addition, in the example of FIG. 174(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. Also, in the example of FIG. 174(a), if the A register was already in use, it was necessary to save the value of the A register by stacking, but here, since the A register is not used, stack processing is not required. In this way, resources can be used efficiently.

Figure 175 is an explanatory diagram for explaining an example of a command for realizing the CPUINIT module. Here, the special game proceeds in either a low probability game state or a high probability game state. The gaming machine 100 is provided with an indicator indicating that the game state is a high probability game state, and when the game state is a high probability game state, the indicator is lit. When the high probability game state is not notified to the player when the power is restored (so-called latency), the indicator can be made invisible. At this time, if the indicator is judged to be lit or not based on the actual game state, the indicator will be lit if the game state at the time of power restoration is a high probability game state. Therefore, a flag indicating latency is prepared from the time of power restoration until the first start of the big role game, and the indicator is judged to be lit or not based on the flag.

The index "CPUINIT:" on the first line of FIG. 175(a) indicates the starting address of the CPUINIT module. The command "LDQ A, (LOW R_KAK_FLG)" on the second line of FIG. 175(a) sets the value of the Q register to the most significant byte of the address, sets the value of the least significant byte of the address "R_KAK_FLG" to the most significant byte of the address, and reads the value stored at that address (the address of the flag indicating whether or not the game is in a high probability game state) (1 if the game is in a high probability game state, 0 if the game is not in a high probability game state) into the A register.

Then, the command "LDQ (LOW R_KAK_HOT), A" on the third line of Figure 175 (a) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_KAK_HOT" to the lower byte of the address, and stores the value of the A register in that address (the address of the flag indicating that it is in hiding).

The commands in FIG. 175(a) can be changed to those in FIG. 175(b). Here, we will omit the explanation of the processes that are essentially the same as those in FIG. 175(a), and only explain the different processes in FIG. 175(b).

The command "LDQ (LOW R_KAK_HOT), (LOW R_KAK_FLG)" on the second line of Figure 175 (b) sets the value of the Q register to the most significant byte of the address, the value of the least significant byte of the address "R_KAK_FLG" to the least significant byte of the address, and the value stored at that address is stored at that address, with the value of the Q register as the most significant byte of the address and the value of the least significant byte of the address "R_KAK_HOT" as the least significant byte of the address.

The total command size of the command group shown in FIG. 175(a) is 2 bytes of the command "LDQ A, (LOW R_KAK_FLG)" on the second line + 2 bytes of the command "LDQ (LOW R_KAK_HOT), A" on the third line = 4 bytes, and the total execution cycles are 3 cycles on the second line + 3 cycles on the third line = 6 cycles.

On the other hand, the total command size of the command group shown in FIG. 175(b) is the command "LDQ (LOW R_KAK_HOT), (LOW R_KAK_FLG)" on the second line, which is 4 bytes = 4 bytes, and the total execution cycles are 6 cycles on the second line = 6 cycles.

As can be seen by comparing Figures 175(a) and 175(b), a group of commands that occupy two lines (lines 2 and 3) in Figure 175(a) can be represented in one line (line 2) in Figure 175(b), making it possible to reduce the number of commands and lighten the design load.

In addition, in the example of FIG. 175(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. Also, in the example of FIG. 175(a), if the A register was already in use, it was necessary to save the value of the A register by stacking, but here, since the A register is not used, stack processing is not required. In this way, resources can be used efficiently.

Figure 176 is an explanatory diagram for explaining an example of a command for implementing the EXE_SET module. The EXE_SET module shown in Figure 176 executes the execution flag setting process shown in step S2400-11 in Figure 91.

The index "EXE_SET:" on the first line of FIG. 176(a) indicates the starting address of the EXE_SET module. The command "LDQ A, (LOW AT_NXT)" on the second line of FIG. 176(a) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "AT_NXT" to the lower byte of the address, and reads the value (the value indicating the presentation state of the next game) stored at that address (the address of the value indicating the presentation state of the next game) into the A register.

Then, the command "LDQ (LOW AT_MOD), A" on the third line of Figure 176 (a) makes the value of the Q register the most significant byte of the address, the value of the least significant byte of the address "AT_MOD" the most significant byte of the address, and stores the value of the A register in that address (the address of the value indicating the presentation status of the game).

The command group in FIG. 176(a) can be changed to that in FIG. 176(b). Here, we will omit the explanation of the processing that is essentially the same as in FIG. 176(a), and only explain the different processing in FIG. 176(b).

The command "LDQ (LOW AT_MOD), (LOW AT_NXT)" on the second line of Figure 176 (b) sets the value of the Q register to the most significant byte of the address, the value of the least significant byte of the address "AT_NXT" to the least significant byte of the address, and the value stored at that address is stored at that address, with the value of the Q register set to the most significant byte of the address and the value of the least significant byte of the address "AT_MOD" set to the least significant byte of the address.

The total command size of the command group shown in FIG. 176(a) is 2 bytes for the command "LDQ A, (LOW AT_NXT)" on the second line + 2 bytes for the command "LDQ (LOW AT_MOD), A" on the third line = 4 bytes, and the total execution cycles are 3 cycles on the second line + 3 cycles on the third line = 6 cycles.

On the other hand, the total command size of the command group shown in FIG. 176(b) is the command "LDQ (LOW AT_MOD), (LOW AT_NXT)" on the second line, which is 4 bytes = 4 bytes, and the total execution cycles are 6 cycles on the second line = 6 cycles.

As can be seen by comparing Figures 176(a) and 176(b), a group of commands that occupy two lines (lines 2 and 3) in Figure 176(a) can be represented in one line (line 2) in Figure 176(b), making it possible to reduce the number of commands and lighten the design load.

In addition, in the example of FIG. 176(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. Also, in the example of FIG. 176(a), if the A register was already in use, it was necessary to save the value of the A register by stacking, but here, since the A register is not used, stack processing is not necessary. In this way, resources can be used efficiently.

<LDIN>
FIG. 177 is a flow chart showing the specific processing of the HPT_GRP module. The HPT_GRP module executes the reach group determination processing of step S612-7 in the special symbol variable number determination processing (see FIG. 39). The numerical values of step S in this figure are used only in the explanation of this figure. In addition, in the explanation of the HPT_GRP module, the first register is the HL register, and the other registers are the BC register or the A register.

In the reach group determination process, the address of a reach group determination random number judgment table that is predetermined according to the reserved type, reserved number, game status, etc. is pre-stored in the HL register.

As shown in FIG. 177, the main CPU 300a loads the comparison value stored in the address (table address) indicated in the HL register into the BC register and adds 2 to the value of the HL register (S1). As will be described in more detail later, the reach group determination random number judgment table stores multiple sets of a 2-byte comparison value and a 1-byte group number in succession in order. Therefore, in this case, by adding 2 to the value of the HL register after loading the comparison value, the HL register becomes the address value where the group number stored next to the loaded comparison value is stored.

Then, the main CPU 300a compares the comparison value loaded into the BC register with the reach group determination random number (random number value) previously loaded into the DE register (S2), and loads the reach group number stored at the address indicated in the HL register (S3).

Then, the main CPU 300a adds 1 to the value (table address) of the HL register (S4). Here, by adding 1 to the value of the HL register after loading the group number, the HL register becomes the address value where the comparison value stored next to the loaded group number is stored.

Then, if the comparison value in step S2 is equal to or less than the reach group determination random number (random value) (YES in S5), the main CPU 300a returns the process to step S1, and if the comparison value is not equal to or less than the reach group determination random number (NO in S5), the main CPU 300a terminates the HPT_GRP module (S6).

Figures 178(a) and (b) are explanatory diagrams for explaining an example of commands for realizing the HPT_GRP module. Figure 178(c) is an explanatory diagram for explaining an example of a reach group determination random number judgment table. The flowchart shown in Figure 177 is realized, for example, by the program shown in Figures 178(a) and (b). First, the reach group determination random number judgment table in Figure 178(c) will be explained, and then the commands for realizing the HPT_GRP module shown in Figures 178(a) and (b) will be explained.

The table starting from the index "D_GRP_SEL_00:" in Figure 178 (c) indicates the top address of one of the reach group determination random number judgment tables. The fixed value "8999" in the second line, the fixed value "9099" in the fourth line, and the fixed value "9299" in the sixth line are each two-byte comparison values, while the fixed value "@D_MOD_SEL_00" in the third line, the fixed value "@D_MOD_SEL_01" in the fifth line, and the fixed value "@D_MOD_SEL_02" in the seventh line are each one-byte group numbers. In the reach group determination random number judgment table, a two-byte comparison value and a one-byte group number corresponding to that comparison value form a set and are stored consecutively in order.

The index "HPT_GRP:" on the first line of Figure 178(a) indicates the starting address of the HPT_GRP module. The command "LDIN BC, (HL)" on the second line of Figure 178(a) reads (loads) a 2-byte value (comparison value) stored at the address indicated by the HL register into the BC register, and adds 2 to the value of the HL register. This command on the second line corresponds to step S1 in Figure 177. Note that the address of a predetermined reach group determination random number judgment table is loaded into the HL register in advance.

Then, the command "CP BC,DE" on the third line of Figure 178(a) compares the value stored in the BC register (comparison value) with the value stored in the DE register (reach group determination random number). If the value stored in the BC register is less than or equal to the value stored in the DE register, the zero flag (if equal) or the carry flag (if less than) will be set to 1. Note that the DE register has previously stored the reach group determination random number. This command on the third line corresponds to step S2 in Figure 177.

After that, the command "LD A, (HL)" on the fourth line of Fig. 178(a) reads a 1-byte value (group number) stored at the address indicated by the HL register into the A register. This command on the fourth line corresponds to step S3 in Fig. 177. Then, the command "INC HL" on the fifth line of Fig. 178(a) adds 1 to the value of the HL register. This command on the fifth line corresponds to step S4 in Fig. 177.

Next, if the zero flag or carry flag is set to 1 by the command "CP BC,DE" on line 3, the command "JLS HPT_GRP" on line 6 of Fig. 178(a) moves to the address indicated by "HPT_GRP", and if the zero flag and carry flag are not set to 1, the command "RET" on line 7 of Fig. 178(a) terminates the HPT_GRP module. These commands on lines 6 and 7 correspond to steps S5 and S6 of Fig. 177. Then, when the HPT_GRP module is terminated, the group number corresponding to the range shown in Fig. 9 is stored in the A register.

The commands in FIG. 178(a) can be changed to those in FIG. 178(b). Here, we will omit the explanation of the processes that are essentially the same as those in FIG. 178(a), and only explain the different processes in FIG. 178(b).

The command "LDIN A, (HL)" on the fourth line of Fig. 178(b) reads a one-byte value (group number) stored at the address indicated by the HL register into the A register, and increments the value of the HL register by one. This command on the fourth line corresponds to steps S3 and S4 in Fig. 177. The command size of this command is "1", and the execution cycle is "2".

The total command size of the command group shown in FIG. 178(a) is 2 bytes of the command "LDIN BC, (HL)" on the second line + 2 bytes of the command "CP BC, DE" on the third line + 1 byte of the command "LD A, (HL)" on the fourth line + 1 byte of the command "INC HL" on the fifth line + 3 bytes of the command "JLS HPT_GRP" on the sixth line + 1 byte of the command "RET" on the seventh line = 10 bytes, and the total execution cycles are 4 cycles on the second line + 2 cycles on the third line + 2 cycles on the fourth line + 1 cycle on the fifth line + 4 (3) cycles on the sixth line + 3 cycles on the seventh line = 16 (15) cycles. The number of cycles in parentheses indicates the execution cycles when there is no movement due to the command "JLS HPT_GRP".

On the other hand, the total command size of the command group shown in FIG. 178(b) is 2 bytes of the command "LDIN BC, (HL)" on line 2 + 2 bytes of the command "CP BC, DE" on line 3 + 1 byte of the command "LDIN A, (HL)" on line 4 + 3 bytes of the command "JLS HPT_GRP" on line 5 + 1 byte of the command "RET" on line 6 = 9 bytes, and the total execution cycles are 4 cycles on line 2 + 2 cycles on line 3 + 2 cycles on line 4 + 4(3) cycles on line 5 + 3 cycles on line 6 = 15(14) cycles. Note that the number of cycles in parentheses indicates the execution cycles if there is no movement due to the command "JLS HPT_GRP".

Therefore, by replacing the command group in FIG. 178(a) with the command group in FIG. 178(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. This replacement shortens the commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 178(a) and 178(b), the command group that occupies two lines (lines 4 and 5) in Figure 178(a) can be represented in one line (line 4) in Figure 178(b), making it possible to reduce the number of commands and lighten the design load.

In addition, in the example of FIG. 178(b), when obtaining a desired 2-byte or 1-byte value from a table in which multiple values of different byte lengths are arranged alternately, it is possible to add 2 and 1 to the value of the HL register using the same command "LDIN," thereby making it possible to reduce the design load.

Figure 179 is an explanatory diagram for explaining the E_ILGER module. The E_ILGER module shown in Figure 179 executes the fraud monitoring process shown in step S3100-19 in Figure 98.

The index "E_ILGER:" on the first line of FIG. 179(a) indicates the starting address of the E_ILGER module. The command "LD HL, _EX_ILTM" on the second line reads the address "EX_ILTM" that stores the unauthorized entry monitoring timer into the HL register.

After that, the command "LD A, (HL)" on the third line of Fig. 179(a) reads a 1-byte value (unauthorized insertion monitoring timer) stored at the address indicated by the HL register into the A register. Then, the command "INC HL" on the fourth line of Fig. 179(a) adds 1 to the value of the HL register. Next, the command "JT Z, A, E_ILGER01" on the fifth line of Fig. 179(a) skips subsequent processing and moves to the index "E_ILGER01:" on the sixth line, and if the value of the A register is not 0, moves to the next command after that command.

The commands in FIG. 179(a) can be changed to those in FIG. 179(b). Here, we will omit the explanation of the processes that are essentially the same as those in FIG. 179(a), and only explain the different processes in FIG. 179(b).

The command "LDIN A, (HL)" on the third line of Figure 179 (b) reads a 1-byte value (unauthorized input monitoring timer) stored at the address indicated by the HL register into the A register, and adds 1 to the value of the HL register. The command size of this command is "1", and the execution cycle is "2".

The total command size of the command group shown in FIG. 179(a) is 3 bytes of the command "LD HL,_EX_ILTM" on line 2 + 1 byte of the command "LD A,(HL)" on line 3 + 1 byte of the command "INC HL" on line 4 + 2 bytes of the command "JT Z,A,E_ILGER01" on line 5 = 7 bytes, and the total execution cycles are 3 cycles on line 2 + 2 cycles on line 3 + 1 cycle on line 4 + 3(2) cycles on line 5 = 9(8) cycles. Note that the number of cycles in parentheses indicates the execution cycles if there is no movement due to the command "JT Z,A,E_ILGER01".

On the other hand, the total command size of the command group shown in FIG. 179(b) is 3 bytes of the command "LD HL,_EX_ILTM" on the second line + 1 byte of the command "LDIN A,(HL)" on the third line + 2 bytes of the command "JT Z,A,E_ILGER01" on the fourth line = 6 bytes, and the total execution cycles are 3 cycles on the second line + 2 cycles on the third line + 3(2) cycles on the fourth line = 8(7) cycles. Note that the number of cycles in parentheses indicates the execution cycles if no movement was made by the command "JT Z,A,E_ILGER01".

Therefore, by replacing the command group in FIG. 179(a) with the command group in FIG. 179(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. This replacement shortens the commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 179(a) and 179(b), the command group that occupies two lines (lines 3 and 4) in Figure 179(a) can be represented in one line (line 3) in Figure 179(b), making it possible to reduce the number of commands and lighten the design load.

Figure 180 is an explanatory diagram for explaining the E_LEVOT module. The E_LEVOT module shown in Figure 180 is a subroutine that is called in the execution flag setting process shown in step S2400-11 in Figure 91, and executes the test signal transmission process when the lever is pressed.

The index "E_LEVOT:" on the first line of Figure 180(a) indicates the starting address of the E_LEVOT module. The command "LD HL, T_EXM_STP" on the second line reads the address "T_EXM_STP" that stores the test stop information transmission table into the HL register. In this test stop information transmission table, six test signal values, each 1 byte long, are stored consecutively as one set, and multiple sets are stored consecutively.

Then, the command "ADDWB HL,A" on the third line of Figure 180(a) adds the value of the A register to the value of the HL register, updating the value of the HL register. Note that the A register stores a value obtained by multiplying the instruction information type by 6. Therefore, in this case, the value of the HL register indicates the first address of a set corresponding to the instruction information type in the test stop information transmission table.

Then, the command "LD B,6" on the fourth line reads the fixed value "6" into the B register. The index "E_LEVOT01:" on the fifth line of Figure 180(a) indicates the address of the index "E_LEVOT01".

The command "LD A, (HL)" on the sixth line of Fig. 180(a) reads a one-byte value (the value of the test signal) stored at the address indicated by the HL register into the A register. Then, the command "OUT (@S2DT___), A" on the seventh line of Fig. 180(a) sets the value of the U register to the upper byte of the address, sets the fixed value "@S2DT___" indicating the lower byte of the address of the RAM access protect register port (internal register I/O port) to the lower byte, and outputs the value of the A register to that address.

The command "INC HL" on line 8 of Fig. 180(a) adds 1 to the value of the HL register. Next, the command "DJNZ E_LEVOT01" on line 9 of Fig. 180(a) decrements the value of the B register (subtracts "1"), and if the result of the decrement is not 0, it moves to address "E_LEVOT01", and if the result of the decrement is 0, it moves to the next command after that command.

The commands in FIG. 180(a) can be changed to those in FIG. 180(b). Here, we will omit the explanation of the processes that are essentially the same as those in FIG. 180(a), and only explain the different processes in FIG. 180(b).

The command "LDIN A, (HL)" on line 6 of Figure 180(b) reads a 1-byte value (the value of the test signal) stored at the address indicated by the HL register into the A register, and adds 1 to the value of the HL register. The command size of this command is "1", and the execution cycle is "2".

Here, the total command size of the command group shown in FIG. 180(a) is 3 bytes of the command "LD HL,T_EXM_STP" on line 2 + 1 byte of the command "ADDWB HL,A" on line 3 + 2 bytes of the command "LD B,6" on line 4 + 1 byte of the command "LD A,(HL)" on line 6 + 2 bytes of the command "OUT (@S2DT＿＿),A" on line 7 + 1 byte of the command "INC HL" on line 8 + 2 bytes of the command "DJNZ E_LEVOT01" on line 9 = 12 bytes, and the total execution cycles are 3 cycles on line 2 + 1 cycle on line 3 + 2 cycles on line 4 + 2 cycles on line 6 + 3 cycles on line 7 + 1 cycle on line 8 + 3(2) cycles on line 9 = 15(14) cycles. Note that the number of cycles in parentheses indicates the execution cycles if no movement is made using the command "DJNZ E_LEVOT01".

On the other hand, the total command size of the command group shown in FIG. 180(b) is 3 bytes of the command "LD HL,T_EXM_STP" on line 2 + 1 byte of the command "ADDWB HL,A" on line 3 + 2 bytes of the command "LD B,6" on line 4 + 1 byte of the command "LDIN A,(HL)" on line 6 + 2 bytes of the command "OUT (@S2DT__),A" on line 7 + 2 bytes of the command "DJNZ E_LEVOT01" on line 5 = 11 bytes, and the total execution cycles are 3 cycles on line 2 + 1 cycle on line 3 + 2 cycles on line 4 + 2 cycles on line 6 + 3 cycles on line 7 + 3(2) cycles on line 9 = 14(13) cycles. Note that the number of cycles in parentheses indicates the execution cycles when there is no movement due to the command "DJNZ E_LEVOT01".

Therefore, by replacing the commands in FIG. 180(a) with those in FIG. 180(b), the total command size is reduced by 1 byte, and the total execution cycles are also reduced by at least 1 cycle. In particular, in the example of FIG. 180(a), if the value of the B register in the command "DJNZ E_LEVOT01" is 2 or greater, the difference in the total execution cycles increases by multiplying that value by 1 cycle, so the reduction in the total execution cycles in FIG. 180(b) also increases. This replacement shortens the commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 180(a) and 180(b), the command group that occupies two lines (lines 6 and 8) in Figure 180(a) can be represented by one line (line 6) in Figure 180(b), making it possible to reduce the number of commands and lighten the design load.

<LDQP>
181 is a flow chart showing the specific processing of the SBC_OUT module. The SBC_OUT module executes the subcommand transmission processing of step S100-65 (see FIG. 23). The numerical values of step S in this figure are used only in the explanation of this figure.

The subcommands are set in the transmission buffer in multiple processes in the interrupt process and are transmitted in the subcommand transmission process. The transmission buffer is, for example, a 96-byte ring buffer, and is a FIFO in which the subcommands are set in order in multiple processes and are transmitted to the sub-control board 330 in the subcommand transmission process, starting with the subcommand that was set first.

As shown in FIG. 181, the main CPU 300a reads the value of the subcommand write pointer into the A register (S1) and compares the value of the subcommand write pointer with the value of the subcommand read pointer (S2). Here, if the value of the subcommand write pointer and the value of the subcommand read pointer are the same, i.e., if there are no unsent subcommands, the zero flag is set to 1; if they are different, i.e., if there are unsent subcommands, the zero flag is not set to 1.

If the zero flag is 1 (YES in S3), the main CPU 300a terminates the SBC_OUT module; if the zero flag is not 1 (NO in S3), the main CPU 300a reads the subcommand pointer upper limit value and the lower byte of the address of the subcommand read pointer into the DE register (S4), and uses the count-up process, which is a general-purpose module, to add 1 to the value of the subcommand read pointer if it is less than the subcommand pointer upper limit value, or clear it to zero if it is equal to or greater than the subcommand pointer upper limit value (S5).

Then, the main CPU 300a reads the address of the subcommand buffer (transmission buffer) into the HL register (S6), executes the above-mentioned word data selection process (S7), outputs the preceding command to the SCU1 data register for transmitting the subcommand (S8), reads the subsequent command into the A register (S9), outputs the subsequent command to the SCU1 data register (S10), and terminates the SBC_OUT module (S11).

Figure 182 is an explanatory diagram illustrating an example of a command for implementing the SBC_OUT module.

The index "SBC_OUT:" on the first line of FIG. 182(a) indicates the starting address of the SBC_OUT module. The command "LDQ A, (LOW R_SBC_WPT)" on the second line of FIG. 182(a) sets the value of the Q register to the most significant byte of the address, sets the value of the least significant byte of the address "R_SBC_WPT" to the least significant byte of the address, and reads the value stored at that address (the value of the sub-command write pointer) into the A register. This command on the second line corresponds to step S1 in FIG. 181.

The command "CPQ A, (LOW R_SBC_RPT)" on the third line of Figure 182 (a) sets the value of the Q register to the most significant byte of the address, sets the value of the least significant byte of the address "R_SBC_RPT" to the most significant byte of the address, and compares the value stored at that address (the value of the sub-command read pointer) with the value of the A register (the value of the sub-command write pointer). If the value stored at that address matches the value of the A register, the zero flag is set to 1. This command on the third line corresponds to step S2 in Figure 181.

The command "RET Z" on the fourth line of FIG. 182(a) terminates the SBC_OUT module if the zero flag is set to 1. This command on the fourth line corresponds to step S3 in FIG. 181.

The command "LD DE, @LMT_CMD_BFP * 256 + LOW R_SBC_RPT" on the fifth line of Figure 182 (a) reads the fixed value "@LMT_CMD_BFP" indicating the upper limit value of the subcommand pointer into the D register, and reads "R_SBC_RPT" indicating the lower byte of the address of the subcommand read pointer into the E register. This command on the fifth line corresponds to step S4 in Figure 181.

The command "RST COUNTUP" on line 6 of FIG. 182(a) reads and executes the COUNTUP module, which is a general-purpose module. As a result, the value of the subcommand read pointer is incremented by 1 if it is less than the subcommand pointer upper limit value, and is cleared to zero if it is equal to or greater than the subcommand pointer upper limit value. This command on line 6 corresponds to step S5 in FIG. 181.

The command "LD HL, R_SBC_SBF" on line 7 of Figure 182 (a) reads "R_SBC_SBF", which indicates the address of the sub-command buffer (transmission buffer), into the HL register. This command on line 7 corresponds to step S6 of Figure 181. Here, "R_SBC_SBF" is 2-byte data. If the most significant byte of the sub-command buffer address is "F0H", it can be read with the command "LDQ", but since the most significant byte of the sub-command buffer may be "F1H", the 2-byte data is read here without using the command "LDQ".

The command "RST WORDSEL" on line 8 of Figure 182(a) reads the WORDSEL module, which is a general-purpose module, adds the value of the A register twice to the HL register, and reads the value of the lower byte of the address indicated in the HL register (the value of the L register, i.e., the preceding command) into the A register. This command on line 8 corresponds to step S7 in Figure 181.

The command "OUT (@S1DT___), A" on line 9 of FIG. 182(a) outputs the value of the A register (preceding command) to the address indicated by the fixed value "@S1DT___". This command on line 9 corresponds to step S8 in FIG. 181.

The command "LD A,H" on line 10 of FIG. 182(a) reads the value of the H register (the subsequent command) into the A register. This command on line 10 corresponds to S9 in FIG. 181.

The command "OUT (@S1DT___), A" on line 11 of FIG. 182(a) outputs the value of the A register (subsequent command) to the address indicated by the fixed value "@S1DT___", and the SBC_OUT module ends. This command on line 11 corresponds to step S10 in FIG. 181, and the command on line 12 corresponds to step S11 in FIG. 181.

The commands in FIG. 182(a) can be changed to those in FIG. 182(b). Here, we will explain the case where the most significant byte of the subcommand buffer (transmission buffer) is "F1H". We will omit the explanation of the processing that is essentially the same as in FIG. 182(a) and only explain the different processing in FIG. 182(b).

The command "LDQP HL, LOW R_SBC_SBF" on line 7 of Figure 182(b) causes a value (address of the sub-command buffer) to be read into the HL register, with the value of the Q register increased by 1 (i.e., "F1H") at the upper level and "R_SBC_SBF" at the lower level. This command on line 7 corresponds to step S6 in Figure 181. The command size of this command is "3", and the execution cycle is "7(5)".

Here, the total command size of the command group shown in FIG. 182(a) is: 2 bytes of the command "LDQ A, (LOW R_SBC_WPT)" on the second line + 3 bytes of the command "CPQ A, (LOW R_SBC_RPT)" on the third line + 1 byte of the command "RET Z" on the fourth line + 2 bytes of the command "LD DE, @LMT_CMD_BFP * 256 + LOW R_SBC_RPT" on the fifth line + 1 byte of the command "RST COUNTUP" on the sixth line + 3 bytes of the command "LD HL, R_SBC_SBF" on the seventh line + 1 byte of the command "RST WORDSEL" on the eighth line + 2 bytes of the command "OUT (@S1DT___), A" on the ninth line + 1 byte of the command "LD A, H" on the tenth line + 1 byte of the command "OUT 2 bytes of "(@S1DT__),A" + 1 byte of the command "RET" on line 12 = 19 bytes, and the total execution cycles are 2 cycles on line 2 + 4 cycles on line 3 + 3(1) cycles on line 4 + 2 cycles on line 5 + 4 cycles on line 6 + 3 cycles on line 7 + 4 cycles on line 8 + 3 cycles on line 9 + 1 cycle on line 10 + 3 cycles on line 11 + 3 cycles on line 12 = 32 (30) cycles. Note that the number of cycles in parentheses indicates the execution cycles if the routine above is not moved to by the command "RET Z".

On the other hand, the total command size of the command group shown in FIG. 182(b) is: 2 bytes of the command "LDQ A, (LOW R_SBC_WPT)" on the second line + 3 bytes of the command "CPQ A, (LOW R_SBC_RPT)" on the third line + 1 byte of the command "RET Z" on the fourth line + 2 bytes of the command "LD DE, @LMT_CMD_BFP * 256 + LOW R_SBC_RPT" on the fifth line + 1 byte of the command "RST COUNTUP" on the sixth line + 3 bytes of the command "LDQP HL, LOW R_SBC_SBF" on the seventh line + 1 byte of the command "RST WORDSEL" on the eighth line + 2 bytes of the command "OUT (@S1DT___), A" on the ninth line + 1 byte of the command "LD A, H" on the tenth line + 1 byte of the command "OUT 2 bytes of "(@S1DT__),A" + 1 byte of the command "RET" on line 12 = 19 bytes, and the total execution cycles are 2 cycles on line 2 + 4 cycles on line 3 + 3(1) cycles on line 4 + 2 cycles on line 5 + 4 cycles on line 6 + 5 cycles on line 7 + 4 cycles on line 8 + 3 cycles on line 9 + 1 cycle on line 10 + 3 cycles on line 11 + 3 cycles on line 12 = 34 (32) cycles. Note that the number of cycles in parentheses indicates the execution cycles if the routine above is not moved to by the command "RET Z".

Therefore, by replacing the command group in FIG. 182(a) with the command group in FIG. 182(b), when the Q register is set to "F0" and an address after F100H is accessed (when the upper byte is "F1H"), it is possible to reduce the design load. In the special symbol memory area shift process shown in step S610-9 of FIG. 37, when the special game special symbol determination flag is read, the upper byte of the address where the special game special symbol determination flag is stored may be set to "F1H" and the command "LDQP" may be used. Furthermore, in the external information management process shown in step S400-29 of FIG. 26, when the composite bit data is saved in the output port 2 buffer, the upper byte of the output port 2 buffer may be set to "F1H" and the command "LDQP" may be used. Furthermore, in the power-off save process of FIG. 25, when saving the backup validity judgment value to the backup validity judgment flag, the upper byte of the address where the backup validity judgment flag is stored may be set to "F1H" and the command "LDQP" may be used.

<RCPQ>
Fig. 183 is an explanatory diagram for explaining an example of another command for realizing the SBC_OUT module. Since Fig. 183(a) is the same as Fig. 182(a), the explanation will be omitted. Regarding Fig. 183(b), the explanation of the process substantially the same as Fig. 183(a) will be omitted, and only the different process of Fig. 183(b) will be explained.

The command "RCPQ Z,A,(LOW R_SBC_RPT)" on the third line of Fig. 183(b) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_SBC_RPT" to the lower byte of the address, compares the value stored at that address (the value of the subcommand read pointer) with the value of the A register (the value of the subcommand write pointer), and if the zero flag is set to 1, terminates the SBC_OUT module so that the command "RET" is executed. This command on the third line corresponds to steps S2 to S4 in Fig. 181. The command size of this command is "3", and the execution cycle is "7(5)". The number of cycles in parentheses indicates the execution cycle when the command does not move to the next higher routine.

Here, the total command size of the command group shown in FIG. 183(b) is: 2 bytes of the command "LDQ A, (LOW R_SBC_WPT)" on the second line + 3 bytes of the command "RCPQ Z,A, (LOW R_SBC_RPT)" on the third line + 2 bytes of the command "LD DE,@LMT_CMD_BFP*256+LOW R_SBC_RPT" on the fourth line + 1 byte of the command "RST COUNTUP" on the fifth line + 3 bytes of the command "LD HL,R_SBC_SBF" on the sixth line + 1 byte of the command "RST WORDSEL" on the seventh line + 2 bytes of the command "OUT (@S1DT___),A" on the eighth line + 1 byte of the command "LD A,H" on the ninth line + 1 byte of the command "OUT 2 bytes of "(@S1DT___),A" + 1 byte of the command "RET" on line 11 = 18 bytes, and the total execution cycles are 2 cycles on line 2 + 7 (5) cycles on line 3 + 2 cycles on line 4 + 4 cycles on line 5 + 3 cycles on line 6 + 4 cycles on line 7 + 3 cycles on line 8 + 1 cycle on line 9 + 3 cycles on line 10 + 3 cycles on line 11 = 32 (30) cycles. Note that the number of cycles in parentheses indicates the execution cycles when the routine above is not moved by the command "RCPQ Z,A,(LOW R_SBC_RPT)".

Therefore, by replacing the command group in FIG. 183(a) with the command group in FIG. 183(b), the total command size is reduced by 1 byte. This replacement shortens the commands and makes it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 183(a) and 183(b), the command group that occupies two lines (lines 3 and 4) in Figure 183(a) can be represented in one line (line 3) in Figure 183(b), making it possible to reduce the number of commands and lighten the design load.

Figure 184 is an explanatory diagram for explaining an example of a command for realizing the FZ_OPN module. The FZ_OPN module shown in Figure 184 executes the normal electric role winning opening control process (see Figure 57).

In the normal electric device winning opening control process, in step S850-5, it is determined whether the counter value of the normal electric device winning ball counter has reached a specified number, i.e., whether the first variable start opening 120B has received the same number of game balls as the maximum number of winning balls during one opening/closing control. If it is determined that the specified number has not been reached, the normal electric device winning opening control process is terminated, and if it is determined that the specified number has been reached, the process proceeds to step S850-7.

As the normal electric role winning opening control process, the index "FZ_OPN:" on the first line of FIG. 184(a) indicates the starting address of the FZ_OPN module. Then, in step S850-5, the command "LDQ A, (LOW R_FDN_CNT)" on the second line sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "R_FDN_CNT" as the lower byte of the address, and reads the value stored at that address (the counter value of the normal electric role winning ball counter) into the A register. The command "CP A, @FDN_CNT" on the third line compares the value of the A register with the fixed value "@FDN_CNT" indicating the specified number, which is 8 in this case. In other words, if the value of the A register is less than 8, the carry flag is set to 1. Then, if the carry flag is 1, the FZ_OPN module is terminated by "RET C" on the fourth line. In other words, if the counter value of the normal electric device winning ball counter is less than 8, the FZ_OPN module is terminated. If the carry flag is not 1, the following process is executed.

The command group in FIG. 184(a) can be changed to that in FIG. 184(b). Here, we will omit the explanation of the processing that is essentially the same as in FIG. 184(a), and only explain the different processing in FIG. 184(b).

The command "RCPQ C, (LOW R_FDN_CNT), @FDN_CNT" on the second line of FIG. 184(b) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_FDN_CNT" to the lower byte of the address, and compares the value stored at that address (the counter value of the winning ball counter for ordinary electric gimmicks) with the fixed value "@FDN_CNT" indicating the specified number, here 8, and if the carry flag is 1, ends the FZ_OPN module so that the command "RET" is executed. The command size of this command is "4", and the execution cycle is "8(6)". The number of cycles in parentheses indicates the execution cycle when the command does not move to the next higher routine.

The total command size of the command group shown in FIG. 184(a) is 2 bytes for the command "LDQ A, (LOW R_FDN_CNT)" on line 2 + 3 bytes for the command "CP A, @FDN_CNT" on line 3 + 1 byte for the command "RET C" on line 4 = 6 bytes, and the total execution cycles are 2 cycles on line 2 + 4 cycles on line 3 + 3(1) cycles on line 4 = 9(7) cycles. Note that the number of cycles in parentheses indicates the execution cycles when the command "RET C" does not move to the routine above.

On the other hand, the total command size of the command group shown in FIG. 184(b) is the command on line 2, "RCPQ C, (LOW R_FDN_CNT), @FDN_CNT" 4 bytes = 4 bytes, and the total execution cycles are line 2, 8(6) cycles = 8(6) cycles. Note that the number of cycles in parentheses indicates the execution cycles when the command "RCPQ C, (LOW R_FDN_CNT), @FDN_CNT" does not move to the routine above.

Therefore, by replacing the command group in FIG. 184(a) with the command group in FIG. 184(b), the total command size is reduced by 2 bytes, and the total execution cycle is also reduced by at least 1 cycle. This replacement shortens the commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 184(a) and 184(b), the command group that occupies three lines (lines 2 to 4) in Figure 184(a) can be represented in one line (line 2) in Figure 184(b), making it possible to reduce the number of commands and lighten the design load.

In addition, in the example of FIG. 184(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. Also, in the example of FIG. 184(a), if the A register was already in use, it was necessary to save the value of the A register by stacking, but here, since the A register is not used, stack processing is not required. In this way, it becomes possible to make effective use of resources.

Figure 185 is an explanatory diagram for explaining an example of a command for realizing the TD_OPN module. The TD_OPN module shown in Figure 185 executes the large prize opening control process (see Figure 47).

In the special prize opening control process, in step S720-5, it is determined whether the counter value of the special prize opening winning ball counter has reached a specified number, i.e., whether the number of game balls equal to the maximum number of winning balls in one round has entered the special prize opening. If it is determined that the specified number has not been reached, the special prize opening control process is terminated, and if it is determined that the specified number has been reached, the process proceeds to step S720-7.

In this large prize opening control process, the indicator "TD_OPN:" on the first line of FIG. 185(a) indicates the starting address of the TD_OPN module. Then, in step S720-5, the command "LDQ A, (LOW R_TDN_FLG)" on the second line sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "R_TDN_FLG" as the lower byte of the address, and reads the value stored at that address (special electric device designation flag) into the A register. The special electric device designation flag indicates which large prize opening is the target of the large prize opening control process.

The command on the third line, "LD HL, D_TDC_MAX-1", reads the value obtained by subtracting 1 from the address of the data table of the number of prizes specified for the large prize slot (the table showing the number specified for the special electric device operation RAM set table in Figure 14) into the HL register.

The command "RST BYTESEL" on the fourth line of Figure 185(a) calls the BYTESEL module, which is a general-purpose module, adds the value of the A register to the HL register, and reads the value (prescribed number) stored at the address indicated in the HL register into the A register.

The command "CPQ A, (LOW R_TDN_CNT)" on the fifth line of FIG. 185(a) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_TDN_CNT" to the lower byte of the address, and compares the value stored at that address (the counter value of the large prize opening winning ball counter) with the value of the A register, here 10. In other words, if the value stored at the same address is less than 10, the carry flag is not set and becomes 0. Then, the "RET NC" on the sixth line ends the TD_OPN module if the carry flag is 0. In other words, if the counter value of the large prize opening winning ball counter is less than 10, the TD_OPN module ends. Note that if the carry flag is 1, the subsequent processing is executed.

The command group in FIG. 185(a) can be changed to that in FIG. 185(b). Here, we will omit the explanation of the processing that is essentially the same as in FIG. 185(a), and only explain the different processing in FIG. 185(b).

The command "RCPQ NC,A, (LOW R_TDN_CNT)" on the fifth line of FIG. 185(b) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_TDN_CNT" to the lower byte of the address, and compares the value stored at that address (the counter value of the large prize slot winning ball counter) with the value of the A register (default value), here 10. If the carry flag is 0, the TD_OPN module is terminated to execute the command "RET". The command size of this command is "3", and the execution cycle is "7(5)". The number of cycles in parentheses indicates the execution cycle when the command does not move to the next higher routine.

The total command size of the command group shown in FIG. 185(a) is 2 bytes of the command "LDQ A, (LOW R_TDN_FLG)" on the second line + 3 bytes of the command "LD HL, D_TDC_MAX-1" on the third line + 1 byte of the command "RST BYTESEL" on the fourth line + 3 bytes of the command "CPQ A, (LOW R_TDN_CNT)" on the fifth line + 1 byte of the command "RET NC" on the fourth line = 10 bytes, and the total execution cycles are 2 cycles on the second line + 3 cycles on the third line + 3 cycles on the fourth line + 4 cycles on the fifth line + 3(1) cycles on the fourth line = 15 (13) cycles. The number of cycles in parentheses indicates the execution cycles when the command "RET NC" does not move to the next higher routine.

On the other hand, the total command size of the command group shown in FIG. 185(b) is 2 bytes of the command "LDQ A, (LOW R_TDN_FLG)" on the second line + 3 bytes of the command "LD HL, D_TDC_MAX-1" on the third line + 1 byte of the command "RST BYTESEL" on the fourth line + 3 bytes of the command "RCPQ NC, A, (LOW R_TDN_CNT)" on the fifth line = 9 bytes, and the total execution cycles are 2 cycles on the second line + 3 cycles on the third line + 3 cycles on the fourth line + 7 (5) cycles on the fifth line = 15 (13) cycles. Note that the number of cycles in parentheses indicates the execution cycles when the command "RCPQ NC, A, (LOW R_TDN_CNT)" does not move to the routine above.

Therefore, by replacing the command group in FIG. 185(a) with the command group in FIG. 185(b), the total command size is reduced by 1 byte. This replacement shortens the commands and makes it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 185(a) and 185(b), the command group that occupies two lines (lines 5 and 6) in Figure 185(a) can be represented in one line (line 5) in Figure 185(b), making it possible to reduce the number of commands and lighten the design load.

<JCPQ>
Fig. 186 is an explanatory diagram for explaining an example of a command for realizing the HSY_PRC module. The HSY_PRC module shown in Fig. 186 executes the launch position designation management process (see step S400-27 in Fig. 26).

In this launch position designation management process, the index "HSY_PRC:" on the first line of Figure 186 (a) indicates the starting address of the HSY_PRC module. The command "XOR A,A" on the second line calculates the exclusive OR of the value of the A register and the value of the A register, and initializes the A register.

Then, the command on the third line, "LDQ HL, LOW R_TDN_FLG," reads the value of the Q register into the H register, and reads the value of the lowest byte of the address "R_TDN_FLG" into the L register.

The command on the fourth line, "JCP NZ, (HL), @TDK_AT2, HSY_PRC_10," compares the value indicated in the HL register (special electric device designation flag) with the fixed value "@TDK_AT2" indicating the second large winning slot, and if the zero flag is not set to 1, it moves to the address indicated by the index "HSY_PRC_10" on the seventh line (branching the process).

On the other hand, if the zero flag is set to 1, the command on line 5, "LDQ HL,LOW R_ZUG_CHK_FIX", reads the value of the Q register into the H register and reads the value of the lowest byte of the address "R_ZUG_CHK_FIX" into the L register.

The command on line 6, "JCP NZ, (HL), @ZUG_SML1, HSY_PRC_20", compares the value indicated in the HL register (special symbol determination flag) with the fixed value "@ZUG_SML1" indicating the small win symbol 1 designation data, here 07H, and if the zero flag is not set to 1, it moves to the address indicated by the index "HSY_PRC_20" on line 8 (branching the process).

The command group in FIG. 186(a) can be changed to that in FIG. 186(b). Here, we will omit the explanation of the processing that is essentially the same as in FIG. 186(a), and only explain the different processing in FIG. 186(b).

The command "JCPQ NZ, (LOW R_TDN_FLG), @TDK_AT2, HSY_PRC_10" on the third line of Figure 186 (b) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_TDN_FLG" to the lower byte of the address, and compares the value indicated at that address (special electric device designation flag) with the fixed value "@TDK_AT2" indicating the second large winning slot. If the zero flag is not set to 1, it moves to the address indicated by the index "HSY_PRC_10" on the fifth line (branching the process).

The command "JCPQ NZ, (LOW R_ZUF_CHK_FIX, @ZUG_SML1, HSY_PRC_20" on the fourth line of Figure 186 (b) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_ZUF_CHK_FIX" to the lower byte of the address, and compares the value indicated at that address (special symbol determination flag) with the fixed value "@TDK_AT2" indicating the second large winning slot, and with the fixed value "@ZUG_SML1" indicating the small winning symbol 1 designation data, here 07H. If the zero flag is not set to 1, it moves to the address indicated by the index "HSY_PRC_20" on the sixth line (branching the process).

Here, the total command size of the command group shown in FIG. 186(a) is 1 byte of the command "XOR A,A" on line 2 + 2 bytes of the command "LDQ HL,LOW R_TDN_FLG" on line 3 + 4 bytes of the command "JCP NZ,(HL),@TDK_AT2,HSY_PRC_10" on line 4 + 2 bytes of the command "LDQ HL,LOW R_ZUG_CHK_FIX" on line 5 + 4 bytes of the command "JCP NZ,(HL),@ZUG_SML1,HSY_PRC_20" on line 6 = 13 bytes, and the total execution cycles are 1 cycle on line 2 + 2 cycles on line 3 + 6(5) cycles on line 4 + 2 cycles on line 5 + 26(5) cycles on line 6 = 17(15) cycles. Note that the number of cycles in parentheses indicates the execution cycles if no movement is made using the command "JCP NZ,...".

On the other hand, the total command size of the command group shown in FIG. 186(b) is 1 byte of the command "XOR A,A" on the second line + 4 bytes of the command "JCPQ NZ, (LOW R_TDN_FLG), @TDK_AT2, HSY_PRC_10" on the third line + 4 bytes of the command "JCPQ NZ, (LOW R_ZUG_CHK_FIX, @ZUG_SML1, HSY_PRC_20" on the fourth line = 9 bytes, and the total execution cycles are 1 cycle on the second line + 6(5) cycles on the third line + 6(5) cycles on the fourth line = 13(11) cycles. Note that the number of cycles in parentheses indicates the execution cycles if no movement was made by the command "JCP NZ, ...".

Therefore, by replacing the command group in FIG. 186(a) with the command group in FIG. 186(b), the total command size is reduced by 4 bytes, and the total execution cycles are also reduced by at least 4 cycles. This replacement shortens the commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 186(a) and 186(b), the command group that occupies four lines (lines 3 to 6) in Figure 186(a) can be represented in two lines (lines 3 to 4) in Figure 186(b), making it possible to reduce the number of commands and lighten the design load.

In addition, in the example of FIG. 186(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. Also, in the example of FIG. 186(a), if the A register was already in use, it was necessary to save the value of the A register by stacking, but here, since the A register is not used, stack processing is not required. In this way, resources can be used efficiently.

Figure 187 is an explanatory diagram for explaining an example of a command for implementing the FDN_CHK module. The FDN_CHK module shown in Figure 187 executes the confirmation process when a normal electric device wins (see step S500-9 in Figure 28).

For the confirmation process when a normal electric device wins, the indicator "FDN_CHK:" on the first line of Figure 187 (a) indicates the starting address of the FDN_CHK module.

Then, the command on the second line, "LDQ HL, (LOW R_FDN_EFF)," sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_FDN_EFF" to the lower byte of the address, and reads the value of that address (the value of the normal electric feature closure valid timer) into the HL register.

The command "RET NTZ" on the third line terminates the FDN_CHK module if the zero flag is not 1. "NTZ" is used here because the command "LDQ HL, (LOW R_FDN_EFF)" changes the second zero flag but does not change the first zero flag.

The command on the fourth line, "LDQ A, (LOW R_FUT_PHS)," sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_FUT_PHS" to the lower byte of the address, and reads the value of that address (normal game management phase) into the A register.

The command on line 5, "JCP NZ,A,@FD_OPN,FDN_CHK_10", compares the value indicated in the A register (normal game management phase) with the fixed value "@FD_OPN", which indicates the normal electric device winning opening control process, in this case 04H, and if the zero flag is not set to 1, it moves to the address indicated by the index "FDN_CHK_10" on line 8 (branching the process).

On the other hand, if the zero flag is set to 1, the command "INCQ (LOW R_FDN_CNT)" on line 6 sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_FDN_CNT" to the lower byte of the address, adds 1 to the value stored at that address (the counter value of the normal electric device winning ball counter), stores the added value at the same address, and the command "RET" on line 7 ends the FDN_CHK module.

The commands in FIG. 187(a) can be changed to those in FIG. 187(b). Here, we will omit the explanation of the processes that are essentially the same as those in FIG. 187(a), and only explain the different processes in FIG. 187(b).

The command "JCPQ NZ, (LOW R_FUT_PHS), @FD_OPN, FDN_CHK_10" on the fourth line of Figure 187 (b) sets the value of the Q register as the upper byte of the address, sets the value of the lowest byte of the address "R_FUT_PHS" as the lower byte of the address, and compares the value of that address (normal game management phase) with the fixed value "@FD_OPN" indicating the normal electric device winning opening control process, 04H in this case. If the zero flag is not set to 1, it moves to the address indicated by the index "FDN_CHK_10" on the seventh line (branching the process).

Here, the total command size of the command group shown in FIG. 187(a) is 2 bytes of the command "LDQ HL, (LOW R_FDN_EFF)" on line 2 + 1 byte of the command "RET NTZ" on line 3 + 2 bytes of the command "LDQ A, (LOW R_FUT_PHS)" on line 4 + 3 bytes of the command "JCP NZ,A,@FD_OPN,FDN_CHK_10" on line 5 + 2 bytes of the command "INCQ (LOW R_FDN_CNT)" on line 6 + 1 byte of the command "RET" on line 7 = 11 bytes, and the total execution cycles are 4 cycles on line 2 + 3(1) cycles on line 3 + 2 cycles on line 4 + 4(3) cycles on line 5 + 5 cycles on line 6 + 3 cycles on line 7 = 21 (18) cycles. Note that the number of cycles in parentheses indicates the execution cycles if no movement is made using the commands "RET NTZ", "JCP NZ, ...".

On the other hand, the total command size of the command group shown in FIG. 187(b) is 2 bytes of the command "LDQ HL, (LOW R_FDN_EFF)" on the second line + 1 byte of the command "RET NTZ" on the third line + 4 bytes of the command "JCPQ NZ, (LOW R_FUT_PHS), @FD_OPN, FDN_CHK_10" on the fourth line + 2 bytes of the command "INCQ (LOW R_FDN_CNT)" on the fifth line + 1 byte of the command "RET" on the sixth line = 10 bytes, and the total execution cycles are 4 cycles on the second line + 3(1) cycles on the third line + 6(5) cycles on the fourth line + 5 cycles on the fifth line + 3 cycles on the sixth line = 19 (16) cycles. The number of cycles in parentheses indicates the execution cycles when no movement is made by the commands "RET NZ", "JCPQ NTZ, ...".

Therefore, by replacing the command group in FIG. 187(a) with the command group in FIG. 187(b), the total command size is reduced by 1 byte, and the total execution cycles are also reduced by at least 2 cycles. This replacement shortens the commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 187(a) and 187(b), the command group that occupies two lines (lines 4 and 5) in Figure 187(a) can be represented in one line (line 4) in Figure 187(b), making it possible to reduce the number of commands and lighten the design load.

In addition, in the example of FIG. 187(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. Also, in the example of FIG. 187(a), if the A register was already in use, it was necessary to save the value of the A register by stacking, but here, since the A register is not used, stack processing is not required. In this way, resources can be used efficiently.

Figure 188 is an explanatory diagram for explaining an example of a command for realizing the FZ_STP module. The FZ_STP module shown in Figure 188 executes the normal symbol stop symbol display process (see Figure 54).

For this normal symbol stop symbol display process, the index "FZ_STP:" on the first line of Figure 188 (a) indicates the starting address of the FZ_STP module.

Then, the command "RET NTZ" on the second line will terminate the FZ_STP module if the second zero flag is not set to 1.

The command on the third line, "LDQ A, (LOW R_FZ_ATA)," sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_FZ_ATA" to the lower byte of the address, and reads the value of that address (the normal symbol winning flag) into the A register. Note that the normal symbol winning flag becomes 01H when a winning regular symbol lottery result is determined, and becomes 00H when a losing regular symbol lottery result is determined.

The command on line 4, "JCP Z,A,@FZ_ATA,FZ_STP_10", compares the value indicated in the A register (the normal symbol winning flag) with the fixed value "@FZ_ATA" indicating a win, here 01H, and if the zero flag is set to 1, it moves to the address indicated in the index "FZ_STP_10" on line 8 (branching the process).

On the other hand, if the zero flag is not set to 1, the command "CLRQ (LOW R_FUT_PHS)" on the fifth line sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_FUT_PHS" to the lower byte of the address, and assigns 0 to the value stored at that address (normal game management phase) (clears it).

The command "CLRQ (LOW R_FZ_STP)" on the sixth line makes the value of the Q register the upper byte of the address, the value of the lowest byte of the address "R_FZ_STP" becomes the lower byte of the address, the value stored at that address (normal symbol stop symbol number) is assigned 0 (cleared), and the command "RET" on the seventh line ends the FZ_STP module.

The commands in FIG. 188(a) can be changed to those in FIG. 188(b). Here, we will omit the explanation of the processes that are essentially the same as those in FIG. 188(a), and only explain the different processes in FIG. 188(b).

The command "JCPQ Z, (LOW R_FZ_ATA), @FZ_ATA, FZ_STP_10" on the third line of Figure 188 (b) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "R_FZ_ATA" to the lower byte of the address, and compares the value of that address (normal symbol winning flag) with the fixed value "@FZ_ATA" indicating a win, 01H in this case. If the zero flag is set to 1, it moves to the address indicated by the index "FZ_STP_10" on the seventh line (branching the process).

Here, the total command size of the command group shown in FIG. 188(a) is 1 byte of the command "RET NTZ" on line 2 + 2 bytes of the command "LDQ A, (LOW R_FZ_ATA)" on line 3 + 3 bytes of the command "JCP Z,A,@FZ_ATA,FZ_STP_10" on line 4 + 2 bytes of the command "CLRQ (LOW R_FUT_PHS)" on line 5 + 2 bytes of the command "CLRQ (LOW R_FZ_STP)" on line 6 + 1 byte of the command "RET" on line 7 = 11 bytes, and the total execution cycles are 3(1) cycles on line 2 + 2 cycles on line 3 + 4(3) cycles on line 4 + 2 cycles on line 5 + 2 cycles on line 6 + 3 cycles on line 7 = 16 (13) cycles. Note that the number of cycles in parentheses indicates the execution cycles if the command "RET NTZ", "JCP Z, ..." is not used to move to the higher routine.

On the other hand, the total command size of the command group shown in FIG. 188(b) is 1 byte of the command "RET NTZ" on the second line + 4 bytes of the command "JCPQ Z, (LOW R_FZ_ATA), @FZ_ATA, FZ_STP_10" on the third line + 2 bytes of the command "CLRQ (LOW R_FUT_PHS)" on the fourth line + 2 bytes of the command "CLRQ (LOW R_FZ_STP)" on the fifth line + 1 byte of the command "RET" on the sixth line = 10 bytes, and the total execution cycle is 3(1) cycles on the second line + 6(5) cycles on the third line + 2 cycles on the fourth line + 2 cycles on the fifth line + 3 cycles on the sixth line = 16 (13) cycles. The number of cycles in parentheses indicates the execution cycle when no movement is made by the commands "RET NTZ", "JCPQ Z, ...".

Therefore, by replacing the command group in FIG. 188(a) with the command group in FIG. 188(b), the total command size is reduced by 1 byte. This replacement shortens the commands and makes it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 188(a) and 188(b), the command group that occupies two lines (lines 3 and 4) in Figure 188(a) can be represented in one line (line 3) in Figure 188(b), making it possible to reduce the number of commands and lighten the design load.

In addition, in the example of FIG. 188(b), the A register is not used. Therefore, the value of the A register will not be updated unintentionally. Also, in the example of FIG. 188(a), if the A register was already in use, it was necessary to save the value of the A register by stacking, but here, since the A register is not used, stack processing is not required. In this way, resources can be used efficiently.

<Random number generator>
189 is a block diagram for explaining the configuration of the random number generators 740 to 746. As described above, the main CPUs 300a, 500a are provided with a plurality of random number generators.

For example, as shown in FIG. 189, the main CPU 300a, 500a is provided with four channels of maximum setting random number generators 740 which are random number generators capable of setting a 16-bit maximum value, four channels of fixed maximum value random number generators 742 which are random number generators whose 16-bit maximum value is fixed at 65536, eight channels of maximum setting random number generators 744 which are random number generators whose 8-bit maximum value can be set, and eight channels of fixed maximum value random number generators 746 which are random number generators whose 8-bit maximum value is fixed at 255. These random number generators 740 to 746 are hardware random number generators (hardware random number generation units).

The maximum value setting random number generator 740 can set the random number update period to any of 32 to 47 clocks, and the start value can be set to any of 0001h, a value based on the ID number, or a value that changes with each system reset. The maximum value fixed random number generator 742 has a random number update period of 1 clock, and the start value is a value that changes with each system reset. Note that a system reset resets the hardware state, and is executed when a specified abnormality occurs when the power is turned on.

The maximum value setting random number generator 744 can set the random number update period to any of 16 to 31 clocks, and the start value can be set to any of 01h, a value based on the ID number, or a value that changes with each system reset. The maximum value fixed random number generator 746 has a random number update period of 1 clock, and the start value is a value that changes with each system reset. In the initial setting process of step S100-1 above, the start value is set and saved, and the random number update periods of the maximum value setting random number generators 740 and 744 are set and saved.

The random number generators 740-746 update their start values every time the system is reset. The maximum value setting random number generator 740 updates the random number (random number counter) by hardware once every 32 to 47 clocks of the internal system clock. The maximum value setting random number generator 744 updates the random number (random number counter) by hardware once every 16 to 31 clocks of the internal system clock. The maximum value fixed random number generators 742 and 746 update the random number (random number counter) by hardware once every clock of the internal system clock. The random number generators 740-746 update their random numbers according to certain rules, and the random number sequence is automatically updated every time the random number sequence goes through one cycle. When the software determines that the game ball has passed through a specified area, the random number (hardware random number count value) is obtained from the random number value register.

The main CPUs 300a, 500a can also generate software random numbers (software random number generation unit) by multiplying and dividing the random number values obtained from the random number generators 740-746 by a predetermined number within the program. The software random number generation unit updates the random numbers while the interrupt processing that occurs every 4 ms is not being executed. Specifically, the software random number generation unit compares the previous random number with the maximum value, and sets the random number to 0 if the previous random number has reached the maximum value, and adds 1 to the random number if the previous random number has not reached the maximum value. Then, when it is determined that the game ball has passed through the predetermined area, a random number (software random number count value) is obtained.

Here, in the gaming machine 100, the following random numbers are provided: a jackpot determining random number, a winning symbol random number, a reach group determining random number, a reach mode determining random number, a variation pattern random number, and a winning random number.

The random number for determining a jackpot is in the range of 0 to 65535, the random number for determining a winning symbol is in the range of 0 to 99, the random number for determining a reach group is in the range of 0 to 10006, the random number for determining a reach mode is in the range of 0 to 250, the random number for determining a fluctuation pattern is in the range of 0 to 238, and the random number for determining a win is in the range of 0 to 99.

In addition, if multiple winning normal symbols are provided, a normal symbol random number must be set, for example in the range of 0 to 99. Furthermore, if multiple normal symbol fluctuation patterns (fluctuation times) are provided, a normal symbol fluctuation pattern random number must be set, for example in the range of 0 to 99.

Figure 190 is a diagram explaining the combination of random number generators. For example, the jackpot determining random number needs to generate a random number between 0 and 65535, so a 16-bit random number generated by a maximum setting random number generator 740 with a maximum value set to 65535 is used. The winning symbol random number needs to generate a random number between 0 and 99, so an 8-bit random number generated by a software random number generator with a maximum value set to 99 is used.

The reach group determination random number needs to generate random numbers between 0 and 10006, so a 16-bit random number generated by a maximum setting random number generator 740 with a maximum value set to 10006 is used. The reach mode determination random number needs to generate random numbers between 0 and 250, so an 8-bit random number generated by a software random number generation unit with a maximum value set to 250 is used. The fluctuation pattern random number needs to generate random numbers between 0 and 238, so an 8-bit random number generated by a software random number generation unit with a maximum value set to 238 is used.

The winning determination random number must generate a random number between 0 and 99, so an 8-bit random number generated by a maximum setting random number generator 744 with the maximum value set to 99 is used. The regular pattern random number must generate a random number between 0 and 99, so an 8-bit random number generated by a software random number generation unit with the maximum value set to 99 is used. The regular variation pattern random number must generate a random number between 0 and 99, so an 8-bit random number generated by a software random number generation unit with the maximum value set to 99 is used.

When using random numbers generated by a software random number generator, it is necessary to execute processes to determine the initial value of the random numbers and to update the random numbers in step S100-61 in FIG. 23, step S400-17 in FIG. 26, and step S100-69 in FIG. 23. This may put a strain on the capacity of the control area for performing game control processing.

As shown in Figs. 190(b) and (c), for example, the jackpot determination random number is in the range of 0 to 65535, the winning pattern random number is in the range of 0 to 99, the reach group determination random number is in the range of 0 to 10006, the reach mode determination random number is in the range of 0 to 1000, the fluctuation pattern random number is in the range of 0 to 255, the winning determination random number is in the range of 0 to 65535, the normal pattern random number is in the range of 0 to 99, and the normal fluctuation pattern random number is in the range of 0 to 255. Note that these random number ranges are merely examples, and any random number may be set to any random number with a maximum value of 65535, which is the maximum value of the maximum value fixed random number generator 742, or a random number with a maximum value of 255, which is the maximum value of the maximum value fixed random number generator 746.

As shown in FIG. 190(b), the jackpot determination random number uses a 16-bit random number generated by a maximum setting random number generator 740 with a maximum value set to 65535. The winning symbol determination random number uses an 8-bit random number generated by a maximum setting random number generator 740 with a maximum value set to 99. The reach group determination random number uses a 16-bit random number generated by a maximum setting random number generator 740 with a maximum value set to 10006. The reach mode determination random number uses a 16-bit random number generated by a maximum setting random number generator with a maximum value set to 1000. The variable pattern random number uses an 8-bit random number generated by a fixed maximum value random number generator 746 with a maximum value fixed to 255.

The winning random number uses a 16-bit random number generated by a maximum setting random number generator 740 with a maximum value set to 65535. The regular pattern random number uses an 8-bit random number generated by a maximum setting random number generator 744 with a maximum value set to 99. The regular variable pattern random number uses an 8-bit random number generated by a fixed maximum value random number generator 746 with a maximum value fixed to 255.

Also, as shown in FIG. 190(c), the jackpot determining random number and the win determining random number may use 16-bit random numbers generated by a fixed maximum random number generator 742 with a maximum value fixed at 65535. The maximum setting random number generator 740 allows the start value, random number update period, maximum random number value, etc. to be set as appropriate, but has a slower random number update period than the fixed maximum random number generator 742. Therefore, for the win/lose random numbers (jackpot determining random numbers and win determining random numbers) that are directly linked to the player's profits, it is better to use the fixed maximum random number generator 742, which has a fast random number update period and makes the random numbers difficult to read.

In this way, by using random numbers generated by random number generators 740-746 (hardware random number generation unit) for multiple random numbers used in the progress of the game, it becomes unnecessary to determine the initial value of the random numbers or execute the process of updating the random numbers in step S100-61 of FIG. 23, step S400-17 of FIG. 26, and step S100-69 of FIG. 23 described above. This makes it possible to reduce the capacity of the main ROM 300b by approximately 35 bytes and to reduce the capacity of the main RAM 300c by approximately 4 bytes. It is thus possible to secure the capacity of the control area for performing game control processing.

<Command "OR">
FIG. 191 is a flowchart showing the specific processing of the SMC_ROT module. Here, as an optional processing, a processing of synthesizing a phase flag indicating the position of a reel with an index flag, which is a part of the SMC_ROT module that executes a processing during steady rotation, will be described. Here, the index flag is a flag represented by a 1-byte value that is turned ON when an index signal is acquired after the reels 410a, 410b, and 410c reach a steady rotation speed. For example, when an index signal of the left reel 410a is acquired, bit 0 of the index flag becomes 1, when an index signal of the center reel 410b is acquired, bit 1 of the index flag becomes 1, and when an index signal of the right reel 410c is acquired, bit 2 of the index flag becomes 1. By referring to such index flags, it is possible to confirm which of the reels 410a, 410b, and 410c has acquired an index signal. Also, the phase flag is a flag represented by 1 byte that specifies the reels 410a, 410b, and 410c that are being processed. For example, when the left reel 410a is being processed, bit 0 of the phase flag becomes 1 (00000001B), when the center reel 410b is being processed, bit 1 of the phase flag becomes 1 (00000010B), and when the right reel 410c is being processed, bit 2 of the phase flag becomes 1 (00000100B). The numerical values of step S in this figure are used only in the explanation of this figure. In addition, in the explanation of the SMC_ROT module, the first register is the C register, the second register is the HL register, and the register different from the first and second registers is the A register.

At the stage of executing such an SMC_ROT module, the value of the phase flag is already held in a predetermined register (for example, the C register). Then, the main CPU 500a executes an arbitrary process as shown in FIG. 191. First, the main CPU 500a sets the address of the index flag (variable) to be subjected to the logical sum in the HL register (S1). Then, in order to synthesize the phase flag with the index flag, the main CPU 500a calculates the logical sum between the value (phase flag) already set in the C register and the 1-byte value stored in the address indicated by the HL register, and overwrites the value stored in the address indicated by the HL register with the result of the logical sum in order to reflect it in the index flag (S2). Here, synthesis means that if any bit of the phase flag, which is a variable, is set (if it is 1), the same bit of the index flag is also set (set to 1). Therefore, since the phase flag is set for the reels 410a, 410b, and 410c being processed, the corresponding bit of the index flag will be set by synthesis regardless of whether an index signal is acquired or not. Furthermore, when all index signals are acquired (when all reels 410a, 410b, 410c reach a steady rotation speed), all bits corresponding to each reel in the index flag are set (00000111B) regardless of the phase flag. Then, the SMC_ROT module is terminated by moving to the PRE_PLS module that executes the excitation pattern update pre-processing (S3). In this way, it is possible to combine the index flag with the phase flag.

Figure 192 is an explanatory diagram for explaining an example of a command for implementing the SMC_ROT module. The flowchart shown in Figure 191 is implemented, for example, by the program shown in Figure 192.

The index "SMC_ROT:" on the first line of FIG. 192 indicates the starting address of the SMC_ROT module. The command "LDQ HL, LOW _IDX_FND" on the second line reads the value of the Q register into the H register, and reads the value of the lowest byte of the address "_IDX_FND" into the L register. This command on the second line corresponds to step S1 in FIG. 191.

The command "LD A, (HL)" on line 3 of Figure 192 reads a one-byte value (the value of the index flag) stored at the address indicated by the HL register into the A register. The command "OR A, C" on line 4 calculates the logical OR of the values in the A register and the C register, and updates the A register with the result of this calculation. Then, the command "LD (HL), A" on line 5 stores the value of the A register at the address indicated by the HL register. In other words, the value of the A register overwrites the one-byte value stored at the address indicated by the HL register, updating the value of the index flag. These commands on lines 3 to 5 correspond to step S2 in Figure 191.

The command "JP PRE_PLS" on the sixth line of FIG. 192 moves to the index "PRE_PLS:" that indicates the start address of the PRE_PLS module. This command on the sixth line corresponds to step S3 in FIG. 191.

In this way, the total command size of the SMC_ROT module commands shown in FIG. 192 is 2 bytes of the command "LDQ HL,LOW _IDX_FND" on line 2 + 1 byte of the command "LD A, (HL)" on line 3 + 1 byte of the command "OR A,C" on line 4 + 1 byte of the command "LD (HL), A" on line 5 + 3 bytes of the command "JP PRE_PLS" on line 6 = 8 bytes, and the total execution cycles are 2 cycles on line 2 + 2 cycles on line 3 + 1 cycle on line 4 + 2 cycles on line 5 + 3 cycles on line 6 = 10 cycles. By providing the processing on lines 3 to 5 in the SMC_ROT module, it becomes possible to easily combine (logical OR) the index flag and phase flag stored as variables.

Figure 193 is an explanatory diagram for explaining another example of commands for implementing the SMC_ROT module. Here, the command group of the SMC_ROT module in Figure 192 is replaced with the command group of the SMC_ROT module in Figure 193.

The index "SMC_ROT:" on the first line of Figure 193 indicates the starting address of the SMC_ROT module. The command "LDQ HL, LOW _IDX_FND" on the second line reads the value of the Q register into the H register, and reads the value of the lowest byte of the address "_IDX_FND" into the L register.

The command "OR (HL), C" on the third line of Fig. 193 calculates the logical sum of the one-byte value stored at the address indicated by the HL register and the value of the C register, and stores the result of this calculation at the address indicated by the HL register. In other words, the result of the calculation is overwritten onto the one-byte value stored at the address indicated by the HL register, and the value of the index flag is updated. This command on the third line corresponds to step S2 in Fig. 191.

The command "JP PRE_PLS" on the fourth line of FIG. 193 moves to the index "PRE_PLS:" that indicates the start address of the PRE_PLS module. This command on the fourth line corresponds to step S3 in FIG. 191.

The total command size of the commands of the SMC_ROT module shown in FIG. 193 is 2 bytes of the command "LDQ HL,LOW _IDX_FND" on the second line + 2 bytes of the command "OR (HL),C" on the third line + 3 bytes of the command "JP PRE_PLS" on the fourth line = 7 bytes, and the total execution cycle is 2 cycles on the second line + 5 cycles on the third line + 3 cycles on the fourth line = 10 cycles. Therefore, compared to the case of FIG. 192, the total command size is reduced by 1 byte. This SMC_ROT module makes it possible to further shorten the commands and secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 192 and 193, the command group that occupies three lines (lines 3 to 5) in Figure 192 can be represented in one line (line 3) in Figure 193, making it possible to reduce the number of commands and lighten the design load.

Note that, although the command "OR (HL), C" which executes a logical sum has been described here, this is not limited to the case, and the command "AND (HL), C" which executes a logical product or "XOR (HL), C" which executes an exclusive logical sum can also be substituted in the same way as a logical sum, and the total command size can be reduced by one byte. Also, the register which stores the address of the variable is not limited to the HL register, but can also be the DE register. Furthermore, the register which is the target of the logical sum is not limited to the C register, but can also be the A register, B register, D register, E register, H register, or L register.

In addition, unlike the example in FIG. 192, the A register is not used here. Therefore, the value of the A register will not be updated unintentionally. Also, in the example in FIG. 192, if the A register was already in use, it was necessary to save the value of the A register by stacking, but here, since the A register is not used, stack processing is not required. In this way, resources can be used efficiently.

<Command "LDF">
Fig. 194 is a flow chart showing the specific processing of the INITIAL module. Here, as an optional processing, the built-in register area setting processing, which is a part of the INITIAL module that executes the CPU initialization processing shown in step S2000 of Fig. 82, will be explained. The numerical values of step S in this figure will be used only in the explanation of this figure. In addition, in the explanation of this INITIAL module, the first register is the HL register.

The main CPU 500a executes an arbitrary process as shown in FIG. 194. First, the main CPU 500a sets the top address of the CPU built-in register setting data table (data table) in the HL register (S1). Then, the main CPU 500a sets the number of setting data (S2).

Then, the main CPU 500a sets the address and setting data of the built-in register accessible through the input/output unit in the C register and the A register, respectively (S3). Next, the value of the A register (setting data) is output to the built-in register indicated by the C register (S4). Next, the main CPU 500a decrements (subtracts "1") the value of the B register (the number of setting data), and determines whether the result of the decrement is 0 or not (S5). Here, if the result of the decrement is not 0 (NO in S5), the process from step S3 is repeated, and if the result of the decrement is 0 (YES in S5), the process proceeds to the next step.

Figure 195 is an explanatory diagram for explaining an example of commands for implementing the INITIAL module. Of these, Figure 195(a) shows the command group of the INITIAL module, and Figure 195(b) shows the arrangement of 1-byte data groups in the program data of main ROM 500b. The flowchart shown in Figure 194 is implemented, for example, by the program shown in Figure 195.

The index "INITIAL:" on the first line of FIG. 195(a) indicates the starting address of the INITIAL module. The command "LD HL, T_CPU_REG" on the second line reads the starting address "T_CPU_REG" of the CPU built-in register setting data table into the HL register. This command on the second line corresponds to step S1 in FIG. 194. The command "LD B, @NUM_CPU_REG" on the third line reads the number of setting data stored at the address "@NUM_CPU_REG" into the B register. This command on the third line corresponds to step S2 in FIG. 194.

As can be seen by referring to line 22 of FIG. 195(b), the address "@NUM_CPU_REG" contains the command "EQU ($-T_CPU_REG)/2". Here, "$" is the address next to the final address of the 1-byte data group that is the source of transfer, i.e., the address "@NUM_CPU_REG" itself, and "T_CPU_REG" is the first address of the 1-byte data group that is the source of transfer, so the value of $-T_CPU_REG (the 1-byte value indicating the number of data) is the total number of bytes of the 1-byte value, and the number of set data is derived by dividing this value by 2, which is the number of combinations of addresses and values. For example, in the example of FIG. 195(b), the number of set data is 20/2=10.

The index "INITIAL01:" on the fourth line of FIG. 195(a) indicates the start address of the repeat process. The command "LDIN AC, (HL)" on the fifth line stores the value stored in the address indicated by the HL register in the C register, and stores the value stored in the address indicated by the value of the HL register plus "1" in the A register. This command on the fifth line corresponds to step S3 in FIG. 194. The command "OUT (C), A" on the sixth line outputs the value of the A register (setting data) to the value indicated by the C register (built-in register). This command on the sixth line corresponds to step S4 in FIG. 194.

For example, if the HL register is the value of address "T_CPU_REG", the 1-byte value "@PT0PR___" on the second line of FIG. 195(b) is stored in the C register, and the value "120" on the third line of FIG. 195(b) is stored in the A register. Then, the value of the A register, i.e., the value "120", is output to the address indicated by the value of the C register, i.e., "@PT0PR___".

Next, the command "DJNZ INITIAL01" on line 7 of Figure 195(a) decrements the value of the B register (subtracts "1"), and if the result of the decrement is not 0, it moves to address "INITIAL01", and if the result of the decrement is 0, it moves to the next command after that command. In this case, the number of data items is "10", so after repeating the process from "INITIAL01" 10 times, the value of the B register will become 0. This command on line 7 corresponds to step S5 in Figure 194.

In this way, the total command size of the INITIAL module commands shown in FIG. 195(a) is 3 bytes of the command "LD HL, T_CPU_REG" on line 2 + 2 bytes of the command "LD B, @NUM_CPU_REG" on line 3 + 2 bytes of the command "LD IN AC, (HL)" on line 5 + 2 bytes of the command "OUT (C), A" on line 6 + 2 bytes of the command "DJNZ INITIAL01" on line 7 = 11 bytes, and the total execution cycle is 3 cycles on line 2 + 2 cycles on line 3 + 4 cycles on line 5 + 3 cycles on line 6 + 3 cycles on line 7 (2 cycles) = 15 cycles (14 cycles). The number of cycles in parentheses indicates the execution cycle when there is no movement by the command "DJNZ INITIAL01". Note that here, since the number of set data = 10, the commands on lines 5 to 7 are repeated 10 times. Therefore, the actual total execution cycles are 3 cycles for line 2 + 2 cycles for line 3 + (4 cycles for line 5 + 3 cycles for line 6 + 3 cycles for line 7) x 9 loops + (4 cycles for line 5 + 3 cycles for line 6 + 2 cycles for line 7) = 104 cycles. This INITIAL module allows you to set the configuration data in the internal register.

Figure 196 is an explanatory diagram for explaining another example of commands for implementing the INITIAL module. Here, the commands of the INITIAL module in Figure 195(a) are replaced with the commands of the INITIAL module in Figure 196(a), and the other 1-byte data groups in the program data of main ROM 500b in Figure 195(b) are used as is as in Figure 196(b).

The index "INITIAL:" on the first line of FIG. 196(a) indicates the start address of the INITIAL module. The command "LDF HL, T_CPU_REG" on the second line reads the start address "T_CPU_REG" of the CPU built-in register setting data table into the HL register. This command on the second line corresponds to step S1 in FIG. 194.

Here, the command "LDF HL, mn" is a command that stores the value of "mn" in the HL register. The command size of this command is "2", and the execution cycle is "2". On the other hand, the commonly used load command "LD HL, mn" is also a command that stores the value of "mn" in the HL register, but the command size of this command is "3", and the execution cycle is "3". Therefore, by changing "LD" to "LDF", on the condition that mn is in the range of 1200H to 1DFFH on the memory map and is loaded into the HL register, the command size is reduced by 1 byte and the execution cycle is also reduced by 1 cycle.

Thus, the value of mn in the command "LDF HL, mn" must be one of 1200H to 1DFFH in the memory map. Therefore, in this embodiment, program data is placed in the range of 1200H to 1DFFH in the used area of main ROM 500b, and the command "LDF HL, mn" is used only when reading data in this range. The assembly code for "LDF HL, 1200H" is expressed as 6A00H, which is the target address "1200H" plus 5800H. Therefore, the assembly code for "LDF HL, 1200H" to "LDF HL, 1DFFH" is 6A00H to 75FFH.

The command "LD B, @NUM_CPU_REG" on the third line of FIG. 196(a) reads the number of setting data stored at the address "@NUM_CPU_REG" into the B register. This command on the third line corresponds to step S2 in FIG. 194.

The index "INITIAL01:" on the fourth line of FIG. 196(a) indicates the start address of the repeat process. The command "LDIN AC, (HL)" on the fifth line stores the value stored in the address indicated by the HL register in the C register, and stores the value stored in the address indicated by the value of the HL register plus "1" in the A register. This command on the fifth line corresponds to step S3 in FIG. 194. The command "OUT (C), A" on the sixth line outputs the value of the A register (setting data) to the value indicated by the C register (built-in register). This command on the sixth line corresponds to step S4 in FIG. 194.

Next, the command "DJNZ INITIAL01" on line 7 of Figure 196(a) decrements the value of the B register (subtracts "1"), and if the result of the decrement is not 0, it moves to address "INITIAL01", and if the result of the decrement is 0, it moves to the next command after that command. In this case, the number of data items is "10", so after repeating the process from "INITIAL01" 10 times, the value of the B register will become 0. This command on line 7 corresponds to step S5 in Figure 194.

In this way, the total command size of the INITIAL module commands shown in FIG. 196(a) is 2 bytes of the command "LDF HL, T_CPU_REG" on line 2 + 2 bytes of the command "LD B, @NUM_CPU_REG" on line 3 + 2 bytes of the command "LDIN AC, (HL)" on line 5 + 2 bytes of the command "OUT (C), A" on line 6 + 2 bytes of the command "DJNZ INITIAL01" on line 7 = 10 bytes, and the total execution cycle is 2 cycles on line 2 + 2 cycles on line 3 + 4 cycles on line 5 + 3 cycles on line 6 + 3 cycles on line 7 (2 cycles) = 14 cycles (13 cycles). The number of cycles in parentheses indicates the execution cycle when there is no movement by the command "DJNZ INITIAL01". Note that here, since the number of set data = 10, the commands on lines 5 to 7 are repeated 10 times. Therefore, the actual total execution cycles are 2 cycles on line 2 + 2 cycles on line 3 + (4 cycles on line 5 + 3 cycles on line 6 + 3 cycles on line 7) x 9 loops + (4 cycles on line 5 + 3 cycles on line 6 + 2 cycles on line 7) = 103 cycles. Therefore, compared to the case of FIG. 195(a), it can be seen that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle. This INITIAL module makes it possible to further shorten the command and reduce the processing load, and ensure the capacity of the control area for performing game control processing.

In the above embodiment, an example was given of the INITIAL module, and in the process of setting configuration data in an internal register, the command "LD HL, T_CPU_REG" was replaced with the command "LDF HL, T_CPU_REG" to further shorten the command and reduce the processing load. However, such a command can be applied to various modules, not limited to the INITIAL module.

For example, the DGEXTRN module, which executes the display data conversion process, also has the command "LD HL, T_SEG_PTN," and like the INITIAL module, the top address of the main display display pattern data table, "T_SEG_PTN," is read into the HL register. The top address, "T_SEG_PTN," is also included in the range of 1200H to 1DFFH. Therefore, in the DGEXTRN module, by changing the command "LD HL, T_SEG_PTN" to the command "LDF HL, T_SEG_PTN," it is possible to further shorten the command and reduce the processing load.

The GET_ARY module, which executes the pattern array data acquisition process, also has the command "LD HL, T_FIG_LIN", and like the INITIAL module, the starting address of the pattern array offset table by active line, "T_FIG_LIN", is read into the HL register. The starting address "T_FIG_LIN" is also included in the range of 1200H to 1DFFH. Therefore, in the GET_ARY module, by changing the command "LD HL, T_FIG_LIN" to the command "LDF HL, T_FIG_LIN", it is possible to further shorten the command and reduce the processing load.

In this way, by keeping the source address within the range of 1200H to 1DFFH, most commands "LD HL, mn" can be replaced with the command "LDF HL, mn." By applying this replacement to all processes in this embodiment, it is possible to reduce the total command size by, for example, 80 to 90 bytes.

This command "LDF" can be used not only in the INITIAL module described above, but also in various other modules, such as the RANKSET module. It can also be used not only in slot machines, but also in pachinko machines, such as the PWRFAIL module and DYM_OUT module.

Figure 197 is an explanatory diagram for explaining the RANKSET module. The RANKSET module shown in step S2020 of Figure 85 performs setting value switching processing, i.e., switches setting values and updates setting value data. Note that here, the data table setting processing at setting value switching in step S2020-5 in the RANKSET module will be described as an example.

The index "RANKSET:" on the first line of Figure 197(a) indicates the starting address of the RANKSET module. The command "LD HL, T_RNK_SET" on the second line reads the starting address "T_RNK_SET" of the data table at the time of setting value switching into the HL register. The command "RST TABLESET" on the third line calls the TABLESET module explained using Figure 138 as a subroutine. The TABLESET module has already been explained, so a detailed explanation is omitted here. Here, two variables (_WIN_DAT, _EXT_REQ) in the data table at the time of setting value switching are set to predetermined values.

If the command "LDF" is substituted here, the command group in FIG. 197(a) can be changed to that in FIG. 197(b). The index "RANKSET:" on the first line of FIG. 197(b) indicates the start address of the RANKSET module. The command "LDF HL, T_RNK_SET" on the second line reads the start address of the data table at the time of setting value switching, "T_RNK_SET", into the HL register. The start address of the data table at the time of setting value switching, "T_RNK_SET", is located in the range of 1200H to 1DFFH in the used area of main ROM 500b. The command "RST TABLESET" on the third line calls the TABLSET module described using FIG. 138 as a subroutine. In this way, similar to FIG. 197(a), the two variables (_WIN_DAT, _EXT_REQ) in the data table when the setting value is switched are set to predetermined values.

Here, the total command size of the commands of the RANKSET module shown in FIG. 197(a) is 3 bytes of the command "LD HL, T_RNK_SET" on the second line + 1 byte of the command "RST TABLESET" on the third line = 4 bytes, and the total execution cycle is 3 cycles on the second line + 4 cycles on the third line = 7 cycles. On the other hand, the total command size of the commands of the RANKSET module shown in FIG. 197(b) is 2 bytes of the command "LDF HL, T_RNK_SET" on the second line + 1 byte of the command "RST TABLESET" on the third line = 3 bytes, and the total execution cycle is 2 cycles on the second line + 4 cycles on the third line = 6 cycles. Therefore, it can be seen that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle compared to the case of FIG. 197(a). This RANKSET module makes it possible to further shorten commands, reduce processing load, and ensure the capacity of the control area for performing game control processing.

Figure 198 is an explanatory diagram for explaining the PWRFAIL module. The PWRFAIL module shown in step S300 of Figure 25 performs a power-off save process, i.e., switches the setting value and updates the setting value data. Note that here, the output port clear process of step S300-11 in the PWRFAIL module will be described as an example.

Here, it is assumed that 00H has been set in advance in the A register as the initial value of the output port. The index "PWRFAIL:" on the first line of FIG. 198(a) indicates the starting address of the PWRFAIL module. The command "LD HL, D_OUT_PRT" on the second line reads the starting address "D_OUT_PRT" of the output port address table into the HL register. The command "LD B, @PRT_CLR_LOP" on the third line reads the output port initialization loop counter value (13 in this case) stored at address "@PRT_CLR_LOP" into the B register as the number of loops.

The index "PWRFAIL_20:" on the fourth line of Figure 198(a) indicates the start address of the repeat process. The command "LD C, (HL)" on the fifth line reads the value stored at the address indicated by the HL register (output port address) into the C register. The command "OUT (C), A" on the sixth line outputs the value of the A register (00H in this case) to the value indicated by the C register (built-in register), and the output port is cleared.

Next, the command "INC HL" on line 7 of Figure 198(a) increments the value of the HL register by 1. The command "DJNZ PWRFAIL_20" on line 8 decrements the value of the B register (subtracts "1"), and if the result of the decrement is not 0, it moves to address "PWRFAIL_20", and if the result of the decrement is 0, it moves to the next command after that command. In this case, the number of data items is "13", so if the process from "PWRFAIL_20" is repeated 13 times, the value of the B register will become 0. In this way, the output port is cleared.

Now, by replacing it with the command "LDF", the command group in FIG. 198(a) can be changed to that in FIG. 198(b). Here again, it is assumed that 00H is set in advance in the A register as the initial value of the output port. The index "PWRFAIL:" in the first line of FIG. 198(b) indicates the start address of the PWRFAIL module. The command "LDF HL, D_OUT_PRT" in the second line reads the start address "D_OUT_PRT" of the output port address table into the HL register. The start address "D_OUT_PRT" of the output port address table is located in the range of 1200H to 1DFFH in the used area of the main ROM 500b. The command "LD B, @PRT_CLR_LOP" in the third line reads the output port initialization loop counter value (here, 13) stored in the address "@PRT_CLR_LOP" into the B register as the number of loops.

The index "PWRFAIL_20:" on the fourth line of Figure 198(b) indicates the start address of the repeat process. The command "LD C, (HL)" on the fifth line reads the value stored at the address indicated by the HL register (output port address) into the C register. The command "OUT (C), A" on the sixth line outputs the value of the A register (00H in this case) to the value indicated by the C register (built-in register), and the output port is cleared.

Next, the command "INC HL" on line 7 of Figure 198 (b) increments the value of the HL register by 1. The command "DJNZ PWRFAIL_20" on line 8 decrements the value of the B register (subtracts "1"), and if the result of the decrement is not 0, it moves to address "PWRFAIL_20", and if the result of the decrement is 0, it moves to the next command after that command. In this case, the number of data items is "13", so after repeating the process from "PWRFAIL_20" 13 times, the value of the B register will become 0. In this way, the output port is cleared.

Here, the total command size of the PWRFAIL module commands shown in Fig. 198(a) is 3 bytes of the command "LD HL, D_OUT_PRT" on line 2 + 2 bytes of the command "LD B, @PRT_CLR_LOP" on line 3 + 1 byte of the command "LD C, (HL)" on line 5 + 2 bytes of the command "OUT (C), A" on line 6 + 1 byte of the command "INC HL" on line 7 + 2 bytes of the command "DJNZ PWRFAIL_20" on line 8 = 11 bytes, and the total execution cycle is 3 cycles on line 2 + 2 cycles on line 3 + 2 cycles on line 5 + 3 cycles on line 6 + 1 cycle on line 7 + 3 cycles (2 cycles) on line 8 = 14 cycles (13 cycles). Note that here, since the output port initialization loop counter value = 13, the commands on lines 5 to 8 are repeated 13 times. Therefore, the actual total execution cycles are 3 cycles for line 2 + 2 cycles for line 3 + (2 cycles for line 5 + 3 cycles for line 6 + 1 cycle for line 7 + 3 cycles for line 8) x 12 loops + (2 cycles for line 5 + 3 cycles for line 6 + 1 cycle for line 7 + 2 cycles for line 8) = 121 cycles.

On the other hand, the total command size of the PWRFAIL module commands shown in FIG. 198(b) is 2 bytes of the command "LDF HL, D_OUT_PRT" on the second line + 2 bytes of the command "LD B, @PRT_CLR_LOP" on the third line + 1 byte of the command "LD C, (HL)" on the fifth line + 2 bytes of the command "OUT (C), A" on the sixth line + 1 byte of the command "INC HL" on the seventh line + 2 bytes of the command "DJNZ PWRFAIL_20" on the eighth line = 10 bytes, and the total execution cycle is 2 cycles on the second line + 2 cycles on the third line + 2 cycles on the fifth line + 3 cycles on the sixth line + 1 cycle on the seventh line + 3 cycles on the eighth line (2 cycles) = 13 cycles (12 cycles). Note that the output port initialization loop counter value is 13 here, so the commands on the fifth to eighth lines are repeated 13 times. Therefore, the actual total execution cycles are 2 cycles on line 2 + 2 cycles on line 3 + (2 cycles on line 5 + 3 cycles on line 6 + 1 cycle on line 7 + 3 cycles on line 8) x 12 loops + (2 cycles on line 5 + 3 cycles on line 6 + 1 cycle on line 7 + 2 cycles on line 8) = 120 cycles. Therefore, compared to the case of FIG. 198(a), it can be seen that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle. This PWRFAIL module makes it possible to further shorten commands, reduce the processing load, and ensure the capacity of the control area for performing game control processing.

Figure 199 is an explanatory diagram for explaining the DYM_OUT module. The DYM_OUT module shown in step S400-5 of Figure 26 executes dynamic port output processing that controls the lighting of the first special symbol display 160, the second special symbol display 162, the first special symbol reserved display 164, the second special symbol reserved display 166, the normal symbol display 168, the normal symbol reserved display 170, the right hit notification display 172, and the performance display monitor 184.

The index "DYM_OUT:" on the first line of Figure 199(a) indicates the starting address of the DYM_OUT module. The command "LD HL, D_DYM_SEL" on the second line reads the starting address of the dynamic display selection table, "D_DYM_SEL", into the HL register. The command "RST WORDSEL" on the third line calls the WORDSEL module described using Figures 127 to 130 as a subroutine. The WORDSEL module has already been described, so a detailed description of it will be omitted here. In this way, four 2-byte data in the dynamic display selection table are selected.

Now, by replacing it with the command "LDF", the command group in FIG. 199(a) can be changed to that in FIG. 199(b). The index "DYM_OUT:" on the first line of FIG. 199(b) indicates the start address of the DYM_OUT module. The command "LDF HL, D_DYM_SEL" on the second line reads the start address "D_DYM_SEL" of the dynamic display selection table to the HL register. The start address "D_DYM_SEL" of the dynamic display selection table is allocated in the range of 1200H to 1DFFH in the used area of main ROM 500b. The command "RST WORDSEL" on the third line calls the WORDSEL module explained using FIG. 127 to FIG. 130 as a subroutine. In this way, four 2-byte data in the dynamic display selection table are selected.

Here, the total command size of the DYM_OUT module commands shown in FIG. 199(a) is 3 bytes of the command "LD HL, D_DYM_SEL" on the second line + 1 byte of the command "RST WORDSEL" on the third line = 4 bytes, and the total execution cycles are 3 cycles on the second line + 4 cycles on the third line = 7 cycles. On the other hand, the total command size of the DYM_OUT module commands shown in FIG. 199(b) is 2 bytes of the command "LDF HL, D_DYM_SEL" on the second line + 1 byte of the command "RST WORDSEL" on the third line = 3 bytes, and the total execution cycles are 2 cycles on the second line + 4 cycles on the third line = 6 cycles. Therefore, it can be seen that the total command size has been reduced by 1 byte and the total execution cycles have been reduced by 1 cycle compared to the case of FIG. 199(a). This DYM_OUT module makes it possible to further shorten commands, reduce processing load, and ensure the capacity of the control area for performing game control processing.

<Command "SET">
Fig. 200 is a flow chart showing the specific processing of the IPT_PD module. Here, as an optional processing, in the CAL_MOD module for executing the state-specific module execution processing shown in step S3100-21 of Fig. 98, the processing of setting the external signal 4, which is a part of the IPT_PD module that selectively transitions once every four times (every 5.96 msec) according to the timer interrupt processing phase (0 to 3) and executes the external signal output control processing, will be described. The numerical values of step S in this figure will be used only in the description of this figure. Also, in the description of the IPT_PD module, the specified register is the HL register.

The main CPU 500a executes any process as shown in FIG. 200. First, the main CPU 500a performs a subtraction process on the counter related to the external signal output hold timer (S1). Then, the main CPU 500a sets the address of the output port 3 image in the HL register (S2). Next, the main CPU 500a determines whether the security signal ON condition is met by the subtraction process of step S1, and if the ON condition is met, sets a specified bit of the external signal 4, i.e., the address value indicated by the HL register (sets it to 1) (S3). Then, the IPT_PD module is terminated and the process returns to the routine one level above (S4). In this way, the external signal 4 can be set.

Figure 201 is an explanatory diagram for explaining an example of a command for implementing the IPT_PD module. The flowchart shown in Figure 200 is implemented, for example, by the program shown in Figure 201.

The index "IPT_PD:" on the first line of FIG. 201 indicates the starting address of the IPT_PD module. The command "RST RAM_DEC" on the second line is a command to call a general-purpose module that decrements a variable by 1, and this command subtracts the counter related to the external signal output holding timer. Here, the command "RST RAM_DEC" updates at least the zero flag. This command on the second line corresponds to step S1 in FIG. 200. The command "LDQ HL, LOW _OUT_PT3" on the third line reads the value of the Q register into the H register, and reads the value of the lowest byte of the address "_OUT_PT3" into the L register. The command "LDQ HL, LOW _OUT_PT3" does not change the zero flag. This command on the third line corresponds to step S2 in FIG. 200.

The command "JR Z, IPT_PD03" on line 4 of Fig. 201 determines whether the subtraction result of the command "RST RAM_DEC" on line 2 is zero. If it is zero (if the zero flag is set), i.e., if the security signal ON condition is not met, it moves to the index "IPT_PD03:" on line 6, and if it is not zero (if the zero flag is not set), it performs the next process. The command "SET @EXT_SG4_POS, (HL)" on line 5 sets the bit of the value (2 in this case) defined by @EXT_SG4_POS in the output port 3 image, i.e., the value stored at the address indicated by the HL register. The index "IPT_PD03:" on line 6 indicates the destination of the command "JR Z, IPT_PD03" on line 4. These commands on lines 4 to 6 correspond to step S3 in Fig. 200. Then, the command "RET" on line 7 of Fig. 201 returns to the routine one level above. This command on line 7 corresponds to step S4 in Fig. 200.

In this way, the total command size of the commands of the IPT_PD module shown in Figure 201 is 1 byte of the command "RST RAM_DEC" on line 2 + 2 bytes of the command "LDQ HL,LOW _OUT_PT3" on line 3 + 2 bytes of the command "JR Z,IPT_PD03" on line 4 + 2 bytes of the command "SET @EXT_SG4_POS,(HL)" on line 5 + 1 byte of the command "RET" on line 7 = 8 bytes, and the total execution cycles are 4 cycles on line 2 + 2 cycles on line 3 + 2 cycles on line 4 + 5 cycles on line 5 + 3 cycles on line 7 = 16 cycles if there is no movement using the command "JR Z,IPT_PD03", and 4 cycles on line 2 + 2 cycles on line 3 + 3 cycles on line 4 + 3 cycles on line 7 = 12 cycles if there is movement using the command "JR Z,IPT_PD03". By implementing the processing on lines 4 to 6 in this IPT_PD module, it becomes possible to manipulate the bits of the output port 3 image according to the subtraction result.

Figure 202 is an explanatory diagram for explaining another example of commands for implementing the IPT_PD module. Here, the command group of the IPT_PD module in Figure 201 is replaced with the command group of the IPT_PD module in Figure 202.

The index "IPT_PD:" on the first line of FIG. 202 indicates the starting address of the IPT_PD module. The command "RST RAM_DEC" on the second line is a command to call a general-purpose module that decrements a variable by 1, and this command subtracts the counter related to the external signal output holding timer. Here, the command "RST RAM_DEC" updates at least the zero flag. This command on the second line corresponds to step S1 in FIG. 200. The command "LDQ HL, LOW _OUT_PT3" on the third line reads the value of the Q register into the H register, and reads the value of the lowest byte of the address "_OUT_PT3" into the L register. The command "LDQ HL, LOW _OUT_PT3" does not change the zero flag. This command on the third line corresponds to step S2 in FIG. 200.

The command "SET NZ, @EXT_SG4_POS, (HL)" on the fourth line of Fig. 202 sets the bit of the value (2 in this case) defined by @EXT_SG4_POS in the output port 3 image, i.e., the address value indicated by the HL register, if the subtraction result of the command "RST RAM_DEC" on the second line is not zero (if the zero flag is not set), i.e., if the security signal ON condition is met. This command on the fourth line corresponds to step S3 in Fig. 200. Then, the command "RET" on the fifth line of Fig. 202 returns to the routine one level above. This command on the fifth line corresponds to step S4 in Fig. 200.

Here, the command "SET cc, b, (HL)" is a command that sets the bth bit of the address value (variable) indicated by the HL register if the flag corresponding to cc (zero flag or carry flag) is true. The command size of this command is "2", and the execution cycle is "5" ("2"). Note that the number of cycles in parentheses indicates the execution cycle when the flag is not true in the command "SET cc, b, (HL)".

In this way, the total command size of the commands of the IPT_PD module shown in FIG. 202 is 1 byte of the command "RST RAM_DEC" on the second line + 2 bytes of the command "LDQ HL, LOW _OUT_PT3" on the third line + 2 bytes of the command "SET NZ, @EXT_SG4_POS, (HL)" on the fourth line + 1 byte of the command "RET" on the fifth line = 6 bytes, and the total execution cycle is 4 cycles on the second line + 2 cycles on the third line + 5 cycles on the fourth line (2 cycles) + 3 cycles on the fifth line = 14 cycles (11 cycles). Therefore, compared to the case of FIG. 201, the total command size is reduced by 2 bytes, and the total execution cycle is reduced by at least 1 cycle. With this IPT_PD module, it is possible to further shorten the commands and reduce the processing load, and ensure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 201 and 202, the command group that occupies three lines (lines 4 to 6) in Figure 201 can be represented in one line (line 4) in Figure 202, making it possible to reduce the number of commands and lighten the design load.

Note that, although the bit setting command "SET cc, b, (HL)" has been given here as an example, the bit setting command "SET cc, b, r" can also be used. Here, the command "SET cc, b, r" is a command that sets the b-th bit of the value of r (A register, B register, D register, E register, H register, L register) if the flag (zero flag or carry flag) corresponding to cc is true. The command size of this command is "2", and the execution cycle is "2".

This command "SET" can be used not only in the IPT_PD module described above, but also in various other modules, such as the DYNMOUT module. It can also be used not only in slot machines, but also in pachinko machines, such as the EXT_PRC module.

Figure 203 is an explanatory diagram for explaining the DYNMOUT module. In the DYNMOUT module shown in step S3100-7 of Figure 98, the main CPU 500a outputs the set output image to the output port, and executes a dynamic port output process (dynamic lighting control process) that controls the lighting of the main credit display section 430, the main payout display section 432, the number of inserted coins indicator, the start indicator, the indicators of the stop switches 420a, 420b, and 420c, the replay indicator, and the section indicator 460.

The index "DYNMOUT:" on the first line of FIG. 203(a) indicates the starting address of the DYNMOUT module. The command "RESQ @CHN_DSP_BIT, (LOW _WIN_DAT+1)" on the second line sets the value of the Q register to the upper byte of the address, and sets the value obtained by adding 1 to the lower byte of the address "_WIN_DAT" to the lower byte of the address, and sets (resets) the bit indicated by @CHN_DSP_BIT (here, bit 7) in the value stored at that address (main display data buffer 2) to 0. The command "LDQ A, (LOW _OUT_PT2)" on the third line sets the value of the Q register to the upper byte of the address, and sets the value of the lower byte of the address "_OUT_PT2" to the lower byte of the address, and reads the value stored at that address (output port 2 image) into the A register. The command on line 4, "JAND Z, A, 00000011B, DYNMOUT02," moves to address "DYNMOUT02" if the logical AND of the value of the A register and 00000011B is zero, and if it is not zero, processes the command on line 5. The command on line 5, "SET Q @CHN_DSP_BIT, (LOW _WIN_DAT+1)," sets the value of the Q register to the upper 1 byte of the address, sets the value obtained by adding 1 to the lower 1 byte of the address "_WIN_DAT" to the lower 1 byte of the address, and sets (sets) the bit indicated by @CHN_DSP_BIT (here, bit 7) of the value stored at that address (main display data buffer 2) to 1. The index "DYNMOUT02:" on the sixth line indicates the destination of the command "JAND Z, A, 00000011B, DYNMOUT02" on the fourth line. This makes it possible to set bit 7 of main display data buffer 2 according to the value of the lowest two bits of the output port 2 image.

If the command "SET" is substituted here, the group of commands in Figure 203(a) can be changed to that shown in Figure 203(b). The index "DYNMOUT:" on the first line of Figure 203(b) indicates the starting address of the DYNMOUT module. The command "LDQ HL,LOW _WIN_DAT+1" on the second line reads the value of the Q register into the H register, and reads the value obtained by adding 1 to the value of the lowest byte of the address "_WIN_DAT" into the L register. The command "RES @CHN_DSP_BIT,(HL)" on the third line sets (resets) the bit indicated by @CHN_DSP_BIT (here, bit 7) in the value stored at the address indicated by the HL register to 0. The command "LDQ A, (LOW _OUT_PT2)" on the fourth line sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "_OUT_PT2" to the lower byte of the address, and reads the value stored at that address (output port 2 image) into the A register. The command "AND A, 00000011B" on the fifth line performs a logical AND operation on the value of the A register and 00000011B, masking the A register. The command "SET NZ, @CHN_DSP_BIT, (HL)" on the sixth line sets the bit indicated by @CHN_DSP_BIT (here, bit 7) in the address value indicated by the HL register (main display data buffer 2) to 1 if the result of the operation of the command "AND A, 00000011B" on the fifth line is not zero (if the zero flag is not set). In this way, similar to Figure 203 (a), it is possible to set bit 7 of main display data buffer 2 according to the value of the lower 2 bits of the output port 2 image.

Here, the total command size of the DYNMOUT module commands shown in FIG. 203(a) is the command on the second line "RESQ @CHN_DSP_BIT, (LOW _WIN_DAT+1)" (3 bytes) + the command on the third line "LDQ A, (LOW _OUT_PT2)" (2 bytes) + the command on the fourth line "JAND Z, A, 00000011B, DYNMOUT02" (3 bytes) + the command on the fifth line "SETQ @CHN_DSP_BIT, (LOW _WIN_DAT+1) (3 bytes) = 11 bytes, and the total execution cycles are 6 cycles on line 2 + 3 cycles on line 3 + 3 cycles on line 4 + 6 cycles on line 5 = 18 cycles if the lowest 2 bits of the output port 2 image are not 0, and 6 cycles on line 2 + 3 cycles on line 3 + 4 cycles on line 4 = 13 cycles if both lowest 2 bits of the output port 2 image are 0.

On the other hand, the total command size of the DYNMOUT module commands shown in Figure 203 (b) is the command on the second line "LDQ HL, LOW _WIN_DAT+1" (2 bytes) + the command on the third line "RES @CHN_DSP_BIT, (HL)" (2 bytes) + the command on the fourth line "LDQ A, (LOW _OUT_PT2)" (2 bytes) + the command on the fifth line "AND A, 00000011B" (2 bytes) + the command on the sixth line "SET NZ, @CHN_DSP_BIT, (HL)" 2 bytes = 10 bytes, and the total execution cycles are 2 cycles on line 2 + 5 cycles on line 3 + 3 cycles on line 4 + 2 cycles on line 5 + 5 cycles on line 6 = 17 cycles if the lowest 2 bits of the output port 2 image are not 0, and 2 cycles on line 2 + 5 cycles on line 3 + 3 cycles on line 4 + 2 cycles on line 5 + 2 cycles on line 6 = 14 cycles if both lowest 2 bits of the output port 2 image are 0. Therefore, it can be seen that the total command size has been reduced by 1 byte compared to the case of FIG. 203(a). This DYNMOUT module makes it possible to further shorten the command and ensure the capacity of the control area for performing game control processing.

Figure 204 is an explanatory diagram for explaining the EXT_PRC module. In the EXT_PRC module shown in step S400-29 of Figure 26, the main CPU 500a performs external information management processing, i.e., sets output data for external information to be output from the game information output terminal board 312 to the outside.

The index "EXT_PRC:" on the first line of Figure 204(a) indicates the starting address of the EXT_PRC module. The command "LD BC, @D_SEC_LOP * 256 + 0" on the second line sets the number of RAMs to be checked (number of loops), @D_SEC_LOP (here 8), in the B register, and sets 0 as the initial value of the composite bit data in the C register. The command "JR Z, EXT_PRC_15" on the third line determines whether the logical product of the target RAM address calculated before executing the command is zero, and if it is zero (if the zero flag is set), it moves to the index "EXT_PRC_15:" on the fifth line, and if it is not zero (if the zero flag is not set), it performs the processing on the fourth line. The command on line 4, "SET @EXT_SEC_POS, C," sets the bit of the value (here, bit 6) defined by @EXT_SEC_POS in the value of the C register (composite bit data). The index on line 5, "EXT_PRC_15:," indicates the destination of the command on line 3, "JR Z, EXT_PRC_15." In this way, it becomes possible to set bit 6 of the composite bit data according to the result of the logical AND operation of the target RAM address.

If the command "SET" is substituted here, the command group in FIG. 204(a) can be changed to that in FIG. 204(b). The index "EXT_PRC:" in the first line of FIG. 204(b) indicates the start address of the EXT_PRC module. The command "LD BC, @D_SEC_LOP*256+0" in the second line sets the number of RAMs to be checked (loop count) @D_SEC_LOP (here, 8) in the B register, and sets 0 as the initial value of the composite bit data in the C register. The command "SET NZ, @EXT_SEC_POS, C" in the third line determines whether the logical product of the target RAM address calculated before the command is executed is zero, and if it is not zero (if the zero flag is not set), the bit of the value (here, bit 6) defined by @EXT_SEC_POS in the value of the C register (composite bit data) is set. In this way, similar to FIG. 204(a), it is possible to set bit 6 of the composite bit data according to the result of the logical AND operation of the target RAM address.

The total command size of the commands in the EXT_PRC module shown in Figure 204(a) is 2 bytes of the command on line 2 "LD BC, @D_SEC_LOP * 256 + 0" + 2 bytes of the command on line 3 "JR Z, EXT_PRC_15" + 2 bytes of the command on line 4 "SET @EXT_SEC_POS, C" = 6 bytes, and the total execution cycles are 2 cycles on line 2 + 2 cycles on line 3 + 2 cycles on line 4 = 6 cycles if the logical product is not 0, and 2 cycles on line 2 + 3 cycles on line 3 = 5 cycles if the logical product is 0.

On the other hand, the total command size of the commands of the EXT_PRC module shown in FIG. 204(b) is 2 bytes of the command on the second line "LD BC, @D_SEC_LOP * 256 + 0" + 2 bytes of the command on the third line "SET NZ, @EXT_SEC_POS, C" = 4 bytes, and the total execution cycles are 2 cycles on the second line + 5 cycles on the third line = 7 cycles if the logical product is not 0, and 2 cycles on the second line + 2 cycles on the third line = 4 cycles if the logical product is 0. Therefore, it can be seen that the total command size has been reduced by 2 bytes compared to the case of FIG. 204(a). With this EXT_PRC module, it is possible to further shorten the commands and ensure the capacity of the control area for performing game control processing.

<Command "JANDQ">
Fig. 205 is a flow chart showing the specific processing of the STOPDCT module. Here, as an optional processing, the processing S2500-23 for checking the stop indicator, which is a part of the STOPDCT module that executes the processing during reel rotation shown in step S2500 of Fig. 92, is explained. The numerical values of step S in this figure are used only in the explanation of this figure. In addition, in the explanation of the STOPDCT module, the specified register is the HL register.

The main CPU 500a executes any process as shown in FIG. 205. First, the main CPU 500a extracts the bit to be operated (S1). This process sets the bit to be operated in the A register. Then, the main CPU 500a combines the bit to be operated in the A register with the rotation in progress flag previously set in the D register (S2). Next, the main CPU 500a checks the stop indicator by performing a logical AND with the address value indicating the stop indicator (S3). If the stop indicator is lit red (YES in S4), the process is repeated from the beginning of the STOPDCT module, and if the stop indicator is not lit red (NO in S4), the next process is executed. Then, the STOPDCT module is terminated by moving to the STP_REL module that executes the rotation stop process (S5). In this way, pressing process according to the state of the stop indicator is possible.

Figure 206 is an explanatory diagram for explaining an example of a command for implementing the STOPDCT module. The flowchart shown in Figure 205 is implemented, for example, by the program shown in Figure 206.

The index "STOPDCT:" on the first line of FIG. 206 indicates the start address of the STOPDCT module. The command "CALLF SMPLBIT" on the second line is a command to call the SMPLBIT module that executes the target bit extraction process, and the bit corresponding to the stop switch that is the target of operation (actually operated) is set in the A register by this command. This command on the second line corresponds to step S1 in FIG. 205. The command "AND A, D" on the third line calculates the logical product of the A register in which the target bit is set and the D register in which the rotation in progress flag is set in advance, and stores the result in the A register. This command on the third line corresponds to step S2 in FIG. 205.

The command "ANDQ A, (LOW _OUT_PT4)" on the fourth line of FIG. 206 calculates the logical product of the value of the Q register as the upper byte and the value of the address "_OUT_PT4" (first predetermined value) as the lower byte (the value of the stop indicator) and the value of the A register, and stores the result in the A register. This command on the fourth line corresponds to step S3 in FIG. 205. The command "JR Z, STOPDCT" on the fifth line determines whether the result of the operation of the command "ANDQ A, (LOW _OUT_PT4)" on the fourth line is zero or not. If it is zero (if the zero flag is set), it moves to the index "STOPDCT:" (second predetermined value) on the first line, and if it is not zero (if the zero flag is not set), the next process is performed. This command on the fifth line corresponds to step S4 in FIG. 205.

In this way, the total command size of the STOPDCT module commands shown in FIG. 206 is 2 bytes of the command "CALLF SMPLBIT" on the second line + 1 byte of the command "AND A, D" on the third line + 3 bytes of the command "ANDQ A, (LOW _OUT_PT4)" on the fourth line + 2 bytes of the command "JR Z, STOPDCT" on the fifth line = 8 bytes, and the total execution cycle is 4 cycles on the second line + 1 cycle on the third line + 4 cycles on the fourth line + 3 cycles (2 cycles) on the fifth line = 12 cycles (11 cycles). The number of cycles in parentheses indicates the execution cycle when no movement is made by the command "JR Z, STOPDCT". By providing the processing on the fourth and fifth lines in this STOPDCT module, it becomes possible to perform pressing processing according to the state of the stop indicator.

Figure 207 is an explanatory diagram for explaining another example of commands for implementing the STOPDCT module. Here, the command group of the STOPDCT module in Figure 206 is replaced with the command group of the STOPDCT module in Figure 207.

The index "STOPDCT:" on the first line of FIG. 207 indicates the start address of the STOPDCT module. The command "CALLF SMPLBIT" on the second line is a command to call the SMPLBIT module that executes the target bit extraction process, and the bit corresponding to the stop switch that is the target of operation is set in the A register by this command. This command on the second line corresponds to step S1 in FIG. 205. The command "AND A, D" on the third line calculates the logical product of the A register in which the target bit is set and the D register in which the rotation in progress flag has been set in advance, and stores the result in the A register. This command on the third line corresponds to step S2 in FIG. 205.

The command "JANDQ Z, A, (LOW _OUT_PT4), STOPDCT" on the fourth line of Fig. 207 calculates the logical product of the value of the Q register as the most significant byte and the value of the address "_OUT_PT4" (first predetermined value) as the least significant byte (the value of the stop indicator) and the value of the A register, and determines whether the result of this calculation is zero or not. If it is zero (if the zero flag is set), it moves to the index "STOPDCT:" (second predetermined value) on the first line, and if it is not zero (if the zero flag is not set), the next process is performed. This command on the fourth line corresponds to steps S3 and S4 in Fig. 205.

Here, the command "JANDQ cc, A, (k), e" calculates the logical AND of the value of the A register, with the value of the Q register as the upper byte and the value of the address indicated by k as the lower byte (first predetermined value), and if the flag corresponding to cc (zero flag or carry flag) of the calculation result is true, it moves to the address indicated by e (second predetermined value), and if the flag corresponding to cc is not true, it moves to the next process. The command size of this command is "4", and the execution cycle is "6" ("5"). Note that the number of cycles in parentheses indicates the execution cycle when the flag is not true in the command "JANDQ cc, A, (k), e".

The total command size of the STOPDCT module commands shown in FIG. 207 is 2 bytes of the command "CALLF SMPLBIT" on the second line + 1 byte of the command "AND A, D" on the third line + 4 bytes of the command "JANDQ Z, A, (LOW _OUT_PT4), STOPDCT" on the fourth line = 7 bytes, and the total execution cycle is 4 cycles on the second line + 1 cycle on the third line + 6 cycles (5 cycles) on the fourth line = 11 cycles (10 cycles). The number of cycles in parentheses indicates the execution cycle when no movement is made by the command "JANDQ Z, A, (LOW _OUT_PT4), STOPDCT". Therefore, compared to the case of FIG. 206, the total command size is reduced by 1 byte, and the total execution cycle is reduced by at least 1 cycle. This STOPDCT module makes it possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 206 and 207, the command group that occupies two lines (lines 4 and 5) in Figure 206 can be represented in one line (line 4) in Figure 207, making it possible to reduce the number of commands and lighten the design load.

<Command "CALLEX">
The E_SETTM module is a module for setting an abnormality non-monitoring timer for turning on, that is, for setting an abnormality non-monitoring timer for turning on, in the ERRWAIT module that executes the error wait process shown in step S2200-11 of Fig. 89 and step S2800-39 of Fig. 95. The E_SETTM module is allocated in another area (2000H to 3FBFH) of the main ROM 500b.

The main CPU 500a reads the program in the use area from the main ROM 500b, executes the read program, and in any process, calls the E_SETTM module in another area as a subroutine and executes the E_SETTM module. The E_SETTM module sets a timer for non-monitoring of abnormal input.

Figure 208 is a flowchart showing the specific processing of the E_SETTM module. Here, as an optional process, a part of the BLKSHUT module that executes the blocker blocking process in the ERRWAIT module that executes the error wait process shown in step S2200-11 in Figure 89 and step S2800-39 in Figure 95 is explained. The numerical values of step S in this figure will be used only in the explanation of this figure.

The main CPU 500a executes any process as shown in FIG. 208(a). The main CPU 500a checks the blocker state, and if bit 3 of the output port 4 image (blocker solenoid output bit number) is not 0, it calls the E_SETTM module in another area. For this reason, the main CPU 500a first prohibits interrupts (S1), and calls the E_SETTM module in another area as a subroutine (S2).

As shown in FIG. 208(b), the main CPU 500a saves the general-purpose registers (A register, B register, C register, D register, E register, H register, L register, F register) in the E_SETTM module (S3). The main CPU 500a then sets the initial value of the on-chip abnormality non-monitoring timer value in the A register (S4), stores the value of the A register at a specified address (on-chip abnormality non-monitoring timer), and sets the on-chip abnormality non-monitoring timer (S5). When this process is complete, the main CPU 500a restores the general-purpose registers (S6), enables interrupts (S7), and ends the E_SETTM module to return to the routine one step above (S8).

The E_SETTM module is designed to meet all of the above conditions (1) to (6) in order to ensure the fairness of the gaming machine while properly dividing roles between the use area and the other area.

Figure 209 is an explanatory diagram for explaining an example of commands for implementing the E_SETTM module. Of these, Figure 209(a) shows a command group for an arbitrary process that calls the E_SETTM module, and Figure 209(b) shows a command group for the E_SETTM module. The flowchart shown in Figure 208 is implemented, for example, by the program shown in Figure 209.

The command "DI" on the first line of Fig. 209(a) disables interrupts. This command on the first line corresponds to step S1 in Fig. 208(a). The command "CALL E_SETTM" on the second line calls the E_SETTM module as a subroutine. This command on the second line corresponds to step S2 in Fig. 208(a).

The index "E_SETM:" on the first line of FIG. 209(b) indicates the starting address of the E_SETM module. The command "EX AF, AF'" on the second line swaps the value of pair register AF with the value of pair register AF', which is a back register, and saves the value of pair register AF. The command "EXX" on the third line swaps the values of pair registers BC, DE, and HL with the values of pair registers BC', DE', and HL', which are back registers, and saves the values of pair registers BC, DE, and HL. These commands on the second and third lines correspond to step S3 in FIG. 208(b).

The command "LD A, @MDL_WAT_TMR" on the fourth line of FIG. 209(b) reads the fixed value "@MDL_WAT_TMR", i.e., (252/6 + 1) equivalent to 250.32 msec as the power-on abnormality non-monitoring timer value (initial value) into the A register. This command on the fourth line corresponds to step S4 in FIG. 208(b). The command "LD (_EX_SLTM), A" on the fifth line stores the value of the A register in the variable "_EX_SLTM" as the power-on abnormality non-monitoring timer. This command on the fifth line corresponds to step S5 in FIG. 208(b). In this way, it is possible to set the power-on abnormality non-monitoring timer value in the power-on abnormality non-monitoring timer.

The command "EXX" on the sixth line in FIG. 209(b) swaps the values of the pair registers BC, DE, and HL with the values of the pair registers BC', DE', and HL', which are backed up registers, and restores the values of the pair registers BC, DE, and HL. The command "EX AF, AF'" on the seventh line swaps the value of the pair register AF with the value of the pair register AF', which is a backed up register, and restores the value of the pair register AF. These commands on the sixth and seventh lines correspond to step S6 in FIG. 208(b). The command "EI" on the eighth line in FIG. 209(b) allows interrupts. Note that here, even if the command "EI" is executed before returning from the subroutine, interrupts are properly allowed. Therefore, by describing the command "EI" in the subroutine, it is possible to secure the capacity of the used area. This command on the eighth line corresponds to step S7 in FIG. 208(b). Then, the command "RET" on the ninth line returns to the routine one level above. The command on line 9 corresponds to step S8 in FIG. 208(b). In this way, it is possible to set a non-monitoring timer for abnormal power-on in a separate area.

In this way, the total command size of the BLKSHUT module shown in Fig. 209(a) and the E_SETTM module shown in Fig. 209(b) is 1 byte of the command "DI" on the first line of Fig. 209(a) + 3 bytes of the command "CALL E_SETTM" on the second line + 1 byte of the command "EX AF, AF'" on the second line of Fig. 209(b) + 1 byte of the command "EXX" on the third line + 2 bytes of the command "LD A, @MDL_WAT_TMR" on the fourth line + 4 bytes of the command "LD (_EX_SLTM), A" on the fifth line + 1 byte of the command "EXX" on the sixth line + 1 byte of the command "EX AF,AF' 1 byte + EI command on line 8 1 byte + RET command on line 9 1 byte = 16 bytes, and the total execution cycle is 1 cycle on line 1 of FIG. 209(a) + 5 cycles on line 2 of FIG. 209(b) + 1 cycle on line 2 of FIG. 209(b) + 1 cycle on line 3 of FIG. 209(b) + 2 cycles on line 4 of FIG. 5 of FIG. 6 of FIG. 7 of FIG. 8 of FIG. 9 of FIG. 10 of FIG. 11 of FIG. 12 of FIG. 13 of FIG. 14 of FIG. 15 of FIG. 16 of FIG. 17 of FIG. 18 of FIG. 19 of FIG. 209(b) + 1 cycle on line 3 of FIG. 209(b) + 2 cycles on line 4 of FIG. 5 of FIG. 6 of FIG. 7 of FIG. 8 of FIG. 9 of FIG. 19 of FIG. 18 of FIG. 19 of FIG. 19 of FIG. 209(b) + 1 cycle on line 6 of FIG. 19 of FIG. 209(b) + 1 cycle on line 7 of FIG. 209(b) + 1 cycle on line 8 of FIG. 209(b) + 3 cycles on line 9 of FIG. 20 of FIG. 209(b) of FIG. 209(b). By providing such an E_SETTM module, it is possible to use the 3-byte command CALL E_SETTM without setting an insertion abnormality non-monitoring timer in each of the above-mentioned modules, and this can be achieved by shortening the command and ensuring the capacity of the control area for performing game control processing.

Figure 210 is an explanatory diagram for explaining another example of commands for implementing the E_SETTM module. Here, the command group for any process that calls the E_SETTM module in Figure 209(a) is replaced with the command group for any process that calls the E_SETTM module in Figure 210(a), and the command group for the E_SETTM module in Figure 209(b) is replaced with the command group for the E_SETTM module in Figure 210(b).

The command "CALLEX E_SETTM" on the first line of Fig. 210(a) calls the E_SETTM module as a subroutine. This command on the first line corresponds to step S2 in Fig. 208(a).

Here, the command "CALLEX mn" is a command that calls a subroutine having a starting address indicated by a fixed value mn, just like the command "CALL mn". However, the command "CALLEX mn" does not simply call a subroutine like the command "CALL mn", but has multiple functions. For example, by executing this command, the non-maskable interrupt (NMI) and maskable interrupt (INT) are automatically prohibited, the register bank is switched from the first register bank 726 to the second register bank 728, and then a subroutine having a starting address indicated by a fixed value mn is called. Therefore, there is no need for the interrupt-related command "DI" or the save-related commands "EX AF, AF'" and "EXX" (or the command "PUSH"). Therefore, the command "CALLEX E_SETTM" on the first line of FIG. 210(a) corresponds not only to step S2 of FIG. 208(a), but also to step S1 of FIG. 208(a) and step S3 of FIG. 208(b). The command size of this command is "2" and the execution cycle is "4".

However, the command "CALLEX mn" has certain limitations. For example, if the call destination address is in the range of 2000H to 20FFH on the address map, the command size of the command is "2" and the execution cycle is "4", but outside of that range, the command size of the command is "4" and the execution cycle is "6". Therefore, in order to shorten the command, in this embodiment, the call destination address, for example, "E_SETTM", is placed so that it is included within 2000H to 20FFH.

The index "E_SETTM:" on the first line of FIG. 210(b) indicates the starting address of the E_SETTM module. The command "LD A, @MDL_WAT_TMR" on the second line reads the fixed value "@MDL_WAT_TMR", i.e., (252/6+1) equivalent to 250.32 msec as the power-on abnormality non-monitoring timer value (initial value) into the A register. This command on the second line corresponds to step S4 in FIG. 208(b). The command "LD (_EX_SLTM), A" on the third line stores the value of the A register in the variable "_EX_SLTM" as the power-on abnormality non-monitoring timer. This command on the third line corresponds to step S5 in FIG. 208(b). In this way, it is possible to set the power-on abnormality non-monitoring timer value in the power-on abnormality non-monitoring timer.

The command "RETEX" on the fourth line of Fig. 210(b) returns to the routine one level above. This command on the fourth line corresponds to step S8 in Fig. 208(b). In this way, it becomes possible to set a non-monitoring timer for abnormal switching in a separate area.

Here, the command "RETEX" is a command to return to the routine one level above, just like the command "RET". However, the command "RETEX" is often used in pairs with the command "CALLEX mn", and unlike the command "RET", it has multiple functions in addition to simply returning from a subroutine. For example, by executing this command, the register bank is automatically switched from the second register bank 728 to the first register bank 726, an interrupt is permitted, and then the routine returns to the one level above. Therefore, there is no need for the return-related commands "EXX", "EX AF, AF'" (or the command "POP"), or the interrupt-related command "EI". Therefore, the command "RETEX" on the fourth line of FIG. 210(b) corresponds not only to step S8 in FIG. 208(b) but also to steps S6 and S7 in FIG. 208(b). The command size of this command is "2", and the execution cycle is "5".

The total command size of the BLKSHUT module shown in FIG. 210(a) and the E_SETTM module shown in FIG. 210(b) is 2 bytes of the command "CALLEX E_SETTM" on the first line of FIG. 210(a) + 2 bytes of the command "LD A, @MDL_WAT_TMR" on the second line of FIG. 210(b) + 4 bytes of the command "LD (_EX_SLTM), A" on the third line + 2 bytes of the command "RETEX" on the fourth line = 10 bytes, and the total execution cycle is 4 cycles on the first line of FIG. 210(a) + 2 cycles on the second line of FIG. 210(b) + 4 cycles on the third line + 5 cycles on the fourth line = 15 cycles. Therefore, compared to the case of FIG. 209, the total command size is reduced by 6 bytes, and the total execution cycle is also reduced by at least 5 cycles. This E_SETTM module makes it possible to further shorten commands and reduce processing load, while ensuring sufficient control area capacity for game control processing.

In addition, as can be seen by comparing Figures 209 and 210, the command group that occupied eight lines in Figure 209 (lines 1 and 2 in Figure 209(a) and lines 2, 3, and 6 to 9 in Figure 209(b)) can be represented in two lines in Figure 210 (line 1 in Figure 210(a) and line 4 in Figure 210(b)), making it possible to reduce the number of commands and lighten the design load.

This command "CALLEX" can be used not only in the BLKSHUT module described above, but also in various other modules. It can also be used not only in slot machines, but also in the DYM_OUT module in pachinko machines, for example.

Figures 211 and 212 are explanatory diagrams for explaining the DYM_OUT module. The DYM_OUT module shown in step S400-5 of Figure 26 executes dynamic port output processing that controls the lighting of the first special symbol display 160, the second special symbol display 162, the first special symbol reserved display 164, the second special symbol reserved display 166, the normal symbol display 168, the normal symbol reserved display 170, the right hit notification display 172, and the performance display monitor 184.

The command "DI" on the first line of Figure 211(a) disables interrupts. The command "CALL E_DMOUT" on the second line calls the E_DMOUT module as a subroutine.

The index "E_DMOUT:" on the first line of FIG. 211(b) indicates the starting address of the E_DMOUT module. The command "EX AF, AF'" on the second line swaps the value of the pair register AF with the value of the back register pair register AF', and saves the value of the pair register AF. The command "EXX" on the third line swaps the values of the pair registers BC, DE, and HL with the values of the back register pair registers BC', DE', and HL', and saves the values of the pair registers BC, DE, and HL. The command "LD HL, R_ERW_IOB" on the fourth line sets the address "R_ERW_IOB" of the identification segment output request buffer in the HL register. The command "LD A, (R_COM_CNT)" on the fifth line reads a 1-byte value (common counter) stored at the address indicated by "R_COM_CNT" into the A register. Here, the common counter is used to determine the common number for LED dynamic lighting control, and a value indicating the common number is stored in it. The command "LD A, (HL+A)" on the sixth line reads out a 1-byte value (display data) stored in the address indicated by the HL register plus (offset) the value of the A register into the A register. The command "OUT (@OTC_PRT), A" on the seventh line sets the value of the U register as the upper byte of the address, sets the fixed value "@OTC_PRT" indicating the lower byte of the address of the output port 12 (internal register I/O port) as the lower byte, and outputs the value of the A register to that address. The command "EXX" on the eighth line swaps the values of the pair registers BC, DE, and HL with the values of the pair registers BC', DE', and HL', which are back registers, and restores the values of the pair registers BC, DE, and HL. The command "EX AF, AF" on line 9 swaps the value of pair register AF with the value of the back register, pair register AF', and restores the value of pair register AF. The command "EI" on line 10 enables interrupts. Note that interrupts are also enabled properly here even if the command "EI" is executed before returning from the subroutine. Therefore, by writing the command "EI" in the subroutine, it is possible to secure the capacity of the area to be used. Then, the command "RET" on line 11 returns to the routine one level above. In this way, dynamic port output processing can be executed in a separate area.

If you replace it with the command "CALLEX" here, the command group in Figure 211 can be changed to that shown in Figure 212. The command "CALLEX E_DMOUT" on the first line of Figure 212(a) calls the E_DMOUT module as a subroutine. Here, the call destination address, for example, "E_DMOUT", is placed so that it is included within 2000H to 20FFH.

The index "E_DMOUT:" on the first line of Figure 212 (b) indicates the starting address of the E_DMOUT module. The command "LD HL, R_ERW_IOB" on the second line sets the address of the identification segment output request buffer "R_ERW_IOB" in the HL register. The command "LD A, (R_COM_CNT)" on the third line reads a one-byte value (common counter) stored at the address indicated by "R_COM_CNT" into the A register. The command "LD A, (HL+A)" on the fourth line reads a one-byte value (display data) stored at the address indicated by the HL register plus (offset) the value of the A register. The command "OUT (@OTC_PRT), A" on line 5 sets the value of the U register to the upper byte of the address, and the fixed value "@OTC_PRT" indicating the lower byte of the address of the output port 12 (internal register I/O port) to the lower byte, and outputs the value of the A register to that address. The command "RETEX" on line 6 returns to the routine one level above. In this way, dynamic port output processing can be executed in a separate area, just like in Figure 211.

In this way, the total command size of the DYM_OUT module shown in Figure 211(a) and the E_DMOUT module shown in Figure 211(b) is 1 byte of the command "DI" on the first line of Figure 211(a) + 3 bytes of the command "CALL E_DMOUT" on the second line + 1 byte of the command "EX AF, AF'" on the second line of Figure 211(b) + 1 byte of the command "EXX" on the third line + 3 bytes of the command "LD HL, R_ERW_IOB" on the fourth line + 3 bytes of the command "LD A, (R_COM_CNT)" on the fifth line + 3 bytes of the command "LD A, (HL+A)" on the sixth line + 2 bytes of the command "OUT (@OTC_PRT), A" on the seventh line + 1 byte of the command "EXX" on the eighth line + 1 byte of the command "EX 1 byte of "AF, AF'" + 1 byte of command "EI" on line 10 + 1 byte of command "RET" on line 11 = 21 bytes, and the total execution cycles are 1 cycle of line 1 in Fig. 211(a) + 5 cycles of line 2 + 1 cycle of line 2 in Fig. 211(b) + 1 cycle of line 3 + 3 cycles of line 4 + 4 cycles of line 5 + 4 cycles of line 6 + 3 cycles of line 7 + 1 cycle of line 8 + 1 cycle of line 9 + 1 cycle of line 10 + 3 cycles of line 11 = 28 cycles.

On the other hand, the total command size of the DYM_OUT module shown in FIG. 212(a) and the E_DMOUT module shown in FIG. 212(b) is 2 bytes of the command "CALLEX E_DMOUT" on the first line of FIG. 212(a) + 3 bytes of the command "LD HL, R_ERW_IOB" on the second line of FIG. 212(b) + 3 bytes of the command "LD A, (R_COM_CNT)" on the third line + 3 bytes of the command "LD A, (HL+A)" on the fourth line + 2 bytes of the command "OUT (@OTC_PRT), A" on the fifth line + 2 bytes of the command "RETEX" on the sixth line = 15 bytes, and the total execution cycles are 4 cycles on the first line of FIG. 212(a) + 3 cycles on the second line of FIG. 212(b) + 4 cycles on the third line + 4 cycles on the fourth line + 3 cycles on the fifth line + 5 cycles on the sixth line = 23 cycles. Therefore, compared to the case of FIG. 211, the total command size is reduced by 6 bytes, and the total execution cycle is also reduced by 5 cycles. This E_DMOUT module makes it possible to further shorten commands and reduce the processing load, and to ensure the capacity of the control area for performing game control processing.

As explained using Figures 208 to 210, the command "CALLEX mn" has a command size of "2" and an execution cycle of "4" if the callee address is in the range of 2000H to 20FFH on the address map, but in any other range, the command size is "4" and the execution cycle is "6". Therefore, it is desirable to place all callee addresses in the range of 2000H to 20FFH. However, since only 256 bytes can be written between 2000H and 20FFH, if subroutines are written directly in this range, the number of subroutines will be limited. For example, even with the E_SETTM module, which has a relatively small command size, the 2 bytes of the command "LD A, @MDL_WAT_TMR" on the second line in Figure 210(b) + the 4 bytes of the command "LD (_EX_SLTM), A" on the third line + the 2 bytes of the command "RETEX" on the fourth line occupy 8 bytes, making it impossible to place a large number of subroutines.

Therefore, in this embodiment, in the range of 2000H to 20FFH on the address map, essentially only the movement-related command "JP mn" is placed, and the main body of the subroutine is placed at the movement destination. Since the command size of such a "JP mn" command is "3", by arranging the "JP mn" command in the range of 2000H to 20FFH on the address map, it becomes possible to call 256/3 = 86 modules as subroutines.

It is also possible to use the command "CALL mn" with a command size of "3" instead of the command "JP mn", but in that case, it becomes necessary to place the command "RETEX" with a command size of "2" after the command "CALL mn", which limits the number of subroutines compared to the command "JP mn". Therefore, it is preferable to use the command "JP mn". Below, we will explain the specific processing of the E_SETTM module that reflects this content.

Figure 213 is a flowchart showing the specific processing of the E_SETTM module. As an optional process, a part of the BLKSHUT module that executes blocker blocking processing, as in Figure 208, will be explained here. The numerical values of step S in this figure will be used only in the explanation of this figure.

The main CPU 500a executes an arbitrary process as shown in FIG. 213(a). The main CPU 500a calls the RRE01 module as a subroutine in another area (S1).

Then, the main CPU 500a moves to the E_SETTM module without performing any significant processing in the RRE01 module, as shown in FIG. 213(b) (S2). In this way, the RRE01 module is a module for moving to the E_SETTM module, and is placed in the range of 2000H to 20FFH on the address map. In this way, a large number of subroutines can be placed.

As shown in FIG. 213(c), the main CPU 500a sets the value of the non-monitoring timer for the power-on abnormality in the A register in the E_SETTM module (S3), stores the value of the A register at a specified address (power-on abnormality non-monitoring timer), and sets the power-on abnormality non-monitoring timer (S4). When this process is completed, the main CPU 500a ends the E_SETTM module and returns to the routine one step above (S5). Since the E_SETTM module is the destination of the RRE01 module, it is not subject to the address map restrictions. Therefore, it can be placed anywhere in the range of 2100H to 3FBFH in a separate area, so a somewhat large total command size is acceptable.

Figure 214 is an explanatory diagram for explaining yet another example of a command for implementing the E_SETTM module. Here, as shown in Figure 214 (b), a new RRE01 module is provided for moving to the E_SETTM module.

The command "CALLEX PRE01" on the first line of Fig. 214(a) calls the RRE01 module as a subroutine instead of the E_SETTM module. This command on the first line corresponds to step S1 in Fig. 213(a). The command "CALLEX PRE01" also disables interrupts and saves the general-purpose registers.

The index "PRE01:" on the first line of Figure 214(b) indicates the starting address of the PRE01 module. The command "JP E_SETTM" on the second line moves to the E_SETTM module body. This command corresponds to step S2 in Figure 213(b).

When calling multiple subroutines using the command "CALLEX mn", the index showing the calling addresses for those multiple subroutines (for example, "PRE01:") and the command "JP mn" are placed consecutively in the range from 2000H to 20FFH. This makes effective use of the range from 2000H to 20FFH, allowing a large number of subroutines to be placed.

The index "E_SETTM:" on the first line of FIG. 214(c) indicates the starting address of the E_SETTM module. The command "LD A, @MDL_WAT_TMR" on the second line reads the fixed value "@MDL_WAT_TMR", i.e., (252/6+1) equivalent to 250.32 msec as the power-on abnormality non-monitoring timer value (initial value) into the A register. This command on the second line corresponds to step S3 in FIG. 213(c). The command "LD (_EX_SLTM), A" on the third line stores the value of the A register in the variable "_EX_SLTM" as the power-on abnormality non-monitoring timer. This command on the third line corresponds to step S4 in FIG. 213(c). In this way, it is possible to set the power-on abnormality non-monitoring timer value in the power-on abnormality non-monitoring timer.

The command "RETEX" on the fourth line of Fig. 214(c) returns to the routine one level above. This command on the fourth line corresponds to step S5 of Fig. 213(c). In this way, it becomes possible to set a timer for non-monitoring of abnormal input in a separate area. The command "RETEX" also restores the general-purpose registers and allows interrupts.

In the example of FIG. 214, the total command size and total execution cycles are larger than in FIG. 210 by the amount of the command "JP E_SETTM". However, by configuring the command "JP E_SETTM" to move to a subroutine, it is possible to allocate many subroutines in the range from 2000H to 20FFH, widening the limit on the number of subroutines and relaxing the limit on the command size of the subroutines themselves. As a result, it is possible to further shorten commands and reduce the processing load, and to ensure the capacity of the control area for performing game control processing.

Note that if there are not enough subroutines to place even if only the "JP mn" command is placed in the range from 2000H to 20FFH, i.e. if there are 86 or more subroutines, it is possible to place modules with a small total command size in the range from 2100H to 217FH (a range of 128 bytes) and use the "JR mn" command with a command size of "2", which is suitable for short distance movement, instead of the "JP mn" command with a command size of "3". This makes it possible to place even more "JR mn" commands in the range from 2000H to 20FFH.

<Command "ICPLMQA", "ICPLMQ">
The RAM_INC module is a module for performing RAM addition processing, that is, incrementing a 1-byte variable in the main RAM 500c by 1 up to a predetermined number. The RAM_INC module not only increments, but also sets a carry flag as a result of the increment. The RAM_INC module can also be used as a general-purpose module.

Such a RAM_INC module is called as a subroutine from a number of modules. For example, the HID_LOT module selectively transitions depending on the game state and presentation state in the EXE_SET module which executes the execution flag setting process shown in step S2400-11 in FIG. 91, and executes this premonition process (AT state = "3"); the FIN_LOT module selectively transitions depending on the game state and presentation state in the EXE_SET module which executes the execution flag setting process shown in step S2400-11 in FIG. 91, and executes the end screen process (AT state = "4"); In the EXE_SET module which executes the execution flag setting process shown in step S2400-11 in FIG. 91, the EXE_SET module selectively transitions depending on the game state and presentation state, and is called from the REG_LOT module which executes the REG processing (AT state = "6"), and in the EXE_SET module which executes the execution flag setting process shown in step S2400-11 in FIG. 91, the EXE_SET module selectively transitions depending on the game state and presentation state, and is called from the BIT_LOT module which executes the BIG processing (AT state = "7"), etc.

The main CPU 500a reads a program from the main ROM 500b, executes the read program, and increments a one-byte value stored in the main RAM 500c during any processing.

Figure 215 is a flow chart showing the specific processing of the RAM_INC module. The numerical values of step S in this figure are used only in the explanation of this figure. In addition, in the explanation of this RAM_INC module, the specified register is the A register, the specified number is the upper limit value, and the specific address is the address to be incremented.

As shown in FIG. 215(a), in any process, the main CPU 500a sets the address to be incremented in the HL register (S1). The main CPU 500a then increments the 1-byte value stored in the address indicated by the HL register (S2), and stores the incremented value in the address indicated by the HL address, updating the value (S3). However, here, an upper limit (a predetermined number) is set so that the incremented result does not exceed this upper limit.

Figures 216 and 217 are explanatory diagrams for explaining an example of a command for implementing the RAM_INC module. The flowchart shown in Figure 215 is implemented, for example, by the program shown in Figure 216.

The index "RAM_INC:" on the first line of FIG. 216 indicates the starting address of the RAM_INC module. The command "LDQ HL,LOW _AT_SET" on the second line reads the value of the Q register into the H register, and the value of the lowest byte of the address "_AT_SET" into the L register. This command on the second line corresponds to step S1 in FIG. 215. The command "LD A, (HL)" on the third line reads a byte value (e.g., 02H) stored at the address indicated by the HL register into the A register, as shown in FIG. 217. The command "INC A" on the fourth line of FIG. 216 increments the value of the A register by 1, for example, from 02H to 03H, as shown in FIG. 217. For versatility, the commands "LD A, 1" and "ADD A, (HL)" can be used instead of the command "LD A, (HL)" on the third line and the command "INC A" on the fourth line. In this case, the increment value can be changed to a value other than 1 by changing the value of "1" stored in the A register.

The command "JCP C, A, 5, RAM_INC01" on line 5 of Figure 216 compares the value of the A register with the upper limit value "5", and if it is less than 5 (if the carry flag is set), it moves to the address "RAM_INC01". In this way, if the value of the A register is less than the upper limit value of 5, the next process can be omitted and it can be moved to the index "RAM_INC01" on line 7. The command "LD A, 5" on line 6 stores the upper limit value "5" in the A register. This is to forcibly overwrite the value of the A register with 5 when the command "INC A" on line 4 causes the value of the A register to exceed 5, so that the increment result is 5 or less. Note that here, if the value of the A register before the increment is 4, that is, when the value of the A register is incremented from 4 to 5, the value of the A register is already 5, so there is no need to update it to 5, but adding a process to determine this would increase the processing load, so versatility is prioritized and the value of the A register is forcibly updated to 5, just as when it exceeds 5. The commands on lines 3 to 6 correspond to step S2 in Figure 215.

The index "RAM_INC01" on line 7 of Figure 216 indicates the destination address of the command "JCP C, A, 5, RAM_INC01" on line 5. The command "LD (HL), A" on line 8 stores the value of the A register (for example, 03H) at the address indicated by the HL register, as shown in Figure 217. This command on line 8 corresponds to step S3 in Figure 215. In this way, it becomes possible to increment a 1-byte variable in main RAM 500c by 1 up to a specified number, while retaining the incremented value in the A register (the value in the A register can be used in subsequent processing).

In this way, the total command size of the commands of the RAM_INC module shown in FIG. 216 is 2 bytes of the command "LDQ HL,LOW _AT_SET" on the second line + 1 byte of the command "LD A, (HL)" on the third line + 1 byte of the command "INC A" on the fourth line + 3 bytes of the command "JCP C,A,5,RAM_INC01" on the fifth line + 2 bytes of the command "LD A,5" on the sixth line + 1 byte of the command "LD (HL), A" on the eighth line = 10 bytes, and the total execution cycle is 2 cycles on the second line + 2 cycles on the third line + 1 cycle on the fourth line + 4 cycles on the fifth line + 2 cycles on the sixth line + 2 cycles on the eighth line = 13 cycles. By providing such a RAM_INC module, 1-byte variables can be incremented uniformly and easily, so it is possible to shorten the commands and ensure the capacity of the control area for performing game control processing.

Figure 218 is an explanatory diagram for explaining another example of commands for implementing the RAM_INC module. Here, the command group of the RAM_INC module in Figure 216 is replaced with the command group of the RAM_INC module in Figure 218.

The index "RAM_INC:" on the first line of FIG. 218 indicates the start address of the RAM_INC module. The command "ICPLMQA (LOW _AT_SET), 5" on the second line sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "_AT_SET" as the lower byte of the address, and compares the byte value stored in that address (the address to be incremented) with the upper limit value "5". If the result is less than 5 (if the carry flag is set), the byte value stored in the address to be incremented is incremented by 1 and stored in the A register, and the byte value stored in the address to be incremented is updated. If the incremented value is 5 or more (if the carry flag is not set), the upper limit value "5" is stored in the A register, and the byte value stored in the address to be incremented is updated to the upper limit value "5". Such commands on the second line correspond to steps S1 to S3 in FIG. 215. In this way, it is possible to increment a 1-byte variable in main RAM 500c by 1 up to a specified number, while retaining the incremented value in the A register (the value in the A register can be used in subsequent processing).

Here, the command "ICPLMQA (k), n" sets the value of the Q register as the upper byte of the address, sets the value k as the lower byte of the address, and compares the byte value stored in the target address with the upper limit value n. If the result is less than n, the byte value stored in the target address is incremented by 1 and stored in the A register, and the byte value stored in the target address is updated; if the result is n or greater, the upper limit value n is stored in the A register, and the byte value stored in the target address is updated to the upper limit value n. The command size is "4" and the execution cycle is "7".

The total command size of the command of the RAM_INC module in Figure 218 is the command on the second line "ICPLMQA (LOW_AT_SET), 5" 4 bytes = 4 bytes, and the total execution cycle is the command on the second line 7 cycles = 7 cycles. Therefore, compared to the case of Figure 216, the total command size is reduced by 6 bytes and the total execution cycle is reduced by 6 cycles. This RAM_INC module makes it possible to further shorten commands and reduce the processing load, and ensure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 216 and 218, the command group that occupies seven lines (lines 2 to 8) in Figure 216 can be represented in one line (line 2) in Figure 218, making it possible to reduce the number of commands and lighten the design load.

Figure 219 is an explanatory diagram for explaining yet another example of a command for implementing the RAM_INC module. In the RAM_INC module explained using Figure 218, an example was given in which a 1-byte variable in main RAM 500c is incremented by 1 up to a predetermined number, while the incremented value is stored in the A register. However, depending on the process, there are cases in which it is sufficient to simply increment a 1-byte variable in main RAM 500c by 1 up to a predetermined number, without leaving the result in the A register. Here, an example is given in which a 1-byte variable is incremented by 1 without updating the A register.

The index "RAM_INC:" on the first line of FIG. 219 indicates the starting address of the RAM_INC module. The command "ICPLMQ (LOW _AT_SET), 5" on the second line sets the value of the Q register as the upper byte of the address, sets the value of the lower byte of the address "_AT_SET" as the lower byte of the address, and compares the byte value stored in that address (the address to be incremented) with the upper limit value "5". If the result is less than 5 (if the carry flag is set), the byte value stored in the address to be incremented is incremented by 1 and updated. If the incremented value is 5 or more (if the carry flag is not set), the byte value stored in the address to be incremented is updated to the upper limit value "5". The command on the second line corresponds to steps S1 to S3 in FIG. 215. In this way, it becomes possible to increment a 1-byte variable in the main RAM 500c by 1, with a predetermined number as the upper limit.

Here, the command "ICPLMQ (k), n" sets the value of the Q register as the upper byte of the address, sets the value k as the lower byte of the address, compares the byte value stored at the target address with the upper limit value n, and if the result is less than n, increments the byte value stored at the target address by 1 and updates it, and if it is equal to or greater than n, updates the byte value stored at the target address to the upper limit value n. The command size is "4" and the execution cycle is "7".

The total command size of the command of the RAM_INC module in Figure 219 is the command on the second line "ICPLMQ (LOW_AT_SET), 5" 4 bytes = 4 bytes, and the total execution cycle is the command on the second line 7 cycles = 7 cycles. Therefore, compared to the case of Figure 216, the total command size is reduced by 6 bytes, and the total execution cycle is reduced by 6 cycles. This RAM_INC module makes it possible to further shorten commands and reduce the processing load, and to ensure the capacity of the control area for performing game control processing.

In addition, unlike the example in FIG. 216, the A register is not used here. Therefore, the value of the A register will not be updated unintentionally. Also, in the example in FIG. 216, if the A register was already in use, it was necessary to save the value of the A register by stacking, but here, since the A register is not used, stack processing is not required. In this way, resources can be used efficiently.

In addition, as can be seen by comparing Figures 216 and 219, the command group that occupies seven lines (lines 2 to 8) in Figure 216 can be represented in one line (line 2) in Figure 219, making it possible to reduce the number of commands and lighten the design load.

<Command "LDINTQR">
The TABLESET module is a general-purpose module for table set processing, i.e., for setting predetermined values (initial values) to variables in the main RAM 500c. Here, an example will be described in which the TABLESET module is allocated at 0030H on the memory map.

The main CPU 500a reads a program from the main ROM 500b, executes the read program, and in any process, calls the TABLESET module as a subroutine and executes the TABLESET module. The TABLESET module transfers multiple 1-byte values written in the program data in the main ROM 500b to an area in the work area of the main RAM 500c that holds multiple pieces of data treated as variables. In this way, the values of multiple variables are set. Here, the number of pieces of data to be transferred is simply called the number of pieces of data.

Figure 220 is a flow chart showing the specific processing of the TABLESET module. Here, as an optional process, the error wait processing shown in step S2200-11 of Figure 89 and step S2800-39 of Figure 95, that is, a part of the ERRWAIT module that executes error display, warning sound request, and error recovery wait, is explained. The numerical values of step S in this figure are used only in the explanation of this figure. Also, in the explanation of this TABLESET module, the first register is the B register, the second register is the HL register, the register different from the first and second registers is the A register, and the predetermined value is "1". It goes without saying that the predetermined value can be set arbitrarily.

As shown in FIG. 220(a), in any process, the main CPU 500a sets the first address of a 1-byte data group that is to be transferred in the HL register (S1). Then, it calls the TABLESET module as a subroutine (S2).

As shown in FIG. 220(b), the main CPU 500a saves the BC register in the TABLESET module (S3) and inhibits interrupts (S4). Then, the main CPU 500a reads the 1-byte value stored in the address indicated by the HL register into the B register (S5). This 1-byte value indicates the number of data. Next, the main CPU 500a transfers the value stored in the address indicated by the value added to the HL register by "2" to the address specified by the value stored in the address indicated by the value added to the HL register by "1", and adds "2" to the value of the HL register to set the address to be transferred next (S6). Next, the main CPU 500a decrements the value of the B register (subtracts "1") and determines whether the result of the decrement is 0 or not (S7). If the result of the decrement is not 0 (NO in S7), the process repeats from step S6. If the result of the decrement is 0 (YES in S7), an interrupt is permitted (S8), the BC register is restored (S9), the TABLESET module is terminated, and the process returns to the routine one level above (S10).

Figures 221 and 222 are explanatory diagrams for explaining an example of commands for implementing the TABLESET module. Of these, Figure 221(a) shows a command group for an arbitrary process that calls the TABLESET module, Figure 221(b) shows a command group for the TABLESET module, Figure 221(c) shows the arrangement of a 1-byte data group in the program data of main ROM 500b, and Figure 221(d) shows the arrangement of a 1-byte data group in the work area of main RAM 500c. The flowchart shown in Figure 220 is implemented, for example, by the program shown in Figure 221.

The command "LD HL, T_ERR_RCV" on the first line of Fig. 221(a) sets the starting address "T_ERR_RCV" of the 1-byte data group that is the transfer source in the HL register. This command on the first line corresponds to step S1 in Fig. 220(a). Then, the command "RST TABLESET" on the second line calls the TABLESET module as a subroutine. This command on the second line corresponds to step S2 in Fig. 220(a).

The index "TABLESET:" on the first line of FIG. 221(b) indicates the top address of the TABLESET module. The command "PUSH BC" on the second line saves the value of the BC register to the stack area. This command on the second line corresponds to step S3 in FIG. 220(b). The command "DI" on the third line disables interrupts. This command on the third line corresponds to step S4 in FIG. 220(b).

The command "LD B, (HL)" on the fourth line of Fig. 221(b) reads the one-byte value stored in the address indicated by the HL register into the B register. At this time, the address "T_ERR_RCV" is set in the HL register as shown in Fig. 221(a). Therefore, the one-byte value "(T_ERR_RCV_-T_ERR_RCV)/2" on the second line of Fig. 221(c) is read into the B register as the number of data (number of transfer repetitions). Note that "T_ERR_RCV_" is the address next to the last address of the one-byte data group that is the transfer source, and T_ERR_RCV is the first address of the one-byte data group that is the transfer source, so the value of T_ERR_RCV_-T_ERR_RCV (the one-byte value indicating the number of data) is the total number of bytes of the one-byte value, and the number of data is derived by dividing this value by 2, which is the number of combinations of addresses and values. In the example of Figure 221(c), the number of data items is 9/2 = 4. The command on the fourth line of Figure 221(b) corresponds to step S5 in Figure 220(b).

The index "TABLESET10:" on line 5 of Figure 221(b) indicates the start address of the repeat process. The command "INLD AC, (HL)" on line 6 and the command "LDQ (C), A" on line 7 store the value stored in the address indicated by the value stored in the address indicated by the value stored in the HL register plus "1", and "2" is added to the value of the HL register to set the address to be transferred next. These commands on lines 6 and 7 correspond to step S6 in Figure 220(b).

For example, if the HL register contains the value of address "T_ERR_RCV", the value of the lowest byte of the 2-byte variable "_ERR_NUM" on the third line of Figure 221(c) is stored in the C register, and the value "0" on the third line of Figure 221(c) is stored in the A register.

The command "LDQ (C), A" on line 7 of Figure 221(b) is a command that stores the value of the A register at the address with the value of the Q register as the most significant byte of the address and the value of the C register as the least significant byte of the address.

For example, the value of the C register, i.e., the value of the lowest byte of "_ERR_NUM", is set as the lowest byte of the address, and the value of the A register, i.e., the value "0", is stored at that address.

Here, in Figures 221(c) and 221(d), the variable "_ERR_NUM" indicates the error number, the variable "_CRE_TMR" indicates the credit button detection timer, the variable "_CRE_FLG" indicates the credit button detection flag, and the variable "_SNS_OLD" indicates the previous state of the medal passage sensor bit. Note that the arrangement of the variables shown in Figure 221(d) does not need to be contiguous as shown in the figure, and they may be spaced apart.

Next, the command "DJNZ TABLESET10" on line 8 of Figure 221(b) decrements the value of the B register (subtracts "1"), and if the result of the decrement is not 0, it moves to address "TABLESET10", and if the result of the decrement is 0, it moves to the next command after that command. In this case, the number of data items is "4", so after repeating the process from "TABLESET10" four times, the value of the B register becomes 0. This command on line 8 corresponds to step S7 in Figure 220(b).

The command "EI" on line 9 of Fig. 221(b) allows interrupts. This command on line 9 corresponds to step S8 of Fig. 220(b). The command "POP BC" on line 10 restores the data saved in the stack area to the BC register. This command on line 10 corresponds to step S9 of Fig. 220(b). Then, the command "RET" on line 11 returns to the routine one level above. This command on line 11 corresponds to step S10 of Fig. 220(b).

In this way, as shown in FIG. 222, it becomes possible to transfer multiple 1-byte values (55H, 77H, 66H, 22H) written in the program data of main ROM 500b to variables ("_ERR_NUM", "_CRE_TMR", "_CRE_FLG", "_SNS_OLD") in the work area of main RAM 500c.

The TABLESET module is called as a subroutine from multiple modules. For example, the HID_LOT module, which selectively transitions depending on the game state and presentation state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, and executes this premonition process (AT state = "3"); the FIN_LOT module, which selectively transitions depending on the game state and presentation state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, and executes the end screen process (AT state = "4"); the PRE_LOT module, which selectively transitions depending on the game state and presentation state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, and executes the preparation process (AT state = "5"); It is called from the REG_LOT module, which selectively transitions depending on the game state and presentation state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, the BIG_LOT module, which selectively transitions depending on the game state and presentation state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, and executes the BIG_LOT module (AT state = "7") in the BIG_LOT module that selectively transitions depending on the game state and presentation state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, the RANKSET module that executes the setting value switching process shown in step S2020 in FIG. 85, the FGSETUP module that executes the symbol code setting process shown in step S2400 in FIG. 91, the GAMESET module that executes the game transition process shown in step S2900 in FIG. 96, and the JCGMSET module that executes the role-operated processing shown in step S2900-3 in FIG. 96.

Thus, the total command size of the commands in the TABLESET module shown in Figure 221 (b) is: 1 byte of the command "PUSH BC" on the second line + 1 byte of the command "DI" on the third line + 1 byte of the command "LD B, (HL)" on the fourth line + 2 bytes of the command "INLD AC, (HL)" on the sixth line + 2 bytes of the command "LDQ (C), A" on the seventh line + 2 bytes of the command "DJNZ TABLESET10" on the eighth line + 1 byte of the command "EI" on the ninth line + 1 byte of the command "POP BC" 1 byte + 1 byte of the command "RET" on line 11 = 12 bytes, and the total execution cycles are 3 cycles on line 2 + 1 cycle on line 3 + 2 cycles on line 4 + 4 cycles on line 6 + 3 cycles on line 7 + 3 cycles (or 2 cycles) on line 8 + 1 cycle on line 9 + 3 cycles on line 10 + 3 cycles on line 11 = 23 cycles (or 22 cycles). The number of cycles in parentheses indicates the execution cycles when no movement is made by the command "DJNZ TABLESET10". By providing such a TABLESET module, it is possible to cover the table set processing in each of the above-mentioned modules with the command size of 1 byte "RST TABLESET", which shortens the command and makes it possible to secure the capacity of the control area for performing game control processing.

Figure 223 is an explanatory diagram for explaining another example of commands for realizing the TABLESET module. Here, the commands of the TABLESET module in Figure 221(b) are replaced with the commands of the TABLESET module in Figure 223(b), and the commands of any other process that calls the TABLESET module in Figure 221(a), the 1-byte data group in the program data of the main ROM 500b in Figure 221(c), and the 1-byte data group in the work area of the main RAM 500c in Figure 221(d) are used as they are in Figures 223(a), 223(c), and 223(d). Here, as in Figures 223(a), 223(c), and 223(d), the description of the processes that are substantially the same as those in Figures 221(a), 221(c), and 221(d) is omitted, and only the different processes in Figure 223(b) are described.

The index "TABLESET:" on the first line of FIG. 223(b) indicates the starting address of the TABLESET module. The command "PUSH BC" on the second line saves the value of the BC register to the stack area. This command on the second line corresponds to step S3 in FIG. 220(b). The command "DI" on the third line disables interrupts. This command on the third line corresponds to step S4 in FIG. 220(b).

The command "LD B, (HL)" on the fourth line of Figure 223(b) reads a one-byte value stored in the address indicated by the HL register into the B register. At this time, the address "T_ERR_RCV" is set in the HL register as shown in Figure 223(a). Therefore, the one-byte value "(T_ERR_RCV_-T_ERR_RCV)/2" on the second line of Figure 223(c) is read into the B register as the number of data (number of transfer repetitions). In the example of Figure 223(c), the number of data is 4. This command on the fourth line of Figure 223(b) corresponds to step S5 in Figure 220(b).

The command "INC HL" on line 5 of Figure 223(b) increments the value of the HL register by 1. The command "LDINTQR (HL)" on line 6 transfers the value stored in the address indicated by the value stored in the HL register plus "1" to the address specified by the value stored in the address indicated by the HL register, adds "2" to the value of the HL register to set the next transfer address, decrements the value of the B register (subtracts "1"), and repeats this process until the decrement result becomes 0. The commands on lines 5 and 6 correspond to steps S6 and S7 of Figure 220(b).

Here, the command "LDINTQR (HL)" sets the value of the Q register to the upper byte of the address, sets the value stored at the address indicated by the HL register to the lower byte of the address, transfers to that address the value stored at the address indicated by the value of the HL register plus "1", updates the value of the HL register by adding "2", decrements the value of the B register (subtracts "1"), and repeats the value transfer until the result of the decrement becomes 0. The command size of this command is "2", and the execution cycle is "5".

For example, if the HL register holds the value of address "T_ERR_RCV," then the value of the Q register becomes the most significant byte of the address, the value of the least significant byte of "_ERR_NUM" on the third line of Figure 223(c) becomes the most significant byte of the address, the value of "0" on the third line of Figure 223(c) is transferred to that address, "2" is added to the value of the HL register, and the value of the B register is decremented (subtracted "1"); this transfer is repeated until the result of the decrement becomes 0, that is, four times.

Next, interrupts are permitted by the command "EI" on line 7 of Fig. 223(b). This command on line 7 corresponds to step S8 of Fig. 220(b). The data saved in the stack area is restored to the BC register by the command "POP BC" on line 8. This command on line 8 corresponds to step S9 of Fig. 220(b). Then, the command "RET" on line 9 returns to the routine one level above. This command on line 9 corresponds to step S10 of Fig. 220(b).

The total command size of the commands in the TABLESET module in Fig. 223(b) is 1 byte of the command "PUSH BC" on line 2 + 1 byte of the command "DI" on line 3 + 1 byte of the command "LD B, (HL)" on line 4 + 1 byte of the command "INC HL" on line 5 + 2 bytes of the command "LDINTQR (HL)" on line 6 + 1 byte of the command "EI" on line 7 + 1 byte of the command "POP BC" on line 8 + 1 byte of the command "RET" on line 9 = 9 bytes, and the total execution cycles are 3 cycles on line 2 + 1 cycle on line 3 + 2 cycles on line 4 + 1 cycle on line 5 + 5 cycles on line 6 + 1 cycle on line 7 + 3 cycles on line 8 + 3 cycles on line 9 = 19 cycles. Therefore, compared to the case in Fig. 221(b), the total command size is reduced by 3 bytes, and the total execution cycles are also reduced by at least 4 cycles. In particular, in the example of FIG. 221(b), if the value of the B register in the command "DJNZ TABLESET10" is 2 or more, the total execution cycles increase by 10 cycles (4 cycles on line 6 + 3 cycles on line 7 + 3 cycles on line 8) multiplied by that value, so the reduction in the total execution cycles in FIG. 221(b) also increases. This TABLESET module makes it possible to further shorten commands and reduce the processing load, and ensure the capacity of the control area for performing game control processing.

In addition, unlike the example in FIG. 221, the A register and C register are not used here. Therefore, the values in the A register and C register will not be updated unintentionally. Also, in the example in FIG. 221, if the A register or C register was already in use, it was necessary to save the values in the A register and C register by stacking them, but here, since the A register and C register are not used, stack processing is not required. In this way, resources can be used efficiently.

In addition, as can be seen by comparing FIG. 221(b) with FIG. 223(b), the command group that occupies four lines (lines 5 to 8) in FIG. 221(b) can be represented by two lines (lines 5 and 6) in FIG. 223(b), making it possible to reduce the number of commands and lighten the design load.

<DECWMQ>
Fig. 224 is a flow chart showing the specific processing of the IPT_PC module. The IPT_PC module executes the time monitoring processing that is read out once every four times in step S3100-21 of the timer interrupt processing (see Fig. 98). The numerical values of step S in this figure are used only in the explanation of this figure.

The time monitoring process is a process that subtracts one from a timer (e.g., a timer for one game) that was set in various steps in Figures 82 to 98.

As shown in FIG. 224(a), the main CPU 500a reads the address where the timer is stored into the HL register (S1), then executes the WORDDEC module shown in FIG. 224(b) (S2) and subtracts 1 from the value of the address shown in the HL register (S3). Then, the WORDDEC module is terminated by the command "RET" to return to the IPT_PC module (S4).

Figure 225 is an explanatory diagram for explaining an example of a command for implementing the IPT_PC module. The flowchart shown in Figure 224 is implemented, for example, by the program shown in Figure 225. Note that Figure 225 explains, as an example, the process of decrementing the timer between one play.

The index "IPT_PC:" on the first line of Figure 225(a) indicates the starting address of the IPT_PC module. The command "LDQ HL, (LOW _GAM_TMR)" on the second line of Figure 225(a) reads the value of the Q register into the H register, and reads the value of the lowest byte of the address "_GAM_TMR" into the L register. This command on the second line corresponds to step S1 in Figure 224(a).

Then, the command "CALLF WORDDEC" on the third line of FIG. 225(a) calls the WORDDEC module shown in FIG. 225(b). The command on the second line corresponds to step S2 in FIG. 224(a).

The index "WORDDEC:" on the first line of FIG. 225(b) indicates the starting address of the WORDDEC module. The command "DCPWLD (HL), 0" on the second line of FIG. 225(b) reads out a 2-byte value (one game timer) stored in the address indicated by the HL register (more precisely, the address indicated by the HL register and the next address), and subtracts (updates) 1 from the read value. If the carry flag is set to 1 by the subtraction, that is, if the read value is 0 (a specified value), a fixed value "0 (specific value)" is stored in the address indicated by the HL register (more precisely, the address indicated by the HL register and the next address). On the other hand, if the carry flag is not set to 1, that is, if the read value is 1 or more, the subtracted value is stored in the address indicated by the HL register (more precisely, the address indicated by the HL register and the next address). The command on the second line corresponds to step S3 in Figure 224 (b).

Then, the command "RET" on the third line of FIG. 225(b) ends the WORDDEC module and returns to the IPT_PC module. This command on the third line corresponds to step S4 of FIG. 224(b). In this way, it becomes possible to decrement the 2-byte value (inter-game timer) stored at the address indicated by the HL register by 1 for each processing until it becomes 0.

The command group in Fig. 225(a) and Fig. 225(b) can be changed to that in Fig. 225(c). Here, we will omit the explanation of the processes that are essentially the same as Fig. 225(a) and Fig. 225(b), and only explain the different processes in Fig. 225(c).

The command "DECWMQ (LOW _GAM_TMR)" on the second line of Figure 225 (c) sets the value of the Q register to the most significant byte of the address, sets the value of the least significant byte of the address "_GAM_TMR" to the most significant byte of the address, and reads out the value stored at that address. Then, 1 is subtracted (decremented) from the value read, and if the carry flag is set to 1 after the subtraction, i.e., if the value read is 0, a fixed value of "0" is stored in that address. On the other hand, if the carry flag is not set to 1, i.e., if the value read is 1 or greater, the subtracted value is stored in that address.

The total command size of the command group shown in Fig. 225(a) and Fig. 225(b) is 2 bytes of the command "LDQ A, (LOW_GAM_TMR)" on the second line of Fig. 225(a) + 2 bytes of the command "CALLF WORDDEC" on the third line of Fig. 225(a) + 4 bytes of the command "DCPWLD (HL), 0" on the second line of Fig. 225(b) + 1 byte of the command "RET" on the third line of Fig. 225(b) = 9 bytes, and the total execution cycles are 2 cycles on the second line of Fig. 225(a) + 4 cycles on the third line of Fig. 225(a) + 9 cycles on the second line of Fig. 225(b) + 3 cycles on the third line of Fig. 225(b) = 18 cycles.

On the other hand, the total command size of the command group shown in FIG. 225(c) is the command "DECWMQ (LOW_GAM_TMR)" on the second line, which is 3 bytes = 3 bytes, and the total execution cycles are 8 cycles on the second line = 8 cycles.

Therefore, by replacing the command groups in Fig. 225(a) and Fig. 225(b) with the command group in Fig. 225(c), the total command size is reduced by 6 bytes, and the total execution cycles are also reduced by 10 cycles. This replacement shortens the commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 225(a) and 225(c), a group of commands that occupy two lines (lines 2 and 3) in Figure 225(a) can be represented in one line (line 2) in Figure 225(c), making it possible to reduce the number of commands and lighten the design load.

In the example of Figure 225 (c), the WORDDEC module can also be deleted, freeing up valuable space for general-purpose modules, allowing other modules to be placed in that space. This allows for more efficient use of resources.

<RIBIT>
Fig. 226 is a flow chart showing the specific processing of the CMDPROC module. The CMDPROC module executes the subcommand transmission processing (see step S3100-11 in Fig. 98). The numerical values of step S in this figure are used only in the explanation of this figure.

As shown in FIG. 226, the main CPU 500a acquires the value of the interrupt wait monitor register (S1). Here, the interrupt wait monitor register is composed of one byte, and a power-off warning signal is input to the sixth bit. When the power supply voltage of the slot machine 400 falls below a predetermined value, a power-off warning signal is input and the sixth bit of the interrupt wait monitor register becomes 1, and otherwise it is 0.

The main CPU 500a refers to the sixth bit of the acquired interrupt wait monitor register to determine whether a power-off warning signal has been input, i.e., whether there is an external interrupt request (S2). If there is an external interrupt request (YES in S2), the CMDPROC module is terminated and the process returns to the routine one step above. If there is no external interrupt request (NO in S2), the process moves to the next process and sends a subcommand to the sub-control board 502.

Figure 227 is an explanatory diagram for explaining an example of a command for implementing the CMDPROC module. The flowchart shown in Figure 226 is implemented, for example, by the program shown in Figure 227.

The index "CMDPROC:" on the first line of Fig. 227(a) indicates the starting address of the CMDPROC module. The command "IN A, (@IRR_____)" on the second line of Fig. 227(a) sets the value of the U register to the most significant byte of the address, sets the fixed value "@IRR_____" indicating the least significant byte of the address of the interrupt wait monitor register to the least significant byte of the address, and reads the value stored at that address into the A register. This command on the second line corresponds to step S1 in Fig. 226.

Then, the command "RBIT NZ,6,A" on the third line of Fig. 227(a) causes the CMDPROC module to terminate and return to the routine one level higher, so that if the sixth bit of the value stored in the A register is not 0, i.e., if it is 1, the command "RET" is executed. On the other hand, if the sixth bit of the value stored in the A register is 0, processing moves to the next command. This command on the third line corresponds to step S2 in Fig. 226.

The commands in FIG. 227(a) can be changed to those in FIG. 227(b). Here, we will omit the explanation of the processes that are essentially the same as those in FIG. 227(a), and only explain the different processes in FIG. 227(b).

The command "RIBIT NZ,6,(@IRR_____)" on the second line of Fig. 227(b) sets the value of the U register to the upper byte of the address, sets the fixed value "@IRR_____" indicating the lower byte of the address of the interrupt wait monitor register to the lower byte of the address, and if the 6th bit of the value stored at that address is not 0, terminates the CMDPROC module and returns to the routine one level above to execute the command "RET". On the other hand, if the 6th bit of the value stored at that address is 0, processing moves to the next command.

The total command size of the command group shown in FIG. 227(a) is 2 bytes of the command "IN A, (@IRR____)" on line 2 + 2 bytes of the command "RBIT NZ, 6, A" on line 3 = 4 bytes, and the total execution cycles are 3 cycles on line 2 + 5 (3) cycles on line 3 = 8 (6) cycles. Note that the number of cycles in parentheses indicates the execution cycles if no movement is made by the command "RBIT NZ, 6, A".

On the other hand, the total command size of the command group shown in FIG. 227(b) is 3 bytes = 3 bytes for the command "RIBIT NZ,6,(@IRR____)" on line 2, and the total execution cycles are 7(5) cycles on line 2 = 7(5) cycles. Note that the number of cycles in parentheses indicates the execution cycles if no movement is made by the command "RIBIT NZ,6,(@IRR____)."

Therefore, by replacing the command group in FIG. 227(a) with the command group in FIG. 227(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. This replacement shortens the commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

Furthermore, in the example of FIG. 227(b), the A register used in FIG. 227(a) is not used. Therefore, the value of the A register will not be updated unintentionally. Also, in the example of FIG. 227(a), if the A register was already in use, it was necessary to save the value of the A register by stacking, but here, since the A register is not used, stack processing is not necessary. In this way, resources can be used efficiently.

In addition, as can be seen by comparing Figures 227(a) and 227(b), a group of commands that occupy two lines (lines 2 and 3) in Figure 227(a) can be represented in one line (line 2) in Figure 227(b), making it possible to reduce the number of commands and lighten the design load.

<AND+OR>
Fig. 228 is a flow chart showing the specific processing of the SET_PLS module. The SET_PLS module executes the excitation pattern update processing read out in the stepping motor control processing (see step S3100-13 in Fig. 98). The numerical values of step S in this figure are used only in the description of this figure.

As shown in FIG. 228, the main CPU 500a acquires the top address of the excitation pattern table in which the excitation pattern of the stepping motor 452 is stored (S1). The main CPU 500a adds, i.e., offsets, the offset value previously stored in the A register to the acquired top address of the excitation pattern table (S2).

Then, the main CPU 500a acquires the output image stored in a specified output port (S3) and masks the upper four bits of the acquired output image (S4). Note that the output image acquired here is 1 byte long, and the upper four bits indicate the excitation pattern of the stepping motor 452. Therefore, by masking the upper four bits of the output image, the excitation pattern is cleared.

Then, the main CPU 500a synthesizes the excitation pattern by taking the logical sum of the value indicated at the address offset in step S2 and the acquired output image (S5), updates the synthesized excitation pattern as the output image (S6), terminates the SET_PLS module, and returns to the routine one level above (S7).

Figure 229 is an explanatory diagram for explaining an example of a command for implementing the SET_PLS module. The flowchart shown in Figure 228 is implemented, for example, by the program shown in Figure 229.

The index "SET_PLS:" on the first line of FIG. 229(a) indicates the starting address of the SET_PLS module. Then, the command "LD HL, T_PLS_PTN" on the second line of FIG. 229(a) reads the address "T_PLS_PTN" of the excitation pattern table in which the excitation pattern of the stepping motor 452 is stored into the HL register. This command on the second line corresponds to step S1 in FIG. 228.

Then, the command "ADDWB HL, A" on the third line of FIG. 229(a) adds the value of the A register (offset value) to the value of the HL register, updating the value of the HL register. This command on the third line corresponds to step S2 in FIG. 228.

Then, the value (output image) stored in the output port address "IY+@OFS_OUT_PRT" is read into the A register by the command "LD A, (IY+@OFS_OUT_PRT)" on the fourth line of Figure 229(a). This command on the fourth line corresponds to step S3 in Figure 228.

Next, the command "AND A,00001111B" on line 5 of Fig. 229(a) calculates the logical product of the value of the A register (output image) and the fixed value "00001111B" (first value) (the upper 4 bits are masked), and stores the result in the A register. This command on line 5 corresponds to step S4 in Fig. 228.

Then, the command "OR A, (HL)" on line 6 of FIG. 229(a) calculates the logical sum of the value of the A register (masked output image) and the value stored at the address indicated by the HL register (excitation pattern, second value), and stores the calculation result in the A register. This command on line 6 corresponds to step S5 in FIG. 228.

After that, the command "LD (IY+@OFS_OUT_PRT), A" on line 7 of Fig. 229(a) stores the value of the A register in the output port address "IY+@OFS_OUT_PRT". This command on line 7 corresponds to step S6 in Fig. 228. Then, the command "RET" on line 8 of Fig. 229(a) ends the SET_PLS module and returns to the routine one level above. This command on line 8 corresponds to step S7 in Fig. 228.

The commands in FIG. 229(a) can be changed to those in FIG. 229(b). Here, we will omit the explanation of the processes that are essentially the same as those in FIG. 229(a), and only explain the different processes in FIG. 229(b).

The command "RST CALADRS" on the third line of Fig. 229(b) calls the CALADRS module shown in Fig. 229(c). The index "CALADRS:" on the first line of Fig. 229(c) indicates the starting address of the CALADRS module. The command "ADDWB HL, A" on the second line of Fig. 229(c) adds the value of the A register (offset value) to the value of the HL register, updating the value of the HL register. The command "LD A, (HL)" on the third line reads a one-byte value stored at the address indicated by the HL register into the A register. The command "RET" on the fourth line of Fig. 229(c) ends the CALADRS module and returns to the SET_PLS module.

Then, the command "AND (IY+@OFS_OUT_PRT), 00001111B" on the fourth line of Figure 229(b) calculates the logical product of the value (output image) stored at address "IY+@OFS_OUT_PRT" and the fixed value "00001111B" (the upper 4 bits are masked), and the result of the calculation is stored at address "IY+@OFS_OUT_PRT".

Then, the command "OR (IY+@OFS_OUT_PRT), A" on the fifth line of Figure 229(b) calculates the logical sum of the value stored in address "IY+@OFS_OUT_PRT" (masked output image) and the value of the A register (excitation pattern), and stores the result of the calculation in address "IY+@OFS_OUT_PRT".

The total command size of the command group shown in FIG. 229(a) is 3 bytes of the command "LD HL, T_PLS_PTN" on line 2 + 1 byte of the command "ADDWB HL, A" on line 3 + 3 bytes of the command "LD A, (IY + @OFS_OUT_PRT)" on line 4 + 2 bytes of the command "AND A, 00001111B" on line 5 + 1 byte of the command "OR A, (HL)" on line 6 + 3 bytes of the command "LD (IY + @OFS_OUT_PRT), A" on line 7 + 1 byte of the command "RET" on line 8 = 14 bytes, and the total execution cycles are 3 cycles on line 2 + 1 cycle on line 3 + 4 cycles on line 4 + 2 cycles on line 5 + 2 cycles on line 6 + 4 cycles on line 7 + 3 cycles on line 8 = 19 cycles.

On the other hand, the total command size of the command group shown in FIG. 229(b) is 3 bytes of the command "LD HL, T_PLS_PTN" on line 2 + 1 byte of the command "RST CALADRS" on line 3 + 4 bytes of the command "AND (IY + @OFS_OUT_PRT), 00001111B" on line 4 + 3 bytes of the command "OR (IY + @OFS_OUT_PRT), A" on line 5 + 1 byte of the command "RET" on line 6 = 12 bytes, and the total execution cycles are 3 cycles on line 2 + 4 cycles on line 3 + 7 cycles on line 4 + 6 cycles on line 5 + 3 cycles on line 6 = 23 cycles.

Therefore, by replacing the command group in FIG. 229(a) with the command group in FIG. 229(b), the total command size is reduced by 2 bytes. This replacement shortens the commands and makes it possible to secure the capacity of the control area for performing game control processing. Note that the CALADRS module, which is a general-purpose module, is read and executed by other modules and is not something that is newly added.

In addition, as can be seen by comparing Figures 229(a) and 229(b), the command group in Figure 229(b) can be reduced by two lines compared to the command group in Figure 229(a), making it possible to reduce the number of commands themselves and lighten the design load.

<CPLBQ>
230 is a flow chart showing the specific processing of the OTM_ATK module. The numerical values of step S in this figure are used only in the explanation of this figure.

Here, as another example of the slot machine 400, a so-called chance zone presentation state is provided. The chance zone presentation state is a state in which it is easier to win the AT lottery than the normal presentation state, and is transitioned over a specified number of games. For example, the chance zone presentation state transitions over eight games, and an AT lottery is held for each game. In addition, in this other example of the slot machine 400, the result of the AT lottery in each game in the chance zone presentation state is stored as 1 bit (win = 1, no win = 0), and all the results of the AT lottery are managed as win/lose information of a total of 8 bits (1 byte length).

The process of managing the results of such AT lotteries is executed by the OTM_ATK module. Note that the OTM_ATK module is called and executed in the execution flag setting process shown in step S2400-11 in FIG. 91 only when the AT lottery is won in each game.

As shown in FIG. 230, the main CPU 500a obtains the number of plays in the chance zone presentation state (S1) and obtains the address of the play count bit table (S2). In addition, in the play count bit table, bit information corresponding to the first play through the eighth play in the chance zone presentation state is consecutively arranged, as will be described in detail later, and each bit information is 1 byte long data in which the bit (1 bit information) corresponding to that play is 1 and the other bits are 0.

The main CPU 500a obtains bit information corresponding to the obtained number of plays from the number of plays bit table (S3), and obtains 1-byte long win/loss information (1-byte information) indicating the result of the AT lottery (S4). The main CPU 500a then updates (combines) the win/loss information by calculating the logical sum of the obtained bit information and the win/loss information (S5), and saves the updated win/loss information (S6). The OTM_ATK module is terminated and the process returns to the routine one step above (S7).

Figure 231 is an explanatory diagram for explaining an example of a command for implementing the OTM_ATK module. The flowchart shown in Figure 230 is implemented, for example, by the program shown in Figure 231.

The index "OTM_ATK:" on the first line of FIG. 231(a) indicates the starting address of the OTM_ATK module. The command "LDQ A, (LOW _CZ_CNT)" on the second line of FIG. 231(a) sets the value of the Q register to the most significant byte of the address, sets the value of the least significant byte of the address "_CZ_CNT" to the most significant byte of the address, and reads the value stored at that address (number of plays) into the A register. This command on the second line corresponds to step S1 in FIG. 230.

Then, the command "LD HL, T_XXX_XXX" on the third line of FIG. 231(a) reads the top address of the number of plays bit table "T_XXX_XXX" shown in FIG. 231(b) into the HL register. This command on the third line corresponds to step S2 in FIG. 230.

The index "T_XXX_XXX:" on the first line of FIG. 231(b) indicates the top address of the table "T_XXX_XXX". The value "00000001B" on the second line of FIG. 231(b) corresponds to the first play in the chance zone presentation state, with only the 0 bit being 1 and the other bits being 0. Similarly, the values on the third to ninth lines of FIG. 231(b) correspond to the second to eighth plays, respectively, in the chance zone presentation state, with the bit corresponding to that play being 1 and the other bits being 0.

The CALADRS module is called by the command "RST CALADRS" on the fourth line of Figure 231 (a). In the CALADRS module, the value of the A register (number of plays) is added to the value of the HL register, the value of the HL register is updated, and the value stored at the address indicated by the updated HL register (bit information corresponding to the number of plays) is read into the A register. This command on the fourth line corresponds to step S3 in Figure 230.

The command "LDQ B, (LOW _ATW_BIT)" on the fifth line of Fig. 231(a) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "_ATW_BIT" to the lower byte of the address, and reads the value stored at that address (win/lose information) into the B register. This command on the fifth line corresponds to step S4 in Fig. 230.

The command "OR A, B" on the sixth line of Figure 231(a) calculates the logical sum of the value of the A register (bit information corresponding to the number of plays) and the value of the B register (win/lose information). Here, when the AT lottery is won in the relevant game, the bit in the win/lose information corresponding to that number of plays becomes 1. This command on the sixth line corresponds to step S5 in Figure 230.

The command "LDQ (LOW _ATW_BIT), A" on line 7 of Figure 231(a) sets the value of the Q register to the upper byte of the address, sets the value of the lower byte of the address "_ATW_BIT" to the lower byte of the address, and stores the value of the A register (updated win/lose information) at that address. This command on line 7 corresponds to step S6 in Figure 230.

Then, the command "RET" on line 8 of FIG. 231(a) causes the OTM_ATK module to terminate and return to the routine one level above. This command on line 8 corresponds to step S7 of FIG. 230.

The command group in FIG. 231(a) can be changed to that in FIG. 231(c). Here, we will omit the explanation of the processing that is essentially the same as in FIG. 231(a), and only explain the different processing in FIG. 231(c).

The command "CPLBQ A, (LOW _ATW_BIT)" on the third line of Figure 231 (c) sets the value of the Q register to the most significant byte of the address, sets the value of the least significant byte of the address "_ATW_BIT" to the most significant byte of the address, and inverts the bit of the value (win/lose information) stored at that address that corresponds to the value of the A register (number of plays). Therefore, here, the bit of the win/lose information that corresponds to the play (number of plays) that resulted in a win in the AT lottery is inverted to 1.

The total command size of the command group shown in FIG. 231(a) is 2 bytes of the command "LDQ A, (LOW _CZ_CNT)" on the second line + 3 bytes of the command "LD HL, T_XXX_XXX" on the third line + 1 byte of the command "RST CALADRS" on the fourth line + 3 bytes of the command "LDQ B, (LOW _ATW_BIT)" on the fifth line + 1 byte of the command "OR A, B" on the sixth line + 2 bytes of the command "LDQ (LOW _ATW_BIT), A" on the seventh line + 1 byte of the command "RET" on the eighth line = 13 bytes, and the total execution cycles are 3 cycles on the second line + 3 cycles on the third line + 4 cycles on the fourth line + 4 cycles on the fifth line + 2 cycles on the sixth line + 3 cycles on the seventh line + 3 cycles on the eighth line = 22 cycles.

On the other hand, the total command size of the command group shown in FIG. 231(c) is 2 bytes of the command "LDQ A, (LOW _CZ_CNT)" on the second line + 3 bytes of the command "CPLBQ A, (LOW _ATW_BIT)" on the third line + 1 byte of the command "RET" on the fourth line = 6 bytes, and the total execution cycles are 3 cycles on the second line + 6 cycles on the third line + 3 cycles on the fourth line = 12 cycles.

Therefore, by replacing the command group in FIG. 231(a) with the command group in FIG. 231(c), the total command size is reduced by 7 bytes, and the total execution cycles are also reduced by at least 10 cycles. This replacement shortens the commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

In addition, as can be seen by comparing Figures 231(a) and 231(c), the command group that occupies five lines (lines 3 to 7) in Figure 231(a) can be represented in one line (line 3) in Figure 231(c), making it possible to reduce the number of commands and lighten the design load.

In addition, by replacing it with the command group in FIG. 231(c), the number of plays bit table becomes unnecessary, and the data volume for the number of plays bit table can also be reduced.

<LDSB>
FIG. 232 is an explanatory diagram illustrating an example of a command for implementing the KRS_JDG module.

As another example of the gaming machine 100, when a game ball enters a probability variable area (specific area) provided in the large prize opening during a specified round of play in a large prize game, the game state after the large prize game is set to a high probability game state. Then, in a large prize game in which a specified special pattern is determined, when a specified number of plays pass through the large prize opening during a specified round of play, the probability variable area is opened, allowing the game ball to enter the probability variable area. Below, an example will be described in which the probability variable area is opened when three game balls enter the large prize opening during the first round of play, and when five game balls enter the large prize opening during the fifth round of play.

The process of managing the opening of such a special probability area is executed by the KRS_JDG module. The KRS_JDG module is called and executed in the special prize opening control process shown in FIG. 47.

The index "KRS_JDG:" on the first line of FIG. 232(a) indicates the starting address of the KRS_JDG module. Then, the command "LDQ A, (LOW R_ROU_CNT)" on the second line of FIG. 232(a) sets the value of the Q register to the most significant byte of the address, sets the value of the least significant byte of the address "R_ROU_CNT" to the most significant byte of the address, and reads the value stored at that address (the number of consecutive operations of the special electric device, i.e., the number of rounds played) into the A register.

Then, the command "LD B, (HL)" on the third line of Figure 232 (a) reads the value of the address indicated by the value stored in the HL register into the B register. Note that the address of the probability change area determination table "D_KRS_JDG_2" shown in Figure 232 (b) has already been read into the HL register.

The index "D_KRS_JDG_2:" in the first line of FIG. 232(b) indicates the top address of the table "D_KRS_JDG_2". The value "(@D_KRS_JDG_2-D_KRS_JDG2-1)/2" in the second line of FIG. 232(b) is the value obtained by subtracting the address of the index "D_KRS_JDG_2:" in the first line and 1 from the address of the index "@D_KRS_JDG_2:" in the seventh line, and dividing the result by 2, and indicates the number of judgments (the number of rounds of play that open the probability change area).

The value "@KRS_TGT_ROU_01" on the third line of Figure 232(b) is a value indicating the first round of play that opens the special probability area (target round value, here, 1), and the value "@KRS_JDG_01" on the fourth line of Figure 232(b) is a value indicating how many game balls need to enter the large prize opening in the first round of play that opens the special probability area (opening identification value, here, 3). Similarly, the value "@KRS_TGT_ROU_03" on the fifth line of FIG. 232(b) is a value indicating the second round of play that opens the special probability area (target round value, here 5), and the value "@KRS_JDG_03" on the sixth line of FIG. 232(b) is a value indicating how many game balls must enter the large prize opening in the second round of play that opens the special probability area (opening identification value, here 5).

Therefore, the command "LD B, (HL)" on the third line of Figure 232 (a) causes the number of judgments to be read into the B register.

The index "KRS_JDG_10:" on the fourth line of Fig. 232(a) indicates the address of the index "KRS_JDG_10". The command "INC HL" on the fifth line of Fig. 232(a) increments the value of the HL register by 1. After that, the command "CP A, (HL)" on the sixth line of Fig. 232(a) compares the value of the A register with the value stored at the address indicated by the value of the HL register (target round value), and if the value of the A register is the same as the value of the HL register, the zero flag is set and the value is 1, and if it is different from the value of the HL register, the zero flag is not set and the value is 0.

Next, the command "INC HL" on line 7 of Fig. 232(a) increments the value of the HL register by 1 again. After that, the command "LD C, (HL)" on line 8 of Fig. 232(a) reads the value of the address indicated by the HL register (the release identification value) into the C register.

Then, the command "RET Z" on line 9 of Figure 232(a) will terminate the KRS_JDG module and return to the module above if the zero flag is set.

Also, if the zero flag is not set, the command "DJNZ KRS_JDG_10" on line 10 of Fig. 232(a) decrements the value of the B register (subtract "1"), and if the result of the decrement is not 0, it moves to address "KRS_JDG_10", and if the result of the decrement is 0, the command "RET" on line 11 of Fig. 232(a) terminates the KRS_JDG module and returns to the module above.

Here, in the gaming machine 100, the number of rounds is a maximum of 10. Also, the number of balls that enter the large prize slot to open the special prize area is set between 2 and 5, since the specified number for each round is 10. In other words, the target round value is a value of 10 or less, and can be expressed in 4 bits. Therefore, although the value "@KRS_TGT_ROU_01" and the value "@KRS_TGT_ROU_03" indicating the target round value are 1 byte long, in reality 4 bits will suffice.

The open identification value is a value of 5 or less and can be expressed in 3 bits. Therefore, the value "@KRS_JDG_01" and the value "@KRS_JDG_03" indicating the open identification value are 1 byte long, but in reality they can be expressed in 3 bits.

Below, we will explain an example in which two values, the target round value, which can be expressed in 4 bits, and the open identification value, which can be expressed in 3 bits, are treated as one value (data) of 1 byte length.

Figure 233 is an explanatory diagram for explaining another example of a command for implementing the KRS_JDG module. Note that an explanation of the processing that is essentially the same as in Figure 232 will be omitted, and only the different processing in Figure 233 will be explained.

The command "LD B, (HL)" on the third line of Figure 233(a) reads the value of the address indicated in the HL register into the B register. Note that the address of the probability change area determination table "D_KRS_JDG_2" shown in Figure 233(b) has already been read into the HL register.

The value "@KRS_TGT_ROU_01*8+@KRS_JDG_01" on the third line of FIG. 233(b) is a value (target round value) in which the top five bits indicate the first round of play that opens the special probability area, and the bottom three bits indicate a value (opening identification value) indicating how many game balls must enter the special probability area in the first round of play that opens the special probability area. Similarly, the value "@KRS_TGT_ROU_03*8+@KRS_JDG_03" on the fourth line of FIG. 233(b) is a value (target round value) in which the top five bits indicate the second round of play that opens the special probability area, and the bottom three bits indicate a value (opening identification value) indicating how many game balls must enter the special probability area in the second round of play that opens the special probability area.

The command "LDSB 2, DE, (HL)" on line 6 of Figure 233(a) reads the lowest 3 bits of the value of the HL register into the E register (the other bits are set to 0), and the highest 5 bits of the value of the HL register are shifted 3 bits to the right and read into the D register (the other bits are set to 0). In other words, the target round value and the release identification value are separated, the target round value is read into the D register, and the release identification value is read into the E register. Note that the "2" in the command "LDSB 2, DE, (HL)" is a value indicating that the 3 bits from bit 0 to bit 2 are read into the E register, and also a value indicating that the higher-order bits (5 bits) are shifted and read into the D register.

The command "CP A, D" on line 7 of Figure 233(a) compares the value of the A register with the value of the D register (target round value), and if the value of the A register is the same as the value of the D register, the zero flag is set and the value is 1, and if the value is different from the target round value, the zero flag is not set and the value is 0.

Here, the total command size of the command group shown in FIG. 232(a) is: 2 bytes of the command "LDQ A, (LOW R_ROU_CNT)" on the second line + 1 byte of the command "LD B, (HL)" on the third line + 1 byte of the command "INC HL" on the fifth line + 1 byte of the command "CP A, (HL)" on the sixth line + 1 byte of the command "INC HL" on the seventh line + 1 byte of the command "LD C, (HL)" on the eighth line + 1 byte of the command "RET Z" on the ninth line + 1 byte of the command "DJNZ" on the tenth line. 2 bytes of "KRS_JDG_10" + 1 byte of the command "RET" on line 11 = 11 bytes, and the total execution cycles are 3 cycles on line 2 + 2 cycles on line 3 + 1 cycle on line 5 + 2 cycles on line 6 + 1 cycle on line 7 + 1 cycle on line 8 + 3(1) cycles on line 9 + 3(2) cycles on line 10 + 3(1) cycles on line 11 = 19 (14) cycles. Also, the probability change area determination table shown in Figure 232 (b) is 5 bytes. Note that the number of cycles in parentheses indicates the execution cycles when no movement is made by a command.

On the other hand, the total command size of the command group shown in FIG. 233(a) is 2 bytes of the command "LDQ A, (LOW R_ROU_CNT)" on line 2 + 1 byte of the command "LD B, (HL)" on line 3 + 1 byte of the command "INC HL" on line 5 + 2 bytes of the command "LDSB 2, DE, (HL)" on line 6 + 1 byte of the command "CP A, D" on line 7 + 1 byte of the command "RET Z" on line 8 + 2 bytes of the command "DJNZ KRS_JDG_10" on line 9 + 1 byte of the command "RET" on line 10 = 11 bytes, and the total execution cycles are 3 cycles on line 2 + 2 cycles on line 3 + 1 cycle on line 5 + 3 cycles on line 6 + 1 cycle on line 7 + 3(1) cycles on line 8 + 3(2) cycles on line 9 + 3(1) cycles on line 10 = 19 (14) cycles. Also, the variable area determination table shown in FIG. 233(b) is 3 bytes. Note that the number of cycles in parentheses indicates the execution cycle when no movement is made by command.

Therefore, by replacing the command group in FIG. 232(a) and the probability change area determination table in FIG. 232(b) with the command group in FIG. 233(a) and the probability change area determination table in FIG. 233(b), the total size is reduced by 2 bytes. This replacement shortens the commands and reduces the processing load, making it possible to secure the capacity of the control area for performing game control processing.

The command "LDSB" can be used when two values (information) totaling 8 bytes or less are treated as one piece of data 1 byte long, and can be applied to cases other than the above example.

<Management of register banks and register groups>
As described with reference to FIG. 101, the register unit 716 of the CPU core 700 is provided with two register banks (a first register bank 726 and a second register bank 728) that can be exclusively switched and used. In addition, each of the first register bank 726 and the second register bank 728 is provided with two register groups (main register groups 726a, 728a and sub-register groups 726b, 728b) that can be exclusively switched and accessed, each of which includes 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY). Therefore, the register groups in which such a plurality of registers are common are present in four areas by combining the two register banks (the first register bank 726 and the second register bank 728) with the two register groups (the main register groups 726a, 728a and the sub-register groups 726b, 728b).

Such register groups are used exclusively between register banks and register groups, and can store information independently, so they are not affected by updates to registers in other areas. In other words, the main CPU 500a can update the contents of the registers in the currently targeted register bank and register group, but cannot access other register banks and register groups that are not the target.

In this way, by taking advantage of the fact that the register groups are independent between register banks and between register groups, it is considered to make each register group correspond to a plurality of programs that can be classified by type (purpose, function, trigger, etc.). For example, in the memory space of this embodiment, as shown in the memory map of FIG. 102, a used area and a separate area are allocated in the main ROM 500b and the main RAM 500c. As described above, the used area of the main ROM 500b stores programs and data for executing game control processing that controls the progress of the game, and the separate area of the main ROM 500b stores instruction codes and program data of programs that perform non-game control processing that does not affect the progress of the game. In this way, since the contents of the processing to be performed differ between the used area and the separate area, it is preferable to make each correspond to a different register group.

Therefore, in this embodiment, the first register bank 726 corresponds to the register group used to execute the game control process in the use area, and the second register bank 728 corresponds to the register group used to execute the game control non-processing in the other area. In other words, the first register bank 726 is used as the register group used to execute the game control process in the use area, and the second register bank 728 is used as the register group used to execute the game control non-processing in the other area. The main CPU 500a refers to the program stored in 0000h to 1FFFh of the main ROM 500b, updates the register group of the first register bank 726 to execute the game control process, and refers to the program stored in 2000h to 3FFFh of the main ROM 500b, switches the register bank, and updates the register group of the second register bank 728 to execute the game control non-processing. With this configuration, the independence and exclusivity between the use area and the other area can be guaranteed in both the memory and the register.

In this embodiment, the program executed in the game control process is divided into two. Here, for example, it is divided into main processing and timer interrupt processing. The main processing (first processing) is a processing that is executed sequentially according to the player's operation and the result thereof, including the main loop, as shown in, for example, Figures 22 to 25 (gaming machine 100) and Figures 82 to 97 (slot machine 400), and the timer interrupt processing (second processing) is a processing that is executed by temporarily interrupting the main processing in response to a timer interrupt every predetermined time (for example, 4 ms, 1.49 ms) that occurs during the execution of the main processing, as shown in, for example, Figures 26 to 59 (gaming machine 100) and Figure 98 (slot machine 400). Note that, here, the main processing is described as the first processing, but it is not limited to such a case, and any processing for progressing the game can be applied. Also, although timer interrupt processing has been described as the second process here, this is not limited to this case, and any process can be applied as long as it is executed by a predetermined interrupt that occurs based on the establishment of a predetermined condition in the progress of the game (a timing trigger, a timing trigger, an operation trigger, a trigger for executing a process, etc.).

In this embodiment, one of the two register groups 726a and 726b of the first register bank 726 corresponds to either the main processing or the timer interrupt processing, and the other of the two register groups 726a and 726b of the first register bank 726 corresponds to the other of the main processing and the timer interrupt processing. In other words, one of the two register groups 726a and 726b of the first register bank 726 is used as a register group used to execute either the main processing or the timer interrupt processing, and the other of the two register groups 726a and 726b of the first register bank 726 is used as a register group used to execute the other of the main processing and the timer interrupt processing. In the following, in the first embodiment, an example in which the main register group 726a corresponds to the main processing and the sub-register group 726b corresponds to the timer interrupt processing will be described, and in the second embodiment, an example in which the sub-register group 726b corresponds to the main processing and the main register group 726a corresponds to the timer interrupt processing will be described.

First Embodiment
Here, an example will be described in which the main register group 726a corresponds to the main processing, and the sub-register group 726b corresponds to the timer interrupt processing. Therefore, the main CPU 500a sequentially executes the main processing by referring to the main register group 726a, and when a timer interrupt occurs, it suspends the main processing, switches from the main register group 726a to the sub-register group 726b to execute the timer interrupt processing, and when the timer interrupt processing ends, switches from the sub-register group 726b to the main register group 726a to resume the main processing.

As mentioned above, this embodiment uses the Q register. The value written in the Q register is referenced as part of the address in any command. By using this Q register, it is possible to write commands that reference the Q register, making it possible to reduce the command size and number of cycles.

For example, regarding the load instruction "LD" that reads data from memory space, if the command "LD A, (mn)" is written into the program, the value stored in the 16-bit address mn can be read into the A register. This command has a command size of 3 bytes and a cycle count of 4 cycles. In contrast, if the command "LDQ A, (n)" that references the Q register is written into the program, the value stored in that address can be read into the A register with the value of the Q register as the upper byte of the address and address n as the lower byte of the address, and treated as a 16-bit address. This command has a command size of 2 bytes and a cycle count of 3 cycles. Therefore, it is possible to reduce both the command size and the cycle count.

As described above, the Q register is managed for each register group. That is, there is a Q register (first register) in the main register group (first register group) 726a and a Q' register (second register) in the sub-register group (second register group) 726b, and they hold values independently of each other.

Also, when the main CPU 500a including the register unit 716 is powered on, the Q register of the main register group 726a and the Q' register of the sub-register group 726b are set to initial values independently of each other. For example, when the power is turned on, the Q register of the main register group 726a is set to "F0h" (first value), which is the same as the value of the upper byte of 1 (e.g., F0h) among the values of multiple upper bytes (e.g., F0h to F3) in the address of the storage area of the main RAM 500c, and the Q' register of the sub-register group 726b is set to "F1h", which is the same as the value of the upper byte of 1 (e.g., F1h) among the values of multiple upper bytes (e.g., F0h to F3) in the address of the storage area of the main RAM 500c. This is based on the assumption that the memory areas referenced by the process using the main register group 726a and the process using the sub-register group 726b are separated.

However, in this embodiment, the main process using the main register group 726a and the timer interrupt process using the sub-register group 726b access variables associated with the same memory area. Therefore, if the Q register of the main register group 726a and the Q' register of the sub-register group 726b, which are referenced as the upper byte of the address, both hold the same value (e.g., F0h), the command size can be reduced by not requiring a command to adjust the address.

Therefore, in this embodiment, both the Q register of the main register group 726a and the Q' register of the sub-register group 726b are set to the same value (here, F0h). Note that since the initial value of the Q register of the main register group 726a is F0h (first value), there is no need to set another value. Therefore, here, only the Q' register of the sub-register group 726b is rewritten from F1h to F0h (second value). Note that the main CPU 500a needs to set a value in the Q' register before a command that references the Q' register is used. Therefore, for example, it is possible to initialize the Q' register during the initialization process of the main process (for example, the CPU initialization process in FIG. 82).

Figure 234 shows an example of a command to set a value in the Q' register. Here, the main CPU 500a sets F0h in the Q' register during the initialization process of the main process. However, as described above, the main CPU 500a can update the contents of the Q register in the main register group 726a, which is the currently targeted register group, but cannot access the Q' register in the sub-register group 726b, which is another register group. Therefore, as shown in Figure 234, the command "EX ALL" on the first line switches from the 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY) in the main register group 726a to the 8-bit registers (Q', A', F', B', C', D', E', H', L') and 16-bit registers (IX', IY') in the sub-register group 726b. Then, the command "LD Q,0F0H" on the second line sets F0h to the Q' register, and the command "EX ALL" on the third line switches from the sub-register group 726b to the main register group 726a.

The total command size of the example command shown in Figure 234 is 2 bytes of the command "EX ALL" on the first line + 1 byte of the command "LD Q,0F0H" on the second line + 2 bytes of the command "EX ALL" on the third line = 5 bytes, and the total execution cycles are 2 cycles on the first line + 1 cycle on the second line + 2 cycles on the third line = 5 cycles.

Note that, here, an example has been described in which the command "EX ALL" is used to switch between the Q register of the main register group 726a and the Q' register of the sub-register group 726b, but this is not the only case, and it is sufficient to switch between Q registers; for example, the command "EX Q, Q'" may be used. Note that the command size of the command "EX Q, Q'" is 2 bytes and the cycle is 2 cycles, so even if it is replaced with the command "EX ALL", the total command size and total execution cycles do not change.

There are many types of commands that refer to the Q' register, including the command "LDQ" shown above, and they are written repeatedly in a program. Therefore, the command size and the number of cycles can be reduced each time a command that refers to the Q' register is used. The frequency with which commands that refer to the Q' register are used increases, and the number of times the Q register is referenced. Therefore, the value of the Q' register should be set reliably. Therefore, instead of or in addition to setting the Q' register only once in the initialization process of the main process, it is also possible to set the Q' register repeatedly through the loop process of the main process. For example, the group of commands in FIG. 234 is set in any of FIG. 88 to FIG. 97 (slot machine 400). In this way, the Q' register can be set to F0h each time the loop process of the main process is executed, so that even if the Q' register becomes the initial value F1h, the value of the Q' register can be set to F0h reliably, and the value of the Q' register can be stably maintained.

However, since the Q' register is used for timer interrupt processing, set F0h in the Q' register before enabling the timer interrupt.

In addition to or instead of setting the Q' register once in the initialization process of the main process, or repeatedly in the loop process of the main process, it is also possible to repeatedly set the Q' register through timer interrupt processing. In this way, the Q' register can be set to F0h every time a timer interrupt occurs, so even if the Q' register is reset to its initial value F1h, the value of the Q' register can be reliably set to F0h, making it possible to stably maintain the value of the Q' register. Below, an example of repeatedly setting the Q' register through timer interrupt processing is described in detail.

Figure 235 shows an example of a command for setting a value in the Q' register. Here, we will first explain normal timer interrupt processing using Figure 235 (a) without mentioning the setting of the Q' register. Note that until the timer interrupt processing occurs (in the main processing), the main CPU 500a targets the main register group 726a. The index "TMR_IPT:" on the first line of Figure 235 (a) indicates the start address of the timer interrupt processing. The command "EX ALL" on the second line switches from the 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY) in the main register group 726a to the 8-bit registers (Q', A', F', B', C', D', E', H', L') and 16-bit registers (IX', IY') in the sub-register group 726b. Thus, the target becomes the sub-register group 726b. Then, after performing the necessary processing in the timer interrupt processing, the command "EX ALL" on line 5 switches from the sub-register group 726b to the main register group 726a. The command "EI" on line 6 allows interrupts. Note that here, even if the command "EI" is executed before returning from the subroutine to the main processing, interrupts are properly allowed. Then, the command "RETI" on line 7 returns to the main processing.

The total command size of the command shown in FIG. 235(a) is 2 bytes of the command "EX ALL" on line 2 + 2 bytes of the command "EX ALL" on line 5 + 1 byte of the command "EI" on line 6 + 2 bytes of the command "RETI" on line 7 = 7 bytes, and the total execution cycles are 2 cycles on line 2 + 2 cycles on line 5 + 1 cycle on line 6 + 4 cycles on line 7 = 9 cycles.

Now, write a command to set the Q' register at any timing in the timer interrupt processing of FIG. 235(a). When setting the Q' register in timer interrupt processing, as shown in FIG. 235(b), it is sufficient to write only the command "LD Q,0F0H" after the command "EX ALL". Note that in the case of timer interrupt processing, the command "EX ALL" is executed again at the end of the processing (line 5), and the main register group 726a is switched to.

The position of the command "LD Q, 0F0H" must precede the command that references the Q' register within the timer interrupt process. Therefore, as shown in Figure 235 (b), it is recommended to place it immediately after the command "EX ALL" on the second line. This can also be achieved by writing a command other than the command that references the Q' register after the command "EX ALL", and then writing the command that references the Q' register after the command "LD Q, 0F0H".

The total command size of the command shown in Fig. 235(b) is 2 bytes of the command "EX ALL" on line 2 + 1 byte of the command "LD Q,0F0H" on line 3 + 2 bytes of the command "EX ALL" on line 5 + 1 byte of the command "EI" on line 6 + 2 bytes of the command "RETI" on line 7 = 8 bytes, and the total execution cycles are 2 cycles on line 2 + 1 cycle on line 3 + 2 cycles on line 5 + 1 cycle on line 6 + 4 cycles on line 7 = 10 cycles. As can be seen by comparing Fig. 235(a) and Fig. 235(b), even if the setting of the Q' register is added, the increase in total command size is limited to 1 byte and total execution cycles is limited to 1 cycle.

As explained using FIG. 234, if the Q' register is set during the initialization process of the main process, a total command size of 5 bytes and a total execution cycle of 5 cycles are required. Similarly, if this is repeated through the loop process of the main process, a total command size of 5 bytes and a total execution cycle of 5 cycles are required. In contrast, if the Q' register is set during timer interrupt processing, the description of two "EX ALL" commands can be omitted, so the increase in total command size is limited to 1 byte and total execution cycle of 1 cycle. Therefore, if the Q' register is set only during timer interrupt processing, it is at least possible to suppress the increase in memory.

Second Embodiment
Next, an example in which the sub-register group 726b corresponds to the main processing and the main register group 726a corresponds to the timer interrupt processing will be described. Therefore, the main CPU 500a first switches from the main register group 726a to the sub-register group 726b, executes the main processing by referring to the sub-register group 726b, suspends the main processing when a timer interrupt occurs, temporarily switches from the sub-register group 726b to the main register group 726a and executes the timer interrupt processing, and when the timer interrupt processing ends, switches from the main register group 726a to the sub-register group 726b and resumes the main processing.

In addition, here too, since the Q register of the main register group 726a has an initial value of F0h, there is no need to set another value, and only the Q' register of the sub-register group 726b is rewritten to F0h. As mentioned above, it is necessary to set the Q' register before a command that references it is used. Therefore, for example, it is possible to initialize the Q' register during the initialization process of the main process (for example, the CPU initialization process in FIG. 82).

Figure 236 shows an example of a command to set a value in the Q' register. Here, the main CPU 500a sets F0h in the Q' register during the initialization process of the main process. However, as described above, the main CPU 500a can update the contents of the Q register in the main register group 726a, which is the currently targeted register group, but cannot access the Q' register in the sub-register group 726b, which is another register group. Therefore, as in Figure 234, the command "EX ALL" on the first line in Figure 236 switches from the 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY) in the main register group 726a to the 8-bit registers (Q', A', F', B', C', D', E', H', L') and 16-bit registers (IX', IY') in the sub-register group 726b.

Then, the command "LD Q,0F0H" on the second line sets F0h to the Q' register. From then on, the sub-register group 726b is referenced and the main processing is performed.

The total command size of the commands shown in Figure 236 is 2 bytes of the command "EX ALL" on the first line + 1 byte of the command "LD Q,0F0H" on the second line = 3 bytes, and the total execution cycles are 2 cycles on the first line + 1 cycle on the second line = 3 cycles.

As explained using FIG. 234, if the main register group 726a is associated with the main processing, the sub-register group 726b is associated with the timer interrupt processing, and the Q' register is set in the initialization processing of the main processing, then a total command size of 5 bytes and a total execution cycle of 5 cycles are required. Similarly, if the Q' register is repeatedly set through the loop processing of the main processing, a total command size of 5 bytes and a total execution cycle of 5 cycles are required. In contrast, if the sub-register group 726b is associated with the main processing, the main register group 726a is associated with the timer interrupt processing, and the Q' register is set in the initialization processing of the main processing, then the description of one "EX ALL" command can be omitted, so that the increase in the total command size and the total execution cycle can be suppressed to 3 bytes and 3 cycles, respectively.

As mentioned above, the Q' register is frequently used, so the value of the Q' register should be set reliably. Therefore, instead of or in addition to setting the Q' register only once in the initialization process of the main process, it is also possible to repeatedly set the Q' register through the loop process of the main process. For example, among the command group in FIG. 236, only the command "EX ALL" on the first line is set in the initialization process of the main process, and among the command group in FIG. 236, the command "LD Q,0F0H" on the second line is set in any of FIG. 88 to FIG. 97 (slot machine 400). In this way, the Q' register can be set to F0h every time according to the loop process of the main process, so that even if the Q' register becomes the initial value F1h, the value of the Q' register can be reliably set to F0h, and the value of the Q' register can be stably maintained.

However, since a command that references the Q' register is used in the main processing, the Q' register is set to F0h before the command that references the Q' register is used.

In addition to or instead of setting the Q' register once in the initialization process of the main process, or repeatedly in the loop process of the main process, it is also possible to repeatedly set the Q' register through timer interrupt processing. In this way, the Q' register can be set to F0h every time a timer interrupt occurs, so even if the Q' register ever becomes the initial value F1h, the value of the Q' register can be reliably set to F0h, making it possible to stably maintain the value of the Q' register.

Figure 237 shows an example of a command to set a value in the Q' register. Here, the Q' register is set in timer interrupt processing. Note that until timer interrupt processing occurs (in main processing), the main CPU 500a targets the sub-register group 726b. Specifically, the index "TMR_IPT:" on the first line of Figure 237 indicates the starting address of the timer interrupt processing. The command "LD Q,0F0H" on the second line sets F0h to the Q' register. Then, in order to save the values of the registers used in the main process, the 8-bit registers (Q', A', F', B', C', D', E', H', L') and 16-bit registers (IX', IY') in the sub-register group 726b are switched to the 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY) in the main register group 726a by the command "EX ALL" in the third line. Thus, the target becomes the main register group 726a. Next, after performing the necessary processing in the timer interrupt processing, the main register group 726a is switched to the sub-register group 726b by the command "EX ALL" in the fifth line. The interrupt is permitted by the command "EI" in the sixth line. Note that here, the interrupt is permitted appropriately even if the command "EI" is performed before returning from the subroutine to the main process. Then, the command "RETI" on line 7 returns to the main process.

The total command size of the commands shown in Figure 237 is 1 byte of the command "LD Q,0F0H" on line 2 + 2 bytes of the command "EX ALL" on line 3 + 2 bytes of the command "EX ALL" on line 5 + 1 byte of the command "EI" on line 6 + 2 bytes of the command "RETI" on line 7 = 8 bytes, and the total execution cycles are 1 cycle on line 2 + 2 cycles on line 3 + 2 cycles on line 5 + 1 cycle on line 6 + 4 cycles on line 7 = 10 cycles.

The command "LD Q,0F0H" must be placed before the command "EX ALL" is executed in the timer interrupt process. Therefore, it is recommended to place it immediately before the command "EX ALL" on the third line.

Here, the sub-register group 726b is associated with the main processing and the main register group 726a is associated with the timer interrupt processing, and the Q' register is set only once in the initialization processing of the main processing, or repeatedly through the loop processing of the main processing, or repeatedly through the timer interrupt processing. In either case, compared to the case where the main register group 726a is associated with the main processing and the sub-register group 726b is associated with the timer interrupt processing and the Q' register is set in the initialization processing of the main processing, the description of one command "EX ALL" can be omitted, so that the increase in the total command size = 3 bytes and the total execution cycle = 3 cycles is limited, and even if the Q' register becomes the initial value F1h, the value of the Q' register can be reliably set to F0h, and the value of the Q' register can be stably maintained.

<Switching between register groups>
However, when a timer interrupt occurs during execution of the main process, the registers continue to be used in the timer interrupt process, regardless of the value of the register at the time of the interrupt. Therefore, when a timer interrupt occurs, it is necessary to separately store the register contents at the time of the interrupt. For example, in order to smoothly resume the main process when returning from the timer interrupt process to the main process, the register contents at the time of the interrupt must be saved to the stack area of the main RAM 500c using a save command. However, the number of save commands increases according to the number of registers to be saved, which increases not only the command size but also the number of cycles.

In this embodiment, as described above, the command "EX ALL" switches between the 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY) in the main register group 726a and the 8-bit registers (Q', A', F', B', C', D', E', H', L') and 16-bit registers (IX', IY') in the sub-register group 726b. With this command, when switching between main processing and timer interrupt processing, the target register group can be saved at once, and the other saved register groups can be restored at once. The command size of this command "EX ALL" is limited to 2 bytes, and the number of cycles is only 2.

The command "CALLEX mn" and command "RETEX" switch between the first register bank 726 and the second register bank 728 for each register bank including the main register group 726a and the sub-register group 726b. These commands can save the target register bank at once and restore the other saved register banks at once. The command "CALLEX mn" can be suppressed to 2 bytes in command size and requires only 4 cycles if the address mn is limited to 2000h to 20FFh. The command "RETEX" can be suppressed to 2 bytes in command size and requires only 5 cycles. Below, such switching commands will be explained by applying them to the first and second embodiments.

Figure 238 is a diagram for explaining the transition of register banks and register groups. As described above, in the example (first embodiment) in which the main register group 726a corresponds to the main processing and the sub-register group 726b corresponds to the timer interrupt processing, the main CPU 500a sequentially executes the main processing by referring to the main register group 726a, and when a timer interrupt occurs, it interrupts the main processing, switches from the main register group 726a to the sub-register group 726b by the command "EX ALL" (1), executes the timer interrupt processing, and when the timer interrupt processing ends, switches from the sub-register group 726b to the main register group 726a by the command "EX ALL" (2), and resumes the main processing. In addition, at a predetermined timing in the game control process, the main CPU 500a switches from the first register bank 726 to the second register bank 728 (3) using the command "CALLEX mn" to execute the game control non-processing, and when the game control non-processing is completed, switches from the second register bank 728 to the first register bank 726 (4) using the command "RETEX" to resume the game control process.

In addition, in an example (second embodiment) in which the sub-register group 726b corresponds to the main processing and the main register group 726a corresponds to the timer interrupt processing, the main CPU 500a first switches from the main register group 726a to the sub-register group 726b (1) using the command "EX ALL", executes the main processing by referring to the sub-register group 726b, and when a timer interrupt occurs, suspends the main processing, temporarily switches from the sub-register group 726b to the main register group 726a using the command "EX ALL" (2), executes the timer interrupt processing, and when the timer interrupt processing is completed, switches from the main register group 726a to the sub-register group 726b using the command "EX ALL" (1), and resumes the main processing. In addition, at a predetermined timing in the game control process, the main CPU 500a switches from the first register bank 726 to the second register bank 728 (3) using the command "CALLEX mn" to execute the game control non-processing, and when the game control non-processing is completed, switches from the second register bank 728 to the first register bank 726 (4) using the command "RETEX" to resume the game control process.

In this way, for the two register banks, the first register bank 726 corresponds to the use area, the second register bank 728 corresponds to another area, one of the main register group 726a and the sub-register group 726b of the first register bank 726 corresponds to the main processing, and the other corresponds to the timer interrupt processing, thereby ensuring the independence and exclusivity of each area. In addition, by switching at least the entire register group as a whole using a switching command in addition to these switching, it is possible to reduce the command size and the number of cycles while ensuring the independence and exclusivity of each area. Note that here, as explained using FIG. 238, an example was given in which one of the main register group 726a and the sub-register group 726b of the first register bank 726 corresponds to the main processing, the other corresponds to the timer interrupt processing, and one or both of the main register group 728a and the sub-register group 728b of the second register bank 728 correspond to the processing outside game control, but for example, the register bank and the register group corresponding to the main processing, the timer interrupt processing, and the processing outside game control can be set arbitrarily. For example, one of the main register group 728a and the sub-register group 728b of the second register bank 728 may correspond to main processing and the other may correspond to timer interrupt processing, and one or both of the main register group 726a and the sub-register group 726b of the first register bank 726 may correspond to processing outside game control, or the main register group 726a of the first register bank 726 may correspond to main processing, the main register group 728a of the second register bank 728 may correspond to timer interrupt processing, and one or both of the sub-register group 726b of the first register bank 726 and the sub-register group 728b of the second register bank 728 may correspond to processing outside game control.

Next, a case where the power supply to the main CPU 500a is cut off will be described. When the power supply to the main CPU 500a is cut off while the main process is being executed, the main CPU 500a saves the register group of the register bank corresponding to the main process (the main register group 726a or the sub-register group 726b of the first register bank 726) to the stack area of the main RAM 500c through a command "PUSH" (for example, the command "PUSH ALL"), and then performs the power-off save process shown in FIG. 97, for example.

Here, the register group corresponding to the main processing (main register group 726a or sub-register group 726b) is saved, but the saving of the register group corresponding to the timer interrupt processing and the processing outside game control is omitted. In the register group corresponding to such timer interrupt processing, necessary information is set after the timer interrupt processing is started, that is, the contents of the register are not taken over from the main processing, but are only referenced within the timer interrupt processing, and when the timer interrupt processing ends, the contents of the register become unnecessary. Similarly, in the register group corresponding to the processing outside game control, necessary information is set after the processing outside game control is started, that is, the contents of the register are not taken over from the game control processing, but are only referenced within the processing outside game control, and when the processing outside game control ends, the contents of the register become unnecessary. Therefore, there is no problem if the register group corresponding to the timer interrupt processing and the processing outside game control is not saved.

In addition, if the power is cut off not during main processing but during timer interrupt processing or during non-game control processing, the processing is carried out as follows. Timer interrupt processing has priority over interrupts due to power cut. In other words, even if a power cut interrupt occurs during timer interrupt processing, the power cut evacuation processing is not executed immediately, but is executed only after the timer interrupt processing is completed. In other words, at the timing when the power cut evacuation processing starts, the timer interrupt processing is completed. Note that, as described above, the timer interrupt processing is only referenced within the timer interrupt processing, and when the timer interrupt processing ends, the contents of the register become unnecessary. Therefore, even if the power is cut off during timer interrupt processing, there is no need to save the contents of the register related to the timer interrupt processing at the timing when the power cut evacuation processing starts, so no problem occurs. Similarly, non-game control processing has priority over interrupts due to power cut. In other words, even if a power cut interrupt occurs during non-game control processing, the power cut evacuation processing is not executed immediately, but is executed only after the non-game control processing ends. In other words, the timer interrupt process is completed when the power-off save process starts. As described above, the game control non-process is only referenced within the game control non-process, and when the game control non-process ends, the contents of the register become unnecessary. Therefore, even if the power is cut off during game control non-process, there is no need to save the contents of the register related to the game control non-process when the power-off save process starts, so no problem occurs.

When the power is turned off, the information in the register bank and register group at the time of the power outage is erased. Then, when the power is restored after the power outage, the register bank and register group are set to their initial values, the first register bank 726 and its main register group 726a. Therefore, the first process executed when the power is restored is the main process, and the first register bank 726 and its main register group 726a correspond to this main process. In this way, after the power is restored, the main process is started. Here, the first register bank 726 and its main register group 726a are saved when the power is turned off, making it possible to execute the main process stably and reliably.

In the above embodiment, an example is described in which the first register group is the main register group, the first register is the Q register, the first value is F0h, the second register group is the sub-register group, the second register is the Q' register, and the second value is F0h. However, this is not limited to the above case, and the first register group may be the sub-register group, the first register is the Q' register, the first value is F1h, the second register group is the main register group, the second register is the Q register, and the second value is F1h. In this configuration, F1h is rewritten in the Q register of the main register group. In addition, in the above embodiment, an example is described in which the first register bank is the first register bank 726 and the second register bank is the second register bank 728. However, this is not limited to the above case, and the first register bank may be the second register bank 728 and the second register bank may be the first register bank 726.

<Register access method>
In the conventional microprocessor, the address space (memory space) to which the main ROM 500b and the main RAM 500c are assigned and the address space (I/O space) to which the input/output unit 704 (the device corresponding to the input/output unit 704) is assigned are managed independently. Here, the memory space to which the main ROM 500b and the main RAM 500c are assigned may be called a memory map, and the I/O space to which the input/output unit 704 is assigned may be called an I/O map.

Conventional microprocessors had to use dedicated instructions to access the memory space and the I/O space. For example, when a conventional microprocessor uses an instruction dedicated to the memory space of the main ROM 500b and the main RAM 500c, the memory request (MREQ) terminal becomes enabled, allowing access to the main ROM 500b and the main RAM 500c. Also, when a conventional microprocessor uses an instruction dedicated to the I/O space of the input/output unit 704, the I/O request (IORQ) terminal becomes enabled, allowing access to the input/output unit 704. Therefore, conventional microprocessors had to change the instruction to be used depending on whether the object to be accessed was the main ROM 500b, the main RAM 500c, or the input/output unit 704. Here, the access method provided for conventional microprocessors to access the input/output unit 704 (device) is called the I/O mapped I/O method. Using commands based on this I/O-mapped I/O method, the main CPU 500a can read information from the input/output unit 704 to a register, and write information from the register to the input/output unit 704.

However, as described above, in this embodiment, the address space of the input/output unit 704 is integrated with the address spaces of the main ROM 500b and the main RAM 500c, and the input/output unit 704 is assigned to FE00h to FFFFh in the memory space. Therefore, there is no concept of I/O space, and the main CPU 500a can access the input/output unit 704 assigned to FE00h to FFFFh in the memory space by using instructions dedicated to the memory space. Here, the access method provided for the main CPU (processor) 500a to access the main ROM (storage means) 500b and the main RAM (storage means) 500c is called the memory-mapped I/O method. With commands based on this memory-mapped I/O method, the main CPU 500a can read information from the input/output unit 704 to a register and write information from a register to the input/output unit 704.

In this way, in this embodiment, the main CPU 500a accesses the input/output unit 704 by the memory-mapped I/O method. On the other hand, from the viewpoint of versatility, such as being able to directly use programs of conventional microprocessors, in this embodiment, access by the I/O-mapped I/O method is also possible. Therefore, in addition to the memory-mapped I/O method, the main CPU 500a can access the input/output unit 704 by the I/O-mapped I/O method, treating a part of the memory space as an I/O space. Note that, although conventional microprocessors were also able to access the input/output unit 704 by the memory-mapped I/O method, whether to use the I/O-mapped I/O method or the memory-mapped I/O method had to be selected at the time of initial startup, and if the memory-mapped I/O method was selected, the I/O-mapped I/O method could not be used.

Figure 239 is an explanatory diagram for explaining the usage of the access method. The memory-mapped I/O method has the advantage that it can use a large number of commands (instructions), such as the LD command and the LDIR command, that are prepared for accessing the main ROM 500b and the main RAM 500c. On the other hand, the memory-mapped I/O method has the disadvantage that the command size is larger than that of the I/O-mapped I/O method when simply reading and writing to the input/output unit 704. On the other hand, the I/O-mapped I/O method has the advantage that the command size is smaller than that of the memory-mapped I/O method when simply reading and writing to the input/output unit 704. On the other hand, the I/O-mapped I/O method has the disadvantage that only limited commands (instructions), such as the IN command and the OUT command, that are prepared for accessing the input/output unit 704, can be used.

In a program, there are usually many simple reads and writes to the input/output unit 704, so it is possible to reduce the command size by using the I/O mapped I/O method rather than the memory mapped I/O method. For example, when reading a value stored at a specific address in the input/output unit 704 to the A register, if the memory mapped I/O method command "LD A, (mn)" (mn is a 2-byte integer) is used, a command size of 3 bytes is required, whereas if the I/O mapped I/O method command "IN A, (g)" (g is a 1-byte integer) is used, the command size is only 2 bytes. Therefore, the I/O mapped I/O method is usually used.

However, in some processes within a program, it may be possible to reduce the capacity of the control area required to perform game control processing by using memory-mapped I/O commands rather than I/O-mapped I/O commands. Specifically, the total command size may be smaller when accessing the same address of input/output unit 704 allocated to memory space with a memory-mapped I/O command such as an LD command than when accessing the same address with an I/O-mapped I/O command such as an IN command or an OUT command. Therefore, here, an appropriate access method that reduces the total command size is used depending on the content of the process.

Figure 240 is a flow chart for explaining an example of the subcommand transmission process, and Figure 241 is a diagram showing an example of a specific command for implementing the subcommand transmission process. Such subcommand transmission process is executed in step S100-65 of Figure 23 and step S3100-11 of Figure 98, as described above. In the subcommand transmission process, a command is transmitted to the sub-control boards 330 and 502 through a transmission buffer (FIFO). For the sake of convenience, an example is given in which the main CPU 500a executes the subcommand transmission process S3100-11, and processing related to the subcommand accumulated data that is not related to this embodiment is omitted. The numerical values of step S in the explanation of Figure 240 will be used only in the explanation of this figure.

Note that here, messages 1, 2, 3, and 4, which make up the 4-byte command message to be sent to the sub-control board 502, are set in the D register, E register, B register, and C register, respectively. However, depending on the command message to be sent, messages 2 to 4 may be set afterwards. Also, if messages have not been set for messages 3 and 4, predetermined values may be set for messages 3 and 4.

As shown in FIG. 240, first, the main CPU 500a saves the values of each register (S1) and determines whether or not telegrams 2 to 4 have already been set based on telegram 1 (S2). If telegrams 2 to 4 have already been set (YES in S2), the main CPU 500a proceeds to step S6. If telegrams 2 to 4 have not yet been set (NO in S2), the main CPU 500a sets the value obtained from the main RAM 500c to telegram 2 (S3) and determines whether telegrams 3 and 4 have already been set based on telegram 1 (S4). If telegrams 3 and 4 have already been set (YES in S4), the main CPU 500a proceeds to step S6. If telegrams 3 and 4 have not yet been set (NO in S4), the main CPU 500a sets predetermined values to telegrams 3 and 4 (S5).

The main CPU 500a then sets the destination address (S6), sets telegram 2 as the augend (S7), and disables interrupts (S8). The main CPU 500a outputs telegrams 1 to 4 (S9), calculates the checksums of telegrams 1 to 4 (S10), and also outputs the calculated checksum (S11). Finally, the main CPU 500a allows interrupts (S12), and restores the values of each register that had been saved (S13).

Specifically, the index "CMDPROC" on the first line of Figure 241 indicates the start address of the subcommand transmission process. The subcommand transmission process is called by this index "CMDPROC". The command "PUSH HL" on the second line saves the value of the HL register to the stack area, and the command "PUSH BC" on the third line saves the value of the BC register to the stack area. These commands on the second and third lines correspond to step S1 in Figure 240, which saves the register values.

The command "LD A,D" on line 4 of Fig. 241 sets the value of the D register, i.e., the value of telegram 1, in the A register, and the command "JCP C,A,0B0H,CMDPROC01" on line 5 compares the value of the A register with a fixed value "B0H", and if the result is less than B0H (if the carry flag is set), it moves to the index "CMDPROC01" on line 12. In this way, if the value of telegram 1 is less than B0H, the next process can be omitted and it can move to the index "CMDPROC01" on line 12. These commands on lines 4 and 5 correspond to step S2 in Fig. 240, which moves to step S6 if telegrams 2 to 4 have already been set.

The command "LDQ A, (E)" on line 6 of Fig. 241 sets the value of the Q register to the upper byte of the address, the value of the E register to the lower byte of the address, and the value of that byte stored in the memory area indicated by that address (telegram 2) is set in the A register, and the command "LD E, A" on line 7 sets the value of the A register, i.e., telegram 2, in the E register. These commands on lines 6 and 7 correspond to step S3 in Fig. 240, which sets telegram 2.

The command "JBIT Z,3,D,CMDPROC01" on line 8 of FIG. 241 moves to the index "CMDPROC01" on line 12 if bit 3 of the value of the D register (text 1) is 0 (if the zero flag is set). In this way, if bit 3 of text 1 is 0, the next process can be omitted and the program can move to the index "CMDPROC01" on line 12. This command on line 8 corresponds to step S4 in FIG. 240, which transitions to step S6 if texts 3 and 4 have already been set.

The command "IN HL, (@CID_____)" on line 9 of Fig. 241 sets the value of the U register as the upper byte of the address, and the symbol "@CID_____" itself (1 byte value) as the lower byte, and inputs the 2-byte value stored in the memory area indicated by that address to the HL register. Specifically, the 1-byte value stored in the memory area indicated by that address is input to the L register, and the 1-byte value stored in the memory area indicated by the address plus 1 is input to the H register. The command "LD B, H" on line 10 sets the value of the H register to the B register, and the command "LD C, L" on line 11 sets the value of the L register to the C register. These commands on lines 9 to 11 correspond to step S5 in Fig. 240, which sets telegrams 3 and 4.

Next, the command "LD H, C" on line 13 of Figure 241 sets the value of the C register to the H register. Here, the C register is freed for use with the OUT command by transferring message 4 stored in the C register to the H register. The command "LD C, @S1DT___" on line 14 sets the symbol "@S1DT___" itself to the C register. Note that the symbol "@S1DT___" indicates the transmission buffer (FIFO) of the asynchronous serial communication circuit dedicated to transmission. These commands on lines 13 and 14 correspond to step S6 in Figure 240, which sets the destination address.

The command "LD A, E" on line 15 of Fig. 241 sets the value of the E register (message 2) in the A register. This is because the value of the A register is used as the augend when calculating the checksum in step S10 of Fig. 240. This command on line 15 corresponds to step S7 of Fig. 240, which sets message 2 in the A register. Then, the command "DI" on line 16 disables interrupts. This command on line 16 corresponds to step S8 of Fig. 240.

The command "OUT (C), D" on line 17 of Figure 241 sets the value of the U register to the upper byte of the address, the value of the C register to the lower byte, and outputs the value of the D register (telegram 1) to the memory area indicated by that address. The command "OUT (C), A" on line 18 sets the value of the U register to the upper byte of the address, the value of the C register to the lower byte, and outputs the value of the A register (telegram 2) to the memory area indicated by that address. The command "OUT (C), B" on line 19 sets the value of the U register to the upper byte of the address, the value of the C register to the lower byte, and outputs the value of the B register (telegram 3) to the memory area indicated by that address. The command "OUT (C), H" on line 20 sets the value of the U register to the upper byte of the address, the value of the C register to the lower byte, and outputs the value of the H register (telegram 4) to the memory area indicated by that address. Here, data is output to the symbol "@S1DT___" itself (address value) in the order of D register, A register (E register), B register, and H register (C register), that is, in the order of messages 1, 2, 3, and 4. The commands on lines 17 to 20 correspond to step S9 in FIG. 240, which outputs messages 1 to 4.

The command "ADD A, D" on line 21 of Figure 241 adds the value in the D register (message 1) to the value in the A register (message 2), and the result is stored in the A register. The command "ADD A, B" on line 22 adds the value in the B register (message 3) to the value in the A register (checksum value), and the result is stored in the A register. The command "ADD A, H" on line 23 adds the value in the H register (message 4) to the value in the A register (checksum value), and the result is stored in the A register. These commands on lines 21 to 23 correspond to step S10 in Figure 240, which calculates the checksums of messages 1 to 4.

The command "OUT (C), A" on line 24 of Fig. 241 sets the value of the U register as the most significant byte of the address, the value of the C register as the least significant byte, and outputs the value of the A register (checksum value) to the memory area indicated by that address. In this way, a command message of 5 bytes in total, consisting of messages 1 to 4 and the checksum value, is output to the send buffer. This command on line 24 corresponds to step S11 in Fig. 240, which outputs the calculated checksum. Then, the command "EI" on line 25 allows an interrupt. This command on line 25 corresponds to step S12 in Fig. 240.

The command "POP BC" on line 26 of Fig. 241 restores the data saved in the stack area to the BC register, and the command "POP HL" on line 27 restores the data saved in the stack area to the HL register. These commands on lines 26 and 27 correspond to step S13 in Fig. 240, which restores the register values. Then, the command "RET" on line 28 returns to the process that called the call.

In Fig. 241, the subcommand transmission process in Fig. 240 is realized by an I/O mapped I/O method using an IN command and an OUT command. However, as mentioned above, in some processes of a program, the command size may be smaller if memory mapped I/O commands are used. Below, an example of applying the memory mapped I/O method to some processes is explained.

Figure 242 shows an example of another command for implementing the sub-command transmission process. Here, as in Figure 241, the four-byte messages 1, 2, 3, and 4 to be transmitted to the sub-control board 502 are set in the D register, E register, B register, and C register, respectively.

Comparing the command group in FIG. 241 with the command group in FIG. 242, there are differences in the command group indicated by (1) corresponding to step S5, and the command group indicated by (2) corresponding to steps S6 to S11. Here, we will focus on the command group in (1) and the command group in (2) to explain the difference in total command size.

For the command group (1), the command "LD BC, (@CID_____)" on line 9 of FIG. 242 sets the two-byte value stored in the memory area indicated by the symbol "@CID_____" to the BC register. Specifically, the one-byte value stored in the memory area indicated by the symbol "@CID_____" is input to the C register, and the one-byte value stored in the memory area indicated by the symbol "@CID_____" + 1 is input to the B register. This command on line 9 corresponds to step S5 in FIG. 240, which sets telegrams 3 and 4.

In the example of FIG. 241, the I/O mapped I/O method is used, so the HL register can be selected as the setting destination for the value input by the IN command, but the BC register cannot be selected. In other words, the command "IN BC, (mn)" (mn is a 2-byte integer) is not prepared as a command. Therefore, in the example of FIG. 241, the 2-byte value stored in the memory area indicated by the symbol "@CID_____" must be temporarily held in the HL register, and then transferred to the B register and C register, respectively. In contrast, in the memory mapped I/O method of FIG. 242, the LD command can be used to directly set the 2-byte value stored in the memory area indicated by the symbol "@CID_____" in the BC register.

Here, the total command size of the command group in Figure 241 (1) is 3 bytes for the command "IN HL, (@CID_____)" on line 9 + 1 byte for the command "LD B,H" on line 10 + 1 byte for the command "LD C,L" on line 11 = 5 bytes, whereas the total command size of the command group (command) in Figure 242 (1) is 4 bytes for the command "LD BC, (@CID_____)" on line 9. Therefore, it can be seen that the total command size can be reduced by 1 byte by changing from the I/O mapped I/O method to the memory mapped I/O method.

Next, for the command group (2), the 2-byte value of the symbol "@S2DT" itself is set in the HL register by the command "LD HL, @S2DT" on line 11 of FIG. 242. The symbol "@S2DT" indicates the input buffer of the asynchronous serial communication circuit dedicated to transmission. The command on line 11 corresponds to step S6 in FIG. 240, which sets the destination address. In the example of FIG. 241, since the I/O mapped I/O method is used, the C register had to be released in order to use the OUT command. In contrast, with the memory mapped I/O method, there is no need to release the C register, and the destination address can be held in the HL register. Therefore, in the example of FIG. 242, the command "LD H, C" on line 13 of FIG. 241 can be deleted.

The command "LD A, E" on line 12 of Fig. 242 sets the value of the E register (message 2) in the A register. This command on line 12 corresponds to step S7 in Fig. 240, which sets message 2 in the A register. Then, the command "DI" on line 13 inhibits interrupts. This command on line 13 corresponds to step S8 in Fig. 240.

The command "LD (HL), D" on line 14 of FIG. 242 stores the value of the D register (message 1) in the memory area indicated by the address of the HL register. The command "LD (HL), A" on line 15 stores the value of the A register (message 2) in the memory area indicated by the address of the HL register. The command "LD (HL), B" on line 16 stores the value of the B register (message 3) in the memory area indicated by the address of the HL register. The command "LD (HL), C" on line 17 stores the value of the C register (message 4) in the memory area indicated by the address of the HL register. Here, the symbol "@S1DT____" itself (address value) stores data in the order of the D register, A register (E register), B register, and C register, that is, in the order of messages 1, 2, 3, and 4, and as a result, the data is output to the send buffer in the order of messages 1, 2, 3, and 4. The commands on lines 14 to 17 correspond to step S9 in FIG. 240, which outputs messages 1 to 4.

The command "ADD A, D" on line 18 of Figure 242 adds the value in the D register (message 1) to the value in the A register (message 2), and the result is stored in the A register. The command "ADD A, B" on line 19 adds the value in the B register (message 3) to the value in the A register (checksum value), and the result is stored in the A register. The command "ADD A, C" on line 20 adds the value in the C register (message 4) to the value in the A register (checksum value), and the result is stored in the A register. These commands on lines 18 to 20 correspond to step S10 in Figure 240, which calculates the checksums of messages 1 to 4.

The command "LD (HL), A" on line 21 of Figure 242 stores the value of the A register (checksum value) in the memory area indicated by the address of the HL register. In this way, a command message of 5 bytes in total, consisting of messages 1 to 4 and the checksum value, is stored in the transmission buffer, and as a result, the command message is output to the transmission buffer. This command on line 21 corresponds to step S11 in Figure 240, which outputs the calculated checksum.

In the example of FIG. 241, the I/O mapped I/O method uses the OUT command to output to the input/output unit 704. In contrast, the memory mapped I/O method can use the LD command. Therefore, it is possible to reduce the command size by holding the destination address in the HL register instead of the C register, and storing the values of each register in the memory area indicated by the address in the HL register using the LD command.

Here, the total command size of the command group in (2) of Figure 241 is 1 byte of the command "LD H, C" on the 13th line + 2 bytes of the command "LD C, @S1DT___" on the 14th line + 1 byte of the command "LD A, E" on the 15th line + 1 byte of the command "DI" on the 16th line + 2 bytes of the command "OUT (C), D" on the 17th line + 2 bytes of the command "OUT (C), A" on the 18th line + 2 bytes of the command "OUT (C), B" on the 19th line + 2 bytes of the command "OUT (C), H" on the 20th line + 1 byte of the command "ADD A, D" on the 21st line + 1 byte of the command "ADD A, B" on the 22nd line + 1 byte of the command "ADD A, H" on the 23rd line + 1 byte of the command "OUT 2 bytes for "LD HL, @S2DT___" on line 11 + 1 byte for "LD A, E" on line 12 + 1 byte for "DI" on line 13 + 1 byte for "LD (HL), D" on line 14 + 1 byte for "LD (HL), A" on line 15 + 1 byte for "LD (HL), B" on line 16 + 1 byte for "LD (HL), C" on line 17 + 1 byte for "ADD A, D" on line 18 + 1 byte for "ADD A, B" on line 19 + 1 byte for "ADD A, C" on line 20 + 1 byte for "LD (HL), A" on line 21 = 13 bytes.

Therefore, for the command group (2), the total command size can be reduced by 5 bytes by changing the I/O mapped I/O method to the memory mapped I/O method. As can be seen by comparing the command group (2) in FIG. 241 with the command group (2) in FIG. 242, the total command size can be reduced by 1 byte each time an OUT instruction is replaced with an LD instruction.

In this way, in this embodiment, while the input/output unit 704 is accessed using the I/O mapped I/O method, depending on the content of the processing, the input/output unit 704 is accessed using the memory mapped I/O method, which reduces the total command size. In this way, by mixing the I/O mapped I/O method and the memory mapped I/O method in the same program and applying an access method that reduces the total command size depending on the content of the processing, it is possible to shorten commands and ensure the capacity of the control area for performing game control processing.

<Memory Mapped I/O Method Usage Example 1>
As described above, in conventional microprocessors, the I/O unit 704 is accessed using the I/O mapped I/O method. In this case, the I/O space to which the I/O unit 704 can be allocated is limited to 256 bytes. In other words, in conventional microprocessors, the I/O unit 704 can be specified by only one byte of address information.

Figure 243 shows some of the commands for implementing the CPU initialization process, and Figure 244 shows a table referenced in the CPU initialization process. For ease of explanation, the initial setting process (step S100-1 in Figure 22 and step S2000-1 in Figure 82) of the CPU initialization process described above will be explained here. In the initial setting process, the input/output unit 704 is initialized by setting setting data in the input/output unit 704 (built-in register). Note that here, an example is given in which the main CPU 500a executes the initial setting process S2000-1.

The command "LD HL, T_CPU_REG" on the first line of Figure 243 sets the top address "T_CPU_REG" of the data group in the CPU built-in register setting data table from which data is read in the HL register. The command "LD B, @NUM_CPU_REG" on the second line sets the symbol "@NUM_CPU_REG" itself in the B register.

As can be seen by referring to the 48th row of the CPU internal register setting data table in FIG. 244, the symbol "@NUM_CPU_REG" contains the command "EQU ($-T_CPU_REG)/2". Here, "$" is the address next to the final address of the source data group, i.e., the symbol "@NUM_CPU_REG" itself, and "T_CPU_REG" is the first address of the source data group, so the value of $-T_CPU_REG (a 1-byte value indicating the number of data) is the total number of bytes of the 1-byte value, and the number of set data is derived by dividing this value by 2, which is the number of combinations of addresses and values. For example, in the example in FIG. 244, the number of set data is 30/2=15.

The index "INITIAL01" on the third line of Figure 243 indicates the start address of the repeat process. The command "LDIN AC, (HL)" on the fourth line stores a byte value stored in the memory area indicated by the address of the HL register in the C register, and stores a byte value stored in the memory area indicated by the address obtained by adding "1" to the HL register in the A register. The command "OUT (C), A" on the fifth line outputs the value of the A register (setting data) to the memory area (built-in register) indicated by the address of the C register.

For example, if the HL register is the value of address "T_CPU_REG", the 1-byte value "@PT0PR___" on the third line of FIG. 244 is stored in the C register, and the 1-byte value "160" on the fourth line of FIG. 244 is stored in the A register. Then, the value of the A register, "160", is output to the memory area indicated by the C register symbol "@PT0PR___".

Next, the command "DJNZ INITIAL01" on line 6 of Figure 243 decrements the value of the B register (subtracts "1"), and if the result of the decrement is not 0, it moves to the index "INITIAL01" on line 3, and if the result of the decrement is 0, it moves to the next command after that command. In this case, the number of data items is "15", so if the process from the index "INITIAL01" is repeated 15 times, the value of the B register will become 0.

Thus, the total command size of the commands in the initial setting process shown in Figure 243 is 3 bytes for the command "LD HL, T_CPU_REG" on the first line + 2 bytes for the command "LD B, @NUM_CPU_REG" on the second line + 2 bytes for the command "LDIN AC, (HL)" on the fourth line + 2 bytes for the command "OUT (C), A" on the fifth line + 2 bytes for the command "DJNZ INITIAL01" on the sixth line = 11 bytes.

As described above, in this embodiment, the address space of the input/output unit 704 is integrated with the address space of the main ROM 500b and the main RAM 500c. Therefore, the main CPU 500a accesses the input/output unit 704 through the addresses FE00h to FFFFh in the memory space. In this case, the memory space to which the input/output unit 704 can be assigned is 512 bytes. By increasing the memory space in this way, the number of input/output units 704 that can be assigned can also be increased. On the other hand, since the memory space becomes larger than 256 bytes, 2 bytes are required as an address to specify the input/output unit 704. For example, in this embodiment, some of the input/output units 704 are assigned in advance to the 256-byte area of the memory space FE00h to FEFFh, and other input/output units 704 are assigned to the 256-byte area of the memory space FF00h to FFFFh. Therefore, each time the main CPU 500a accesses an I/O unit 704 with a different upper byte of the address, it must change the value of the U register between "FEH" and "FFH." Here, we will explain another embodiment in which the initial setting process shown in FIG. 243 is realized using the U register.

Figure 245 shows another example of part of the command group for realizing CPU initialization processing, and Figure 246 shows another example of a table referenced in CPU initialization processing. Here, as in Figures 243 and 244, for the sake of convenience, the main CPU 500a sets configuration data in the input/output unit 704 (built-in register) using the I/O mapped I/O method.

The command "LDF HL, T_CPU_REG" on the first line of Fig. 245 sets the top address "T_CPU_REG" of the data group in the CPU built-in register setting data table of Fig. 246 in the HL register. The command "LD B, @NUM_CPU_RG1" on the second line sets the symbol "@NUM_CPU_RG1" itself in the B register.

As can be seen by referring to the 42nd row of the CPU internal register setting data table in FIG. 246, the symbol "@NUM_CPU_RG1" contains the command "EQU ($-T_CPU_REG)/2". Here, "$" is the symbol "@NUM_CPU_RG1" itself, and "T_CPU_REG" is the first address of the data group that is the transfer source, so the value of $-T_CPU_REG is the total number of bytes of the 1-byte value indicating the number of data, and by dividing this value by 2, which is the number of combinations of addresses and values, the number of set data is derived. For example, in the example in FIG. 246, the number of set data is 26/2=13.

The command "LD U,0FEH" on the third line of FIG. 245 sets "FEH" in the U register, which is the upper byte of the address indicating the input/output unit 704. Here, two values "FEH" and "FFH" are prepared as the upper addresses of the addresses indicating the multiple input/output units 704, and the main CPU 500a changes the value of the U register, which is the upper byte, each time depending on the input/output unit 704 to be accessed. The initial value of the U register is "FFH". Here, first "FEH" is set in the U register (changing "FFH" to "FEH"), and setting data is set for the input/output unit 704 whose upper address is "FEH".

The index "INITIAL01" on the fourth line of Figure 245 indicates the start address of the repeat process. The command "LDIN AC, (HL)" on the fifth line stores the value stored in the memory area indicated by the address of the HL register in the C register, and stores the value stored in the memory area indicated by the address obtained by adding "1" to the value of the HL register in the A register. The command "OUT (C), A" on the sixth line outputs the value of the A register (setting data) to the memory area (built-in register) indicated by the address of the C register.

For example, if the HL register is the value of address "T_CPU_REG", the 1-byte value "@PT0PR___" (e.g., "01H") on the third line of FIG. 246 is stored in the C register, and the 1-byte value "160" on the fourth line of FIG. 246 is stored in the A register. Then, the value of the A register, "160", is output to the memory area indicated by the C register symbol "@PT0PR___".

The command "DJNZ INITIAL01" on line 7 of Figure 245 decrements the value of the B register (subtracts "1"), and if the result of the decrement is not 0, it moves to the index "INITIAL01" on line 4, and if the result of the decrement is 0, it moves to the next command after that command. In this case, the number of data items is "13", so the value of the B register becomes 0 after repeating the process from the index "INITIAL01" 13 times. In this way, the setting of the configuration data for the 13 input/output units 704 in the first row of Figure 246 is completed.

The command "LD U, 0FFH" on line 8 of FIG. 245 sets "FFH" in the U register, which is the upper byte of the address indicating the input/output unit 704. As described above, of the two values "FEH" and "FFH" that indicate the address of the input/output unit 704, setting of the configuration data for the input/output unit 704 whose upper address is "FEH" has been completed, so here, "FFH" is set in the U register, and configuration data is set for the input/output unit 704 whose upper address is "FFH". Note that setting "FFH" in the U register resets the U register to its initial value.

The command "LD B, @NUM_CPU_RG2" on line 9 of Figure 245 sets the symbol "@NUM_CPU_RG2" itself in the B register. As can be understood by referring to line 50 of the CPU built-in register setting data table in Figure 246, the command "EQU ($-T_CPU_REG)/2-@NUM_CPU_RG1" is written in the symbol "@NUM_CPU_RG2". Here, "$" is the symbol "@NUM_CPU_RG2" itself, and "T_CPU_REG" is the first address of the 1-byte data group that is the transfer source, so the value of $-T_CPU_REG is 30/2=15, and "@NUM_CPU_RG1" is 13, so in the example of Figure 246, the number of set data is 15-13=2.

The index "INITIAL02" on line 10 of Figure 245 indicates the start address of the repeat process. The command "LDIN AC, (HL)" on line 11 stores the value stored in the memory area indicated by the address of the HL register in the C register, and stores the value stored in the memory area indicated by the address obtained by adding "1" to the value of the HL register in the A register. The command "OUT (C), A" on line 12 outputs the value of the A register (setting data) to the memory area (built-in register) indicated by the address of the C register.

For example, if the HL register is the symbol "@NUM_CPU_RG1" itself, the 1-byte value "@S1CM___" (e.g., "2CH") on line 44 of FIG. 246 is stored in the C register, and the 1-byte value "10000000B" on line 45 of FIG. 246 is stored in the A register. Then, the value of the A register, "10000000B", is output to the memory area indicated by the symbol "@S1CM___" in the C register.

Next, the command "DJNZ INITIAL02" on line 13 of Figure 245 decrements the value of the B register (subtracts "1"), and if the result of the decrement is not 0, it moves to the index "INITIAL02" on line 10, and if the result of the decrement is 0, it moves to the next command after that command. In this case, the amount of data is "2", so repeating the process from the index "INITIAL02" twice will set the value of the B register to 0. In this way, the setting of the configuration data for the input/output unit 704 number 2 in the latter part of Figure 246 is completed.

In this way, the total command size of the commands in the initial setting process shown in Figure 245 is 2 bytes of the command "LDF HL, T_CPU_REG" on the 1st line + 2 bytes of the command "LD B, @NUM_CPU_RG1" on the 2nd line + 3 bytes of the command "LD U, 0FEH" on the 3rd line + 2 bytes of the command "LDIN AC, (HL)" on the 5th line + 2 bytes of the command "OUT (C), A" on the 6th line + 2 bytes of the command "DJNZ INITIAL01" on the 7th line + 3 bytes of the command "LD U, 0FFH" on the 8th line + 2 bytes of the command "LD B, @NUM_CPU_RG2" on the 9th line + 2 bytes of the command "LDIN AC, (HL)" on the 11th line + 2 bytes of the command "OUT (C), A" on the 12th line + 2 bytes of the command "DJNZ INITIAL02" on the 13th line = 24 bytes.

Here, the U register must be changed to access multiple input/output units 704, so the total command size is larger than in the example of Figure 243. However, as mentioned above, in some processes within a program, the command size may be smaller if memory-mapped I/O instructions are used instead of I/O-mapped I/O instructions. Therefore, an example in which the memory-mapped I/O method is applied to some processes will be explained.

Figure 247 shows another example of part of the command group for realizing CPU initialization processing. Here, unlike Figures 243 and 245, the main CPU 500a sets configuration data in the input/output unit 704 (built-in register) using the memory-mapped I/O method. Note that the CPU built-in register setting data table referenced in the CPU initialization processing can use the CPU built-in register setting data table in Figure 246 as is, so it will be explained using Figure 246.

The command "LDF HL, T_CPU_REG" on the first line of Fig. 247 sets the top address "T_CPU_REG" of the data group in the CPU built-in register setting data table (table containing transfer information) in Fig. 246 in the HL register (second register). The command "LD B, @NUM_CPU_RG1" on the second line sets the symbol "@NUM_CPU_RG1" itself (the number to be transferred) in the B register (first register).

As can be seen by looking at the 42nd line of the CPU internal register setting data table in Figure 246, the symbol "@NUM_CPU_RG1" contains the command "EQU ($-T_CPU_REG)/2". Here, the value of $-T_CPU_REG is the total number of bytes in the 1-byte value indicating the number of data items, and when this value is divided by 2, which is the number of combinations of addresses and values, the number of set data items becomes 26/2 = 13.

The command "LD Q, HIGH @PTOPR___" on the third line of FIG. 247 sets the value of the upper byte of the symbol "@PTOPR___" ("FEH") in the Q register. Here, since the input/output unit 704 is accessed using the memory-mapped I/O method, the upper byte of the input/output unit 704 is set in the QH register instead of the U register. As described above, two values "FEH" and "FFH" are prepared as addresses indicating the input/output unit 704, and the main CPU 500a changes the value of the Q register, which is the upper byte, each time depending on the input/output unit 704 to be accessed. The initial value of the Q register is "F0H", which corresponds to the top address of the main RAM 500c. Here, "FEH" is first set in the Q register (third register), and setting data is set for the input/output unit 704 whose upper address is "FEH".

The command "LDINTQR (HL)" on the fourth line of FIG. 247 sets the value of the Q register to the upper byte of the destination address, sets the value stored in the memory area indicated by the address of the HL register to the lower byte of the destination address, transfers the value stored in the memory area indicated by the address of the value of the HL register plus "1" to the memory area indicated by the destination address, adds "2" to the value of the HL register to update the next transfer address, decrements the value of the B register (subtracts "1"), and repeats the process until the decremented result becomes 0, that is, 13 times, which is the set data. In this way, the setting of the setting data for the 13 input/output units 704 in the first stage of FIG. 246 is completed. With this LDINTQR command, processing is executed without using registers other than the B register, HL register, and Q register, such as the A register.

The symbol "@NUM_CPU_RG2" itself (the number to be transferred) is set in the B register (first register) by the command "LD B, @NUM_CPU_RG2" on the fifth line of Fig. 247. As can be understood by referring to the 50th line of the CPU built-in register setting data table in Fig. 246, the command "EQU ($-T_CPU_REG)/2-@NUM_CPU_RG1" is written in the symbol "@NUM_CPU_RG2". Here, the value of $-T_CPU_REG (a 1-byte value indicating the number of data) is 30/2=15, and "@NUM_CPU_RG1" is 13, so in the example of Fig. 246, the number of set data is 15-13=2.

The command "LD Q, HIGH @S2CMS___" on line 6 of FIG. 247 sets the value of the upper byte of the symbol "@S2CMS___" ("FFH") in the Q register (third register). Here too, to access the input/output unit 704 using the memory-mapped I/O method, the upper byte of the input/output unit 704 is set in the QH register instead of the U register. As described above, of the two values "FEH" and "FFH" that indicate the input/output unit 704, setting of the configuration data has been completed for the input/output unit 704 whose upper address is "FEH", so here "FFH" is set in the Q register, and setting of the configuration data for the input/output unit 704 whose upper address is "FFH".

The command "LDINTQR (HL)" on the seventh line of FIG. 247 sets the value of the Q register to the upper byte of the destination address, sets the value stored in the memory area indicated by the address of the HL register (second register) to the lower byte of the destination address, transfers the value stored in the memory area indicated by the address of the value of the HL register plus "1" to the memory area indicated by the destination address, adds "2" to the value of the HL register to update the next transfer address, decrements the value of the B register (subtracts "1"), and repeats the process until the decremented result becomes 0, that is, twice, which is the set data. In this way, the setting of the setting data for the input/output unit 704 of 2 in the latter part of FIG. 246 is completed. With this LDINTQR command, the process is executed without using registers other than the B register, HL register, and Q register, such as the A register.

Then, the command "LD Q, HIGH @RAM_BGN_ADR" on line 8 of Figure 247 sets the value of the upper byte of the symbol "@RAM_BGN_ADR" to the Q register. In this way, the value of the Q register is restored to its initial value "F0H".

Thus, the total command size of the commands in the initial setting process shown in Figure 247 is 2 bytes of the command "LDF HL, T_CPU_REG" on the first line + 2 bytes of the command "LD B, @NUM_CPU_RG1" on the second line + 2 bytes of the command "LD Q, HIGH @PTOPR___" on the third line + 2 bytes of the command "LDINTQR (HL)" on the fourth line + 2 bytes of the command "LD B, @NUM_CPU_RG2" on the fifth line + 2 bytes of the command "LD Q, HIGH @S2CMS___" on the sixth line + 2 bytes of the command "LDINTQR (HL)" on the seventh line + 1 byte of the command "LD Q, HIGH @RAM_BGN_ADR" = 15 bytes.

Here, the I/O mapped I/O method in FIG. 245 is changed to a memory mapped I/O method as in FIG. 247, which makes it possible to use the LDINTQR command. In this way, the total command size of the commands in the initial setting process in FIG. 245 is 24 bytes, while the total command size of the commands in the initial setting process in FIG. 247 is 15 bytes, making it possible to reduce 9 bytes. In this way, by using the LDINTQR command with the memory mapped I/O method, it is possible to shorten the commands and ensure the capacity of the control area for performing game control processing.

<Memory Mapped I/O Method Usage Example 2>
Fig. 248 is an explanatory diagram showing the addresses of output ports, and Fig. 249 is a diagram showing a part of a group of commands for realizing the power-off save process. For the sake of convenience, the output port clear process (step S300-11 in Fig. 25 and step S3000-11 in Fig. 97) of the power-off save process S3000 will be explained here. In the output port clear process, the output of the output port is cleared to 0. Note that here, an example is given in which the main CPU 500a executes the output port clear process S3000-11.

In this embodiment, a total of nine output ports, output ports 0 to 8, are provided as the input/output unit 704. Output ports 0 to 8 can continuously output discrete signals (two values, Hi (high level) and Low (low level)) in bit units. Note that the target of the output port clear process is limited to a total of six output ports, output ports 0 to 4 and 7, out of output ports 0 to 8. Therefore, output ports 0 to 4 and 7 are cleared in the output port clear process.

Referring to FIG. 248, output port 4 is assigned to address "FFF0H" in the memory space, output port 3 is assigned to address "FFF1H", output port 2 is assigned to address "FFF2H", output port 1 is assigned to address "FFF3H", output port 0 is assigned to address "FFF4H", and output port 7 is assigned to address "FFF5H".

The output port clear process in Figure 249 is performed only when "0" is set in the A register, and when the output port clear process is executed, "0" has already been set in the A register. The command "LD BC,6*256+@OUT_PRT_7" on the first line of Figure 249 sets the number of output ports, 6, in the B register, and sets the address value of the lowest byte indicating output port 7 in the C register. As shown in Figure 248, the value of the lowest byte indicating output port 7 is "F5H". The command "OUT (C), A" on the third line sets the value of the U register (here, the initial value "FFH") to the highest byte of the address, the value of the C register to the lowest byte, and the value of the A register ("0") is output to the memory area indicated by that address.

The command "DEC C" on the fourth line of Figure 249 decrements the value stored at the address indicated by the C register by 1. The command "DJNZ PRFPROC02" on the fifth line decrements the value of the B register (subtracts "1"), and if the result of the decrement is not 0, it moves to the index "PRFPROC02" on the second line, and if the result of the decrement is 0, it moves to the next command after that command. In this case, the number of output ports is "6", so if the process from the index "PRFPROC02" is repeated six times, the value of the B register will become 0.

In this way, the address of input/output unit 704 is decremented from "FFF5H" → "FFF4H" → "FFF3H" → "FFF2H" → "FFF1H" → "FFF0H", and accordingly, each bit of the output port is set to 0 in the order of output port 7 → output port 0 → output port 1 → output port 2 → output port 3 → output port 4.

In this way, the total command size of the output port clear processing command shown in Figure 249 is 3 bytes of the command "LD BC, 6*256+@OUT_PRT_7" on the first line + 2 bytes of the command "OUT (C), A" on the third line + 1 byte of the command "DEC C" on the fourth line + 2 bytes of the command "DJNZ PRFPROC02" on the fifth line = 8 bytes.

As mentioned above, in some processes within a program, the command size may be smaller if memory-mapped I/O instructions are used instead of I/O-mapped I/O instructions. Therefore, we will explain an example in which memory-mapped I/O is applied to some processes.

Figure 250 shows another example of a portion of the command group for implementing the power-off evacuation process. Here, the main CPU 500a clears the output of the output port to 0 using the memory-mapped I/O method.

The command "LD HL, @OUT_PRT_4" on the first line of Fig. 250 sets the 2-byte symbol "@OUT_PRT_4" itself (output port information) indicating output port 4 in the HL register (second register). As shown in Fig. 248, the value of the 2 bytes indicating output port 4 is "FFF0H". The command "LD B, 6" on the second line sets 6, which is the number of output ports to be cleared (the number to be cleared), in the B register (first register).

The command "CLRIRS" on the third line of Figure 250 stores "0" in the memory area indicated by the address of the HL register (clearing the output port), adds "1" to the value of the HL register to update the next address to be cleared, and decrements the value of the B register (subtracts "1"), repeating this process until the decrement result becomes 0, i.e., six times, which is the number of output ports to be cleared. With this CLRIRS command, processing is executed without using any registers other than the B register and HL register, such as the A register.

In this way, the address of the input/output unit 704 is incremented from "FFF0H" → "FFF1H" → "FFF2H" → "FFF3H" → "FFF4H" → "FFF5H", and the output of the output ports is set to 0 in the following order: output port 4 → output port 3 → output port 2 → output port 1 → output port 0 → output port 7.

In this way, the total command size of the output port clear processing command shown in Figure 250 is 3 bytes for the command "LD HL, @OUT_PRT_4" on the first line + 2 bytes for the command "LD B, 6" on the second line + 2 bytes for the command "CLRIRS" on the third line = 7 bytes.

Here, the I/O mapped I/O method of FIG. 249 is changed to a memory mapped I/O method as shown in FIG. 250, which makes it possible to use the CLRIRS command. In this way, the total command size of the command for the output port clear process of FIG. 249 is 8 bytes, while the total command size of the command for the output port clear process of FIG. 250 is 7 bytes, making it possible to reduce by 1 byte. In this way, by using the CLRIRS command using the memory mapped I/O method, it is possible to shorten the command and ensure the capacity of the control area for performing game control processing.

In the example of FIG. 250, by using the CLRIRS command, it is not necessary to use the A register. Therefore, the value of the A register will not be updated unintentionally. For example, if the A register is already in use, it would normally be necessary to save the A register, but since the A register is not used here, there is no need to save it. This makes it possible to use resources more efficiently. In the example of FIG. 249, it is assumed that the A register is set to the value "0" in advance, but since the command "CLRIRS" has a function for setting the value "0", the process of setting the value "0" in advance is also unnecessary. In this way, it is possible to further shorten the command and ensure the capacity of the control area for performing game control processing.

(Medalless gaming machines, managed gaming machines)
Incidentally, instead of the above-mentioned gaming machine 100 (pachinko machine), a controlled gaming machine is being considered, which is a pachinko machine with an enclosed circulation system, allowing the player to play without touching the gaming balls. Also, instead of the slot machine 400, a medal-less gaming machine is being considered, allowing the player to play without the intervention of actual medals. The controlled gaming machine and medal-less gaming machine will be explained below. Here, medal-less gaming machines will be mainly mentioned, and specifications common to the controlled gaming machine and medal-less gaming machine will be explained, and details specific to the controlled gaming machine will be supplemented as necessary.

Figure 251 is a functional block diagram showing a gaming system 900. The gaming system 900 includes a medal-less gaming machine 902, a dedicated unit 904 (specific unit), a hall computer 906, a management computer 908, a card company data center 910, and a gaming machine information center 912. Note that the gaming system 900 uses electronic medals (game value) as electronic gaming media (game value) instead of actual medals. Therefore, the game using medals in the slot machine 400 described above can be read as a game using electronic medals in the medal-less gaming machine 902 and applied.

In the medalless gaming machine 902, a game can be played in the same manner as in the slot machine 400, without the intervention of medals. The medalless gaming machine 902 can output various information within the medalless gaming machine 902 to the dedicated unit 904. The dedicated unit 904 is connected to the medalless gaming machine 902, and can lend electronic medals to players and count the electronic medals acquired by players. The hall computer 906 is installed in the hall (amusement hall) and manages the status of all gaming machines in the hall, including the medalless gaming machine 902, in order to collect fraud monitoring information. The management computer 908 is connected to all the dedicated units 904 in the hall, and collects various information on the medalless gaming machine 902 through the dedicated unit 904. The card company data center 910 is connected to the management computer 908, and manages the card units and card media based on various information on the medalless gaming machine 902. The gaming machine information center 912 is connected to the card company data center 910 and collects and manages various information about the medalless gaming machine 902.

Figure 252 is an external view for explaining the general mechanical configuration of the medalless gaming machine 902 and the dedicated unit 904, and Figure 253 is a block diagram showing the general electrical configuration of the medalless gaming machine 902 and the dedicated unit 904.

As can be understood by comparing Figures 73 and 76 with Figures 252 and 253, the slot machine 400 and the medalless gaming machine 902 are almost identical in structure and function with respect to the progress of the game. Here, the components that are identical in structure and function to the slot machine 400 are given the same reference numerals and their explanation is omitted, and the components that differ from the slot machine 400 are described in detail.

The medal-less gaming machine 902 does not require the insertion and dispensing of actual medals, and therefore does not require the provision of functional units for distributing medals, such as the medal insertion unit 414 and medal dispensing device 442 in the slot machine 400. Meanwhile, unlike the slot machine 400, the medal-less gaming machine 902 includes a medal count control board 920 that connects to the dedicated unit 904 via a gaming ball etc. lending device connection terminal board 948, which will be described later. The medal count control board 920 is connected to a counting switch 922 and a gaming medal count display device 924. The counting switch 922 is composed of a push switch located near the display device 924, and detects an operation to transfer some or all of the electronic medals that the player has won and that are electronically held in the medalless gaming machine 902 (that can be used for gaming) (the total number of electronic medals that are electronically held in the medalless gaming machine 902 and can be used for gaming is referred to as the "game medal number" (game value number), and the memory section of the RAM that holds the electronic medals is sometimes referred to as the "medal holding section") to the dedicated unit 904. The counting switch 922 can be operated in two ways: a short press of less than 500 msec and a long press of 500 msec or more. When the counting switch 922 is pressed briefly, one electronic medal is counted for each operation, and when the counting switch 922 is pressed for a long time, as shown in Figs. 264 and 265 described later, 50 electronic medals are counted at the timing when the count notification is made every 300 msec (if there are less than 50 medals held in the medal holding section, all electronic medals are counted). The medal count clear switch (not shown) is configured as a push switch located in a position where the player cannot operate it, and clears the number of medals displayed on the medal count display device 924. Specifically, after the medalless gaming machine 902 is powered off, the medalless gaming machine 902 is powered on while operating the medal count clear switch, thereby clearing the number of medals. At this time, the medal count clear status is turned on, and when the game ends, the medal count clear status is turned off.

The game medal count display device 924 displays the total number of electronic medals held in the medal holding section (game medal count). However, the electronic medals bet is not included in the game medal count. Therefore, the game medal count display device 924 displays the number obtained by subtracting the number of electronic medals bet from the number of electronic medals acquired by the player. The game medal count is displayed as follows on a 5-digit or 6-digit 7-segment display or the like arranged in a position visible to the player. That is, the numerical range is expressed as 0 to 16368 taking into account the maximum difference in number of medals in one business day, and if the upper digit of a significant numerical value is 0, the numerical value is left blank. Here, if the numerical value becomes 15000 or more, a notification is executed to prompt the player to count, the lending process of electronic medals is restricted, and a test counting signal is output for about 3500 msec. However, the player can continue playing. And, if the numerical value becomes 16369 or more, the progress of the game is restricted. Specifically, the bet switch 416, the start switch 418, and the settlement switch 437 are prohibited from being accepted. Instead of when the numerical value is 16369 or more, when the numerical value is likely to be 16369 or more, the payout of electronic medals may be prohibited until the player executes the counting. For example, when the numerical value is 16357 or more, which is obtained by subtracting 12 medals (maximum payout number (for example, 15 medals) - a prescribed number (for example, 3 medals)) which is the maximum difference number that can be obtained in one game from 16369, the game may be stopped. Furthermore, the game medal number display device 924 reflects and displays the updated game medal number within approximately 300 msec after the game medal number held in the medalless game machine 902 is updated. Furthermore, the game medal number display device 924 is a shared device with an error code display function unit, and can display an error code. However, the error code can only be displayed when play is not possible (the bet switch 416, start switch 418, and settlement switch 437 are not accepted, and the electronic medal lending process and counting process are restricted).

The bet switch 416, which shares the same function as the slot machine 400, detects an operation to bet a specified number of electronic medals required for one game among the electronic medals held in the medal holding section of the medalless gaming machine 902. Also, a one-bet switch (not shown) can be used to bet one electronic medal among the electronic medals held in the medal holding section of the medalless gaming machine 902. Such bet switch 416 and one-bet switch can be shared with a settlement switch 437, which shares the same function as the slot machine 400, and can be provided with a settlement function. Furthermore, the settlement switch 437 returns all electronic medals bet by one operation of the bet switch 416 or one-bet switch to the medal holding section. The operation of such a settlement switch 437 is valid only from the time electronic medals are bet until the start switch 418 is operated.

The dedicated unit 904 includes a dedicated unit control board 930 that is connected to the medal count control board 920 of the medalless gaming machine 902. The dedicated unit control board 930 is connected to a cash insertion section 932, a card insertion section 934, a loan switch 936, a return switch 938, a game switch 940, a degree display device 942, and an acquired medal count display device 944. The cash insertion section 932 functions as an insertion port for inserting cash. The card insertion section 934 enables the insertion and withdrawal of a card medium capable of accumulating electronic medals. The loan switch 936 is composed of a push switch, and detects an operation of transferring an electronic medal corresponding to the degree of cash held in the dedicated unit 904 to the medalless gaming machine 902. The return switch 938 is composed of a push switch, and detects an operation of transferring an electronic medal held in the dedicated unit 904 to a card medium and withdrawing the card medium from the dedicated unit 904 through the card insertion section 934. The game switch 940 is composed of a push switch, and detects the operation of transferring the electronic medals held in the dedicated unit 904 to the medal-less game machine 902. The point display device 942 displays the point number held in the dedicated unit 904, i.e., the point number equivalent to the cash inserted from the cash insertion unit 932. The acquired medal number display device 944 displays the acquired medal number, which is the total number of electronic medals held in the dedicated unit 904.

When a player tries to play on the medal-less gaming machine 902, he or she first inserts cash into the cash insertion section 932 of the dedicated unit 904 shown in FIG. 252. Then, the number of points corresponding to the inserted cash (for example, "10" for the insertion of 1,000 yen) is displayed on the point display device 942 of the dedicated unit 904. When the player operates the loan switch 936, electronic medals corresponding to the number of points held in the dedicated unit 904 are transferred to the medal-less gaming machine 902. Then, the number of electronic medals transferred (for example, "50") is displayed on the game medal number display device 924 of the medal-less gaming machine 902. Specifically, when the medal-less gaming machine 902 receives a loan notification from the dedicated unit 904, which will be described later, if the loan notification is normal, the medal-less gaming machine 902 receives the transfer of the electronic medals and notifies "normal" in the loan receipt result response. On the other hand, if the values of the message length (05h) and command (13h) in the loan notification are normal but other information is abnormal, the medalless gaming machine 902 notifies "abnormal" in the loan receipt result response described below. Also, if the loan notification is not received normally or the message length and command values of the loan notification are abnormal, the medalless gaming machine 902 discards the received message without displaying an error, and waits until it can receive a loan notification with at least a normal message length and command. If the loan process cannot be performed, that is, if the gaming machine information notification described below is abnormal, the counted medal count (the number of electronic medals transferred to the dedicated unit 904 at one time) in the counting notification described below is "1" or more, the number of gaming medals displayed on the gaming medal count display device 924 is 15,000 or more, the checksum of the received loan notification is abnormal, the loan serial numbers in the received loan notification are not consecutive, the loaned medal count in the received loan notification is "51" or more, or the gaming machine information notification sent from the medal count control CPU 946 described below to the dedicated unit 904 notifies other than hall control/fraud monitoring information, the medalless gaming machine 902 will notify "abnormality" in the loan receipt result response.

Next, when the player operates the bet switch 416, electronic medals are bet. At this time, the game medal count display device 924 displays a value (e.g., "47") obtained by subtracting the number of electronic medals bet (e.g., "3") from the value. The player can then start playing, just like with the slot machine 400. If, as a result of playing, a minor combination resulting in a payout of 11 medals is won, the number of electronic medals paid out (e.g., "11") is added (e.g., "58").

When the settlement switch 437 is operated after the player operates the bet switch 416 to bet electronic medals and before the start switch 418 is operated (to start playing), the number of electronic medals bet (for example, "3") is added to the game medal count display device 924 (for example, "50"), and the bet state is released.

When the player has finished playing, he or she operates the counting switch 922 to transfer the digitized medals held in the medal holding section to the dedicated unit 904. The number of game medals held in the medal holding section is then displayed on the acquired medal count display device 944 of the dedicated unit 904, and "0" is displayed on the game medal count display device 924. When the player operates the return switch 938, the digitized medals held in the dedicated unit 904 are transferred to the card, and the card is withdrawn from the dedicated unit 904 via the card insertion section 934. In this way, the player can accumulate the acquired digitized medals on the card medium.

When the player tries to play again, he or she can insert the card medium on which the electronic medals have been accumulated into the card insertion section 934 instead of cash, and play with the electronic medals accumulated on the card medium. The electronic medals accumulated on the card medium are then transferred to the dedicated unit 904, and the total number of electronic medals accumulated on the card medium is displayed on the acquired medal count display device 944. By operating the play switch 940 instead of the loan switch 936, the player can transfer the electronic medals held in the dedicated unit 904 to the medal-less gaming machine 902.

When the loan switch 936 or the count switch 922 is operated, the medal count control CPU (control unit) 946 executes the loan process or count process of the electronic medals and transmits a command to that effect to the main CPU (control unit) 500a, and the main CPU 500a, which receives the command, transmits the command to the sub-CPU 502a. Then, the sub-CPU 502a outputs a predetermined sound representing the movement of the electronic medals to the speaker 428 as the electronic medals are actually loaned or counted in the loan process or count process. In this way, the player can audibly confirm that the loan process or count process is being executed appropriately. The sub-CPU 502a may also notify the fact that the loan process or count process is being executed through each device, such as the liquid crystal display unit 424 and the performance lamp 426, in addition to the speaker 428. Note that, here, a CPU (Central Processing Unit) is used as an example of the control unit, but various computing elements capable of performing calculations, such as an MPU (Micro Processor Unit), DSP (Digital Signal Processor), or FPGA (Field Programmable Gate Array), can also be used.

In such a medal-less gaming machine 902, actual medals are not required, making it possible to prevent cheating, such as inserting medals artificially or using medals that have been illegally brought in. Also, since there is no need to provide a mechanism for inserting and paying out gaming media within the gaming machine, design and manufacturing costs can be reduced. Furthermore, by centrally managing the lending of gaming media to players and the counting of acquired gaming media, it is possible to prevent fraud. Furthermore, by centrally managing data, it is possible to curb speculation and, ultimately, to strengthen measures against addiction.

In addition, in the managed gaming machine, by applying a frame control board, a counting switch, and a gaming ball number display device that have the same functions as the medal count control board 920, the counting switch 922, and the gaming medal number display device 924 in the medalless gaming machine 902, respectively, it becomes possible to proceed with the game without circulating gaming balls between the managed gaming machine and the dedicated unit 904, just like the medalless gaming machine 902.

In addition, an example has been described here in which a medal count control board 920 is provided in the medalless gaming machine 902 separately from the main control board 500, and the medal count control board 920 operates independently, but this is not the only case, and the board and CPU configurations can be different.

Figure 254 is an explanatory diagram for explaining another board configuration. In the above-mentioned embodiment, as shown in Figure 254 (a), the main control board 500 is provided with a main CPU 500a (first control unit) that controls the progress of the game, and the medal count control board 920 is provided with a medal count control CPU 946 (second control unit) that manages the electronic medals used in the game, and the main control board 500 and the medal count control board 920 are connected via a harness, and the medal count control board 920 and the game ball etc. lending device connection terminal board 948 are connected via a harness. Here, the game ball etc. lending device connection terminal board 948 is a connection terminal board for connecting the medalless gaming machine 902 and the dedicated unit 904, and receives signals related to the lending of electronic medals, transmits the lending receipt result of electronic medals, transmits signals related to the counting of electronic medals, and transmits each information of the medalless gaming machine 902. In addition, the game ball etc. dispensing device connection terminal board 948 receives power (VL) from the dedicated unit 904, uses the power as input to an insulating element such as a photocoupler, generates a VL connection signal (specific connection signal) indicating the connection state with the dedicated unit 904, and outputs it to the medal count control board 920. The medal count control board 920 can determine that power is being supplied from the dedicated unit 904, in other words, that the dedicated unit 904 is powered on and properly connected to the dedicated unit 904, by the ON/OFF of the VL connection signal. With such a board configuration, it is possible to minimize the need to modify the configuration of the existing main control board 500 and to increase the occupied area, thereby reducing design costs.

The medal count control board 920 does not necessarily need to be separate from the main control board 500, and may be formed integrally with the main control board 500 as long as it fulfills its function. Specifically, as shown in FIG. 254(b), the main control board 500 may be provided with both the main CPU 500a that controls the progress of the game and the medal count control CPU 946 that manages the electronic medals used in the game, and the main control board 500 and the game ball etc. lending device connection terminal board 948 may be connected via a harness. Here, by providing both the main CPU 500a and the medal count control CPU 946 on a single main control board 500, the connectors and harnesses used for information exchange between the two can be eliminated, the occupied area can be reduced, and the reliability of information transmission can be improved.

In the example of FIG. 254(c), the main CPU 500a arranged on the main control board 500 manages the electronic medals used in the game instead of the medal count control CPU 946, and the main control board 500 and the game ball etc. lending device connection terminal board 948 are connected via a harness. Here, in the main control board 500, the main CPU 500a controls the progress of the game and manages the electronic medals, so there is no need for a connection line for information exchange between the main CPU 500a and the medal count control CPU 946, which further reduces the occupied area and improves the reliability of information transmission.

Here, at least the main control board 500 must be enclosed in the main board case to prevent fraud. In addition, if the medal count control board 920, which has the function of managing the electronic medals used in the game, is a separate entity, it must be enclosed in the main board case together with the main control board 500.

255 is an explanatory diagram for explaining the enclosure of the case. For example, as shown in FIG. 254(a), when the main control board 500, the medal count control board 920, and the game ball etc. lending device connection terminal board 948 are formed separately, and the main control board 500 and the medal count control board 920 are connected, and the medal count control board 920 and the game ball etc. lending device connection terminal board 948 are connected, it is possible to enclose the main control board 500, the medal count control board 920, and the game ball etc. lending device connection terminal board 948 all in one main board case 500e as shown in FIG. 255(a). Here, as shown in FIG. 255(a), an example is given in which the main control board 500 and the medal count control board 920 are integrally formed by directly and fixedly connecting the connectors to each other without using a harness, but the two may be connected via a harness.

Also, as shown in Figures 254(b) and 254(c), when the main CPU 500a and the medal count control CPU 946 are arranged on the main control board 500, or when the main CPU 500a is arranged alone and the main control board 500 and the game ball etc. lending device connection terminal board 948 are connected via a harness, the main control board 500 and the game ball etc. lending device connection terminal board 948 may be individually enclosed in the main board case 500e and the game ball etc. lending device connection terminal board 948 in the connection terminal case 948e, respectively, in a state where they are connected, as shown in Figure 255(b), or it is possible to enclose the main control board 500 and the game ball etc. lending device connection terminal board 948 all in a single main board case 500e, as shown in Figure 255(c).

In any case, the main control board 500, medal count control board 920, and game ball etc. dispensing device connection terminal board 948 are all enclosed in a case. In this case, the structure must be such that it is easy to check not only the front surface of the board, but also the back surface of the board.

In the example shown in Figures 254(a) and 254(b), in a medalless gaming machine 902, the main CPU 500a and medal count control CPU 946 operate independently, with the main CPU 500a controlling the progress of the game and the medal count control CPU 946 managing the electronic medals used in the game.

256 is an explanatory diagram for explaining the CPUs and areas (used areas or non-used areas described above) that execute each function of the medalless gaming machine 902. In FIG. 256, "◎" indicates a general execution unit when the functions are shared by two CPUs, the main CPU 500a and the medal count control CPU 946, as in FIG. 254(a) and FIG. 254(b), "◯" indicates an executable execution unit, and "×" indicates an inexecutable execution unit. For example, when the functions are shared by two CPUs, as shown in No. 12 in FIG. 256, the function of controlling the game medal count display device 924 and the function of controlling communication with the dedicated unit 904 are generally carried out in the usage area of the medal count control CPU 946 (shown by "◎" in FIG. 256), but it is also possible for some or all of these functions to be borne in the usage area of the main CPU 500a (shown by "◯" in FIG. 256).

(Communication between medal-less gaming machine and dedicated unit)
The above-described functional units allow the medal-less gaming machine 902 and the dedicated unit 904 to exchange various information (messages) via serial communication to ensure normal operation of each other. The serial communication is controlled by full-duplex communication control using an asynchronous communication method, with a communication speed of, for example, 62,500 bps, and each byte of data being represented by one start bit, eight data bits, and one stop bit. At this time, the character transmission time is 0.16 msec to 3.9 msec, and if the next start bit is not received within 3.9 msec, the character is considered to be one message. For example, the medal-less gaming machine 902 (here, for example, the medal count control CPU 946 of the medal count control board 920) sends the following gaming machine information notification, counting notification, and loan receipt result response to the dedicated unit 904 via such serial communication.

Figures 257 to 260 are explanatory diagrams for explaining the format of gaming machine information notification. As shown in Figure 257, the gaming machine information notification transmits one of the three gaming machine information items, gaming machine performance information, gaming machine installation information, and hall control/fraud monitoring information, to the dedicated unit 904, and the message length is variable from 18 to 57 bytes. Specifically, the first byte of the gaming machine information notification message indicates the message length (12h to 39h), and the second byte indicates "01h" indicating the type of command (here, gaming machine information notification). The third byte indicates a sequence number from 00h to FFh as a serial number. When the power is turned on, the serial number is notified as 00h, and is incremented by 1 each time a notification is made. However, the notification following FFh is notified as 00h, but as 01h.

The fourth byte indicates the type of gaming machine. Bit 7 of the gaming machine type indicates the management medium, with gaming balls being represented by "0" and gaming medals by "1". Bits 6 to 4 indicate the group classification, with the Japan Machinery Works Union being represented by "0" and the Japan Electrical Manufacturers Association being represented by "1". Bits 3 to 0 indicate the type of gaming machine, with pachinko machines being represented by "1", slot machines being represented by "2", arrange ball machines being represented by "3", and jankyu machines being represented by "4". The fifth byte indicates the type of gaming machine information. For example, if the gaming machine information is gaming machine performance information, it will be "00h", if the gaming machine information is gaming machine installation information, it will be "01h", and if the gaming machine information is hall control/fraud monitoring information, it will be "02h". From the sixth byte onwards, gaming machine information (either gaming machine performance information, gaming machine installation information, or hall control/fraud monitoring information) is indicated in variable length.

For example, if the gaming machine information type is "00h", the gaming machine performance information is represented by 51 bytes as gaming machine information, and as shown in FIG. 258, includes the total number of coins inserted, the total number of coins paid out, MY (maximum difference in number of coins), the total number of coins paid out for special features, the total number of coins paid out for consecutive special features, the bonus feature ratio, the consecutive bonus feature ratio, the ratio of advantageous zones, the ratio of special features with instructions, the bonus feature status ratio, the number of times played, the reserve, reservation 1, and reservation 2. The gaming machine performance information is transferred to the dedicated unit 904, and then further transmitted to the gaming machine information center 912. Of this information, the byte order of the total number of coins inserted, the total number of coins paid out, MY, the total number of coins paid out for special features, the total number of coins paid out for consecutive special features, and the number of times played is little endian.

If the gaming machine information type is "01h", the gaming machine installation information is represented by 40 bytes as gaming machine information, and includes the main control chip ID number, main control chip manufacturer code, main control chip product code, medal count control chip ID number, medal count control chip manufacturer code, and medal count control chip product code, as shown in FIG. 259. Here, the main control chip ID number (9 bytes) and medal count control chip ID number (9 bytes) are represented by the upper 4 bytes being 0, the following 4 bytes being chip individual number or chip code, and the lowest byte being identification code (LEM50A = "21h", LES50A = "22h", LEM7OA = "23h", IDNAC8701 = "41h", IDNAC8702 = "42h", IDNAC8703 = "43h"). However, if the medal count control CPU 946 is not installed, all 9 bytes are represented by 0. The byte order of the main control chip ID number, main control chip manufacturer code, main control chip product code, medal count control chip ID number, medal count control chip manufacturer code, and medal count control chip product code is big endian.

If the gaming machine information type is "02h", the hall control/fraud monitoring information is represented as gaming machine information in 12 to 16 bytes, and includes the number of gaming medals, the number of inserted medals, the number of paid out medals, main control status 1, main control status 2, gaming machine error status, gaming machine fraud 1, gaming machine fraud 2, gaming machine fraud 3, the number of gaming information, type information 1, count information 1, type information 2, and count information 2, as shown in FIG. 260. Here, the relationship between the number of gaming medals, the number of inserted medals, and the number of paid out medals is "number of gaming medals" = "number of gaming medals" sent last time - "number of inserted medals" + "number of paid out medals" + "number of loaned medals" received after the number of gaming medals sent last time - "counted number of gaming medals" sent after the number of gaming medals sent last time. If this relationship is not satisfied, it can be determined that the hall control/fraud monitoring information is abnormal. In addition, the setting change signal in bit 0 of gaming machine fraud 1 indicates that the setting is being changed and that the setting has been changed, and is output continuously from the time the setting is being changed to the time one game ends after the setting is changed. In addition, the setting check signal in bit 1 indicates that the setting is being checked, and must be output for at least three seconds as a countermeasure against cheating. If a power outage occurs while the setting check signal is being output, the timer that was timing for three seconds may be reset and the setting check signal may be output again for three seconds, or the value of the timer at the time of the power outage may be saved, and when the power is turned on (when the power is restored), the timer may be restarted from the saved value of the timer and the setting check signal may be output. In this case, the total time that the setting check signal is output before the power outage and after the power is restored is three seconds. In the game information consisting of a combination of type information 1 and count information 1, or a combination of type information 2 and count information 2, type information 1 and 2 indicate whether the specified number (when the start switch 418 is operated) or the number of coins to be paid out (when the game ends), and the number of coins is indicated by count information 1 and 2. During replay, the specified number at the time of replay activation is notified. The number of game information indicates the number of game information, and if the number of game information is 0, the four items type information 1, count information 1, type information 2, and count information 2 are not sent.

Figure 261 is an explanatory diagram for explaining the format of the count notification. The count notification transmits the counted cumulative medal count, which will be described later, to the dedicated unit 904, and the message length is a fixed length of 7 bytes. Specifically, the first byte of the message indicates the message length (07h), and the second byte indicates "02h" indicating the type of command (here, count notification). The third byte indicates a sequence number from 00h to FFh as the count serial number. This count serial number is notified as 00h when the power is turned on, and is incremented by 1 each time a notification is made. However, the next notification after FFh is set to 01h instead of 00h. The fourth byte indicates the counted medal number. The counted medal number is the number of electronic medals counted at the time of the count notification. The fifth byte indicates the counted cumulative medal number. The cumulative medal count is the accumulated medal count value after being cleared to 0000h when the medalless gaming machine 902 is turned on, and the value after FFFFh is 0000h. The seventh byte indicates a checksum.

Figure 262 is an explanatory diagram for explaining the format of the loan receipt result response. The loan receipt result response is a response of the receipt result when a loan notification is received from the dedicated unit 904, and the message length is a fixed length of 5 bytes. Specifically, the first byte of the message indicates the message length (05h), and the second byte indicates "03h" indicating the type of command (here, loan receipt result response). The third byte indicates a sequence number of 00h to FFh as the loan serial number. This loan serial number is notified as 00h when the power is turned on, and if the loan medal count reception result described later is normal, it reflects the loan serial number received from the dedicated unit 904 as it is, and if the loan medal count reception result is abnormal, it reflects the loan serial number when the loan medal count reception result was normally received from the dedicated unit 904 earlier. The fourth byte indicates the loan medal count reception result (normal = 00h, abnormal = 01h). The fifth byte indicates a checksum.

In addition, the following loan notification is sent from the dedicated unit 904 to the medalless gaming machine 902 (here, for example, the medal count control CPU 946):

Figure 263 is an explanatory diagram for explaining the format of the loan notification. The loan notification transmits the number of loaned medals to the medalless gaming machine 902 when a counting notification is received from the medalless gaming machine 902, and the message length is a fixed length of 5 bytes. Specifically, the first byte of the message indicates the message length (05h), and the second byte indicates "13h" indicating the type of command (here, loan notification). The third byte indicates a sequence number from 00h to FFh as the loan serial number. This loan serial number is notified as 00h when the power is turned on, and is incremented by 1 for each notification. However, the notification following FFh is set to 01h instead of 00h. The fourth byte indicates the number of loaned medals. The number of loaned medals indicates the number of electronic medals loaned. If no gaming machine information notification has been received, if a gaming machine information type other than "02h: Hall control/fraud monitoring information" has been received, or if the counted medal number in the count notification is "1" or more, the number of lent medals "0" will be notified. The fifth byte indicates a checksum.

If a specific internal abnormality occurs in the medalless gaming machine 902, the medalless gaming machine 902 can be configured not to communicate with the dedicated unit 904. For example, if a specific abnormality occurs such as a backup abnormality or a RAM (RWM) abnormality, or if the manufacturer code does not match, the medal count control CPU 946 of the medalless gaming machine 902 issues an operation stop error without completing the startup process, and restricts the start of communication with the dedicated unit 904.

Figure 264 is a timing chart showing the notification timing of gaming machine information notification, counting notification, loan notification, and loan receipt result response. As shown in Figure 264, the medalless gaming machine 902 (here, for example, the medal count control CPU 946) transmits a gaming machine information notification to the dedicated unit 904 at intervals of 300 msec (300 msec or more, 310 msec or less) from the completion of startup of the medalless gaming machine 902. In addition, the medalless gaming machine 902 transmits a counting notification to the dedicated unit 904 100 msec (90 msec or more, 100 msec or less) from the start of the gaming machine information notification. The dedicated unit 904 transmits a loan notification to the medalless gaming machine 902 within 170 msec from the start of receiving the counting notification. After completing receipt of the loan notification, the medal-less gaming machine 902 notifies the dedicated unit 904 of the loan receipt result response within 10 msec. In this way, a time of 20 msec or more can be secured between the time when the medal-less gaming machine 902 notifies the loan receipt result response and the time when the next gaming machine information notification is made.

Figure 265 is an explanatory diagram for explaining the transmission timing of the gaming machine information notification. As described above, the gaming machine information notification is notified to the dedicated unit 904 at 300 msec intervals. The gaming machine information notification includes three types of gaming machine information: gaming machine performance information, gaming machine installation information, and hall control/fraud monitoring information, and as shown in Figure 265, each has a different transmission timing and priority. For example, the gaming machine installation information is notified 60 sec after the start-up of the medalless gaming machine 902 is completed, and is notified at 60 sec intervals thereafter. The gaming machine performance information is notified 180 sec after the start-up of the medalless gaming machine 902 is completed, and is notified at 180 sec intervals thereafter. The hall control/fraud monitoring information is notified at 300 msec intervals after the start-up of the medalless gaming machine 902 is completed. However, the transmission timing of the three notifications may overlap. When the transmission timings overlap, the gaming machine information notification is notified in order of priority. For example, when the gaming machine performance information, the gaming machine installation information, and the hall control/fraud monitoring information overlap in 180 sec, if there is no update of the main control state in the hall control/fraud monitoring information and there is no game information, the gaming machine installation information with the higher priority is notified first, the gaming machine performance information is notified after the next 300 msec, and the hall control/fraud monitoring information is notified after the next 300 msec. Also, when the gaming machine installation information and the hall control/fraud monitoring information overlap in 60 sec, if there is no update of the main control state in the hall control/fraud monitoring information and there is no game information, the gaming machine installation information with the higher priority is notified first, and the hall control/fraud monitoring information is notified after the next 300 msec. However, if there is an update to the main control state in the hall control/fraud monitoring information or if there is game information, the hall control/fraud monitoring information, which has a higher priority, is notified first, followed by the gaming machine installation information and gaming machine performance information. With this configuration, the medal-less gaming machine 902 and the dedicated unit 904 can confirm gaming machine information notifications (gaming machine performance information, gaming machine installation information, hall control/fraud monitoring information), counting notifications, loan notifications, and loan receipt result responses with the appropriate timing and priority.

(Contents stored in RAM)
As explained with reference to Fig. 254(a) and Fig. 254(b), the main CPU 500a and the medal count control CPU 946 are provided separately, and each CPU has an independent ROM and RAM, and processes based on an independent program. However, for example, information such as the total number of inserted coins, the total number of paid out coins, MY (maximum MY), the total number of payout coins for special features, the total number of payout coins for consecutive special features, and the number of games are information that starts accumulating when the power is turned on and is maintained until reset when the power is restored after a power outage. Here, if the main CPU 500a manages part of the information and the medal count control CPU 946 manages the other information independently, the following problem will occur. That is, if the power supply of either the main CPU 500a or the medal count control CPU 946 is turned off and the power supply of the other is kept on, for example, the total number of inserted coins and the total number of paid coins are counted from a reset state, but the total number of paid coins for consecutively played coins are counted in an accumulated state without being reset. Therefore, information involving accumulation such as the total number of inserted coins, the total number of paid coins, MY (maximum MY), the total number of paid coins for consecutively played coins, and the number of games is managed by one of the CPUs. For example, here, the main CPU 500a manages all such information. With such a configuration, it is possible to avoid inconsistencies in information and to appropriately progress the game.

(Error Priority)
Here, it is assumed that in addition to the error in the main CPU 500a, the medal count control CPU 946 is also set to perform its own error determination process. In such a setting, if an error occurs in the main CPU 500a and the medal count control CPU 946 at the same timing, the error occurring in the main CPU 500a may be given priority and notified by devices such as the main credit display unit 430, the main payout display unit 432, and the speaker 428. Note that specific errors that may occur at the same timing in the main CPU 500a and the medal count control CPU 946 (for example, errors that are determined to have a serious problem such as a backup error or an error indicating that the RAM reading and writing is abnormal) may be set, and if an error occurs at the same timing in the main CPU 500a and the medal count control CPU 946, the specific error may be notified by a device. Also, if multiple errors occur at the same timing in the medal count control CPU 946, the most recently occurring error may be given priority and notified by a device such as the game medal count display device 924. In addition, it is also possible to set priorities for multiple errors in advance, and when multiple errors occur at the same timing in the medal count control CPU 946, the errors may be notified based on the set priorities. By predetermining the priorities for notifying errors in this way, it is possible to respond quickly and effectively according to the urgency and priority of the error. For example, when multiple errors occur, an error with a high priority is notified. Here, when the cause of the error is removed and an error release operation is performed, the error notification with the highest priority at that time is erased, and the error with the next highest priority is sequentially notified. That is, the error notification with the first release operation is erased. In addition, not only in the case where the error notification with the first release operation is controlled to be erased, but also in the case where multiple error notifications with the cause of the error removed are controlled to be erased simultaneously in response to the first release operation. In that case, when the error release operation is performed, multiple error notifications with the cause of the error removed are erased, and the error with the highest priority among the errors with the cause of the error not removed is notified. In addition, an individual device such as a 7-segment device may be installed separately on the medal count control board 920, and if an error occurs in the medal count control CPU 946, the individual device may be used to notify the error instead of or in addition to the game medal count display device 924.

(RAM abnormality)
Furthermore, among errors, processing for RAM abnormalities is performed in a non-used area in the main CPU 500a, and in a used area in the medal count control CPU 946. This is because the main CPU 500a does not have a sufficient capacity for the used area, but the medal count control CPU 946 has a sufficient capacity for the used area. This configuration makes it possible to appropriately progress with the game while suppressing an increase in the memory capacity of the main ROM 500b.

(VL connection signal)
As described with reference to FIG. 254, the game ball etc. dispensing device connection terminal board 948 receives power from the dedicated unit 904, uses the power as input to an insulating element such as a photocoupler, generates a VL connection signal (specific connection signal) indicating the connection state with the dedicated unit 904, and outputs it to the medal count control CPU 946 of the medal count control board 920. The medal count control CPU 946 may or may not transmit a command to the main CPU 500a indicating that it has received the VL connection signal. When the medal count control CPU 946 transmits a command to the main CPU 500a indicating that it has received the VL connection signal, the main CPU 500a can restrict (prohibit) the start of only the main control board 500, only the medal count control board 920, or both the main control board 500 and the medal count control board 920, or stop the progress of the game, depending on whether the command indicates the reception of the VL connection signal. In addition, if the medal count control CPU 946 does not send a command to the main CPU 500a indicating that it has received a VL connection signal, the medal count control CPU 946 can individually restrict (prohibit) the startup of the medal count control board 920 or stop the progress of the game.

If the VL connection signal is ON, the medalless gaming machine 902 can determine that it is properly connected to the dedicated unit 904 and that the power supply of the dedicated unit 904 is ON, and can therefore execute various processes targeted at the main CPU 500a and the dedicated unit 904. On the other hand, if the VL connection signal is OFF, the medalless gaming machine 902 determines that it is not properly connected to the dedicated unit 904 (not connected) or that the power supply of the dedicated unit 904 is OFF, and restricts the progress of the game. Specifically, if the VL connection signal is OFF, the medalless gaming machine 902 executes a game stop process. In this game stop process, the game is restricted as an error state of the main control board 500 (electronic medal bets, electronic medal settlement, processing for game progress based on the operation of the start switch 418, and counting processing are all restricted (prohibited)). At this time, if the VL connection signal is OFF, the main CPU 500a and medal count control CPU 946 may not be started.

Here, the counting process refers to a process of transferring some or all of the electronic medals held in the medal holding section to the dedicated unit 904 in response to the player's operation of the counting switch 922. Specifically, when the counting switch 922 is not being accepted, when the number of game medals in the medal holding section is 0, when the VL connection signal is OFF, and when counting is not possible, the counted medal number (counting value number) is set to "0", and when a short press of the counting switch 922 is accepted, the counted medal number is set to "1". When a long press of the counting switch 922 is accepted, if the number of game medals in the medal holding section is less than 50, all of the electronic medals (game medal number) are set as the counted medal number, and if it is 50 or more, the counted medal number is set to "50". Then, the counted medal number is added to the cumulative counted medal number, and the counting serial number is updated. The medal-less gaming machine 902 executes a checksum to find the sum of the data string of the count notification message, treating it as a string of integer values, and sends a count notification to the dedicated unit 904. In parallel with this, the number of counted medals is subtracted from the number of game medals held in the medal holding section.

Here, if the counting switch 922 is operated while play is possible, the counting process is always executed. "While play is possible" refers to a state in which the medalless gaming machine 902 and the dedicated unit 904 are connected and both are powered on (a state in which a series of operations is possible in which a player borrows an electronic medal, plays a game on the medalless gaming machine 902, and counts the results of the game). Note that if the medalless gaming machine 902 is powered on but the dedicated unit 904 is not, or if the medalless gaming machine 902 and the dedicated unit 904 are not connected, even if the medalless gaming machine 902 accepts the operation of the counting switch 922, there is a risk that the counted medal number will be lost. Therefore, the operation of the counting switch 922 is invalidated, and this period is not included in "while play is possible". Additionally, periods during which the medal-less gaming machine 902 is not (cannot be) used to play on its own, such as during initialization processing after power-on, during settings being changed or checked, and during an error state that requires recovery processing by resetting or the like, are not included in "periods during which play is possible." During periods during initialization processing after power-on, during settings being changed or checked, and during an error state that requires recovery processing by resetting or the like, counting processing may or may not be performed.

In this way, if the VL connection signal is ON, the medalless gaming machine 902 allows play to proceed and accepts counting processing while play is possible. On the other hand, if the VL connection signal is OFF, the medalless gaming machine 902 executes game stop processing and restricts (prohibits) all of the following: betting electronic medals, settling electronic medals, processing for game progress based on operation of the start switch 418, and the counting processing described above. This is because, as described above, if the VL connection signal is OFF, it can be determined that the medalless gaming machine 902 is not properly connected to the dedicated unit 904, or that the power supply to the dedicated unit 904 is OFF.

As described with reference to FIG. 264, the medalless gaming machine 902 (e.g., medal count control CPU 946) transmits a counting notification including information on the counted medal count to the dedicated unit 904. Here, if the medalless gaming machine 902 and the dedicated unit 904 are not properly connected (e.g., not connected) or the dedicated unit 904 is powered off, and the dedicated unit 904 is not properly prepared to receive the counting notification, when the medalless gaming machine 902 receives an input operation (e.g., a pressing operation) of the counting switch 922 and transmits the counting notification to the dedicated unit 904, there is a risk that the counted medal count based on the input operation will be lost. If the counted medal count is lost, the total number of electronic medals will decrease, and an inconsistency in the electronic medals will occur. In this embodiment, an inconsistency refers to a situation in which the total number of digitized medals, which is the sum of the number of game medals and the number of acquired medals, which is the total number of digitized medals held in the dedicated unit 904, differs before and after the input operation of the counting switch 922, due to unintended loss or increase of digitized medals. For example, when the total number of game medals is counted using the counting switch 922, if the number of game medals held in the medal-less gaming machine 902 before counting differs from the number of acquired medals transferred to the dedicated unit 904 by counting, an inconsistency has occurred.

The medalless gaming machine 902 (e.g., medal count control CPU 946) therefore checks whether the dedicated unit 904 is connected or not by checking the ON/OFF state of a VL connection signal indicating the connection status with the dedicated unit 904 before sending a counting notification to the dedicated unit 904. If the VL connection signal is OFF, indicating that the dedicated unit 904 is not connected, the medalless gaming machine 902 sets the counted medal number to "0" to limit the counting process itself.

When the counted medal count is set to "0", the medalless gaming machine 902 updates the gaming medal count by subtracting the counted medal count of "0" from the gaming medal count. In other words, the updated gaming medal count does not substantially change from before the update. The medalless gaming machine 902 displays the updated gaming medal count on the gaming medal count display device 924. Because the gaming medal count does not substantially change, the display on the gaming medal count display device 924 does not change either.

The medalless gaming machine 902 also transmits a counting notification to the dedicated unit 904, including information on the number of counted medals that has been set to "0." If the dedicated unit 904 is not connected, the dedicated unit 904 cannot properly receive the counting notification, and so the number of acquired medals does not change. As the number of acquired medals does not change, the display on the acquired medal count display device 944 does not change either.

In this way, by setting the number of counted medals to "0", both the number of game medals in the medalless gaming machine 902 and the number of medals acquired by the dedicated unit 904 do not change, and the total number of digitized medals does not change either. As a result, the medalless gaming machine 902 does not execute a counting process, and it is possible to prevent digitized medals from disappearing in response to an input operation of the counting switch 922. In other words, the medalless gaming machine 902 is able to avoid inconsistencies in the digitized medals.

Figure 266 is a flow chart showing the flow of the count switch monitoring process in the medal count control CPU 946. The count switch monitoring process is executed when the count switch 922 is pressed. Here, the process related to this embodiment will be explained, and processes unrelated to this embodiment will be omitted. The numerical values of step S in this figure will be used only in the explanation of this figure.

266, when the medal count control CPU 946 detects the pressing of the counting switch 922, specifically, when it detects the ON edge of the counting switch 922 (YES in S1), it acquires a VL connection signal and judges whether the VL connection signal is ON or not (S2). When the VL connection signal is ON (YES in S2), the medal count control CPU 946 starts the timing of the timing counter of the medalless gaming machine 902 (S3). The timing counter starts timing in response to the detection of the ON edge of the counting switch 922, and measures the time from the ON edge to the OFF edge. Next, the medal count control CPU 946 judges whether the OFF edge of the counting switch 922 is detected (S4). When the OFF edge of the counting switch 922 is not detected (NO in S4), the medal count control CPU 946 judges whether a predetermined time (for example, 500 msec) has elapsed since the start of the timing of the timing counter (S5). If the predetermined time has not elapsed (NO in S5), the medal count control CPU 946 returns to the process of step S4. If the predetermined time has elapsed (YES in S5), the medal count control CPU 946 sets the long press flag to ON (S6) and returns to the process of step S4. The long press flag is a flag for identifying a long press; when it is ON, it indicates a long press, and when it is OFF, it indicates that it is not a long press (i.e., a short press).

When the OFF edge of the counting switch is detected (YES in S4), the medal count control CPU 946 determines whether the long press flag is OFF or not (S7). When the long press flag is OFF (YES in S7), the medal count control CPU 946 sets the counted medal count to "1" and proceeds to processing in step S9. The set counted medal count is stored in a specified register or RAM. When the long press flag is ON (NO in S7), the medal count control CPU 946 proceeds to processing in step S9. In step S9, the medal count control CPU 946 clears (sets OFF) the long press flag. The medal count control CPU 946 clears the timing counter and ends the counting switch monitoring processing.

If the ON edge of the counting switch 922 is not detected (NO in S1), the counting switch monitoring process ends without executing any processing. If the VL connection signal is OFF (NO in S2), the medal count control CPU 946 sets the counted medal number to "0" (S11) and ends the counting switch monitoring process. The counted medal number "0" is stored in a specified register or RAM. In other words, even if the counting switch 922 is pressed, if the VL connection signal is OFF, the counted medal number is set to "0" and the player's operation to count the electronic medals is not accepted, or if accepted, is invalidated.

Figure 267 is a flowchart showing the flow of the counting process in the medal count control CPU 946. The counting process is a process related to updating the count of the number of game medals, and is executed at interrupt timings that are repeated at a predetermined cycle (e.g., every 300 ms) regardless of whether the count switch 922 is pressed. Here, the process related to this embodiment will be explained, and processes that are not related to this embodiment will be omitted. The numerical values of step S in this figure will be used only in the explanation of this figure.

As shown in FIG. 267, when an interrupt timing occurs, which is repeated at a predetermined cycle, the medal count control CPU 946 acquires a VL connection signal and determines whether the VL connection signal is ON or not (S21). If the VL connection signal is ON (YES in S21), the medal count control CPU 946 proceeds to processing of step S23. If the VL connection signal is OFF (NO in S21), the medal count control CPU 946 sets the counted medal number to "0" (S22) and proceeds to processing of step S23. The counted medal number "0" is stored in a predetermined register or RAM. In step S23, the medal count control CPU 946 acquires the current game medal number from the medal holding unit (S23).

Next, the medal count control CPU 946 judges whether the long press flag is ON (S24). If the long press flag is ON (YES in S24), the medal count control CPU 946 judges whether the game medal count acquired in step S23 is "50" or more (S25). If the game medal count is "50" or more (YES in S25), the medal count control CPU 946 sets the count medal count to "50" (S26) and proceeds to processing of step S28. If the game medal count is less than "50" (NO in S25), the medal count control CPU 946 sets the game medal count to the count medal count (S27) and proceeds to processing of step S28. The count medal count set in step S26 or step S27 is stored in a predetermined register or RAM. Also, if the long press flag is OFF (NO in S24), the process proceeds to processing of step S28.

In step S28, the medal count control CPU 946 acquires the latest stored medal count from the register or RAM in which the medal count is stored (S28). For example, assume that immediately before the current counting process, the count switch monitoring process (see FIG. 266) is performed and the medal count is set to "1". In this case, in step S28 of the counting process (see FIG. 267), the medal count control CPU 946 acquires the medal count "1" stored in a predetermined register or RAM. Also, if the medal count is set to "50" in step S26 of the current counting process, the medal count control CPU 946 acquires the medal count "50" stored in a predetermined register or RAM. Also, if the medal count is set to a medal count less than "50" in step S27 of the current counting process, the medal count control CPU 946 acquires the medal count less than "50" stored in a predetermined register or RAM as the medal count. Furthermore, if the counted medal count is set to "0" in step S11 of the count switch monitoring process (see FIG. 266) or in step S22 of the counting process (see FIG. 267), the medal count control CPU 946 acquires the counted medal count "0" stored in a specified register or RAM.

Next, the medal count control CPU 946 updates the game medal count by subtracting the acquired count medal count from the acquired game medal count (S29). For example, if the acquired count medal count is "1", the medal count obtained by subtracting "1" from the acquired current game medal count becomes the updated (subtracted) game medal count. If the acquired count medal count is "50", the medal count obtained by subtracting "50" from the acquired current game medal count becomes the updated game medal count. If a game medal count less than "50" is acquired as the count medal count, all game medal counts less than "50" as the count medal count are subtracted from the acquired current game medal count, and the updated game medal count becomes "0". If the acquired count medal count is "0", the medal count obtained by subtracting "0" from the acquired current game medal count becomes the updated game medal count. In other words, if the count medal count is "0", the game medal count does not change substantially.

Next, the medal count control CPU 946 updates the display of the number of game medals on the game medal count display device 924 to the number of game medals derived in step S29 (S30). Next, the medal count control CPU 946 generates a count notification including information on the acquired counted medal number and transmits it to the dedicated unit 904 (S31). Next, the medal count control CPU 946 clears the counted medal number in response to completion of the count notification (S32), and ends the counting process.

In this way, the medal count control CPU 946 checks whether the VL connection signal is ON/OFF, and if the VL connection signal is OFF, it sets the counted medal count to "0". Therefore, if the VL connection signal is OFF, even if the count switch 922 is pressed, the updated game medal count does not substantially change from the game medal count before the update. Also, if the VL connection signal is OFF, the dedicated unit 904 cannot properly receive the count notification, so the number of acquired medals does not change. Therefore, even if a count notification is sent when the dedicated unit 904 is not properly prepared to receive the count notification, in the medalless gaming machine 902, the electronic medals do not disappear or increase, and inconsistencies in the electronic medals can be avoided.

In addition, as shown in FIG. 266, the medal count control CPU 946 sets the counted medal count to "0" immediately before updating the game medal count, in other words, immediately before sending the count notification. Therefore, in the medalless gaming machine 902, the counted medal count can be more reliably set to "0", and inconsistencies in the electronic medals can be more reliably avoided.

The medalless gaming machine 902 judges whether the VL connection signal is ON/OFF in both the counting switch monitoring process and the counting process, and sets the counted medal count to "0" if the VL connection signal is OFF. As a result, for example, the counted medal count is set to "0" at the timing of the VL connection signal judgment process executed first after the VL connection signal turns OFF, out of the VL connection signal judgment process in the counting switch monitoring process and the VL connection signal judgment process in the counting process, so the counted medal count can be set to "0" early. In addition, since the medalless gaming machine 902 judges whether the VL connection signal is ON/OFF in both the counting switch monitoring process and the counting process, there are two opportunities to judge whether the VL connection signal is ON/OFF, and the counted medal count can be set to "0" more reliably than in a mode in which there is only one opportunity to judge whether the VL connection signal is ON/OFF.

In addition, in the medalless gaming machine 902, the medal count control CPU 946 performs count switch monitoring processing and counting processing. The storage capacity of the ROM or RAM (storage unit) in the medal count control board 920 is smaller than that of the main ROM 500b or main RAM 500c (storage unit), but the processing load is small, so the free space is large as a result. Therefore, even if a program performs the ON/OFF determination of the VL connection signal and the processing of setting the count medal number to "0" when the VL connection signal is OFF in both the count switch monitoring processing and the counting processing, it does not put a strain on the storage capacity of the medal count control board 920.

The medalless gaming machine 902 may determine whether the VL connection signal is ON/OFF in either the counting switch monitoring process or the counting process, and may omit the ON/OFF determination of the VL connection signal in the other process. In this case, it is more preferable to omit the ON/OFF determination of the VL connection signal in the counting switch monitoring process, and to determine whether the VL connection signal is ON/OFF in the counting process. Also, in the medalless gaming machine 902, it is sufficient that the ON/OFF determination of the VL connection signal is performed before updating the number of game medals or notifying the count, and if the VL connection signal is OFF, the counted medal number is set to "0", and is not limited to the form in which the ON/OFF of the VL connection signal is determined in the counting switch monitoring process or the counting process.

(Counting process 1)
As described above, the medal count control CPU 946 of the medalless gaming machine 902 performs counting processing to transfer at least a portion of the electronic medals held in the medal holding section to the dedicated unit 904 in response to the player's operation of the counting switch 922.

Figure 268 is a timing chart for explaining the counting process. Here, the medal count control CPU 946 measures the time during which the counting switch 922 is continuously operated in order to grasp the counting mode (short press or long press) desired by the player. For example, as shown in Figure 268 (a), when the counting switch 922 is short pressed, that is, an operation of less than 500 msec is accepted (time point a), the count medal number is set to "1". When the 300 msec cycle (predetermined transmission cycle) by the timer interrupt shown in Figure 264 arrives (time point b), "1" is subtracted from the game medal number. Here, it is assumed that the game medal number is "29" by subtracting "1" from "30". The count medal number and the game medal number are variables held in the RAM by the medal count control CPU 946. Then, the medalless gaming machine 902 transmits a counting notification to the dedicated unit 904. When the dedicated unit 904 receives the count notification, it adds the number of counted medals indicated in the count notification (here, "1") to the number of medals won (e.g., "0"), and displays the result of the addition (e.g., "1") on the medal count display device 944.

For example, as shown in FIG. 268(b), when the player continues to operate the counting switch 922 and a 300 msec cycle arrives (time point c), if the counting switch 922 is pressed and held, i.e., the operation is continued for 500 msec or more, if the number of game medals in the medal holding section is 50 or more, the counted medal number is set to "50", and if the number of game medals is less than 50, the total number is set as the counted medal number. Here, it is assumed that the number of game medals is "30", and the total number "30" is set as the counted medal number by pressing and holding. Accordingly, the total number of game medals "30" is subtracted, and the game medal number becomes "0". Then, the medalless gaming machine 902 transmits a counting notification to the dedicated unit 904, and clears the counted medal number (sets it to "0"). When the dedicated unit 904 receives the count notification, it adds the number of counted medals indicated in the count notification (here, "30") to the number of medals won (e.g., "0"), and displays the result of the addition (e.g., "30") on the medal count display device 944.

As described above, if the counting switch 922 is operated while play is possible, the counting process is always executed. Therefore, if the player operates the counting switch 922 while play is in progress, the payout of electronic medals in the progress of the game and the counting process may be executed in quick succession. For example, as shown in FIG. 268(c), when the number of game medals is "30", a small prize is won as the game progresses, and 15 electronic medals are paid out (time point d). The medal number control CPU 946 receives a payout end command including the number of paid out medals, and adds the number of paid out medals "15" to the number of game medals "30" to update the number of game medals to "45". At this time, the player continues to operate the counting switch 922, and when the 300 msec cycle arrives (time point e), the medal count control CPU 946 accepts a long press of the counting switch 922, i.e., an operation that continues for 500 msec or more, and sets all electronic medals (here, "45") as the counted medal count. Accordingly, the game medal count "45" is all subtracted, and the game medal count becomes "0". The medalless gaming machine 902 then transmits a counting notification to the dedicated unit 904 and clears the counted medal count. Upon receiving the counting notification, the dedicated unit 904 adds the counted medal count (here, "45") indicated in the counting notification to the earned medal count (for example, "0"), and displays the result of the addition (for example, "45") on the earned medal count display device 944.

Here, the counting process is executed immediately after the electronic medals are paid out, depending on the timing of the winning of the minor prize and the operation of the counting switch 922. Therefore, the number of game medals changes each time from "30" to "45" to "0". However, if the payout process and counting process of the electronic medals are executed consecutively within the 300 msec period in which the counting notification is sent, the counting notification will notify only the result. Therefore, regardless of the change in the number of game medals from "30" to "45" to "0", the dedicated unit 904 will only display the change in the number of earned medals from "0" to "45" on the earned medal number display device 944.

As shown in FIG. 268, when the cycle for sending a counting notification arrives, the medal count control CPU 946 transmits a part or all of the game medal count (here, the whole, "45") to the dedicated unit 904 as the counted medal count, if the counting switch 922 has been continuously operated for a predetermined time (e.g., 500 msec) or more, regardless of the timing when the number of game medals changes, i.e., the timing when the electronic medal payout process or counting process is executed, and without waiting for the change in the game medal count due to the electronic medal payout process to be displayed on the game medal count display device 924. Therefore, even if the payout process and the counting process of the electronic medals overlap, depending on the timing, a period for transmitting a counting notice may arrive, and the number of game medals may change from "30" to "0" as a result of a long press, and "30" may be transmitted to the dedicated unit 904 as the counted medal number, and then the payout process of the electronic medals may change the number of game medals from "0" to "15", and again a period for transmitting a counting notice may arrive, and the number of game medals may change from "15" to "0" as a result of a long press, and "15" may be transmitted to the dedicated unit 904 as the counted medal number. In this case, the display content of the acquired medal number display device 944 may change from "0" to "30" to "45", and as shown in FIG. 268(c), the display content of the acquired medal number display device 944 may also change from "0" to "45". However, since the player has already started counting the number of game medals by pressing and holding the count switch 922, it is sufficient for the player to confirm that the display content of the acquired medal count display device 944, which was "0," has finally become "45," including the number of game medals and the number of paid-out electronic medals. Therefore, differences in the manner in which the number of game medals displayed on the acquired medal count display device 944 changes do not affect the progress of the game.

Here, regardless of the timing of the change in the number of game medals, if the counting switch 922 has been operated continuously for a predetermined time (e.g., 500 msec) or more when the cycle for sending a counting notification arrives, the medal count control CPU 946 transmits some or all of the game medal count (here, "45") to the dedicated unit 904. This allows the player to quickly grasp the final number of medals won without having to unnecessarily wait for the display update of the medal count display device 944, and to quickly begin the next operation, thereby improving the operability of the medalless gaming machine 902.

In addition, here, the medal count control CPU 946 always accepts operation of the counting switch 922 regardless of the number of game medals (even if the number of game medals is "0"), and measures the time that the counting switch 922 is continuously operated.

For example, if the number of game medals is "0", the count notification will show the number of counted medals as "0" regardless of whether the counting process has been performed. Therefore, if the number of game medals is "0", it is conceivable that the counting process will not be performed, or that the time during which the counting switch 922 is continuously operated will not be measured. However, as shown in FIG. 268(c), if a payout process for electronic medals occurs, even if the number of game medals before the payout process was "0", the counting process can be performed on the paid-out electronic medals (number of game medals). In this case, if the time during which the counting switch 922 was continuously operated is measured for the first time after the number of game medals becomes a number other than "0" (after the payout process is completed), the counting process will be delayed accordingly, resulting in poor operability.

Here, the medal count control CPU 946 is configured to count the time that the count switch 922 is continuously operated regardless of the number of game medals, so that it can reliably determine that a long press has been performed when the period for sending a count notification arrives, allowing the player to quickly determine the final number of medals won and to quickly begin the next operation, improving the operability of the medalless gaming machine 902. In addition, the program executed by the medal count control CPU 946 does not require a determination (branch) as to whether the number of game medals is "0", which reduces the processing load and makes it possible to reduce memory capacity.

The period (e.g., 300 msec) at which the medal count control CPU 946 sends the count notification and the period (a predetermined display period by timer interrupt: e.g., 1 msec) at which the display of the game medal count display device 924 is updated are managed independently. Therefore, depending on the time relationship between the timing of the payout process and counting process of the electronic medals described above and the display update timing of the game medal count display device 924, the display mode of the game medal count on the game medal count display device 924 will differ.

Figure 269 is a timing chart for explaining the display mode of the number of game medals. Here, as shown in Figure 268 (c), it is assumed that a small win occurs as the game progresses, and 15 electronic medals are paid out. In parallel with this, the player continues to operate the counting switch 922, and when a 300 msec period arrives, the medal count control CPU 946 accepts a long press of the counting switch 922, that is, an operation that continues for 500 msec or more, and sets all electronic medals (here, "45") as the number of counted medals. Here, the number of game medals changes from "30" to "45" due to the electronic medal payout process, and from "45" to "0" due to the counting process. In addition, in the dedicated unit 904, the number of medals acquired changes from "0" to "45" due to the counting process.

For example, as shown in FIG. 269(a), assume that the display content of the game medal count display device 924 is updated (changed) between the payout process and the counting process of the electronic medals. Then, in response to the change in the game medal count from "30" to "45" due to the payout process of the electronic medals, the medal count control CPU 946 changes the display of the game medal count on the game medal count display device 924 from "30" to "45" when the period for updating the display of the game medal count display device 924 arrives (time f). Similarly, in response to the change in the game medal count from "45" to "0" due to the counting process, the medal count control CPU 946 changes the display of the game medal count on the game medal count display device 924 from "45" to "0" when the period for updating the display of the game medal count display device 924 arrives (time g).

Here, the display contents of the game medal count display device 924 are updated after the electronic medal payout process and the counting process are executed. Therefore, as the game medal count changes from "30" to "45" to "0", the display of the game medal count display device 924 also changes from "30" to "45" to "0". In this case, the player can understand through the game medal count display device 924 that the game medal count has changed from "30" to "45" to "0".

For example, as shown in FIG. 269(b), assume that both the payout process and the counting process of the electronic medals are executed during the period in which the display of the game medal count display device 924 is updated. In this case, the medal count control CPU 946 changes the game medal count from "30" to "45" by the payout process of the electronic medals, and from "45" to "0" by the counting process. However, when the period in which the display of the game medal count display device 924 is updated arrives (time point h), the game medal count has already become "0", so the medal count control CPU 946 directly changes the display of the game medal count on the game medal count display device 924 from "30" to "0".

Here, the display contents of the game medal count display device 924 are updated after both the electronic medal payout process and the counting process have been executed. Therefore, the game medal count increases from "30" to "45" and then decreases to "0", while the display of the game medal count display device 924 immediately decreases from "30" to "0". In this case, the player understands through the game medal count display device 924 that the game medal count has changed from "30" to "0".

If we try to have the player understand through the game medal count display device 924 that the number of game medals has changed stepwise, such as from "30" to "45" to "0," the medal count control CPU 946 must wait for the display content of the game medal count display device 924 to be updated before performing the counting process, which delays the counting process accordingly. Note that in order to have the player recognize the update of the display of the game medal count display device 924, it is necessary to extend the display time to a degree that allows the player to recognize it, which delays the counting process accordingly and reduces operability.

Here, as shown in FIG. 269, the medal count control CPU 946 transmits a part or all of the game medal count (here, all of it, "45") to the dedicated unit 904 as the count medal count when the period for transmitting the count notification arrives, regardless of whether the display content of the game medal count display device 924 has been updated in response to the change in the game medal count. Therefore, when the game medal count changes from "30" to "45" to "0", the game medal count on the game medal count display device 924 may change from "30" to "45" to "0" as shown in FIG. 269(a), or the game medal count on the game medal count display device 924 may change from "30" to "0" as shown in FIG. 269(b). However, since the player has already started counting the game medal count by pressing and holding the count switch 922, it is sufficient to confirm that the display content of the game medal count display device 924, which was "30", has finally become "0". Furthermore, the player only needs to be able to confirm that the display content of the acquired medal count display device 944, which was "0," has finally become "45," including the number of game medals and the number of electronic medals paid out. Therefore, differences in the manner in which the number of game medals displayed on the game medal count display device 924 changes do not affect the progress of the game.

Here, regardless of the timing of the change in the number of game medals, if the counting switch 922 has been operated continuously for a predetermined time (e.g., 500 msec) or more when the cycle for sending a counting notification arrives, the medal count control CPU 946 transmits at least a portion of the game medal count (here, "45") to the dedicated unit 904. This allows the player to quickly grasp the final game medal count and quickly begin the next operation without having to unnecessarily wait for the display update of the game medal count display device 924, thereby improving the operability of the medalless gaming machine 902.

Note that, although an example has been given in which the payout process and counting process of electronic medals are executed consecutively in Figures 268 and 269, changes in the number of game medals are not limited to such processes, and can include various processes such as the insertion process of electronic medals.

(Counting process 2)
As described with reference to FIG. 264, the medalless gaming machine 902 (e.g., medal count control CPU 946) transmits a gaming machine information notification to the dedicated unit 904 at a predetermined cycle (e.g., every 300 msec). In addition, the medalless gaming machine 902 transmits a counting notification to the dedicated unit 904 100 msec after transmitting the gaming machine information notification to the dedicated unit 904. In other words, the medalless gaming machine 902 transmits a counting notification including information on the counted medal number to the dedicated unit 904 at a predetermined cycle (e.g., every 300 msec), similar to the gaming machine information notification.

The counting switch 922 is an input operation unit that accepts a predetermined input operation (e.g., a pressing operation) by the player. The medalless gaming machine 902 (e.g., medal count control CPU 946) is capable of receiving a signal indicating the input operation from the counting switch 922 (input operation unit). Based on the signal received from the counting switch 922, the medalless gaming machine 902 sets the counted medal count as described below. The medalless gaming machine 902 updates the gaming medal count by subtracting the set counted medal count from the current gaming medal count at the above-mentioned predetermined period (e.g., 300 msec), and updates the display of the gaming medal count display device 924 to the updated gaming medal count at a period (e.g., 1 msec) different from the predetermined period.

When the update of the number of game medals is completed, the display content of the game medal count display device 924 is updated immediately, for example, in 1 msec, so that the display content is updated approximately at a predetermined cycle (for example, 300 msec). As a result, the medalless gaming machine 902 changes the display content of the game medal count display device 924 (i.e., the number of game medals displayed by the game medal count display device 924) based on the signal received from the counting switch 922, essentially at a predetermined cycle (for example, 300 msec).

The medalless gaming machine 902 also transmits a counting notification including information on the set number of counted medals to the dedicated unit 904 at the above-mentioned predetermined period (e.g., 300 msec). In other words, the medalless gaming machine 902 outputs a counting notification to the outside based on the signal received from the counting switch 922 at a predetermined period.

The dedicated unit 904 also updates the number of medals won based on the counting notification received, and updates the display of the won medal count display device 944 to the updated number of medals won at a period (e.g., 1 msec) different from the predetermined period as needed. When the dedicated unit 904 completes updating the number of medals won based on the counting notification, the display content of the won medal count display device 944 is updated immediately, for example, in 1 msec, so that the display content is updated at approximately the predetermined period (e.g., 300 msec). For this reason, the dedicated unit 904 updates the display on the won medal count display device 944 substantially at the predetermined period (300 msec) based on the counting notification received from the medalless gaming machine 902.

Here, it is possible that the player may press the counting switch 922 quickly and consecutively multiple times. In such a case, the medalless gaming machine 902 may receive (be input) a signal indicating a pressing operation multiple times during one period (e.g., within 300 msec) of a predetermined period (e.g., 300 msec period). The medalless gaming machine 902 ensures that the display on the dedicated unit 904 is performed appropriately even if such multiple pressing operations are performed during one period.

Specifically, when the medalless gaming machine 902 (e.g., medal count control CPU 946) receives a signal from the counting switch 922 multiple times during one cycle, it validates only one of the multiple signals. More specifically, even if the medalless gaming machine 902 receives a signal from the counting switch 922 multiple times during one cycle, it sets the counted medal number corresponding to the pressing operation of the counting switch 922 to a fixed "1". Then, based on the one valid signal (more specifically, based on the counted medal number of "1"), the medalless gaming machine 902 updates the display on the gaming medal count display device 924 and outputs a signal (e.g., a counting notification) to the outside.

Figure 270 is a flow chart showing the flow of count switch processing in the medal count control CPU 946. The count switch processing is executed when the count switch 922 is pressed. The count switch processing corresponds to the processing of steps S3 to S10 that are performed when step S1 in Figure 266 is YES. Here, the processing related to this embodiment will be explained, and processing that is not related to this embodiment will be omitted. The numerical values of step S in this figure will be used only in the explanation of this figure.

As shown in FIG. 270, when the medal count control CPU 946 detects the pressing of the count switch 922 (specifically, when the ON edge of the count switch 922 is detected), it starts the timing of the timing counter of the medalless gaming machine 902 (S3). The medal count control CPU 946 judges whether or not the OFF edge of the count switch 922 is detected (S4). If the OFF edge of the count switch 922 is not detected (NO in S4), the medal count control CPU 946 judges whether or not a predetermined time (e.g., 500 msec) has elapsed since the start of timing of the timing counter (S5). If the predetermined time has not elapsed (NO in S5), the medal count control CPU 946 returns to the processing of step S4. If the predetermined time has elapsed (YES in S5), the medal count control CPU 946 sets the long press flag to ON (S6) and returns to the processing of step S4.

When the OFF edge of the counting switch is detected (YES in S4), the medal count control CPU 946 judges whether or not the long press flag is OFF (S7). When the long press flag is OFF (YES in S7), the medal count control CPU 946 sets the counted medal count to "1" and proceeds to processing in step S9. The set counted medal count is stored in a specified register or RAM. When the long press flag is ON (NO in S7), the medal count control CPU 946 proceeds to processing in step S9. In step S9, the medal count control CPU 946 clears (sets OFF) the long press flag. The medal count control CPU 946 clears the time counter and ends the counting switch processing. Here, in step S8, the counted medal count is not incremented by "+1", but is instead set to "1".

Figure 271 is a time chart explaining the setting of the counted medal number. As shown in Figure 271, for example, at time point a, the number of game medals is "50", a counting notification including information that the counted medal number is "0" is sent from the medalless gaming machine 902 to the dedicated unit 904, and the number of acquired medals is "50". Then, from time point a until one cycle's worth of 300 msec has elapsed, the counting switch 922 is pressed three times.

The above-mentioned counting switch process starts at the ON edge of the pressing operation of the counting switch 922, and at the OFF edge of the pressing operation, if it is a short press, the counted medal number is set to "1". Since the counted medal number is repeatedly set to "1" each time the counting switch 922 is short pressed, for example, even if it is the third short press in one cycle, the counted medal number is set to "1" rather than "3".

At time b when one cycle's worth of 300 msec has elapsed from time a, as described above with reference to FIG. 267, the medalless gaming machine 902 subtracts the set count medal number "1" from the current gaming medal number "50" to derive the gaming medal number "49". The medalless gaming machine 902 updates the display of the gaming medal number on the gaming medal number display device 924 from "50" to "49". In this way, even if a pressing operation is performed three times during one cycle, if the number immediately prior to the display update on the gaming medal number display device 924 is, for example, "50", it is not updated to "47", but rather updated to "49".

At time b, the medalless gaming machine 902 transmits a counting notification including information on the counted medal number of "1" to the dedicated unit 904. Upon receiving the counting notification, the dedicated unit 904 adds the received counted medal number of "1" to the number of acquired medals of "50" to derive the number of acquired medals of "51". The dedicated unit 904 updates the display of the number of acquired medals on the acquired medal number display device 944 from "50" to "51". In this way, even if a pressing operation is performed three times during one cycle, if the number immediately prior to the display update of the acquired medal number display device 944 is, for example, "50", the display is updated to "51" rather than to "53".

That is, even if the pressing operation is performed multiple times during one cycle, the medal count control CPU 946 can update the display of the acquired medal count display device 944 of the dedicated unit 904 to increase by 1 every predetermined cycle (e.g., 300 msec) by setting the counted medal count to "1". For example, the display content of the acquired medal count display device 944 does not jump from "50" to "53", but changes continuously by 1, such as from "50" to "51". Therefore, in the medal-less gaming machine 902, the acquired medal count can be appropriately displayed on the acquired medal count display device 944 of the dedicated unit 904, and distrust from the player can be suppressed.

In the above medal-less gaming machine 902, when a signal (e.g., an ON edge) of the counting switch 922 is received (input) multiple times during one cycle, only one of the multiple signals is considered valid. However, when the medal-less gaming machine 902 receives a signal (e.g., an ON edge) of the counting switch 922 multiple times during one cycle, all of the multiple received signals may be processed as valid.

Figure 272 is a flowchart showing the flow of counting switch processing in a modified example in which all multiple signals are processed effectively. The flowchart in Figure 272 differs from the flowchart in Figure 270 in that step S8 in the flowchart in Figure 270 has been changed to step S18, but the other steps are the same as the flowchart in Figure 270.

As shown in FIG. 272, if the long press flag is OFF (YES in S7), the medalless gaming machine 902 increments the counted medal number by "+1" (increments by 1).

Figure 273 is a time chart that explains how to set the number of counted medals in a modified example in which all multiple signals are processed effectively. As shown in Figure 273, assume that the counting switch 922 is pressed three times from time point c until one cycle's worth of 300 msec has elapsed.

The counting switch process in this modified example begins with the ON edge of the pressing operation of the counting switch 922, and at the OFF edge of the pressing operation, if the pressing operation is a short press, the counted medal number is incremented by "+1". Therefore, each time the counting switch 922 is short pressed during one cycle, the counted medal number increases by "1". For example, at the second OFF edge during one cycle, the counted medal number is set to "2", and at the third OFF edge during one cycle, the counted medal number is set to "3".

At time d, when one cycle's worth of 300 msec has elapsed since time c, as described above with reference to FIG. 267, the medalless gaming machine 902 subtracts the set count medal number "3" from the current medal number "50" to derive the medal number "47". The medalless gaming machine 902 updates the display of the medal number on the medal number display device 924 so that it decreases by "1" in sequence, such as "50" → "49" → "48" → "47".

At time d, the medalless gaming machine 902 has been pressed three times during one cycle, and thus transmits a counting notification including information on the counted medal number "3" to the dedicated unit 904. Upon receiving the counting notification, the dedicated unit 904 adds the received counted medal number "3" to the number of earned medals "50" to derive the number of earned medals "53". The dedicated unit 904 updates the display of the number of earned medals on the earned medal number display device 944 so that it increases by "1" in succession, such as "50" → "51" → "52" → "53".

In this way, even in the modified example in which all multiple signals are effectively processed, the number of medals won can be properly displayed on the medal count display device 944 of the dedicated unit 904.

(Communication between the main CPU and the medal count control CPU)
The communication between the medal-less gaming machine 902 and the dedicated unit 904 has been described above. However, specifically, in parallel with the serial communication between the medal count control CPU 946 and the dedicated unit 904 described above, the main CPU 500a and the medal count control CPU 946 communicate serially inside the medal-less gaming machine 902, and the medal count control CPU 946 acquires information by sending and receiving commands to the main CPU 500a, and notifies the above-mentioned dedicated unit 904 of information based on the acquired information. Note that the serial communication has a communication speed of, for example, 125,000 bps, and each byte of data is represented by a 1-bit start bit, 8-bit data bits, and 1-bit stop bit. Here, the communication between the main CPU 500a and the medal count control CPU 946, which is the first stage of notification between the medal count control CPU 946 and the dedicated unit 904, will be described in detail.

The main CPU 500a transmits a predetermined command to the medal count control CPU 946. For example, the main CPU 500a may transmit a standby command consisting of identification information for identifying the command, transmission information indicating the requested number of medals to be inserted, and a checksum to the medal count control CPU 946 during standby before the start switch 418 for the next game is operated after the game ends. The main CPU 500a may also transmit a game medal insertion command consisting of identification information, transmission information indicating the requested number of medals to be inserted, and a checksum to the medal count control CPU 946 when the bet switch 416 is operated. The main CPU 500a may also transmit a start command consisting of identification information, transmission information indicating the requested number of medals to be inserted, and a checksum to the medal count control CPU 946 when the start switch is operated. The main CPU 500a may also transmit a payout end command consisting of identification information, transmission information indicating the payout number, and a checksum to the medal count control CPU 946 when the payout is completed. Furthermore, the main CPU 500a may transmit a one-game end command consisting of identification information, role ratio-related transmission information, and a checksum to the medal count control CPU 946 at the end of one game. Furthermore, the main CPU 500a may transmit a startup command consisting of identification information, transmission information required at startup, role ratio-related transmission information, and a checksum to the medal count control CPU 946 at startup. Furthermore, the main CPU 500a may transmit a change command consisting of identification information and a checksum to the medal count control CPU 946 when the internal state changes, when an error occurs, or when an error is cleared. The length of the above-mentioned command can be set arbitrarily.

Now, let us assume that the command that the main CPU 500a sends to the medal count control CPU 946 is variable length. In that case, when the medal count control CPU 946 starts receiving the command, the length of the command is unknown, so it is unclear how long the command reception state should be maintained for, or at what point in time the command analysis should begin. When the command is made variable length in this way, the identification information indicates what type of command it is and how many bytes long it is, allowing the medal count control CPU 946 to easily understand the command.

In addition, for example, if there is a bit in the identification information to which no information is assigned, that bit can be assigned to the "replay status," which is information required by the medal count control CPU 946. In this way, the free space in the transmission data can be effectively utilized, and it is not necessary to generate a separate program that generates and transmits a one-byte command for the replay status.

The medal count control CPU 946 also transmits a specified command to the main CPU 500a. For example, when the medal count control CPU 946 receives the above commands (standby command, medal insertion command, start command, payout completion command, and startup command) from the main CPU 500a, it may transmit a reply command consisting of identification information, transmission information indicating the number of medals that can be inserted and the number of medals used, and a checksum to the main CPU 500a. Note that the medal count control CPU 946 does not transmit a reply command in response to a game end command or a change command.

Let us assume that a specific bit of the identification information of the reply command is associated with an "ACK" indicating that the medal count control CPU 946 has normally received the command sent from the main CPU 500a. This "ACK" is processed independently of other bits. For example, if the specific bit of the identification information is 1, the main CPU 500a can proceed to the next game process regardless of the contents of the other bits. Also, if a bit other than the specific bit is set, the main CPU 500a performs the process corresponding to the set bit while continuing the game. This configuration makes it possible to effectively use the area of the identification information and increase the efficiency of information transfer.

In addition, such communication between the main CPU 500a and the medal count control CPU 946 may be performed at all times, or a predetermined limit may be set. For example, two-way communication between the main CPU 500a and the medal count control CPU 946 may be started when the winning type lottery or AT lottery is completed by operating the start switch 418, and may be limited when one game ends. In this embodiment, when the start switch 418 is operated, a random number is acquired (latched) from the random number generator 500d, and is used as a winning type lottery random number for the winning type lottery or for the AT lottery. Here, communication between the main CPU 500a and the medal count control CPU 946 is not performed until the winning type lottery or AT lottery is completed by operating the start switch 418, and communication is started when the winning type lottery or AT lottery is completed by operating the start switch 418. This eliminates the risk that the communication between the main CPU 500a and the medal count control CPU 946 will affect the latch timing of the random number, and makes it possible to appropriately acquire the random number.

When the main CPU 500a and the medal count control CPU 946 are provided separately as in Figures 254(a) and 254(b), they transmit information using commands via the serial communication described above. On the other hand, when the main CPU 500a manages the electronic medals used in games instead of the medal count control CPU 946 as in Figure 254(c), the information is held as a common internal variable in the main RAM 500c.

(Command Management)
As described above, the main CPU 500a transmits a number of types of commands (standby command, command when a game medal is inserted, start command, command when payout is completed, command when one game is completed, command when booting, and command when changed) as information to the medal count control CPU 946. In addition, a reply command is transmitted from the medal count control CPU 946 to the main CPU 500a. If the main CPU 500a normally receives the reply command and the content of the reply command indicates "ACK", it is determined that communication between the main CPU 500a and the medal count control CPU 946 has been normally completed and the process can proceed to the next step.

However, communication between the main CPU 500a and the medal count control CPU 946 is not always completed normally. For example, the main CPU 500a may send a command normally, but for some reason the medal count control CPU 946 may not receive the command normally. Also, the medal count control CPU 946 may receive a command from the main CPU 500a normally and send a reply command to that command normally, but for some reason the main CPU 500a may not receive the reply command normally. In either case, however, the main CPU 500a cannot determine whether the medal count control CPU 946 received the command normally. Therefore, in order to proceed with the process, the main CPU 500a will resend the command it sent immediately before to the medal count control CPU 946.

Here, we will explain an example of a case where the transmission of the payout end command is not completed normally. In the former case, i.e., when the main CPU 500a transmits the command normally but the medal count control CPU 946 cannot receive the command normally, the medal count control CPU 946 has not effectively processed the payout end command itself. Therefore, even if the main CPU 500a resends the payout end command, no problem will occur as long as the medal count control CPU 946 can receive the resent payout end command normally.

However, in the latter case, that is, when the medal count control CPU 946 normally receives a command from the main CPU 500a and normally transmits a reply command to that command, but the main CPU 500a is unable to normally receive the reply command, it is highly likely that the medal count control CPU 946 is validly processing the payout end command. For example, suppose that the medal count control CPU 946 normally receives the payout end command and adds the payout number included in the payout end command to the game medal count. The medal count control CPU 946 normally transmits the reply command, but is unable to grasp whether the main CPU 500a normally received the reply command. Then, if the main CPU 500a is unable to normally receive the reply command and resends the payout end command, and the medal count control CPU 946 normally receives the payout end command, there is a risk that the payout number included in the payout end command will be further added to the game medal count. In this case, the number of electronic medals paid out will be repeatedly added to the number of game medals for each payout trigger, and the player will obtain unfair gaming profits. Also, if the harness between the main control board 500 and the medal count control board 920 is manipulated to send the payout end command illegally multiple times, an event similar to the above may occur in which the number of payout medals is repeatedly added to the number of game medals.

Therefore, in this embodiment, the command sent from the main CPU 500a to the medal count control CPU 946 is appropriately validated only once. Specifically, when the medal count control CPU 946 receives the same type of command (first information) continuously from the main CPU 500a (external), it invalidates the same type of command received from the second time onwards and does not process the command. Here, the command refers to the above-mentioned waiting command, game medal insertion command, start command, payout end command, one game end command, startup command, and change command. For example, if a payout end command is received without receiving any other command after a payout end command, it means that the same type of command has been received continuously. Note that when the same type of command is received from the main CPU 500a two or more times in succession, the same type of command received from the second time onwards is not necessarily invalidated. For example, if a specific command of the same type is received two or more times in succession under a specific situation that allows for the continuous reception of commands, such as when a 1 bet switch is operated two or more times in succession, the medal count control CPU 946 may process the second and subsequent commands of the same type validly.

In addition, when the medal count control CPU 946 receives a predetermined command (first information) from the main CPU 500a, it may invalidate the predetermined command received after the first received predetermined command until it receives a specific command (second information) different from the predetermined command. For example, once the medal count control CPU 946 receives a payout end command from the main CPU 500a, it invalidates the payout end command received later until it receives a specific command, for example, a start command. At this time, the predetermined command received after the first received predetermined command is only valid when a specific command (second information) is received, and even if commands or information other than the specific command (second information) are received between the first and next reception of the predetermined command, the payout end command received later is invalidated. For example, once the payout end command is received as a predetermined command from the main CPU 500a, the payout end command received later is invalidated until it receives a start command as a specific command, even if other standby commands, game medal insertion commands, one game end commands, start commands, and change commands are received.

Note that, here, an example is given in which the medal count control CPU 946, upon receiving a specified command (first information) from the main CPU 500a, validly processes a specified command received after the first received specified command, provided that a specific command (second information) is received; however, the medal count control CPU 946 may also validly process a specified command received after the first received specified command, provided that any command or any information other than the specified command (first information) is received, not limited to a specific command (second information).

Figures 274 to 276 are flow charts showing the flow of command reception processing in the medal count control CPU 946. Here, processing related to this embodiment is explained, and processing not related to this embodiment, such as specific command generation processing, is omitted. The numerical values of step S in this figure are used only in the explanation of this figure. Also, here, 1-byte buffers (insertion request buffer, IN signal confirmation buffer, payout confirmation buffer, main reception command error buffer) are used as flags, switching between two values, "0h" and "FFh". Here, byte values are used as flags instead of bit values because, in the case of bit values, after reading the byte value, a process must be executed to judge the bit itself, and the total command size for judgment becomes longer. Note that each of the above buffers used as flags is backed up, and is not initialized even when the power is turned off.

As shown in FIG. 274, when the medal count control CPU 946 normally receives a command from the main CPU 500a, it determines whether the received command (received command) is a startup command (S1). As a result, if the received command is a startup command (YES in S1), the medal count control CPU 946 performs gaming machine installation information reception processing to receive gaming machine installation information (S2), performs manufacturer code confirmation processing to confirm the main control chip manufacturer code (S3), and ends the command reception processing. Also, if the received command is not a startup command (NO in S1), the medal count control CPU 946 determines whether the received command is a payout end command (S4). As a result, if the received command is a payout end command (YES in S4), the medal count control CPU 946 executes payout number setting processing (S5) and ends the command reception processing. Such payout number setting processing will be described in detail later.

If the received command is not a payout end command (NO in S4), the medal count control CPU 946 determines whether the received command is a one-game end command (S6). If the received command is a one-game end command (YES in S6), the medal count control CPU 946 performs a game machine performance information setting process to set game machine performance information (S7) and ends the command reception process. If the received command is not a one-game end command (NO in S6), the medal count control CPU 946 determines whether the received command is a change command (S8). If the received command is a change command (YES in S8), the medal count control CPU 946 executes a main control status reception process (S9) to receive the main control status and ends the command reception process.

If the received command is not a change command (NO in S8), the medal count control CPU 946 executes a requested number of medals to be inserted update process (S10) to update the requested number of electronic medals to be inserted, and determines whether the received command is a start command (S11). As a result, if the received command is a start command (YES in S11), the medal count control CPU 946 executes a game start process (S12) and ends the command reception process. Such game start process will be described in detail later. If the received command is not a start command (NO in S11), the medal count control CPU 946 ends the command reception process.

In the flowchart of FIG. 274, processes are executed exclusively and independently depending on which of the multiple types of commands is received. For example, if the received command is a payout end command, the payout number setting process (S5) is executed but the game start process (S12) is not executed, and if the received command is a start command, the game start process (S12) is executed but the payout number setting process (S5) is not executed. In this embodiment, the payout number setting process (S5) executed in response to the receipt of a payout end command and the game start process (S12) executed in response to the receipt of a start command are managed independently, and the payout confirmation buffer and the IN signal confirmation buffer are switched to appropriately manage the commands received by the medal count control CPU 946.

In the payout number setting process (S5) shown in FIG. 275, the medal count control CPU 946 sets the input request buffer to 0h (S5-1) and sets the IN signal confirmation buffer to 0h (S5-2). Here, by setting the IN signal confirmation buffer to 0h, the invalidation of the start command received in the game start process (S12) described later is canceled. Next, the medal count control CPU 946 determines whether the payout confirmation buffer is 0h (S5-3). As a result, if the payout confirmation buffer is not 0h (NO in S5-3), the payout end command is not received for the first time, so the medal count control CPU 946 ends the payout number setting process. On the other hand, if the payout confirmation buffer is 0h (YES in S5-3), the payout end command is received for the first time, so the medal count control CPU 946 sets the payout confirmation buffer to FFh (S5-4) and invalidates the second and subsequent payout end commands. Next, the medal count control CPU 946 determines whether the payout number is 16 or more (S5-5). If the payout number is 16 or more (YES in S5-5), it sets FFh to the main received command error buffer (S5-6) and ends the payout number setting process.

On the other hand, if the number of payouts is 15 or less (NO in S5-5), the medal count control CPU 946 determines whether or not replay is activated (S5-7). As a result, if replay is not activated (NO in S5-7), the medal count control CPU 946 determines whether or not the number of payouts is 0 (S5-8). As a result, if the number of payouts is 0 (YES in S5-8), the medal count control CPU 946 ends the payout number setting process. On the other hand, if the number of payouts is not 0 (NO in S5-8), the medal count control CPU 946 adds the payout number to the number of game medals to update the number of game medals (S5-9), and sets the payout number to the number of paid out medals (S5-10). In this way, the number of game medals is appropriately updated. When the payout number is set to the payout medal number (S5-10), or if replay is activated (YES in S5-7), the medal number control CPU 946 performs a game information setting process to set game information (S5-11), and ends the payout number setting process.

In the game start process (S12) shown in FIG. 276, the medal count control CPU 946 determines whether the IN signal confirmation buffer is 0h (S12-1). As a result, if the IN signal confirmation buffer is not 0h (NO in S12-1), the start command is not received for the first time, and the medal count control CPU 946 ends the game start process. On the other hand, if the IN signal confirmation buffer is 0h (YES in S12-1), the start command is received for the first time, and the medal count control CPU 946 sets the IN signal confirmation buffer to FFh (S12-2), invalidates the second and subsequent start commands, performs game information setting process to set game information (S12-3), sets the payout confirmation buffer to 0h (S12-4), and ends the game start process. Here, by setting the payout confirmation buffer to 0h, the invalidation of the payout end command received in the payout number setting process (S5) is canceled. In the above, step S12-4 is executed if the result of the judgment in S12-1 is YES, but it may be executed before step S12-1.

Here, when the medal count control CPU 946 receives the same type of payout end command (first information) consecutively from the main CPU 500a, it invalidates the payout end command received the second time onwards. Specifically, if the payout confirmation buffer is 0h in step S5-3 of FIG. 275, the medal count control CPU 946 determines that the payout end command has been received for the first time, switches the payout confirmation buffer to FFh, and normally executes the processing of step S5-6 and subsequent steps for the payout number. After that, even if the next payout end command is received, it is determined in step S5-3 that the payout confirmation buffer is not 0h (it is FFh), so the processing of step S5-6 and subsequent steps for the payout number will not be performed (the payout end command is invalidated).

In addition, when the medal count control CPU 946 receives a start command (second information) from the main CPU 500a under the circumstances where the received payout end command (first information) is invalidated in this way, the medal count control CPU 946 cancels the invalidation of the payout end command. Specifically, if the payout confirmation buffer is 0h in step S5-3 of FIG. 275, the medal count control CPU 946 switches the payout confirmation buffer to FFh and invalidates the payout end command received thereafter. However, if a start command is received thereafter, the payout confirmation buffer is reset to 0h in step S12-4 of FIG. 276. Therefore, when the next payout end command is received, the payout confirmation buffer is determined to be 0h in step S5-3 of FIG. 275, that is, the payout end command is determined to be received for the first time, and the processing from step S5-4 onwards for the payout number is executed normally.

In addition, when the medal count control CPU 946 receives the same type of start command (first information) consecutively from the main CPU 500a, it invalidates the second and subsequent received start commands. Specifically, if the IN signal confirmation buffer is 0h in step S12-1 of FIG. 276, the medal count control CPU 946 determines that the first start command has been received, switches the IN signal confirmation buffer to FFh, and normally executes the game information setting process in step S12-3. After that, even if the next start command is received, it is determined in step S12-1 that the IN signal confirmation buffer is not 0h (it is FFh), so the game information setting process in step S12-3 is not performed (the start command is invalidated).

In addition, when the medal count control CPU 946 subsequently receives a payout end command (second information) from the main CPU 500a under the circumstances where the start command (first information) received in this way is invalidated, the medal count control CPU 946 cancels the invalidation of the start command. Specifically, if the IN signal confirmation buffer is 0h in step S12-1 of FIG. 276, the medal count control CPU 946 switches the IN signal confirmation buffer to FFh and invalidates any start commands received thereafter. However, when a payout end command is received, the IN signal confirmation buffer is reset to 0h in step S5-2 of FIG. 275. Therefore, when the next start command is received, the IN signal confirmation buffer is determined to be 0h in step S12-1 of FIG. 276, that is, the start command is determined to be received for the first time, and the game information setting process in step S12-3 is executed normally.

In this way, when a command is received multiple times in succession, the same type of command received from the second time onwards is invalidated, so that a process that should only be executed once in response to the command is not executed multiple times, and the game progresses appropriately. Also, even if an illegal board is attached between the main control board 500 and the medal count control board 920 and a command is illegally sent multiple times by this illegal board, the command is invalidated, so game profits will not be obtained unfairly.

In this case, if the end of payout command is received multiple times in succession, the payout confirmation buffer is switched to invalidate the second and subsequent receptions, and if the start command is received multiple times in succession, the IN signal confirmation buffer is switched to invalidate the second and subsequent receptions. Since the end of payout command and the start command are processed exclusively, one buffer is sufficient. However, if the two values of one buffer are assigned to allow the end of payout command and the start command, respectively, when one buffer is in a state where it allows either the end of payout command or the start command and does not allow the other, if a backup abnormality occurs in the medal count control CPU 946 or a setting change occurs in the main control board 500, the other command that should be allowed will not be allowed, and the game may not proceed. Therefore, here, a buffer (payout confirmation buffer, IN signal confirmation buffer) is provided for the end of payout command and the start command, and when a certain initialization condition such as a backup abnormality or a setting change is met, both buffers are set to 0h to transition to a state where both commands are allowed. This configuration allows the game to proceed properly even if a backup error occurs in the medal count control CPU 946 or if a setting change occurs in the main control board 500.

This embodiment can also be implemented with one buffer, for example, by providing a separate state in which a command confirmation buffer allows both the end of payout command and the start command. For example, a state in which both the end of payout command and the start command are allowed is set to 0h, a state in which only the end of payout command is allowed and the start command is not allowed is set to 1h, and a state in which only the start command is allowed and the end of payout command is not allowed is set to 2h. When the medal count control CPU 946 receives a payout end command, it switches the command confirmation buffer to 2h in order to invalidate the second and subsequent receptions when the end of payout command is received multiple times in succession, and when it receives a start command, it switches the command confirmation buffer to 1h in order to invalidate the second and subsequent receptions when the start command is received multiple times in succession. When a predetermined initialization condition such as a backup abnormality or a setting change is met, the command confirmation buffer is set to 0h to transition to a state in which both commands are allowed.

Note that, here, commands have been given as an example of information sent and received between the main CPU 500a and the medal count control CPU 946, but this is not limited to this and can include a variety of content such as data and signals.

(Connection check by VL connection signal)
As described above, if the VL connection signal is ON in checking the connection between the medalless gaming machine 902 and the dedicated unit 904, the medalless gaming machine 902 proceeds with the game and accepts counting processing while the game is possible. On the other hand, if the VL connection signal is OFF, the medalless gaming machine 902 executes game stop processing and restricts (prohibits) all of the following: betting electronic medals, settling electronic medals, processing for game progress based on the operation of the start switch 418, and the counting processing described above. This is because if the VL connection signal is OFF, it can be determined that the medalless gaming machine 902 is not properly connected to the dedicated unit 904, or that the power supply of the dedicated unit 904 is OFF.

However, even if the VL connection signal is ON, that is, even if the medalless gaming machine 902 and the dedicated unit 904 are properly connected and the power supply of the dedicated unit 904 can be recognized as ON, there are cases where it is better not to immediately execute the counting process. For example, when the VL connection signal is ON, communication between the main control board 500 and the medal count control board 920 is not established, or is established once but then the communication connection is cut off. In this case, the counting process cannot be executed normally, so even if the medalless gaming machine 902 accepts the operation of the counting switch 922 and transmits information to the dedicated unit 904, the counted medal count may be lost. Therefore, in a modified example of this embodiment, not only the VL connection signal but also the established state of communication between the main control board 500 and the medal count control board 920 is judged, and it is judged whether or not to execute the game stop process, and if the communication is not established, the game stop process is executed and the progress of the game is restricted. Here, an example has been described in which game stop processing is performed in both cases where communication between the main control board 500 and the medal count control board 920 is not established when the VL connection signal is ON, and where communication is established once but then disconnected. However, this is not the only case. Game stop processing is performed when communication between the main control board 500 and the medal count control board 920 is not established when the VL connection signal is ON. However, when communication is established once but then disconnected, only the processing for game progress based on the bet of electronic medals, settlement of electronic medals, and operation of the start switch 418 may be restricted, and counting processing may be maintained as possible.

Figure 277 is a flow chart showing the communication specifications when the power is turned on. The numerical values of step S in this figure are used only in the explanation of this figure. For example, when the medalless gaming machine 902 is turned on, the main CPU 500a of the main control board 500 sends and receives predetermined commands (start-up command, reply command) to and from the medal count control CPU 946 of the medal count control board 920, and determines whether communication has been established.

First, the main CPU 500a sets its own register (S1), checks the backup from the previous power outage (S2), and transitions to a signal waiting state. In this waiting state, the main CPU 500a checks whether the power outage warning signal, which indicates that a power outage will occur after a predetermined time, is OFF and whether the command permission signal received from the medal count control board 920 is ON (S3), and if the power outage warning signal is ON or the command permission signal is OFF (NO in S3), it maintains the waiting state.

In parallel with this, the medal count control CPU 946 sets its own register (S4), checks the backup from the previous power outage (S5), executes the initial setting process at startup (S6), and transitions to a state of waiting for a startup command. In this startup command waiting state, the medal count control CPU 946 checks whether a startup command has been received (S7), and if it has been received (YES in S7), checks whether the startup command is normal (S8). If the startup command has not been received (NO in S7) or the startup command is abnormal (NO in S8), the startup command wait state is maintained. The startup command and reply command are composed of a serial signal of a start bit, 1 byte (8 bits) of information indicating the type of command, a stop bit, and a parity bit. Therefore, the medal count control CPU 946 determines that the startup command is normal if the type of command indicates a startup command and the parity bit is normal.

If the power failure warning signal is OFF and the command permission signal is ON (YES in S3), the main CPU 500a sends a startup command to the medal count control CPU 946 (S9). The main CPU 500a then sets a communication timer (S10) and transitions to a state of waiting for a reply command. In this state of waiting for a reply command, the main CPU 500a checks whether a reply command has been received (S11), and if it has been received (YES in S11), checks whether the reply command is normal (S12). If it has not received a reply command (NO in S11) or the reply command is abnormal (NO in S12), the main CPU 500a maintains the state of waiting for a reply command. Note that the main CPU 500a determines that the reply command is normal if the type of command indicates a reply command and the parity bit is normal.

When the main CPU 500a sends a startup command (S9), the medal count control CPU 946 receives the startup command (YES in S7). When the medal count control CPU 946 determines that the startup command is normal (YES in S8), it transitions to a signal waiting state. In this waiting state, the medal count control CPU 946 confirms that the command permission signal received from the main control board 500 is ON (S13), and if the command permission signal is OFF (NO in S13), it maintains the waiting state. On the other hand, if the command permission signal is ON (YES in S13), the medal count control CPU 946 sends a reply command to the main CPU 500a (S14), starts communication with the dedicated unit 904, and transitions to a counting possible state.

When the medal count control CPU 946 sends a reply command (S14), the main CPU 500a receives the reply command (YES in S11). When the main CPU 500a determines that the reply command is normal (YES in S12), it transitions to the setting change process or power interruption recovery process. Note that here, an example has been described in which the main CPU 500a transitions to the setting change process or power interruption recovery process when it receives a reply command and determines that the reply command is normal. However, this is not limited to such a case. After sending the startup command (S9), the main CPU 500a transitions to the setting change process or power interruption recovery process without waiting for the reply command, and after the setting change process or power interruption recovery process is completed, it checks the reception status of the reply command, and transitions to an error state if the reply command has not been received or the reply command has been received but is not normal.

When waiting for a reply command, the communication timer set in step S10 is timed, and when a predetermined time has elapsed, it times out, transitions to an error state, and the contents are displayed on the game medal count display device 924, and the communication process ends. This communication process is set not to resume unless the power is turned back on. The main CPU 500a determines through this timeout that communication between the main CPU 500a and the medal count control CPU 946 has not been established, or that it has been established but the communication connection has since been cut off, and performs a game stop process to restrict the progress of the game.

Figure 278 is a flow chart showing the communication specifications during operation. The numerical values of step S in this figure will be used only in the explanation of this figure. For example, when the bet switch 416, settlement switch 437, start switch 418, etc. are operated, the main CPU 500a of the main control board 500 sends and receives commands (start command, reply command) to and from the medal count control CPU 946 of the medal count control board 920, and determines whether communication has been established.

For example, when the start switch 418 is operated, the main CPU 500a transitions to a state of waiting for a signal. In this waiting state, the main CPU 500a confirms that the power failure warning signal is OFF and the command permission signal is ON (S1), and if the power failure warning signal is ON or the command permission signal is OFF (NO in S1), it maintains the waiting state.

On the other hand, if the power failure warning signal is OFF and the command permission signal is ON (YES in S1), the main CPU 500a sends a start command to the medal count control CPU 946 (S2) and sets the communication timer (S3).

When the main CPU 500a sends a start command (S2), the medal count control CPU 946 judges whether the received start command is normal (S4), and if it is not normal (NO in S4), the medal count control CPU 946 does not execute the processing for that operation. On the other hand, if the received start command is normal (YES in S4), the medal count control CPU 946 transitions to a waiting state until the command permission signal received from the main control board 500 turns ON. In this waiting state, the medal count control CPU 946 confirms that the command permission signal is ON (S5), and if the command permission signal is OFF (NO in S5), it maintains the waiting state. On the other hand, if the command permission signal is ON (YES in S5), the medal count control CPU 946 sends a reply command to the main CPU 500a (S6), and ends the processing for that operation.

When the main CPU 500a receives a reply command, it checks whether the reply command is normal (S7), and if it is normal (YES in S7), it checks whether game progress is permitted (S8). If the reply command is abnormal (NO in S7) or if game progress is not permitted (NO in S8), it maintains a waiting state for the reply command. Here, if the reply command is normal (YES in S7) and game progress is permitted (YES in S8), the main CPU 500a proceeds with the game.

As with the communication specifications when the power is turned on, the communication timer set in step S3 is timed while waiting for a reply command, and when a predetermined time has elapsed, it times out and operation information for the bet switch 416, settlement switch 437, start switch 418, etc. is discarded (invalidated). By invalidating the operations in this way, the game is set not to proceed.

Figure 279 is a flow chart showing the communication specifications when a game ends. The numerical values of step S in this figure will be used only in the explanation of this figure. For example, when all the reels 410 come to a halt and the display determination process S2700 ends, the main CPU 500a of the main control board 500 sends and receives commands (payout end command, reply command) to and from the medal count control CPU 946 of the medal count control board 920, and determines whether communication has been established.

When all the reels 410 have stopped and the display determination process S2700 has ended, the main CPU 500a transitions to a signal waiting state. In this waiting state, the main CPU 500a confirms that the power failure warning signal is OFF and the command permission signal is ON (S1), and if the power failure warning signal is ON or the command permission signal is OFF (NO in S1), it maintains the waiting state.

On the other hand, if the power failure warning signal is OFF and the command permission signal is ON (YES in S1), the main CPU 500a sends a payout end command to the medal count control CPU 946 (S2) and sets the communication timer (S3).

When the main CPU 500a transmits a payout end command (S2), the medal count control CPU 946 judges whether the received payout end command is normal (S4), and if it is not normal (NO in S4), it does not execute the process at the end of the game. On the other hand, if the received payout end command is normal (YES in S4), the medal count control CPU 946 transitions to a waiting state until the command permission signal received from the main control board 500 turns ON. In this waiting state, the medal count control CPU 946 confirms that the command permission signal is ON (S5), and if the command permission signal is OFF (NO in S5), it maintains the waiting state. On the other hand, if the command permission signal is ON (YES in S5), the medal count control CPU 946 transmits a reply command to the main CPU 500a (S6), and ends the process at the end of the game.

When the main CPU 500a receives a reply command, it checks whether the reply command is normal (S7), and if the reply command is abnormal (NO in S7), it maintains a state of waiting for the reply command. If the reply command is normal (YES in S7), the main RAM 500c is updated and the game proceeds.

As with the communication specifications when the power is turned on, the communication timer set in step S3 is timed while waiting for a reply command, and when a predetermined time has elapsed, it times out and the main RAM 500c is not updated. Even if a timeout does not occur, as explained using FIG. 278, the operation information of the bet switch 416, settlement switch 437, start switch 418, etc. is discarded (becomes invalid), so the game does not proceed in either case.

Here, the establishment status of communication between the main CPU 500a and the medal count control CPU 946 is also determined, and if communication is not established, a game stop process is executed, which prevents inconsistencies between the number of game medals and the number of counted medals, and enables the counting process to be carried out appropriately.

(Bet Processing)
As described above, the player can bet any number of electronic medals (number of game medals) held in the medal holding section managed by the medal number control CPU 946 through the betting means 602 managed by the main CPU 500a by operating the bet switch 416. In addition, the player can reset the bet electronic medals and return them to the medal holding section by operating the reset switch 437.

At this time, the main CPU 500a transmits the requested number of medals to the medal count control CPU 946 via a standby command, a medal insertion command, or a start command. The requested number of medals indicates the total number of electronic medals that the player wishes to bet in one game. For example, when the player operates the bet switch 416, the requested number of medals becomes the specified number required in one game, for example, three medals. Also, when the player operates the 1 bet switch, the requested number of medals is increased by one each time the player operates the switch, up to the specified number. For example, each time the player operates the 1 bet switch, the requested number of medals changes from "0" to "1" to "2" to "3", and even if the 1 bet switch is operated thereafter, the requested number of medals to be inserted remains "3". Each time the bet switch 416 or the 1 bet switch is operated, the main CPU 500a transmits a medal insertion command including the requested number of medals to the medal count control CPU 946, regardless of whether the requested number of medals has changed.

The medal count control CPU 946 then sends the number of medals that can be inserted and the number of game medals to the main CPU 500a via a reply command. The number of medals that can be inserted indicates the total number of electronic medals that can be bet from the medal holding unit in one game. The number of game medals indicated in the reply command is the number of game medals remaining when the number of medals that can be inserted has been bet (after the bet has been made) (the updated number of game medals). The main CPU 500a bets the number of electronic medals that can be inserted received from the medal count control CPU 946, and updates the number of game medals.

Here, an example was given in which the main CPU 500a waits to receive the number of insertable medals and the number of game medals from the medal count control CPU 946 through a reply command, and then bets the number of electronic medals that can be inserted. However, this is not the only case, and the main CPU 500a may bet electronic medals in advance in response to the operation of the bet switch 416 or the 1 bet switch, and may adopt a specification in which consistency is achieved by the reply command from the medal count control CPU 946. For example, the main CPU 500a holds information on the number of inserted medals (input value number), which is the total number of electronic medals that have already been bet by the main CPU 500a, the requested number of inserts, and the number of game medals in the main RAM 500c, so that it can grasp the number of insertable medals that can be bet. Therefore, the main CPU 500a bets the number of electronic medals that can be inserted in response to the operation of the bet switch 416 or the 1 bet switch, and transmits a game medal insertion command including the requested number of inserts to the medal count control CPU 946. In response, the medal count control CPU 946 sends a reply command indicating the number of medals that can be inserted and the number of medals that have been played to the main CPU 500a. The main CPU 500a then confirms that the received number of medals that can be inserted is the same as the number of electronic medals that have been bet (if they are different, it resends the medal insertion command or issues an error, as described below), and ends the betting process. By adopting this configuration, the main CPU 500a can immediately bet electronic medals in response to the operation of the bet switch 416 or 1 bet switch, and by enabling the operation of the start switch 418, for example, it is possible to avoid delays in the progress of the game.

In this way, the main CPU 500a transmits the requested number of coins to be bet to the medal count control CPU 946, and the medal count control CPU 946 replies with the number of coins that can be bet. Therefore, the number of coins that can be bet and the requested number of coins to be bet should basically be equal.

However, since the number of times that the bet switch 416 and the 1 bet switch can be operated is not limited, they can be operated multiple times before one game is started. If the number of coins that can be inserted is simply set to the number of coins requested to be inserted, the number of coins requested to be inserted is transmitted to the medal count control CPU 946 each time the bet switch 416 or the 1 bet switch is operated, and the number of coins requested to be inserted is subtracted from the number of game medals each time, and electronic medals are bet in excess of the specified number. If the number of coins requested to be inserted is simply added to the number of game medals in the settlement process, the number of coins requested to be inserted is transmitted to the medal count control CPU 946 each time the settlement switch 437 is operated, and the number of coins requested to be inserted is added to the number of game medals each time. Furthermore, even if the number of game medals is less than the number of coins that can be inserted, if the number of coins that can be inserted is simply set to the number of coins requested to be inserted, there is a risk that the number of game medals will become negative due to the bet.

Therefore, the medal count control CPU 946 appropriately manages the number of electronic medals. Specifically, here, not only the main CPU 500a but also the medal count control CPU 946 holds the number of inserted medals as information in RAM, and controls so that the number of inserted medals is equal in both CPUs. The medal count control CPU 946 then derives the number of insertable medals based on the number of inserted medals. For example, assuming that electronic medals have already been bet, the medal count control CPU 946 derives the number of insertable medals by subtracting the number of inserted medals from the requested number of insertions. Furthermore, if the number of insertable medals derived in this way is greater than the number of game medals, transmitting the derived number of insertable medals would cause the number of game medals to become negative, so the total number of game medals is set to the number of insertable medals to prevent this from becoming negative.

Figure 280 is a flowchart showing the flow of bet processing in the medal count control CPU 946. Here, processing related to this embodiment will be explained, and processing that is not related to this embodiment, such as specific command generation processing, will be omitted. The numerical values of step S in this figure will be used only in the explanation of this figure. Here, the medal count control CPU 946 holds not only the number of game medals but also the number of inserted medals in the RAM belonging to the medal count control CPU 946.

If a command is normally received from the main CPU 500a and the command is a command including the requested number of coins (a waiting command, a command when inserting a game coin, or a command at the start), as shown in FIG. 280, the medal count control CPU 946 judges whether the requested number of coins is 0 or more and 3 or less (S1). As a result, if the requested number of coins is less than 0 or 4 or more (NO in S1), an error command indicating that the requested number of coins is not within the allowable range is sent to the main CPU 500a (S2), and the bet process is terminated. Note that, although the allowable range of the requested number of coins is judged here, the process can proceed to step S3 only when various allowable conditions are met, such as when the VL connection signal is ON, and when the allowable conditions are not met, an error command is sent to the main CPU 500a, and other error processing may be performed. Also, in this embodiment, if the requested number of coins to be inserted is zero, settlement processing is performed. However, in other embodiments, if the settlement processing does not adopt a specification that sets the requested number of coins to be inserted at zero, if the requested number of coins to be inserted is zero, error processing such as sending an error command to the main CPU 500a may be performed.

On the other hand, if the requested number of medals to be inserted is equal to or greater than 0 and equal to or less than 3 (YES in S1), the medal count control CPU 946 subtracts the requested number of medals from the number of medals inserted, and determines the increase/decrease in the number of medals inserted (S3). Here, the number of medals inserted takes a value between 0 and 3, and the requested number of medals inserted takes a value between 0 and 3, so the increase/decrease in the number of medals inserted takes a value between 0 and 3, and so the increase/decrease in the number of medals inserted takes a value between -3 and 3. At this time, if the increase/decrease in the number of medals inserted is a negative value, it indicates a bet of electronic medals from the medal count control CPU 946 to the main CPU 500a, and if the increase/decrease in the number of medals inserted is a positive value, it indicates the settlement of electronic medals from the main CPU 500a to the medal count control CPU 946. Therefore, for example, if the requested number of medals to be inserted is 0, the total number of medals inserted is subject to settlement.

Next, the medal count control CPU 946 adds the increased or decreased medal count to the game medal count, and sets the result as the addition result (S4). This addition result is the updated game medal count in the case where there is no restriction on the game medal count becoming negative.

Next, the medal count control CPU 946 determines whether the addition result is a negative value (S5). As a result, if the addition result is a negative value (YES in S5), the medal count control CPU 946 adds the current number of game medals to the number of inserted medals to derive the number of medals that can be inserted (S6). If the addition result is negative, it means that even if the current number of game medals is all bet, it will not meet the requested number of medals to be inserted. Therefore, in this case, in order to bet as many electronic medals as possible, the total number of current game medals is added to the number of inserted medals to determine the number of medals that can be inserted. Then, the medal count control CPU 946 sets the remainder after all the number is bet, i.e., 0, as the updated number of game medals (S7).

On the other hand, if the sum is not a negative value (NO in S5), the medal count control CPU 946 sets the requested number of medals to the number that can be inserted (S8) and sets the sum to the updated number of game medals (S9). Here, since the number of game medals is sufficient to match the requested number of medals to be inserted, the number that can be inserted = the requested number of medals to be inserted, and the sum can be set to the updated number of game medals.

Then, the medal count control CPU 946 updates the number of inserted medals managed by the medal count control CPU 946 to the number that can be inserted (S10), sets the updated number that can be inserted and the updated number of game medals in the reply command (S11), and ends the bet process. In this way, the reply command is sent to the main CPU 500a.

The main CPU 500a can obtain the number of coins that can be inserted through the reply command and start one game. However, in a specification in which the start condition of one game is the maximum specified number of bets, the main CPU 500a holds information on the number of inserted medals and the number of game medals in the main RAM 500c, so it can grasp whether the number of coins that can be inserted does not reach the maximum specified number even if the total number of game medals is bet, and if it does not reach the maximum specified number, it may restrict the start of one game. For example, when the main CPU 500a grasps that the number of coins that can be inserted does not reach the maximum specified number, it can not send a command including the requested number of coins to the medal number control CPU 946, or even if it does, the medal number control CPU 946 can send an error command instead of the reply command (so-called "optimum max bet" control). In this way, it is possible to avoid the game proceeding in a state in which a number of electronic medals that does not reach the maximum specified number have been bet. For example, even if the specified number is allowed to be two or three and either number of medals can be inserted for one game, if the number of medals that can be inserted is less than the maximum specified number of three medals (for example, if only two medals are inserted), the progress of the game can be restricted. Therefore, if the number of game medals is zero, it is possible for the main CPU 500a to not send a command including the requested number of medals to be inserted to the medal count control CPU 946.

281 is an explanatory diagram showing an actual calculation example of the bet process. For example, as shown in FIG. 281(a), when the number of game medals held in the RAM of the medal count control CPU 946 is "10" and the number of inserted medals is "0", a command including the requested number of medals to be inserted is received from the main CPU 500a, and the requested number of medals to be inserted is "3". The medal count control CPU 946 subtracts the requested number of medals to be inserted "3" from the number of inserted medals "0" to derive the increase/decrease number of medals "-3", and adds the increase/decrease number of medals "-3" to the number of game medals "10", to derive the addition result "7". Since the addition result "7" is not a negative value, the number of medals that can be inserted becomes "3", which is equal to the requested number of medals to be inserted, and the number of game medals after the update becomes "7", which is equal to the addition result, and the number of inserted medals becomes the number of medals that can be inserted "3". The number of medals that can be inserted, "3," and the updated number of medals to be played, "7," are set in the reply command, and the updated number of medals inserted, "3," is stored in the RAM of the medal count control CPU 946.

281(b), when the number of game medals held in the RAM of the medal count control CPU 946 is "1" and the number of inserted medals is "1", a command including a requested number of medals to be inserted is received from the main CPU 500a, and the requested number of medals to be inserted is "3". The medal count control CPU 946 subtracts the requested number of medals to be inserted "3" from the number of inserted medals "1" to derive the increase/decrease number of medals "-2", and adds the increase/decrease number of medals "-2" to the number of game medals "1" to derive the addition result "-1". As the addition result "-1" is a negative value, the number of medals that can be inserted becomes "2", which is the sum of the number of inserted medals "1" and the current number of game medals "1", the number of game medals after the update becomes "0", and the number of inserted medals becomes "2", which is equal to the number of medals that can be inserted. This number of medals that can be inserted, "2," and the updated number of medals to be played, "0," are set in the reply command, and the updated number of medals inserted, "2," is stored in the RAM of the medal count control CPU 946.

281(c), when the number of game medals held in the RAM of the medal count control CPU 946 is "3" and the number of inserted medals is "3", a command including a requested number of medals to be inserted is received from the main CPU 500a, and the requested number of medals to be inserted is "0". Such an event can occur when the settlement switch 437 is operated. The medal count control CPU 946 subtracts the requested number of medals to be inserted "0" from the number of inserted medals "3" to derive the increase/decrease number of medals "3", and adds the increase/decrease number of medals "3" to the number of game medals "3" to derive the addition result "6". Since the addition result "6" is not a negative value, the number of medals that can be inserted becomes "0", which is equal to the requested number of medals to be inserted, the updated number of game medals becomes "6", which is equal to the addition result, and the number of inserted medals becomes the number of medals that can be inserted "0". This number of medals that can be inserted, "0," and the updated number of medals to be played, "6," are set in the reply command, and the updated number of medals inserted, "0," is stored in the RAM of the medal count control CPU 946.

281(d), when the number of game medals held in the RAM of the medal count control CPU 946 is "2" and the number of inserted medals is "3", a command including a requested number of medals to be inserted is received from the main CPU 500a, and the requested number of medals to be inserted is "3". Such an event may occur, for example, when the bet switch 416 is operated multiple times. It may also occur when the main CPU 500a sends a command including the requested number of medals to the medal count control CPU 946, and the medal count control CPU 946 receives it normally, but for some reason the main CPU 500a is unable to properly receive a reply command from the medal count control CPU 946, and the main CPU 500a resends a command including the requested number of medals to the medal count control CPU 946. The medal count control CPU 946 subtracts the requested number of medals to be inserted "3" from the number of medals inserted "3" to derive the increase/decrease number of medals "0", and adds the increase/decrease number of medals "0" to the number of game medals used "2" to derive the addition result "2". Because the addition result "2" is not a negative value, the number of medals that can be inserted becomes "3", which is equal to the requested number of medals to be inserted, and the updated number of game medals becomes "2", which is equal to the addition result, and the number of medals inserted becomes the number of medals that can be inserted "3". The number of medals that can be inserted "3" and the updated number of game medals "2" are set in the reply command, and the updated number of medals inserted "3" is held in the RAM of the medal count control CPU 946.

281(e), when the number of game medals held in the RAM of the medal count control CPU 946 is "3" and the number of inserted medals is "0", a command including a requested number of medals to be inserted is received from the main CPU 500a, and the requested number of medals to be inserted is "0". Such an event may occur, for example, when the settlement switch 437 is operated multiple times. It may also occur when the main CPU 500a sends a command including the requested number of medals to the medal count control CPU 946, and the medal count control CPU 946 receives the command normally, but for some reason the main CPU 500a is unable to properly receive a reply command from the medal count control CPU 946, and the main CPU 500a resends a command including the requested number of medals to the medal count control CPU 946. The medal count control CPU 946 subtracts the requested number of medals to be inserted "0" from the number of medals inserted "0" to derive the increase/decrease number of medals "0", and adds the increase/decrease number of medals "0" to the number of game medals used "3" to derive the addition result "3". Because the addition result "3" is not a negative value, the number of medals that can be inserted becomes "0" which is equal to the requested number of medals to be inserted, and the updated number of game medals becomes "3" which is equal to the addition result, and the number of medals inserted becomes the number of medals that can be inserted "0". The number of medals that can be inserted "0" and the updated number of game medals "3" are set in the reply command, and the updated number of medals inserted "0" is held in the RAM of the medal count control CPU 946.

In this way, both the main CPU 500a and the medal count control CPU 946 store the number of inserted medals as information in their respective RAMs, and by controlling both CPUs so that the number of inserted medals is equal, the medal count control CPU 946 is able to grasp the number of inserted medals that is normally managed only by the main CPU 500a. Therefore, based on the number of game medals and inserted medals managed by the medal count control CPU 946, and the requested number of medals to be inserted obtained from the main CPU 500a, it is possible to appropriately derive the number of medals that can be inserted, the updated number of game medals, and the updated number of inserted medals through calculations such as "number of inserted medals - requested number of medals" and "number of game medals + increase/decrease".

Thus, for example, even if the bet switch 416 or the 1 bet switch is operated multiple times, the medal count control CPU 946 appropriately derives the requested number of medals to be inserted based on the number of medals inserted, and subtracts the required number of electronic medals from the number of game medals. Therefore, in the bet process, electronic medals will not be bet in excess of the specified number, and in the settlement process, electronic medals will not be unnecessarily added to the number of game medals. Furthermore, if the number of game medals is less than the number that can be inserted, the medal count control CPU 946 will bet the number of game medals held in the medal holding section up to the upper limit, so that the number of game medals will not become negative as a result of the bet.

When a setting change occurs in the main control board 500, both the number of inserted medals and the number of game medals held in the RAM of the main CPU 500a and the RAM of the medal count control CPU 946 are cleared to 0. Specifically, when a setting change occurs, the main CPU 500a clears the number of inserted medals and the number of game medals held in its own RAM to 0. Then, the main CPU 500a transmits a command to the dedicated unit 904 via the medal count control CPU 946 to the effect that a setting change has been executed. At this time, when the medal count control CPU 946 receives a command to the effect that such a setting change has been executed, it clears the number of inserted medals to 0. In addition, since the number of game medals held in the medal holding section is not cleared by any trigger other than the operation of the "game medal count clear button", the medal count control CPU 946 transmits the current number of game medals to the main CPU 500a in a reply command to the start-up command, and the main CPU 500a updates the number of game medals held in its own RAM with the received number of game medals. This ensures that the number of inserted medals and the number of game medals are identical between the main CPU 500a and the medal count control CPU 946. Furthermore, if a backup abnormality occurs in the medal count control CPU 946, the RAM belonging to the medal count control CPU 946 is cleared to 0. Even in this case, the main CPU 500a can ensure the identity of the inserted medals by transmitting the number of inserted medals held in the main RAM 500c of the main CPU 500a to the medal count control CPU 946 via a startup command at startup.

(Change settings/Check settings)
As described above, in this embodiment, the setting is changed by the setting value setting means. When attempting to change the setting, first, the power supply of the medalless gaming machine 902 is turned OFF. Then, when a predetermined operation key is inserted into the setting door key 438 and rotated from the OFF position to the ON position, the power supply is turned ON via the power switch 444, the setting is changed to a setting change mode, the setting is changed, and the setting change status is turned ON. Here, the setting change status is ON while the setting change is being executed, and is OFF otherwise. Note that, if the main RAM 500c is abnormal at the start of the setting change mode, all the variables of the main RAM 500c are cleared, and if the main RAM 500c is normal, only the setting change area of the main RAM 500c is cleared. Note that, when the main CPU 500a transmits the setting change status to the dedicated unit 904, the medal count control CPU 946 can acquire the setting change status, but the medal count managed by the medal count control CPU 946 is not cleared in response to the setting change status. When the setting change switch is pressed in a state in which the setting can be changed, the setting value is incremented by one each time, and the numbers are repeated in ascending order from 1 to 6, such as 1 → 2 → 3 → 4 → 5 → 6 → 1 → .... Here, the setting value is updated to one of six setting values, and when the start switch 418 is operated, the setting value is confirmed. Then, by returning the setting door key 438 to its original position (OFF position), the setting change mode ends and play becomes possible. The setting change in progress status is turned OFF when one game is completed after the setting change mode ends.

In addition, in the setting change mode, the main CPU 500a generates a setting change signal to transmit the setting change status to the dedicated unit 904. The setting change signal indicates the ON/OFF status of the setting change status, and is set to bit 0 of gaming machine fraud 1 of the hall control/fraud monitoring information (gaming machine information) in the gaming machine information notification shown in FIG. 260, and is notified to the dedicated unit 904 at 300 msec intervals as shown in FIG. 265.

Here, in the case where two independent CPUs (main CPU 500a and medal count control CPU 946) are installed as shown in FIG. 254(a) and FIG. 254(b), it is assumed that the setting change in progress status is managed by the main CPU 500a. In this case, when a predetermined operation key is inserted into the setting door key 438 and rotated from the OFF position to the ON position, the main CPU 500a turns on the power via the power switch 444 to indicate that the setting change in progress status is ON, and transmits a gaming machine information notification to the dedicated unit 904 via the medal count control CPU 946. On the other hand, after returning the setting door key 438 to its original position (OFF position), and after one game is completed, the main CPU 500a turns off the setting change in progress signal to indicate that the setting change in progress status has become OFF, and transmits a gaming machine information notification to the dedicated unit 904 via the medal count control CPU 946. In other words, the setting change signal must remain ON until the end of one game. If such processing were to be implemented by the main CPU 500a, not only would a program be required to set the setting change signal, but also to wait for one game to end and then turn OFF the setting change signal, which could put a strain on the usable area, especially the control area. Therefore, here, the processing to set the setting change signal and the processing to wait for one game to end and then turn OFF the setting change signal are implemented by the medal count control CPU 946, rather than the main CPU 500a.

Figure 282 is a flow chart showing the update process of the setting change signal. The numerical values of step S in this figure will be used only in the explanation of this figure. When the power switch 444 is turned ON while a specific operation key is ON, the main CPU 500a executes a setting change process to change the setting value (S1). Then, when the initialization process including the setting change is completed, the main CPU 500a executes a bet process to bet electronic medals in response to the player's operation of the bet switch 416 (S2). Next, the main CPU 500a executes a lottery process in response to the player's operation of the start switch 418 (S3). Then, the main CPU 500a starts the rotation of the reels 410a, 410b, 410c to execute a reel rotation process (S4). Next, in response to the operation of the stop switches 420a, 420b, and 420c by the player, a reel stop process is executed to stop the reels 410a, 410b, and 410c corresponding to the operated stop switches 420a, 420b, and 420c (S5). When the reels 410a, 410b, and 410c stop, the main CPU 500a executes a determination process to determine whether or not the symbol combination displayed on the pay line A corresponds to any winning combination (S6), and when a symbol combination corresponding to a minor combination is displayed on the pay line A based on the determination result, a medal payout process corresponding to the minor combination is executed (S7). In this way, one game is executed through a series of processes from step S2 to step S7. Thereafter, steps S2 to S7 are repeated.

In addition, at the start of the setting change process (S1), the main CPU 500a transmits a change command (first command) indicating that the setting change has started to the medal count control CPU 946. When the medal count control CPU 946 receives the change command, it sets bit 0 in the gaming machine fraud 1 of the hall control/fraud monitoring information shown in FIG. 260 to 1, thereby turning on the setting change signal (S11). In addition, when the payout of medals is completed in the payout process (S7), the main CPU 500a transmits a payout end command (second command) to the medal count control CPU 946. When the medal count control CPU 946 receives the payout end command, it sets bit 0 in the gaming machine fraud 1 of the hall control/fraud monitoring information to 0, thereby turning off the setting change signal (S12). In this way, a functional unit that turns on the setting change signal at the start of the setting value change and sends it to the dedicated unit 904, and then turns off the setting change signal at the end of one game and sends it to the dedicated unit 904 after the setting value change is completed is sometimes referred to as a setting change signal update unit. Note that the first command is not limited to a change command and can be any command as long as it is specified that the setting value change is started, and the second command is not limited to a payout end command and can be any command as long as it is specified that each time a game is completed.

In this way, by implementing the process of setting the setting change signal in the medal count control CPU 946 instead of the main CPU 500a, the increase in programs in the main ROM 500b can be suppressed. Therefore, the area in use, especially the control area, is not put under pressure. Note that the ROM of the medal count control CPU 946 has ample memory capacity (2.5K bytes), so there is no problem in implementing the program in the medal count control CPU 946.

Here, the main CPU 500a transmits a payout end command to the medal count control CPU 946 in the payout process (S7) for each game, and the medal count control CPU 946 turns off the setting change signal in response to the payout end command (S12). In this configuration, the medal count control CPU 946 repeatedly turns off the setting change signal. However, the setting change signal remains OFF, and the setting change signal that has once been turned OFF is appropriately notified to the dedicated unit 904 at 300 msec intervals. Therefore, there is no problem with the medal count control CPU 946 repeatedly turning off the setting change signal. Here, when transmitting a payout end command to the medal count control CPU 946, the main CPU 500a does not need to determine the condition that this is the first game in which the setting change process has been completed, so there is no need for a program that determines the condition that this is the first game in which the setting change process has been completed, and this makes it possible to further suppress the increase in programs in the main ROM 500b.

Note that, here, an example has been described in which the main CPU 500a sends a command to the medal count control CPU 946 during the payout process (S7), but as long as one game has ended, the command may also be sent during the reel stop process (S5) or judgment process (S6).

In addition to changing the settings, the medalless gaming machine 902 allows the user to check the set values by checking the settings. When checking the settings, a specific operation key is inserted into the setting door key 438 and rotated from the OFF position to the ON position. This causes the device to switch to a setting check mode, allowing the user to check the set values, and the setting check status is turned ON. The setting check status is ON while the setting check is being performed, and is OFF otherwise. During the setting check status, the operation of the bet switch 416, the settlement switch 437, and the start switch 418 may be disabled. The setting value is then displayed, and the status timer starts to count. The status timer is a timer that counts the time the setting check status is maintained. The setting check mode ends when the operation key is returned to its original position (OFF position), allowing the user to play. The setting check status is turned OFF when the setting door key 438 is OFF and the status timer has elapsed for 5 seconds or more.

In addition, in the setting confirmation mode, the main CPU 500a generates a setting confirmation signal to transmit the setting confirmation status to the dedicated unit 904. The setting confirmation signal indicates the ON/OFF status of the setting confirmation status, and as shown in FIG. 260, is set to bit 1 of gaming machine fraud 1 in the hall control/fraud monitoring information (gaming machine information) in the gaming machine information notification, and is notified to the dedicated unit 904 at 300 msec intervals, as shown in FIG. 265.

Here, in the case where two independent CPUs (main CPU 500a and medal count control CPU 946) are installed as shown in Figures 254(a) and 254(b), if the setting confirmation status is managed by the main CPU 500a, not only will a program be required to set the setting confirmation signal, but also to count five seconds with the status timer, which could put a strain on the usage area, especially the control area. Therefore, as with the setting change mode, the processing to set the setting confirmation signal and the processing to count five seconds with the status timer are realized by the medal count control CPU 946, not the main CPU 500a.

Figure 283 is a flow chart showing the update process of the setting confirmation signal. The numerical values of step S in this figure will be used only in the explanation of this figure. While one game is being played through the series of processes shown in Figure 283, the payout process of the previous game (S1) ends, and in the state of waiting for a bet of electronic medals, a specific operation key is turned ON, and the main CPU 500a starts the setting confirmation process to check the setting value (S2). Then, when the setting confirmation is completed, the specific operation key is turned OFF, and the main CPU 500a ends the setting confirmation process (S3). In this way, the main CPU 500a becomes able to perform the bet process (S4).

In addition, the main CPU 500a transmits a change command (third command) to the medal count control CPU 946 in response to the start of the setting confirmation process at the start of the setting confirmation (S2). When the medal count control CPU 946 receives the change command, it sets bit 1 in the gaming machine fraud 1 of the hall control/fraud monitoring information shown in FIG. 260 to 1, thereby turning on the setting confirmation signal (S11). In addition, the main CPU 500a transmits a change command (fourth command) to the medal count control CPU 946 at the end of the setting confirmation process (S3). When the medal count control CPU 946 receives the change command, it sets the status timer to 5 seconds and starts timing (S12). Then, the medal count control CPU 946 judges whether the status timer has elapsed for 5 seconds (S13), waits until 5 seconds have elapsed (NO in S13), and when 5 seconds have elapsed (YES in S13), sets bit 1 in gaming machine fraud 1 of the hall control/fraud monitoring information to 0, thereby turning off the setting confirmation signal (S14). In this way, a functional unit that turns on the setting confirmation signal at the start of setting value confirmation and transmits it to the dedicated unit 904, waits for a predetermined time to elapse after completing the setting value confirmation, turns off the setting confirmation signal, and transmits it to the dedicated unit 904 may be called a setting confirmation signal update unit. Note that the third command is not limited to the above, and can be any command as long as it is specified at the start of setting value confirmation, and the fourth command is not limited to the above, and can be any command as long as it is specified at the completion of setting value confirmation.

In this way, by implementing the process of setting the setting confirmation signal and the process of counting 5 seconds with the status timer in the medal count control CPU 946 instead of the main CPU 500a, the increase in programs in the main ROM 500b can be suppressed, so that the usage area, especially the control area, is not strained.

As described above, the setting confirmation signal indicates that the machine is in the setting confirmation mode, and must be output for at least three seconds as a countermeasure against cheating. However, the gaming machine information notification including the setting confirmation signal is only sent to the dedicated unit 904 at a cycle of 300 msec. In that case, for example, if the medal count control CPU 946 receives a change command immediately after the gaming machine information notification is sent, the time between ON and OFF of the setting confirmation signal may be reduced by about 300 msec. Here, by setting the waiting time in the status timer to 5 seconds, the time between ON and OFF of the setting confirmation signal can be made 3 seconds or more regardless of the timing of sending the gaming machine information notification. In addition, the start of the 5-second count is not when the command indicating the start of setting confirmation is received, but when the command indicating the end of setting confirmation is received, so that the time between the command indicating the start of setting confirmation and the command indicating the end of setting confirmation is added to the 5 seconds, and therefore the time between ON and OFF of the setting confirmation signal can be reliably made 3 seconds or more.

(Replay winner)
In addition, the setting change signal and the setting confirmation signal are generated not by the main CPU 500a but by the medal count control CPU 946, thereby reducing the processing load of the main CPU 500a and the memory capacity of the main ROM 500b. However, this is not the only case, and various information from the main CPU 500a to the medal count control CPU 946 may be kept to a minimum, and information that needs to be notified to the dedicated unit 904 may be generated by the medal count control CPU 946. This configuration also reduces the burden on the main CPU 500a. For example, the medalless gaming machine 902 must transmit the hall control/fraud monitoring information and game information in the game machine information notification shown in FIG. 260 to the dedicated unit 904 every 300 msec, and as the game information, the number of inserted medals and the number of paid out medals must be transmitted when the start switch 418 is operated or when the game ends. Here, for example, when the game result is a winning replay combination, the main CPU 500a transmits only the information of the replay flag and the payout number "0" to the medal count control CPU 946, and the medal count control CPU 946 generates each piece of information necessary for the dedicated unit 904, for example, when the start switch 418 is operated, the specified number at the time of replay operation (the specified number bet in that game) as the number of inserted medals, and when the game ends, the specified number as the number of payout medals and notifies the dedicated unit 904. With this configuration, it is possible to reduce the processing load of the main CPU 500a and the memory capacity of the main ROM 500b.

In addition, at this time, the replay flag that the main CPU 500a sends to the medal count control CPU 946 is assigned to a specific bit of the identification information, the "replay status" (1 bit), rather than to a 1-byte command, eliminating the need to prepare a 1-byte command for the replay status, consolidating commands and reducing the processing load.

(Data transmission control)
When two independent CPUs (main CPU 500a and medal count control CPU 946) are installed as shown in Figures 254(a) and 254(b), serial communication is executed between the main CPU 500a and medal count control CPU 946. For example, the main CPU 500a transmits a predetermined command to the medal count control CPU 946 through serial communication. Then, the medal count control CPU 946 transmits a gaming machine information notification to the dedicated unit 904 as shown in Figures 257 to 265.

Figure 284 is an explanatory diagram showing a comparative example of communication processing between the main CPU 500a and the medal count control CPU 946. Here, an example is given in which the main CPU 500a sends a 5-byte (fixed length) command including a checksum to the medal count control CPU 946.

As shown in FIG. 284, the main control board 500 is provided with a transmission FIFO 950 for serial transmission. The transmission FIFO 950 has a memory capacity of 64 bytes, holds the first 1 byte of data input, and has a buffer function of outputting that 1 byte of data first at a transmittable timing (e.g., every 80 μsec). In addition, the main RAM 500c corresponding to the main CPU 500a is provided with a transmission candidate buffer 952 that holds 4 bytes of commands (data).

When a command (4 bytes excluding the checksum) to be sent to the medal count control CPU 946 occurs, the main CPU 500a first determines whether the command is already held in the transmission candidate buffer 952. If a command is held here, the main CPU 500a waits for the transmission candidate buffer 952 to become free. If a command is not held, the main CPU 500a causes the transmission candidate buffer 952 to hold the 4-byte command shown by cross-hatching, as shown in FIG. 284(a). Next, the main CPU 500a determines whether there is 10 bytes of free space in the transmission FIFO 950 in response to the command being held in the transmission candidate buffer 952. Here, 10 bytes of free space refers to a state in which the data held in the 64-byte buffer of the transmission FIFO 950 is 54 (64-10) or less and at least 10 bytes of data can be held. The reason for determining whether there is 10 bytes of free space here is that there is a case in which two 5-byte commands including a checksum are sent consecutively. If there are not 10 bytes free in the transmission FIFO 950, the main CPU 500a waits for 10 bytes to become free in the transmission FIFO 950. If there are 10 bytes free in the transmission FIFO 950, the main CPU 500a causes the transmission FIFO 950 to hold the command, as shown in FIG. 284(b).

In addition, as shown in FIG. 284(c), when the main CPU 500a causes the transmission FIFO 950 to store a command, it calculates a checksum of the 4-byte command stored in the transmission candidate buffer 952, and causes the transmission FIFO 950 to store the checksum, shown in black, in addition to the 4-byte command. In this way, a 5-byte command is set in the transmission FIFO 950. Then, as shown in FIG. 284(d), the transmission FIFO 950 transmits the 5-byte command to the medal count control CPU 946 at 80 μsec intervals.

In FIG. 284, a comparative example in which the command is fixed length was described, but there are also cases in which the command is variable length. For example, the main CPU 500a transmits a variable-length command of, for example, 3 bytes to 80 bytes to the medal count control CPU 946. In this way, when the command is variable length, the following problem occurs. For example, a 3-byte command can be held at once in the 4-byte transmission candidate buffer 952 or the 64-byte transmission FIFO 950, but an 80-byte command cannot be held at once in either. Therefore, the command to be sent is divided into multiple parts, and the command is transmitted in units of a small number of bytes (for example, 1 byte). Also, here, the configuration of the transmission candidate buffer 952 is deleted, and the checksum generation process is changed.

Figure 285 shows a flowchart illustrating the concept of sending one byte of a command, and a diagram showing the command. The numerical values of step S in this figure will only be used in the explanation of this figure.

285(a), the main CPU 500a first obtains information from the transmission FIFO 950 (S1). Specifically, the command "PUSH AF" on the first line of FIG. 285(b) saves the value of the AF register to the stack area, and the command "IN A, (@S0ST___)" on the third line reads the value of the multiplication result register indicated by the address into the A register with the value of the U register as the upper byte of the address and the address "@S0ST___" as the lower byte. In this way, the information of the transmission FIFO 950 is obtained from "@S0ST___". Next, as shown in FIG. 285(a), the main CPU 500a determines whether or not there is at least one byte of free space in the transmission FIFO 950 (S2), and repeats the process of step S1 until there is at least one byte of free space in the transmission FIFO 950 (NO in S2). Specifically, the command "JBIT Z, 6, A, MCD_SND01" on the fourth line of Figure 285 (b) repeats the process from the index "MCD_SND01" on the second line if bit 6 of the A register is 0, i.e., if there is not at least one byte of free space in the transmit FIFO 950, and executes the command on the fifth line if bit 6 is not 0.

Next, as shown in FIG. 285(a), if there is at least one byte free in the transmission FIFO 950 (YES in S2), the main CPU 500a transmits one byte of data to the transmission FIFO 950 (S3). Specifically, the data saved in the stack area is restored to the AF register by the command "POP AF" on the fifth line of FIG. 285(b). The command "OUT (@S0DT___), A" on the sixth line sets the value of the U register as the upper byte of the address, sets the address "@S0DT___" as the lower byte, and outputs the value of the A register restored to the transmission FIFO 950 indicated by that address. Next, as shown in FIG. 285(a), the checksum for one byte is updated (S4). Specifically, the command "ADD A, E" on line 7 of Figure 285(b) adds the value in the E register, which holds the checksum, to the value in the A register, the command "LD E, A" on line 8 returns the result of the addition (the value in the A register) to the E register, and the command "RET" on line 9 returns to the routine one level above.

Figure 286 is an explanatory diagram showing the communication process between the main CPU 500a and the medal count control CPU 946. Here, an example is given in which the main CPU 500a sends an 80-byte command out of the variable-length commands to the medal count control CPU 946.

As shown in FIG. 286, the main CPU 500a is provided with a transmission FIFO 950 for serial transmission. As in FIG. 284, the transmission FIFO 950 has a memory capacity of 64 bytes, holds the first byte of data input, and has a buffer function of outputting that byte of data first at a transmittable timing (e.g., at 80 μsec intervals). In addition, the main RAM 500c belonging to (corresponding to) the main CPU 500a is provided with a checksum buffer 954 that holds a 1-byte checksum.

When the main CPU 500a receives a command (76 bytes excluding the checksum) to send to the medal count control CPU 946, it clears the checksum buffer 954 (sets it to 0) and determines whether or not there is one byte of free space in the transmission FIFO 950. If there is not one byte of free space in the transmission FIFO 950, the main CPU 500a waits for one byte to become free in the transmission FIFO 950. If there is one byte of free space in the transmission FIFO 950, then, as shown in FIG. 286(a), the main CPU 500a causes the transmission FIFO 950 to hold the one byte of data located at the beginning of the command.

When the main CPU 500a stores 1 byte of data in the transmission FIFO 950, it calculates a checksum between the data in the checksum buffer 954 and that 1 byte of data, and overwrites the checksum (calculation result) shown in black in the checksum buffer 954. In this way, the checksum is updated every time 1 byte of data is transmitted.

As shown in FIG. 286(b), if there is one byte free in the transmission FIFO 950, the main CPU 500a causes the transmission FIFO 950 to hold the command one byte at a time, and the transmission FIFO 950 transmits the command one byte at a time at 80 μsec intervals to the medal count control CPU 946. In this way, if there is one or more byte free in the transmission FIFO 950, the main CPU 500a causes the transmission FIFO 950 to hold the command divided into one byte units in sequence. However, since the command to be sent has a larger number of bytes than the capacity of the transmission FIFO 950 as described above, a state in which there is no free space in the transmission FIFO 950 may occur, as shown in FIG. 286(c). In this case, the main CPU 500a waits for one byte to become free in the transmission FIFO 950.

When the main CPU 500a has stored all the commands in the transmission FIFO 950, it stores the checksum stored in the checksum buffer 954 in the transmission FIFO 950, as shown in FIG. 286(d). In this way, an 80-byte command is set in the transmission FIFO 950. The transmission FIFO 950 then transmits the 80-byte command to the medal count control CPU 946 at 80 μsec intervals.

In this way, by dividing commands and storing them in the transmission FIFO 950, the main CPU 500a can appropriately send commands to the medal count control CPU 946 regardless of the length of the command, even if the length of the command is greater than the capacity of the transmission FIFO 950.

In addition, regardless of the number of bytes in the command, for example, even if the command is 3 bytes, the main CPU 500a uniformly classifies the command and stores it in the transmission FIFO 950, which simplifies the program and prevents the increase in programs in the main ROM 500b. Therefore, the area used, especially the control area, is not put under pressure. Also, unlike the configuration in FIG. 284, the transmission candidate buffer 952 has been eliminated, so the capacity of the main RAM 500c can be secured.

In addition, since the main CPU 500a uniformly updates the checksum every time it stores one byte of data in the transmission FIFO 950, the checksum calculation is completed when the command transmission is completed. Therefore, a separate program for calculating the checksums of multiple data at once is not required, and not only is there no pressure on the used area, especially the control area, but the processing time can also be reduced.

Here, an example has been described in which the main CPU 500a divides the command into 1-byte chunks and stores them in the transmission FIFO 950, but this is not the only option. For example, the command can be divided into a specified byte unit less than the maximum length, such as into 2-byte chunks. If the division unit is not a common divisor of the command lengths, the main CPU 500a repeatedly transmits the command at the divided length, and transmits the remaining data in the final transmission. For example, if the command is 80 bytes long and the byte unit is 5 bytes, the main CPU 500a divides the command into 5-byte chunks and stores them repeatedly (16 times) in the transmission FIFO 950.

In addition, an example has been described here in which a command is sent from the main CPU 500a (first control unit) to the medal count control CPU 946 (second control unit) in the medalless gaming machine 902, but this is not limited to the above case. For example, the present invention can be applied to serial communication between various independent CPUs as the first control unit or second control unit, such as when sending a command between other boards in the medalless gaming machine 902, or from the main CPU 300a in a managed gaming machine to the CPU of a frame control board.

In addition, although an example in which the capacity of the transmission FIFO 950 is 64 bytes has been described here, any capacity can be applied. This embodiment is particularly effective when the command is longer than the capacity of the transmission FIFO 950. In addition, the microprocessor LEM50A sold by LETech, which is based on a Z80-series CPU, is used here, and the capacity of the transmission FIFO 950 is 64 bytes, but even other microprocessors, such as the LC701A, have a mode in which the capacity of the transmission FIFO 950 operates at 64 bytes, and this mode can be selected, for example, when the program of the LEM50A is used for the LC701A. It goes without saying that the effects of this embodiment can be obtained even in this case.

In the above embodiment, an example was described in which a transmission FIFO 950 for serial transmission is provided on the main control board 500, and the transmission FIFO 950 is used for communication processing from the main CPU 500a to the medal count control CPU 946. In parallel with this, a transmission FIFO for serial transmission (not shown) is also provided on the medal count control board 920, and the transmission FIFO is used for communication processing from the medal count control CPU 946 to the main CPU 500a. The transmission FIFO for serial transmission provided on the medal count control board 920 has a memory capacity of 16 bytes, holds the first 1 byte of data input, and has a buffer function that outputs that 1 byte of data first at a transmittable timing (for example, at 80 μsec intervals).

As described above, when the medal count control CPU 946 receives a specific command (standby command, medal insertion command, start command, payout completion command, startup command) from the main CPU 500a, it transmits a reply command, for example 5 bytes long, to the main CPU 500a, which is composed of identification information, transmission information indicating the number of medals that can be inserted and the number of medals used, and a checksum. If such reply commands are transmitted frequently, there may be cases where the transmission FIFO, which has a memory capacity of only 16 bytes, is unable to hold the transmitted data.

Therefore, when sending a reply command, the medal count control CPU 946 sends it to the transmission FIFO with a transmission interval. For example, the medal count control CPU 946 waits for 4 msec or more after the previous reply command is sent (waits for 4 msec) before sending the next reply command. At this time, the main CPU 500a executes the reception process at a cycle of 1.49 msec, refers to the FIFO trigger level, waits for the completion of reception of all bytes (5 bytes in this case) of the reply command, and executes the analysis process of the reply command. With this configuration, it is possible to avoid a state in which transmission data is accumulated in the transmission FIFO for serial transmission provided in the medal count control board 920, and the transmission data cannot be held.

In addition, by managing the information triggered by the lending process and the counting process independently on a bit-by-bit basis in the reply command, even if the lending process and the counting process are executed simultaneously, the information can be written simultaneously and independently in a single reply command, thereby reducing the frequency with which reply commands are sent.

(Command 1 of main CPU 500a)
Also, as described above, here, the command transmitted by the main CPU 500a to the medal count control CPU 946 is assumed to be variable length. In that case, the time from the start of command transmission to the completion of transmission will differ. Here, if a power outage occurs, it may happen that the transmission of the command is not completed in the power outage processing. Some commands can be complemented by other processing even if the transmission is not completed, and some require the completion of transmission. For example, a command at the end of one game is resent when the power is restored (when starting up) even if the transmission of the command is not completed and the command is not transmitted, so there is no problem. Therefore, the power outage processing can be started, for example, immediately, without waiting for the completion of command transmission. With such a configuration, it is possible to avoid the transmission of unnecessary commands and suppress the increase in the interruption prohibition time.

On the other hand, in the payout end command, transmission information indicating the number of payout coins is transmitted. The number of payout coins should not be transmitted multiple times. This is because if the number of payout coins is transmitted at the end of the game and then retransmitted when power is restored (started), it will be considered as having been paid out multiple times, and the number of payout coins will be increased (doubled). In addition, since the number of payout coins is information of high importance that directly relates to the player's profit, it must be transmitted reliably to the medal count control CPU 946. Therefore, among the multiple commands that the main CPU 500a transmits to the medal count control CPU 946, commands of high importance such as the payout end command are reliably transmitted to the medal count control CPU 946 between the detection of the power failure warning signal and the start of the power failure process. In other words, the power failure process is started after the transmission of the command is completed. Note that, since the transmission of the command must be completed in a short time before the power failure process is started, the number of bytes of the command of high importance is shortened (for example, to 10 bytes). This configuration allows the main CPU 500a to reliably send high-importance commands to the medal count control CPU 946, allowing the game to proceed appropriately.

(Command 2 of main CPU 500a)
Also, as described above, here, the command transmitted by the main CPU 500a to the medal count control CPU 946 is assumed to be variable length. Then, depending on the transmission order of the commands and their contents, the time from the start of transmission to the completion of transmission will differ. For example, if a power interruption notice signal occurs immediately after a relatively long (e.g., 60 bytes) one game end command is transmitted, there is a risk of a power interruption occurring without completing the transmission of the command. Also, when the power is turned on, the main CPU 500a transmits a startup command (e.g., 80 bytes) longer than the one game end command to the medal count control CPU 946, and resumes processing from the state before the power interruption occurred. Here, when one game ends, the role ratio-related data is updated, and the one game end command is transmitted after the startup command. Then, since there is a high possibility that the startup command still remains in the transmission FIFO 950, the transmission of the one game end command is further awaited. If a power outage warning signal occurs immediately after such a game end command is sent, the completion of command transmission may be further delayed, and there is a risk that a power outage may occur before the command has been sent completely.

However, as mentioned above, even if the end-of-game command is not transmitted to the medal count control CPU 946, no problem occurs because it is resent when power is restored (started up). Furthermore, when power is restored (started up), no data is held in the transmission FIFO 950, so unless a power interruption occurs, the start-up command is properly transmitted to the medal count control CPU 946.

Therefore, when a command includes "role ratio-related transmission information" like the end of one game command, when the power cut warning signal is detected, the power cut processing is immediately started without waiting for the command to be sent. For example, in step S2 of FIG. 285(a), if there is at least one byte of free space in the transmission FIFO 950, the main CPU 500a determines in step S3 whether the command includes "role ratio-related transmission information" and whether the power cut warning signal has been detected before sending one byte of data to the transmission FIFO 950. Then, when the power cut warning signal is detected, the main CPU 500a ends the processing without performing the subsequent steps S3 and S4, i.e., without sending one byte of data (by canceling the sending of the end of one game command including the checksum), and moves to the power cut processing. With this configuration, it is possible to avoid sending unnecessary commands and suppress an increase in the interrupt prohibition time.

On the other hand, if the command does not include "combination information related to winning ratios" or if the power cut warning signal is not detected, the main CPU 500a executes steps S3 and S4. With this configuration, if a power cut warning signal is detected during the transmission of a one-game end command, which is of low importance, it becomes possible to immediately cancel the transmission of the command and execute the power cut processing appropriately.

Let us also assume that the power is turned on, the start-up command is sent, processing resumes from the state before the power failure, and immediately after that, the end-of-game command is sent, and the power failure warning signal is detected. In this case, since no data is stored in the transmission FIFO 950 when the power is turned on, the first 64 bytes of the start-up command are immediately stored in the transmission FIFO 950. Thereafter, when the end-of-game command is sent, the latter half of the start-up command still remains in the transmission FIFO 950. Therefore, it takes a long time for the command to be sent. However, due to the configuration for determining whether the power failure warning signal has been detected, when an empty space appears in the transmission FIFO 950, the transmission of the end-of-game command is canceled, making it possible to properly execute the power failure process.

The "role ratio-related transmission information" is included not only in the end-of-game command, but also in the start-up command. Therefore, if a power cut warning signal is detected when sending the start-up command, the process will end without sending any further data (by canceling the sending of the start-up command, including the checksum), and the process will move on to power cut processing.

However, the transmission of the "transmission information required at startup" from the startup commands is not stopped, and the power cut process is not performed until the transmission is complete. This is for the following reason. The "transmission information required at startup" includes gaming machine information, chip ID, manufacturer code, etc., and the confirmation of the power cut warning signal must also be recorded in multiple places, which may result in an increase in processing load and memory capacity. Also, as described above, since no data is held in the transmission FIFO 950 at startup, the "transmission information required at startup" can be held in the transmission FIFO 950 in a short period of time, and it does not take a long time to complete the transmission.

Here, we have explained an example of the end of one game command and the start command, in which if the command contains "combination information related to winning ratios" and the power cut warning signal is detected, the process immediately transitions to power cut processing without transmitting any further data. For other commands (standby commands, start commands, end of payout commands, and change commands), the process in FIG. 285(a) may be executed as is, or before step S1 in FIG. 285(a), i.e., at the start of transmission, it may be determined whether or not the power cut warning signal has been detected, and if it has been detected, the process immediately transitions to power cut processing without performing all of steps S1 to S4, i.e., without transmitting any further data. With this configuration, the process transitions appropriately to power cut processing for all commands.

(Communication between the main CPU and the tester)
The medal-less gaming machine 902, like the slot machine 400, is also subjected to type testing by the Security Communications Association (SCA), a testing organization designated by the Public Safety Commission, and the general incorporated association GLI Japan. The Connection Specifications for Testing Machines for Slot Machines (7th Edition) describes the specifications required for conducting appropriate testing using testing machines used by the designated testing organization. An outline of the specifications is given below.

Figure 287 is an explanatory diagram for explaining a test firing test of the medal-less gaming machine 902. In the test firing test, as shown in Figure 287, the medal-less gaming machine 902 and the test firing test machine 1000 are connected via a first interface board 504 and a second interface board 506 to unify the various signals.

First, the test firing machine 1000 outputs a predetermined signal to the medalless gaming machine 902 via connect CN3 of the first interface board 504. The predetermined signal output here is, for example, a pseudo signal indicating that the bet switch 416, start switch 418, stop switch 420, etc. have been operated. Note that, since these switches are not actually operated, the sensors provided for each switch do not output a detection signal, but a pseudo signal is output as if they have been operated in a pseudo manner.

In response to such signals, the main control board 500 outputs a predetermined signal to the test firing test machine 1000 via the connects CN1 and CN2 of the first interface board 504. The predetermined signal output here is a signal indicating the state of the performance lamp 426, the state of the various sensors, the position of the stepping motor 452, etc. Furthermore, when auxiliary performance based on the AT performance state, etc. is adopted, the main control board 500 outputs a predetermined signal to the test firing test machine 1000 via the connect CN4 of the second interface board 506. The predetermined signal output here is a signal related to a game method that can obtain the maximum ball payout rate, etc. Here, such signals are mainly represented as discrete signals, i.e., two values of 1 (HIGH) or 0 (LOW).

Assuming the configuration shown in FIG. 287, the operation status of the game control process (lottery for winning type, reel control, bet, etc.) in response to inputs of the start switch 418, stop switch 420, bet switch 416, etc. is tested to see if it is normal, and whether the main credit display unit 430, main payout display unit 432, and various lamps are displayed normally. In addition, various timings of operation of the bet switch 416, start switch 418, stop switch 420, and game control process are tested to see if the signal changes after the condition for turning the signal on/off is satisfied, such as the timing when the stop switch 420 is first enabled after the start switch 418 is operated and the lamp signal that manages the lighting/exiting state of the corresponding performance lamp 426 is turned on, or whether the timing is within an appropriate time range.

In addition, tests related to ball-discharge performance (checking the upper and lower limits of ball-discharge rate) include, for example, (1) short-term ball-discharge rate (ball-discharge rate in any 400-play period is less than 300%), (2) medium-time ball-discharge rate (ball-discharge rate in any 6,000-play period is less than 150%), (3) long-term ball-discharge rate (ball-discharge rate in any 17,500-play period is less than 120% and greater than 55%), (4) device ratio (of the game medals paid out from the slot machine 400, 70% or less of the balls won through the operation of the device (SB, CB, MB, RB, BB)), and (5) consecutive device ratio (of the game medals paid out from the gaming machine, 60% or less of the balls won through the operation of the consecutive device (RB or BB)). The test methods include (A) a simulation test (a test to obtain the maximum number of coins that can be obtained in each play), (B) test firing test 1 (a test to play using the same playing method as the player plays), and (C) test firing test 2 (a test to play using the playing method that results in the lowest payout rate), etc.

Here, as a comparative example, we will explain the case where a slot machine 400 is connected to a test firing test machine 1000, and then we will explain the case where a medalless gaming machine 902 is connected to a test firing test machine 1000.

Figure 288 is an explanatory diagram for explaining the operation of the slot machine 400. For example, when the slot machine 400 and the test firing test machine 1000 are connected, and the test firing test machine 1000 sequentially inputs pseudo signals from the bet switch 416, the start switch 418, and the stop switch 420 to the slot machine 400, the reel control means 606 of the slot machine 400 controls the reels 410a, 410b, and 410c to stop in response to the pseudo signals. Such pseudo signals cause the slot machine 400 to execute an auto play in which the game is repeated. Here, a case will be explained where, in one game of the auto play, a symbol combination corresponding to a minor role with a payout of 15 coins is displayed on the pay line A.

When all reels 410a, 410b, 410c are stopped by the reel control means 606 at time a in FIG. 288, the determination means 608 determines whether or not a symbol combination corresponding to a winning role has been displayed on the pay line A, and the payout control means 610 pays out medals in the number corresponding to the minor role (here, 15 medals) based on the symbol combination corresponding to the winning role (here, a minor role) being displayed on the pay line A. Here, medals are paid out one at a time at equal intervals according to the number of medals paid out for the minor role. Then, when the payout of medals is completed, the payout control means 610 permits the start of the next game, i.e., a bet by the betting means 602.

At this time, a payout count signal (first signal) consisting of 15 pulses with a duty of 50% is transmitted (outputted to the outside) from the slot machine 400 to the test firing test machine 1000 based on the payout of 15 medals, and at time point b indicating the end of the payout count signal 178.8 msec later, a throw-in request lamp signal (second signal) turns ON (outputted to the outside). The test firing test machine 1000 judges whether the payout number of medals has been appropriately performed based on the payout count signal, and also grasps that the next game is possible (the next auto game can be started) based on the ON of the throw-in request lamp signal. Here, the first signal is not limited to a payout count signal, and it is sufficient if it can transmit the number of electronic medals to the test firing test machine 1000 as the number of pulses. Also, the second signal is not limited to a throw-in request lamp signal, and it is sufficient if it can transmit to the test firing test machine 1000 the completion of the output of the first signal, for example, that the number of pulses has been output equal to the number of electronic medals.

The slot machine 400 and the medalless gaming machine 902 have substantially the same game progress processing. Therefore, the signals transmitted to and received from the test firing test machine 1000 are also substantially the same. However, the slot machine 400 and the medalless gaming machine 902 may have different operations. For example, the slot machine 400 pays out actual medals, which takes time to do so, but the medalless gaming machine 902 progresses the game without the intervention of medals, so the payout control means 610 does not pay out medals. Therefore, there is no actual payout of medals by the payout control means 610 as shown in FIG. 288. In the slot machine 400, the payout control means 610 restricts the start of the next game during the payout of medals, and allows the start of the next game after the payout is completed. However, in the medalless gaming machine 902, there is no need to pay out actual medals, and the payout of electronic medals ends instantly. In this way, as long as all reels 410a, 410b, and 410c have stopped, the next game can start immediately afterwards.

However, as described above, since the slot machine 400 and the medalless gaming machine 902 have substantially the same game progression process, the signals transmitted to and received from the test firing test machine 1000 are substantially the same. In this case, the medalless gaming machine 902 needs to output a payout count signal and an insertion request lamp signal even when no actual medals are paid out. Therefore, the medalless gaming machine 902 can also transmit a payout count signal consisting of 15 pulses to the test firing test machine 1000 based on the payout of 15 medals, and after 178.8 msec, turn on the insertion request lamp signal in response to the end of the payout, and synchronize with the insertion request lamp signal to enable the start of the next game in the medalless gaming machine 902.

However, in the medal-less gaming machine 902, after all reels 410a, 410b, and 410c have stopped, the payout of electronic medals is completed instantly, so the player must wait for the payout count signal to be completed after the payout of electronic medals is completed before starting the next game. This can lead to a situation where the player operates the bet switch 416 while the start of the next game is restricted, and the operation is not accepted effectively, preventing improvement in operability. Furthermore, when the payout of electronic medals has been completed and the next game can be started, providing a waiting time for the payout count signal means that the progress of the game is needlessly delayed.

Therefore, the game progress of the medalless gaming machine 902 itself and the signal transmission to the test firing test machine 1000 are operated independently to ensure that the game progresses appropriately.

Figure 289 is an explanatory diagram for explaining the operation of the medalless gaming machine 902. For example, when the medalless gaming machine 902 is connected to the test firing test machine 1000, and the pseudo signals of the bet switch 416, start switch 418, and stop switch 420 are input from the test firing test machine 1000 to the medalless gaming machine 902 in sequence, the reel control means 606 controls the reels 410a, 410b, and 410c to stop in response to the pseudo signals. Such pseudo signals cause the slot machine 400 to execute an auto play in which the game is repeated. Here, as in Figure 288, it is assumed that a symbol combination corresponding to a minor role with a payout of 15 coins is displayed on the pay line A.

When all reels 410a, 410b, 410c are stopped by the reel control means 606 at time a, the determination means 608 determines whether or not a symbol combination corresponding to a winning role has been displayed on the pay line A, and the payout control means 610 pays out the number of electronic medals corresponding to the small role (here, 15 medals) at once based on the symbol combination corresponding to the winning role (here, a small role) being displayed on the pay line A. In this way, when the payout of medals is instantly completed, the payout control means 610 allows the start of the next game. This allows the player to start the next game immediately after the electronic medals are paid out.

At this time, a payout count signal (first signal) consisting of 15 pulses is transmitted (output to the outside) from the medalless gaming machine 902 to the test firing test machine 1000 based on the payout of 15 medals, independent of the payout of the electronic medals, and a throw-in request lamp signal (second signal) turns ON (output to the outside) at time b indicating the end of the payout count signal 178.8 msec later. The test firing test machine 1000 uses this payout count signal to determine whether the medals have been properly paid out, and also knows that the next game is possible due to the throw-in request lamp signal turning ON.

Here, the progress of the game on the medalless gaming machine 902 itself and the transmission of signals to the test firing machine 1000 are operated independently, and the next game can be started immediately after the payout of the electronic medals is completed. This allows the bet switch 416 to be accepted immediately after the payout of the electronic medals is completed, so the player is not restricted in accepting the bet switch 416, improving operability. In addition, since the next game can be started immediately after the payout of the electronic medals is completed, it is possible to progress the game appropriately.

Although the preferred embodiment of the present invention has been described above with reference to the attached drawings, it goes without saying that the present invention is not limited to such an embodiment. It is clear that a person skilled in the art can come up with various modified or revised examples within the scope of the claims, and it is understood that these also naturally fall within the technical scope of the present invention.

For example, the security-related signal transmitted from the medal-less gaming machine 902 to the dedicated unit 904 is output continuously for three seconds or more. Here, if the medal-less gaming machine 902 is powered off while outputting a security-related signal, the medal-less gaming machine 902 may or may not output the security-related signal again after power is restored. If the medal-less gaming machine 902 outputs the security-related signal again, it may output the security-related signal again for three seconds or more continuously after power is restored.

In the above embodiment, the main CPU 500a obtains a door open error detection flag that is set to "1" when the front upper door 404 or the front lower door 406 is open, and determines whether a door open error has occurred. In a medal-less gaming machine, not only the main CPU 500a but also the medal count control CPU 946 manages the door open error. Specifically, the door open signal output when the front upper door 404 or the front lower door 406 is open is input as an electrical signal (hardware) to both the main CPU 500a and the medal count control CPU 946, and the main CPU 500a notifies the door open error through the sub-CPU 502a, and in parallel with this, the medal count control CPU 946 notifies the door open error through the dedicated unit 904 or the hall computer 906. With this configuration, even if a malfunction occurs in one of the main CPU 500a and the medal count control CPU 946, as long as the other CPU is normal, the door open error can be notified, so security can be ensured.

In the above-described embodiment, the main control board 500, the sub-control board 502, and the medal count control board 920 are arranged to share the functional parts for progressing through the game, but some of the functional parts of the main control board 500 may be arranged on the sub-control board 502 or the medal count control board 920, some of the functional parts of the sub-control board 502 may be arranged on the main control board 500 or the medal count control board 920, some of the functional parts of the medal count control board 920 may be arranged on the main control board 500 or the sub-control board 502, or all of the functional parts may be arranged together on a single control board.

Furthermore, each process performed by the main control boards 300, 500, sub-control boards 330, 502, and medal count control board 920 described above does not necessarily have to be performed in chronological order according to the order described in the flowchart, and may include parallel or subroutine processing.

100 Gaming machine 300, 500 Main control board 300a, 500a Main CPU
300b, 500b Main ROM
300c, 500c Main RAM
330, 502 Sub-control board 330a, 502a Sub-CPU
330b, 502b Sub ROM
330c, 502c, Sub RAM
400 Slot machine 900 Gaming system 902 Medalless gaming machine 904 Dedicated unit 920 Medal count control board 946 Medal count control CPU

Claims (1)

A gaming machine capable of outputting a predetermined signal to the outside,
A betting means for betting a gaming value to be used in a game;
a reel control means for controlling the rotation of a plurality of reels on which a plurality of types of symbols are respectively arranged based on the operation of a start switch after a gaming value is bet, and for controlling the stop of each of the reels corresponding to the operated stop switch in response to the operation of a stop switch corresponding to the rotating reel;
a payout control means for paying out a game value corresponding to a stop state of the reels;
Equipped with
The dispensing control means
pay out the game value at once in response to the stopping of the reels, and then permit a bet for the next game by the betting means;
outputting, to the outside, a first signal constituted by pulses corresponding to the number of game values to be paid out, and then, when the output of the first signal is completed, outputting, to the outside, a second signal indicating that a next game is possible;
The timing at which the bet for the next game is permitted is earlier than the timing at which the output of the first signal is completed .

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