JP7453360B2 - キャッシュアクセス測定デスキュー - Google Patents

キャッシュアクセス測定デスキュー Download PDF

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JP7453360B2
JP7453360B2 JP2022522317A JP2022522317A JP7453360B2 JP 7453360 B2 JP7453360 B2 JP 7453360B2 JP 2022522317 A JP2022522317 A JP 2022522317A JP 2022522317 A JP2022522317 A JP 2022522317A JP 7453360 B2 JP7453360 B2 JP 7453360B2
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cache
area
accesses
access
monitored
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JP2023500590A (ja
JP2023500590A5 (https=
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モイヤー ポール
ケリー ジョン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G06F12/127—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning using additional replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2022522317A 2019-10-31 2020-10-29 キャッシュアクセス測定デスキュー Active JP7453360B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/669,973 2019-10-31
US16/669,973 US11210234B2 (en) 2019-10-31 2019-10-31 Cache access measurement deskew
PCT/US2020/057966 WO2021087115A1 (en) 2019-10-31 2020-10-29 Cache access measurement deskew

Publications (3)

Publication Number Publication Date
JP2023500590A JP2023500590A (ja) 2023-01-10
JP2023500590A5 JP2023500590A5 (https=) 2023-10-18
JP7453360B2 true JP7453360B2 (ja) 2024-03-19

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JP2022522317A Active JP7453360B2 (ja) 2019-10-31 2020-10-29 キャッシュアクセス測定デスキュー

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US (2) US11210234B2 (https=)
EP (1) EP4052133B1 (https=)
JP (1) JP7453360B2 (https=)
KR (1) KR102709340B1 (https=)
CN (1) CN114631082B (https=)
WO (1) WO2021087115A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11372556B2 (en) * 2020-09-03 2022-06-28 Dell Products, L.P. Snapshot access using nocopy undefined thin devices
US20230214323A1 (en) * 2021-12-30 2023-07-06 Micron Technology, Inc. Selectable cache writing policies for cache management
US12387011B2 (en) * 2022-10-24 2025-08-12 Synopsys, Inc. Secured computer memory
CN118227446B (zh) * 2024-05-21 2024-08-02 北京开源芯片研究院 高速缓存性能评估方法、装置、电子设备及可读存储介质
US20260093808A1 (en) * 2024-09-30 2026-04-02 Advanced Micro Devices, Inc. Hardware Mitigation of Cache Side-Channel Attacks
EP4730143A1 (en) * 2024-10-16 2026-04-22 Amadeus S.A.S. Controlling an update strategy of a cache

Citations (5)

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Publication number Priority date Publication date Assignee Title
JP2003280987A (ja) 2002-03-25 2003-10-03 Kawasaki Microelectronics Kk 適応置換制御機能を有するセット・アソシアティブ方式のキャッシュシステム及びキャッシュ制御方法
CN101866318A (zh) 2010-06-13 2010-10-20 北京北大众志微系统科技有限责任公司 一种高速缓存替换策略的管理系统及方法
US20130151778A1 (en) 2011-12-09 2013-06-13 International Business Machines Corporation Dynamic Inclusive Policy in a Hybrid Cache Hierarchy Using Bandwidth
JP2019516188A (ja) 2016-04-27 2019-06-13 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ キャッシュテスト領域に基づくプリフェッチのためのキャッシュエージングポリシーの選択
JP2019517690A (ja) 2016-06-13 2019-06-24 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ キャッシュ置換ポリシーのスケーリングされたセットデュエリング

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7676630B2 (en) 2006-10-05 2010-03-09 Sun Microsystems, Inc. Method and apparatus for using a determined file access pattern to perform caching in a file system
CN101866322A (zh) * 2010-06-13 2010-10-20 北京北大众志微系统科技有限责任公司 一种高速缓存管理策略的调整方法及系统
US9047225B1 (en) * 2012-09-27 2015-06-02 Emc Corporation Dynamic selection of data replacement protocol for cache
US20160239432A1 (en) 2015-02-17 2016-08-18 Linkedin Corporation Application-layer managed memory cache
JP5992592B1 (ja) 2015-09-16 2016-09-14 株式会社東芝 キャッシュメモリシステム
US9928176B2 (en) * 2016-07-20 2018-03-27 Advanced Micro Devices, Inc. Selecting cache transfer policy for prefetched data based on cache test regions
US11182306B2 (en) 2016-11-23 2021-11-23 Advanced Micro Devices, Inc. Dynamic application of software data caching hints based on cache test regions
US10496551B2 (en) 2017-06-28 2019-12-03 Intel Corporation Method and system for leveraging non-uniform miss penality in cache replacement policy to improve processor performance and power
CN110297787B (zh) 2018-03-22 2021-06-01 龙芯中科技术股份有限公司 I/o设备访问内存的方法、装置及设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003280987A (ja) 2002-03-25 2003-10-03 Kawasaki Microelectronics Kk 適応置換制御機能を有するセット・アソシアティブ方式のキャッシュシステム及びキャッシュ制御方法
CN101866318A (zh) 2010-06-13 2010-10-20 北京北大众志微系统科技有限责任公司 一种高速缓存替换策略的管理系统及方法
US20130151778A1 (en) 2011-12-09 2013-06-13 International Business Machines Corporation Dynamic Inclusive Policy in a Hybrid Cache Hierarchy Using Bandwidth
JP2019516188A (ja) 2016-04-27 2019-06-13 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ キャッシュテスト領域に基づくプリフェッチのためのキャッシュエージングポリシーの選択
JP2019517690A (ja) 2016-06-13 2019-06-24 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ キャッシュ置換ポリシーのスケーリングされたセットデュエリング

Also Published As

Publication number Publication date
CN114631082B (zh) 2023-10-24
EP4052133A4 (en) 2023-11-29
JP2023500590A (ja) 2023-01-10
US20220121579A1 (en) 2022-04-21
KR102709340B1 (ko) 2024-09-25
EP4052133B1 (en) 2025-09-24
EP4052133A1 (en) 2022-09-07
CN114631082A (zh) 2022-06-14
KR20220087459A (ko) 2022-06-24
US20210133114A1 (en) 2021-05-06
US11210234B2 (en) 2021-12-28
WO2021087115A1 (en) 2021-05-06
US11880310B2 (en) 2024-01-23

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