CN114631082B - 高速缓存访问测量偏斜校正 - Google Patents

高速缓存访问测量偏斜校正 Download PDF

Info

Publication number
CN114631082B
CN114631082B CN202080073396.6A CN202080073396A CN114631082B CN 114631082 B CN114631082 B CN 114631082B CN 202080073396 A CN202080073396 A CN 202080073396A CN 114631082 B CN114631082 B CN 114631082B
Authority
CN
China
Prior art keywords
region
cache
monitored
access
accesses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202080073396.6A
Other languages
English (en)
Chinese (zh)
Other versions
CN114631082A (zh
Inventor
保罗·莫耶
约翰·凯利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN114631082A publication Critical patent/CN114631082A/zh
Application granted granted Critical
Publication of CN114631082B publication Critical patent/CN114631082B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • G06F12/121Replacement control using replacement algorithms
    • G06F12/126Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • G06F12/121Replacement control using replacement algorithms
    • G06F12/126Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G06F12/127Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning using additional replacement algorithms
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502Control mechanisms for virtual memory, cache or TLB using adaptive policy
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60Details of cache memory
    • G06F2212/601Reconfiguration of cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN202080073396.6A 2019-10-31 2020-10-29 高速缓存访问测量偏斜校正 Active CN114631082B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/669,973 2019-10-31
US16/669,973 US11210234B2 (en) 2019-10-31 2019-10-31 Cache access measurement deskew
PCT/US2020/057966 WO2021087115A1 (en) 2019-10-31 2020-10-29 Cache access measurement deskew

Publications (2)

Publication Number Publication Date
CN114631082A CN114631082A (zh) 2022-06-14
CN114631082B true CN114631082B (zh) 2023-10-24

Family

ID=75687634

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080073396.6A Active CN114631082B (zh) 2019-10-31 2020-10-29 高速缓存访问测量偏斜校正

Country Status (6)

Country Link
US (2) US11210234B2 (https=)
EP (1) EP4052133B1 (https=)
JP (1) JP7453360B2 (https=)
KR (1) KR102709340B1 (https=)
CN (1) CN114631082B (https=)
WO (1) WO2021087115A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11372556B2 (en) * 2020-09-03 2022-06-28 Dell Products, L.P. Snapshot access using nocopy undefined thin devices
US20230214323A1 (en) * 2021-12-30 2023-07-06 Micron Technology, Inc. Selectable cache writing policies for cache management
US12387011B2 (en) * 2022-10-24 2025-08-12 Synopsys, Inc. Secured computer memory
CN118227446B (zh) * 2024-05-21 2024-08-02 北京开源芯片研究院 高速缓存性能评估方法、装置、电子设备及可读存储介质
US20260093808A1 (en) * 2024-09-30 2026-04-02 Advanced Micro Devices, Inc. Hardware Mitigation of Cache Side-Channel Attacks
EP4730143A1 (en) * 2024-10-16 2026-04-22 Amadeus S.A.S. Controlling an update strategy of a cache

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101866318A (zh) * 2010-06-13 2010-10-20 北京北大众志微系统科技有限责任公司 一种高速缓存替换策略的管理系统及方法
CN101866322A (zh) * 2010-06-13 2010-10-20 北京北大众志微系统科技有限责任公司 一种高速缓存管理策略的调整方法及系统
WO2018098225A2 (en) * 2016-11-23 2018-05-31 Advanced Micro Devices, Inc. Dynamic application of software data caching hints based on cache test regions
CN109478165A (zh) * 2016-07-20 2019-03-15 超威半导体公司 基于缓存测试区针对预取数据选择缓存转移策略

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3964705B2 (ja) * 2002-03-25 2007-08-22 川崎マイクロエレクトロニクス株式会社 適応置換制御機能を有するセット・アソシアティブ方式のキャッシュシステム及びキャッシュ制御方法
US7676630B2 (en) 2006-10-05 2010-03-09 Sun Microsystems, Inc. Method and apparatus for using a determined file access pattern to perform caching in a file system
US8843707B2 (en) * 2011-12-09 2014-09-23 International Business Machines Corporation Dynamic inclusive policy in a hybrid cache hierarchy using bandwidth
US9047225B1 (en) * 2012-09-27 2015-06-02 Emc Corporation Dynamic selection of data replacement protocol for cache
US20160239432A1 (en) 2015-02-17 2016-08-18 Linkedin Corporation Application-layer managed memory cache
JP5992592B1 (ja) 2015-09-16 2016-09-14 株式会社東芝 キャッシュメモリシステム
US10509732B2 (en) 2016-04-27 2019-12-17 Advanced Micro Devices, Inc. Selecting cache aging policy for prefetches based on cache test regions
US10430349B2 (en) * 2016-06-13 2019-10-01 Advanced Micro Devices, Inc. Scaled set dueling for cache replacement policies
US10496551B2 (en) 2017-06-28 2019-12-03 Intel Corporation Method and system for leveraging non-uniform miss penality in cache replacement policy to improve processor performance and power
CN110297787B (zh) 2018-03-22 2021-06-01 龙芯中科技术股份有限公司 I/o设备访问内存的方法、装置及设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101866318A (zh) * 2010-06-13 2010-10-20 北京北大众志微系统科技有限责任公司 一种高速缓存替换策略的管理系统及方法
CN101866322A (zh) * 2010-06-13 2010-10-20 北京北大众志微系统科技有限责任公司 一种高速缓存管理策略的调整方法及系统
CN109478165A (zh) * 2016-07-20 2019-03-15 超威半导体公司 基于缓存测试区针对预取数据选择缓存转移策略
WO2018098225A2 (en) * 2016-11-23 2018-05-31 Advanced Micro Devices, Inc. Dynamic application of software data caching hints based on cache test regions

Also Published As

Publication number Publication date
EP4052133A4 (en) 2023-11-29
JP2023500590A (ja) 2023-01-10
US20220121579A1 (en) 2022-04-21
KR102709340B1 (ko) 2024-09-25
EP4052133B1 (en) 2025-09-24
EP4052133A1 (en) 2022-09-07
CN114631082A (zh) 2022-06-14
KR20220087459A (ko) 2022-06-24
US20210133114A1 (en) 2021-05-06
US11210234B2 (en) 2021-12-28
WO2021087115A1 (en) 2021-05-06
US11880310B2 (en) 2024-01-23
JP7453360B2 (ja) 2024-03-19

Similar Documents

Publication Publication Date Title
CN114631082B (zh) 高速缓存访问测量偏斜校正
US11321245B2 (en) Selecting cache aging policy for prefetches based on cache test regions
US9928176B2 (en) Selecting cache transfer policy for prefetched data based on cache test regions
US10725923B1 (en) Cache access detection and prediction
US10762000B2 (en) Techniques to reduce read-modify-write overhead in hybrid DRAM/NAND memory
US20110320720A1 (en) Cache Line Replacement In A Symmetric Multiprocessing Computer
US8364904B2 (en) Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer
US20130191599A1 (en) Cache set replacement order based on temporal set recording
WO2018098225A2 (en) Dynamic application of software data caching hints based on cache test regions
US10810126B2 (en) Cache storage techniques
US10534721B2 (en) Cache replacement policy based on non-cache buffers
EP3239848A1 (en) Selecting cache aging policy for prefetches based on cache test regions
US9734071B2 (en) Method and apparatus for history-based snooping of last level caches

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant