KR102709340B1 - 캐시 액세스 측정 디스큐 - Google Patents

캐시 액세스 측정 디스큐 Download PDF

Info

Publication number
KR102709340B1
KR102709340B1 KR1020227014466A KR20227014466A KR102709340B1 KR 102709340 B1 KR102709340 B1 KR 102709340B1 KR 1020227014466 A KR1020227014466 A KR 1020227014466A KR 20227014466 A KR20227014466 A KR 20227014466A KR 102709340 B1 KR102709340 B1 KR 102709340B1
Authority
KR
South Korea
Prior art keywords
cache
area
policy
monitored
weight
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020227014466A
Other languages
English (en)
Korean (ko)
Other versions
KR20220087459A (ko
Inventor
폴 모이어
존 켈리
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20220087459A publication Critical patent/KR20220087459A/ko
Application granted granted Critical
Publication of KR102709340B1 publication Critical patent/KR102709340B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G06F12/127—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning using additional replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020227014466A 2019-10-31 2020-10-29 캐시 액세스 측정 디스큐 Active KR102709340B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/669,973 2019-10-31
US16/669,973 US11210234B2 (en) 2019-10-31 2019-10-31 Cache access measurement deskew
PCT/US2020/057966 WO2021087115A1 (en) 2019-10-31 2020-10-29 Cache access measurement deskew

Publications (2)

Publication Number Publication Date
KR20220087459A KR20220087459A (ko) 2022-06-24
KR102709340B1 true KR102709340B1 (ko) 2024-09-25

Family

ID=75687634

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020227014466A Active KR102709340B1 (ko) 2019-10-31 2020-10-29 캐시 액세스 측정 디스큐

Country Status (6)

Country Link
US (2) US11210234B2 (https=)
EP (1) EP4052133B1 (https=)
JP (1) JP7453360B2 (https=)
KR (1) KR102709340B1 (https=)
CN (1) CN114631082B (https=)
WO (1) WO2021087115A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11372556B2 (en) * 2020-09-03 2022-06-28 Dell Products, L.P. Snapshot access using nocopy undefined thin devices
US20230214323A1 (en) * 2021-12-30 2023-07-06 Micron Technology, Inc. Selectable cache writing policies for cache management
US12387011B2 (en) * 2022-10-24 2025-08-12 Synopsys, Inc. Secured computer memory
CN118227446B (zh) * 2024-05-21 2024-08-02 北京开源芯片研究院 高速缓存性能评估方法、装置、电子设备及可读存储介质
US20260093808A1 (en) * 2024-09-30 2026-04-02 Advanced Micro Devices, Inc. Hardware Mitigation of Cache Side-Channel Attacks
EP4730143A1 (en) * 2024-10-16 2026-04-22 Amadeus S.A.S. Controlling an update strategy of a cache

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170315932A1 (en) 2016-04-27 2017-11-02 Advanced Micro Devices, Inc. Selecting Cache Aging Policy For Prefetches Based on Cache Test Regions
CN110297787A (zh) 2018-03-22 2019-10-01 龙芯中科技术有限公司 I/o设备访问内存的方法、装置及设备

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3964705B2 (ja) * 2002-03-25 2007-08-22 川崎マイクロエレクトロニクス株式会社 適応置換制御機能を有するセット・アソシアティブ方式のキャッシュシステム及びキャッシュ制御方法
US7676630B2 (en) 2006-10-05 2010-03-09 Sun Microsystems, Inc. Method and apparatus for using a determined file access pattern to perform caching in a file system
CN101866322A (zh) * 2010-06-13 2010-10-20 北京北大众志微系统科技有限责任公司 一种高速缓存管理策略的调整方法及系统
CN101866318B (zh) * 2010-06-13 2012-02-22 北京北大众志微系统科技有限责任公司 一种高速缓存替换策略的管理系统及方法
US8843707B2 (en) * 2011-12-09 2014-09-23 International Business Machines Corporation Dynamic inclusive policy in a hybrid cache hierarchy using bandwidth
US9047225B1 (en) * 2012-09-27 2015-06-02 Emc Corporation Dynamic selection of data replacement protocol for cache
US20160239432A1 (en) 2015-02-17 2016-08-18 Linkedin Corporation Application-layer managed memory cache
JP5992592B1 (ja) 2015-09-16 2016-09-14 株式会社東芝 キャッシュメモリシステム
US10430349B2 (en) * 2016-06-13 2019-10-01 Advanced Micro Devices, Inc. Scaled set dueling for cache replacement policies
US9928176B2 (en) * 2016-07-20 2018-03-27 Advanced Micro Devices, Inc. Selecting cache transfer policy for prefetched data based on cache test regions
US11182306B2 (en) 2016-11-23 2021-11-23 Advanced Micro Devices, Inc. Dynamic application of software data caching hints based on cache test regions
US10496551B2 (en) 2017-06-28 2019-12-03 Intel Corporation Method and system for leveraging non-uniform miss penality in cache replacement policy to improve processor performance and power

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170315932A1 (en) 2016-04-27 2017-11-02 Advanced Micro Devices, Inc. Selecting Cache Aging Policy For Prefetches Based on Cache Test Regions
CN110297787A (zh) 2018-03-22 2019-10-01 龙芯中科技术有限公司 I/o设备访问内存的方法、装置及设备

Also Published As

Publication number Publication date
CN114631082B (zh) 2023-10-24
EP4052133A4 (en) 2023-11-29
JP2023500590A (ja) 2023-01-10
US20220121579A1 (en) 2022-04-21
EP4052133B1 (en) 2025-09-24
EP4052133A1 (en) 2022-09-07
CN114631082A (zh) 2022-06-14
KR20220087459A (ko) 2022-06-24
US20210133114A1 (en) 2021-05-06
US11210234B2 (en) 2021-12-28
WO2021087115A1 (en) 2021-05-06
US11880310B2 (en) 2024-01-23
JP7453360B2 (ja) 2024-03-19

Similar Documents

Publication Publication Date Title
KR102709340B1 (ko) 캐시 액세스 측정 디스큐
US11321245B2 (en) Selecting cache aging policy for prefetches based on cache test regions
US9176878B2 (en) Filtering pre-fetch requests to reduce pre-fetching overhead
US8683129B2 (en) Using speculative cache requests to reduce cache miss delays
US11803484B2 (en) Dynamic application of software data caching hints based on cache test regions
US9798668B2 (en) Multi-mode set associative cache memory dynamically configurable to selectively select one or a plurality of its sets depending upon the mode
US9928176B2 (en) Selecting cache transfer policy for prefetched data based on cache test regions
US8806139B2 (en) Cache set replacement order based on temporal set recording
US8954680B2 (en) Modifying data prefetching operation based on a past prefetching attempt
US20170046278A1 (en) Method and apparatus for updating replacement policy information for a fully associative buffer cache
WO2008149348A2 (en) Method architecture circuit & system for providing caching
JP5298826B2 (ja) キャッシュメモリ及びプリフェッチ方法
US10810126B2 (en) Cache storage techniques
EP3239848A1 (en) Selecting cache aging policy for prefetches based on cache test regions
JP2024011696A (ja) 演算処理装置及び演算処理方法
Olson et al. Probabilistic Directed Writebacks for Exclusive Caches

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PA0302 Request for accelerated examination

St.27 status event code: A-1-2-D10-D17-exm-PA0302

St.27 status event code: A-1-2-D10-D16-exm-PA0302

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601