JP7447849B2 - Power element drive device - Google Patents

Description

The present invention relates to a power element driving device.

The applicant has proposed a device for driving a power element as in Patent Document 1. According to Patent Document 1, each of a plurality of power elements is provided with gate voltage detection, and resonance is achieved by configuring a resistor and a diode in parallel between the control pole of each power element and the control voltage detection section. The route is blocked.

By the way, as a circuit for turning off the power element, in addition to a normal OFF drive circuit, a soft cutoff circuit and an OFF holding drive circuit are provided. The drive IC is provided with terminals corresponding to outputs from the respective drive sections. The drive IC also includes a gate voltage detection section that detects the gate voltage of the power element. The number of terminals has been reduced by sharing the terminals of the gate voltage detection section with the off-holding drive section that is driven after the power element is turned off.

However, when it is desired to use an external element to maintain the power element off in order to more reliably keep it off, two terminals are required: a terminal for monitoring the gate voltage and a terminal for driving the external terminal. In order to reduce the number of terminals, the off-holding function cannot be consolidated into one terminal, and the gate voltage detection section cannot share the terminal with the off-holding drive section, so a separate terminal for the gate voltage detection section must be provided. occurs. As a result, the number of terminals of the drive IC increases, which impedes miniaturization of the drive IC.

JP 2018-148745 Publication

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a power element drive device that can be downsized by reducing the number of terminals.

According to the invention described in claim 1, the power supply device includes an OFF drive circuit, a soft cutoff circuit, an OFF holding drive circuit, a first voltage detection circuit, a second voltage detection circuit, and a control section. The off drive circuit normally performs off drive from the off drive terminal by extracting the gate charge of the power element based on the off command of the drive signal. The soft cutoff circuit turns off the power element from the cutoff drive terminal at a speed different from when the off drive circuit drives the power element off. The off-holding drive circuit maintains the off state of the power element by connecting the control terminal of the power element to a low impedance. The first voltage detection circuit monitors the control voltage of the power element at the off-drive terminal of the off-drive circuit. The second voltage detection circuit monitors the control voltage of the power element at the cutoff drive terminal of the soft cutoff circuit. The control unit determines and controls the control content based on the drive signal and the results of monitoring the control voltage by the first voltage detection circuit and the second voltage detection circuit.

The first voltage detection circuit can monitor the control voltage of the power element from the off drive terminal, and the second voltage detection circuit can monitor the control voltage of the power element from the cutoff drive terminal, and the off drive terminal and cutoff drive terminal are used for voltage detection. It can be shared as a terminal. Voltage detection, OFF driving, and soft shutoff can be performed through the cutoff drive terminal and the OFF drive terminal, and the power element can be driven while reducing the number of terminals and achieving miniaturization.

Electrical configuration diagram of the power element drive system in the first embodiment Normal time chart explaining the flow of the first embodiment A time chart schematically showing voltage changes in each part during half-on detection in the first embodiment Electrical configuration diagram of the power element drive system in the second embodiment A time chart schematically showing voltage changes in various parts when short-circuit overcurrent is detected in the second embodiment Electrical configuration diagram of power element drive system in third embodiment Electrical configuration diagram of the power element drive system in the fourth embodiment Electrical configuration diagram showing a part of the power element drive system in the fifth embodiment Electrical configuration diagram of the power element drive system in the sixth embodiment

Hereinafter, some embodiments will be described with reference to the drawings. In each of the embodiments described below, components that perform the same or similar operations are designated by the same or similar reference numerals, and description thereof will be omitted as necessary.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. 1 to 3. As shown in FIG. 1, the power element drive device A is a device that drives a gate drive type IGBT 1, and is mainly configured with a drive IC 10. The collector-emitter of the IGBT 1 is connected to a power supply path to a load (not shown). IGBT is an abbreviation for Insulated Gate Bipolar Transistor, and is used as a power element to be driven. In this embodiment, a mode is shown in which there is only one IGBT 1 to be driven.

The IGBT 1 includes a sense emitter for detecting current, and the sense emitter is connected to a resistor 2 for detecting current. The drain and source of an N-channel MOS transistor 6 are connected between the gate of the IGBT 1 and the ground through a parallel connection circuit 5 including a resistor 3 and a diode 4. The MOS transistor 6 is provided as a semiconductor element that maintains the gate of the IGBT 1 in an off state by bringing the gate of the IGBT 1 into a lower impedance state than the off drive circuit 20 .

The drive IC 10, which is an integrated circuit, functions as a semiconductor element drive circuit, and performs gate drive control for turning on and turning off the IGBT 1. The drive IC 10 is turned on by supplying power to the gate G of the IGBT 1 from the DC power supply Vcc, and turned off by discharging the gate charge of the IGBT 1 to the ground through the parallel connection circuit 5. The drive IC 10 includes an on drive terminal MP, a current detection terminal SOC, a cutoff drive terminal SCO, an off drive terminal MN, and an off hold drive terminal SOUT.

The drive IC 10 is mainly configured with a control section 11. The control unit 11 is composed of a microcomputer or a logic circuit. The control unit 11 is a circuit that, when receiving a drive signal MIN for the IGBT 1 from the outside, provides a drive signal to the gate G of the IGBT 1 in response to the drive signal MIN, and controls the IGBT 1 to be in an on state or an off state. The control unit 11 determines and controls the control content based on the drive signal MIN and the monitoring results of the gate voltage of the IGBT 1 by the first voltage detection circuit 18 and the second voltage detection circuit 27.

The ON drive circuit 12 is configured inside the drive IC 10, and is configured using, for example, a MOS transistor and a buffer circuit. The on-drive circuit 12 is supplied with power from the DC power supply Vcc and outputs a gate drive signal through the on-drive terminal MP. When the ON drive circuit 12 receives a drive signal from the control unit 11, the ON drive circuit 12 drives the IGBT 1 by applying the drive signal from the ON drive terminal MP to the gate G of the IGBT 1 through the resistor 13.

The off-drive circuit 14 is configured inside the drive IC 10 and includes, for example, an N-channel type MOS transistor 15 and a buffer circuit 16. The drain of MOS transistor 15 is connected to off-drive terminal MN, and the source is connected to ground. When the buffer circuit 16 receives a drive signal from the control unit 11, it supplies the gate drive signal to the gate G of the MOS transistor 15. The off-drive terminal MN is connected to the gate G of the IGBT 1 through the resistor 17 and the parallel connection circuit 5.

A parallel connection circuit 5 is configured between the gate of the IGBT 1 and the off drive terminal MN of the off drive circuit 14. The parallel connection circuit 5 has a configuration in which a resistor 3 and a diode 4 are connected in parallel between the gate of the IGBT 1 and the resistor 17, respectively. The diode 4 has its anode connected to the gate of the IGBT 1, and its cathode connected to the off-drive terminal MN through the resistor 17.

The first voltage detection circuit 18 includes a comparator 19 and inputs the off-holding threshold Vt to an inverting input terminal. The first voltage detection circuit 18 is connected to share the off-drive terminal MN to which the off-drive circuit 14 is connected, and detects the gate voltage of the IGBT 1 at the off-drive terminal MN through the parallel connection circuit 5 and the resistor 17. It is detected whether the detection voltage exceeds the off-holding threshold Vt. The off-holding threshold Vt is predetermined according to the threshold voltage of the IGBT 1 and the off-control voltage, and if the voltage of the off-drive terminal MN exceeds the off-holding threshold Vt, a high-level detection signal is output.

The soft cutoff circuit 20 includes an N-channel type MOS transistor 21 and a buffer circuit 22. The drain of the MOS transistor 21 is connected to the cutoff drive terminal SCO, and the source is connected to the ground. The buffer circuit 22 is supplied with a drive signal from the control section 11 and supplies a gate drive signal to the MOS transistor 21 . The cutoff drive terminal SCO is connected to the gate G of the IGBT 1 via a resistor 23 and a parallel connection circuit 24. A parallel connection circuit 24 is configured between the gate of the IGBT 1 and the cutoff drive terminal SCO of the OFF drive circuit 14. The parallel connection circuit 24 has a configuration in which a resistor 26 and a diode 25 are connected in parallel between the gate of the IGBT 1 and the resistor 23, respectively. The diode 25 has its anode connected to the gate of the IGBT 1, and its cathode connected to the cutoff drive terminal SCO through the resistor 23.

Note that in this embodiment, the resistance value of the resistor 23 is set to be larger than the resistance value of the resistor 17 in the resistor 17 and the resistor 23. This is because the gate charge of the IGBT 1 is discharged for a longer time than in normal times during soft cutoff. The resistance values of the resistors 17 and 23 can be set to appropriate values depending on the characteristics of the IGBT 1, and the magnitude relationship may also be set to be reversed.

The second voltage detection circuit 27 includes a comparator 28 and inputs the off-holding threshold Vt to an inverting input terminal. A non-inverting input terminal of the comparator 28 is connected to a common connection point between the cutoff drive terminal SCO and the drain of the MOS transistor 21.

The second voltage detection circuit 27 is connected to share the cutoff drive terminal SCO to which the soft cutoff circuit 20 is connected, and detects the gate voltage of the IGBT 1 at the cutoff drive terminal SCO through the parallel connection circuit 24 and the resistor 23, It is detected whether this detection voltage exceeds the off-holding threshold Vt.

The comparator 28 inputs the gate voltage of the IGBT 1 through the parallel connection circuit 24, the resistor 23, and the cutoff drive terminal SCO, and outputs a high-level detection signal if it exceeds the off-holding threshold Vt.

The off-hold drive circuit 29 includes an N-channel MOS transistor 30 and a buffer circuit 31, and in response to an off-hold signal given from the control unit 11, the off-hold drive circuit 29 drives the gate of the off-hold MOS transistor 6, which is an external output element. An off-hold signal is output from the off-hold drive terminal SOUT.

The external element drive circuit 32 is configured inside the drive IC 10 and is configured by a buffer circuit, and is connected to share the off-hold drive terminal SOUT to which the off-hold drive circuit 29 is connected. The external element drive circuit 32 is a circuit for driving the MOS transistor 6, which is an external output element, in accordance with the off-hold signal given from the control unit 11, and connects the gate of the MOS transistor 6 through the off-hold drive terminal SOUT. Outputs an OFF hold signal.

The current detection circuit 33 is a circuit configured as a first short circuit overcurrent detection section that detects whether an overcurrent or short circuit current flows through the IGBT 1, and is connected to the sense emitter of the IGBT 1 via the current detection terminal SOC. ing. The current detection circuit 33 includes a comparator 34 and inputs the short circuit overcurrent threshold value Vk to an inverting input terminal.

The current detection circuit 33 detects the sense current by detecting the voltage of the current detection resistor 2 of the IGBT 1 from the current detection terminal SOC, and determines whether the detected voltage of the sense current exceeds the short circuit overcurrent threshold Vk. To detect. The short circuit overcurrent threshold Vk is predetermined according to the overcurrent threshold and the short circuit current threshold of IGBT1, and if the voltage of the current detection terminal SOC exceeds the short circuit overcurrent threshold Vk, a high level detection signal is output. .

Next, the operation of the above-mentioned configuration in normal operation will be explained with reference to FIG. Next, the operation at the time of half-on detection will be explained with reference to FIG.

<Normal operation>
FIG. 2 is a timing chart corresponding to normal operation. In the control unit 11, a drive signal is applied to the OFF drive circuit 14 and the OFF holding drive circuit 29 during a time period t0 to t1 before the ON drive drive signal MIN is applied from the outside.

At this time, the MOS transistor 15 of the OFF drive circuit 14 is turned on, and the OFF holding MOS transistor 30 of the OFF holding drive circuit 29 is turned on. As a result, the charge on the gate G of the IGBT 1 is in a discharged state, and the gate voltage is at a low potential level.

Next, at time t1, when an ON drive signal is externally applied as a gate drive signal, the control unit 11 switches the OFF drive circuit 14 and the OFF holding drive circuit 29 to the OFF state, and further sends an ON drive signal to the ON drive circuit 12. give.

As a result, the MOS transistor 15 of the off-drive circuit 14 is turned off, and the first voltage detection circuit 18 connected to the off-drive terminal MN becomes able to detect the gate voltage of the IGBT 1. Moreover, since the soft cutoff circuit 20 is in the off state, the second voltage detection circuit 27 connected to the cutoff drive terminal SCO is in a state where it can detect the gate voltage of the IGBT 1.

The on-drive circuit 12 applies a voltage to the gate G of the IGBT 1 from the DC power supply Vcc. As a result, the gate voltage of IGBT1 increases, and when the gate voltage of IGBT1 reaches the on-threshold voltage, IGBT1 is turned on, and current is supplied from IGBT1 to the load. If at least the gate voltage of the IGBT 1 has reached the on-threshold voltage, the first voltage detection circuit 18 and the second voltage detection circuit 27 output high-level detection signals to the control unit 11.

After that, at time t3, when the drive signal MIN reaches a level corresponding to OFF drive, the control unit 11 stops driving the ON drive circuit 12 and drives the OFF drive circuit 14. As a result, the gate G of IGBT1 is cut off.

When the MOS transistor 15 is turned on by receiving a drive command at time t3 and driving the off drive circuit 14, the gate charge of the IGBT 1 is transferred from the parallel connection circuit 5 and the resistor 17 to the off drive terminal after time t4. It is discharged to ground through MN and MOS transistor 15. At this time, the parallel connection circuit 5 is configured by connecting a resistor 3 and a diode 4 in parallel, and when the same current is passed through these resistors 3 and diode 4, the voltage drops instantly by the forward voltage Vf of the diode 4. . Thereby, the gate voltage of IGBT1 can be quickly lowered. Even after that, the gate voltage of IGBT1 decreases.

During this time, the first voltage detection circuit 18 is detecting the voltage of the off-drive terminal MN, but as shown from time t4 to t5, the voltage of the off-drive terminal MN is at a low potential at the same time as the MOS transistor 15 is turned on. level, and therefore falls below the off-holding threshold Vt at time t5.

On the other hand, since the MOS transistor 21 of the soft cutoff circuit 20 is in the off state, the second voltage detection circuit 27 detects the gate voltage of the IGBT 1 from the cutoff drive terminal SCO through the parallel connection circuit 24 and the resistor 23 from time t4 to t5. can. Therefore, after the control unit 11 drives the off-drive circuit 14, the gate voltage of the IGBT 1 can be detected from the cut-off drive terminal SCO using the detection signal of the second voltage detection circuit 27.

When the gate voltage of the IGBT 1 decreases and the voltage of the cutoff drive terminal SCO decreases to the off-holding threshold Vt at time t6, the second voltage detection circuit 27 outputs a low-level detection signal. As a result, the control unit 11 outputs an off-hold drive signal to the off-hold drive circuit 29 at time t6.

The off-hold drive circuit 29 is turned on by applying a drive signal to the gate of the off-hold MOS transistor 30 via the off-hold drive terminal SOUT. Then, the gate charge of IGBT1 is rapidly discharged via the on-resistance of MOS transistor 6, and the gate voltage instantly drops to a low potential level. Since the gate voltage of IGBT1 is maintained at a low potential level, it is fixed in the off state.

Note that in the above operation, the detection value of the first voltage detection circuit 18 cannot be used between times t3 and t6 because the off-drive circuit 14 is driving. However, in other periods except for the time period t3 to t6, since neither the OFF drive circuit 14 nor the soft cutoff circuit 20 is used, neither the first voltage detection circuit 18 nor the second voltage detection circuit 27 is used. detection signals can be used. By using both detection signals, erroneous detection due to noise can be prevented and reliability can be increased.

In summary, the control unit 11 controls the OFF-holding drive circuit 29 when the voltages at both the OFF-drive terminal MN and the cut-off drive terminal SCO have decreased to a predetermined OFF-holding threshold Vt while the IGBT 1 is being driven OFF. control to maintain the off state. This ensures reliable off-holding drive.

<Operation when half-on>
Next, with reference to FIG. 3, the operation when the IGBT 1 is continuously detected as a half-on state after being turned off will be described. The half-on state indicates a state in which the IGBT 1 operates in the active region.

Time t13 shown in FIG. 3 corresponds to time t3 in FIG. 2, and the operation before time t13 is the same as the operation from time t0 to t3 in FIG. 2, so the explanation will be omitted. At time t13 in FIG. 3, when the drive signal MIN reaches a level corresponding to OFF drive, the control unit 11 stops driving the ON drive circuit 12 and drives the OFF drive circuit 14.

As a result, the output of the on-drive circuit 12 is turned off, and the gate G of the IGBT 1 is cut off. Furthermore, by turning on the OFF drive circuit 14, the gate charge of the IGBT 1 is discharged from the parallel connection circuit 5 and the resistor 17 to the ground level through the MOS transistor 15 via the OFF drive terminal MN. As a result, the gate voltage of IGBT1 decreases.

During this time, the first voltage detection circuit 18 is detecting the voltage of the OFF drive terminal MN, but almost at the same time as the MOS transistor 15 is turned on, the OFF drive terminal MN drops to the ground level at time t14. The voltage detection circuit 18 cannot detect the gate voltage of the IGBT1. On the other hand, the second voltage detection circuit 27 can detect the gate voltage of the IGBT 1 because the MOS transistor 21 of the soft cutoff circuit 20 is in the off state.

Therefore, when the control unit 11 drives the off-drive circuit 14, the gate voltage of the IGBT 1 is detected using the detection signal of the second voltage detection circuit 27. When the half-on state continues, the gate voltage of IGBT1 decreases slowly, and the voltage at the cutoff drive terminal SCO does not reach the off-holding threshold Vt even at time t15, when a predetermined time T1 has elapsed from time t13.

Since the second voltage detection circuit 27 does not output a low-level detection signal even at time t15, the control unit 11 supplies an off-hold drive signal to the off-hold drive circuit 29 at time t15 when the predetermined time T1 has elapsed from time t13. Output.

The off-hold drive circuit 29 applies a drive signal to the off-hold MOS transistor 6 via the off-hold drive terminal SOUT to turn it on. Then, the gate charge of IGBT1 is rapidly discharged via the on-resistance of MOS transistor 6, and the gate voltage instantly drops to a low potential level. As a result, the gate voltage of the IGBT 1 is maintained at a low potential level, so that the IGBT 1 is fixed in the off state.

In addition, in other periods except for the time period t13 to t15, since neither the off drive circuit 14 nor the soft cutoff circuit 20 is used, neither the first voltage detection circuit 18 nor the second voltage detection circuit 27 is used. A detection signal can be used, and by using both detection signals, false detection due to noise etc. can be prevented and reliability can be increased.

In the present embodiment, the half-on state is detected when the voltage of the cutoff drive terminal SCO remains higher than the off-holding threshold Vt even after the control unit 11 measures the predetermined time T1. The half-on state may be detected if no detection signal is output from either the first voltage detection circuit 18 or the second voltage detection circuit 27 even if T1 is measured.

In summary, at the time of half-on detection, the control unit 11 determines that when the IGBT 1 is turned off, the voltage of either the off drive terminal MN or the cutoff drive terminal SCO is higher than the predetermined off holding threshold Vt. When the half-on state continues for a time T1 or longer, half-on detection is performed, and control is performed so that the off-state is maintained by the off-holding drive circuit 29 at the timing of the half-on detection. This ensures reliable off-holding drive.

As described above, according to the present embodiment, the first voltage detection circuit 18 can monitor the gate voltage of the IGBT 1 from the off drive terminal MN, and the second voltage detection circuit 27 can monitor the gate voltage from the cutoff drive terminal SCO. In addition, the off drive terminal MN and cutoff drive terminal SCO can also be shared as voltage detection terminals. Voltage detection, OFF driving, and soft shutoff can be performed through the cutoff drive terminal SCO and the OFF drive terminal MN, and the IGBT 1 can be driven while suppressing the number of terminals and achieving miniaturization.

(Second embodiment)
A second embodiment will be described with reference to FIGS. 4 and 5. In this embodiment, a configuration and operation for detecting short circuit overcurrent will be described.

As shown in FIG. 4, the first voltage detection circuit 18 includes a comparator 19a and inputs the short-circuit overcurrent threshold Vm to an inverting input terminal, and inputs the detected voltage of the off-drive terminal MN to a non-inverting input terminal. Ru. Comparator 19a is used as a second short circuit overcurrent detection section. Further, the first voltage detection circuit 18 includes a comparator 19b, and is configured by inputting the off-holding threshold Vt to an inverting input terminal and inputting the voltage of the off-drive terminal MN to a non-inverting input terminal.

The comparator 19b has the same function as the comparator 19 of the above-mentioned embodiment, so a description thereof will be omitted. The comparator 19a detects a voltage based on the gate voltage of the IGBT 1 at the off-drive terminal MN, and outputs a detection signal to the control unit 11 for determining whether the voltage has reached the short-circuit overcurrent threshold Vm. The control unit 11 can determine whether a short circuit or overcurrent is occurring based on this detection signal.

The second voltage detection circuit 27 includes a comparator 28a, inputs the short circuit overcurrent threshold Vm into an inverting input terminal, and inputs the detected voltage of the cutoff drive terminal SCO into a non-inverting input terminal. Comparator 28a is used as a second short circuit overcurrent detection section. The second voltage detection circuit 27 includes a comparator 28b and is configured by inputting the off-holding threshold Vt to an inverting input terminal and inputting the voltage of the cutoff drive terminal SCO to a non-inverting input terminal.

The comparator 28b has the same function as the comparator 28 of the embodiment described above, so a description thereof will be omitted. The comparator 28a detects a voltage based on the gate voltage of the IGBT 1 at the cutoff drive terminal SCO, and outputs a detection signal to the control unit 11 for determining whether the voltage has reached the short circuit overcurrent threshold Vm. The control unit 11 can determine whether a short circuit or overcurrent is occurring based on this detection signal.

<Operation when short circuit/overcurrent is detected>
Next, referring to FIG. 5, the operation when a short circuit or overcurrent is detected when the IGBT 1 is turned on will be described. As shown in FIG. 4, between time t20 and time t21 before the on-drive drive signal MIN is applied, a drive signal is applied to the off-drive circuit 14 and the off-hold drive circuit 29, and the charge on the gate G of IGBT1 is is in a discharged state, and the gate voltage is 0V, which is the ground level.

Next, at time t21, when the on-drive drive signal MIN is applied, the control unit 11 switches the off-drive circuit 14 and the off-hold drive circuit 29 to the off state, and further provides an on-drive signal to the on-drive circuit 12. . As a result, IGBT1 is turned on. When the gate voltage of the IGBT 1 reaches the threshold voltage, the comparator 19b of the first voltage detection circuit 18 and the comparator 28b of the second voltage detection circuit 27 output a high-level detection signal to the control unit 11.

After that, when a short circuit current flows through IGBT1 around time t23, a current corresponding to the short circuit current flows through the sense emitter as well, so that the voltage of the sense emitter of IGBT1 becomes high exceeding the short circuit overcurrent threshold Vk. On the other hand, the detected voltage of the off-drive terminal MN becomes higher than the short-circuit overcurrent threshold Vm. When the voltage of the sense emitter of the IGBT 1 exceeds the short-circuit overcurrent threshold Vk, the comparator 34 of the current detection circuit 33 outputs a high-level detection signal to the control unit 11. Furthermore, when the detection voltage of the off-drive terminal MN becomes higher than the short-circuit overcurrent threshold Vm, the comparator 19a of the first voltage detection circuit 18 outputs a high-level detection signal to the control unit 11.

When the current detection circuit 33 detects that the short-circuit overcurrent threshold Vk has been exceeded and the comparator 19a of the first voltage detection circuit 18 detects that the short-circuit overcurrent threshold Vm has been exceeded, the control section 11 starts driving. The IC 10 turns on its internal flag at time t23a, and then stops driving the ON drive circuit 12 and drives the soft cutoff circuit 20.

As a result, the gate G of the IGBT1 is cut off, and the MOS transistor 21 of the soft cutoff circuit 20 is turned on, so that the gate charge of the IGBT1 is discharged from the resistor 23 to the ground through the cutoff drive terminal SCO and the MOS transistor 21 from time t24. be done. At this time, since the parallel connection circuit 24 is configured between the cutoff drive terminal SCO and the gate of the IGBT 1, when the same current is applied to these resistors 26 and the diode 25, the forward voltage Vf of the diode 25 is instantaneously reduced. Since the voltage drops, the gate voltage of the IGBT 1 can be quickly lowered. After that, the gate voltage of IGBT1 continues to decrease.

During this time, the second voltage detection circuit 27 is detecting the voltage at the cutoff drive terminal SCO. The cutoff drive terminal SCO falls to the ground level at time t24 simultaneously with the turning on of the MOS transistor 21. Therefore, the detection operation cannot be performed through the cutoff drive terminal SCO. On the other hand, since the MOS transistor 15 of the OFF drive circuit 14 is in the OFF state, the first voltage detection circuit 18 is maintained in a state capable of detecting the gate voltage of the IGBT 1.

The control unit 11 uses the detection signal of the first voltage detection circuit 18 when driving the soft cutoff circuit 20. When the gate voltage of the IGBT 1 decreases and reaches the off-holding threshold Vt at time t25, the first voltage detection circuit 18 outputs a high-level detection signal. Thereby, the control unit 11 outputs an off-hold drive signal to the off-hold drive circuit 29.

The off-holding drive circuit 29 applies a drive signal to the gate of the off-holding MOS transistor 6 via the off-holding drive terminal SOUT to turn it on. Then, the gate charge of IGBT1 is rapidly discharged via the on-resistance of MOS transistor 6, and the gate voltage instantly drops to the ground level. As a result, the gate voltage of the IGBT 1 is maintained at the ground level, so that the IGBT 1 is fixed in the off state.

In the above operation, the second voltage detection circuit 27 cannot be used between time t24 and time t25 because the soft cutoff circuit 20 performs soft cutoff. However, in other periods except for the period between time t24 and time t25, neither the OFF drive circuit 14 nor the soft cutoff circuit 20 is used, so the first voltage detection circuit 18 and the second voltage detection circuit 27 are not used. Either detection signal can be used, and by using both detection signals, erroneous detection due to noise etc. can be prevented and reliability can be increased.

According to this embodiment, the control unit 11 detects that a predetermined short-circuit overcurrent threshold Vk has been reached by the current detection circuit 33 when the power element 1 is turned on, and also controls the off-drive terminal MN. A short circuit or an overcurrent is determined when the voltage is determined to be higher than a predetermined short circuit overcurrent threshold Vm.

For example, even if an overcurrent temporarily flows through the power element 1 due to some noise and the current detection circuit 33 detects that the detected current has reached the short-circuit overcurrent threshold Vk, the detected voltage of the off-drive terminal MN If the current does not reach the short circuit overcurrent threshold Vm, it will not be determined that there is a short circuit or an overcurrent. This allows the influence of noise to be excluded. By using the detection voltage of the off-drive terminal MN, reliability of short circuit or overcurrent detection can be improved.

(Modified example)
In this embodiment, when it is detected that the detected current of the power element 1 reaches the short-circuit overcurrent threshold Vk and the detected voltage of the off-drive terminal MN reaches the short-circuit overcurrent threshold Vm, the control unit 11 software Although the cutoff circuit 20 is driven and the voltage at the off drive terminal MN is monitored by the comparator 19a of the first voltage detection circuit 18, the present invention is not limited to this.

Further, when it is detected that the detected current of the power element 1 reaches the short-circuit overcurrent threshold Vk and the detected voltage of the off-drive terminal MN reaches the short-circuit overcurrent threshold Vm, the controller 11 turns the off-drive circuit 14 on. It may be driven. At this time, since the MOS transistor 21 of the soft cutoff circuit 20 is in the off state, it is preferable that the second voltage detection circuit 27 detects the gate voltage of the IGBT 1, and the voltage of the soft cutoff terminal SCO is adjusted to the short circuit overcurrent threshold Vm by the comparator 28a. It is better to detect whether it has been reached or not. As a result, the influence of noise can be excluded as described above, and the reliability of short circuit or overcurrent detection can be improved by using the detection voltage of the off-drive terminal MN.

Furthermore, regardless of whether or not it is detected that the detected voltage of the off-drive terminal MN has reached the short-circuit overcurrent threshold Vm, the current detection circuit 34 detects that the detected current of the power element 1 has reached the short-circuit overcurrent threshold Vk. A short circuit or an overcurrent may be determined based on the detection of the current. Even if a short circuit or overcurrent flows, it can be safely detected. In this case, the control unit 11 may drive the soft cutoff circuit 20 or may drive the off drive circuit 14. As a result, the same effect as described above can be obtained.

(Third embodiment)
A third embodiment will be described with reference to FIG. 6. As shown in FIG. 6, a plurality of IGBTs 1a and 1b to be driven may be connected in parallel and driven. The number of parallel-connected IGBTs 1a and 1b to be simultaneously driven may be determined according to the driving capability of the power element driving device A, and is not limited to two, but may be three or more.

As shown in FIG. 6, the power element driving device A is mainly composed of a driving IC 110, and is configured to simultaneously drive IGBTs 1a and 1b as a plurality of power elements through resistors 13a and 13b. Note that a sense emitter is configured in each of the plurality of IGBTs 1a and 1b. Although not shown, these plural IGBTs 1a and 1b are used with their collectors and emitters commonly connected in parallel.

Resistors 2a and 2b are connected to the sense emitters of IGBTs 1a and 1b, respectively, and the detection voltages of resistors 2a and 2b are input to the current detection circuit 33 through current detection terminals SOC1 and SOC2. The current detection circuit 33 includes comparators 34a and 34b, and inputs the short-circuit overcurrent threshold Vk to an inverting input terminal as a comparison reference.

The off-drive circuit 14 is configured to simultaneously turn off the plurality of IGBTs 1a and 1b through the off-drive terminal MN and the resistor 17. Parallel connection circuits 5 are configured between the gates of the plurality of IGBTs 1a and 1b and the OFF drive terminal MN of the OFF drive circuit 14, respectively. The off-drive circuit 14 is configured to turn off the plurality of IGBTs 1a and 1b by applying the same control voltage to the gates of all the plurality of IGBTs 1a and 1b through the parallel connection circuit 5.

The soft cutoff circuit 20 is configured to soft cut off the plurality of IGBTs 1a and 1b simultaneously through the soft cutoff terminal SCO and the resistor 23. A parallel connection circuit 24 is configured between the gates of the plurality of IGBTs 1a and 1b and the soft cutoff terminal SCO of the soft cutoff circuit 20, respectively. The soft cutoff circuit 20 is configured to be able to softly cut off the plurality of IGBTs 1a and 1b by applying the same control voltage to the gates of all the plurality of IGBTs 1a and 1b through the parallel connection circuit 24. It has been confirmed that this embodiment also exhibits the same behavior as the above-described normal operation, operation at half-on detection, and operation at short-circuit overcurrent detection, and has the same effects as the above-mentioned embodiment. .

(Fourth embodiment)
A fourth embodiment will be described with reference to FIG. 7. A short circuit or an overcurrent may be detected by detecting the gate voltages of the plurality of IGBTs 1a and 1b through the cutoff drive terminal SCO and the off drive terminal MN.

The first voltage detection circuit 18 includes a comparator 19a, and is configured by inputting the short-circuit overcurrent threshold Vm into an inverting input terminal, and inputting the voltage of the off-drive terminal MN into a non-inverting input terminal. The first voltage detection circuit 18 includes a comparator 19b and is configured by inputting the off-holding threshold Vt to an inverting input terminal and inputting the voltage of the off-drive terminal MN to a non-inverting input terminal.

The comparator 19b has the same function as the comparator 19 of the above-mentioned embodiment, so a description thereof will be omitted. The comparator 19a detects a voltage based on the gate voltage of the IGBT 1 through the off-drive terminal MN, and outputs a detection signal to the control unit 11 to determine whether the short-circuit overcurrent threshold Vm has been reached. The control unit 11 can determine whether a short circuit or overcurrent is occurring based on this detection signal.

The second voltage detection circuit 27 includes a comparator 28a, and is configured by inputting the short-circuit overcurrent threshold Vm into an inverting input terminal, and inputting the voltage of the cutoff drive terminal SCO into a non-inverting input terminal. The second voltage detection circuit 27 includes a comparator 28b and is configured by inputting the off-holding threshold Vt to an inverting input terminal and inputting the voltage of the cutoff drive terminal SCO to a non-inverting input terminal.

The comparator 28b has the same function as the comparator 28 of the embodiment described above, so a description thereof will be omitted. The comparator 28a detects a voltage based on the gate voltage of the IGBT 1 through the cutoff drive terminal SCO, and outputs a detection signal to the control unit 11 to determine whether the short circuit overcurrent threshold Vm has been reached. The control unit 11 can determine whether a short circuit or overcurrent is occurring based on this detection signal. This embodiment also provides the same effects as the embodiment described above.

(Fifth embodiment)
A fifth embodiment will be described with reference to FIG. 8. As shown in FIG. 8, the current detection circuit 33 includes comparators 34c and 34d. The comparator 34c is configured as a short circuit detection section that inputs a predetermined short circuit determination threshold Vk1 to an inverting input terminal, and inputs a sense emitter current detection voltage to a non-inverting input terminal through a current detection terminal SOC.

The comparator 34d is configured as an overcurrent detection section that inputs a predetermined overcurrent determination threshold Vk2 to an inverting input terminal, and inputs a sense emitter current detection voltage to a non-inverting input terminal through a current detection terminal SOC. The rest of the configuration of the power element driving device A is the same as the configuration of FIG. 1, so illustration and description thereof will be omitted.

In such a configuration, the short circuit determination threshold Vk1 and the overcurrent determination threshold Vk2 are preferably set to different values. Then, short circuit detection and overcurrent detection can be separated. If the short-circuit determination threshold Vk1 and the overcurrent determination threshold Vk2 are set to different values, the thresholds can be flexibly adjusted and the degree of freedom in setting can be increased.

(Sixth embodiment)
A sixth embodiment will be described with reference to FIG. 9. As shown in FIG. 9, the first voltage detection circuit 18 includes comparators 19c and 19d in addition to the comparator 19. The comparator 19c is configured as a short-circuit detection section that inputs a predetermined short-circuit determination threshold Vm1 to an inverting input terminal and inputs the detection voltage of the off-drive terminal MN to a non-inverting input terminal. The comparator 19d is configured as an overcurrent detection section that inputs a predetermined overcurrent determination threshold Vm2 to an inverting input terminal and inputs the detected voltage of the off-drive terminal MN to a non-inverting input terminal.

In addition to the comparator 28, the second voltage detection circuit 27 includes comparators 28c and 28d. The comparator 28c is configured as a short circuit detection section that inputs a predetermined short circuit determination threshold Vm1 to an inverting input terminal and inputs the detected voltage of the soft cutoff terminal SCO to a non-inverting input terminal. The comparator 28d is configured as an overcurrent detection section that inputs a predetermined overcurrent determination threshold Vm2 to an inverting input terminal and inputs the detected voltage of the soft cutoff terminal SCO to a non-inverting input terminal. The rest of the configuration of the power element driving device A is the same as the configuration in FIG. 1, so the explanation will be omitted.

In such a configuration, it is preferable that the short circuit determination threshold Vm1 and the overcurrent determination threshold Vm2 be set to different values. Then, short circuit detection and overcurrent detection can be separated. If the short-circuit determination threshold Vm1 and the overcurrent determination threshold Vm2 are set to different values, the thresholds can be flexibly adjusted and the degree of freedom in setting can be increased.

(Other embodiments)
The present invention is not limited to the above-mentioned embodiment, and for example, the following modifications or expansions are possible. Although IGBTs 1, 1a, and 1b are illustrated as power elements, the present invention is not limited thereto, and MOSFETs may also be used. For example, power elements using silicon carbide (SiC) or silicon (Si) as a semiconductor material can be applied.

Although the present invention has been described based on the embodiments described above, it is understood that the present invention is not limited to the embodiments or structures. The present invention also includes various modifications and equivalent modifications. In addition, various combinations and configurations, as well as other combinations and configurations that include one, more, or fewer elements, fall within the scope and spirit of the present invention.

In the drawing, 1, 1a, and 1b are IGBTs (power devices), 11 is a control unit, 14 is an off drive circuit, MN is an off drive terminal, 20 is a soft cutoff circuit, 29 is an off holding drive circuit, and 18 is a first voltage Detection circuit, 27 is a second voltage detection circuit, 34c is a comparator (short circuit detection section), 34d is a comparator (short circuit detection section), Vk is the first short circuit overcurrent threshold, Vm is the second short circuit overcurrent threshold, Vk1, Vm1 indicates a short circuit determination threshold, and Vk2 and Vm2 indicate overcurrent determination thresholds.

Claims (11)

an OFF drive circuit (14) that normally performs OFF drive from an OFF drive terminal (MN) by extracting the gate charge of the power element (1, 1a, 1b) based on an OFF command of a drive signal (MIN);
a soft cut-off circuit (20) that drives the power element off from a cut-off drive terminal by extracting gate charge at a speed different from when the off-drive is performed by the off-drive circuit;
an off-holding drive circuit (29) that maintains the off state of the power element by connecting the gate and source of the power element to a lower impedance than the off-drive circuit;
a first voltage detection circuit (18) that monitors the control voltage of the power element at the off drive terminal of the off drive circuit; and a first voltage detection circuit (18) that monitors the control voltage of the power element at the cutoff drive terminal of the soft cutoff circuit. 2 voltage detection circuit (27),
a control unit (11) that determines and controls control content based on the drive signal and results of monitoring control voltages by the first voltage detection circuit and the second voltage detection circuit;
A power element drive device comprising: The power element driving device according to claim 1, wherein the power element to be driven is driven as one. The power element driving device according to claim 1, wherein a plurality of the power elements to be driven are connected in parallel and driven. The control unit is configured to control the control unit when the voltage at both terminals of the off drive terminal (MN) and the cutoff drive terminal (SCO) decreases to a predetermined off-holding threshold while turning off the power element. The power element drive device according to any one of claims 1 to 3, wherein the power element drive device is controlled to be maintained in an off state by an off-holding drive circuit. The control unit is configured to maintain a state in which a voltage of one of the off drive terminal (MN) and the cutoff drive terminal (SCO) is higher than a predetermined off holding threshold for a predetermined period of time when the power element is turned off. (T1) The power element drive device according to any one of claims 1 to 3, wherein half-on detection is performed when the above continues, and control is performed such that the off-state is maintained by the off-holding drive circuit at the timing of the half-on detection. . a first short-circuit overcurrent detection for detecting whether the detected current of the power element has reached a predetermined first short-circuit overcurrent threshold (Vk) in order to detect whether an overcurrent or a short-circuit current has flowed through the power element; The power element drive device according to any one of claims 1 to 5, further comprising a portion (33). A second short-circuit overcurrent detection section (19a, 28a) that detects whether the detected voltage of the gate voltage of the power element has reached a predetermined second short-circuit overcurrent threshold (Vm),
The control unit detects that a predetermined first short-circuit overcurrent threshold (Vk) has been reached by the first short-circuit overcurrent detection unit when the power element is turned on, and detects that the second short-circuit overcurrent threshold (Vk) has been reached. A short circuit or an overcurrent occurs when the overcurrent detection unit determines that the voltage of either the off drive terminal (MN) or the cutoff drive terminal (SCO) is higher than a predetermined second short circuit overcurrent threshold (Vm). The power element driving device according to claim 6, wherein the power element driving device determines that. The first short-circuit overcurrent detection section includes a short-circuit detection section (34c) that uses a predetermined short-circuit judgment threshold (Vk1) to judge whether the power element is short-circuited, and a short-circuit detection section (34c) that uses a predetermined overcurrent judgment threshold (Vk2) to judge the short-circuit of the power element. An overcurrent detection section (34d) that detects whether the current flowing through the power element is an overcurrent,
The power element drive according to claim 6 or 7, wherein the predetermined first short-circuit overcurrent threshold (Vk) is set to a value different from the short-circuit determination threshold (Vk1) and the overcurrent determination threshold (Vk2). Device. The second short-circuit overcurrent detection section includes a short-circuit detection section (19c) that uses a predetermined short-circuit judgment threshold (Vm1) to judge whether the power element is short-circuited, and a short-circuit detection section (19c) that uses a predetermined overcurrent judgment threshold (Vm2) to judge the short-circuit of the power element. An overcurrent detection unit (19d) that detects whether the current flowing through the power element is an overcurrent,
The power element drive device according to claim 7 , wherein the predetermined second short-circuit overcurrent threshold (Vm) is set to a value different from the short-circuit determination threshold (Vm1) and the overcurrent determination threshold (Vm2). The power element drive device according to any one of claims 1 to 9, further comprising a parallel connection circuit (5) of a resistor (3) and a diode (4) provided between the gate of the power element and the off-drive terminal. . The power element drive device according to any one of claims 1 to 10, further comprising a parallel connection circuit (24) of a resistor (26) and a diode (25) between the gate of the power element and the cutoff drive terminal. .

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