JP7413386B2 - 測定後の量子ビット周波数変更のためのスタッド・バンプ - Google Patents
測定後の量子ビット周波数変更のためのスタッド・バンプ Download PDFInfo
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- 239000002096 quantum dot Substances 0.000 title claims description 230
- 238000005259 measurement Methods 0.000 title claims description 27
- 239000002184 metal Substances 0.000 claims description 173
- 229910052751 metal Inorganic materials 0.000 claims description 173
- 229910000679 solder Inorganic materials 0.000 claims description 128
- 238000012360 testing method Methods 0.000 claims description 125
- 238000000034 method Methods 0.000 claims description 55
- 230000008878 coupling Effects 0.000 claims description 39
- 238000010168 coupling process Methods 0.000 claims description 39
- 238000005859 coupling reaction Methods 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000001816 cooling Methods 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 39
- 239000000758 substrate Substances 0.000 description 16
- 230000004048 modification Effects 0.000 description 9
- 238000012986 modification Methods 0.000 description 9
- 230000007704 transition Effects 0.000 description 7
- 238000000137 annealing Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000005224 laser annealing Methods 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000003698 laser cutting Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000012993 chemical processing Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000002887 superconductor Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000009529 body temperature measurement Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000013101 initial test Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000000386 microscopy Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000002174 soft lithography Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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Description
Claims (19)
- 量子コンピュータ・チップを製造する方法であって、
量子ビット・チップの動作温度で、前記量子ビット・チップ上の量子ビットのためのテスト・インターポーザ・チップに結合された前記量子ビット・チップに対する周波数測定を実行することと、
前記周波数測定の実行後に、前記量子ビット・チップを前記テスト・インターポーザ・チップから引き離すことと、
前記量子ビット・チップを前記テスト・インターポーザ・チップから引き離した後に、測定された前記周波数が対象の固定周波数から逸脱している前記量子ビットの前記周波数を、前記対象の固定周波数となるように変更することと、
前記量子ビットの前記周波数を前記対象の固定周波数となるように変更した後に、前記量子ビット・チップをデバイス・インターポーザ・チップに結合することとを含む、方法。 - 前記周波数測定を実行する前に、前記量子ビット・チップを前記テスト・インターポーザ・チップに結合することと、
前記結合された量子ビット・チップおよびテスト・インターポーザ・チップを前記量子ビット・チップの前記動作温度に冷却することとをさらに含む、請求項1に記載の方法。 - 前記量子ビット・チップが少なくとも1つの金属パッドおよび各金属パッド上に形成された金属スタッドを備え、
前記テスト・インターポーザ・チップが少なくとも1つの金属パッドおよび各金属パッド上に形成されたテストはんだバンプを備え、
前記デバイス・インターポーザ・チップが少なくとも1つの金属パッドおよび各金属パッド上に形成されたデバイスはんだバンプを備え、
前記量子ビット・チップを前記テスト・インターポーザ・チップに結合することが、前記量子ビット・チップ上に形成された前記金属スタッドを前記テスト・インターポーザ・チップ上に形成された前記テストはんだバンプに結合することを含み、
前記量子ビット・チップを前記デバイス・インターポーザ・チップに結合することが、前記量子ビット・チップ上に形成された前記金属スタッドを前記デバイス・インターポーザ・チップ上に形成された前記デバイスはんだバンプに結合することを含む、請求項2に記載の方法。 - 前記テストはんだバンプが、前記金属スタッドが形成されている前記金属パッドの第1の領域と接触し、
前記デバイスはんだバンプが、前記金属スタッドが形成されている前記金属パッドの第2の領域と接触し、前記第2の領域の少なくとも一部が前記第1の領域と異なっている、請求項3に記載の方法。 - 前記量子ビット・チップが、各金属パッド上に形成された第2の金属スタッドをさらに備え、前記デバイス・インターポーザ・チップが、少なくとも1つの第2の金属パッドおよび各第2の金属パッド上に形成された第2のデバイスはんだバンプをさらに備え、
前記方法が、前記量子ビット・チップ上に形成された前記第2の金属スタッドを前記デバイス・インターポーザ・チップ上に形成された前記第2のデバイスはんだバンプに結合することをさらに含む、請求項3に記載の方法。 - 前記量子ビット・チップが、各金属パッド上に形成された少なくとも1つの金属板状の柱をさらに備え、前記デバイス・インターポーザ・チップが、少なくとも1つの第2の金属パッドおよび各第2の金属パッド上に形成された第2のデバイスはんだバンプをさらに備え、
前記方法が、前記量子ビット・チップ上に形成された前記金属板状の柱を前記デバイス・インターポーザ・チップ上に形成された前記第2のデバイスはんだバンプに結合することをさらに含む、請求項3に記載の方法。 - 前記量子ビット・チップが複数の金属スタッドを備え、
前記テスト・インターポーザ・チップが複数のテストはんだバンプを備え、
前記デバイス・インターポーザ・チップが複数のデバイスはんだバンプを備える、請求項3に記載の方法。 - 前記複数のテストはんだバンプにおけるテストはんだバンプの数が、前記複数の金属スタッドにおける金属スタッドの数よりも少なく、
前記複数のテストはんだバンプにおけるテストはんだバンプの数が、前記複数のデバイスはんだバンプにおけるデバイスはんだバンプの数よりも少なく、
前記量子ビット・チップを前記テスト・インターポーザ・チップに結合することが、前記複数の金属スタッドのサブセットを前記複数のテストはんだバンプに結合することを含み、
前記量子ビット・チップを前記デバイス・インターポーザ・チップに結合することが、前記複数の金属スタッドを前記複数のデバイスはんだバンプに結合することを含む、請求項7に記載の方法。 - 前記量子ビット・チップが複数の金属板状の柱をさらに備えており、
前記量子ビット・チップを前記テスト・インターポーザ・チップに結合することが、前記複数の金属スタッドを前記複数のテストはんだバンプに結合することを含み、
前記量子ビット・チップを前記デバイス・インターポーザ・チップに結合することが、前記複数の金属スタッドを前記複数のデバイスはんだバンプのうちの第1の複数のデバイスはんだバンプに結合することと、前記複数の金属板状の柱を前記複数のデバイスはんだバンプのうちの第2の複数のデバイスはんだバンプに結合することとを含む、請求項7に記載の方法。 - デバイスはんだバンプの数およびサイズが前記テストはんだバンプの数およびサイズよりも大きい、請求項8または9に記載の方法。
- 前記デバイス・インターポーザ・チップが、再利用された前記テスト・インターポーザ・チップであり、前記方法が、前記引き離しの後に前記テストはんだバンプを前記テスト・インターポーザ・チップから除去することと、前記複数のデバイスはんだバンプを前記テスト・インターポーザ・チップ上に形成することとをさらに含む、請求項8ないし10のいずれか1項に記載の方法。
- 前記量子ビット・チップを前記テスト・インターポーザ・チップに結合する前に、前記量子ビット・チップ上に形成されたジョセフソン接合全体にわたって抵抗測定を実行することをさらに含む、請求項1ないし11のいずれか1項に記載の方法。
- 前記結合された量子ビット・チップおよび前記テスト・インターポーザ・チップを、前記周波数の前記変更を実行できる温度に加熱することをさらに含む、請求項1ないし12のいずれか1項に記載の方法。
- 少なくとも1つの金属パッドおよび各金属パッド上に形成された金属スタッドを備える量子ビット・チップと、
少なくとも1つの金属パッドおよび各金属パッド上に形成されたデバイスはんだバンプを備えるデバイス・インターポーザ・チップと、
前記量子ビット・チップ上に形成された前記金属スタッドが、前記デバイス・インターポーザ・チップ上に形成された前記デバイスはんだバンプに結合される量子コンピュータ・チップであって、
前記量子ビット・チップは、
前記量子ビット・チップ上の量子ビットのための、少なくとも1つの金属パッドおよび各金属パッド上に形成されたテストはんだバンプを備えるテスト・インターポーザ・チップに結合され、前記量子ビット・チップの動作温度で前記量子ビット・チップに対する周波数測定を実行し、
前記周波数測定の実行後に、前記量子ビット・チップを前記テスト・インターポーザ・チップから引き離し、
前記量子ビット・チップを前記テスト・インターポーザ・チップから引き離した後に、測定された前記周波数が対象の固定周波数から逸脱している前記量子ビットの前記周波数を、前記対象の固定周波数となるように変更し、
前記量子ビットの前記周波数を前記対象の固定周波数となるように変更した後に、前記量子ビット・チップを前記デバイス・インターポーザ・チップに結合する、
前記量子コンピュータ・チップ。 - 前記金属スタッドが、超伝導でない材料から形成され、前記デバイスはんだバンプが前記量子ビット・チップ上に形成された前記金属スタッドを覆う距離または前記デバイスはんだバンプが前記量子ビット・チップ上に形成された前記金属パッドに接触する距離が、前記デバイスはんだバンプのコヒーレンス長よりもはるかに大きい、請求項14に記載の量子コンピュータ・チップ。
- 前記テストはんだバンプが、超伝導である材料から形成され、前記デバイスはんだバンプが、超伝導である材料から形成される、請求項14に記載の量子コンピュータ・チップ。
- 前記量子ビット・チップが、各金属パッド上に形成された第2の金属スタッドをさらに備え、前記デバイス・インターポーザ・チップが、少なくとも1つの第2の金属パッドおよび各第2の金属パッド上に形成された第2のデバイスはんだバンプをさらに備え、
前記第2の金属スタッドが前記第2のデバイスはんだバンプに結合される、請求項14に記載の量子コンピュータ・チップ。 - 前記量子ビット・チップが、各金属パッド上に形成された少なくとも1つの金属板状の柱をさらに備え、前記デバイス・インターポーザ・チップが、少なくとも1つの第2の金属パッドおよび各第2の金属パッド上に形成された第2のデバイスはんだバンプをさらに備え、
前記金属板状の柱が前記第2のデバイスはんだバンプに結合される、請求項14に記載の量子コンピュータ・チップ。 - 前記量子ビット・チップの一部および前記デバイス・インターポーザ・チップの一部が読み出し共振器を形成する、請求項14に記載の量子コンピュータ・チップ。
方法。
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