JP7408722B2 - Error correction device, encoding device and communication system - Google Patents

Description

The present invention relates to an error correction device, a coding device, and a communication system that can improve error correction capability while suppressing circuit scale in a communication system.

In coherent optical communication, in order to improve transmission characteristics, distortion and frequency/phase fluctuations that occur during transmission are compensated for by digital signal processing.In addition to the above compensation function, to further improve transmission characteristics, An error correction device is installed between the transmitter and the receiver to reduce data errors in transmission characteristics. Generally, the transmitting side performs error correction encoding on data, and the receiving side performs error correction in accordance with the encoding, thereby improving transmission characteristics.

Further, digital transmission systems using multilevel modulation such as 16QAM (Quadrature Amplitude Modulation) and 64QAM have been put into practical use as modulation methods that increase the speed of data transmission. 2. Description of the Related Art As an error correction technique used in a digital multilevel modulation method, techniques disclosed in Patent Document 1 and Patent Document 2, for example, are known.

The transmitting device and receiving device disclosed in Patent Document 1 solve the problem that error correction efficiency decreases due to bias in the reliability of each bit assigned to a symbol in multi-level modulation, by using two types of devices with different correction capabilities. By combining FEC (Forward Error Correction) decoding processing, correction efficiency is improved.

However, the technology disclosed in Patent Document 1 requires FEC distribution processing to determine the coding rate and adjust the bit size accordingly, and this FEC distribution processing is complex, resulting in a long processing time. There was a problem of increase in size and circuit scale.

In the transmission device disclosed in Patent Document 2, the frequency of code error occurrence differs due to the influence of noise in 64QAM encoding, so the code of bits with high error occurrence frequency among the 6-bit code of one symbol is subjected to error correction. Improve error correction ability by encoding bits with low error occurrence frequency using error correction codes with low redundancy and low error correction ability. That's what I do.

However, in the technology disclosed in Patent Document 2, when decoding is performed on the receiving side, a code decoded by a correction code with high error correction ability is used in the process of decoding another correction code with low error correction ability. Since the processing becomes complicated, there are problems of increased processing time and circuit scale.

International publication WO2010/146694 Japanese Patent Application Publication No. 2002-064579

The present invention has been made to solve the above problems, and provides an error correction device, a coding device, and a communication system that can improve error correction capability while suppressing increases in processing time and circuit scale. The purpose is to

The error correction device of the present invention performs error correction on a first bit string that has been subjected to first encoding and second encoding on the transmitting side of received data demodulated by multilevel modulation symbol demapping processing. , a first error correction decoder configured to perform the correction based on a second redundant bit added to the first bit string by the second encoding, and a transmitting side of the demodulated received data. Error correction of the second bit string subjected to the first encoding and third encoding is performed based on the third redundant bit added to the second bit string by the third encoding. a second error correction decoding unit configured to perform error correction on the information bits included in the error-corrected first and second bit strings; a third error correction decoding unit configured to perform the correction based on the added first redundant bit, and the second bit string is configured to perform the error correction decoding based on the added first redundant bit; a third bit string that is allocated to bits lower than the bit to which the bit string of 1 is allocated, and a bit to the lower side than the bit to which the third bit string is allocated among the plurality of bits corresponding to the symbol; The fourth bit string assigned to A fourth error correction decoding unit configured to perform error correction of the fourth bit string based on the third redundant bits added to the fourth bit string by the third encoding. The redundancy level of the third encoding for the third bit string is equal to the redundancy level of the second encoding. The redundancy of the third encoding for the fourth bit string is four times the redundancy of the second encoding, and the output bit of the first error correction decoding unit The total number of output bits of the second error correction decoding section and the number of output bits of the third error correction decoding section match the number of input bits of the third error correction decoding section.

Furthermore, the error correction device of the present invention corrects errors in the first bit string that has been subjected to first encoding and second encoding on the transmitting side of the received data demodulated by multilevel modulation symbol demapping processing. a first error correction decoding unit configured to perform correction based on second redundant bits added to the first bit string by the second encoding; Error correction of the second bit string subjected to the first encoding and third encoding on the transmitting side is performed on the third redundant bit added to the second bit string by the third encoding. A second error correction decoding unit configured to perform error correction of information bits included in the error-corrected first and second bit strings based on the information by the first encoding. a third error correction decoding unit configured to perform the correction based on the first redundant bits added to the bits, and the second bit string includes a plurality of bits corresponding to symbols of multi-level modulation. The bit string is a bit string assigned to a lower bit than the bit to which the first bit string is allocated, and the third coding redundancy is a predetermined number (a predetermined number) of the second coding redundancy. is a real number greater than 0) times the number of output bits of the first error correction decoding unit and the number of output bits of the second error correction decoding unit, which is equal to the input bits of the third error correction decoding unit. The first encoding is a process of adding the first redundant bits in the row direction for each column to the information bits included in the first and second bit strings; Encoding No. 2 is a process of adding the second redundant bits in the column direction to each of the information bits included in the first bit string and the first redundant bits added to the information bits. , the third encoding adds the third redundant bits in the column direction to each of the information bits included in the second bit string and the first redundant bits added to the information bits. This processing is characterized in that in the configuration of the demodulated received data, the arrangement direction of the first redundant bits and the arrangement direction of the second and third redundant bits are orthogonal.
Further, in one configuration example of the error correction device of the present invention, the redundancy of the third encoding is twice the redundancy of the second encoding.

Further, the encoding device of the present invention includes a first encoding unit configured to perform first encoding on transmission data, and a first encoding unit configured to perform first encoding on transmission data; a second encoding section configured to perform second encoding on the first bit string; and a second bit string of the transmission data encoded by the first encoding section. a third encoding section configured to perform a third encoding on the second bit string, and the second bit string is configured to perform a third encoding on the outputs of the second and third encoding sections. A third bit string is assigned to bits lower than the bits to which the first bit string is allocated among the plurality of bits corresponding to the multi-level modulation symbol , and a third bit string among the plurality of bits corresponding to the symbol. The third bit string is divided into two parts, a fourth bit string being allocated to lower bits than the bits to which the third bit string is allocated, and the third encoding unit is configured to perform the third bit string with respect to the third bit string. A fourth encoding unit configured to perform encoding, and a fifth encoding unit configured to perform the third encoding on the fourth bit string, The redundancy of the third encoding for the third bit string is twice the redundancy of the second encoding, and the redundancy of the third encoding for the fourth bit string is twice the redundancy of the second encoding. It is characterized in that the redundancy is four times the redundancy of the second encoding .

Further, the encoding device of the present invention includes a first encoding unit configured to perform first encoding on transmission data, and a first encoding unit configured to perform first encoding on transmission data; a second encoding section configured to perform second encoding on the first bit string; and a second bit string of the transmission data encoded by the first encoding section. and a third encoding unit configured to perform third encoding on the output of the second and third encoding units, and the second bit string is configured to perform a third encoding on the outputs of the second and third encoding units. is a bit string that is assigned to a lower bit than the bit to which the first bit string is allocated among a plurality of bits corresponding to a symbol of multilevel modulation, and the redundancy of the third encoding is The redundancy of the second encoding is multiplied by a predetermined number (the predetermined number is a real number greater than 0), and the first encoding is performed for each column of information bits included in the first and second bit strings. is a process of adding first redundant bits in the row direction, and the second encoding is a process of adding first redundant bits in the row direction to The third encoding is a process of adding second redundant bits in the column direction to This is a process of adding a third redundant bit in the column direction to each of the first redundant bits in the arrangement direction of the first redundant bits and the third redundant bit in the configuration of data output from the second and third encoding units. The arrangement direction of the second and third redundant bits is orthogonal to each other.
Further, in one configuration example of the encoding device of the present invention, the redundancy of the third encoding is twice the redundancy of the second encoding.

Further, the communication system of the present invention includes an encoding device configured to encode transmission data, and a symbol mapping configured to perform multilevel modulation of data encoded by the encoding device. a symbol demapping device configured to demodulate encoded data from a signal received from the transmitting device; and a symbol demapping device configured to demodulate data encoded from a signal received from the transmitting device, and perform error correction on the data demodulated by the symbol demapping device. a first encoding unit configured to perform a first encoding on the transmission data; and an error correction device configured to perform a first encoding on the transmission data; a second encoding section configured to perform second encoding on the first bit string of the transmission data encoded by the encoding section; and a third encoding unit configured to perform third encoding on the second bit string of the transmitted data, the error correction device configured to perform third encoding on the second bit string of the transmitted data, A first error correction decoding unit configured to perform error correction of the first bit string of data based on second redundant bits added to the first bit string by the second encoding. and a second bit string configured to perform error correction of the second bit string of the demodulated data based on third redundant bits added to the second bit string by the third encoding. and a second error correction decoding unit that performs error correction of the information bits included in the error-corrected first and second bit strings using a first redundant decoder added to the information bits by the first encoding. a third error correction decoding unit configured to perform the correction based on bits, and the second bit string is assigned the first bit string among a plurality of bits corresponding to symbols of multilevel modulation. a third bit string that is assigned to bits lower than the bits; and a fourth bit string that is assigned to the bits lower than the bits to which the third bit string is assigned among the plurality of bits corresponding to the symbol. The second error correction decoding unit performs error correction of the third bit string based on a third redundant bit added to the third bit string by the third encoding. A fourth error correction decoding unit configured as follows, and configured to perform error correction of the fourth bit string based on third redundant bits added to the fourth bit string by the third encoding. the redundancy of the third encoding for the third bit string is twice the redundancy of the second encoding; The redundancy of the third encoding for the fourth bit string is four times the redundancy of the second encoding, and the number of output bits of the first error correction decoding unit and the second error correction The total number of output bits of the decoding section matches the number of input bits of the third error correction decoding section.
Further, the communication system of the present invention includes an encoding device configured to encode transmission data, and a symbol mapping configured to perform multilevel modulation of data encoded by the encoding device. a symbol demapping device configured to demodulate encoded data from a signal received from the transmitting device; and a symbol demapping device configured to demodulate data encoded from a signal received from the transmitting device, and perform error correction on the data demodulated by the symbol demapping device. a first encoding unit configured to perform a first encoding on the transmission data; and an error correction device configured to perform a first encoding on the transmission data; a second encoding section configured to perform second encoding on the first bit string of the transmission data encoded by the encoding section; and a third encoding unit configured to perform third encoding on the second bit string of the transmitted data, the error correction device configured to perform third encoding on the second bit string of the transmitted data, A first error correction decoding unit configured to perform error correction of the first bit string of data based on second redundant bits added to the first bit string by the second encoding. and a second bit string configured to perform error correction of the second bit string of the demodulated data based on third redundant bits added to the second bit string by the third encoding. and a second error correction decoding unit that performs error correction of the information bits included in the error-corrected first and second bit strings using a first redundant decoder added to the information bits by the first encoding. a third error correction decoding unit configured to perform the correction based on bits, and the second bit string is assigned the first bit string among a plurality of bits corresponding to symbols of multilevel modulation. It is a bit string assigned to bits on the lower side than the bit, and the redundancy of the third encoding is a predetermined number (the predetermined number is a real number larger than 0) times the redundancy of the second encoding, The sum of the number of output bits of the first error correction decoding section and the number of output bits of the second error correction decoding section matches the number of input bits of the third error correction decoding section. The encoding is a process of adding the first redundant bits in the row direction for each column to the information bits included in the first and second bit strings, and the second encoding is a process of adding the first redundant bits in the row direction for each column. The third encoding is a process of adding the second redundant bits in the column direction to each of the information bits included in the bit string and the first redundant bits added to the information bits, and the third encoding This is a process of adding the third redundant bit in the column direction to each of the information bits included in the second bit string and the first redundant bit added to the information bit, and the demodulated received data In the configuration, the arrangement direction of the first redundant bits is orthogonal to the arrangement direction of the second and third redundant bits.

According to the present invention, the first error correction decoding section, the second error correction decoding section, and the third error correction decoding section are provided, and the second bit string is set among a plurality of bits corresponding to a symbol of multilevel modulation. , the bit string is assigned to bits lower than the bits to which the first bit string is assigned, the redundancy of the third encoding is set to a predetermined number times the redundancy of the second encoding, and the first error is By making the sum of the number of output bits of the correction decoding section and the number of output bits of the second error correction decoding section match the number of input bits of the third error correction decoding section, increases in processing time and circuit scale can be avoided. It is possible to improve the error correction ability while suppressing the errors.

FIG. 1 is a block diagram showing the configuration of a communication system according to a first embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the encoding device in the transmission signal processing device according to the first embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of an error correction device in a received signal processing device according to the first embodiment of the present invention. FIG. 4 is a diagram showing the configuration of a bit string encoded by the encoding device in the transmission signal processing device and a bit string demodulated by the symbol demapping device in the reception signal processing device in the first embodiment of the present invention. . FIG. 5 is a block diagram showing the configuration of an encoding device in a transmission signal processing device according to a second embodiment of the present invention. FIG. 6 is a diagram showing an example of symbol arrangement when the multilevel modulation method is 16QAM. FIG. 7 is a diagram showing an example of symbol mapping when the multilevel modulation method is 16QAM. FIG. 8 is a block diagram showing the configuration of an error correction device in a received signal processing device according to a second embodiment of the present invention. FIG. 9 is a diagram showing the configuration of a bit string encoded by the encoding device in the transmission signal processing device and a bit string demodulated by the symbol demapping device in the reception signal processing device in the third embodiment of the present invention. . FIG. 10 is a block diagram showing the configuration of an encoding device in a transmission signal processing device according to a third embodiment of the present invention. FIG. 11 is a block diagram showing the configuration of an error correction device in a received signal processing device according to a third embodiment of the present invention. FIG. 12 is a diagram showing an example of symbol arrangement when the multilevel modulation method is 64QAM. FIG. 13 is a diagram showing the configuration of a bit string encoded by the encoding device in the transmission signal processing device and a bit string demodulated by the symbol demapping device in the reception signal processing device in the fourth embodiment of the present invention. . FIG. 14 is a block diagram showing the configuration of an encoding device in a transmission signal processing device according to a fourth embodiment of the present invention. FIG. 15 is a diagram showing an example of symbol mapping when the multilevel modulation method is 64QAM. FIG. 16 is a block diagram showing the configuration of an error correction device in a received signal processing device according to a fourth embodiment of the present invention. FIG. 17 is a diagram showing the configuration of a bit string encoded by an encoding device in a transmission signal processing device and a bit string demodulated by a symbol demapping device in a reception signal processing device in the fifth embodiment of the present invention. . FIG. 18 is a block diagram showing the configuration of an encoding device in a transmission signal processing device according to a fifth embodiment of the present invention. FIG. 19 is a block diagram showing the configuration of an error correction device in a received signal processing device according to a fifth embodiment of the present invention.

[First example]
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a communication system according to a first embodiment of the present invention. FIG. 1 shows a configuration example in which an encoding device 10 and an error correction device 20 according to the present embodiment are applied to a communication system using a coherent optical communication method.

In the coherent optical communication system shown in FIG. 1, the transmitting device 6 includes a transmitting signal processing device 1 and an optical transmitting module 3. The receiving device 7 includes an optical receiving module 4 and a received signal processing device 2. The transmitting device 6 and the receiving device 7 are connected via an optical fiber transmission line 5. The transmitted signal processing device 1 includes an encoding device 10, and the received signal processing device 2 includes an error correction device 20.

The encoding device 10 in the transmission signal processing device 1 performs error correction encoding on transmission data. The optical transmission module 3 generates an optical signal based on transmission data that has been encoded for error correction. In general coherent optical communication, a horizontally polarized optical signal X and a vertically polarized optical signal Y are combined and transmitted. When QAM is used as the modulation method, the transmission data is divided into horizontally polarized optical signal data XI, XQ and vertically polarized optical signal data YI, YQ.

XI indicates the coordinate of the horizontally polarized optical signal data on the horizontal axis in the complex plane, and XQ indicates the coordinate of the horizontally polarized optical signal data on the orthogonal axis in the complex plane. Further, YI indicates the coordinate of the vertically polarized optical signal data on the horizontal axis in the complex plane, and YQ indicates the coordinate of the vertically polarized optical signal data on the orthogonal axis in the complex plane. Transmission data is mapped to coordinates on the complex plane of the carrier wave, and transmitted to the receiving side via the optical fiber transmission line 5.

The optical receiving module 4 generates received data from the received optical signal. The optical receiving module 4 outputs horizontally polarized optical signal data XI, XQ and vertically polarized optical signal data YI, YQ. These data XI, XQ, YI, YQ are converted into digital signals in the received signal processing device 2, and error correction processing is performed in the error correction device 20.

FIG. 2 is a block diagram showing the configuration of the encoding device 10 in the transmission signal processing device 1 according to this embodiment. The encoding device 10 includes an encoding section 100-A (second encoding section), an encoding section 100-B (third encoding section), and an encoding section 101 (first encoding section). It consists of

Encoding section 101 performs first encoding on input transmission data. Specifically, encoding section 101 generates first redundant bits for error correction performed on the receiving side from the information bits of the transmission data, and outputs the information bits and the first redundant bits.

Encoding section 100-A performs second encoding on the transmission data encoded by encoding section 101. Specifically, the encoding unit 100-A selects a bit string from a first bit string that is allocated to the upper bits of a plurality of bits corresponding to symbols of multi-level modulation among bit strings included in encoded transmission data. , generates second redundant bits for error correction performed on the receiving side, and outputs the first bit string and second redundant bits. The first bit string may include only the information bits of the transmission data, may include the information bits and the first redundant bits, or may include only the first redundant bits.

Encoding section 100-B performs third encoding on the transmission data encoded by encoding section 101. Specifically, encoding section 100-B encodes a second bit string that is assigned to the lower bits of a plurality of bits corresponding to symbols of multilevel modulation among bit strings included in encoded transmission data. , generates third redundant bits for error correction performed on the receiving side, and outputs the second bit string and third redundant bits. The second bit string may include only the information bits of the transmission data, may include the information bits and the first redundant bits, or may include only the first redundant bits. The encoding unit 100-B sets the redundancy of the third encoding to a predetermined number (the predetermined number is a real number larger than 0, for example, 2) with respect to the redundancy of the second encoding by the encoding unit 100-A. Double it.

In this way, the transmitted data is encoded. Next, the symbol mapping device 11 in the transmission signal processing device 1 maps the transmission data encoded by the encoding device 10 to symbols (signal points) on the complex plane according to a predetermined mapping rule. Executes multilevel modulation of data.

Specifically, the symbol mapping device 11 sequentially extracts, for example, two bits at a time from a bit string consisting of the first bit string and the second redundant bits included in the encoded transmission data, and , to the upper bits (for example, the first and second bits) of the plurality of bits corresponding to the symbol. At the same time, the symbol mapping device 11 sequentially extracts, for example, two bits at a time from a bit string consisting of the second bit string and the third redundant bits included in the encoded transmission data, and converts the extracted two bits into a symbol. It is assigned to the lower bits (for example, the 3rd and 4th bits) of the corresponding plurality of bits.

For example, when the multilevel modulation method is 16QAM, the upper 2 bits of the 4 bits corresponding to the symbol are used as the I-axis value of the X-polarized wave and the Q-axis value of the X-polarized wave. The lower two bits of the four bits corresponding to the symbol are mapped as information in a bit string representing the position of the quadrant, and the lower two bits of the four bits corresponding to the symbol are mapped to the I axis of the bit string representing the position among the four symbols in each quadrant of the IQ plane. It is mapped as information on the value and Q-axis value. As a result, a total of 4 bits of data, XI (2 bits) and XQ (2 bits), is output as data for the X-polarized optical signal. In addition, data for Y-polarized optical signals is similarly mapped on the IQ plane using the 16QAM multi-level modulation method, resulting in a total of 4 bits of YI (2 bits) and YQ (2 bits). Output data.
In the following, an example of mapping and demapping of data for an optical signal of X polarization (horizontal polarization) will be explained, but the case of data for an optical signal of Y polarization (vertical polarization) will also be explained. Examples of implementation can be considered as well.
As described above, the optical transmission module 3 generates an optical signal based on the data output from the symbol mapping device 11.

FIG. 3 is a block diagram showing the configuration of the error correction device 20 in the received signal processing device 2 according to this embodiment. The error correction device 20 includes an error correction decoding section 200-A (first error correction decoding section), an error correction decoding section 200-B (second error correction decoding section), and an error correction decoding section 201 (third error correction decoding section). error correction decoding unit).

As described above, the optical receiving module 4 generates received data XI, XQ, YI, and YQ from the received optical signals.
The symbol demapping device 21 in the received signal processing device 2 determines symbol positions on the complex plane from the set of received data XI, By converting it into a bit string, symbol demapping processing is performed to demodulate a bit string including information bits and first, second, and third redundant bits.

Next, the error correction decoding unit 200-A performs error correction on the first bit string of the output of the symbol demapping device 21 based on the second redundant bit added to the first bit string, and performs error correction. The subsequent first bit string is output.

The error correction decoding unit 200-B performs error correction on the second bit string of the output of the symbol demapping device 21 based on the third redundant bit added to the second bit string, and Outputs 2 bit strings.

The error correction decoding section 201 corrects the error of the information bits included in the first bit string whose error was corrected by the error correction decoding section 200-A, and corrects the error of the information bit contained in the first bit string whose error was corrected by the error correction decoding section 200-B. Error correction of the information bits included in the bit string is performed based on the first redundant bits added to these information bits. The first redundant bit may be added to both the information bits contained in the first bit string and the information bit contained in the second bit string, or it may be added only to the information bit contained in the second bit string. Sometimes there are. In this way, the received data can be decoded.

In this embodiment, the redundancy of the third encoding by the encoding unit 100-B is multiplied by a predetermined number with respect to the redundancy of the second encoding by the encoding unit 100-A. The error correction ability for the second bit string assigned to the lower bits among the plurality of bits can be improved.

Furthermore, in this embodiment, the information bits of the transmission data are divided into a first bit string assigned to the upper bits of a plurality of bits corresponding to a symbol, and a second bit string assigned to the lower bits. Since errors can be dispersed by performing different encoding and decoding processes, burst error correction capability can be improved without adding another process such as interleaving.

As in this embodiment, when dividing the information bits of the transmission data into a first bit string and a second bit string and shortening the code length of the second bit string, there is a possibility that the error correction ability will decrease. By performing common error correction decoding processing on the first bit string and the second bit string by the error correction decoding section 201 at the subsequent stage, error correction efficiency can be improved.

Furthermore, in this embodiment, by making the sum of the number of output bits of the error correction decoding section 200-A and the number of output bits of the error correction decoding section 200-B equal to the number of input bits of the error correction decoding section 201, Since distribution processing of the 1 bit string and the second bit string is not necessary, the amount of processing can be reduced, and it is possible to realize faster error correction processing, lower delay, and lower power consumption.

[Second example]
Next, a second embodiment of the present invention will be described. This example is a specific example of the first example. Since the configuration of the communication system in this embodiment is the same as that in the first embodiment, it will be explained using the reference numerals in FIG. FIG. 4 shows the configurations of the bit string encoded by the encoding device in the transmitted signal processing device 1 and the bit string demodulated by the symbol demapping device in the received signal processing device 2.

In the example of FIG. 4, D1 is the information bit included in the first bit string that is assigned to the higher order bits among the plurality of bits corresponding to the symbol, and the information bit included in the first bit string is assigned to the lower order bit among the plurality of bits corresponding to the symbol. The information bits included in the bit string are D2-1 and D2-2, the first redundant bit is R1, the second redundant bit is R2, and the third redundant bit is R3-1 and R3-2.

In this embodiment, the block of information bits D1 has a length of 120 bits in the column direction (horizontal direction in FIG. 4) and M rows. The number of rows M is an integer of 1 or more. Furthermore, the configuration of the block of information bits D2-1 is 56 bits long in the column direction and M rows, and the block of information bits D2-2 is 48 bits long in the column direction and M rows. It is said that The length of each redundant bit R1, R2, R3-1, R3-2 is 8 bits.

FIG. 5 is a block diagram showing the configuration of the encoding device 10 in the transmission signal processing device 1 according to this embodiment. The encoding device 10 includes an encoding section 100a-A (second encoding section), an encoding section 100a-B (third encoding section), and an encoding section 101a (first encoding section). It consists of

The encoding unit 101a generates a redundant bit R1 of 8 bits in length from the information bits D1, D2-1, D2-2 of 224 bits in length×1 row, and converts the information bits D1, D2-1, D2-2 into information bits D1, D2-1, D2-2. and redundant bit R1. The encoding unit 101a performs such encoding processing and outputs the processing results for each row of information bits D1, D2-1, and D2-2 shown in FIG. The code length in the encoding unit 101a is (length of D1, D2-1, D2-2+length of R1)=224+8=232 bits.

Next, the encoding unit 100a-A generates redundant bits R2 of 8 bits in length from the information bits D1 of 120 bits in length×1 row out of the output of the encoding unit 101a, and combines the information bits D1 and the redundant bits. R2 is output. The encoding unit 100a-A performs such encoding processing and outputs the processing result for each row of information bits D1 shown in FIG. 4.

On the other hand, the encoding unit 100a-B generates redundant bits R3-1 of 8 bits in length from the information bits D2-1 of 56 bits in length×1 row out of the output of the encoding unit 101a, and generates redundant bits R3-1 in length of 48 bits. A redundant bit R3-2 with a length of 8 bits is generated from the information bit D2-2 of x 1 row and the redundant bit R1 of 8 bits long x 1 row, and the information bit D2-1 and the redundant bit R3-1 are Information bit D2-2 and redundant bits R1 and R3-2 are output. The encoding units 100a-B perform such encoding processing and output the processing results for each row of information bits D2-1, D2-2 and redundant bit R1 shown in FIG.

The code length in encoding section 100a-A is (length of D1+length of R2)=120+8=128 bits. The code length in the encoding section 100a-B is (length of D2-1 + length of R3-1) = (length of D2-2 + length of R1 + length of R3-2) = 56 + 8 = 64 bits. The code length is 1/2 of the code length in the encoding unit 100a-A.

Further, the redundancy of the redundant bit R2 is (length of R2)/(length of D1+length of R2)=8/128. The redundancy of redundant bits R3-1 and R3-2 is (length of R3-1)/(length of D2-1+length of R3-1)=(length of R3-2)/(D2- 2+length of R1+length of R3-2)=8/64, which is twice the redundancy of redundant bit R2.

Next, the symbol mapping device 11a in the transmission signal processing device 1 performs multilevel modulation of the transmission data encoded by the encoding device 10. Specifically, the symbol mapping device 11a sequentially extracts, for example, two bits at a time from a bit string consisting of D1 and R2 included in the encoded transmission data, and uses the extracted two bits as one of the bits corresponding to the symbol. Allocate to the upper bits (for example, the 1st and 2nd bits). At the same time, the symbol mapping device 11a sequentially extracts, for example, 2 bits at a time from a bit string consisting of D2-1, R3-1, D2-2, R1, and R3-2 included in the encoded transmission data, and extracts the extracted 2 bits. are assigned to the lower bits (for example, the third and fourth bits) of the plurality of bits corresponding to the symbol.

For example, when the multilevel modulation method is 16QAM, the upper two bits of the four bits corresponding to the symbol are used as the I-axis value and Q-axis value of the X polarization to create a bit string that represents the position of each quadrant on the IQ plane. The lower two bits of the four bits corresponding to the symbol are mapped as information, and the I-axis value and Q of the bit string representing the position among the four symbols in each quadrant of the IQ plane of the X polarization are mapped. Map as axis value information. As a result, the symbol mapping device 11a outputs XI and XQ data, and similarly outputs YI and YQ data for the Y polarization.

FIG. 6 shows an example of symbol arrangement when the multilevel modulation method is 16QAM. In the example of FIG. 6, of the four bits corresponding to the symbol, the first bit from the higher order is d4, the second bit is d3, the third bit is d2, and the fourth bit is d1.

FIG. 7 is a diagram showing an example of symbol mapping when the multilevel modulation method is 16QAM. When bits d4="0" and d3="0", the symbol selected by the symbol mapping device 11a is one of the four points in the first quadrant 31 of FIG. If d4="1" and d3="0", the symbol will be any of the four points in the second quadrant 32. If d4="1" and d3="1", the symbol will be any of the four points in the third quadrant 33. When d4="0" and d3="1", the symbol is one of the four points in the fourth quadrant 34. Further, depending on the values of bits d2 and d1, one of the four points within the quadrant is selected as the symbol corresponding to d4, d3, d2, and d1.

FIG. 8 is a block diagram showing the configuration of the error correction device 20 in the received signal processing device 2 according to this embodiment. The error correction device 20 includes an error correction decoding section 200a-A (first error correction decoding section), an error correction decoding section 200a-B (second error correction decoding section), and an error correction decoding section 201a (third error correction decoding section). error correction decoding unit).

The symbol demapping device 21a in the received signal processing device 2 calculates the symbol position on the complex plane from the received data XI, The bit string having the configuration shown in 4 is demodulated.

Next, the error correction decoding unit 200a-A performs error correction on the information bit D1 having a length of 120 bits out of the output of the symbol demapping device 21a based on the redundant bit R2 added to D1, and after the error correction The information bit D1 is output. The error correction decoding unit 200a-A performs such error correction decoding processing and outputs the processing result for each row of information bits D1 shown in FIG. 4.

The error correction decoding unit 200a-B performs error correction on the 56-bit information bit D2-1 of the output of the symbol demapping device 21a based on the redundant bit R3-1 added to D2-1, Furthermore, error correction is performed on the information bit D2-2 having a length of 48 bits and the redundant bit R1 having a length 8 bits based on the redundant bit R3-2 added to D2-2 and R1. D2-1, D2-2 and redundant bit R1 are output. The error correction decoding units 200a-B perform such error correction decoding processing and output the processing results for each row of information bits D2-1, D2-2 and redundant bit R1 shown in FIG.

The error correction decoding unit 201a performs error correction on the information bit D1 output from the error correction decoding unit 200a-A and the information bits D2-1 and D2-2 output from the error correction decoding unit 200a-B. -1 and D2-2, and outputs error-corrected information bits D1, D2-1, and D2-2. The error correction decoding unit 201a performs such error correction decoding processing and outputs the processing results for each row of information bits D1, D2-1, and D2-2 shown in FIG. In this way, the received data can be decoded.

In the case of 16QAM, if the deviation of the received signal coordinates from the transmitted signal coordinates of each symbol follows a normal distribution, the ratio of the error rate of the upper bits to the lower bits of the 4 bits corresponding to the symbol is 1:2. becomes. Therefore, by bringing the ratio of the redundancy of redundant bits R3-1 and R3-2 to the redundancy of redundant bit R2 close to 2:1, the error rate of the upper bit of the 4 bits corresponding to a symbol and the lower side Error correction can be performed so that the bit error rate becomes approximately the same.

In this embodiment, the number of output bits of the error correction decoding section 200a-A (the length of the information bit D1 is 120 bits) and the number of output bits of the error correction decoding section 200a-B (the length of the information bits D2-1 and D2-2) The total length (104 bits of length + 8 bits of length of redundant bit R1) matches the number of input bits of error correction decoding section 201a, 232 bits. In this way, in this embodiment, the effects described in the first embodiment can be obtained.

[Third example]
Next, a third embodiment of the present invention will be described. This example is another specific example of the first example. Since the configuration of the communication system in this embodiment is the same as that in the first embodiment, it will be explained using the reference numerals in FIG. FIG. 9 shows the structure of the bit string encoded by the encoding device in the transmitted signal processing device 1 and the bit string demodulated by the symbol demapping device in the received signal processing device 2.

Similarly to FIG. 4, D1 is the information bit included in the first bit string that is assigned to the upper bit of the plurality of bits corresponding to the symbol, and the second information bit is assigned to the lower bit of the plurality of bits corresponding to the symbol. Assume that the information bits included in the bit string are D2-1 and D2-2, the second redundant bit is R2, and the third redundant bit is R3-1 and R3-2. Further, the first redundant bit added to the information bit D1 is R1-1, and the first redundant bits added to the information bits D2-1 and D2-2 are R1-2 and R1-3.

In this embodiment, the block of information bits D1 has a length of 120 bits in the column direction (horizontal direction in FIG. 9) and M rows. The number of rows M is an integer of 1 or more. Furthermore, the blocks of information bits D2-1 and D2-2 each have a length of 56 bits in the column direction and M rows. The length of redundant bits R1-1, R1-2, and R1-3 is assumed to be R bits (for example, 8 bits). The length of redundant bits R2, R3-1, and R3-2 is 8 bits each.

FIG. 10 is a block diagram showing the configuration of the encoding device 10 in the transmission signal processing device 1 according to this embodiment. The encoding device 10 includes an encoding section 100b-A (second encoding section), an encoding section 100b-B (third encoding section), and an encoding section 101b (first encoding section). It consists of

The encoding unit 101b generates redundant bits R1-1, R1-2, R1-3 of length R bits from each of the information bits D1, D2-1, D2-2 of length 1 bit×M rows. , information bits D1, D2-1, D2-2 and redundant bits R1-1, R1-2, R1-3. The encoding unit 101b performs such encoding processing for each column of information bits D1, D2-1, and D2-2 shown in FIG. 9, and outputs the processing results for each row. At this time, the encoding unit 101b generates redundant bits R1-1, R1-2, R1-3 generated for each column of information bits D1, D2-1, D2-2 along the row direction, as shown in FIG. The bit string is output in an output format such that it is arranged as follows. The length of the bit string output by the encoding unit 101b is (length of D1, D2-1, D2-2)=120+56×2=232 bits.

Next, the encoding unit 100b-A generates redundant bits R2 with a length of 8 bits from the information bits D1 with a length of 120 bits×1 row outputted from the encoding unit 101b, and combines the information bits D1 and the redundant bits. R2 is output. Further, the encoding unit 100b-A calculates the length from the bit string of the i-th bit (i is an integer from 1 to R)×120 columns of the 120 columns of redundant bits R1-1 added to the information bit D1. An 8-bit redundant bit R2 is generated, and a bit string of 120 columns of the i-th bit of the redundant bit R1-1 and the redundant bit R2 are output. The encoding unit 100b-A performs such encoding processing and outputs the processing results for each row of information bits D1 and for each redundant bit R1-1 shown in FIG.

On the other hand, the encoding unit 100b-B converts the information bits D2-1 and D2-2 of length 56 bits x 1 row output from the encoding unit 101b into redundant bits R3-1 and R3-2 of length 8 bits, respectively. Generate 2. Encoding section 100b-B outputs information bit D2-1, redundant bit R3-1, information bit D2-2, and redundant bit R3-2.

The encoding unit 100b-B also generates an 8-bit redundant bit R3-B from the i-th bit x 56 columns of redundant bits R1-2 added to the information bit D2-1. 1, and of the 56 columns of redundant bits R1-3 added to the information bit D2-2, a redundant bit R3-2 of length 8 bits is generated from the i-th bit x 56 columns of bit strings. The encoding unit 100b-B encodes a bit string of the i-th bit x 56 columns of the redundant bits R1-2, a bit string of the i-th bit x 56 columns of the redundant bit R1-2, a redundant bit R3-1, a bit string of the i-th bit x 56 columns of the redundant bit R1-3, and Bits R3-2 are output. The encoding unit 100b-B performs the above encoding process and outputs the processing results for each row of information bits D2-1 and D2-2 and redundant bits R1-2 and R1-3 shown in FIG. Do this bit by bit.

The code length in encoding section 100b-A is (length of D1+length of R2)=120+8=128 bits. The code length in the encoding unit 100b-B is (length of D2-1 + length of R3-1) = (length of D2-2 + length of R3-2) = 56 + 8 = 64 bits. This is 1/2 of the code length in section 100b-A.

Further, the redundancy of the redundant bit R2 is (length of R2)/(length of D1+length of R2)=8/128. The redundancy of redundant bits R3-1 and R3-2 is (length of R3-1)/(length of D2-1+length of R3-1)=(length of R3-2)/(D2- 2 length+R3-2 length)=8/64, which is twice the redundancy of redundant bit R2.

Next, the symbol mapping device 11b in the transmission signal processing device 1 performs multilevel modulation of the transmission data encoded by the encoding device 10. Specifically, the symbol mapping device 11b sequentially extracts, for example, two bits at a time from a bit string consisting of D1 and R2 included in the encoded transmission data, and uses the extracted two bits as one of the bits corresponding to the symbol. Allocate to the upper bits (for example, the 1st and 2nd bits). At the same time, the symbol mapping device 11b sequentially extracts, for example, two bits at a time from the bit string consisting of D2-1, R3-1, D2-2, and R3-2 included in the encoded transmission data, and the extracted two bits are It is assigned to the lower bits (for example, the third and fourth bits) among the plurality of bits corresponding to the symbol.

Further, the symbol mapping device 11b sequentially extracts, for example, two bits at a time from the redundant bits R1-1 and redundant bits R2 for 120 columns, and assigns the extracted two bits to the upper bits of the plurality of bits corresponding to the symbol. assign. At the same time, the symbol mapping device 11b sequentially extracts, for example, 2 bits at a time from the redundant bits R1-2 and redundant bits R3-1 for 56 columns and the redundant bits R1-3 and redundant bits R3-2 for 56 columns. The two bits thus obtained are assigned to the lower bits among the plurality of bits corresponding to the symbol.

FIG. 11 is a block diagram showing the configuration of the error correction device 20 in the received signal processing device 2 according to this embodiment. The error correction device 20 includes an error correction decoding section 200b-A (first error correction decoding section), an error correction decoding section 200b-B (second error correction decoding section), and an error correction decoding section 201b (third error correction decoding section). error correction decoding unit).

The symbol demapping device 21b in the received signal processing device 2 determines the symbol position on the complex plane from the received data XI, 9 is demodulated.

Next, the error correction decoding unit 200b-A performs error correction on the information bit D1 having a length of 120 bits out of the output of the symbol demapping device 21b based on the redundant bit R2 added to D1, and after the error correction The information bit D1 is output. In addition, the error correction decoding unit 200b-A detects an error in the bit string of the i-th bit (i is an integer from 1 to R)×120 columns among the 120 columns of redundant bits R1-1 added to the information bit D1. Correction is performed based on the redundant bit R2 added to this bit string, and a bit string of error-corrected i-th bit×120 columns is output. The error correction decoding unit 200b-A performs such error correction decoding processing and outputs the processing results for each row of information bits D1 and for each redundant bit R1-1 shown in FIG.

The error correction decoding unit 200b-B performs error correction on the information bits D2-1 and D2-2, each having a length of 56 bits, out of the output from the symbol demapping device 21b. This is performed based on bits R3-1 and R3-2, and error-corrected information bits D2-1 and D2-2 are output.

Furthermore, the error correction decoding unit 200b-B adds error correction for the i-th bit×56 columns of bit strings to this bit string among the 56 columns of redundant bits R1-2 added to the information bit D2-1. The error-corrected bit string of the i-th bit×56 columns is output. Furthermore, the error correction decoding unit 200b-B adds error correction of the i-th bit×56 columns of bit strings to this bit string among the 56 columns of redundant bits R1-3 added to the information bits D2-2. The error-corrected bit string of the i-th bit×56 columns is output. The error correction decoding unit 200b-B performs the above-described error correction decoding process and outputs the processing results for each row of information bits D2-1 and D2-2 and redundant bits R1-2 and R1- shown in FIG. Perform every 3 bits.

The error correction decoding unit 201b performs error correction on the information bits D1 having a length of 1 bit×M rows outputted from the error correction decoding unit 200b-A, using redundant bits R1- in the row direction added to this one column of D1. 1 and outputs the error-corrected information bit D1. In addition, the error correction decoding unit 201b performs error correction on the information bits D2-1 and D2-2 of 1 bit in length×M rows output from the error correction decoding unit 200b-B, respectively. This is performed based on the redundant bits R1-2 and R1-3 in the row direction added to D2-2, and error-corrected information bits D2-1 and D2-2 are output. The error correction decoding unit 201b performs such error correction decoding processing for each column of information bits D1, D2-1, and D2-2 shown in FIG. 9, and outputs the processing results for each row. In this way, the received data can be decoded.

In this embodiment, the number of output bits of the error correction decoding section 200b-A (the length of the information bit D1 is 120 bits) and the number of output bits of the error correction decoding section 200b-B (the length of the information bits D2-1 and D2-2) are compared. The total number of input bits (112 bits) matches the number of input bits of the error correction decoding section 201b, 232 bits. In this way, in this embodiment, the effects described in the first embodiment can be obtained.

In addition, in the second embodiment, a redundant bit R1 is added to the information bits D1, D2-1, D2-2 in the column direction, and the redundant bit R1 is added to the information bits D1, D2-1, D2-2 and the redundant bit R1. On the other hand, redundant bits R2, R3-1, and R3-2 were added in the column direction.

On the other hand, in this embodiment, redundant bits R1-1, R1-2, R1-3 are added to the information bits D1, D2-1, D2-2 in the row direction, and the information bits D1, D2 -1, D2-2 and redundant bits R1-1, R1-2, R1-3, redundant bits R2, R3-1, R3-2 are added in the column direction. In this embodiment, by making the arrangement direction of redundant bits R1-1, R1-2, R1-3 orthogonal to the arrangement direction of redundant bits R2, R3-1, R3-2, redundant bits R1-1, R1- Since the error that overlaps between 2 and R1-3 and the redundant bits R2, R3-1, and R3-2 is one bit at most, the error correction ability can be further improved compared to the second embodiment.

In the second and third embodiments, the case where the multilevel modulation method is 16QAM is described, but the second and third embodiments may be applied to, for example, 64QAM. FIG. 12 shows an example of symbol arrangement when the multilevel modulation method is 64QAM. In the example of FIG. 12, the first bit from the higher order of the six bits corresponding to the symbol is d6, the second bit is d5, the third bit is d4, the fourth bit is d3, the fifth bit is d2, and the sixth bit is is set as d1.

[Fourth example]
Next, a fourth embodiment of the present invention will be described. This example is another specific example of the first example. Since the configuration of the communication system in this embodiment is the same as that in the first embodiment, it will be explained using the reference numerals in FIG. FIG. 13 shows the configurations of the bit string encoded by the encoding device in the transmitted signal processing device 1 and the bit string demodulated by the symbol demapping device in the received signal processing device 2.

In the second and third embodiments, the first bit string (D1 in the second embodiment and D1 in the third embodiment) is assigned to the upper bits of a plurality of bits corresponding to a multilevel modulation symbol. The second bit string (D2 in the second embodiment) assigned to the lower bits of the plurality of bits corresponding to the symbol, with respect to the redundancy of the second redundant bit R2 added to -1, D2-2, R1, and in the third embodiment, the redundancy of the third redundant bit R3 added to D2-1 and R1 added to it, and D2-2 and R1 added to it. It was doubled.

In contrast, in this embodiment, the second bit string is further divided. Specifically, among a plurality of bits corresponding to a symbol, the symbol is divided into a bit string (third bit string) allocated to the middle bits and a bit string (fourth bit string) allocated to the lower bits.

In the example of FIG. 13, D1 is the information bit included in the first bit string that is allocated to the upper bits among the plurality of bits corresponding to the symbol, and the third information bit is allocated to the middle bit among the plurality of bits corresponding to the symbol. The information bits included in the bit string are D3-1, D3-2, and the information bits included in the fourth bit string assigned to the lower bits among the plurality of bits corresponding to the symbol are D4-1, D4-2, D4. -3, D4-4. In addition, R1 is the first redundant bit, R2 is the second redundant bit added to the information bit D1, and R4-1, R4- is the third redundant bit added to the information bit D3-1, D3-2. 2. Let R5-1, R5-2, R5-3, and R5-4 be the third redundant bits added to the information bits D4-1, D4-2, D4-3, and D4-4. However, in the case of this embodiment, redundancy bit R5-4 is added to information bit D4-4 and redundancy bit R1.

In this embodiment, the block of information bits D1 has a length of 120 bits in the column direction (horizontal direction in FIG. 13) and M rows. The number of rows M is an integer of 1 or more. The blocks of information bits D3-1 and D3-2 each have a length of 56 bits in the column direction and M rows. Furthermore, the configuration of the blocks of information bits D4-1 to D4-3 is each 24 bits long in the column direction and M rows, and the block configuration of the information bits D4-4 is 16 bits long in the column direction. , M rows. The length of each redundant bit R1, R2, R4-1, R4-2, R5-1 to R5-4 is 8 bits.

FIG. 14 is a block diagram showing the configuration of the encoding device 10 in the transmission signal processing device 1 according to this embodiment. The encoding device 10 includes an encoding section 100c-A (second encoding section), an encoding section 100c-B (fourth encoding section), and an encoding section 100c-C (fifth encoding section). section) and an encoding section 101c (first encoding section).

The encoding unit 101c generates redundant bits R1 with a length of 8 bits from the information bits D1, D3-1, D3-2, D4-1 to D4-4 of a length of 320 bits x 1 row, and , D3-1, D3-2, D4-1 to D4-4 and redundant bit R1. The encoding unit 101c performs such encoding processing and outputs the processing results for each row of information bits D1, D3-1, D3-2, D4-1 to D4-4 shown in FIG. The code length in the encoding unit 101c is (length of D1, D3-1, D3-2, D4-1 to D4-4+length of R1)=320+8=328 bits.

Next, the encoding unit 100c-A generates redundant bits R2 of 8 bits in length from the information bits D1 of 120 bits in length×1 row out of the output of the encoding unit 101c, and combines the information bits D1 and the redundant bits. R2 is output. The encoding unit 100c-A performs such encoding processing and outputs the processing result for each row of information bits D1 shown in FIG. 13.

On the other hand, the encoding unit 100c-B converts the information bits D3-1 and D3-2 of 56 bits in length×1 row out of the output of the encoding unit 101c into redundant bits R4-1 and R4-2 of 8 bits in length, respectively. 2, and outputs information bit D3-1, redundant bit R4-1, information bit D3-2, and redundant bit R4-2. The encoding unit 100c-B performs such encoding processing and outputs the processing results for each row of information bits D3-1 and D3-2 shown in FIG. 13.

The encoding unit 100c-C converts the output from the encoding unit 101c into redundant bits R5-1, 8 bits long from the information bits D4-1, D4-2, D4-3 of 24 bits long×1 row, respectively. R5-2 and R5-3 are generated, and a redundant bit R5-4 of length 8 bits is generated from information bit D4-4 of length 16 bits × 1 row and redundant bit R1 of length 8 bits × 1 row. information bit D4-1, redundant bit R5-1, information bit D4-2, redundant bit R5-2, information bit D4-3, redundant bit R5-3, information bit D4-4, redundant bit R1, R5- Outputs 4. The encoding unit 100c-C performs such encoding processing and outputs the processing results for each row of information bits D4-1 to D4-4 and redundant bit R1 shown in FIG.

The code length in the encoding unit 100c-A is (length of D1+length of R2)=120+8=128 bits. The code length in the encoding unit 100c-B is (length of D3-1 + length of R4-1) = (length of D3-2 + length of R4-2) = 56 + 8 = 64 bits. This is 1/2 of the code length in section 100c-A. The code length in the encoding unit 100c-C is (length of D4-1 + length of R5-1) = (length of D4-2 + length of R5-2) = (length of D4-3 + length of R5- 3) = (length of D4-4 + length of R1 + length of R5-4) = 24 + 8 = 32 bits, which is 1/2 of the code length in encoding unit 100c-B (length of encoding unit 100c -1/4 of the code length in A).

Further, the redundancy of the redundant bit R2 is (length of R2)/(length of D1+length of R2)=8/128. The redundancy of redundant bits R4-1 and R4-2 is (length of R4-1)/(length of D3-1+length of R4-1)=(length of R4-2)/(length of D3- 2 length+R4-2 length)=8/64, which is twice the redundancy of redundant bit R2. The redundancy of redundant bits R5-1, R5-2, R5-3, and R5-4 is (length of R5-1)/(length of D4-1+length of R5-1)=(R5-2 length) / (Length of D4-2 + Length of R5-2) = (Length of R5-3) / (Length of D4-3 + Length of R5-3) = (Length of R5-4 )/(length of D4-4 + length of R1 + length of R5-4) = 8/32, which is twice the redundancy of redundant bits R4-1 and R4-2 (redundancy of redundant bit R2) 4 times).

Next, the symbol mapping device 11c in the transmission signal processing device 1 performs multilevel modulation of the transmission data encoded by the encoding device 10. Specifically, the symbol mapping device 11c sequentially extracts, for example, two bits at a time from a bit string consisting of information bits D1 and redundant bits R2 included in the encoded transmission data, and maps the extracted two bits to symbols. It is assigned to the upper bits (for example, the first and second bits) of the plurality of bits. Further, the symbol mapping device 11c sequentially selects, for example, 2 bits at a time from a bit string consisting of information bit D3-1, redundant bit R4-1, information bit D3-2, and redundant bit R4-2 included in the encoded transmission data. The extracted two bits are assigned to intermediate bits (for example, the third and fourth bits) among the plurality of bits corresponding to the symbol.

Further, the symbol mapping device 11c includes information bits D4-1, redundant bits R5-1, information bits D4-2, redundant bits R5-2, information bits D4-3, and redundant bits R5 included in the encoded transmission data. -3, information bit D4-4, and redundant bits R1 and R5-4, for example, 2 bits at a time are extracted sequentially, and the extracted 2 bits are added to the lower bits (for example, 5 bits) of the plurality of bits corresponding to the symbol. bit and 6th bit).

An example of symbol arrangement when the multilevel modulation method is 64QAM is as shown in FIG. FIG. 15 is a diagram showing an example of symbol mapping when the multilevel modulation method is 64QAM. When bits d6="0" and d5="0", the symbol selected by the symbol mapping device 11c is one of the 16 points in the first quadrant 31 of FIG. When d6="1" and d5="0", the symbol is any one of the 16 points in the second quadrant 32. When d6="1" and d5="1", the symbol is any of the 16 points in the third quadrant 33. When d6="0" and d5="1", the symbol is any one of the 16 points in the fourth quadrant 34.

Further, when bits d4="0" and d3="0", the symbol selected by the symbol mapping device 11c is one of four points within the quadrant frame 41 determined by bits d6 and d5. When d4="1" and d3="0", the symbol is one of four points within the quadrant frame 42 determined by bits d6 and d5. When d4="1" and d3="1", the symbol is one of four points within the quadrant frame 43 determined by bits d6 and d5. When d4="0" and d3="1", the symbol is one of four points within the quadrant frame 44 determined by bits d6 and d5. Further, depending on the values of bits d2 and d1, one of the four points within frames 41 to 44 is selected as the symbol corresponding to d6, d5, d4, d3, d2, and d1.

FIG. 16 is a block diagram showing the configuration of the error correction device 20 in the received signal processing device 2 according to this embodiment. The error correction device 20 includes an error correction decoding section 200c-A (first error correction decoding section), an error correction decoding section 200c-B (fourth error correction decoding section), and an error correction decoding section 200c-C ( and an error correction decoding unit 201c (third error correction decoding unit).

The symbol demapping device 21c in the received signal processing device 2 determines the symbol position on the complex plane from the received data XI, 13 is demodulated.

Next, the error correction decoding unit 200c-A performs error correction on the information bit D1 having a length of 120 bits out of the output of the symbol demapping device 21c based on the redundant bit R2 added to D1, and after the error correction The information bit D1 is output. The error correction decoding unit 200c-A performs such error correction decoding processing and outputs the processing result for each row of information bits D1 shown in FIG. 13.

The error correction decoding unit 200c-B performs error correction on the information bits D3-1 and D3-2, each having a length of 56 bits, out of the output from the symbol demapping device 21c. This is performed based on bits R4-1 and R4-2, and error-corrected information bits D3-1 and D3-2 are output. The error correction decoding unit 200c-B performs such error correction decoding processing and outputs the processing results for each row of information bits D3-1 and D3-2 shown in FIG.

The error correction decoding unit 200c-C performs error correction on the information bits D4-1, D4-2, and D4-3 having a length of 24 bits out of the output from the symbol demapping device 21c, into D4-1, D4-2, and D4-3, respectively. Based on the redundant bits R5-1, R5-2, and R5-3 added to D4-3, error correction is performed on the 16-bit information bit D4-4 and the 8-bit redundant bit R1, This is performed based on the redundant bit R5-4 added to D4-4 and R1, and the error-corrected information bits D4-1 to D4-4 and redundant bit R1 are output. The error correction decoding unit 200c-C performs such error correction decoding processing and outputs the processing results for each row of information bits D4-1 to D4-4 and redundant bit R1 shown in FIG.

The error correction decoding unit 201c receives the information bit D1 output from the error correction decoding unit 200c-A, the information bits D3-1 and D3-2 output from the error correction decoding unit 200c-B, and the error correction decoding unit 200c-C. Error correction of the information bits D4-1 to D4-4 outputted from the The information bits D1, D3-1, D3-2, D4-1 to D4-4 are output. The error correction decoding unit 201c performs such error correction decoding processing and outputs the processing results for each row of information bits D1, D3-1, D3-2, D4-1 to D4-4 shown in FIG. In this way, the received data can be decoded.

In the case of 64QAM, if the deviation of the received signal coordinates from the transmitted signal coordinates of each symbol follows a normal distribution, the error rate of the upper bits (upper 2 bits) of the 6 bits corresponding to the symbol and the middle bits (middle 2 bits) The ratio of the error rate of bits) to the error rate of lower bits (lower two bits) is 1:2:4. Therefore, the ratio of the redundancy of redundant bits R5-1, 5-2, 5-3, 5-4, the redundancy of redundant bits R4-1, R4-2, and the redundancy of redundant bit R2 is 4:2: By making it close to 1, error correction can be performed so that the error rate of the upper 2 bits of the 6 bits corresponding to the symbol, the error rate of the middle 2 bits, and the error rate of the lower 2 bits are approximately the same. .

In this embodiment, the number of output bits of the error correction decoding section 200c-A (the length of the information bit D1 is 120 bits) and the number of output bits of the error correction decoding section 200c-B (the length of the information bits D3-1 and D3-2) are compared. 112 bits) and the number of output bits of the error correction decoding unit 200c-C (88 bits long for information bits D4-1 to D4-4 + 8 bits long for redundant bit R1). This matches the input bit number of 328 bits. In this way, in this embodiment, the effects described in the first embodiment can be obtained.

[Fifth example]
Next, a fifth embodiment of the present invention will be described. This example is another specific example of the first example. Since the configuration of the communication system in this embodiment is the same as that in the first embodiment, it will be explained using the reference numerals in FIG. FIG. 17 shows the structure of the bit string encoded by the encoding device in the transmitted signal processing device 1 and the bit string demodulated by the symbol demapping device in the received signal processing device 2.

Similarly to FIG. 13, D1 is the information bit included in the first bit string that is assigned to the upper bit of the plurality of bits corresponding to the symbol, and the third information bit is assigned to the middle bit of the plurality of bits corresponding to the symbol. The information bits included in the bit string are D3-1 and D3-2, and the information bits included in the fourth bit string assigned to the lower bits among the plurality of bits corresponding to the symbol are D4-1 to D4-4. . The first redundant bit added to the information bit D1 is R1-1, the first redundant bit added to the information bits D3-1 and D3-2 is R1-2, R1-3, the information bit D4-1, The first redundant bits added to D4-2, D4-3, and D4-4 are assumed to be R1-4, R1-5, R1-6, and R1-7. Further, the second redundant bit added to the information bit D1 is R2, the third redundant bit added to the information bits D3-1 and D3-2 is R4-1, R4-2, the information bit D4-1, The third redundant bits added to D4-2, D4-3, and D4-4 are assumed to be R5-1, R5-2, R5-3, and R5-4.

In this embodiment, the block of information bits D1 has a length of 120 bits in the column direction (horizontal direction in FIG. 17) and M rows. The number of rows M is an integer of 1 or more. In addition, the configuration of the blocks of information bits D3-1 and D3-2 is each 56 bits long in the column direction and M rows, and the configuration of the blocks of information bits D4-1 to D4-4 is each configured in the column direction. It has a length of 24 bits and a configuration of M lines. The length of redundant bits R1-1 to R1-7 is assumed to be R bits (for example, 8 bits). The length of each redundant bit R2, R4-1, R4-2, R5-1 to R5-4 is 8 bits.

FIG. 18 is a block diagram showing the configuration of the encoding device 10 in the transmission signal processing device 1 according to this embodiment. The encoding device 10 includes an encoding section 100d-A (second encoding section), an encoding section 100d-B (fourth encoding section), and an encoding section 100d-C (fifth encoding section). 1) and an encoding section 101d (first encoding section).

The encoding unit 101d generates redundant data of length R bits from each of the information bits D1, D3-1, D3-2, D4-1, D4-2, D4-3, and D4-4 of length 1 bit×M rows. Generate bits R1-1, R1-2, R1-3, R1-4, R1-5, R1-6, R1-7, and information bits D1, D3-1, D3-2, D4-1 to D4 -4 and redundant bits R1-1 to R1-7. The encoding unit 101d performs such encoding processing for each column of information bits D1, D3-1, D3-2, D4-1 to D4-4 shown in FIG. 17, and outputs the processing results for each row. do. At this time, the encoding unit 101d generates redundant bits R1 to R7 generated for each column of information bits D1, D3-1, D3-2, D4-1 to D4-4 along the row direction, as shown in FIG. The bit string is output in an output format such that it is arranged as follows. The length of the bit string output by the encoding unit 101d is (length of D1, D3-1, D3-2, D4-1 to D4-4)=120+56×2+24×4=328 bits.

Next, the encoding unit 100d-A generates redundant bits R2 having a length of 8 bits from the information bits D1 having a length of 120 bits×1 row and outputting the information bits D1 and the redundant bits. R2 is output. Further, the encoding unit 100d-A calculates the length from the bit string of the i-th bit (i is an integer from 1 to R)×120 columns of the 120 columns of redundant bits R1-1 added to the information bit D1. An 8-bit redundant bit R2 is generated, and a bit string of 120 columns of the i-th bit of the redundant bit R1-1 and the redundant bit R2 are output. The encoding unit 100d-A performs such encoding processing and outputs the processing results for each row of information bits D1 and for each redundant bit R1-1 shown in FIG. 17.

On the other hand, the encoding unit 100d-B converts the information bits D3-1 and D3-2 of length 56 bits×1 row outputted from the encoding unit 101d into redundant bits R4-1 and R4-2 of length 8 bits, respectively. Generate 2. Encoding section 100d-B outputs information bit D3-1, redundant bit R4-1, information bit D3-2, and redundant bit R4-2.

The encoding unit 100d-B also generates an 8-bit length redundant bit R4- from the i-th bit x 56 columns of redundant bits R1-2 added to the information bit D3-1. 1, and of the 56 columns of redundant bits R1-3 added to the information bit D3-2, a redundant bit R4-2 with a length of 8 bits is generated from the i-th bit×56 columns of bit strings. The encoding unit 100d-B encodes a bit string of the i-th bit x 56 columns of the redundant bit R1-2, a bit string of the i-th bit x 56 columns of the redundant bit R1-2, a redundant bit R4-1, a bit string of the i-th bit x 56 column of the redundant bit R1-3, and a bit string of the i-th bit x 56 columns of the redundant bit R1-2. Bits R4-2 are output. The encoding unit 100d-B performs the above encoding process and outputs the processing results for each row of information bits D3-1 and D3-2 and redundant bits R1-2 and R1-3 shown in FIG. Do this bit by bit.

The encoding unit 100d-C extracts redundant bits each having a length of 8 bits from the information bits D4-1, D4-2, D4-3, and D4-4 of 24 bits in length x 1 row output from the encoding unit 101d. Generate R5-1, R5-2, R5-3, and R5-4. The encoding unit 100d-B encodes information bit D4-1, redundant bit R5-1, information bit D4-2, redundant bit R5-2, information bit D4-3, redundant bit R5-3, and information bit D4-4. Redundant bits R5-4 are output.

The encoding unit 100d-C also generates an 8-bit length redundant bit R4- from the i-th bit x 24 columns of redundant bits R1-4 added to the information bit D4-1. 1, and of the 24 columns of redundant bits R1-5 added to the information bit D4-2, a redundant bit R4-2 with a length of 8 bits is generated from the i-th bit x 24 columns of bit strings, Among the 24 columns of redundant bits R1-6 added to the information bit D4-3, a redundant bit R4-3 with a length of 8 bits is generated from the i-th bit x 24 columns of redundant bits R1-6, and the information bit D4-4 is Of the 24 columns of redundant bits R1-7 added to , redundant bits R4-4 having a length of 8 bits are generated from the i-th bit×24 columns of bit strings.

The encoding unit 100d-B encodes a bit string of the i-th bit x 24 columns of the redundant bits R1-4, a bit string of the i-th bit x 24 columns of the redundant bits R1-4, a redundant bit R5-1, a bit string of the i-th bit x 24 columns of the redundant bits R1-5, and a redundant bit string of the redundant bits R1-4. Bit R5-2, a bit string of the i-th bit of redundant bits R1-6 x 24 columns, redundant bit R5-3, a bit string of i-th bit of redundant bits R1-7 x 24 columns, and redundant bit R5. -4 is output. The encoding unit 100d-C performs the above encoding process and outputs the processing results for each row of information bits D4-1, D4-2, D4-3, and D4-4 shown in FIG. 17, and redundant bits. This is done for each bit of R1-4 to R1-7.

The code length in the encoding unit 100d-A is (length of D1+length of R2)=120+8=128 bits. The code length in the encoding unit 100d-B is (length of D3-1 + length of R4-1) = (length of D3-2) = 56 + 8 = 64 bits, and the code length in the encoding unit 100d-A is It is 1/2 of the length. The code length in the encoding unit 100d-C is (length of D4-1 + length of R5-1) = (length of D4-2 + length of R5-2) = (length of D4-3 + length of R5- 3) = (length of D4-4 + length of R5-4) = 24 + 8 = 32 bits, which is 1/2 of the code length in the encoding unit 100d-B (the length of the code in the encoding unit 100d-A). 1/4 of the length).

Further, the redundancy of the redundant bit R2 is (length of R2)/(length of D1+length of R2)=8/128. The redundancy of redundant bits R4-1 and R4-2 is (length of R4-1)/(length of D3-1+length of R4-1)=(length of R4-2)/(length of D3- 2 length+R4-2 length)=8/64, which is twice the redundancy of redundant bit R2. The redundancy of redundant bits R5-1, R5-2, R5-3, and R5-4 is (length of R5-1)/(length of D4-1+length of R5-1)=(R5-2 length) / (Length of D4-2 + Length of R5-2) = (Length of R5-3) / (Length of D4-3 + Length of R5-3) = (Length of R5-4 )/(length of D4-4 + length of R5-4) = 8/32, which is twice the redundancy of redundant bits R4-1 and R4-2 (four times the redundancy of redundant bit R2) It is.

Next, the symbol mapping device 11d in the transmission signal processing device 1 performs multilevel modulation of the transmission data encoded by the encoding device 10. Specifically, the symbol mapping device 11d sequentially extracts, for example, two bits at a time from a bit string consisting of D1 and R2 included in the encoded transmission data, and uses the extracted two bits as one of the bits corresponding to the symbol. Allocate to the upper bits (for example, the 1st and 2nd bits). At the same time, the symbol mapping device 11d sequentially extracts, for example, two bits at a time from the bit string consisting of D3-1, R4-1, D3-2, and R4-2 included in the encoded transmission data, and the extracted two bits are It is assigned to the intermediate bits (for example, the third and fourth bits) among the plurality of bits corresponding to the symbol. Furthermore, the symbol mapping device 11d consists of D4-1, R5-1, D4-2, R5-2, D4-3, R5-3, D4-4, and R5-4 included in the encoded transmission data. For example, two bits are sequentially extracted from the bit string, and the extracted two bits are assigned to the lower bits (for example, the 5th and 6th bits) among the plurality of bits corresponding to the symbol.

Further, the symbol mapping device 11d sequentially extracts, for example, two bits at a time from the redundant bits R1-1 and redundant bits R2 for 120 columns, and assigns the extracted two bits to the upper bits of the plurality of bits corresponding to the symbol. assign. At the same time, the symbol mapping device 11d sequentially extracts, for example, two bits each from redundant bits R1-2 and redundant bits R4-1 for 56 columns and redundant bits R1-3 and redundant bits R4-2 for 56 columns. The two bits thus obtained are assigned to the middle bits among the plurality of bits corresponding to the symbol. Further, the symbol mapping device 11d generates redundant bits R1-4 and R5-1 for 24 columns, redundant bits R1-5 and R5-2 for 24 columns, and redundant bits R1-6 for 24 columns. For example, 2 bits are sequentially extracted from the redundant bit R5-3, 24 columns of redundant bits R1-7, and redundant bit R5-4, and the extracted 2 bits are set as the lower bits of the plurality of bits corresponding to the symbol. assign.

FIG. 19 is a block diagram showing the configuration of the error correction device 20 in the received signal processing device 2 according to this embodiment. The error correction device 20 includes an error correction decoding section 200d-A (first error correction decoding section), an error correction decoding section 200d-B (fourth error correction decoding section), and an error correction decoding section 200d-C ( and an error correction decoding section 201d (third error correction decoding section).

The symbol demapping device 21d in the received signal processing device 2 determines the symbol position on the complex plane from the received data XI, 17 is demodulated.

Next, the error correction decoding unit 200d-A performs error correction on the information bit D1 having a length of 120 bits out of the output of the symbol demapping device 21d based on the redundant bit R2 added to D1, and after the error correction The information bit D1 is output. In addition, the error correction decoding unit 200d-A detects an error in the i-th bit (i is an integer from 1 to R) x 120 columns of redundant bits R1-1 added to the information bit D1. Correction is performed based on the redundant bit R2 added to this bit string, and a bit string of error-corrected i-th bit×120 columns is output. The error correction decoding unit 200d-A performs such error correction decoding processing and outputs the processing results for each row of information bits D1 and for each redundant bit R1-1 shown in FIG.

The error correction decoding unit 200d-B performs error correction on the information bits D3-1 and D3-2, each having a length of 56 bits, out of the output from the symbol demapping device 21d. This is performed based on bits R4-1 and R4-2, and error-corrected information bits D3-1 and D3-2 are output.

Additionally, the error correction decoding unit 200d-B adds error correction for the i-th bit x 56 columns of bit strings to this bit string among the 56 columns of redundant bits R1-2 added to the information bit D3-1. The error-corrected bit string of the i-th bit×56 columns is output. Furthermore, the error correction decoding unit 200d-B adds error correction of the i-th bit×56 columns of bit strings to this bit string among the 56 columns of redundant bits R1-3 added to the information bits D3-2. The error-corrected bit string of the i-th bit×56 columns is output. The error correction decoding unit 200d-B performs the above error correction decoding process and outputs the processing results for each row of information bits D3-1 and D3-2 shown in FIG. 17 and redundant bits R1-2 and R1-. Perform every 3 bits.

The error correction decoding unit 200d-C performs error correction on the information bits D4-1, D4-2, D4-3, and D4-4, each having a length of 24 bits, out of the output from the symbol demapping device 21d. Information bits D4-1, D4-2 after error correction based on redundant bits R5-1, R5-2, R5-3, R5-4 added to D4-2, D4-3, D4-4 , D4-3, and D4-4.

Additionally, the error correction decoding unit 200d-C adds error correction for the i-th bit x 24 columns of bit strings to this bit string among the 24 columns of redundant bits R1-4 added to the information bit D4-1. The error-corrected bit string of the i-th bit×24 columns is output. Additionally, the error correction decoding unit 200d-C adds error correction for the i-th bit×24 columns of bit strings to this bit string among the 24 columns of redundant bits R1-5 added to the information bits D4-2. The error-corrected bit string of the i-th bit×24 columns is output.

Furthermore, the error correction decoding unit 200d-C adds error correction for the i-th bit×24 columns of bit strings to this bit string among the 24 columns of redundant bits R1-6 added to the information bits D4-3. The error-corrected bit string of the i-th bit×24 columns is output. Furthermore, the error correction decoding unit 200d-C adds error correction of the i-th bit×24 columns of bit strings to this bit string among the 24 columns of redundant bits R1-7 added to the information bits D4-4. The error-corrected bit string of the i-th bit×24 columns is output based on the redundant bit R5-4. The error correction decoding unit 200d-C performs the above error correction decoding process and outputs the processing results for each row of information bits D4-1 to D4-4 and redundant bits R1-4 to R1- shown in FIG. This is done every 7 bits.

The error correction decoding unit 201d performs error correction on the information bits D1 having a length of 1 bit×M rows outputted from the error correction decoding unit 200d-A, using redundant bits R1- in the row direction added to this one column D1. 1 and outputs the error-corrected information bit D1. In addition, the error correction decoding unit 201d performs error correction on the information bits D3-1 and D3-2 of 1 bit in length×M rows output from the error correction decoding unit 200d-B, and the error correction of the information bits D3-1 and D3-2 of one column, respectively. This is performed based on the redundant bits R1-2 and R1-3 in the row direction added to D3-2, and error-corrected information bits D3-1 and D3-2 are output.

Furthermore, the error correction decoding unit 201d performs error correction on the information bits D4-1, D4-2, D4-3, and D4-4 of length 1 bit×M rows output from the error correction decoding unit 200d-C. Error correction is performed based on redundant bits R1-4, R1-5, R1-6, and R1-7 in the row direction added to D4-1, D4-2, D4-3, and D4-4 in one column, respectively. The subsequent information bits D4-1, D4-2, D4-3, and D4-4 are output. The error correction decoding unit 201d performs the above error correction decoding process for each column of information bits D1, D3-1, D3-2, D4-1 to D4-4 shown in FIG. Output each time. In this way, the received data can be decoded.

In this embodiment, the number of output bits of the error correction decoding section 200d-A (the length of the information bit D1 is 120 bits) and the number of output bits of the error correction decoding section 200d-B (the length of the information bits D3-1 and D3-2) are compared. The total of the number of output bits (length of information bits D4-1 to D4-4, 96 bits) of the error correction decoding unit 200d-C matches the number of input bits of the error correction decoding unit 201d, which is 328 bits. . In this way, in this embodiment, the effects described in the first embodiment can be obtained.

Further, in the fourth embodiment, a redundant bit R1 is added in the column direction to the information bits D1, D3-1, D3-2, D4-1 to D4-4, and furthermore, the information bits D1, D3-1, Redundant bits R2, R4-1, R4-2, R5-1 to R5-4 were added in the column direction to D3-2, D4-1 to D4-4 and redundant bit R1.

In contrast, in this embodiment, redundant bits R1-1 to R1-7 are added to the information bits D1, D3-1, D3-2, D4-1 to D4-4 in the row direction, and further information For bits D1, D3-1, D3-2, D4-1 to D4-4 and redundant bits R1-1 to R1-7, redundant bits R2, R4-1, R4-2, R5-1 to R5-4 is added. In this embodiment, redundant bit R1 and Since the error that overlaps between the redundant bits R2, R4-1, R4-2, R5-1 to R5-4 is at most 1 bit, the error correction ability can be further improved compared to the fourth embodiment. .

Note that the encoding methods applicable to the first to sixth embodiments include, for example, an LDPC (Low Density Parity Check) code, a Reed-Solomon code, a BCH (Bose-Chaudhuri-Hocquenghem) code, a Hamming code, a convolutional code, There are turbo codes, etc. In the first to sixth embodiments, the explanation is given using an example of encoding in which the length of information bits does not change, but the redundancy of the third encoding is higher than the redundancy of the second encoding. If the sum of the number of output bits of the first error correction decoding unit and the number of output bits of the second error correction decoding unit matches the number of input bits of the third error correction decoding unit by multiplying by a predetermined number. , the present invention may be applied to encoding where the length of information bits is converted.

Each of the transmission signal processing device 1 and reception signal processing device 2 described in the first to fifth embodiments includes a computer equipped with a CPU (Central Processing Unit), a storage device, and an interface, and a computer that controls these hardware resources. This can be achieved by using a program. The CPU of each device executes the processes described in the first to sixth embodiments according to the program stored in the storage device. It is also possible to configure at least a portion of each of the transmission signal processing device 1 and the reception signal processing device 2 with hardware logic such as an ASIC (application specific integrated circuit) or an FPGA (field-programmable gate array). .

The present invention can be applied to, for example, a coherent optical communication system.

DESCRIPTION OF SYMBOLS 1... Transmission signal processing device, 2... Reception signal processing device, 3... Optical transmission module, 4... Optical receiving module, 5... Optical fiber transmission line, 6... Transmitting device, 7... Receiving device, 10... Encoding device, 11 , 11a to 11d... Symbol mapping device, 21, 21a to 21d... Symbol demapping device, 20... Error correction device, 100-A, 100a-A to 100d-A, 100-B, 100a-B to 100d-B, 100c-C, 100d-C, 101, 101a to 101d... encoding unit, 200-A, 200a-A to 200d-A, 200-B, 200a-B to 200d-B, 200c-C, 200d-C, 201, 201a to 201d...Error correction decoding unit.

Claims (8)

Among the received data demodulated by multi-level modulation symbol demapping processing, the error correction of the first bit string that has been subjected to the first encoding and the second encoding on the transmitting side is performed by the second encoding. a first error correction decoding unit configured to perform the correction based on a second redundant bit added to the first bit string;
Error correction of a second bit string that has been subjected to the first encoding and third encoding on the transmitting side of the demodulated received data is added to the second bit string by the third encoding. a second error correction decoding unit configured to perform the correction based on the third redundant bits that have been detected;
Error correction of information bits included in the error-corrected first and second bit strings is performed based on first redundant bits added to the information bits by the first encoding. a third error correction decoding unit,
The second bit string corresponds to the symbol, and a third bit string is allocated to bits lower than the bits to which the first bit string is allocated, among a plurality of bits corresponding to a symbol of multilevel modulation. out of the plurality of bits, a fourth bit string is allocated to a lower bit than the bit to which the third bit string is allocated, and
The second error correction decoding unit includes:
a fourth error correction decoding unit configured to perform error correction of the third bit string based on third redundant bits added to the third bit string by the third encoding;
Two of the fifth error correction decoding units configured to perform error correction of the fourth bit string based on third redundant bits added to the fourth bit string by the third encoding. including;
The redundancy of the third encoding for the third bit string is twice the redundancy of the second encoding, and the redundancy of the third encoding for the fourth bit string is twice the redundancy of the second encoding. 4 times the redundancy of the second encoding,
The total number of output bits of the first error correction decoding section and the second error correction decoding section matches the number of input bits of the third error correction decoding section. correction device. Among the received data demodulated by multi-level modulation symbol demapping processing, the error correction of the first bit string that has been subjected to the first encoding and the second encoding on the transmitting side is performed by the second encoding. a first error correction decoding unit configured to perform the correction based on a second redundant bit added to the first bit string;
Error correction of a second bit string that has been subjected to the first encoding and third encoding on the transmitting side of the demodulated received data is added to the second bit string by the third encoding. a second error correction decoding unit configured to perform the correction based on the third redundant bits;
Error correction of information bits included in the error-corrected first and second bit strings is performed based on first redundant bits added to the information bits by the first encoding. a third error correction decoding unit,
The second bit string is a bit string assigned to bits lower than the bits to which the first bit string is assigned, among a plurality of bits corresponding to a symbol of multilevel modulation,
The redundancy of the third encoding is a predetermined number (the predetermined number is a real number greater than 0) times the redundancy of the second encoding,
The sum of the number of output bits of the first error correction decoding unit and the number of output bits of the second error correction decoding unit matches the number of input bits of the third error correction decoding unit,
The first encoding is a process of adding the first redundant bits in the row direction for each column to the information bits included in the first and second bit strings,
The second encoding is a process of adding the second redundant bits in the column direction to each of the information bits included in the first bit string and the first redundant bits added to the information bits. and
The third encoding is a process of adding the third redundant bits in the column direction to each of the information bits included in the second bit string and the first redundant bits added to the information bits. and
An error correction device characterized in that in the structure of the demodulated received data, the direction in which the first redundant bits are arranged and the directions in which the second and third redundant bits are arranged are orthogonal. The error correction device according to claim 2 ,
The error correction device characterized in that the redundancy of the third encoding is twice the redundancy of the second encoding. a first encoding unit configured to perform first encoding on transmission data;
a second encoding unit configured to perform second encoding on a first bit string of the transmission data encoded by the first encoding unit;
and a third encoding unit configured to perform third encoding on the second bit string of the transmission data encoded by the first encoding unit,
The second bit string is a bit to which the first bit string is assigned among a plurality of bits corresponding to a multi-level modulation symbol when performing multi-level modulation on the outputs of the second and third encoding units. and a fourth bit string that is assigned to bits lower than the bits to which the third bit string is assigned among the plurality of bits corresponding to the symbol. Divided into
The third encoding unit includes:
a fourth encoding unit configured to perform the third encoding on the third bit string;
including two fifth encoding units configured to perform the third encoding on the fourth bit string,
The redundancy of the third encoding for the third bit string is twice the redundancy of the second encoding, and the redundancy of the third encoding for the fourth bit string is twice the redundancy of the second encoding. An encoding device characterized in that the redundancy of the second encoding is four times that of the second encoding . a first encoding unit configured to perform first encoding on transmission data;
a second encoding unit configured to perform second encoding on a first bit string of the transmission data encoded by the first encoding unit;
and a third encoding unit configured to perform third encoding on the second bit string of the transmission data encoded by the first encoding unit,
The second bit string is a bit to which the first bit string is assigned among a plurality of bits corresponding to a multi-level modulation symbol when performing multi-level modulation on the outputs of the second and third encoding units. is a bit string assigned to the lower bits than
The redundancy of the third encoding is a predetermined number (the predetermined number is a real number greater than 0) times the redundancy of the second encoding,
The first encoding is a process of adding first redundant bits in the row direction for each column to the information bits included in the first and second bit strings,
The second encoding is a process of adding second redundant bits in the column direction to each of the information bits included in the first bit string and the first redundant bits added to the information bits. can be,
The third encoding is a process of adding third redundant bits in the column direction to each of the information bits included in the second bit string and the first redundant bits added to the information bits. can be,
In the configuration of data output from the second and third encoding units, the arrangement direction of the first redundant bits is orthogonal to the arrangement direction of the second and third redundant bits. encoding device. The encoding device according to claim 5,
An encoding device characterized in that the redundancy of the third encoding is twice the redundancy of the second encoding. a transmitting device comprising: an encoding device configured to encode transmission data; and a symbol mapping device configured to perform multilevel modulation of data encoded by the encoding device;
A symbol demapping device configured to demodulate encoded data from a signal received from the transmitting device; and an error correction device configured to perform error correction on the data demodulated by the symbol demapping device. and
The encoding device includes a first encoding unit configured to perform first encoding on the transmission data;
a second encoding unit configured to perform second encoding on a first bit string of the transmission data encoded by the first encoding unit;
and a third encoding unit configured to perform third encoding on the second bit string of the transmission data encoded by the first encoding unit,
The error correction device includes:
Error correction of the first bit string of the data demodulated by the symbol demapping device is performed based on second redundant bits added to the first bit string by the second encoding. a first error correction decoding unit,
a second bit string configured to perform error correction of the second bit string of the demodulated data based on third redundant bits added to the second bit string by the third encoding; an error correction decoding unit;
Error correction of information bits included in the error-corrected first and second bit strings is performed based on first redundant bits added to the information bits by the first encoding. a third error correction decoding unit,
The second bit string corresponds to a third bit string that is allocated to bits lower than the bits to which the first bit string is allocated, among a plurality of bits corresponding to a symbol of multilevel modulation , and a third bit string that is allocated to a lower bit than the bit to which the first bit string is allocated. The plurality of bits are divided into two: a fourth bit string is allocated to a bit lower than the bit to which the third bit string is allocated;
The second error correction decoding unit includes:
a fourth error correction decoding unit configured to perform error correction of the third bit string based on third redundant bits added to the third bit string by the third encoding;
Two of the fifth error correction decoding units configured to perform error correction of the fourth bit string based on third redundant bits added to the fourth bit string by the third encoding. including;
The redundancy of the third encoding for the third bit string is twice the redundancy of the second encoding, and the redundancy of the third encoding for the fourth bit string is twice the redundancy of the second encoding. 4 times the redundancy of the second encoding,
Communication characterized in that the sum of the number of output bits of the first error correction decoding section and the number of output bits of the second error correction decoding section matches the number of input bits of the third error correction decoding section. system. a transmitting device comprising: an encoding device configured to encode transmission data; and a symbol mapping device configured to perform multilevel modulation of data encoded by the encoding device;
A symbol demapping device configured to demodulate encoded data from a signal received from the transmitting device; and an error correction device configured to perform error correction on the data demodulated by the symbol demapping device. and
The encoding device includes a first encoding unit configured to perform first encoding on the transmission data;
a second encoding unit configured to perform second encoding on a first bit string of the transmission data encoded by the first encoding unit;
and a third encoding unit configured to perform third encoding on the second bit string of the transmission data encoded by the first encoding unit,
The error correction device includes:
Error correction of the first bit string of the data demodulated by the symbol demapping device is performed based on second redundant bits added to the first bit string by the second encoding. a first error correction decoding unit,
a second bit string configured to perform error correction of the second bit string of the demodulated data based on third redundant bits added to the second bit string by the third encoding; an error correction decoding unit;
Error correction of information bits included in the error-corrected first and second bit strings is performed based on first redundant bits added to the information bits by the first encoding. a third error correction decoding unit,
The second bit string is a bit string that is allocated to lower bits than the bits to which the first bit string is allocated, among a plurality of bits corresponding to a symbol of multilevel modulation,
The redundancy of the third encoding is a predetermined number (the predetermined number is a real number greater than 0) times the redundancy of the second encoding,
The sum of the number of output bits of the first error correction decoding unit and the number of output bits of the second error correction decoding unit matches the number of input bits of the third error correction decoding unit,
The first encoding is a process of adding the first redundant bits in the row direction for each column to the information bits included in the first and second bit strings,
The second encoding is a process of adding the second redundant bits in the column direction to each of the information bits included in the first bit string and the first redundant bits added to the information bits. and
The third encoding is a process of adding the third redundant bits in the column direction to each of the information bits included in the second bit string and the first redundant bits added to the information bits. and
A communication system characterized in that, in the configuration of the demodulated received data, the direction in which the first redundant bits are arranged and the directions in which the second and third redundant bits are arranged are orthogonal to each other.

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