JP7179934B1 - Error correction device, error correction method and communication device - Google Patents

Abstract

An error correction device capable of improving transmission characteristics while suppressing the circuit scale is provided. An error correction device (20) of the present invention includes three or more stages of error correction processing circuits (31, 32, 33) that perform soft-decision error correction processing based on likelihood information, and error correction processing circuits. Three or more stages of likelihood calculation circuits (21, 22, 23) for supplying likelihood information are provided, and three or more stages of error correction processing circuits (31, 32, 33) are arranged in descending order of correction capability, and at least One error correction processing circuit (31, 32, 33) is configured not to perform iterative decoding processing, and at least one likelihood calculation circuit (22, 23) in the second and subsequent stages performs error correction processing in the preceding stage. Using the first likelihood information updated by the correction processing of the circuit, the second likelihood information having a smaller number of bits than the output bit number of the first likelihood information is calculated, and the second likelihood information is obtained. is supplied to an error correction processing circuit arranged in the subsequent stage. [Selection drawing] Fig. 3

Description

The present invention relates to an error correction device, an error correction method, and a communication device capable of improving transmission characteristics.

In coherent optical communication, in order to improve transmission characteristics, digital signal processing is used to compensate for distortion and frequency/phase fluctuations that occur during transmission. An error correction device is provided between transmission and reception to reduce data errors in transmission characteristics. In general, transmission characteristics are improved by performing error correction coding on data on the transmitting side and performing error correction according to the coding on the receiving side.

Hamming code, BCH code, Reed-Solomon code, and convolutional code/Viterbi decoding, for example, are generally well-known error correction methods. In recent years, in particular, in communication devices, the development of CPU computing power has made it possible to perform complex and large-scale processing. An error correction method is used. In recent years, data are arranged in a matrix of n rows and m columns, and error correction processing is performed on the data in the row and column directions to improve the correction capability.

In error correction processing, hard decision is performed based on the result of decoding to "1" or "0" and correction processing is performed. There is a soft decision in which correction processing is performed based on The latter method has a higher correction capability than the former method, but the circuit scale and processing scale increase, and the power consumption also increases. Therefore, conventionally, in correction processing using soft decisions, there have been proposed methods for improving correction capability while suppressing increases in circuit scale and processing scale.

For example, Patent Literature 1 proposes a method of reducing the number of iterations until completion of decoding by updating the log-likelihood ratio during iterative decoding processing in an iterative decoding method for LDPC codes. Further, Patent Document 2 proposes a method of suppressing an increase in circuit size by changing the likelihood during iteration in iterative decoding using concatenated codes including convolutional codes. Furthermore, Japanese Patent Laid-Open No. 2002-200003 proposes a method of performing error correction processing based on two soft decisions to improve error correction capability when the transmission speed is increased.

JP 2009-225164 A JP 2011-205511 A JP 2003-069535 A

In Patent Documents 1 and 2, there is a problem that the increase in circuit size due to the circuits required for the repeated processing cannot be suppressed because the repeated processing is performed in one error correction processing. Moreover, in Patent Document 3, since the number of output bits of the soft decision value is the same in each error correction process, there is a problem that the accompanying increase in circuit size cannot be suppressed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an error correction device, an error correction method, and a communication device capable of improving transmission characteristics while suppressing the circuit scale.

In order to solve the above-described problems, the error correction apparatus of the present invention includes three or more stages of error correction processing circuits that perform soft-decision error correction processing based on likelihood information; three or more stages of likelihood calculation circuits for supplying degree information, wherein the three or more stages of error correction processing circuits are arranged in descending order of correction capability, and at least one of the error correction processing circuits performs iterative decoding processing. At least one of the likelihood calculation circuits in the second and subsequent stages uses the first likelihood information updated by the correction processing of the error correction processing circuit in the previous stage to calculate the first likelihood Second likelihood information having a number of bits smaller than the number of output bits of information is calculated, and the second likelihood information is supplied to the error correction processing circuit arranged at the subsequent stage.

In order to solve the above-described problems, the error correction method of the present invention includes three or more stages of error correction processing circuits for performing soft-decision error correction processing based on likelihood information; An error correction method in an error correction device having a likelihood calculation circuit that supplies degree information, wherein the three or more stages of error correction processing circuits are arranged in descending order of correction capability, and at least one of the error correction processing circuits is configured not to perform iterative decoding processing, and at least one of the likelihood calculation circuits in the second and subsequent stages uses the first likelihood information updated by the correction processing of the error correction processing circuit in the preceding stage. , second likelihood information having a number of bits smaller than the number of output bits of the first likelihood information is calculated, and the second likelihood information is supplied to the error correction processing circuit disposed in the subsequent stage.

According to the present invention, it is possible to provide an error correction device, an error correction method, and a communication device capable of improving transmission characteristics while suppressing the circuit scale.

FIG. 1 is a diagram showing a configuration example of a communication device including an error correction device according to an embodiment of the present invention. FIG. 2 is a diagram showing a configuration example of an error correction coding apparatus according to an embodiment of the present invention. FIG. 3 is a diagram showing a configuration example of an error correction device according to an embodiment of the present invention. FIG. 4 is a diagram for explaining likelihood information according to the embodiment of the present invention. FIG. 5 is a diagram for explaining the operation of the error correction coding device according to the embodiment of the present invention. FIG. 6 is a diagram for explaining the operation of the error correction device according to the embodiment of the present invention. FIG. 7 is a flowchart for explaining the encoding operation of the error correction method according to the embodiment of the present invention. FIG. 8 is a flowchart for explaining the error correction operation of the error correction method according to the embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth below.

<Overview of the present invention>
SUMMARY OF THE INVENTION An object of the present invention is to provide an error correction device capable of improving transmission characteristics while suppressing the circuit scale.

The present invention has the following features in order to solve the above problems.
(a) In error correction processing, iterative decoding processing is not performed.
(b) Decoding processing is performed by successively connecting three or more stages of error correction processing based on soft decisions with different correction capabilities.
(c) The likelihood information obtained in the previous error correction process is used in the subsequent error correction process.
(d) Decrease the number of quantization bits of likelihood information in the order of error correction processing.

ADVANTAGE OF THE INVENTION This invention has the following effects by having the said characteristic.
(A) Since iterative decoding processing is not performed in error correction processing, the circuit scale can be reduced.
(B) Improve the correction capability by combining three or more stages of soft-decision processing with different correction capabilities instead of not performing iterative decoding processing inside the error correction processing. Since it is used, the circuit scale can be reduced.
(D) The circuit size can be reduced by reducing the number of bits of likelihood information used in the subsequent error correction process.

Reducing the number of redundant bits reduces the circuit scale, but by combining three or more stages of error correction by different soft-decision processes, the correction capability is improved. can be done. Furthermore, the circuit size can be reduced by using the likelihood information obtained in the preceding error correction processing in the succeeding error correction processing to reduce the number of bits of the likelihood information.

<Communication device including error correction device>
FIG. 1 is a configuration example of a communication device including an error correction device according to an embodiment of the present invention. FIG. 1 shows a configuration example in which an error correction coding device 10 and an error correction device 20 according to an embodiment of the present invention are applied to a coherent optical communication system communication device.

In the coherent optical communication system communication apparatus of FIG. A transmission signal processing device 100 includes an error correction coding device 10 . The received signal processing device 200 includes an error correction device 20 . The transmitting side device and the receiving side device are connected via an optical fiber transmission line 500 .

The error correction coding device 10 in the transmission signal processing device 100 performs error correction coding on transmission data. The optical transmission module 300 generates an optical signal from transmission data encoded for error correction. In general coherent optical communication, a horizontally polarized optical signal X and a vertically polarized optical signal are combined and transmitted. When QPSK is used as the modulation method, transmission data is divided into horizontal polarization optical signal data (XI, XQ) and vertical polarization optical signal data (YI, YQ).

XI and XQ indicate the coordinates on the horizontal axis and the orthogonal axis on the complex plane of the horizontally polarized optical signal data, that is, the horizontal component and the orthogonal component, respectively. YI and YQ indicate coordinates on the horizontal axis and the orthogonal axis on the complex plane of the vertically polarized optical signal data, that is, the horizontal component and the orthogonal component, respectively. The transmission data is mapped to coordinates on the complex plane of the carrier wave and transmitted to the receiving side via the optical fiber transmission line 500 .

The optical receiver module 400 generates received data from the received optical signal. The optical receiver module 400 can output horizontally polarized optical signal data (XI, XQ) and vertically polarized optical signal data (YI, YQ). These data (XI, XQ, YI, YQ) are converted into digital signals in the received signal processing device 200 and subjected to data error correction processing in the error correction device 20 .

In the coherent optical communication device, transmission data is transmitted as a horizontally polarized optical signal and a vertically polarized optical signal, but it is also possible to transmit data using only one polarized signal. Even in that case, the error correction device 20 according to the embodiment of the present invention can be used.

Moreover, the communication device that can use the error correction device 20 according to the embodiment of the present invention is not limited to the coherent optical communication device described above. The error correction device 20 according to the embodiment of the present invention can also be used in other communication devices including wireless communication. It goes without saying that such communication devices are also within the scope of the present invention.

<Configuration of Error Correction Coding Device>
FIG. 2 is a diagram showing a configuration example of an error correction coding apparatus according to an embodiment of the present invention. In the configuration example of FIG. 2, in response to error correction processing by three stages of soft decisions on the receiving side, error correction coding apparatus 10 on the transmitting side includes three stages of redundant bit addition circuits (11, 12, 13). In the following description, a case will be described in which error correction processing is performed using three stages of soft decisions, but the present invention is not limited to error correction processing using three stages of soft decisions.

In the configuration example of FIG. 2, a redundant bit adding circuit #3 (third redundant bit adding circuit) having a low redundancy is arranged in the first stage, and a redundant bit adding circuit #3 having a higher redundancy than the first stage is arranged in the second stage. A bit addition circuit #2 (second redundancy bit addition circuit) is arranged, and a redundancy bit addition circuit #1 (first redundancy bit addition circuit) having higher redundancy than the second stage is arranged in the third stage. It is

The redundant bit adding circuit #3 is supplied with transmission data and adds redundant bits for the third error correction. The signal to which redundant bits have been added by the redundant bit adding circuit #3 is supplied to the redundant bit adding circuit #2, where redundant bits are added for the second error correction. The signal to which redundant bits have been added by the redundant bit adding circuit #2 is supplied to the redundant bit adding circuit #1, where redundant bits are added for the first error correction.

In the configuration example of FIG. 2, by arranging a plurality of redundant bit addition circuits, the error correction capability is improved, and the code length (information bit + redundant bit) of the first and second stages is shortened. Scale can be reduced.

For example, an LDPC code can be used as the soft-decision error correction code in this embodiment. All three-stage soft-decision error correction codes may be LDPC codes. As the soft-decision error correcting code in each stage, in addition to the LDPC code, a Reed-Solomon code, a BCH code, a Hamming code, a convolutional code, a turbo code, a code combining a plurality of codes (concatenated code), and the like are used. good too. The code length of the error correction code at each stage can also be appropriately determined according to the state of the transmission line.

<Configuration of error correction device>
FIG. 3 is a diagram showing a configuration example of an error correction device according to an embodiment of the present invention. In this embodiment, since error correction processing is performed by three stages of soft decisions, the error correction device 20 on the receiving side is configured with three stages of error correction processing circuits (31, 32, 33) accordingly. there is Likelihood calculation circuits (21, 22, 23) for calculating likelihood information for performing soft-decision error correction are installed in the preceding stages of the correction processing circuits in each stage.

<Likelihood information>
First, the likelihood information used for error correction in this embodiment will be described. Likelihood information represents likelihood (reliability) for each bit (or symbol). The likelihood information of the likelihood calculation circuit #1, the likelihood calculation circuit #2, and the likelihood calculation circuit #3 of the present embodiment are respectively the likelihood of each bit (or symbol) of received data on the receiving side, It represents the likelihood of each bit (or symbol) after one error correction and the likelihood of each bit (or symbol) after second error correction. When obtaining likelihood information based on coordinate information, which will be described later, the coordinate information is for each symbol (symbol: a group of data sent in one modulation in communication). , the likelihood information can be obtained for each bit, or the likelihood can be calculated for each symbol and each bit in the symbol can be used as common likelihood information. As an example of a modulation system in which a plurality of bits constitutes one symbol, one symbol in QPSK has two bits of information, and one symbol in 16QAM has four bits of information. 8 bits) can be transmitted.

Since the likelihood value of likelihood information representing the reliability of a signal bit is originally an analog value, it is possible to appropriately set how many bits are used to express the likelihood value. When the input likelihood value is large, there are few errors and the probability of erroneous correction is low, so the output likelihood value is large. Conversely, when the input likelihood value is small, there are many errors, and the probability of erroneous correction is high, so the output likelihood value is small. The likelihood value after error correction processing substantially indicates the residual error probability.

The likelihood value can be calculated based on the distance between the coordinates of the ideal point to be transmitted and the coordinates of the received ideal point on the complex plane. The higher the likelihood value of a target bit (or symbol) is, the higher the reliability (probability) of the bit (or symbol) is determined, and error correction processing based on the likelihood value is performed. Further, by transmitting the calculated likelihood information to the error correction processing circuit of the next stage, it can be used for error correction of the next stage.

As a method of calculating the distance between the coordinates on the complex plane, a method of calculating using the sum of the absolute values of the differences of the coordinate values on each axis can be considered. The maximum likelihood value is obtained when the received coordinates coincide with the ideal coordinate point, and the likelihood value decreases as the difference from the ideal coordinate point increases. If there are multiple ideal coordinate points, the intermediate coordinates of the ideal coordinate points will have the lowest likelihood value.

<Specific example of likelihood information>
In this embodiment, a logarithmic likelihood ratio is used as the likelihood information. The likelihood information is not limited to the log-likelihood ratio, and other likelihood information may be used. A specific example of the log-likelihood ratio when the log-likelihood ratio is used as the likelihood information will be described below in the case of using QPSK as the modulation scheme.

FIG. 4 is a diagram for explaining likelihood information according to the embodiment of the present invention. Let Xt1 (XIt1, XQt1) be the ideal coordinate point set on the transmitting side, Xt2 (XIt2, XQt2) be the coordinate point of an adjacent signal point different from the coordinate point Xt1, and Xr (XIr, XQr) be the coordinate point on the receiving side. .

Ar is the amplitude before error correction on the receiving side, At1 is the ideal amplitude of the ideal coordinate point Xt1, At2 is the amplitude of the adjacent coordinate point Xt2 different from the coordinate point Xt1, and φ1 and φ2 are the amplitudes of the receiving side. It is the phase difference between the coordinate point Xr and Xt1 and Xt2.

When expressed on the complex plane, the following relational expressions hold between the coordinate points and the amplitude and phase.
(XIr-XIt1)+j(XQr-XQt1)=(Ar/At1) exp(jφ1)
(XIr-XIt2)+j(XQr-XQt2)=(Ar/At2) exp(jφ2)

The likelihood value can be obtained as follows using, for example, the absolute value of the difference between the coordinates on the transmitting side and the coordinates on the receiving side.
L1=|XIr−XIt1|+|XQr−XQt1|
L2=|XIr−XIt2|+|XQr−XQt2|

The likelihood ratio is the ratio of these two, and the log-likelihood ratio (LLR) can be obtained by logarithmically transforming the likelihood ratio as follows.
LLR=ln(L1/L2)

As the likelihood information, the value of LLR=L1/L2 can also be used as the likelihood information without logarithmically transforming the likelihood ratio. In this case, the amount of arithmetic processing by logarithmic arithmetic can be reduced, and the circuit scale required for it can be reduced. Further, the likelihood information is not limited to information based on the difference in coordinate values, and other information may be used as long as it is an index indicating likelihood.

In the above, an example of calculation of the log-likelihood ratio for one polarized signal (horizontally polarized optical signal X) was explained, but in the case of orthogonal polarization multiplexing transmission, the other polarized signal (vertically polarized optical signal Y) Similarly, the log-likelihood ratio can be calculated.

As a method of logarithmic transformation for obtaining the logarithmic likelihood ratio, there is a method of obtaining the logarithmic value of the likelihood ratio using a calculator. The logarithmic value may be obtained by referring to the up-table and making the correspondence. The use of the logarithmic conversion table eliminates the need for a computing unit for logarithmic conversion, thereby achieving the effects of speeding up processing and reducing circuit size.

As for the logarithmic conversion table, it is possible to keep a conversion table of many patterns, or keep a partial correspondence table, and use the symmetry and similarity of the logarithmic function to convert an arbitrary constant multiple or any constant addition may be combined to obtain the logarithmic value. By using such a simplified method for hardware, it is possible to reduce processing time, circuit scale, and power consumption.

FIG. 4 illustrates the method of calculating likelihood information when QPSK is used as the modulation scheme, but the likelihood information can be obtained in a similar manner even when other modulation schemes are used as the modulation scheme. . Since the error correction in this embodiment does not depend on the modulation scheme, the same error correction method can be applied even when BPSK, 8QAM, 16QAM, 64QAM, or other modulation schemes are used.

For example, when BPSK is used, Xt1 (XIt1, 0) and Xt2 (XIt2, 0) are the ideal coordinate points on the transmitting side, and Xr (XIr, 0) is the coordinate point before error correction on the receiving side. , the sum of the absolute values of the differences from the ideal coordinate points (Xt1, XIt2) on the transmission side. Likelihood information can be similarly calculated for the other polarization signal (vertically polarized optical signal Y) in the case of orthogonal polarization multiplexing transmission.

<First-stage error correction processing>
Received signals XI/XQ/YI/YQ are supplied from the optical receiver module 400 to the likelihood calculation circuit #1 (first likelihood calculation circuit) in the first stage in FIG. The likelihood calculation circuit #1 calculates a logarithmic likelihood ratio as likelihood information #1 for each bit (or symbol) of the received signal. It is assumed that likelihood information #1 to be output has N1 bits.

The error correction processing circuit #1 (first error correction processing circuit) in the first stage performs error correction on the input data #1 using the likelihood information #1. The error correction processing circuit #1 determines bits (or symbols) to be corrected based on the magnitude of the likelihood information #1. For example, among bit (or symbol) candidates to be error-corrected, error correction is performed on bits (or symbols) whose log-likelihood ratio values are smaller than other candidate bits (or symbols). Bits (or symbols) with high likelihood values are probabilistically correct bits (or symbols), so it is better to correct bits (or symbols) with low likelihood values.

Whether or not to perform error correction can be determined by selecting a predetermined number of bits (or symbols) in descending order of likelihood information values, or by selecting bits (or symbols) whose likelihood information values are smaller than a predetermined threshold. There are various possible methods such as the selection of The error correction processing circuit #1 performs error correction on bits (or symbols) selected based on the likelihood information and does not perform iterative decoding. By not performing iterative decoding, the circuit scale can be reduced.

The error correction processing circuit #1 updates the likelihood information of the corrected bit (or symbol), deletes the likelihood information corresponding to the redundant bit, outputs the error-corrected likelihood information #1, and corrects the error. Delete redundant bits from data #1 and output data #2.

<Second-stage error correction processing>
Likelihood calculation circuit #2 (second likelihood calculation circuit) in the second stage in FIG. 1 is supplied.

The likelihood calculation circuit #2 creates likelihood information #2 for each bit (or symbol) for all the input data #2. It is assumed that likelihood information #2 to be output has N2 bits. The likelihood calculation circuit #2 uses the post-error-correction likelihood information #1 (first likelihood information) updated by the error-correction processing circuit #1 to calculate from the least significant post-correction likelihood information #1 By deleting (N1-N2) bits of information, N2-bit likelihood information #2 (second likelihood information) is created.

In the likelihood calculation circuit #2, since the number of output bits is reduced by (N1-N2) bits from the least significant of the corrected likelihood information #1, no separate likelihood calculation circuit is required. Therefore, the circuit scale can be significantly reduced compared to the case where individual calculation circuits are provided.

The second-stage error correction processing circuit #2 (second error correction processing circuit) performs error correction on the input data #2 using the likelihood information #2. In the present embodiment, in the same manner as in error correction processing circuit #1, among bit (or symbol) candidates to be error-corrected, bits (or symbols) whose likelihood information values are smaller than other candidate bits (or symbols) error correction is performed.

Similar to the error correction processing circuit #1, the determination as to whether or not to perform error correction is performed by selecting a predetermined number of bits (or symbols) in descending order of the likelihood information value, or Various methods are conceivable, such as a method of selecting bits (or symbols) smaller than a predetermined threshold. Similarly to the error correction circuit #1, the error correction circuit #2 corrects the error of the selected bit based on the likelihood information and does not perform the iterative decoding process. By not performing iterative decoding processing, the circuit scale can be reduced.

The error correction processing circuit #2 updates the likelihood information of the corrected bit (or symbol), deletes the likelihood information corresponding to the redundant bit, and outputs error-corrected likelihood information #2, Delete redundant bits from the corrected data #2 and output data #3.

<Third-stage error correction processing>
The likelihood calculation circuit #3 (third likelihood calculation circuit) in the third stage in FIG. is supplied.

The likelihood calculation circuit #3 creates likelihood information #3 for each bit (or symbol) for all the input data #3. It is assumed that likelihood information #3 to be output has N3 bits. The likelihood calculation circuit #3 uses the post-error correction likelihood information #2 updated by the error correction processing circuit #2 to calculate (N2-N3) bits from the least significant post-correction likelihood information #2. By deleting the information, N3-bit likelihood information #3 is created.

The likelihood calculation circuit #3 performs a process of reducing the number of output bits from the least significant (N2-N3) bits of the post-correction likelihood information #2. The circuit scale can be significantly reduced as compared with the case of providing a calculation circuit for .

The error correction processing circuit #3 (third error correction processing circuit) in the third stage performs error correction on the input data #3 using the likelihood information #3. In the present embodiment, similar to error correction processing circuit #1 and error correction processing circuit #2, among candidates for bits (or symbols) to be error-corrected, values of likelihood information of other candidate bits (or symbols) Perform error correction on smaller bits (or symbols).

Whether or not to perform error correction is determined by selecting a predetermined number of bits (or symbols) in descending order of likelihood information values, as in error correction processing circuit #1 and error correction processing circuit #2. , a method of selecting bits (or symbols) whose likelihood information value is smaller than a predetermined threshold, and the like. Similarly to the error correction processing circuit #1 and the error correction processing circuit #2, the error correction processing circuit #3 also performs error correction of bits selected based on the likelihood information, and does not perform iterative decoding processing. By not performing iterative decoding processing, the circuit scale can be reduced.

The error correction processing circuit #3 deletes redundant bits from the corrected data #3 and outputs the final received data. Since it is the final stage, it is not necessary to output post-error-correction likelihood information, but post-error-correction likelihood information may be output in order to analyze the state of error correction or the like.

In the error correction processing circuit #1, the error correction processing circuit #2, and the error correction processing circuit #3 of the present embodiment described above, a configuration in which iterative decoding is not performed has been described as an example. Iterative decoding need not be performed, and at least one error correction processing circuit may be configured not to perform iterative decoding.

In addition, a configuration example may be conceived in which a conventional error correction code having high redundancy and performing iterative decoding is combined with a code having low redundancy and not performing iterative decoding. Such a configuration cannot reduce the circuit scale, but by adding a circuit with a small circuit scale to an existing circuit that performs iterative decoding processing, an improvement in error correction capability can be expected. For example, if the redundancy is 1%, there is a high possibility that the error correction capability will not improve even if iterative calculations are performed. An additional configuration is also conceivable.

In the likelihood calculation circuit #2 and the likelihood calculation circuit #3 of the present embodiment described above, likelihood information is generated using the likelihood information transmitted from the previous stage. It is not necessary to use the likelihood information of the previous stage in the decoding process, and at least one decoding process may use the likelihood information of the previous decoding process.

Further, in the error correction process at each stage, if there is only one correction candidate, it may be determined that the correction is to be performed unconditionally. You may If there are multiple correction candidates, the possibility of erroneous correction increases, so whether or not to correct can be determined based on the likelihood information of the bit. For example, if the likelihood value is smaller than a predetermined threshold, it is corrected, and if it is larger than the predetermined threshold, it is not corrected.

As described above, likelihood calculation circuit #1, likelihood calculation circuit #2, and likelihood calculation circuit #3 of the present embodiment output likelihood information for each bit (or symbol). In the error correction process of the third stage, the likelihood information obtained in the previous stage is used to update the likelihood information only in the error-corrected bits. Also, when transmitting the likelihood information to the subsequent stage, since the number of output bits of the corrected likelihood information is reduced from the least significant bit, as a result, the likelihood information of the first stage is reused. will do.

In an actual circuit, when N1, N2, N3=3, 2, 1 bits, which is the minimum number of bits set for three stages, the bit width of the likelihood information is the minimum (3, 2, 1 bit combination) is also sufficient and has been found to perform well. In addition, even when error correction is performed in three stages, the likelihood calculation processing in the second and third stages has a significantly smaller number of calculation processes than in the first stage, so all likelihood information is calculated in each stage. Processing time, circuit scale, and power consumption can all be reduced compared to the case of

Likelihood information represents reliability for each bit. Since the reliability of the received data decreases as the difference from the ideal coordinate point increases, when the probability that the first error correction is correct is high, the reliability of the bit to be corrected in the first error correction is will increase.

On the other hand, when the probability that the first error correction is correct is low, only the probability of the bit (or symbol) that is a candidate for correction by the first error correction is reduced, and the error of the bit (or symbol) is reduced. Correction should not be made. The same is true for the second error correction.

In the present embodiment, by reducing the number of output bits of the likelihood information, the probability of the bits that are highly likely to be erroneous in the error correction processing of each stage is reduced. Since the probability of error correction processing can be increased, error correction performance can be improved and high performance can be maintained even with a small redundancy and a small number of bits of likelihood information.

<Operation of Error Correction Coding Device>
FIG. 5 is a diagram for explaining the operation of the error correction coding device according to the embodiment of the present invention. The code length and redundancy in the configuration example of FIG. 5 are not limited to the code length and redundancy described below, and can be appropriately determined according to the state of the applied transmission line and the circuit scale of the communication device. can.

In the configuration example of FIG. 5, an LDPC code is used as the soft-decision error correction code. Since the LDPC code has a short code length, the circuit scale can be made very small. In high-performance error correction such as LDPC, the larger the code length, the larger the circuit scale. Therefore, as shown in FIG. Therefore, the circuit scale can be reduced.

In FIG. 5, redundant bit addition circuit #3 adds 10 redundant bits to each row of transmission data (information bits) of 1028 bits.times.145 rows, resulting in 1038 (1028+10) bits.times.145 rows. Data #3 is output. The code length in redundant bit addition circuit #3 is 1038 bits, and the redundancy is 1038/1028=1.010.

Redundant bit adding circuit #2 adds 18-bit PAD (additional bit for aligning the number of digits; padding bit), and adds 8-bit redundant bit to each row of 224 bits x 672 rows of data. As a result, 232 (224+8) bits x 672 rows of data #2 are output. The code length in redundant bit addition circuit #2 is 232 bits, and the redundancy is 232/224=1.036.

Redundant bit addition circuit #1 divides the input data into X-polarized waves and Y-polarized waves, and adds 8000 redundant bits to 77952-bit data in each of the X-polarized waves and Y-polarized waves. , X polarization, and Y polarization, 85952-bit data #1 is output. The code length in redundant bit adding circuit #3 is 85952 bits, and the redundancy is 85952/77952=1.102. Here, the values of the number of redundant bits added in the redundant bit adding circuits #3, #2, and #1, and the number of data bits, number of rows, etc., are examples, and any number of bits may be used.

XI and XQ indicating the horizontal component and the orthogonal component on the complex plane of the data for the X-polarized optical signal, and the horizontal component and the orthogonal component on the complex plane for the data for the Y-polarized optical signal from the error correcting encoder. YI and YQ are output. XI and XQ, YI and YQ are mapped to coordinates on the complex plane of the carrier wave in the optical transmission module 300 and transmitted to the receiving side via the optical fiber transmission line 500 .

<Operation of error correction device>
FIG. 6 is a diagram for explaining the operation of the error correction device according to the embodiment of the present invention. The code length and redundancy in the configuration example of FIG. 6 correspond to the configuration example of FIG.

The received signals XI/XQ/YI/YQ are supplied from the optical receiver module 400 to the likelihood calculation circuit #1. The likelihood calculation circuit #1 calculates a log-likelihood ratio (LLR) for each bit (or symbol) of the received signal. Here, the log-likelihood ratio is composed of N1 bits.

The error correction processing circuit #1 executes error correction processing on the input data #1 using the likelihood information #1 supplied from the likelihood calculation circuit #1. Of the bit (or symbol) candidates for error correction, error correction is performed on a bit (or symbol) having a log-likelihood ratio smaller than that of other candidate bits (or symbols). Whether or not to perform error correction can be determined by selecting a predetermined number of bits (or symbols) in descending order of likelihood information values, or by selecting bits (or symbols) whose likelihood information values are smaller than a predetermined threshold. There are various possible methods such as the selection of The error correction processing circuit #1 does not perform iterative decoding.

The error correction processing circuit #1 updates the likelihood information of the corrected bit (or symbol), deletes the likelihood information corresponding to the redundant bit, outputs the error-corrected likelihood information #1, and corrects the error. Delete redundant bits from data #1 and output data #2.

In the likelihood calculation circuit #2, the data for the X polarization and the data for the Y polarization are combined, and the corrected data #2 of the error correction processing circuit #1 and the corrected likelihood information #1 (LLR ) is supplied. The likelihood calculation circuit #2 creates likelihood information #2 (LLR) for each bit (or symbol) of the received signal. Here, the likelihood information #2 is composed of N2 bits. The likelihood calculation circuit #2 generates likelihood information #2 by subtracting one bit from the least significant bit of the corrected likelihood information #1.

The error correction processing circuit #2 uses the likelihood information supplied from the likelihood calculation circuit #2 to perform error correction processing on the output data #2 of the correction processing circuit #1. As in error correction processing circuit #1, error correction is performed on bits (or symbols) among bit (or symbol) candidates to be error-corrected that have smaller likelihood information values than other candidate bits (or symbols). . Whether or not to perform error correction can be determined by selecting a predetermined number of bits (or symbols) in descending order of likelihood information values, or by selecting bits (or symbols) whose likelihood information values are smaller than a predetermined threshold. There are various possible methods such as the selection of The error correction processing circuit #2 does not perform iterative decoding.

The error correction processing circuit #2 updates the likelihood information of the corrected bit (or symbol), deletes the likelihood information corresponding to the redundant bit, and outputs error-corrected likelihood information #2, Delete redundant bits from the corrected data #2 and output data #3.

The likelihood calculation circuit #3 is supplied with the corrected data #3 of the correction processing circuit #2 and data obtained by removing the PAD data from the corrected likelihood information #2 (LLR). The likelihood calculation circuit #3 calculates likelihood information #3 (LLR) for each bit (or symbol) of the received signal. Here, the log-likelihood ratio is composed of N3 bits. The likelihood calculation circuit #3 generates likelihood information #3 by performing a process of subtracting one bit from the least significant bit of the corrected likelihood information #2.

The error correction processing circuit #3 uses the likelihood information #3 supplied from the likelihood calculation circuit #3 to perform error correction processing on the output data #3 of the correction processing circuit #2. Similar to the error correction processing circuit #1 and error correction processing circuit #2, of the bit (or symbol) candidates to be error-corrected, bits (or symbols) whose likelihood information values are smaller than other candidate bits (or symbols) ) is corrected. The error correction processing circuit #3 does not perform iterative decoding.

<Operation of Error Correction Encoding Method>
FIG. 7 is a flowchart for explaining the encoding operation of the error correction method according to the embodiment of the present invention. The encoding operation of the present embodiment is performed in an error correcting encoder 10 having redundant bit adding circuit #3, redundant bit adding circuit #2, and redundant bit adding circuit #1.

When transmission data is input to the error correction coding apparatus 10 (step S1-1), redundant bits are added in the redundant bit adding circuit #3 (step S1-2).

PAD is added to the output data of redundant bit adding circuit #3 (step S1-3), and redundant bits are added in redundant bit adding circuit #2 (step S1-4).

The output data of redundant bit adding circuit #2 is distributed as data for X polarized wave and Y polarized wave (step S1-5). It is added to the data (step S1-6).

The data added with redundant bits in the redundant bit addition circuit #1 is output as XI/XQ/YI/YQ data (step S1-7).

<Operation of Error Correction Method>
FIG. 8 is a flowchart for explaining the error correction operation of the error correction method according to the embodiment of the present invention. The error correction operation of this embodiment includes a likelihood calculation circuit #1, an error correction processing circuit #1, a likelihood calculation circuit #2, an error correction processing circuit #2, a likelihood calculation circuit #3, and an error correction processing circuit #. 3 in the error correction device 20.

When the received signal XI/XQ/YI/YQ is supplied from the optical receiver module 400 to the error correction device 20 (step S2-1), the likelihood calculation circuit #1 calculates data of the X polarized wave/Y polarized wave. Likelihood information #1 is calculated for each bit (or symbol) of (step S2-2).

The error correction processing circuit #1 uses the likelihood information #1 supplied from the likelihood calculation circuit #1 to perform error correction processing on the data #1 of X polarization/Y polarization (step S2- 3).

The likelihood calculation circuit #2 combines the data for the X polarization and the data for the Y polarization, and supplies the corrected data #2 and the corrected likelihood information #1 of the error correction processing circuit #1. (step S2-4), and likelihood information #2 is created by a process of subtracting one bit from the least significant bit of the corrected likelihood information #1 (step S2-5).

The error correction processing circuit #2 uses the likelihood information #2 supplied from the likelihood calculation circuit #2 to perform error correction processing on the output data #2 of the correction processing circuit #1 (step S2-6). ).

The likelihood calculation circuit #3 is supplied with the corrected data #3 of the correction processing circuit #2 and the data obtained by removing the PAD data from the corrected likelihood information #2 (step S2-7). Likelihood information #3 is created by a process of subtracting one bit from the least significant bit of likelihood information #2 (step S2-8).

The error correction processing circuit #3 uses the likelihood information #3 supplied from the likelihood calculation circuit #3 to perform error correction processing on the output data #3 of the correction processing circuit #2 (step S2-9). , the received data is output (step S2-10).

<Effects of the embodiment of the present invention>
According to the present embodiment, although the circuit size is reduced by reducing the number of redundant bits, the error correction capability is improved if the error correction is performed in three or more stages. can be suppressed. In addition, since the number of bits of likelihood information in the error correction process at the final stage can be reduced to about 1 bit, it is possible to suppress deterioration in error correction capability while reducing the circuit scale.

<Relationship between Redundancy and Number of Bits of Likelihood Information and Circuit Scale>
The larger the number of bits of the likelihood value, the higher the correction capability.

As for the number of bits of likelihood information, a large number of bits is required when there are many bits that are estimated to be likely to be erroneous. Therefore, it is possible to specify a bit with a high possibility of being erroneous with likelihood information having a smaller number of bits in the error correction in the latter stage than in the error correction in the former stage.

Also, since the number of bits of the likelihood information in the previous stage can express many bits that are highly likely to be erroneous, for example, the data #1 using the likelihood information #1 in the first stage has a redundancy of about 10%. However, since the data #3 that uses the likelihood information #3 in the final stage can only express a small number of bits, a code with a low correction capability with a redundancy of about 1% is used for the calculation and the result. better balance.

When three-stage soft-decision error correction processing is performed as in the present embodiment, the redundancies of error correction processing circuits #1, #2, and #3 are respectively set as a combination of redundancies in three-stage error correction processing. A configuration of approximately 10%, 4%, and 1% will be described as an example. This is 3 stages such as 10% + 4% + 1% redundancy where the total redundancy is about the same (about 15%) as compared to the case of only one stage (one type) of error correction with 15% redundancy. This is based on the fact that the performance of the error correction processing is better when the error correction is performed with the configuration (three different types).

In addition, since multiple stages of error correction processing are performed during decoding, it is likely that there are fewer errors in the latter stage than in the previous stage. The combined configuration can improve the overall error correction performance. From these, the combination of redundancy and likelihood value is 10% redundancy (N1 = 3 bits of likelihood information #1), 4% redundancy (N2 = 2 bits of likelihood information #2), 1 redundancy A combination of % (N3=1 bit of likelihood information #3) can be configured as an example of conditions for good error correction performance.

If the number of bits of the likelihood information is reduced by one bit, the maximum value of the likelihood value is halved. Efficiency of using the likelihood information can be increased by using a simple error correction circuit (setting redundancy, etc.). Therefore, the aforementioned example of combination of redundancy and likelihood value (redundancy 10%, 4%, 1%, likelihood information bit number 3, 2, 1) is one of the conditions for increasing the utilization efficiency of likelihood information. It is an example.

According to simulation results, when the number of bits of likelihood information is set to 3, 2, and 1, the performance is maintained at approximately the same level as when the number of bits of likelihood information is set to 3, 3, and 3. It was confirmed that By arranging a plurality of error correction processes in descending order of capability as in the present embodiment, high performance is maintained even when the number of bits of likelihood information is changed from 3 to 2 to 1 in order from the previous stage.

On the other hand, regarding the circuit scale, when the number of bits of likelihood information is reduced from the preceding stage to the succeeding stage (3→2→1), it is sufficient to simply delete the information for the lower bits. no extra circuitry is required. Furthermore, when the number of bits of likelihood information is 2 bits, the circuit scale is halved when the number of bits of likelihood information is 3 bits, and when the number of bits of likelihood information is 1 bit, the circuit scale is reduced. Estimated to be about 1/4.

For example, when the number of bits of likelihood information is changed from 3 bits to 3 bits to 3 bits in three stages of soft decision processing, when the number of bits of likelihood information is changed from 3 bits to 2 bits to 1 bit, the circuit The scale is 1.75/3=0.58 times, and the effect of reducing the circuit scale by 40% or more can be obtained without deteriorating the performance of error correction.

In order to reduce the number of bits of likelihood information without lowering the total correction capability, it is necessary to adjust the correction capability (redundancy) for each error correction process. If there are many errors, the correction capability can be improved by increasing the number of bits of likelihood information. Increasing the number of bits may not improve the correction capability. In the present embodiment, since most of the errors are corrected in the error correction of the first stage, the number of bits of the likelihood information is reduced in the error correction of the latter stage because the number of errors is small. be able to.

INDUSTRIAL APPLICABILITY The present invention can be used as an error correction device and a communication device in optical communication or the like.

DESCRIPTION OF SYMBOLS 100... Transmission signal processing apparatus 200... Reception signal processing apparatus 300... Optical transmission module 400... Optical reception module 10... Error correction coding apparatus 11, 12, 13... Redundant bit addition circuit 20... Error correction apparatus , 21, 22, 23 ... likelihood calculation circuits, 31, 32, 33 ... error correction processing circuits.

Claims (8)

Three or more stages of error correction processing circuits that perform soft-decision error correction processing based on likelihood information, and three or more stages of likelihood calculation circuits that supply the likelihood information to the error correction processing circuits,
The three or more stages of error correction processing circuits are arranged in descending order of correction capability, and at least one of the error correction processing circuits is configured not to perform iterative decoding processing,
At least one of the likelihood calculation circuits in the second and subsequent stages uses the first likelihood information updated by the correction processing of the error correction processing circuit in the previous stage to calculate the output bit number of the first likelihood information. an error correction device configured to calculate second likelihood information with a smaller number of bits and to supply said second likelihood information to said error correction processing circuit arranged in a subsequent stage. At least one of the error likelihood calculation circuits in the second and subsequent stages calculates the second likelihood information by deleting a predetermined number of bits of information from the lower bits of the first likelihood information. 1. The error correction device according to 1. 3. The error correction processing circuit determines a bit or symbol to be corrected based on the magnitude of the second likelihood information supplied from the likelihood calculation circuit arranged in the previous stage. The error correction device described in . The error correction processing circuit is
4. The error correction device according to claim 3, wherein a predetermined number of bits or symbols are selected in ascending order of the likelihood information value to determine the bits or symbols to be corrected. The error correction processing circuit is
4. The error correction device according to claim 3, wherein a bit or symbol whose likelihood information value is smaller than a predetermined threshold is selected to determine a bit or symbol to be corrected. Three stages of the error correction processing circuit and three stages of the likelihood calculation circuit arranged in front of each of the error correction processing circuits,
The number of bits of likelihood information supplied to the error correction processing circuit of the first stage is 3 bits,
The number of bits of likelihood information supplied to the second-stage error correction processing circuit is 2 bits,
The number of bits of likelihood information supplied to the third-stage error correction processing circuit is 1 bit,
The error correction device according to any one of claims 1 to 5. An error correction method in an error correction device comprising three or more stages of error correction processing circuits for performing soft-decision error correction processing based on likelihood information, and a likelihood calculation circuit that supplies the likelihood information to the error correction processing circuits. and
The three or more stages of error correction processing circuits are arranged in descending order of correction capability, and at least one of the error correction processing circuits is configured not to perform iterative decoding processing,
At least one of the likelihood calculation circuits in the second and subsequent stages uses the first likelihood information updated by the correction processing of the error correction processing circuit in the previous stage to calculate the output bit number of the first likelihood information. calculating second likelihood information with a smaller number of bits, and supplying said second likelihood information to said error correction processing circuit arranged in a subsequent stage. A communication device comprising the error correction device according to any one of claims 1 to 6.

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