JP4202161B2 - Encoding device and decoding device - Google Patents

Description

ここで、Ｃ_ｊ ^１は第ｋ位置のビットが１である符号語候補であり、Ｃ_ｊ ^０は第ｋ位置のビットが０である符号語候補であり、ｐ（Ｙ｜Ｃ）はガウスの遷移確率である。
【００５９】
ターボ積符号の第ｋ番チャネルの値ｒ_ｋは、復号器が対数尤度比Ｌ_ｋを算出する間、遅延線で遅延させられた後、復号器が算出した対数尤度比Ｌ_ｋから減算器により差し引かれる。この減算結果には、最適な重み係数が乗算器により乗算される。この乗算結果は、次の段階（第ｍ＋１段階）の復号器の復号対象データｗ^{（ｍ＋１）} _ｋであり、第ｍ＋１段階の復号器の前段では、ターボ積符号の第ｋ番のチャネル値ｒ_ｋを第ｍ＋１段階の復号対象データｗ^{（ｍ＋１）} _ｋに加算器により加えて、合計値である軟入力値ｙ_ｋを得る。このようにして、ある段階の復号器の復号結果に基づいて、次の段階の復号器が軟判定復号を行うという繰り返し復号が実現される。そして、最終段階の復号器が算出した対数尤度比Ｌ_ｋから復号装置に入力された情報系列が推定される。
【００６０】
上記の繰り返し復号装置は、実施の形態１から実施の形態３のいずれの復号装置の繰り返し復号部Ｂとして利用してもよい。つまり、実施の形態１から実施の形態３の各ＢＣＨ復号回路１１〜１６を上記の各段階のＳＩＳＯ復号器で置換し、上記の加算器、減算器、遅延線および乗算器を各復号器に付随させてもよい。繰り返し復号部Ｂの軟判定復号結果に基づいて、ＲＳ復号回路１７は硬判定復号を行い、その復号結果を最終的な誤り訂正結果すなわち推定結果として出力端子１８に出力する。このように、ＢＣＨ積符号の繰り返し復号を軟入力・軟出力で行うことによって、より訂正能力を強化することが可能である。
【００６１】
また、この実施の形態４の繰り返し復号部Ｂは、繰り返し復号の途中までは軟判定復号し、この軟判定復号結果に対して最終的に硬判定復号するのでもよい。具体的には、例えば、繰り返し復号部Ｂ中のＢＣＨ復号回路１１〜１４は上述のＳＩＳＯ復号器とし、最終段階およびその付近の段階のＢＣＨ復号回路１５，１６は簡易な構成の硬判定復号器とし、ＢＣＨ復号回路１５，１６では、水平方向ＢＣＨ復号回路１４の軟判定復号結果に基づいて情報系列を硬判定で復号するようにしてもよい。ただし、どの段階まで軟判定復号し、どこから硬判定復号するかは任意であり、例えばＢＣＨ復号回路１１〜１５は上述のＳＩＳＯ復号器とし、最終段階のＢＣＨ復号回路１６のみは硬判定復号器としてもよい。
【００６２】
このように最終段階（および場合によりその付近）のＢＣＨ復号回路を硬判定復号器とすることにより、軟判定復号での残留ランダム誤りの個数を明確に硬判定復号器で把握することが可能である。このランダム誤りの個数はＲＳ復号回路１７に供給され、ＲＳ復号回路１７はランダム誤りの個数を参照して、より精確に誤り訂正することが可能である。
【００６３】
実施の形態５．
実施の形態３では、繰り返し復号部Ｂの軟判定復号結果に基づいて、ＲＳ復号回路１７は硬判定復号を行い、ＲＳ復号回路１７の硬判定復号結果を最終的な誤り訂正結果すなわち推定結果として出力端子１８に出力する。これに対して、以下に述べる実施の形態５では、ＲＳ復号回路１７の誤り訂正結果または誤り検出結果に基づいて、繰り返し復号部Ｂの軟判定復号結果を修正して、再度軟判定復号する。
【００６４】
図１１は、この発明の実施の形態５に係る復号装置を示す。この復号装置は、実施の形態１に係る復号装置（図３）と同様の構成要素に加えて、軟判定更新回路４０と第２の繰り返し復号部Ｂ２を備える。図１１では、図５と共通する構成要素を示すために同一の符号を使用し、説明を簡略化する。この復号装置は、実施の形態１に係る符号化装置（図２）によるＢＣＨ積符号の伝送データフォーマットを復号して誤り訂正する。この実施の形態においては、繰り返し復号部Ｂが実施の形態４に関連して上述したように軟判定復号結果を出力する。一方、ＲＳ復号部１７は、繰り返し復号部Ｂの軟判定復号結果に対して硬判定復号により誤り訂正または誤り検出を施すようになっているが、ＲＳ復号回路１７の出力結果は最終的な誤り訂正結果として出力されるのではない。
【００６５】
繰り返し復号部Ｂの軟判定復号結果およびＲＳ復号回路１７による誤り訂正数または誤り検出状態は、軟判定更新回路４０に供給される。軟判定更新回路４０は、ＲＳ復号回路１７による誤り訂正数または誤り検出状態に基づいて繰り返し復号部Ｂの軟判定復号結果を修正する。軟判定更新回路４０により修正された軟判定復号結果は、第２の繰り返し復号部Ｂ２に供給される。
【００６６】
第２の繰り返し復号部Ｂ２は、繰り返し復号部Ｂと同様に、交互に配置された垂直方向ＢＣＨ復号回路４１，４３，４５と水平方向ＢＣＨ復号回路４２，４４，４６を備える。第２の繰り返し復号部Ｂ２の復号回路４１〜４６は、繰り返し復号部Ｂの復号回路１１〜１６と同様に、垂直方向または水平方向のＢＣＨ符号に対応する復号形式で情報系列を復号することが可能であり、さらに実施の形態４の繰り返し復号部Ｂの復号回路１１〜１６と同様に、軟判定復号することが可能である。従って、第２の繰り返し復号部Ｂ２は、繰り返し復号部Ｂと同様に、軟判定による繰り返し復号が可能である。ただし、第２の繰り返し復号部Ｂ２は、繰り返し復号の途中までは軟判定復号し、この軟判定復号結果に対して最終的に硬判定復号するのでもよい。
【００６７】
この実施の形態によれば、ＲＳ復号回路１７の誤り訂正数または誤り検出状態に基づいて軟判定復号結果を修正し、修正された軟判定復号結果を、再度第２の繰り返し復号部Ｂ２によって軟判定による繰り返し復号の対象とすることが可能である。以上のようにして、軟判定復号の精度を高めることが可能である。第２の繰り返し復号部Ｂ２の復号結果は、最終的な誤り訂正結果すなわち推定結果として出力端子１８に出力してもよいし、図示のように再度ＲＳ復号回路４７に供給してＲＳ符号の復号法による誤り訂正を施すようにしてもよい。
【００６８】
なお、この実施の形態５の復号装置は、実施の形態１に係る復号装置を修正したものであるが、実施の形態２または実施の形態３に係る復号装置（図８）を同様に修正してもよい。
【００６９】
以上、この発明をその好適な実施の形態を参照しながら詳細に図示して説明したが、請求の範囲に記載されたこの発明の範囲内で、形式および細部に関する様々な変更が可能であることは当業者であれば理解できることだろう。かかる変更、代替、修正もこの発明の範囲に含まれる。
【００７０】
例えば、上記の実施の形態では、伝送データフォーマットでは、ＢＣＨ符号を用いた積符号が使用されているが、他の形式の繰り返し復号可能な符号を使用してもよい。例えば、ユ・コウ（Yu Kou）、外２名、「有限幾何学に基づく低密度パリティ検査符号：再発見と新結果」（"Low-Density Parity-Check Codes Based on Finite Geometries: A Rediscovery and New Results"）、「情報理論に関するＩＥＥＥ報告書」（"IEEE Transactions on Information Theory"）、（米国）、電気電子技術者協会（Institute of Electrical and Electronics Engineers)、２００１年１１月、第４７巻、第７号、ＯＦＣ２００２、ｐ．２７１１−２７３６に開示された各種の低密度パリティ検査符号（low-density parity-check codes）のうち組織符号に分類できる符号を用いて符号化・復号するように、全ての実施の形態を修正してもよい。また、ＲＳ符号を用いた積符号、その他のブロック符号を用いた積符号、およびＲＳ符号その他のブロック符号を用いた連接符号を用いるように、全ての実施の形態を修正してもよい。
【００７１】
また、上記の実施の形態では、復号装置の繰り返し復号部Ｂおよび第２の繰り返し復号部Ｂ２に三つの垂直方向ＢＣＨ復号回路と三つの水平方向ＢＣＨ復号回路１２，１４，１６が設けられているが、垂直方向ＢＣＨ復号回路および水平方向ＢＣＨ復号回路の各々の個数は２つ以上であればいくつでもよい。
また、上記の実施の形態では、復号装置の繰り返し復号部Ｂおよび第２の繰り返し復号部Ｂ２において、多数の復号回路が直列に配置されているが、復号回路の復号結果を他の復号回路に供給する形式にして、復号回路の個数を削減してもよい。
【００７２】
また、上記の実施の形態では、復号装置での誤り訂正の処理は必ず最終段階の復号回路（例えばＲＳ復号回路１７）に進むが、繰り返し復号の途中の段階で復号結果に誤りが含まれていないと確認できれば、誤り訂正処理を終了して、その段階での復号結果を最終的な誤り訂正結果として出力してもよい。
また、上記の実施の形態では、符号化、復号、インタリーブ、デインタリーブといった各種の処理を回路で実現するが、同様の処理を実現するソフトウエアを利用してコンピュータを用いることも可能である。
【００７３】
【発明の効果】
以上のように、この発明によれば、元の情報記号を規則的に分割して得られる複数の情報部分の各々にＲＳ（リード・ソロモン）符号化を施すとともに、各情報部分に対応する複数のＲＳ検査記号を生成するＲＳ検査記号生成部と、元の情報記号とＲＳ検査記号とを有する情報配列に複数のブロック符号化形式による誤り訂正符号化を施すとともに、複数のブロック符号化形式に対応する複数の形式の検査記号を生成する組み合わせ符号化部と、元の情報記号と、ＲＳ検査記号が複数のブロック符号化形式により誤り訂正符号化されて生成されたＲＳ検査記号と、複数の形式の検査記号とを出力する出力部と、元の情報記号を組み合わせ符号化部に供給されるべき並びの順序と異なる順序に並べて、ＲＳ検査記号生成部に供給するインタリーブ部とを備え、組み合わせ符号化部による誤り訂正符号化は繰り返し復号が可能な形式であり、繰り返し復号による誤り訂正能力よりもＲＳ検査記号による復号の誤り訂正能力が高くされているので、冗長度が小さい符号を用いて高い誤り訂正能力で効率的に誤り訂正することが可能となる。特に、組み合わせ符号化部は、複数のブロック符号化形式による誤り訂正符号化を施し、ＲＳ符号化もブロック符号化であるので、畳込み符号に比較して、符号の構成が簡単であり、並列処理などの迅速な処理が行いやすく、かつ符号化装置および復号装置を簡易に構成することが可能である。
【図面の簡単な説明】
【図１】 この発明の実施の形態１に係る符号化装置および復号装置で使用される２次元に配列された伝送データフォーマットを示す模式図である。
【図２】 図１の伝送データフォーマットを生成する実施の形態１に係る符号化装置を示すブロック図である。
【図３】 図１の伝送データフォーマットから元の情報記号を推定する実施の形態１に係る復号装置を示すブロック図である。
【図４】 図１の伝送データフォーマット上に存在することがある格子状に位置する複数の誤りを示す模式図である。
【図５】 この発明の実施の形態２に係る符号化装置を示すブロック図である。
【図６】 この発明の実施の形態２に係る符号化装置および復号装置で使用される２次元に配列された伝送データフォーマットを示す模式図である。
【図７】 実施の形態２に係る符号化装置および復号装置の動作を示す模式図である。
【図８】 この発明の実施の形態２に係る復号装置を示すブロック図である。
【図９】 この発明の実施の形態３に係る符号化装置および復号装置で使用される２次元に配列された伝送データフォーマットを示す模式図である。
【図１０】 実施の形態３に係る符号化装置および復号装置の動作を示す模式図である。
【図１１】 この発明の実施の形態５に係る復号装置を示すブロック図である。
【符号の説明】
１ ユーザデータ（元の情報記号）、２ 水平方向ＢＣＨ検査記号部、３ 垂直方向ＢＣＨ検査記号部、４ ＲＳ検査記号部、５ 入力端子、６ ＲＳ符号化回路、７ 水平方向ＢＣＨ符号化回路、８ 垂直方向ＢＣＨ符号化回路、９ 出力端子、１０ 入力端子、１１，１３，１５，４１，４３，４５ 垂直方向ＢＣＨ復号回路、１２，１４，１６，４２，４４，４６ 水平方向ＢＣＨ復号回路、１７ ＲＳ復号回路、１８ 出力端子、２０ 格子状に位置する複数の誤り、２１ インタリーブ回路、２２ デインタリーブ回路、３１ インタリーブ回路、３２ デインタリーブ回路、４０ 軟判定更新回路、４７ ＲＳ復号回路、Ａ 組み合わせ符号化部、Ｂ 繰り返し復号部、Ｂ２ 第２の繰り返し復号部。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an encoding device and a decoding device effective for error correction in digital transmission.
[0002]
[Prior art]
In order to correct an error in a digital transmission apparatus, a product code or a concatenated code in which block codes are two-dimensionally arranged is often used (for example, see Non-Patent Document 1).
For example, in product code encoding, each row of user data (information symbols) arranged in two dimensions is encoded with a horizontal linear code and a horizontal check symbol is generated, and then user data and Each column of check symbols in the horizontal direction is encoded with a vertical linear code and a check symbol in the vertical direction is generated. The minimum distance of the product code obtained by such encoding is the product of the minimum distance of the horizontal linear code and the minimum distance of the vertical linear code. Therefore, by combining linear codes with a small minimum distance, it is possible to obtain a product code with a large minimum distance as a result, thereby improving the error correction capability.
[0003]
In decoding of the product code, error correction is performed in the vertical direction based on the check symbol in the vertical direction, and error correction is performed in the horizontal direction on the basis of the check symbol in the horizontal direction. In the error correction in the subsequent horizontal direction, erasure correction can also be performed using detection information such that correction cannot be performed in the vertical error correction in the previous stage.
[0004]
Furthermore, the horizontal error correction result is corrected again in the vertical direction based on the vertical check symbol, and the error is corrected in the horizontal direction based on the horizontal check symbol. Iterative decoding is also already known in which residual errors are reduced by correction.
[0005]
On the other hand, as a technique similar to a product code, a combination of horizontal coding and diagonal coding has also been proposed (see, for example, Patent Document 1). In addition, the transmission source performs convolution encoding on the codes encoded in a plurality of different directions as described above, and the transmission destination performs maximum likelihood decoding using the convolutional code, and further performs the maximum likelihood decoding result. A method of performing decoding has also been proposed (see, for example, Patent Document 1).
[0006]
Furthermore, a technique is disclosed in which error correction coding is performed only on important data so as to have stronger error correction capability than unimportant data (see, for example, Patent Document 2). In the technique described in Patent Document 2, important data and unimportant data are separated, important data is encoded with an inner code, and the encoded result and unimportant data are combined and further encoded with an outer code. Get the sign.
[0007]
[Patent Document 1]
JP-A-1-228327
[Patent Document 2]
JP-A-7-162801
[Non-Patent Document 1]
Hideki Imai, "Code Theory", 4th edition, The Institute of Electronics, Information and Communication Engineers, June 1990, p. 229-245
[0008]
[Problems to be solved by the invention]
However, in the method using the general product code described in Non-Patent Document 1, if there are a plurality of errors located in a lattice pattern in the product code arranged in two dimensions, correction of these errors is performed. Is difficult. Even if such a product code having a lattice error is repeatedly decoded, if the decoding result is arranged two-dimensionally, there is a tendency that an error located in a lattice shape also occurs on the decoding result.
[0009]
In the technique described in Patent Document 1, a convolutional code is used in order to obtain a high error correction capability. However, the use of the convolutional code inevitably increases the length of the code block, which makes it long for data transmission and decoding. It takes time. Further, maximum likelihood decoding for the complex convolutional code described in Patent Document 1 requires a very large amount of calculation and storage, and is extremely difficult.
[0010]
With the technique described in Patent Document 2, it is possible for an decoder to perform error correction on important data with higher reliability than other data. However, it cannot be said that the error correction capability by the outer code is high when the error correction at the time of decoding the important data by the inner code fails, although the redundancy becomes higher with the concatenated encoding.
[0011]
The present invention has been made in order to solve the above-described problems, and provides an encoding device that can generate a code with a low redundancy that can be efficiently corrected by a decoding device with high error correction capability. The purpose is to obtain.
[0012]
Another object of the present invention is to provide a decoding apparatus capable of efficiently correcting errors with high error correction capability using a code with low redundancy. And
[0013]
[Means for Solving the Problems]
  The encoding apparatus according to the present invention performs RS (Reed-Solomon) encoding on each of a plurality of information parts obtained by regularly dividing the original information symbol, and a plurality of RSs corresponding to each information part. An RS check symbol generation unit for generating a check symbol, and an information array having an original information symbol and an RS check symbol are subjected to error correction encoding using a plurality of block encoding formats, and correspond to a plurality of block encoding formats A combination coding unit that generates a plurality of check symbols, an original information symbol, an RS check symbol generated by error correction coding of the RS check symbol in a plurality of block coding formats, and a plurality of formats An output unit for outputting a test symbol;An interleaving unit that arranges the original information symbols in an order different from the order of the sequences to be supplied to the combination encoding unit and supplies the information symbols to the RS check symbol generation unit;The error correction coding by the combination coding unit is a format that enables iterative decoding, and the error correction capability of decoding by RS check symbols is higher than the error correction capability by iterative decoding.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 shows a two-dimensionally arranged transmission data format used in the encoding apparatus and decoding apparatus according to Embodiment 1 of the present invention. As shown in FIG. 1, this transmission data format includes user data (original information symbol) 1, horizontal BCH (Bose-Chaudhuri-Hocquenghem) check symbol portion 2, vertical BCH check symbol portion 3, RS (Reed-Solomon) It has an inspection symbol part 4.
[0015]
FIG. 2 shows an encoding apparatus according to Embodiment 1 that generates the transmission data format of FIG. As shown in FIG. 2, the encoding device includes an input terminal 5, an RS encoding circuit (RS check symbol generation unit) 6, a combination encoding unit A, and an output terminal (output unit) 9. The combination encoding unit A includes a horizontal BCH encoding circuit 7 and a vertical BCH encoding circuit 8.
[0016]
User data 1 which is an original information symbol is input to the input terminal 5, and the user data 1 is supplied from the input terminal 5 to the RS encoding circuit 6. As shown in FIG. 1, the user data 1 has a horizontal symbol number (number of columns) of k.₁And the number of vertical symbols (number of rows) is k₂Can be understood as a two-dimensional array. In this embodiment, it is assumed that the order of regular data is arranged along a vertical column and proceeds to the beginning of the next column after the end of each column. Is not intended to limit. From the input terminal 5, k constituting the information portion of each column (vertical direction)₂K constituting the information part of the next column with a time interval after the bits are supplied to the RS encoding circuit 6 at once₂The number of bits may be supplied to the RS encoding circuit 6 at a time. Or the bit which comprises the information part of each row | line | column may be supplied to RS encoding circuit 6 for every one time or every several time intervals.
[0017]
The RS encoding circuit 6 constitutes the information portion of each row of the user data 1 when it is assumed that the RS encoding circuit 6 is arranged in two dimensions.₁The bits are read in the horizontal direction (horizontal processing direction in FIG. 1), and RS coding is performed on the information portion of each row, and an RS check symbol corresponding to the information portion of each row is generated. Therefore, k equal to the number of rows₂RS check symbols are obtained.
[0018]
The original user data 1 is also supplied to the horizontal BCH encoding circuit 7. Thereafter, the RS check symbol generated by the RS encoding circuit 6 is also supplied to the horizontal BCH encoding circuit 7. The horizontal BCH encoding circuit 7 configures an information portion of one row in a format in which an information portion of each row (horizontal direction) of the user data 1 is associated with an RS check symbol generated based on the information portion. k₁A row consisting of a number of bits and an RS check symbol is read in the horizontal direction (horizontal processing direction in FIG. 1) as one encoding target, and BCH encoding in the horizontal direction is applied to this row, and the horizontal corresponding to this row is also read. A direction BCH check symbol is generated. Therefore, the horizontal BCH encoding circuit 7₂Rows, k₂K using the BCH codes and resulting from the encoding₂Horizontal BCH check symbols (length is n₁-K₁-K₃Is). The horizontal direction BCH check symbol part 2 has these k₂A set of horizontal BCH check symbols.
[0019]
The horizontal BCH encoding circuit 7 includes the original user data 1 and the RS check symbol code (length k) BCH encoded in the horizontal direction.₃× Number of rows k₂) Is supplied to the vertical BCH encoding circuit 8 in accordance with the order of regular data. Thereafter, the horizontal BCH check symbol generated by the horizontal BCH encoding circuit 7 is also supplied to the vertical BCH encoding circuit 8 in accordance with the order of regular data arrangement. The vertical BCH encoding circuit 8 performs k of each column.₂One bit is read in the vertical direction (vertical processing direction in FIG. 1) as one encoding target, and BCH encoding in the vertical direction is performed on this column, and a vertical BCH check symbol corresponding to this column is generated. . Therefore, the vertical direction BCH encoding circuit 8 has n₁N columns₁N using the BCH codes, and n resulting from the encoding₁Vertical BCH check symbols (length is n₂-K₂Is). The vertical direction BCH check symbol part 3 has these n₁A set of vertical BCH check symbols.
[0020]
In this way, the horizontal BCH check symbol part 2, the vertical BCH check symbol part 3 and the RS check symbol part 4 shown in FIG. 1 are obtained. Among these, the RS check symbol unit 4 is a set of codes generated by performing BCH encoding (that is, BCH product encoding) in the horizontal direction and the vertical direction on the RS check symbol generated by the RS encoding circuit 6. Also, since the horizontal BCH check symbol is also BCH encoded in the vertical direction, the horizontal BCH check symbol portion 2 shown in FIG. 1 is actually a set of horizontal BCH check symbols that are BCH encoded in the vertical direction. .
[0021]
The vertical BCH encoding circuit 8 outputs the original user data 1, the RS check symbol part 4, the horizontal BCH check symbol part 2, and the vertical BCH check symbol part 3 that are not encoded at all to the output terminal 9. This output also proceeds along the vertical columns in accordance with the above-described regular data arrangement sequence, and proceeds to the beginning of the next column after the end of each column. Accordingly, each column of the user data 1 and each column of the vertical BCH check symbol portion 3 corresponding to the column are output first, and then each column of the RS check symbol portion 4 and the vertical direction BCH check symbol corresponding to the column. Each column of the unit 3 is output, and finally each column of the horizontal BCH check symbol unit 2 and each column of the vertical BCH check symbol unit 3 corresponding to the column are output. Thus, the transmission data format of FIG. 1 is realized, and the output terminal 9 also outputs the bits constituting the transmission data format to the outside according to the above order.
[0022]
This transmission data format is a product code using a BCH code, and further improves the error correction capability of user data by adding an RS code check symbol to user data 1. Therefore, decoding can be performed based on the vertical direction BCH check symbol unit 3, and then decoding can be performed based on the horizontal direction BCH check symbol unit 2 using the decoding result. Thereafter, it is possible to perform iterative decoding in which the decoding in one format is continued while using the decoding result in the other format in the vertical direction and the horizontal direction. After decoding based on the horizontal BCH check symbol part 2, decoding based on the RS check symbol can improve error correction capability.
[0023]
That is, with regard to this transmission data format, the error correction capability of decoding using RS check symbols is higher than the error correction capability of iterative decoding. Specifically, this implementation is performed so that the error correction capability of decoding based on the RS check symbol is higher than the error correction capability of decoding performed immediately before (for example, decoding based on the horizontal BCH check symbol unit 2). The minimum distance guaranteed by the RS code selected for the form is greater than the minimum distance guaranteed by the BCH code (eg, horizontal) used in the previous decoding. For this reason, as will be described later, the error correction capability is particularly improved with respect to a plurality of errors located in a grid pattern in the user data 1 that is assumed to be two-dimensionally arranged.
[0024]
FIG. 3 shows an example of a decoding apparatus that estimates the original user data 1 from the transmission data format of FIG. As illustrated in FIG. 3, the decoding device includes an input terminal 10 to which the received information series is input, an iterative decoding unit B, an RS decoding circuit 17, and an output terminal 18. The iterative decoding unit B decodes the received information sequence conforming to the transmission data format in a decoding format corresponding to the vertical BCH code used by the encoding device, and the horizontal BCH used by the encoding device. Repeat decoding in a decoding format corresponding to the code. For this purpose, the iterative decoding unit B includes alternately arranged vertical BCH decoding circuits and horizontal BCH decoding circuits, and the decoding result of the one-way decoding circuit is input to the decoding circuit in the other direction. It has become so.
[0025]
Each of the vertical BCH decoding circuits 11, 13, and 15 performs error correction of the information sequence based on the vertical BCH check symbol unit 3, and each of the horizontal BCH decoding circuits 12, 14, and 16 Based on the symbol part 2, error correction of the information series is performed. The decoding result output from the horizontal BCH decoding circuit 16 at the final stage of the iterative decoding unit B is input to the RS decoding circuit 17. The RS decoding circuit 17 performs error correction by the decoding method of the RS code on the decoding result of the iterative decoding unit B based on the RS check symbol unit 4, and the error correction result (corresponding to the user data 1). The final error correction result, that is, the estimation result is output to the output terminal 18.
[0026]
First, from the input terminal 10, n constituting the information portion of each column in the transmission data format of FIG.₂Bits are input to the first vertical BCH decoding circuit 11 at a time, and the vertical BCH decoding circuit 11 reads the column in accordance with the vertical processing direction of FIG.₂-K₂Based on the number of vertical BCH check symbols, error correction of the column is performed. The vertical BCH decoding circuit 11 may handle one column at a time, or a plurality of columns may be simultaneously input from the input terminal 10 to the vertical BCH decoding circuit 11 and subjected to error correction by parallel processing. By decoding by the vertical BCH decoding circuit 11, at least a part of errors included in the user data 1, the RS check symbol part 4 and the horizontal BCH check symbol part 2 is corrected. That is, the error bit is replaced with the correct bit in the transmission data format.
[0027]
The result of this error correction, that is, the transmission data format in which the error bits are corrected is supplied from the vertical BCH decoding circuit 11 to the horizontal BCH decoding circuit 12. In this case, n constituting the information part of each row₁Bits are input to the horizontal BCH decoding circuit 12 at a time, and the horizontal BCH decoding circuit 12 reads the column according to the horizontal processing direction of FIG. 1, and based on the horizontal BCH check symbol included in the row, Perform line error correction. The horizontal BCH decoding circuit 12 may handle one row at a time, or a plurality of rows may be simultaneously input from the vertical BCH decoding circuit 11 to the horizontal BCH decoding circuit 12 and error correction may be performed by parallel processing. In the error correction in the horizontal BCH decoding circuit 12, it is possible to perform erasure correction of bits based on the correction status in the vertical BCH decoding circuit 11. When the vertical BCH check symbol part 3 is configured on the same body as the horizontal BCH check symbol part 2, each horizontal row of the vertical BCH check symbol part 3 is also a horizontal BCH code. N at the end₁-K₁-K₃The bits can be regarded as a horizontal BCH check symbol for the row. Therefore, the vertical BCH check symbol unit 3 can be corrected by the horizontal BCH decoding circuit 12 using the horizontal BCH check symbol by the same decoding method as that for other rows.
[0028]
The result of error correction by the horizontal BCH decoding circuit 12, that is, the transmission data format in which error bits are corrected, is similar to the vertical BCH decoding circuit 11 in that the information sequence is errored vertically based on the vertical BCH check symbol unit 3. This is supplied to the vertical BCH decoding circuit 13 to be corrected. There is a possibility that the error remaining in the horizontal BCH decoding circuit 12 can be corrected by correcting the error again in the vertical BCH decoding circuit 13. Further, in the error correction in the vertical BCH decoding circuit 13, it is possible to perform erasure correction of bits based on the correction status in the horizontal BCH decoding circuit 12.
[0029]
In the same manner, the horizontal BCH decoding circuit 14 in the horizontal direction, the vertical BCH decoding circuit 15 in the vertical direction, and the horizontal BCH decoding circuit 16 in the horizontal direction are in error with respect to the error correction result of the preceding decoding circuit. Make corrections. By alternately repeating different types of decoding in this manner, errors that cannot be corrected by a single error correction can be corrected.
[0030]
However, with only the above iterative decoding, it is difficult to correct a plurality of errors 20 located in a lattice shape illustrated in FIG. Here, “located in a grid pattern” means that a plurality of errors existing in one row in a format assumed to be two-dimensionally arranged and a plurality of errors existing in other rows are on the same plurality of columns. Is to exist. The error 20 located in a lattice shape may be included in the transmission data format from the beginning of reception, or may be caused by erroneous correction during the repeated decoding. Even if such a code having the error 20 located in a lattice is repeatedly decoded, a plurality of errors located in a lattice also tend to occur on the decoding result assumed to be arranged in two dimensions. In particular, if there is an error located in a grid pattern in the error correction result output from the last-stage vertical BCH decoding circuit (for example, the circuit 15) in the iterative decoding unit B, the final horizontal BCH decoding is performed. A circuit (for example, the circuit 16) cannot perform erasure correction. In some cases, the number of correctable errors corresponding to the minimum distance guaranteed by the horizontal decoding based on the horizontal BCH check symbol unit 2 is the actual number of errors. Error correction may be impossible.
[0031]
Therefore, in this embodiment, the RS decoding circuit 17 further decodes the decoding result of the iterative decoding unit B. The RS decoding circuit 17 constitutes the information portion of each row of the estimated user data 1₁Bits and the corresponding k₃An RS check symbol consisting of a number of bits is read in the horizontal direction (horizontal processing direction in FIG. 1), and based on these, error estimation of the original user data 1 is further performed.
[0032]
As described above, this implementation is performed so that the error correction capability of decoding based on the RS check symbol is higher than the error correction capability of decoding performed immediately before (for example, decoding based on the horizontal BCH check symbol portion 2). The minimum distance guaranteed by the RS code selected for the form is greater than the minimum distance guaranteed by the BCH code (eg, horizontal) used in the previous decoding. Therefore, even if there are a plurality of errors 20 located in a lattice pattern in the error correction result output from the horizontal BCH decoding circuit (for example, the circuit 16) at the final stage of the iterative decoding unit B, it is guaranteed by the RS code. These errors can be corrected based on a minimum distance.
[0033]
Note that the final horizontal BCH decoding circuit (for example, the circuit 16) of the iterative decoding unit B may perform only error position detection and no error correction. In this case, while verifying the determination of the error position finally detected by the iterative decoding unit B, the RS decoding circuit 17 performs the second-stage vertical BCH decoding circuit (from the last in the iterative decoding unit B ( For example, an error can be corrected by decoding the error correction result output from the circuit 15).
[0034]
As described above, according to the first embodiment, the encoding apparatus performs RS encoding on each of a plurality of information parts obtained by dividing original user data 1 into a plurality of lines, and each information part. RS encoding circuit 6 for generating a plurality of RS check symbols corresponding to, and an error correction using a plurality of BCH encoding formats in an information array in which each information portion and the RS check symbol corresponding thereto are arranged in association with each other Combined encoding section A that performs encoding and generates a plurality of check symbols corresponding to a plurality of BCH encoding formats, and original user data 1 and RS check symbols are error-corrected by a plurality of BCH encoding formats An RS check symbol unit 4 generated by encoding, an output unit that outputs a horizontal BCH check symbol unit 2 and a vertical BCH check symbol unit 3 are provided. The error correction coding by the combination coding unit A is a format that can be iteratively decoded, and the error correction capability of decoding using RS check symbols is higher than the error correction capability of iterative decoding. Since the RS check symbol does not cause a significant increase in redundancy, and the combination coding in a form that can be iteratively decoded does not cause a significant increase in redundancy, the encoding device can generate a code with a small redundancy. . The decoding apparatus corrects errors generated on the transmission path as much as possible by iterative decoding of the iterative decoding unit B, and has a high error correction capability for errors remaining in the correction result, for example, a plurality of errors 20 located in a lattice shape. Since the RS decoding circuit 17 can correct by decoding with the RS check symbol, the decoding apparatus can efficiently correct the error with high error correction capability.
[0035]
The horizontal direction BCH encoding circuit 7 and the horizontal direction BCH decoding circuits 12, 14, 16 and the RS encoding circuit 6 and the RS decoding circuit 17 receive the next column after the information portion of one column (vertical direction) is input. 1 are input, while these process the information portion of each row (horizontal direction) in the horizontal direction, so that a plurality of bit sequences corresponding to the plurality of rows in FIG. It is efficient to design for processing. If designed in this way, bits in one column extending over a plurality of rows are output simultaneously or within a short period from these circuits, so that the subsequent vertical BCH encoding circuit 8 and vertical BCH decoding circuit 11, 13 and 15 can easily pipeline the bits in one column. If designed as described above, it is possible to further contribute to speeding up the processing.
[0036]
Embodiment 2. FIG.
In the first embodiment, the RS encoding circuit 6 and the RS decoding circuit 17 are similar to the horizontal BCH encoding circuit 7 and the horizontal BCH decoding circuits 12, 14, 16 in each row in the horizontal processing direction of FIG. Is read and processed. Accordingly, the individual RS check symbols in the RS check symbol portion 4 are BCH-coded in the horizontal direction together with the information portion of the same row from which they are created, and similarly decoded together. On the other hand, in the second embodiment described below, the RS coding direction is made different from the horizontal BCH coding direction, so that the individual RS check symbols in the transmission data format and the information part in the same row And the error correction capability in decoding is further enhanced.
[0037]
FIG. 5 shows an encoding apparatus according to Embodiment 2 of the present invention. This encoding device includes an interleave circuit 21 and a deinterleave circuit 22 in addition to the same components as those of the encoding device (FIG. 2) according to the first embodiment. In FIG. 5, the same reference numerals are used to indicate the same components as in FIG. 2, and the description will be simplified. The interleave circuit 21 is arranged in the preceding stage of the RS encoding circuit 6 and is different from the normal sequence order (the sequence order input from the input terminal 5) to be supplied to the combination encoding unit A with the original user data. Arranged in order and supplied to the RS encoding circuit 6. The deinterleaving circuit 22 is arranged at the subsequent stage of the RS encoding circuit 6, and the user data rearranged by the interleaving circuit 21 and a plurality of RS check symbols generated by the RS encoding circuit 6 are stored in the deinterleaving circuit 22. Supplied. The deinterleaving circuit 22 returns the user data supplied from the interleaving circuit 21 to the user data 1 in the normal order, and supplies the user data 1 to the horizontal BCH encoding circuit 7 of the combination encoding unit A. Thereafter, the RS check symbol generated by the RS encoding circuit 6 is supplied to the horizontal BCH encoding circuit 7.
[0038]
A specific operation of the encoding apparatus will be described in detail with reference to FIGS. 6 and 7. In FIG. 6, R₁, R₂, R₃, R₄... indicates an RS check symbol (not BCH product encoded) generated by the RS encoding circuit 6. R₁₁, R₁₂, R₁₃, R₁₄... RS check symbol R₁, R₂, R₃, R₄Indicates the bit string required to generate. The length of each bit string may be one or more. Of these bit strings, bit string r₁₁, R₁₂, R₁₃, R₁₄... r_1nAre subject to the same RS encoding and RS check symbol R₁Is used to generate a bit string r₂₁, R₂₂, R₂₃... is the target of other RS coding and RS check symbol R₂Used to generate That is, in this embodiment, in the original user data 1 that is assumed to be two-dimensionally arranged, one check symbol is generated from a plurality of bit strings arranged substantially obliquely. Same RS inspection symbol R₁A bit string r that generates₁₁, R₁₂, R₁₃, R₁₄... r_1nIn the original user data 1 that is assumed to be arranged in two dimensions, the bit string r₁₁, R₁₂, R₁₃, R₁₄... exist in different columns, and adjacent bit strings (for example, bit string r)₁₁, R₁₂) Includes bits in different rows.
[0039]
In this way, the bit string r arranged in a direction different from the horizontal processing direction₁₁, R₁₂, R₁₃, R₁₄... r₂₁, R₂₂, R₂₃From RS inspection symbol R₁, R₂, R₃, R₄.. Are easily generated, the interleave circuit 21 generates a bit string (for example, bit string r) to be subjected to the same RS encoding from the user data 1 in the regular sequence as shown in FIG.₁₁, R₁₂, R₁₃, R₁₄... r_1n) Is repeated, and the user data 1 is rearranged so as to be suitable for encoding by the RS encoding circuit 6. In other words, the same bit string (for example, bit string r) subject to RS encoding₁₁, R₁₂, R₁₃, R₁₄... r_1n) On a line. Then, the RS encoding circuit 6 performs RS encoding on the bit string of each row and also performs an RS check symbol R₁, R₂, R₃, R₄... is generated. In this way, the bit string r₁₁, R₁₂, R₁₃, R₁₄... r_1nTo RS inspection symbol R₁Is generated and the bit string r₂₁, R₂₂, R₂₃... r_2nTo other RS inspection symbol R₂Is generated.
[0040]
The deinterleaving circuit 22 returns the user data rearranged by the interleaving circuit 21 to the normal arrangement order, and the user data 1 in the normal arrangement order is sent to the horizontal BCH encoding circuit 7 of the combination encoding unit A. After that, the RS check symbol generated by the RS encoding circuit 6 is supplied to the horizontal BCH encoding circuit 7.
[0041]
The horizontal BCH encoding circuit 7 receives the information part of each row (horizontal direction) of the user data 1 in the normal sequence received from the deinterleave circuit 22 and the RS check symbol R.₁, R₂, R₃, R₄K constitutes the information part of one line in a format in which ... is associated₁A row consisting of a number of bits and an RS check symbol is read in the horizontal direction (horizontal processing direction in FIG. 6) as one encoding target, and BCH encoding in the horizontal direction is applied to this row, and the horizontal corresponding to this row is also read. A direction BCH check symbol is generated. Therefore, in the original user data 1 that is assumed to be arranged two-dimensionally, a bit string (for example, bit string r) arranged almost diagonally.₁₁, R₁₂, R₁₃, R₁₄... r_1n) Generated from one RS check symbol (for example, RS check symbol R)₁) Are subject to BCH encoding in the horizontal direction along with the information part in the same row.
[0042]
Similarly to the first embodiment, the vertical direction BCH encoding circuit 8 uses the bits in each column (vertical direction) in the format assumed to be two-dimensionally arranged as one encoding target in the vertical direction (see FIG. 6 vertical processing directions), BCH encoding in the vertical direction is applied to this column, and a vertical BCH check symbol corresponding to this column is generated. One RS inspection symbol (for example, RS inspection symbol R₁) Used to create the bit string (eg, bit string r)₁₁, R₁₂, R₁₃, R₁₄... r_1n) Will be on different columns and will contribute to the generation of different vertical BCH check symbols.
[0043]
FIG. 8 shows a decoding apparatus according to the second embodiment. This decoding apparatus includes an interleave circuit 31 and a deinterleave circuit 32 in addition to the same components as those of the decoding apparatus (FIG. 3) according to the first embodiment. In FIG. 8, the same reference numerals are used to indicate the same components as in FIG. 3, and the description will be simplified. The interleave circuit 31 is arranged between the iterative decoding unit B and the RS decoding circuit 17, and arranges information symbols corresponding to the original user data 1 among the decoding results by the iterative decoding unit B in the decoding result by the iterative decoding unit B. These are arranged in an order different from the order of and are supplied to the RS decoding unit 17.
[0044]
Specifically, the information sequence of the decoding result in the format shown in FIG. 6 is supplied from the iterative decoding unit B to the interleave circuit 31. In the information sequence of this decoding result, the RS check symbol R in the previous stage of the BCH product encoding is performed by the horizontal BCH decoding circuits 12, 14, and 16.₁, R₂, R₃, R₄... is estimated. Similar to the interleaving circuit 21 of the above encoding apparatus, as shown in FIG. 7, the interleaving circuit 31 starts from the information symbol (corresponding to the user data 1) in the normal sequence and is subjected to the same RS encoding target bit string ( For example, bit string r₁₁, R₁₂, R₁₃, R₁₄... r_1n) Are repeated, and the information symbols are rearranged so as to be suitable for decoding by the RS decoding circuit 17. That is, a bit string (for example, bit string r) subjected to the same RS encoding.₁₁, R₁₂, R₁₃, R₁₄... r_1n) On a line. Then, the RS decoding circuit 17 performs a bit string (for example, bit string r) in each row.₁₁, R₁₂, R₁₃, R₁₄... r_1n) And RS inspection symbol (for example, RS inspection symbol R)₁) To estimate the error of the bit string.
[0045]
The deinterleave circuit 32 is arranged at the subsequent stage of the RS decoding circuit 17 and returns the information symbols corresponding to the original user data 1 among the decoding results by the RS decoding circuit 17 to the order of arrangement in the decoding results by the iterative decoding unit B. This is output to the output terminal 18 as a final error correction result, that is, an estimation result.
[0046]
As described above, according to the second embodiment, as in the first embodiment, the encoding device can generate a code with a small redundancy, and the decoding device uses the error correction result of the iterative decoding unit B. Error, for example, a plurality of errors 20 located in a lattice pattern can be corrected by the RS decoding circuit 17 by decoding with an RS check symbol having a high error correction capability, so that the decoding apparatus can efficiently perform with a high error correction capability. It is possible to correct errors.
[0047]
Further, according to the second embodiment, the encoding apparatus arranges the original user data 1 in an order different from the order of the sequences to be supplied to the combination encoding unit A, and supplies it to the RS encoding circuit 6. A circuit 21 is provided. Further, the decoding apparatus arranges information symbols corresponding to the original user data 1 among the decoding results obtained by the iterative decoding unit B in an order different from the arrangement order of the decoding results by the iterative decoding unit B, and supplies the information symbols to the RS decoding circuit 17. And a deinterleaving circuit 32 that returns the information symbols corresponding to the original user data 1 among the decoding results obtained by the RS decoding circuit 17 to the order of arrangement in the decoding results obtained by the repeated decoding unit B. Therefore, by making the RS encoding direction different from the encoding direction in the combination encoding unit A (horizontal direction BCH encoding direction in the embodiment), individual RS check symbols in the transmission data format, and this There is a possibility that the error correction capability in decoding can be further enhanced by weakening the correlation with the information part encoded and decoded together with the RS check symbol.
[0048]
This effect will be described in more detail. As shown in FIG. 6, it is assumed that some errors among a plurality of errors 20 located in a lattice form exist in the RS check symbol part 4. In the first embodiment, each RS check symbol in the RS check symbol portion 4 is BCH-coded in the horizontal direction together with the information portion of the same row from which the RS is generated, and similarly decoded together. . Therefore, if there is an error in the same row of the user data 1 and the RS check symbol part 4 at the stage when the decoding apparatus receives the transmission format or in the middle of the iterative decoding part B, there is a possibility that the error cannot be corrected. On the other hand, in Embodiment 2, the information part of the same row in which individual RS check symbols are encoded and decoded together does not have a close relationship with the RS check symbol due to the effect of interleaving. Therefore, even if there is an error in the same row of the user data 1 and the RS check symbol unit 4 at the stage when the decoding apparatus receives the transmission format or in the middle of the iterative decoding unit B, the RS check symbol (for example, RS check symbol R₁) Is decoded from the interleaved bit string (bit string r₁₁, R₁₂, R₁₃, R₁₄... r_1nTherefore, there is a possibility that the error correction capability can be improved. As described above in connection with the first embodiment, the final horizontal BCH decoding circuit (for example, circuit 16) of the iterative decoding unit B performs only error position detection, and the RS decoding circuit 17 performs iterative decoding. It is further preferable to correct the error while verifying the judgment of the error position finally detected by the part B.
[0049]
Embodiment 3 FIG.
The interleaving method described above in connection with the second embodiment may be modified as in the third embodiment. Also in the third embodiment, the encoding device of FIG. 5 and the decoding device of FIG. 8 are used.
[0050]
A specific operation of the encoding apparatus will be described in detail with reference to FIGS. 9 and 10. In FIG. 9, r₁, R₂, R₃, R₄... are RS inspection symbols R₁, R₂, R₃, R₄Indicates the bit string required to generate. That is, the bit string r₁Are subject to the same RS encoding and RS check symbol R₁Is used to generate a bit string r₂Becomes the target of other RS coding and RS check symbol R₂Used to generate That is, in this embodiment, in the original user data 1 that is assumed to be two-dimensionally arranged, one check symbol is generated from one bit string arranged in the vertical direction.
[0051]
In this way, the bit string r arranged in a direction different from the horizontal processing direction₁, R₂, R₃, R₄From RS inspection symbol R₁, R₂, R₃, R₄.. Are easily generated, the interleave circuit 21 generates each bit string r from the user data 1 in the normal sequence as shown in FIG.₁, R₂, R₃, R₄Are extracted so that the user data 1 is rearranged so as to be suitable for encoding by the RS encoding circuit 6. That is, each bit string is arranged in one line. Then, the RS encoding circuit 6 performs RS encoding on the bit string of each row and also performs an RS check symbol R₁, R₂, R₃, R₄... is generated. In this way, the bit string r₁, R₂, R₃, R₄From RS inspection symbol R₁, R₂, R₃, R₄... are generated respectively. Therefore, in the horizontal BCH encoding circuit 7, a bit string (for example, bit string r) arranged in the vertical direction in the original user data 1 that is assumed to be two-dimensionally arranged.₁) Generated from one RS check symbol (for example, RS check symbol R)₁) Are subject to BCH encoding in the horizontal direction along with the information part in the same row.
[0052]
Similarly to the first and second embodiments, the vertical BCH encoding circuit 8 encodes the bits in each column (vertical direction) in the format assumed to be two-dimensionally arrayed once. Are read in the vertical direction (vertical processing direction in FIG. 9), the vertical BCH coding is applied to this column, and a vertical BCH check symbol corresponding to this column is generated. One RS inspection symbol (for example, RS inspection symbol R₁) Used to create the bit string (eg, bit string r)₁) On the same column will contribute to the generation of the same vertical BCH check symbol.
[0053]
On the other hand, in the decoding device, the iterative decoding unit B supplies the information sequence of the decoding result in the format shown in FIG. In the information sequence of this decoding result, the RS check symbol R in the previous stage of the BCH product encoding is performed by the horizontal BCH decoding circuits 12, 14, and 16.₁, R₂, R₃, R₄... is estimated. Similar to the interleave circuit 21 of the above encoding apparatus, as shown in FIG. 10, the interleave circuit 31 generates each bit string r from the information symbol (corresponding to the user data 1) in the normal sequence.₁, R₂, R₃, R₄.. Are repeated, and the information symbols are rearranged so as to be suitable for decoding by the RS decoding circuit 17. That is, each bit string is arranged in one line. Then, the RS decoding circuit 17 performs a bit string (for example, bit string r) in each row.₁) And RS inspection symbol (for example, RS inspection symbol R)₁) To estimate the error of the bit string. Also in the third embodiment, the information part of the same row in which individual RS check symbols are encoded / decoded together does not have a close relationship with the RS check symbol due to the effect of interleaving. Therefore, even if there is an error in the same row of the user data 1 and the RS check symbol unit 4 at the stage when the decoding apparatus receives the transmission format or in the middle of the iterative decoding unit B, the RS check symbol (for example, RS check symbol R₁) Is decoded from the interleaved bit string (bit string r₁Therefore, there is a possibility that the error correction capability can be improved. The deinterleave circuit 32 returns the information symbols corresponding to the original user data 1 among the decoding results obtained by the RS decoding circuit 17 to the order of arrangement in the decoding results obtained by the iterative decoding unit B, and this is the final error correction result. That is, it outputs to the output terminal 18 as an estimation result.
[0054]
As described above, also in this third embodiment, transmission is performed by making the RS encoding direction different from the encoding direction in combination encoding section A (in the embodiment, the direction of horizontal BCH encoding). There is a possibility that the error correction capability in decoding can be further enhanced by weakening the correlation between individual RS check symbols in the data format and the information parts encoded and decoded together with the RS check symbols.
[0055]
Embodiment 4 FIG.
In the decoding apparatus according to the first to third embodiments, the information sequence may be hard-input from the input terminal 10 to the iterative decoding unit B, and the iterative decoding unit B may perform hard decision decoding. However, as in the fourth embodiment described below, the iterative decoding unit B may perform soft decision decoding to further enhance the correction capability.
[0056]
Regarding soft decision decoding, for example, Masashi Akita, 6 others, “Third Generation FEC Employing Turbo Product Code for Long” -Haul DWDM Transmission Systems ")," OFC 2002 "(" Optical Fiber Communication Conference 2002 "), (USA), Optical Society of America, March 2002, p. 289-290. The iterative decoding apparatus for turbo product codes described in this document can be used as the iterative decoding unit B of the decoding apparatus according to the present invention.
[0057]
In the technique disclosed in this document, a soft decision is performed by a decoder at each stage of a turbo product code iterative decoding apparatus. The turbo product code used here is a product code of a BCH code. Assume that a decoder at a certain stage is a decoder at the m-th stage (m is 1 or more and any integer less than or equal to the total number of decoders of the iterative decoder). In the preceding stage of the m-th stage decoder, the k-th channel value r of the turbo product code_kIs the m-th stage decryption target data w^(M) _kThe soft input value y, which is the total value_kGet. And the soft input value y_kAre input to a SISO (soft input / soft output) decoder. This SISO decoder uses a soft input value y_kA number of codeword component candidates {C_j} And the log-likelihood ratio L for these candidates_kIs calculated according to equation (1).
[0058]
[Expression 1]

Where C_j ¹Is a codeword candidate whose bit at the k-th position is 1, and C_j ⁰Is a codeword candidate whose bit at the k-th position is 0, and p (Y | C) is a Gaussian transition probability.
[0059]
Value of channel k of turbo product code r_kIs the log likelihood ratio L_kThe log likelihood ratio L calculated by the decoder after being delayed by the delay line while calculating_kIs subtracted from the subtractor. This subtraction result is multiplied by an optimum weight coefficient by a multiplier. The result of multiplication is the decoding target data w of the decoder at the next stage (stage m + 1).^{(M + 1)} _kIn the preceding stage of the (m + 1) -th stage decoder, the k-th channel value r of the turbo product code_kIs the decoding target data w in the (m + 1) th stage^{(M + 1)} _kThe soft input value y, which is the total value_kGet. In this manner, iterative decoding is realized in which the decoder at the next stage performs soft decision decoding based on the decoding result of the decoder at a certain stage. And the log likelihood ratio L calculated by the decoder at the final stage_kThe information sequence input to the decoding device is estimated.
[0060]
The above iterative decoding apparatus may be used as the iterative decoding unit B of any decoding apparatus according to the first to third embodiments. That is, the BCH decoding circuits 11 to 16 in the first to third embodiments are replaced with the SISO decoders in the respective stages, and the adder, subtracter, delay line, and multiplier are replaced with the decoders. It may be accompanied. Based on the soft decision decoding result of the iterative decoding unit B, the RS decoding circuit 17 performs hard decision decoding, and outputs the decoding result to the output terminal 18 as a final error correction result, that is, an estimation result. In this way, it is possible to further enhance the correction capability by performing iterative decoding of the BCH product code with soft input / soft output.
[0061]
Further, the iterative decoding unit B of the fourth embodiment may perform soft decision decoding until halfway of iterative decoding, and finally perform hard decision decoding on the soft decision decoding result. Specifically, for example, the BCH decoding circuits 11 to 14 in the iterative decoding unit B are the above-described SISO decoders, and the BCH decoding circuits 15 and 16 in the final stage and the vicinity thereof are hard decision decoders with a simple configuration. In addition, the BCH decoding circuits 15 and 16 may decode the information series with a hard decision based on the soft decision decoding result of the horizontal BCH decoding circuit 14. However, up to which stage soft decision decoding is performed and where hard decision decoding is performed are arbitrary. For example, the BCH decoding circuits 11 to 15 are the above-described SISO decoders, and only the final stage BCH decoding circuit 16 is a hard decision decoder. Also good.
[0062]
In this way, by using the BCH decoding circuit at the final stage (and possibly in the vicinity thereof) as a hard decision decoder, the number of residual random errors in soft decision decoding can be clearly grasped by the hard decision decoder. is there. The number of random errors is supplied to the RS decoding circuit 17, and the RS decoding circuit 17 can correct the error more accurately with reference to the number of random errors.
[0063]
Embodiment 5 FIG.
In the third embodiment, the RS decoding circuit 17 performs hard decision decoding based on the soft decision decoding result of the iterative decoding unit B, and the hard decision decoding result of the RS decoding circuit 17 is used as a final error correction result, that is, an estimation result. Output to the output terminal 18. On the other hand, in the fifth embodiment described below, the soft decision decoding result of the iterative decoding unit B is corrected based on the error correction result or error detection result of the RS decoding circuit 17, and soft decision decoding is performed again.
[0064]
FIG. 11 shows a decoding apparatus according to Embodiment 5 of the present invention. This decoding apparatus includes a soft decision update circuit 40 and a second iterative decoding unit B2 in addition to the same components as the decoding apparatus (FIG. 3) according to the first embodiment. In FIG. 11, the same reference numerals are used to indicate the same components as in FIG. 5, and the description will be simplified. This decoding apparatus decodes and corrects errors in the transmission data format of the BCH product code by the encoding apparatus (FIG. 2) according to the first embodiment. In this embodiment, the iterative decoding unit B outputs the soft decision decoding result as described above in connection with the fourth embodiment. On the other hand, the RS decoding unit 17 performs error correction or error detection on the soft decision decoding result of the iterative decoding unit B by hard decision decoding, but the output result of the RS decoding circuit 17 is a final error. It is not output as a correction result.
[0065]
The soft decision decoding result of the iterative decoding unit B and the error correction number or the error detection state by the RS decoding circuit 17 are supplied to the soft decision updating circuit 40. The soft decision update circuit 40 corrects the soft decision decoding result of the iterative decoding unit B based on the number of error corrections or error detection states by the RS decoding circuit 17. The soft decision decoding result corrected by the soft decision update circuit 40 is supplied to the second iterative decoding unit B2.
[0066]
Similar to the iterative decoding unit B, the second iterative decoding unit B2 includes vertical BCH decoding circuits 41, 43, and 45 and horizontal BCH decoding circuits 42, 44, and 46 that are alternately arranged. Similarly to the decoding circuits 11 to 16 of the iterative decoding unit B, the decoding circuits 41 to 46 of the second iterative decoding unit B2 can decode the information sequence in a decoding format corresponding to the vertical or horizontal BCH code. Further, it is possible to perform soft decision decoding similarly to the decoding circuits 11 to 16 of the iterative decoding unit B of the fourth embodiment. Therefore, like the iterative decoding unit B, the second iterative decoding unit B2 can perform iterative decoding by soft decision. However, the second iterative decoding unit B2 may perform soft-decision decoding until halfway through iterative decoding, and finally perform hard-decision decoding on the soft-decision decoding result.
[0067]
According to this embodiment, the soft decision decoding result is corrected based on the number of error corrections or the error detection state of the RS decoding circuit 17, and the corrected soft decision decoding result is again softened by the second iterative decoding unit B2. It is possible to make it an object of iterative decoding by determination. As described above, the accuracy of soft decision decoding can be increased. The decoding result of the second iterative decoding unit B2 may be output to the output terminal 18 as a final error correction result, that is, an estimation result, or supplied again to the RS decoding circuit 47 as shown in the figure to decode the RS code. Error correction by law may be performed.
[0068]
The decoding apparatus according to the fifth embodiment is a modification of the decoding apparatus according to the first embodiment. However, the decoding apparatus according to the second or third embodiment (FIG. 8) is similarly modified. May be.
[0069]
Although the present invention has been illustrated and described in detail with reference to the preferred embodiments thereof, various changes in form and details can be made within the scope of the invention described in the claims. Will be understood by those skilled in the art. Such changes, substitutions, and modifications are also included in the scope of the present invention.
[0070]
For example, in the above embodiment, a product code using a BCH code is used in the transmission data format, but other types of codes that can be repeatedly decoded may be used. For example, Yu Kou, two others, “Low-Density Parity-Check Codes Based on Finite Geometries: A Rediscovery and New Results ")," IEEE Reports on Information Theory "(" IEEE Transactions on Information Theory "), (USA), Institute of Electrical and Electronics Engineers, November 2001, Vol. 47, Vol. 7, OFC2002, p. All embodiments have been modified so that encoding and decoding are performed using codes that can be classified into systematic codes among various low-density parity-check codes disclosed in 2711-2736. May be. Further, all the embodiments may be modified so that a product code using an RS code, a product code using another block code, and a concatenated code using an RS code or other block code are used.
[0071]
In the above embodiment, the iterative decoding unit B and the second iterative decoding unit B2 of the decoding apparatus are provided with three vertical BCH decoding circuits and three horizontal BCH decoding circuits 12, 14, and 16. However, the number of each of the vertical BCH decoding circuits and the horizontal BCH decoding circuits is not limited as long as it is two or more.
In the above embodiment, a large number of decoding circuits are arranged in series in the iterative decoding unit B and the second iterative decoding unit B2 of the decoding device, but the decoding results of the decoding circuit are transferred to other decoding circuits. The number of decoding circuits may be reduced in the form of supply.
[0072]
In the above embodiment, the error correction processing in the decoding apparatus always proceeds to the final stage decoding circuit (for example, the RS decoding circuit 17), but the decoding result includes an error in the middle of the iterative decoding. If it can be confirmed that there is no error, the error correction process may be terminated and the decoding result at that stage may be output as the final error correction result.
In the above embodiment, various processes such as encoding, decoding, interleaving, and deinterleaving are realized by a circuit. However, a computer can be used by using software that realizes the same process.
[0073]
【The invention's effect】
  As described above, according to the present invention, RS (Reed-Solomon) encoding is performed on each of a plurality of information parts obtained by regularly dividing the original information symbol, and a plurality of information parts corresponding to each information part are provided. An RS check symbol generation unit for generating the RS check symbol, and an information array having the original information symbol and the RS check symbol are subjected to error correction encoding in a plurality of block encoding formats and converted into a plurality of block encoding formats A combination coding unit for generating a check symbol of a plurality of corresponding formats, an original information symbol, an RS check symbol generated by error correction coding of the RS check symbol in a plurality of block coding formats, a plurality of An output unit for outputting a test symbol in the format;An interleaving unit that arranges the original information symbols in an order different from the order of the sequences to be supplied to the combination encoding unit and supplies the information symbols to the RS check symbol generation unit;The error correction coding by the combination coding unit is a format that can be iteratively decoded, and the error correction capability of the RS check symbol is higher than the error correction capability of the iterative decoding, so the redundancy is small It becomes possible to perform error correction efficiently with high error correction capability using a code. In particular, the combination coding unit performs error correction coding in a plurality of block coding formats, and the RS coding is also block coding. Therefore, the code structure is simpler than the convolutional code, and the parallel coding is performed in parallel. It is easy to perform rapid processing such as processing, and it is possible to easily configure the encoding device and the decoding device.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a two-dimensionally arranged transmission data format used in an encoding device and a decoding device according to Embodiment 1 of the present invention.
2 is a block diagram showing an encoding apparatus according to Embodiment 1 that generates the transmission data format of FIG. 1; FIG.
3 is a block diagram showing a decoding apparatus according to Embodiment 1 that estimates original information symbols from the transmission data format of FIG. 1; FIG.
4 is a schematic diagram showing a plurality of errors located in a lattice pattern that may exist on the transmission data format of FIG. 1; FIG.
FIG. 5 is a block diagram showing an encoding apparatus according to Embodiment 2 of the present invention.
FIG. 6 is a schematic diagram showing a two-dimensionally arranged transmission data format used in an encoding device and a decoding device according to Embodiment 2 of the present invention.
FIG. 7 is a schematic diagram showing operations of the encoding device and the decoding device according to Embodiment 2.
FIG. 8 is a block diagram showing a decoding apparatus according to Embodiment 2 of the present invention.
FIG. 9 is a schematic diagram showing a two-dimensionally arranged transmission data format used in an encoding device and a decoding device according to Embodiment 3 of the present invention.
FIG. 10 is a schematic diagram showing operations of an encoding device and a decoding device according to Embodiment 3.
FIG. 11 is a block diagram showing a decoding apparatus according to Embodiment 5 of the present invention.
[Explanation of symbols]
1 user data (original information symbol), 2 horizontal BCH check symbol part, 3 vertical BCH check symbol part, 4 RS check symbol part, 5 input terminal, 6 RS encoding circuit, 7 horizontal BCH encoding circuit, 8 vertical BCH encoding circuit, 9 output terminal, 10 input terminal, 11, 13, 15, 41, 43, 45 vertical BCH decoding circuit, 12, 14, 16, 42, 44, 46 horizontal BCH decoding circuit, 17 RS decoding circuit, 18 output terminals, 20 multiple errors located in a grid, 21 interleave circuit, 22 deinterleave circuit, 31 interleave circuit, 32 deinterleave circuit, 40 soft decision update circuit, 47 RS decode circuit, A combination An encoding unit, B iterative decoding unit, B2 second iterative decoding unit.

Claims (6)

RS check symbol generation for performing RS (Reed-Solomon) encoding on each of a plurality of information parts obtained by regularly dividing the original information symbol and generating a plurality of RS check symbols corresponding to each information part And
The information array having the original information symbol and the RS check symbol is subjected to error correction coding using a plurality of block coding formats, and a plurality of types of check symbols corresponding to the plurality of block coding formats are generated. A combination coding unit;
An output unit for outputting the original information symbol, the RS check symbol code generated by error correction coding of the RS check symbol using the plurality of block coding formats, and the plurality of check symbols ;
An interleaving unit that arranges original information symbols in an order different from the order of sequences to be supplied to the combination encoding unit and supplies the information symbols to the RS check symbol generation unit ,
The error correction coding by the combination coding unit is a format that allows iterative decoding, and the error correction capability of decoding by the RS check symbol is higher than the error correction capability by the iterative decoding.   The combination coding unit performs error correction coding in the BCH coding format on the information array having the original information symbol and the RS check symbol,
  The output unit outputs according to a transmission data format having an RS check symbol code obtained by BCH encoding the RS check symbol as an outer code, and a BCH check symbol obtained by BCH encoding the information array as an inner code. The encoding apparatus according to claim 1. An iterative decoding unit that repeats decoding an information sequence in a plurality of decoding formats corresponding to a plurality of block encoding formats;
An RS decoding unit that performs decoding by an RS code decoding method on a decoding result by the iterative decoding unit ;
An interleaving unit that supplies information symbols corresponding to original information symbols among the decoding results obtained by the iterative decoding unit to the RS decoding unit by arranging the information symbols in an order different from the order of arrangement of the decoding results by the iterative decoding unit;
The RS decoder decrypt apparatus example Bei a deinterleaving unit for returning to the order of arrangement of the decoding result by the information symbol iterative decoding portion corresponding to the original information symbols out of the decoding result by. The decoding apparatus according to claim 3 , wherein the iterative decoding unit performs soft decision decoding at least halfway through the iterative decoding. The decoding apparatus according to claim 4 , wherein the iterative decoding unit performs soft decision decoding until halfway of iterative decoding, and performs hard decision decoding on the soft decision decoding result. The iterative decoding unit outputs a soft decision decoding result, and the RS decoding unit performs error correction or error detection on the soft decision decoding result by hard decision decoding,
A soft decision updating unit for correcting the soft decision decoding result based on an error correction number or an error detection state by the RS decoding unit;
A second iterative decoding unit that repeats decoding the soft decision decoding result modified by the soft decision updating unit in a plurality of decoding formats corresponding to a plurality of block coding formats, and the second iterative decoding 5. The decoding apparatus according to claim 4 , wherein the unit performs soft decision decoding at least until halfway of iterative decoding.

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