JP2004282600A - Encoder and decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform error correction at a high error correction performance, and to generate signals with small redundancy. <P>SOLUTION: An encoder applies RS (Reed Solomon) encoding to multiple information parts of an original information symbol, and generate RS test symbols corresponding to each information parts. The encoder further applies error correction encoding with multiple block encoding formats to an information array including the original symbol and the RS test symbols, and generates test symbols of multiple formats corresponding to the block encoding formats. The error correction encoding with the multiple block encoding formats is a format allowing repeated decoding, and the decoding with the RS test symbols shows higher error correction performance than the repeated decoding. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

ここで、Ｃ_ｊ ^１は第ｋ位置のビットが１である符号語候補であり、Ｃ_ｊ ^０は第ｋ位置のビットが０である符号語候補であり、ｐ（Ｙ｜Ｃ）はガウスの遷移確率である。
【００５９】
ターボ積符号の第ｋ番チャネルの値ｒ_ｋは、復号器が対数尤度比Ｌ_ｋを算出する間、遅延線で遅延させられた後、復号器が算出した対数尤度比Ｌ_ｋから減算器により差し引かれる。この減算結果には、最適な重み係数が乗算器により乗算される。この乗算結果は、次の段階（第ｍ＋１段階）の復号器の復号対象データｗ^{（ｍ＋１）} _ｋであり、第ｍ＋１段階の復号器の前段では、ターボ積符号の第ｋ番のチャネル値ｒ_ｋを第ｍ＋１段階の復号対象データｗ^{（ｍ＋１）} _ｋに加算器により加えて、合計値である軟入力値ｙ_ｋを得る。このようにして、ある段階の復号器の復号結果に基づいて、次の段階の復号器が軟判定復号を行うという繰り返し復号が実現される。そして、最終段階の復号器が算出した対数尤度比Ｌ_ｋから復号装置に入力された情報系列が推定される。
【００６０】
上記の繰り返し復号装置は、実施の形態１から実施の形態３のいずれの復号装置の繰り返し復号部Ｂとして利用してもよい。つまり、実施の形態１から実施の形態３の各ＢＣＨ復号回路１１〜１６を上記の各段階のＳＩＳＯ復号器で置換し、上記の加算器、減算器、遅延線および乗算器を各復号器に付随させてもよい。繰り返し復号部Ｂの軟判定復号結果に基づいて、ＲＳ復号回路１７は硬判定復号を行い、その復号結果を最終的な誤り訂正結果すなわち推定結果として出力端子１８に出力する。このように、ＢＣＨ積符号の繰り返し復号を軟入力・軟出力で行うことによって、より訂正能力を強化することが可能である。
【００６１】
また、この実施の形態４の繰り返し復号部Ｂは、繰り返し復号の途中までは軟判定復号し、この軟判定復号結果に対して最終的に硬判定復号するのでもよい。具体的には、例えば、繰り返し復号部Ｂ中のＢＣＨ復号回路１１〜１４は上述のＳＩＳＯ復号器とし、最終段階およびその付近の段階のＢＣＨ復号回路１５，１６は簡易な構成の硬判定復号器とし、ＢＣＨ復号回路１５，１６では、水平方向ＢＣＨ復号回路１４の軟判定復号結果に基づいて情報系列を硬判定で復号するようにしてもよい。ただし、どの段階まで軟判定復号し、どこから硬判定復号するかは任意であり、例えばＢＣＨ復号回路１１〜１５は上述のＳＩＳＯ復号器とし、最終段階のＢＣＨ復号回路１６のみは硬判定復号器としてもよい。
【００６２】
このように最終段階（および場合によりその付近）のＢＣＨ復号回路を硬判定復号器とすることにより、軟判定復号での残留ランダム誤りの個数を明確に硬判定復号器で把握することが可能である。このランダム誤りの個数はＲＳ復号回路１７に供給され、ＲＳ復号回路１７はランダム誤りの個数を参照して、より精確に誤り訂正することが可能である。
【００６３】
実施の形態５．
実施の形態３では、繰り返し復号部Ｂの軟判定復号結果に基づいて、ＲＳ復号回路１７は硬判定復号を行い、ＲＳ復号回路１７の硬判定復号結果を最終的な誤り訂正結果すなわち推定結果として出力端子１８に出力する。これに対して、以下に述べる実施の形態５では、ＲＳ復号回路１７の誤り訂正結果または誤り検出結果に基づいて、繰り返し復号部Ｂの軟判定復号結果を修正して、再度軟判定復号する。
【００６４】
図１１は、この発明の実施の形態５に係る復号装置を示す。この復号装置は、実施の形態１に係る復号装置（図３）と同様の構成要素に加えて、軟判定更新回路４０と第２の繰り返し復号部Ｂ２を備える。図１１では、図５と共通する構成要素を示すために同一の符号を使用し、説明を簡略化する。この復号装置は、実施の形態１に係る符号化装置（図２）によるＢＣＨ積符号の伝送データフォーマットを復号して誤り訂正する。この実施の形態においては、繰り返し復号部Ｂが実施の形態４に関連して上述したように軟判定復号結果を出力する。一方、ＲＳ復号部１７は、繰り返し復号部Ｂの軟判定復号結果に対して硬判定復号により誤り訂正または誤り検出を施すようになっているが、ＲＳ復号回路１７の出力結果は最終的な誤り訂正結果として出力されるのではない。
【００６５】
繰り返し復号部Ｂの軟判定復号結果およびＲＳ復号回路１７による誤り訂正数または誤り検出状態は、軟判定更新回路４０に供給される。軟判定更新回路４０は、ＲＳ復号回路１７による誤り訂正数または誤り検出状態に基づいて繰り返し復号部Ｂの軟判定復号結果を修正する。軟判定更新回路４０により修正された軟判定復号結果は、第２の繰り返し復号部Ｂ２に供給される。
【００６６】
第２の繰り返し復号部Ｂ２は、繰り返し復号部Ｂと同様に、交互に配置された垂直方向ＢＣＨ復号回路４１，４３，４５と水平方向ＢＣＨ復号回路４２，４４，４６を備える。第２の繰り返し復号部Ｂ２の復号回路４１〜４６は、繰り返し復号部Ｂの復号回路１１〜１６と同様に、垂直方向または水平方向のＢＣＨ符号に対応する復号形式で情報系列を復号することが可能であり、さらに実施の形態４の繰り返し復号部Ｂの復号回路１１〜１６と同様に、軟判定復号することが可能である。従って、第２の繰り返し復号部Ｂ２は、繰り返し復号部Ｂと同様に、軟判定による繰り返し復号が可能である。ただし、第２の繰り返し復号部Ｂ２は、繰り返し復号の途中までは軟判定復号し、この軟判定復号結果に対して最終的に硬判定復号するのでもよい。
【００６７】
この実施の形態によれば、ＲＳ復号回路１７の誤り訂正数または誤り検出状態に基づいて軟判定復号結果を修正し、修正された軟判定復号結果を、再度第２の繰り返し復号部Ｂ２によって軟判定による繰り返し復号の対象とすることが可能である。以上のようにして、軟判定復号の精度を高めることが可能である。第２の繰り返し復号部Ｂ２の復号結果は、最終的な誤り訂正結果すなわち推定結果として出力端子１８に出力してもよいし、図示のように再度ＲＳ復号回路４７に供給してＲＳ符号の復号法による誤り訂正を施すようにしてもよい。
【００６８】
なお、この実施の形態５の復号装置は、実施の形態１に係る復号装置を修正したものであるが、実施の形態２または実施の形態３に係る復号装置（図８）を同様に修正してもよい。
【００６９】
以上、この発明をその好適な実施の形態を参照しながら詳細に図示して説明したが、請求の範囲に記載されたこの発明の範囲内で、形式および細部に関する様々な変更が可能であることは当業者であれば理解できることだろう。かかる変更、代替、修正もこの発明の範囲に含まれる。
【００７０】
例えば、上記の実施の形態では、伝送データフォーマットでは、ＢＣＨ符号を用いた積符号が使用されているが、他の形式の繰り返し復号可能な符号を使用してもよい。例えば、ユ・コウ（Ｙｕ Ｋｏｕ）、外２名、「有限幾何学に基づく低密度パリティ検査符号：再発見と新結果」（”Ｌｏｗ−Ｄｅｎｓｉｔｙ Ｐａｒｉｔｙ−Ｃｈｅｃｋ Ｃｏｄｅｓ Ｂａｓｅｄ ｏｎ Ｆｉｎｉｔｅ Ｇｅｏｍｅｔｒｉｅｓ： Ａ Ｒｅｄｉｓｃｏｖｅｒｙ ａｎｄ Ｎｅｗ Ｒｅｓｕｌｔｓ”）、「情報理論に関するＩＥＥＥ報告書」（”ＩＥＥＥ Ｔｒａｎｓａｃｔｉｏｎｓ ｏｎ Ｉｎｆｏｒｍａｔｉｏｎ Ｔｈｅｏｒｙ”）、（米国）、電気電子技術者協会（Ｉｎｓｔｉｔｕｔｅ ｏｆ Ｅｌｅｃｔｒｉｃａｌ ａｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｅｎｇｉｎｅｅｒｓ）、２００１年１１月、第４７巻、第７号、ＯＦＣ２００２、ｐ．２７１１−２７３６に開示された各種の低密度パリティ検査符号（ｌｏｗ−ｄｅｎｓｉｔｙ ｐａｒｉｔｙ−ｃｈｅｃｋ ｃｏｄｅｓ）のうち組織符号に分類できる符号を用いて符号化・復号するように、全ての実施の形態を修正してもよい。また、ＲＳ符号を用いた積符号、その他のブロック符号を用いた積符号、およびＲＳ符号その他のブロック符号を用いた連接符号を用いるように、全ての実施の形態を修正してもよい。
【００７１】
また、上記の実施の形態では、復号装置の繰り返し復号部Ｂおよび第２の繰り返し復号部Ｂ２に三つの垂直方向ＢＣＨ復号回路と三つの水平方向ＢＣＨ復号回路１２，１４，１６が設けられているが、垂直方向ＢＣＨ復号回路および水平方向ＢＣＨ復号回路の各々の個数は２つ以上であればいくつでもよい。
また、上記の実施の形態では、復号装置の繰り返し復号部Ｂおよび第２の繰り返し復号部Ｂ２において、多数の復号回路が直列に配置されているが、復号回路の復号結果を他の復号回路に供給する形式にして、復号回路の個数を削減してもよい。
【００７２】
また、上記の実施の形態では、復号装置での誤り訂正の処理は必ず最終段階の復号回路（例えばＲＳ復号回路１７）に進むが、繰り返し復号の途中の段階で復号結果に誤りが含まれていないと確認できれば、誤り訂正処理を終了して、その段階での復号結果を最終的な誤り訂正結果として出力してもよい。
また、上記の実施の形態では、符号化、復号、インタリーブ、デインタリーブといった各種の処理を回路で実現するが、同様の処理を実現するソフトウエアを利用してコンピュータを用いることも可能である。
【００７３】
【発明の効果】
以上のように、この発明によれば、元の情報記号を規則的に分割して得られる複数の情報部分の各々にＲＳ（リード・ソロモン）符号化を施すとともに、各情報部分に対応する複数のＲＳ検査記号を生成するＲＳ検査記号生成部と、前記元の情報記号と前記ＲＳ検査記号とを有する情報配列に複数のブロック符号化形式による誤り訂正符号化を施すとともに、前記複数のブロック符号化形式に対応する複数の形式の検査記号を生成する組み合わせ符号化部と、前記元の情報記号と、前記ＲＳ検査記号が前記複数のブロック符号化形式により誤り訂正符号化されて生成されたＲＳ検査記号符号と、前記複数の形式の検査記号とを出力する出力部とを備え、前記組み合わせ符号化部による誤り訂正符号化は繰り返し復号が可能な形式であり、前記繰り返し復号による誤り訂正能力よりも前記ＲＳ検査記号による復号の誤り訂正能力が高くされているので、冗長度が小さい符号を用いて高い誤り訂正能力で効率的に誤り訂正することが可能となる。特に、組み合わせ符号化部は、複数のブロック符号化形式による誤り訂正符号化を施し、ＲＳ符号化もブロック符号化であるので、畳込み符号に比較して、符号の構成が簡単であり、並列処理などの迅速な処理が行いやすく、かつ符号化装置および復号装置を簡易に構成することが可能である。
【図面の簡単な説明】
【図１】この発明の実施の形態１に係る符号化装置および復号装置で使用される２次元に配列された伝送データフォーマットを示す模式図である。
【図２】図１の伝送データフォーマットを生成する実施の形態１に係る符号化装置を示すブロック図である。
【図３】図１の伝送データフォーマットから元の情報記号を推定する実施の形態１に係る復号装置を示すブロック図である。
【図４】図１の伝送データフォーマット上に存在することがある格子状に位置する複数の誤りを示す模式図である。
【図５】この発明の実施の形態２に係る符号化装置を示すブロック図である。
【図６】この発明の実施の形態２に係る符号化装置および復号装置で使用される２次元に配列された伝送データフォーマットを示す模式図である。
【図７】実施の形態２に係る符号化装置および復号装置の動作を示す模式図である。
【図８】この発明の実施の形態２に係る復号装置を示すブロック図である。
【図９】この発明の実施の形態３に係る符号化装置および復号装置で使用される２次元に配列された伝送データフォーマットを示す模式図である。
【図１０】実施の形態３に係る符号化装置および復号装置の動作を示す模式図である。
【図１１】この発明の実施の形態５に係る復号装置を示すブロック図である。
【符号の説明】
１ ユーザデータ（元の情報記号）、２ 水平方向ＢＣＨ検査記号部、３ 垂直方向ＢＣＨ検査記号部、４ ＲＳ検査記号部、５ 入力端子、６ ＲＳ符号化回路、７ 水平方向ＢＣＨ符号化回路、８ 垂直方向ＢＣＨ符号化回路、９ 出力端子、１０ 入力端子、１１，１３，１５，４１，４３，４５ 垂直方向ＢＣＨ復号回路、１２，１４，１６，４２，４４，４６ 水平方向ＢＣＨ復号回路、１７ ＲＳ復号回路、１８ 出力端子、２０ 格子状に位置する複数の誤り、２１ インタリーブ回路、２２ デインタリーブ回路、３１ インタリーブ回路、３２ デインタリーブ回路、４０ 軟判定更新回路、４７ ＲＳ復号回路、Ａ 組み合わせ符号化部、Ｂ 繰り返し復号部、Ｂ２ 第２の繰り返し復号部。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an encoding device and a decoding device effective for error correction in digital transmission.
[0002]
[Prior art]
For error correction of digital transmission devices, product codes or concatenated codes in which block codes are arranged two-dimensionally are often used (for example, see Non-Patent Document 1).
For example, in the encoding of a product code, each row of two-dimensionally arranged user data (information symbols) is encoded with a horizontal linear code and a horizontal check symbol is generated. Each column of the horizontal check symbols is encoded with a vertical linear code, and a vertical check symbol is generated. The minimum distance of the product code obtained by such encoding is the product of the minimum distance of the horizontal linear code and the minimum distance of the vertical linear code. Therefore, by combining linear codes having a small minimum distance, a product code having a large minimum distance can be obtained as a result, and therefore, the error correction capability can be improved.
[0003]
In decoding the product code, error correction is performed in the vertical direction based on the check symbol in the vertical direction, and the correction result is corrected in the horizontal direction based on the check symbol in the horizontal direction. In the subsequent error correction in the horizontal direction, the erasure correction can be performed using detection information indicating that the error correction in the vertical error in the previous step cannot be corrected.
[0004]
Furthermore, the result of the horizontal error correction is corrected again in the vertical direction based on the check symbol in the vertical direction, and the correction result is corrected in the horizontal direction based on the check symbol in the horizontal direction. Iterative decoding that reduces residual errors by performing correction is already known.
[0005]
On the other hand, as a technique similar to the product code, a combination of horizontal encoding and oblique encoding has been proposed (for example, see Patent Document 1). In addition, the transmission source performs convolutional coding on the codes coded in a plurality of different directions, and the transmission destination performs maximum likelihood decoding using the convolutional code. A method of performing decoding has also been proposed (for example, see Patent Document 1).
[0006]
Further, a technique for performing error correction coding only on important data so as to have a stronger error correction capability than non-important data is disclosed (for example, see Patent Document 2). In the technique described in Patent Document 2, important data and insignificant data are separated, important data is encoded with an inner code, and the encoding result and the insignificant data are additionally encoded with an outer code, so that concatenation is performed. Get the sign.
[0007]
[Patent Document 1]
JP-A 1-228327
[Patent Document 2]
JP-A-7-162801
[Non-patent document 1]
Hideki Imai, "Coding Theory", 4th edition, The Institute of Electronics, Information and Communication Engineers, June 1990, p. 229-245
[0008]
[Problems to be solved by the invention]
However, in the method employing a general product code described in Non-Patent Document 1, when there are a plurality of errors positioned in a lattice in a two-dimensionally arranged product code, these errors are corrected. Is difficult. Even if the product code having such a lattice-like error is repeatedly decoded, if the decoding result is arranged two-dimensionally, there is a tendency that an error located in a lattice-like manner on the decoding result also occurs.
[0009]
In the technique described in Patent Document 1, a convolutional code is used to obtain a high error correction capability. However, the use of a convolutional code inevitably increases the length of a code block, which makes it difficult to transmit and decode data. Takes time. Further, maximum likelihood decoding of a complicated convolutional code described in Patent Document 1 requires an extremely large amount of calculation and storage, and is extremely difficult.
[0010]
According to the technique described in Patent Literature 2, it is possible for a decoder to perform error correction on important data with higher reliability than other data. However, although the redundancy increases with concatenated coding, the error correction ability by the outer code when the error correction at the time of decoding the important data by the inner code fails cannot be said to be high.
[0011]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an encoding apparatus that generates a code with a small degree of redundancy, which enables a decoding apparatus to efficiently correct errors with high error correction capability, is provided. The purpose is to get.
[0012]
Another object of the present invention is to solve the above-described problems, and an object of the present invention is to provide a decoding device capable of efficiently correcting an error with a high error correction capability using a code having a small redundancy. And
[0013]
[Means for Solving the Problems]
An encoding apparatus according to the present invention performs RS (Reed-Solomon) encoding on each of a plurality of information portions obtained by regularly dividing an original information symbol, and a plurality of RSs corresponding to each information portion. An RS check symbol generation unit for generating a check symbol, and performing error correction coding using a plurality of block coding formats on an information array having the original information symbols and the RS check symbols; A combination coding unit that generates a plurality of types of check symbols corresponding to the above, an RS check symbol generated by performing error correction coding of the original information symbol and the RS check symbol using the plurality of block coding formats. A code, and an output unit that outputs the plurality of types of check symbols, wherein the error correction coding by the combination coding unit is a format that can be repeatedly decoded. Than error correction capability of the decoder in which the error correction capability of the decoding is higher by the RS check symbol.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 shows a two-dimensionally arranged transmission data format used in an encoding device and a decoding device according to Embodiment 1 of the present invention. As shown in FIG. 1, this transmission data format includes user data (original information symbol) 1, a horizontal BCH (Bose-Chaudhuri-Hocquenghem) check symbol unit 2, a vertical BCH check symbol unit 3, and an RS (Reed-Solomon) has a check symbol part 4.
[0015]
FIG. 2 shows an encoding device according to Embodiment 1 for generating the transmission data format of FIG. As shown in FIG. 2, the encoding device includes an input terminal 5, an RS encoding circuit (RS check symbol generation unit) 6, a combination encoding unit A, and an output terminal (output unit) 9. The combination coding unit A includes a horizontal BCH coding circuit 7 and a vertical BCH coding circuit 8.
[0016]
User data 1 which is the original information symbol is input to the input terminal 5, and the user data 1 is supplied from the input terminal 5 to the RS encoding circuit 6. As shown in FIG. 1, the user data 1 has a horizontal symbol number (the number of columns) of k.₁And the number of vertical symbols (the number of rows) is k₂And can be understood as a two-dimensional array. In this embodiment, it is assumed that the order of the regular data sequence goes along the vertical columns, and goes to the beginning of the next column after the end of each column. Is not intended to be limiting. From the input terminal 5, k forming an information portion of each column (vertical direction)₂K bits are supplied to the RS encoding circuit 6 at one time, and after a time interval, k forming the information portion of the next column₂The number of bits may be supplied to the RS encoding circuit 6 at a time. Alternatively, the bits constituting the information portion of each column may be supplied to the RS encoding circuit 6 at time intervals of one or more bits.
[0017]
The RS encoding circuit 6 configures an information portion of each row of the user data 1 when it is assumed that the user data 1 is arranged two-dimensionally.₁The bits are read in the horizontal direction (horizontal processing direction in FIG. 1), the information portion of each row is subjected to RS encoding, and an RS check symbol corresponding to the information portion of each row is generated. Thus k equals the number of rows₂RS check symbols are obtained.
[0018]
The original user data 1 is also supplied to the horizontal direction BCH encoding circuit 7. Thereafter, the RS check symbol generated by the RS encoding circuit 6 is also supplied to the horizontal direction BCH encoding circuit 7. The horizontal direction BCH encoding circuit 7 configures an information part of one row in a format in which an information part of each row (horizontal direction) of the user data 1 is associated with an RS check symbol generated based on this information part. k₁Is read in the horizontal direction (horizontal processing direction in FIG. 1) as a single encoding target, the row is subjected to horizontal BCH encoding, and the horizontal corresponding to this row is encoded. Generate a direction BCH check symbol. Therefore, the horizontal direction BCH encoding circuit 7 calculates k₂Rows k₂, And k is generated by the encoding.₂Horizontal BCH check symbols (length is n₁-K₁-K₃Is obtained). The horizontal BCH check symbol part 2₂A set of horizontal BCH check symbols.
[0019]
The horizontal direction BCH encoding circuit 7 converts the original user data 1 and the RS check symbol code (length k₃X number of rows k₂) Are supplied to the vertical BCH encoding circuit 8 in accordance with the regular data arrangement order. Thereafter, the horizontal BCH check symbol generated by the horizontal BCH encoder 7 is also supplied to the vertical BCH encoder 8 in accordance with the normal data arrangement order. The vertical direction BCH encoding circuit 8 calculates k of each column.₂The bits are read in the vertical direction (vertical processing direction in FIG. 1) as a single encoding target, and this column is subjected to vertical BCH encoding, and a vertical BCH check symbol corresponding to this column is generated. . Therefore, the vertical direction BCH encoding circuit 8 calculates n₁Columns n₁N BCH codes, and n₁Vertical BCH check symbols (length is n₂-K₂Is obtained). The vertical BCH check symbol part 3₁It is a set of vertical BCH check symbols.
[0020]
Thus, the horizontal BCH check symbol part 2, the vertical BCH check symbol part 3, and the RS check symbol part 4 shown in FIG. 1 are obtained. The RS check symbol section 4 is a set of codes generated by subjecting the RS check symbols generated by the RS coding circuit 6 to BCH coding in the horizontal and vertical directions (ie, BCH product coding). Since the horizontal BCH check symbols are also subjected to the vertical BCH coding, the horizontal BCH check symbol section 2 shown in FIG. 1 is actually a set of vertical BCH coded horizontal BCH check symbols. .
[0021]
The vertical BCH encoding circuit 8 outputs to the output terminal 9 the original user data 1, the RS check symbol part 4, the horizontal BCH check symbol part 2, and the vertical BCH check symbol part 3, which are not encoded at all. This output also proceeds along the vertical columns in accordance with the above-described regular data arrangement order, and proceeds to the head of the next column after the end of each column. Therefore, each column of the user data 1 and each column of the vertical BCH check symbol portion 3 corresponding to that column are output first, and then each column of the RS check symbol portion 4 and the vertical BCH check symbol corresponding to that column. Each column of the unit 3 is output, and finally each column of the horizontal BCH check symbol unit 2 and each column of the vertical BCH check symbol unit 3 corresponding to that column are output. In this way, the transmission data format of FIG. 1 is realized, and the output terminal 9 also outputs bits constituting the transmission data format to the outside according to the above order.
[0022]
This transmission data format is a product code using a BCH code, and further enhances the error correction capability of the user data 1 by adding an RS code check symbol to the user data 1. Therefore, decoding can be performed based on the vertical BCH check symbol part 3 and then based on the horizontal BCH check symbol part 2 using the decoding result. Thereafter, it is also possible to perform iterative decoding in which decoding results in one of the vertical and horizontal directions are used and decoding of the other format is further continued. After decoding based on the horizontal direction BCH check symbol part 2, decoding based on the RS check symbol can improve the error correction capability.
[0023]
That is, regarding this transmission data format, the error correction capability of decoding using RS check symbols is higher than the error correction capability of repeating decoding. Specifically, this implementation is performed such that the error correction capability of decoding based on the RS check symbol is higher than the error correction capability of decoding performed immediately before (for example, decoding based on the horizontal BCH check symbol portion 2). The minimum distance guaranteed by the RS code selected for the configuration is greater than the minimum distance guaranteed by the (eg, horizontal) BCH code used in the previous decode. For this reason, as will be described later, the capability of error correction particularly for a plurality of errors located in a grid pattern in the user data 1 which is assumed to be arranged two-dimensionally is improved.
[0024]
FIG. 3 shows an example of a decoding device for estimating the original user data 1 from the transmission data format of FIG. As shown in FIG. 3, the decoding device includes an input terminal 10 to which a received information sequence is input, an iterative decoding unit B, an RS decoding circuit 17, and an output terminal 18. The iterative decoding unit B decodes the received information sequence conforming to the above transmission data format in a decoding format corresponding to the vertical BCH code used by the encoder, and decodes the horizontal BCH used by the encoder. Decoding in the decoding format corresponding to the code is repeated. For this purpose, the iterative decoding unit B includes a vertical direction BCH decoding circuit and a horizontal direction BCH decoding circuit arranged alternately, and the decoding result of the one-way decoding circuit is input to the decoding circuit of the other direction. It has become so.
[0025]
Each of the vertical direction BCH decoding circuits 11, 13, and 15 performs error correction of the information sequence based on the vertical direction BCH check symbol part 3, and each of the horizontal direction BCH decoding circuits 12, 14, and 16 performs a horizontal direction BCH check. Error correction of the information sequence is performed based on the symbol part 2. The decoding result output from the horizontal BCH decoding circuit 16 at the final stage of the iterative decoding unit B is input to the RS decoding circuit 17. The RS decoding circuit 17 performs error correction on the decoding result of the iterative decoding unit B by an RS code decoding method based on the RS check symbol unit 4, and outputs the error correction result (corresponding to user data 1). The result is output to the output terminal 18 as a final error correction result, that is, an estimation result.
[0026]
First, from the input terminal 10, n constituting the information portion of each column in the transmission data format of FIG.₂Bits are input to the first vertical BCH decoding circuit 11 at a time, and the vertical BCH decoding circuit 11 reads the column according to the vertical processing direction of FIG.₂-K₂Based on the vertical BCH check symbols, error correction of the column is performed. The vertical direction BCH decoding circuit 11 may handle one column at a time, or a plurality of columns may be simultaneously input from the input terminal 10 to the vertical direction BCH decoding circuit 11 and error-corrected by parallel processing. The decoding by the vertical BCH decoding circuit 11 corrects at least a part of the errors included in the user data 1, the RS check symbol section 4, and the horizontal BCH check symbol section 2. That is, error bits are replaced with correct bits in the transmission data format.
[0027]
The result of this error correction, that is, the transmission data format in which the error bits have been corrected, is supplied from the vertical direction BCH decoding circuit 11 to the horizontal direction BCH decoding circuit 12. In this case, n forming the information portion of each row₁Bits are input to the horizontal BCH decoding circuit 12 at a time, and the horizontal BCH decoding circuit 12 reads the column according to the horizontal processing direction in FIG. 1 and, based on the horizontal BCH check symbol included in the row, Performs line error correction. The horizontal direction BCH decoding circuit 12 may handle one row at a time, or a plurality of rows may be simultaneously input from the vertical direction BCH decoding circuit 11 to the horizontal direction BCH decoding circuit 12 and error-corrected by parallel processing. In the error correction in the horizontal direction BCH decoding circuit 12, it is also possible to perform erasure correction of bits based on the correction status in the vertical direction BCH decoding circuit 11. Further, when the vertical BCH check symbol section 3 is formed on the same body as the horizontal BCH check symbol section 2, each horizontal row of the vertical BCH check symbol section 3 is also a horizontal BCH code. Trailing n₁-K₁-K₃Bits can be considered a horizontal BCH check symbol for that row. Therefore, the vertical BCH check symbol part 3 can be corrected by the horizontal BCH decoding circuit 12 using the horizontal BCH check symbol by the same decoding method as the other rows.
[0028]
As a result of the error correction by the horizontal BCH decoding circuit 12, that is, the transmission data format in which the error bits are corrected, the information sequence is vertically erroneous based on the vertical BCH check symbol part 3 as in the vertical BCH decoding circuit 11. The signal is supplied to the vertical BCH decoding circuit 13 for correction. There is a possibility that the error remaining in the horizontal BCH decoding circuit 12 can be corrected by correcting the error again in the vertical BCH decoding circuit 13. In the error correction in the vertical BCH decoding circuit 13, it is also possible to perform erasure correction of bits based on the correction status in the horizontal BCH decoding circuit 12.
[0029]
In the same manner, the horizontal horizontal BCH decoding circuit 14, the vertical vertical BCH decoding circuit 15, and the horizontal horizontal BCH decoding circuit 16 generate an error with respect to the error correction result of the preceding decoding circuit. Make corrections. By alternately repeating different types of decoding in this manner, an error that cannot be corrected by a single error correction can be corrected.
[0030]
However, it is difficult to correct a plurality of errors 20 located in a lattice pattern illustrated in FIG. Here, “located in a grid pattern” means that a plurality of errors existing in one row in a format assumed to be two-dimensionally arranged and a plurality of errors existing in another row are on the same plurality of columns. Is to exist. The errors 20 located in a lattice shape may be included in the transmission data format from the beginning of reception, or may occur due to erroneous correction during repeated decoding. Even if a code having such a lattice-positioned error 20 is repeatedly decoded, a plurality of lattice-positioned errors still tend to occur on a decoding result assumed to be two-dimensionally arranged. In particular, when an error correction result output from the second-to-last vertical BCH decoding circuit (for example, the circuit 15) in the iterative decoding unit B has an error located in a lattice pattern, the last-stage horizontal BCH decoding is performed. The erasure correction cannot be performed by the circuit (for example, the circuit 16), and in some cases, the number of correctable errors corresponding to the minimum distance guaranteed by the horizontal decoding based on the horizontal BCH check symbol part 2 is determined by the number of actual errors. May be exceeded and error correction may not be possible.
[0031]
Therefore, in this embodiment, the decoding result of the iterative decoding unit B is further decoded by the RS decoding circuit 17. The RS decoding circuit 17 calculates k of the information portion of each row of the estimated user data 1.₁Bits and the corresponding k₃The RS check symbol composed of a number of bits is read in the horizontal direction (the horizontal processing direction in FIG. 1), and based on these, an error estimation of the original user data 1 is further performed.
[0032]
As described above, the error correction capability of the decoding based on the RS check symbol is higher than the error correction capability of the decoding performed immediately before (for example, the decoding based on the horizontal BCH check symbol portion 2). The minimum distance guaranteed by the RS code selected for the configuration is greater than the minimum distance guaranteed by the (eg, horizontal) BCH code used in the previous decode. Therefore, even if the error correction result output from the horizontal BCH decoding circuit (for example, the circuit 16) in the final stage of the iterative decoding unit B includes a plurality of errors 20 arranged in a lattice, it is guaranteed by the RS code. These errors can be corrected based on the minimum distance.
[0033]
The horizontal BCH decoding circuit (for example, the circuit 16) at the final stage of the iterative decoding unit B can detect only an error position and do not perform error correction. In this case, the RS decoding circuit 17 verifies the determination of the error position finally detected by the iterative decoding unit B, and the second-to-last vertical BCH decoding circuit ( For example, the error can be corrected by decoding the error correction result output from the circuit 15).
[0034]
As described above, according to the first embodiment, the encoding device performs RS encoding on each of a plurality of information portions obtained by dividing the original user data 1 into a plurality of rows, and performs , An RS encoding circuit 6 for generating a plurality of RS check symbols corresponding to the above, and an error correction by a plurality of BCH coding formats in an information array in which each information portion is arranged in association with the corresponding RS check symbol. Combination coding section A that performs coding and generates a plurality of check symbols corresponding to a plurality of BCH coding formats, and corrects error of original user data 1 and RS check symbols using a plurality of BCH coding formats. An output unit that outputs an RS check symbol unit 4, a horizontal BCH check symbol unit 2, and a vertical BCH check symbol unit 3 generated by encoding. The error correction coding by the combination coding unit A has a format that enables iterative decoding, and the error correction capability of decoding using RS check symbols is higher than the error correction capability of iterative decoding. Since the RS check symbol does not cause a large increase in redundancy and the combination coding of a format that can be repeatedly decoded does not cause a large increase in redundancy, the encoding device can generate a code with small redundancy. . In addition, the decoding device corrects an error generated on the transmission path as much as possible by iterative decoding of the iterative decoding unit B, and has a high error correction capability for errors remaining in the correction result, for example, a plurality of errors 20 located in a lattice shape. Since the RS decoding circuit 17 can correct the error by decoding using the RS check symbol, the decoding device can efficiently correct the error with high error correction capability.
[0035]
After the information portion of one column (vertical direction) is input to the horizontal direction BCH encoding circuit 7 and the horizontal direction BCH decoding circuits 12, 14, 16, and the RS encoding circuit 6 and the RS decoding circuit 17, the next column is input. , While the information part of each row (horizontal direction) is processed in the horizontal direction, a plurality of bit sequences corresponding to a plurality of rows in FIG. It is efficient to design to handle. With this design, the bits in one column extending over a plurality of rows are output simultaneously or within a short period from these circuits, so that the subsequent vertical BCH encoding circuit 8 and vertical BCH decoding circuit 11, 13 and 15 can easily pipeline the bits in one column. By designing as described above, it is possible to further contribute to speeding up of processing.
[0036]
Embodiment 2 FIG.
In the first embodiment, the RS encoding circuit 6 and the RS decoding circuit 17, like the horizontal direction BCH encoding circuit 7 and the horizontal direction BCH decoding circuits 12, 14, and 16, transmit the bits of each row in the horizontal processing direction in FIG. Is read to perform the processing. Accordingly, the individual RS check symbols in the RS check symbol section 4 are BCH-coded in the horizontal direction together with the information part of the same row from which the RS check symbol was created, and similarly decoded together. On the other hand, in the second embodiment described below, by making the direction of RS encoding different from the direction of horizontal BCH encoding, each RS check symbol in the transmission data format and the information portion of the same row And the error correction capability in decoding is further enhanced.
[0037]
FIG. 5 shows an encoding device according to Embodiment 2 of the present invention. This encoding device includes an interleaving circuit 21 and a deinterleaving circuit 22 in addition to the same components as those of the encoding device according to Embodiment 1 (FIG. 2). In FIG. 5, the same reference numerals are used to indicate the same components as those in FIG. 2, and the description will be simplified. The interleave circuit 21 is arranged before the RS encoding circuit 6 and is different from the normal order of the original user data to be supplied to the combination encoding unit A (the order of the sequence input from the input terminal 5). They are arranged in order and supplied to the RS encoding circuit 6. The deinterleave circuit 22 is arranged at a stage subsequent to the RS encoding circuit 6. The deinterleave circuit 22 stores the user data rearranged by the interleave circuit 21 and a plurality of RS check symbols generated by the RS encoding circuit 6. Supplied. The deinterleave circuit 22 returns the user data supplied from the interleave circuit 21 to the user data 1 in the normal order, and supplies the user data 1 to the horizontal BCH encoding circuit 7 of the combination encoding unit A. Then, the RS check symbol generated by the RS encoding circuit 6 is supplied to the horizontal direction BCH encoding circuit 7.
[0038]
The specific operation of the encoding device will be described in detail with reference to FIGS. In FIG. 6, R₁, R₂, R₃, R₄... indicate RS check symbols (not BCH product coded) generated by the RS coding circuit 6. Also, r₁₁, R₁₂, R_Thirteen, R₁₄… Is the RS inspection symbol R₁, R₂, R₃, R₄The bit string required to generate ... is shown. The length of each bit string may be one or more. Of these bit strings, bit string r₁₁, R₁₂, R_Thirteen, R₁₄... r_1nAre subject to the same RS encoding and RS check symbol R₁And a bit string r₂₁, R₂₂, R₂₃… Are subject to other RS encoding and RS check symbol R₂Used to generate That is, in this embodiment, in the original user data 1 which is assumed to be arranged two-dimensionally, one check symbol is generated from a plurality of bit strings arranged substantially obliquely. Same RS check symbol R₁A bit string r that produces₁₁, R₁₂, R_Thirteen, R₁₄... r_1nWith respect to the original user data 1 assumed to be arranged two-dimensionally, the bit string r₁₁, R₁₂, R_Thirteen, R₁₄.. Exist in different columns, and adjacent bit strings (for example, bit string r₁₁, R₁₂) Includes bits from different rows.
[0039]
Thus, the bit string r arranged in a direction different from the horizontal processing direction₁₁, R₁₂, R_Thirteen, R₁₄... r₂₁, R₂₂, R₂₃... RS inspection code R₁, R₂, R₃, R₄.. Are easily generated, the interleaving circuit 21 converts the user data 1 in the normal order into a bit string to be subjected to the same RS encoding (for example, the bit string r₁₁, R₁₂, R_Thirteen, R₁₄... r_1n) Is repeated, and the user data 1 is rearranged so as to be suitable for encoding by the RS encoding circuit 6. That is, a bit string to be subjected to the same RS encoding (for example, bit string r₁₁, R₁₂, R_Thirteen, R₁₄... r_1n) On one line. Then, the RS encoding circuit 6 performs the RS encoding on the bit string in each row, and performs the RS check symbol R₁, R₂, R₃, R₄... is generated. Thus, the bit string r₁₁, R₁₂, R_Thirteen, R₁₄... r_1nTo RS inspection symbol R₁Is generated, and the bit string r₂₁, R₂₂, R₂₃... r_2nFrom other RS check symbols R₂Is generated.
[0040]
The deinterleave circuit 22 returns the user data rearranged by the interleave circuit 21 to the normal order, and sends the user data 1 in the normal order to the horizontal BCH encoding circuit 7 of the combination encoding unit A. Then, the RS check symbol generated by the RS encoder 6 is supplied to the horizontal BCH encoder 7.
[0041]
The horizontal direction BCH encoding circuit 7 receives the information part of each row (horizontal direction) of the user data 1 in the regular order received from the deinterleave circuit 22 and the RS check symbol R₁, R₂, R₃, R₄.. Are associated with each other to form an information portion of one line.₁A row consisting of a number of bits and an RS check symbol is read in the horizontal direction (horizontal processing direction in FIG. 6) as a single encoding target, and this row is subjected to horizontal BCH encoding, and the horizontal Generate a direction BCH check symbol. Therefore, in the original user data 1 which is assumed to be two-dimensionally arranged, the bit string (for example, the bit string r₁₁, R₁₂, R_Thirteen, R₁₄... r_1n) Generated from one RS check symbol (for example, RS check symbol R₁) Are subject to horizontal BCH encoding along with the information portion in the same row.
[0042]
Similarly to the first embodiment, the vertical direction BCH encoding circuit 8 sets the bit of each column (vertical direction) in a format assumed to be two-dimensionally arranged as one encoding target in the vertical direction (FIG. 6), the column is subjected to vertical BCH encoding, and a vertical BCH check symbol corresponding to this column is generated. One RS check symbol (eg, RS check symbol R₁) To create the bit string (eg, bit string r₁₁, R₁₂, R_Thirteen, R₁₄... r_1n) Are on different columns and thus contribute to the generation of different vertical BCH check symbols.
[0043]
FIG. 8 shows a decoding device according to the second embodiment. This decoding apparatus includes an interleave circuit 31 and a deinterleave circuit 32 in addition to the same components as those of the decoder according to Embodiment 1 (FIG. 3). In FIG. 8, the same reference numerals are used to indicate the same components as those in FIG. The interleaving circuit 31 is arranged between the iterative decoding unit B and the RS decoding circuit 17 and arranges information symbols corresponding to the original user data 1 in the decoding result by the iterative decoding unit B in the decoding result by the iterative decoding unit B. Are supplied to the RS decoding unit 17 in an order different from the order.
[0044]
More specifically, from the iterative decoding unit B, an information sequence of the decoding result in the format shown in FIG. In the information sequence as a result of the decoding, the horizontal direction BCH decoding circuits 12, 14, and 16 use the RS check symbol R in the previous stage of the BCH product encoding.₁, R₂, R₃, R₄... is estimated. Similarly to the interleave circuit 21 of the above-described encoding apparatus, as shown in FIG. 7, the interleave circuit 31 converts the information symbols (corresponding to the user data 1) in the normal order into the same bit string ( For example, the bit string r₁₁, R₁₂, R_Thirteen, R₁₄... r_1n) Is repeated, and the information symbols are rearranged so as to be suitable for decoding by the RS decoding circuit 17. That is, a bit string (for example, a bit string r₁₁, R₁₂, R_Thirteen, R₁₄... r_1n) On one line. Then, the RS decoding circuit 17 outputs the bit string of each row (for example, the bit string r₁₁, R₁₂, R_Thirteen, R₁₄... r_1n) And RS check symbol (for example, RS check symbol R₁), The error of the bit string is estimated.
[0045]
The deinterleave circuit 32 is arranged at the subsequent stage of the RS decoding circuit 17 and returns the information symbols corresponding to the original user data 1 in the decoding result by the RS decoding circuit 17 to the order of the arrangement in the decoding result by the iterative decoding unit B. This is output to the output terminal 18 as a final error correction result, that is, an estimation result.
[0046]
As described above, according to the second embodiment, as in the first embodiment, the encoding device can generate a code having a small degree of redundancy, and the decoding device can perform the error correction of the iterative decoding unit B. , For example, a plurality of errors 20 located in a lattice pattern can be corrected by the RS decoding circuit 17 by decoding with an RS check symbol having a high error correction capability. Error correction is possible.
[0047]
Further, according to the second embodiment, the encoding apparatus arranges the original user data 1 in an order different from the order of the order to be supplied to the combination encoding unit A, and supplies the order to the RS encoding circuit 6 The circuit 21 is provided. Further, the decoding device arranges the information symbols corresponding to the original user data 1 in the decoding result by the iterative decoding unit B in a different order from the order in the decoding result by the iterative decoding unit B, and supplies the same to the RS decoding circuit 17. And a deinterleave circuit 32 for returning the information symbols corresponding to the original user data 1 in the decoding result by the RS decoding circuit 17 to the order of arrangement in the decoding result by the iterative decoding unit B. Therefore, by making the direction of RS coding different from the direction of coding in the combination coding unit A (the direction of horizontal BCH coding in the embodiment), each RS check symbol in the transmission data format and this It may be possible to weaken the correlation between the RS check symbol and the information part that is encoded and decoded together, further increasing the error correction capability in decoding.
[0048]
This effect will be described in more detail. As shown in FIG. 6, it is assumed that some errors among a plurality of errors 20 arranged in a lattice exist in the RS check symbol part 4. In the first embodiment, the individual RS check symbols in the RS check symbol part 4 are BCH-coded in the horizontal direction together with the information part of the same row from which they were created, and similarly decoded together. . Therefore, if there is an error in the same row of the user data 1 and the RS check symbol unit 4 at the stage when the decoding device receives the transmission format or at the stage in the middle of the iterative decoding unit B, the error may not be corrected. On the other hand, in the second embodiment, the information part of the same row in which the individual RS check symbols are encoded and decoded together does not have a close relationship with the RS check symbols due to the effect of interleaving. Therefore, even if there is an error in the same row of the user data 1 and the RS check symbol section 4 at the stage when the decoding device receives the transmission format or at a stage in the middle of the iterative decoding section B, the RS check symbol (for example, the RS check symbol R₁) Are decoded from the interleaved bit sequence (bit sequence r₁₁, R₁₂, R_Thirteen, R₁₄... r_1n), The error correction capability may be improved. As described above in relation to Embodiment 1, the horizontal BCH decoding circuit (eg, circuit 16) at the final stage of iterative decoding section B only detects an error position, and RS decoding circuit 17 performs iterative decoding. It is more preferable to correct the error while verifying the determination of the error position finally detected by the part B.
[0049]
Embodiment 3 FIG.
The interleaving method described above in relation to Embodiment 2 may be modified as in Embodiment 3 below. Embodiment 3 also uses the encoding device of FIG. 5 and the decoding device of FIG.
[0050]
The specific operation of the encoding device will be described in detail with reference to FIG. 9 and FIG. In FIG. 9, r₁, R₂, R₃, R₄... are RS check symbols R, respectively.₁, R₂, R₃, R₄The bit string required to generate ... is shown. That is, the bit string r₁Are subject to the same RS encoding and RS check symbol R₁And a bit string r₂Is the target of another RS encoding and the RS check symbol R₂Used to generate That is, in this embodiment, one check symbol is generated from one bit string arranged in the vertical direction in the original user data 1 which is assumed to be arranged two-dimensionally.
[0051]
Thus, the bit string r arranged in a direction different from the horizontal processing direction₁, R₂, R₃, R₄... RS inspection code R₁, R₂, R₃, R₄.. Are easily generated, the interleave circuit 21 converts each bit string r from the user data 1 in the normal arrangement order as shown in FIG.₁, R₂, R₃, R₄Are repeated, and the user data 1 is rearranged so as to be suitable for encoding by the RS encoding circuit 6. That is, the bit strings are arranged in one line. Then, the RS encoding circuit 6 performs the RS encoding on the bit string in each row, and performs the RS check symbol R₁, R₂, R₃, R₄... is generated. Thus, the bit string r₁, R₂, R₃, R₄... RS inspection code R₁, R₂, R₃, R₄Are generated respectively. Therefore, in the horizontal direction BCH encoding circuit 7, the bit string (for example, the bit string r) which is arranged in the vertical direction with the original user data 1 which is assumed to be two-dimensionally arranged.₁) Generated from one RS check symbol (for example, RS check symbol R₁) Are subject to horizontal BCH encoding along with the information portion in the same row.
[0052]
Also, as in the first and second embodiments, the vertical direction BCH encoding circuit 8 converts the bits of each column (vertical direction) in a format assumed to be arranged two-dimensionally into one encoding target. In the vertical direction (vertical processing direction in FIG. 9), the column is subjected to vertical BCH encoding, and a vertical BCH check symbol corresponding to this column is generated. One RS check symbol (eg, RS check symbol R₁) To create the bit string (eg, bit string r₁) Are on the same column and therefore contribute to the generation of the same vertical BCH check symbol.
[0053]
On the other hand, in the decoding device, the information sequence of the decoding result in the format shown in FIG. 9 is supplied from the iterative decoding unit B to the interleave circuit 31. In the information sequence as a result of the decoding, the horizontal direction BCH decoding circuits 12, 14, and 16 use the RS check symbol R in the previous stage of the BCH product encoding.₁, R₂, R₃, R₄... is estimated. Similarly to the interleave circuit 21 of the above-described encoding apparatus, as shown in FIG. 10, the interleave circuit 31 converts each bit string r from the information symbols (corresponding to the user data 1) in the normal arrangement order.₁, R₂, R₃, R₄Are repeated, and the information symbols are rearranged so as to be suitable for decoding by the RS decoding circuit 17. That is, the bit strings are arranged in one line. Then, the RS decoding circuit 17 outputs the bit string of each row (for example, the bit string r₁) And RS check symbol (for example, RS check symbol R₁), The error of the bit string is estimated. Also in the third embodiment, the information part of the same row in which individual RS check symbols are encoded and decoded together does not have a close relationship with the RS check symbols due to the effect of interleaving. Therefore, even if there is an error in the same row of the user data 1 and the RS check symbol section 4 at the stage when the decoding device receives the transmission format or at a stage in the middle of the iterative decoding section B, the RS check symbol (for example, the RS check symbol R₁) Are decoded from the interleaved bit sequence (bit sequence r₁), The error correction capability may be improved. The deinterleave circuit 32 returns the information symbols corresponding to the original user data 1 in the decoding result by the RS decoding circuit 17 to the order of arrangement in the decoding result by the iterative decoding unit B, and converts this to the final error correction result. That is, it is output to the output terminal 18 as the estimation result.
[0054]
As described above, also in the third embodiment, transmission is performed by making the direction of RS coding different from the direction of coding in combination coding section A (the direction of horizontal BCH coding in the embodiment). It may be possible to weaken the correlation between the individual RS check symbols in the data format and the information part which is encoded and decoded together with this RS check symbol, further increasing the error correction capability in decoding.
[0055]
Embodiment 4 FIG.
In the decoding devices according to the first to third embodiments, the information sequence may be hard-input to the iterative decoding unit B from the input terminal 10, and the iterative decoding unit B may perform hard-decision decoding. However, as in Embodiment 4 described below, iterative decoding section B may perform soft decision decoding to further enhance the correction capability.
[0056]
Regarding soft-decision decoding, for example, Masashi Akita, et al., And six others, “Third Generation FEC Employing Turbo Product Code Long Using Third-Generation FEC Using Turbo Product Codes for Long-Distance DWDM Transmission Systems”. -Haul DWDM Transmission Systems ")," OFC2002 "(" Optical Fiber Communication Conference 2002 "), (United States), Optical Society of America (Optical Society of Japan, March 2003, October 2003). 289-290. The iterative decoding device for turbo product codes described in this document can be used as the iterative decoding unit B of the decoding device according to the present invention.
[0057]
In the technique disclosed in this document, soft decision is performed by a decoder at each stage of the iterative decoding device for turbo product codes. The turbo product code used here is a product code of the BCH code. Assume that a decoder in a certain stage is an m-th stage decoder (m is any integer greater than or equal to 1 and less than or equal to the total number of decoders in the iterative decoder). Before the m-th stage decoder, the k-th channel value r of the turbo product code_kIs the decoding target data w of the m-th stage.^(M) _kTo the soft input value y which is the total value._kGet. And the soft input value y_kIs input to a SISO (soft input / soft output) decoder. This SISO decoder has a soft input value y_kOf the codeword components based on the matrix Y of_j｝, And the log likelihood ratio L for these candidates_kIs calculated according to equation (1).
[0058]
(Equation 1)

Where C_j ¹Is a code word candidate whose bit at the k-th position is 1, and C_j ⁰Is a codeword candidate whose bit at the k-th position is 0, and p (Y | C) is a Gaussian transition probability.
[0059]
The value r of the k-th channel of the turbo product code_kIs that the decoder has a log likelihood ratio L_kIs calculated, the log likelihood ratio L calculated by the decoder after being delayed by the delay line_kIs subtracted by a subtractor. This subtraction result is multiplied by an optimum weighting coefficient by a multiplier. The result of this multiplication is the decoding target data w of the decoder in the next stage (m + 1-th stage)^{(M + 1)} _kIn the preceding stage of the m + 1-th stage decoder, the k-th channel value r of the turbo product code_kIs the decoding target data w of the (m + 1) th stage^{(M + 1)} _kTo the soft input value y which is the total value._kGet. In this way, iterative decoding in which the decoder at the next stage performs soft decision decoding based on the decoding result of the decoder at a certain stage is realized. Then, the log likelihood ratio L calculated by the decoder at the final stage_k, An information sequence input to the decoding device is estimated.
[0060]
The above iterative decoding device may be used as the iterative decoding unit B of any of the decoding devices according to the first to third embodiments. That is, each of the BCH decoding circuits 11 to 16 of the first to third embodiments is replaced by the SISO decoder of each stage described above, and the adder, the subtractor, the delay line, and the multiplier are replaced by each decoder. It may be attached. The RS decoding circuit 17 performs hard decision decoding based on the soft decision decoding result of the iterative decoding unit B, and outputs the decoding result to the output terminal 18 as a final error correction result, that is, an estimation result. As described above, by performing iterative decoding of the BCH product code with soft input / soft output, it is possible to further enhance the correction capability.
[0061]
Further, iterative decoding section B of the fourth embodiment may perform soft-decision decoding up to the middle of iterative decoding, and finally perform hard-decision decoding on the soft-decision decoding result. Specifically, for example, the BCH decoding circuits 11 to 14 in the iterative decoding unit B are the above-described SISO decoders, and the BCH decoding circuits 15 and 16 in the final stage and in the vicinity thereof are hard decision decoders having a simple configuration. The BCH decoding circuits 15 and 16 may decode the information sequence by hard decision based on the soft decision decoding result of the horizontal BCH decoding circuit 14. However, it is arbitrary to which stage soft decision decoding is performed and where hard decision decoding is performed. For example, the BCH decoding circuits 11 to 15 are the above-described SISO decoders, and only the BCH decoding circuit 16 at the final stage is a hard decision decoder. Is also good.
[0062]
By using the hard decision decoder for the BCH decoding circuit at the final stage (and possibly in the vicinity thereof), the number of residual random errors in soft decision decoding can be clearly grasped by the hard decision decoder. is there. The number of random errors is supplied to the RS decoding circuit 17, and the RS decoding circuit 17 can correct the error more accurately by referring to the number of random errors.
[0063]
Embodiment 5 FIG.
In Embodiment 3, RS decoding circuit 17 performs hard decision decoding based on the soft decision decoding result of iterative decoding section B, and uses the hard decision decoding result of RS decoding circuit 17 as the final error correction result, that is, the estimation result. Output to the output terminal 18. On the other hand, in a fifth embodiment described below, the soft decision decoding result of the iterative decoding unit B is corrected based on the error correction result or the error detection result of the RS decoding circuit 17, and the soft decision decoding is performed again.
[0064]
FIG. 11 shows a decoding device according to Embodiment 5 of the present invention. This decoding device includes a soft decision update circuit 40 and a second iterative decoding unit B2 in addition to the same components as the decoding device according to Embodiment 1 (FIG. 3). In FIG. 11, the same reference numerals are used to indicate the same components as those in FIG. 5, and the description will be simplified. This decoding device decodes the transmission data format of the BCH product code by the encoding device according to Embodiment 1 (FIG. 2) and corrects the error. In this embodiment, iterative decoding section B outputs a soft decision decoding result as described above in connection with Embodiment 4. On the other hand, the RS decoding unit 17 performs error correction or error detection by hard decision decoding on the soft decision decoding result of the iterative decoding unit B, but the output result of the RS decoding circuit 17 It is not output as a correction result.
[0065]
The soft decision decoding result of the iterative decoding unit B and the number of error corrections or the error detection state by the RS decoding circuit 17 are supplied to the soft decision updating circuit 40. The soft-decision updating circuit 40 corrects the soft-decision decoding result of the iterative decoding unit B based on the number of errors corrected by the RS decoding circuit 17 or the error detection state. The soft decision decoding result corrected by the soft decision updating circuit 40 is supplied to the second iterative decoding unit B2.
[0066]
Like the iterative decoding unit B, the second iterative decoding unit B2 includes alternately arranged vertical BCH decoding circuits 41, 43, 45 and horizontal BCH decoding circuits 42, 44, 46. Similarly to the decoding circuits 11 to 16 of the iterative decoding unit B, the decoding circuits 41 to 46 of the second iterative decoding unit B2 can decode the information sequence in a decoding format corresponding to the vertical or horizontal BCH code. It is possible to perform soft-decision decoding similarly to the decoding circuits 11 to 16 of the iterative decoding unit B according to the fourth embodiment. Therefore, like the iterative decoding unit B, the second iterative decoding unit B2 can perform iterative decoding by soft decision. However, the second iterative decoding unit B2 may perform soft decision decoding up to the middle of the iterative decoding, and may finally perform hard decision decoding on the soft decision decoding result.
[0067]
According to this embodiment, the soft decision decoding result is corrected based on the number of error corrections or the error detection state of RS decoding circuit 17, and the corrected soft decision decoding result is again softened by second iterative decoding section B2. It is possible to set it as the target of iterative decoding by judgment. As described above, it is possible to improve the accuracy of soft decision decoding. The decoding result of the second iterative decoding unit B2 may be output to the output terminal 18 as a final error correction result, that is, an estimation result, or may be supplied again to the RS decoding circuit 47 as shown to decode the RS code. Error correction by a method may be performed.
[0068]
Although the decoding device according to the fifth embodiment is a modification of the decoding device according to the first embodiment, the decoding device according to the second or third embodiment (FIG. 8) is similarly modified. You may.
[0069]
While the present invention has been illustrated and described in detail with reference to the preferred embodiments, various modifications in form and detail are possible within the scope of the invention described in the claims. Will be understood by those skilled in the art. Such alterations, substitutions and modifications are also included in the scope of the present invention.
[0070]
For example, in the above embodiment, a product code using a BCH code is used in the transmission data format, but a code that can be repeatedly decoded in another format may be used. For example, Yu Kou, et al., "Low-Density Parity-Check Codes Based on Finite Geometry: A Rediscovery New News:" Low-Density Parity-Check Codes Based on Finite Geometry. Results ”),“ IEEE Transactions on Information Theory ”, (United States), Institute of Electrical and Electronics Engineers (Institute of Electrical and Electronics and Electronics, Vol. 11, November, the fourth month of Enginers, November 2001). No. 7, OFC2002, p. All the embodiments are modified so that encoding / decoding is performed using a code that can be classified as a systematic code among various low-density parity-check codes disclosed in 2711-2736. You may. Further, all embodiments may be modified to use a product code using an RS code, a product code using another block code, and a concatenated code using an RS code or another block code.
[0071]
In the above embodiment, three vertical BCH decoding circuits and three horizontal BCH decoding circuits 12, 14, and 16 are provided in the iterative decoding unit B and the second iterative decoding unit B2 of the decoding device. However, the number of each of the vertical direction BCH decoding circuit and the horizontal direction BCH decoding circuit may be any number as long as it is two or more.
Further, in the above embodiment, a large number of decoding circuits are arranged in series in the iterative decoding unit B and the second iterative decoding unit B2 of the decoding device, but the decoding result of the decoding circuit is transferred to another decoding circuit. The number of decoding circuits may be reduced in the form of supply.
[0072]
Further, in the above embodiment, the error correction processing in the decoding device always proceeds to the decoding circuit in the final stage (for example, the RS decoding circuit 17), but the decoding result contains an error in the middle of the iterative decoding. If it is confirmed that there is no error correction process, the error correction processing may be terminated, and the decoding result at that stage may be output as the final error correction result.
In the above-described embodiment, various processes such as encoding, decoding, interleaving, and deinterleaving are realized by circuits. However, a computer can be used by using software for realizing the same processes.
[0073]
【The invention's effect】
As described above, according to the present invention, RS (Reed-Solomon) encoding is performed on each of a plurality of information parts obtained by regularly dividing an original information symbol, and a plurality of information parts corresponding to each information part are encoded. An RS check symbol generation unit for generating an RS check symbol, and performing error correction coding in a plurality of block coding formats on an information array having the original information symbol and the RS check symbol; A combination encoding unit that generates a plurality of types of check symbols corresponding to a plurality of encoding formats, an RS generated by subjecting the original information symbols and the RS check symbols to error correction encoding according to the plurality of block encoding formats. A check symbol code, and an output unit for outputting the plurality of types of check symbols, wherein the error correction coding by the combination coding unit is a format that can be repeatedly decoded, Since the error correction capability of the decoding using the RS check symbol is higher than the error correction capability by the repetitive decoding, it is possible to efficiently correct the error with a high error correction capability using a code having a small redundancy. . In particular, the combination coding unit performs error correction coding in a plurality of block coding formats, and the RS coding is also block coding, so that the code configuration is simpler than the convolutional code, It is easy to perform quick processing such as processing, and it is possible to easily configure the encoding device and the decoding device.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a two-dimensionally arranged transmission data format used in an encoding device and a decoding device according to Embodiment 1 of the present invention.
FIG. 2 is a block diagram showing an encoding device according to Embodiment 1 for generating the transmission data format of FIG. 1;
FIG. 3 is a block diagram showing a decoding device according to Embodiment 1 for estimating original information symbols from the transmission data format of FIG. 1;
FIG. 4 is a schematic diagram showing a plurality of errors located in a grid that may exist on the transmission data format of FIG. 1;
FIG. 5 is a block diagram showing an encoding device according to Embodiment 2 of the present invention.
FIG. 6 is a schematic diagram showing a two-dimensionally arranged transmission data format used in an encoding device and a decoding device according to Embodiment 2 of the present invention.
FIG. 7 is a schematic diagram illustrating operations of an encoding device and a decoding device according to Embodiment 2.
FIG. 8 is a block diagram showing a decoding device according to Embodiment 2 of the present invention.
FIG. 9 is a schematic diagram showing a two-dimensionally arranged transmission data format used in an encoding device and a decoding device according to Embodiment 3 of the present invention.
FIG. 10 is a schematic diagram illustrating operations of an encoding device and a decoding device according to Embodiment 3.
FIG. 11 is a block diagram showing a decoding device according to Embodiment 5 of the present invention.
[Explanation of symbols]
1 user data (original information symbol), 2 horizontal BCH check symbols, 3 vertical BCH check symbols, 4 RS check symbols, 5 input terminals, 6 RS coding circuit, 7 horizontal BCH coding circuit, 8 vertical BCH encoding circuit, 9 output terminal, 10 input terminal, 11, 13, 15, 41, 43, 45 vertical BCH decoding circuit, 12, 14, 16, 42, 44, 46 horizontal BCH decoding circuit, 17 RS decoding circuit, 18 output terminals, 20 multiple errors located in a grid, 21 interleave circuit, 22 deinterleave circuit, 31 interleave circuit, 32 deinterleave circuit, 40 soft decision update circuit, 47 RS decode circuit, A combination Encoder, B iterative decoder, B2 second iterative decoder.

Claims (7)

RS check symbol generation for performing RS (Reed-Solomon) coding on each of a plurality of information portions obtained by regularly dividing an original information symbol and generating a plurality of RS check symbols corresponding to each information portion Department and
Performing error correction encoding using a plurality of block coding formats on an information array having the original information symbols and the RS check symbols, and generating a plurality of types of check symbols corresponding to the plurality of block coding formats. A combination encoding unit;
An output unit that outputs the original information symbol, an RS check symbol code generated by error-correction encoding the RS check symbol in the plurality of block coding formats, and a check symbol in the plurality of formats. Prepare,
An encoding device in which the error correction encoding by the combination encoding unit is in a format that enables iterative decoding, and the error correction capability of decoding by the RS check symbol is higher than the error correction capability by the iterative decoding. 2. The encoding apparatus according to claim 1, further comprising an interleaving section for arranging the original information symbols in an order different from the order of the arrangement to be supplied to the combination encoding section and supplying the same to the RS check symbol generation section. An iterative decoding unit that repeats decoding information sequences in a plurality of decoding formats corresponding to a plurality of block coding formats,
A decoding device comprising: an RS decoding unit that decodes a decoding result of the iterative decoding unit by an RS code decoding method. An interleaving unit that arranges information symbols corresponding to the original information symbols in the decoding result by the iterative decoding unit in an order different from the order of arrangement in the decoding result by the iterative decoding unit, and supplies the information symbols to the RS decoding unit;
4. The deinterleaving unit according to claim 3, further comprising: a deinterleaving unit for returning an information symbol corresponding to an original information symbol in a decoding result by the RS decoding unit to an order of arrangement in the decoding result by the iterative decoding unit. Decoding device. The decoding apparatus according to claim 3, wherein the iterative decoding unit performs soft decision decoding at least halfway through the iterative decoding. The decoding apparatus according to claim 5, wherein the iterative decoding unit performs soft decision decoding up to the middle of the iterative decoding, and performs hard decision decoding on the soft decision decoding result. The iterative decoding unit outputs a soft decision decoding result, and the RS decoding unit performs error correction or error detection by hard decision decoding on the soft decision decoding result,
A soft decision update unit that corrects the soft decision decoding result based on the number of error corrections or the error detection state by the RS decoding unit;
A second iterative decoding unit that repeats decoding of a soft decision decoding result corrected by the soft decision updating unit in a plurality of decoding formats corresponding to a plurality of block coding formats, and the second iterative decoding The decoding apparatus according to claim 5, wherein the unit performs soft decision decoding at least halfway through the iterative decoding.

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