JP7241851B1 - Error correction circuit, error correction device, error correction method, and communication device - Google Patents

Abstract

An error correction circuit capable of improving transmission characteristics while suppressing the circuit scale is provided. An error correction circuit (21, 22) of the present invention is an error correction circuit that performs soft-decision error correction processing using a multi-stage arithmetic circuit (30) that performs iterative decoding processing. ) includes an error correction processing circuit (32) that performs soft-decision error correction processing using likelihood information, and a likelihood calculation circuit (31) that supplies likelihood information to the error correction processing circuit (32). An error correction processing circuit (32) performs decoding processing using a code in which a part of pre-encoded data is duplicated between two consecutive codes, and a likelihood calculation circuit (31) performs a preceding arithmetic circuit. Likelihood information having a number of bits smaller than the number of bits of the likelihood information updated by the correction in , is calculated and supplied to the error correction processing circuit. [Selection drawing] Fig. 3A

Description

The present invention relates to an error correction circuit capable of improving transmission characteristics while suppressing circuit scale.

In coherent optical communication, in order to improve transmission characteristics, digital signal processing is used to compensate for distortion and frequency/phase fluctuations that occur during transmission. An error correction device is provided between transmission and reception to reduce data errors in transmission characteristics. In general, transmission characteristics are improved by performing error correction coding on data on the transmitting side and performing error correction according to the coding on the receiving side.

Hamming code, BCH code, Reed-Solomon code, and convolutional code/Viterbi decoding, for example, are generally well-known error correction methods. In particular, in recent communication devices, the development of CPU computing power has enabled complex and large-scale processing, so high-performance error correction such as LDPC (low density parity check code) method is used. In recent years, data are arranged in a matrix of n rows and m columns, and error correction processing is performed on the data in the row and column directions to improve the correction capability.

In error correction processing, hard decision is performed based on the result of decoding to "1" or "0" and correction processing is performed. There is a soft decision in which correction processing is performed based on The latter method has a higher correction capability than the former method, but the circuit scale and processing scale increase, and the power consumption also increases. Therefore, conventionally, in correction processing using soft decisions, there have been proposed methods for improving correction capability while suppressing increases in circuit scale and processing scale.

For example, in Patent Document 1, in the iterative decoding method of the LDPC code, in the middle of the iterative process, when a predetermined number of times is reached, by changing to a process based on different information, when the decoding process takes time due to an erroneous decision A method has been proposed to reduce the processing time of Further, in Patent Document 2, a soft-decision output method is applied to both the convolutional decoding process and the Reed-Solomon decoding process to improve performance. We have proposed a reception method that can be realized while suppressing.

JP 2009-225164 A JP 2011-205511 A

In Patent Document 1, decoding by iterative processing of an LDPC code is used, and error correction capability is improved by increasing the number of iterative operations in error correction processing, but there is a problem that the amount of computation increases and the processing time becomes long. rice field. In Patent Document 2, decoding by iterative processing of concatenated codes is used, and if the number of effective bits of likelihood information is increased, the error correction capability is improved, but there is a problem that the amount of calculation increases and the scale of the circuit also increases. there were.

In addition, in error correction processing involving iterative calculations, it is conceivable to equip only one error correction circuit and use the circuit repeatedly. error correction processing is delayed. On the other hand, by preparing error correction circuits corresponding to the number of repetitions, processing delay can be reduced and high-speed processing becomes possible, but there is a problem that the circuit scale becomes large.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems described above, and provides an error correction circuit capable of improving transmission characteristics while suppressing the circuit scale, thereby speeding up error correction processing and reducing power consumption. The purpose is to realize

In order to solve the above-described problems, an error correction circuit of the present invention is an error correction circuit that performs soft-decision error correction processing using a multi-stage arithmetic circuit that performs iterative decoding processing, wherein the arithmetic circuit is an error correction processing circuit for performing soft-decision error correction processing based on likelihood information; and a likelihood calculation circuit for supplying the likelihood information to the error correction processing circuit, wherein the error correction processing circuit comprises two continuous error correction processing circuits. The decoding process is performed using a code in which a part of the pre-encoding data between two codes overlaps, and at least one of the likelihood calculation circuits is updated by the arithmetic circuit of the preceding stage. 1 likelihood information is used to calculate second likelihood information having a number of bits smaller than the number of bits of the first likelihood information; is configured to be supplied to a correction processing circuit, and when compared with the redundancy of the code and the number of bits of the first likelihood information, such that the error correction circuit has a predetermined circuit scale and correction capability. A reduction amount of the number of bits of the second likelihood information is set .

In order to solve the problems described above, the error correction method of the present invention is an error correction method in an error correction circuit that performs soft-decision error correction processing using a multi-stage arithmetic circuit that performs iterative decoding processing, The arithmetic circuit includes an error correction processing circuit that performs soft-decision error correction processing based on likelihood information, and a likelihood calculation circuit that supplies the likelihood information to the error correction processing circuit, wherein the error correction processing circuit , decoding processing is performed using a code in which a part of pre-encoded data between two consecutive codes overlaps, and at least one of the likelihood calculation circuits is configured to perform Using the updated first likelihood information, calculating second likelihood information having a smaller number of bits than the number of bits of the first likelihood information, and arranging the second likelihood information in the subsequent stage. and supplied to the error correction processing circuit, and when compared with the redundancy of the code and the number of bits of the first likelihood information so that the error correction circuit has a predetermined circuit scale and correction capability. Sets the amount of reduction in the number of bits of the second likelihood information .

According to the present invention, it is possible to provide an error correction circuit capable of improving transmission characteristics while suppressing the circuit scale, and to realize high-speed error correction processing and low power consumption.

FIG. 1 is a diagram showing a configuration example of a communication device including an error correction device according to an embodiment of the present invention. FIG. 2A is a diagram showing a configuration example of an error correction coding device according to an embodiment of the present invention. FIG. 2B is a diagram showing a configuration example of an error correction coding device according to an embodiment of the present invention. FIG. 3A is a diagram showing a configuration example of an error correction device according to an embodiment of the present invention. FIG. 3B is a diagram for explaining the operation of the error correction device according to the embodiment of the present invention; FIG. 4A is a diagram showing a configuration example of an error correction device according to an embodiment of the present invention. FIG. 4B is a diagram for explaining the operation of the error correction device according to the embodiment of the present invention; FIG. 5A is a diagram showing a configuration example of an error correction device according to an embodiment of the present invention. FIG. 5B is a diagram for explaining the operation of the error correction device according to the embodiment of the present invention; FIG. 6A is a diagram for explaining likelihood information according to the embodiment of the present invention. FIG. 6B is an example of a table for obtaining log-likelihood ratios according to the embodiment of the present invention. FIG. 7 is a diagram showing a code configuration example according to the embodiment of the present invention. FIG. 8 is a diagram showing a configuration example of codes and redundant bits according to the embodiment of the present invention. FIG. 9 is a diagram showing a configuration example of codes and redundant bits according to the embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth below.

<Overview of the present invention>
SUMMARY OF THE INVENTION It is an object of the present invention to provide an error correction circuit capable of improving transmission characteristics while suppressing the circuit scale, and to realize high-speed error correction processing and low power consumption.

In the present invention, in an error correction circuit that performs soft-decision error correction processing using a plurality of stages of arithmetic circuits that perform iterative decoding processing, the number of errors that is reduced by one iterative decoding processing is used to determine the likelihood of subsequent iterative decoding. In addition to reducing the number of bits of degree information, decoding is performed using a code in which the pre-encoded data corresponding to one code and part of the pre-encoded data between two consecutive codes overlap. Thus, the above object is achieved.

By reducing the number of bits of likelihood information in the iterative decoding process and decoding using a code in which the data before encoding overlaps, it is possible to maintain or improve the correction capability while suppressing an increase in the circuit scale. , high-speed error correction processing and low power consumption can be realized.

Furthermore, in a code in which the pre-encoding data partly overlaps between two consecutive codes, by configuring the encoding direction of the pre-encoding data to be different, the correction capability can be improved. .

In addition, in the iterative decoding process of error correction, by adjusting the redundancy of the error correction code and the amount of reduction in the number of bits of likelihood information, it is also possible to realize an error correction circuit with a desired circuit scale and correction capability. can.

<Communication device including error correction device>
FIG. 1 is a configuration example of a communication device including an error correction device according to an embodiment of the present invention. FIG. 1 shows a configuration example in which an error correction coding device 10 and an error correction device 20 according to an embodiment of the present invention are applied to a coherent optical communication system communication device.

In the coherent optical communication system communication device of FIG. is configured to The transmitting side device and the receiving side device are connected via an optical fiber transmission line 500 . The transmission signal processing device 100 has an error correction coding device 10 , and the reception signal processing device 200 has an error correction device 20 .

The error correction coding device 10 in the transmission signal processing device 100 performs error correction coding on transmission data. The optical transmission module 300 generates an optical signal from transmission data encoded for error correction. In general coherent optical communication, a horizontally polarized optical signal X and a vertically polarized optical signal are combined and transmitted. When QPSK is used as the modulation method, transmission data is divided into horizontal polarization optical signal data (XI, XQ) and vertical polarization optical signal data (YI, YQ).

XI and XQ indicate the coordinates on the horizontal axis and the orthogonal axis on the complex plane of the horizontally polarized optical signal data, that is, the horizontal component and the orthogonal component, respectively. YI and YQ indicate coordinates on the horizontal axis and the orthogonal axis on the complex plane of the vertically polarized optical signal data, that is, the horizontal component and the orthogonal component, respectively. The transmission data is mapped to coordinates on the complex plane of the carrier wave and transmitted to the receiving side via the optical fiber transmission line 500 .

The optical receiver module 400 generates received data from the received optical signal. The optical receiver module 400 can output horizontally polarized optical signal data (XI, XQ) and vertically polarized optical signal data (YI, YQ). These data (XI, XQ, YI, YQ) are converted into digital signals by the received signal processing device 200 and error correction processing is performed by the error correction device 20 .

In a coherent optical communication device, transmission data is transmitted using a horizontally polarized optical signal and a vertically polarized optical signal, but it is also possible to transmit data using only one polarized signal. Even in that case, the error correction device 20 according to the embodiment of the present invention can be used.

Moreover, the communication device that can use the error correction device 20 according to the embodiment of the present invention is not limited to the coherent optical communication device described above. The error correction device 20 according to the embodiment of the present invention can also be used in other communication devices including wireless communication. It goes without saying that such communication devices are also within the scope of the present invention.

<Configuration of Error Correction Coding Device>
FIG. 2A is a diagram showing a configuration example of an error correction coding device according to an embodiment of the present invention. The configuration example of FIG. 2A is a device that performs coding for one type of error correction, and error correction coding device 10 has redundant bit adding circuit 11 . The error correction device on the receiving side is configured to perform error correction processing based on one type of soft decision according to the configuration of FIG. 2A.

The configuration example of FIG. 2B is a device that performs encoding for two types of error correction. The error correction device on the receiving side is configured to perform error correction processing based on two types of soft decisions according to the configuration of FIG. 2B.

As shown in FIG. 2B, by arranging redundant bit addition circuits corresponding to two types of error correction processing, the error correction capability can be improved. The circuit scale can be reduced by shortening the code length (information bit + redundant bit) in .

Here, at least one of the two types of error correction processing may be error correction processing by soft decision involving repeated calculations, and both of the two types may be error correction processing by soft decision, or error correction processing by soft decision. , error correction processing by hard decision may be mixed. The error correcting device on the receiving side has a configuration corresponding to the configuration of the error correcting coding device on the transmitting side.

The present invention is not limited to the two types of error correction coding processes illustrated in FIG. 2B. The transmitting side may perform three or more types of error correction coding processing, and the receiving apparatus may perform error correction processing according to the configuration of the coding processing on the transmitting side.

For example, an LDPC code can be used as the soft-decision error correction code in this embodiment. A plurality of types of soft-decision error correcting codes may all be LDPC codes. As the soft-decision error correction code in each process, in addition to the LDPC code, a Reed-Solomon code, a BCH code, a Hamming code, a convolutional code, a turbo code, a code combining a plurality of codes (concatenated code), etc. are used. good too. The code length of the error correction code at each stage can also be appropriately determined according to the state of the transmission line.

<Configuration of error correction device>
FIG. 3A is a diagram showing a configuration example of an error correction device according to an embodiment of the present invention. The configuration example of FIG. 3A is a configuration example of an error correction device (error correction circuit) 20 corresponding to the error correction coding device 10 of FIG. 2A. The error correction device 20 of FIG. 3A is a soft-decision error correction device provided with arithmetic circuits #1 to #3 (30, 40, 50) that perform iterative decoding processing by soft decision.

Arithmetic circuits (30, 40, 50) include error correction processing circuits (32, 42, 52) that perform soft-decision error correction processing based on likelihood information, and likelihood information that supplies likelihood information to the error correction processing circuit. A degree calculation circuit (31, 41, 51) is provided.

The error correction device 20 is a configuration example in which iterative decoding processing by soft decision is performed three times. An arithmetic circuit is provided for each decoding process of the iterative decoding process. The number of iterative decoding processes in the error correction process of the present invention is not limited to three, and can be appropriately set to an arbitrary number of iterations according to the required error correction capability. .

When error correction is repeatedly performed using one circuit, processing delay occurs because the next data cannot be processed until the processing for one received data is completed. In the present embodiment, by providing an arithmetic circuit for each decoding process of the iterative decoding process, it is possible to realize high-speed and low-delay error correction processing.

The circuit scale of error correction processing using soft decision increases according to the number of bits of likelihood information used for soft decision and the number of iterations of decoding. In the arithmetic circuit of the present embodiment, when the number of iterations is increased, the likelihood information (second likelihood information) of the arithmetic circuit in the subsequent stage is compared with the likelihood information (first likelihood information) in the arithmetic circuit in the preceding stage. By reducing the number of bits of the error correction information), the circuit scale can be reduced without degrading the performance of error correction.

FIG. 3A shows a configuration example in which the number of iterative decoding processes is three, and the number of bits of likelihood information is set so as to satisfy N1>N2>N3 in order from the previous stage. For example, if the number of bits of likelihood information is set to N1=3, N2=2, and N3=1, the circuit scale of arithmetic circuit #2 (40) is approximately half that of arithmetic circuit #1 (30). The circuit scale of #3 (50) can be approximately half that of arithmetic circuit #2 (40). By setting the number of bits of the likelihood information to N1=3, N2=2, and N3=1, the overall circuit scale can be reduced to approximately approx. can be halved.

<Operation of error correction device>
FIG. 3B is a diagram for explaining the operation of the error correction device according to the embodiment of the present invention; The error correction operation of this embodiment is executed in the error correction device 20 including the arithmetic circuit #1 (30), the arithmetic circuit #2 (40), and the arithmetic circuit #3 (50) of FIG. 3A.

When the received signal XI/XQ/YI/YQ is input from the optical receiver module 400 to the arithmetic circuit #1 (30) (step S1-1), the likelihood calculation circuit #A1 (31) calculates the X polarized wave/ Likelihood information #A1 is calculated for each bit (or symbol) of Y-polarized data (step S1-2), and the calculated likelihood information #A1 is supplied to error correction processing circuit #A1 (32). be.

The error correction processing circuit #A1 (32) uses the likelihood information #A1 supplied from the likelihood calculation circuit #A1 (31) to perform error correction processing on the X polarized wave/Y polarized wave data #A1. (step S1-3).

The corrected and updated likelihood information #A2 and the corrected data #A2 are supplied from the arithmetic circuit #1 (30) to the arithmetic circuit #2 (40), and the arithmetic circuit #2 (40) calculates the likelihood. Error correction processing is performed using processing and likelihood information.

In the likelihood calculation circuit #2 (41) of the arithmetic circuit #2 (40), the data for the X polarization and the data for the Y polarization are combined, and the error correction processing circuit #A1 (32) corrects Data #A2 and corrected and updated likelihood information #A2 are supplied, and likelihood information #A2 is calculated using the corrected and updated likelihood information #A2 (step S1-4). The calculated likelihood information #A2 is supplied to the error correction processing circuit #A2 (42).

The number of bits N2 of the likelihood information #A2 is smaller than the number of bits N1 of the corrected likelihood information #A2. For example, the likelihood information #A2 can be calculated by subtracting one bit of information from the least significant bit of the corrected and updated likelihood information #A2.

The error correction processing circuit #A2 (42) of the arithmetic circuit #2 (40) uses the likelihood information #A2 supplied from the likelihood calculation circuit #A2 (41) to perform error correction processing circuit #A1 (32). is executed for the output data #A2 (step S1-5).

The corrected and updated likelihood information #A3 and the corrected data #A3 are supplied from the arithmetic circuit #2 to the arithmetic circuit #3. Corrective action is taken.

In the likelihood calculation circuit #A3 (51) of the arithmetic circuit #3 (50), the data for the X polarization and the data for the Y polarization are combined, and the corrected data of the error correction processing circuit #A2 (42) Data #A3 and corrected and updated likelihood information #A3 are supplied, and likelihood information #A3 is calculated using the corrected and updated likelihood information #A3 (step S1-6). The calculated likelihood information #A3 is supplied to the error correction processing circuit #A3 (52).

The number of bits N3 of the likelihood information #A3 is less than the number of bits N2 of the corrected likelihood information #A3. For example, the likelihood information #A3 can be calculated by subtracting one bit of information from the least significant bit of the corrected and updated likelihood information #A3.

The error correction processing circuit #A3 (52) of the arithmetic circuit #3 (50) uses the likelihood information #A3 supplied from the likelihood calculation circuit #A3 (51) to perform the error correction processing circuit #A2 (42). is executed for the output data #A3 (step S1-7).

Since the arithmetic circuits #1-#3 (30, 40, 50) have performed arithmetic processing for the predetermined number of repetitions, the corrected reception data is output from the arithmetic circuit #3 (step S1-8).

In the present embodiment, in the iterative decoding process of the soft-decision error correction process, the number of bits of likelihood information in the subsequent decoding process is reduced from that in the preceding decoding process, thereby increasing the circuit size as the number of iterations increases. can be suppressed. Furthermore, by adjusting the redundancy of coding used in the decoding process, it is possible to configure such that the correction capability does not deteriorate even if the number of bits of the likelihood information is reduced.

For example, by setting the redundancy so that the error rate is halved by a single-stage arithmetic circuit, it is possible to reduce the number of bits of the likelihood information bit by bit without lowering the correction capability. It is possible to configure such that the error correction capability is not degraded while suppressing an increase in circuit size. According to an example of simulation results, the error occurrence rate was halved by setting the coding redundancy to about 7%. This is an example of a configuration that maintains correction capability.

In the configuration example described above, a configuration example (N1=3, N2=2, N3=1) in which the number of likelihood information bits is reduced by one bit for each iterative decoding process has been described. may be configured to reduce the number of bits of For example, the number of bits of likelihood information is set to N1=3, N2=2, and N3=2, or the number of bits of likelihood information is set to N1=3, N2=1, and N3=1. A configuration in which the number is set is conceivable.

Further, in a configuration example in which the number of bits of likelihood information is N1=3, N2=1, and N3=1, by setting a redundancy code that reduces the error rate to about 1/4, error It is possible to reduce the circuit scale without lowering the correction performance. The reduction in the number of bits of likelihood information is not limited to halving. can be configured to set the redundancy of Thus, by adjusting the redundancy of the error correction code and the amount of reduction in the number of bits of the likelihood information, it is possible to realize an error correction circuit having a desired circuit scale and correction capability.

For example, an LDPC code can be used as the soft-decision error correction code used in the error correction processing of this embodiment. When two or more stages of error correction codes are cascaded, LDPC codes may be used in all stages. As the soft-decision error correction code in each stage, Reed-Solomon code, BCH code, Hamming code, convolutional code, turbo code, concatenated code obtained by combining a plurality of codes, etc. may be used in addition to LDPC code. The code length of the error correction code at each stage can also be appropriately determined according to the state of the transmission line.

<Another configuration example of the error correction circuit>
FIG. 4A is a diagram showing a different configuration example of the receiving side of the error correction circuit according to the present invention. The configuration example of FIG. 4A is a configuration example of an error correction device 20 corresponding to the error correction coding device 10 of FIG. 2B. The error correction device 20 in FIG. 4A is an error correction device that includes an error correction circuit #B (21) and an error correction circuit #A (22) that perform iterative decoding processing using two types of soft decisions.

The error correction circuit #B (21) and the error correction circuit #A (22) are composed of arithmetic circuits (30, 40, 50) that perform iterative decoding processing, as in FIG. 3A. Arithmetic circuits (30, 40, 50) include error correction processing circuits (32, 42, 52) that perform soft-decision error correction processing based on likelihood information, and likelihood processing circuits (32, 42, 52) that supply likelihood information to the error correction processing circuits. A calculation circuit (31, 41, 51) is provided.

In the configuration example of FIG. 4A, in soft-decision error correction processing with two types of iterative calculations, soft-decision error correction processing including iterative calculations is performed. Multiple stages of soft-decision error correction circuits are cascade-connected, and in repeated decoding processing of soft-decision processing of each error correction circuit, the number of bits of likelihood information in the arithmetic circuit in the latter stage is reduced compared to the arithmetic circuit in the preceding stage. Thus, it is possible to improve the correction capability while suppressing the circuit scale. Furthermore, by adjusting the redundancy of coding used in the decoding process, it is possible to configure such that the correction capability does not deteriorate even if the number of bits of the likelihood information is reduced.

FIG. 4B is a diagram for explaining the operation of the error correction device according to the embodiment of the present invention;
The error correcting operation of this embodiment is executed in the error correcting device 20 provided with two types of error correcting circuits #A and #B provided with three stages of arithmetic circuits in FIG. 4A.

In the error correction circuit #B (21), the arithmetic circuits #B1 to #B3 (30, 40, 50) perform three iterative decoding processes, and then the corrected data #A is output from the arithmetic circuit #B3. are output (steps S2-2 to S2-4). The processing contents of the arithmetic circuits #B1 to #B3 (30, 40, 50) are the same as the processing contents of the arithmetic circuits #1 to #3 described with reference to FIGS. 3A and 3B.

The error correction circuit #A (22) receives the data #A corrected by the error correction circuit #B, and the arithmetic circuits #A1 to #A3 (30, 40, 50) perform iterative decoding processing three times. After that, the corrected data is output from the arithmetic circuit #A3 (steps S2-5 to S2-8). The processing contents of the arithmetic circuits #A1 to #A3 (30, 40, 50) are the same as the processing contents of the arithmetic circuits #1 to #3 described with reference to FIGS. 3A and 3B.

A hard-decision error correction circuit 23 may be connected after the soft-decision error correction circuit 21, as shown in FIG. 5A. As a result, compared with the case of a single-stage soft-decision error correcting device, the error correction capability can be improved, and since the circuit in the subsequent stage is a small-scale hard-decision circuit that does not use likelihood information, as shown in FIG. 4A. Compared to the case where two soft-decision error correction circuits are connected to each other, it is possible to suppress an increase in circuit scale and realize a configuration in which the error correction capability is improved more than in the case of one soft-decision processing.

The number of stages of the error correction processing circuit in this embodiment is not limited to the two-stage configuration described with reference to FIGS. 4A and 5A, and may be three or more stages. Also, the connection order of the plurality of error correction circuits is arbitrary. An arbitrary number of stages of soft-decision error correction apparatuses and an arbitrary number of stages of hard-decision error correction apparatuses may be connected in an arbitrary order. Even in the case of a configuration of three or more stages, by configuring at least one of the soft-decision error correction circuits as in this embodiment, the error correction capability can be improved while suppressing an increase in the circuit scale as a whole. A correction device can be implemented.

FIG. 5B is a diagram for explaining the operation of the error correction device according to the embodiment of the present invention; The error correction operation of this embodiment is performed by the soft-decision error correction circuit 21 having the three-stage arithmetic circuit shown in FIG. Executed in the correction device 20 .

In the error correction circuit B (21), the arithmetic circuits #B1 to #B3 (30, 40, 50) perform iterative decoding processing three times, and then the corrected data is output from the arithmetic circuit #B3 (50). It is output (steps S3-2 to S3-4). The processing contents of the arithmetic circuits #B1 to #B3 (30, 40, 50) are the same as the processing contents of the arithmetic circuits #1 to #3 described with reference to FIGS. 3A and 3B.

The hard-decision error correction circuit 23 in the subsequent stage performs hard-decision error correction on the output of the soft-decision error correction circuit 21, and outputs corrected data (steps S3-5 to S3-6).

In the configuration example of FIG. 3A described above, a case is illustrated in which a three-stage arithmetic circuit that performs iterative arithmetic operations three times is provided. A circuit may be provided. The arithmetic circuit in the fourth stage does not use likelihood information, so it corresponds to the hard-decision error correction circuit in FIG. 5A. According to such a configuration, since a circuit corresponding to hard decision is added to the final stage, the increase in circuit scale is reduced compared to the case where a soft decision error correction circuit is connected as in the configuration of FIG. 5A. It is possible to realize an error correction device that improves the error correction capability while suppressing the error.

<Likelihood information>
The likelihood information used in soft-decision error correction according to the present embodiment will be described. Likelihood information represents likelihood (reliability) for each bit (or symbol). The likelihood information of likelihood calculation circuit #A1 (31), likelihood calculation circuit #A2 (41), and likelihood calculation circuit #A3 (51) in the embodiment of FIG. It represents the likelihood of each bit (or symbol), the likelihood of each bit (or symbol) after the first error correction, and the likelihood of each bit (or symbol) after the second error correction.

When obtaining likelihood information based on coordinate information, the coordinate information is symbol-by-symbol (symbol: a group of data sent in a single modulation in communication). Likelihood information can be obtained for each symbol, or likelihood information can be calculated for each symbol and each bit in the symbol can be used as common likelihood information.

As an example of a modulation system in which a plurality of bits constitutes one symbol, one symbol in QPSK has two bits of information, and one symbol in 16QAM has four bits of information. 8 bits) can be transmitted.

Since the likelihood value of likelihood information representing the reliability of a signal bit is originally an analog value, it is possible to appropriately set how many bits are used to express the likelihood value. When the input likelihood value is large, there are few errors and the probability of erroneous correction is low, so the output likelihood value is large. Conversely, when the input likelihood value is small, there are many errors, and the probability of erroneous correction is high, so the output likelihood value is small. The likelihood value after error correction processing substantially indicates the residual error probability.

The likelihood value can be calculated based on the distance (shift amount) between the coordinate value of the ideal point to be transmitted and the coordinate value received on the complex plane. It is measured by the amount of deviation due to noise and the like from ideal coordinate points, and it is estimated that the smaller the amount of deviation, the greater the "probability" of the data. That is, the likelihood value and the shift amount on the coordinates have an inverse increase/decrease relationship. Therefore, the larger the likelihood value of the target bit (or symbol), the smaller the amount of deviation on the coordinates, so it is determined that the bit (or symbol) has high reliability (likelihood). An error correction process based on the value may be performed. Further, by transmitting the calculated likelihood information to the error correction processing circuit of the next stage, it can be used for error correction of the next stage.

As a method of calculating the distance between the coordinates on the complex plane, a method of calculating using the sum of the absolute values of the differences of the coordinate values on each axis can be considered. The maximum likelihood value is obtained when the received coordinates coincide with the ideal coordinate point, and the likelihood value decreases as the difference from the ideal coordinate point increases. If there are multiple ideal coordinate points, the intermediate coordinates of the ideal coordinate points will have the lowest likelihood value.

In the above description, the difference (shift amount) in the coordinates is used as the index of the likelihood, but the calculation of the likelihood is not limited to using the above-described difference in the coordinates. For example, it is possible to obtain the likelihood only from the signal intensity or from only the phase difference. Likelihood, which is an index indicating likelihood, can generally be calculated by various methods, and also in the present invention, other indices can be used as long as they indicate likelihood. In the present invention, it is possible to use an index other than the coordinate difference as the likelihood, and such cases are also within the scope of the present invention.

<Specific example of likelihood information>
A log likelihood ratio (LLR) can be used as the likelihood information in this embodiment. The likelihood information is not limited to the log-likelihood ratio, and other likelihood information may be used. A specific example of the log-likelihood ratio when the log-likelihood ratio is used as the likelihood information will be described below in the case of using QPSK as the modulation scheme.

FIG. 6A is a diagram for explaining likelihood information according to the embodiment of the present invention. Let Xt1 (XIt1, XQt1) be the ideal coordinate point set on the transmitting side, Xt2 (XIt2, XQt2) be the coordinate point of an adjacent signal point different from the coordinate point Xt1, and Xr (XIr, XQr) be the coordinate point of the receiving side. do.

Ar is the amplitude before error correction on the receiving side, At1 is the ideal amplitude of the ideal coordinate point Xt1, At2 is the amplitude of the adjacent coordinate point Xt2 different from the coordinate point Xt1, and φ1 and φ2 are the amplitudes of the receiving side. It is the phase difference between the coordinate point Xr and Xt1 and Xt2.

When expressed on the complex plane, the following relational expressions hold between the coordinate points and the amplitude and phase.
(XIr-XIt1)+j(XQr-XQt1)=(Ar/At1) exp(jφ1)
(XIr-XIt2)+j(XQr-XQt2)=(Ar/At2) exp(jφ2)

In general, the LLR is the logarithm of the ratio of the probability that the received target bit is 1 and the probability that it is 0, and is proportional to the coordinates of the received signal. Therefore, considering the coordinate XIr of the I-axis component among the coordinates (XIr, XQr) of the received signal Xr, the LLR of the I-axis component can also be expressed as follows. where A is a constant.
LLR=A|XIr|

FIG. 6B shows an example of correspondence between received coordinate values and LLRs. If the ideal coordinate values (I-axis components) on the transmitting side are, for example, +7 (=XIt1) and -7 (=XIt2), then by setting A=1/7, the received coordinate value can be either LLR=1, which is the maximum value of LLR, when it matches the ideal coordinate value of . In addition, when the received coordinate is zero (XIr=0), it is the intermediate value of the ideal coordinates, so the probability that the received target bit is 1 and the probability that it is 0 are equal, which is the minimum value of LLR. LLR=0. Also, the value of the LLR represents the reliability (likelihood) of the received bit. A value such as this LLR can be used as likelihood information. A general definition of LLR includes a logarithm (log), and a logarithmically transformed value can be used, but if the noise contained in the received signal can be approximated by a normal distribution, LLR is proportional to the received coordinate value. It is not necessary to perform logarithmic operations to calculate LLRs.

As described above, when using likelihood information that is not logarithmically transformed, it is possible to reduce the amount of arithmetic processing by logarithmic arithmetic and reduce the circuit scale required for it. Further, the likelihood information is not limited to information based on the difference in coordinate values, and other information may be used as long as it is an index indicating likelihood.

As the likelihood information, information obtained based on the coordinates of the received signal and the coordinates of the transmitted signal as described above and the positional relationship (distance information) between them can also be used. It can express the likelihood of the coordinates of the signal.

In the above, an example of calculation of the log-likelihood ratio for one polarized signal (horizontally polarized optical signal X) was explained, but in the case of orthogonal polarization multiplexing transmission, the other polarized signal (vertically polarized optical signal Y) Similarly, the log-likelihood ratio can be calculated.

As a method of obtaining the logarithmic likelihood ratio from the coordinate values, there is a method of obtaining the distance and the logarithmic value using a calculator. A method may be considered in which a table or the like of values and likelihood information is held in memory in advance, and this table is referred to for correspondence, whereby logarithmic values or likelihood information can be obtained. By preparing and using conversion tables such as a logarithmic conversion table and a coordinate/likelihood information conversion table in advance, arithmetic units for logarithmic conversion, likelihood information conversion, etc. become unnecessary, speeding up processing and circuit scale. A reduction effect is obtained.

Regarding the conversion table, it is possible to have a conversion table of many patterns, or to keep a partial correspondence table, and use the symmetry and similarity of the logarithmic function to convert an arbitrary constant multiple or any constant addition may be combined to obtain the logarithmic value. By using such a simplified method for hardware, it is possible to reduce processing time, circuit scale, and power consumption.

FIG. 6A illustrates the method of calculating likelihood information when QPSK is used as the modulation scheme, but the likelihood information can be obtained in the same manner even when other modulation schemes are used as the modulation scheme. . Since the error correction in this embodiment does not depend on the modulation scheme, the same error correction method can be applied even when BPSK, 8QAM, 16QAM, 64QAM, or other modulation schemes are used.

For example, when BPSK is used, Xt1 (XIt1, 0) and Xt2 (XIt2, 0) are the ideal coordinate points on the transmitting side, and Xr (XIr, 0) is the coordinate point before error correction on the receiving side. , the sum of the absolute values of the differences from the ideal coordinate points (Xt1, XIt2) on the transmission side. Likelihood information can be similarly calculated for the other polarization signal (vertically polarized optical signal Y) in the case of orthogonal polarization multiplexing transmission.

<Code configuration example>
FIG. 7 is a diagram showing a code configuration example according to the embodiment of the present invention. The code in the configuration example of FIG. 7 is a combination of the first half code (first code) obtained by vertically coding the pre-encoding data and the second half code (second code) obtained by horizontally coding the data. A plurality of these combined codes are concatenated to constitute one concatenated code.

"A: Data Configuration" in FIG. 7 is the configuration of the transmission/reception data. FIG. 7 shows an example of the configuration in which the data is folded back by horizontal 8 bits. The arrows in "A: data configuration" represent the data flow (order). It is assumed that the number of bits in the horizontal width of data is N bits (the figure shows an example of N=8). Data in the m-th row and the n-th column are represented by (m, n)=(row, column). Here, the data folding bit number N may be any number of bits, such as 128 bits or 256 bits.

"B: Concatenated code 1" in FIG. 7 shows the configuration of the first concatenated code A(1). The number (serial number) of the concatenated code is shown in parentheses of the concatenated code. Codes A1(1) to A8(1) are configured as follows.
Code A1 (1): [(1, 1) to (8, 1), (12, 1) to (12, 8)]
Code A2 (1): [(1, 2) to (8, 2), (13, 1) to (13, 8)]
Code A3 (1): [(1, 3) to (8, 3), (14, 1) to (14, 8)]
Codes A4(1) to A8(1) are also assigned according to the same rule.

The first concatenated code A(1) is obtained by concatenating these codes A1(1) to A8(1), and is constructed as follows.
Concatenated code A(1): [A1(1), A2(1), ..., A8(1)]

Here, the first half of the code (1st to 8th rows) is coded (in the vertical direction) every N=8 bits, which is the number of folding bits, with respect to the data flow. The latter half (12th to 19th lines) is coded along the data flow (horizontally). In addition, in the configuration example of FIG. 7, three blank lines are provided between the first half and the second half of the code.

"C: Concatenated code 2" in FIG. 7 shows the configuration of the second concatenated code A(2).
Code A1 (2): [(9, 1) to (16, 1), (20, 1) to (20, 8)]
Code A2 (2): [(9, 2) to (16, 2), (21, 1) to (21, 8)]
Code A3 (2): [(9, 3) to (16, 3), (22, 1) to (22, 8)]
The same applies to symbols A4(2) to A8(2).

The second concatenated code A(2) is obtained by concatenating these codes A1(2) to A8(2), and is constructed as follows.
Concatenated code A(2): [A1(2), A2(2), ..., A8(2)]

Here, the second concatenated code starts from the line next to the first half of the first concatenated code (from the ninth line in FIG. 7). As a result, concatenated codes are assigned to all data without gaps.

"D: Concatenated code 3" in FIG. 7 indicates the configuration of the third concatenated code A(3).
Code A1 (3): [(17, 1) to (24, 1), (28, 1) to (28, 8)]
Code A2(3): [(17, 2) to (24, 2), (29, 1) to (29, 8)]
Code A3 (3): [(17, 3) to (24, 3), (30, 1) to (30, 8)]
The same applies to symbols A4(3) to A8(3).

The third concatenated code A(3) is obtained by concatenating these codes A1(3) to A8(3), and is constructed as follows.
Concatenated code A(3): [A1(3), A2(3), ..., A8(3)]

In FIG. 7, it is desirable to use the same coding method for the first half and the second half of one concatenated code. The first half and the second half are configured as one code with the same coding method, and there is an overlap in the coding region of the coded data, and correction processing is performed using codes in different directions, thereby improving the correction capability. be able to. It is also possible to divide the code into the first half and the second half and use different coding schemes. Therefore, there may be cases where the correction capability is lower than when the same encoding method is used.

<Example of code and redundant bit configuration>
FIG. 8 is a diagram showing a configuration example of codes and redundant bits according to the embodiment of the present invention. FIG. 8 is a configuration example of a concatenated code and redundant code bits in the code configuration example of FIG.

FIG. 8 illustrates the configuration of the k-th concatenated code A(k). To simplify the explanation, the starting coordinates of the concatenated code are assumed to be (1, 1) as shown in FIG. Let N be the number of bits for folding data, and M be the number of bits in the first half of the concatenated code. Any number of bits can be set for N and M. For example, the number of bits may be 128 bits, 256 bits, or the like.

Let N be the number of bits in the second half of the concatenated code. N=M may be used, or a different number of bits may be used. A blank line may be provided between the first half and the second half of the code, and the number of blank lines is L bits (L lines). L is an arbitrary number of bits (number of rows) including 0. FIG. 7 described above is a configuration example when L=3, M=8, and N=8 in FIG.

Code A1(k) to code AN(k) and concatenated code A(k) are configured as follows.
Code A1(k): [(1, 1) ~ (M, 1), (M + L + 1, 1) ~ (M + L + 1, N)]
Code A2(k): [(1, 2) ~ (M, 2), (M + L + 2, 1) ~ (M + L + 2, N)]
Code A3(k): [(1, 3) ~ (M, 3), (M + L + 3, 1) ~ (M + L + 3, N)]
・・・
Code AN(k): [(1, N) ~ (M, N), (M + L + N, 1) ~ (M + L + N, N)]

The concatenated code A(k) is obtained by concatenating these codes A1(3) to AN(3), and is constructed as follows.
Concatenated code A(k): [A1(k), A2(k), . . . AN(k)]

Let R be the number of redundant code bits included in the code A1(k). Redundant bits can be placed at arbitrary positions. For example, as shown in FIG. 8, R bits may be assigned from the last part of the code obtained by combining the first half and the second half.

For example, when M = 8, N = 8, and R = 1, the number of bits (code length) of one code is 16 bits, and the last bit of the 16 bits is a redundant bit. , 1/(16−1)=about 7%. When the original data overlaps between successive codes as in this embodiment, the code length of all codes is double the original data before encoding. , 1 bit out of 8 bits is a redundant bit, and the redundancy is about 1/(8-1)=14%.

When M=128, N=128, and R=17, the number of bits (code length) of one code is 256 bits. degree is 17/(256-17)=about 7%. In the same manner as above, 17 bits out of 128 bits are redundant bits in the original data before encoding, so the redundancy is about 17/(128-17)=15%.

In the configuration example of FIG. 8, the first half code assigned in the vertical direction and the second half code assigned in the horizontal direction are combined to form one code, and a plurality of combined codes are concatenated to form one concatenation. constitute a sign. By encoding the same pre-encoded data in different directions between two consecutive concatenated codes, the overlapping portion of the pre-encoded data between the two concatenated codes is reduced, thereby improving error correction performance. can be expected. The encoding direction of the concatenated code and the method of overlapping two consecutive concatenated codes can be appropriately set according to the requirements for improving the performance of error correction and processing time for error correction processing.

For example, in contrast to the configuration example of FIG. 8, the code assigned in the horizontal direction in the first half and the code assigned in the vertical direction in the latter half are combined to form one code, and a plurality of combined codes are concatenated. One concatenated code may be constructed by this. As for the combination of the direction of code allocation, a combination of a diagonal code and a vertical or horizontal code may be used, or the first half may be a right-down diagonal code, and the second half may be a left-down diagonal code. good too. By configuring the encoding direction of the pre-encoding data to be different between two consecutive concatenated codes, the overlapping portion of the pre-encoding data between the two concatenated codes is reduced, and error correction performance is improved. I can expect it.

When the code assigned in the horizontal direction in the first half and the code assigned in the vertical direction in the second half are combined to form one code, the assignment in the vertical direction is distributed without following the original data flow. Therefore, the resistance to burst errors is increased. As a countermeasure against burst errors, a method of distributing data by adding an interleave function is known. It is possible to improve the performance of error correction. Further, by adding a general interleave function as a separate circuit to the error correction circuit of this embodiment, it is possible to further improve the error correction performance.

In the configuration in which the latter half is allocated in the horizontal direction, the allocation of the latter half is performed along the flow of data, so that portion may become vulnerable to burst errors. There is an advantage that the number of upper buffers can be reduced, and by constructing a code in combination with a code in the vertical direction, it is possible to improve the performance of error correction as a whole.

In this embodiment, the first half code assigned in the vertical direction and the second half code assigned in the horizontal direction are combined to form one code, and a space is provided between the first half code and the second half code. line is set. When the first half and the second half are combined to form one code, by providing a blank line between the first half code and the second half code, the resistance to burst errors can be improved.

When a concentrated bit error occurs in a short bit string such as a burst error, the code in the first half and the code in the second half are separated in the data flow so that the first half and the second half are connected. The impact of burst errors on the single code itself is reduced. In situations where burst errors occur, it is possible to suppress the occurrence of code errors due to burst errors by providing a blank line between the code in the first half and the code in the second half.

The effect of overlapping encoding in different directions for the same pre-encoded data will be described with reference to FIG. FIG. 9 is a configuration example of concatenated codes and redundant bits when M=8, N=8, L=1, and the upper left coordinates are (1, 1) in FIG.

For example, as shown in FIG. 9, if there is an error in the data at coordinates (1, 11), the two concatenated codes A(1) and A(2) will be affected. Thus, when decoding the first concatenated code A(1), there is a possibility of error correction in code A2(1). Also, when decoding the second concatenated code A(2), there is a possibility that the code A1(2) will be error-corrected.

Therefore, the code A(1) and the code A(2) are double-corrected, and a combination of different data, that is, a horizontal code for the code A(1) and a vertical code for the code A(2). Since correction processing is performed, it is possible to reduce the possibility of overlooking an error and improve the error correction capability.

Here, the likelihood information of each bit after correction in the case of double error correction of code A(1) and code A(2) is obtained by using the likelihood information after correction processing in both codes. can be calculated. For example, it can be easily calculated by a method such as calculating the likelihood information by adding two pieces of likelihood information obtained by error correction of each code.

In the present embodiment, the case of performing double correction processing between two consecutive concatenated codes has been described, but it is also possible to multiplex combinations of different codes three times or more. By making the code overlap three times or more, the number of error corrections also becomes three or more times, and the error correction performance can be further improved.

<Effects of the embodiment of the present invention>

According to this embodiment, in an error correction circuit that performs soft-decision error correction processing using a plurality of stages of arithmetic circuits that perform iterative decoding processing, according to the number of errors that are reduced by one iterative decoding processing, In iterative decoding, the number of bits of likelihood information is reduced, and a code in which the data before encoding corresponding to one code and the data before encoding between two consecutive codes partially overlap is used. By decoding with the same number of pixels, it is possible to maintain or improve the correction capability while suppressing an increase in circuit size, so that it is possible to realize high-speed error correction processing and low power consumption.

Furthermore, in a code in which a part of the pre-encoding data is duplicated between two consecutive codes, the encoding direction of the pre-encoding data is different, thereby further improving the correction capability. can.

Also, by making the data sequence of the concatenated code different from the transmission order of the pre-encoded data, the burst error correction capability can be improved. Since resistance to burst errors can be increased without adding processing such as interleaving, it is possible to reduce the circuit size and power consumption.

In addition, when the first half code and the second half code are combined to form one code, a blank line is provided between the first half code and the second half code to increase resistance to burst errors. be able to.

Also, by adjusting the redundancy of the error correction code and the amount of reduction in the number of bits of the likelihood information, it is possible to realize an error correction circuit having a desired circuit scale and correction capability. By adjusting the redundancy of the error correction code, it is possible to prevent deterioration of the correction capability even when the amount of likelihood information is reduced to about 1/4 or 1/8.

For example, the number of bits of likelihood information, which is soft-decision information, can be reduced by 1 bit by setting the redundancy so that the number of errors in one iterative operation by error correction is approximately halved, for example, by setting the redundancy to about 7%. It is possible to configure so that the correction capability is not degraded even if the

Further, even when multiple stages of error correction processing circuits are cascade-connected, the number of bits of likelihood information is reduced in at least one iterative decoding process of error correction processing, and between consecutive concatenated codes, By performing the decoding process using overlapping codes on the data, it is possible to improve the correction capability while suppressing an increase in the circuit scale.

Furthermore, by combining soft-decision error correction processing with other different error correction processing, such as hard decision, and cascade-connecting them, it is possible to further improve the error correction capability while suppressing an increase in circuit size.

INDUSTRIAL APPLICABILITY The present invention can be used as an error correction device in optical communication or the like.

DESCRIPTION OF SYMBOLS 100... Transmission signal processing apparatus 200... Receiving signal processing apparatus 300... Optical transmission module 400... Optical reception module 10... Error correction coding apparatus 11, 12... Redundant bit addition circuit 20... Error correction apparatus 21 , 22... error correction circuit (soft decision), 23... error correction circuit (hard decision), 30, 40, 50... arithmetic circuit, 31, 41, 51... likelihood calculation circuit, 32, 42, 52... error correction processing circuit.

Claims (8)

An error correction circuit that performs soft-decision error correction processing using a multi-stage arithmetic circuit that performs iterative decoding processing,
The arithmetic circuit is
An error correction processing circuit that performs soft decision error correction processing based on likelihood information, and a likelihood calculation circuit that supplies the likelihood information to the error correction processing circuit,
The error correction processing circuit is
configured to perform decoding processing using a code in which a part of pre-encoded data between two consecutive codes overlaps,
At least one likelihood calculation circuit,
using the first likelihood information updated by the arithmetic circuit in the previous stage, calculating second likelihood information having a number of bits smaller than the number of bits of the first likelihood information; is configured to supply the error information to the error correction processing circuit arranged in the latter stage ,
reducing the number of bits of the second likelihood information when compared with the redundancy of the code and the number of bits of the first likelihood information so that the error correction circuit has a predetermined circuit scale and correction capability; A set amount of error correction circuitry. The code is a concatenated code composed of a first code and a second code, and the first code and the second code are configured such that the direction of encoding in the pre-encoded data is different. The error correction circuit according to claim 1, wherein the error correction circuit is The code is such that a part of the pre-encoding data corresponding to the second code in which the direction of encoding in the first code and the pre-encoding data is different between two consecutive codes overlaps. 3. The error correction circuit according to claim 2, wherein: 4. The error correction circuit according to any one of claims 1 to 3, wherein the redundancy of said code is set to a value such that a data error rate is halved by correction processing in said error correction processing circuit. An error correction device comprising at least one stage of the error correction circuit according to any one of claims 1 to 4. 6. The error correction device according to claim 5, wherein a hard decision error correction circuit is connected to at least one stage of the error correction circuit. An error correction method in an error correction circuit that performs soft-decision error correction processing using a multi-stage arithmetic circuit that performs iterative decoding processing,
The arithmetic circuit is
An error correction processing circuit that performs soft decision error correction processing based on likelihood information, and a likelihood calculation circuit that supplies the likelihood information to the error correction processing circuit,
The error correction processing circuit is
configured to perform decoding processing using a code in which a part of pre-encoded data between two consecutive codes overlaps,
At least one likelihood calculation circuit,
using the first likelihood information updated by the arithmetic circuit in the previous stage, calculating second likelihood information having a number of bits smaller than the number of bits of the first likelihood information; supplying the error information to the error correction processing circuit arranged in the latter stage;
reducing the number of bits of the second likelihood information when compared with the redundancy of the code and the number of bits of the first likelihood information so that the error correction circuit has a predetermined circuit scale and correction capability; Sets the amount of error correction method. A communication device comprising the error correction device according to claim 5 or 6.

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