JPWO2020183525A1 - Coding device, decoding device, and error correction device - Google Patents

Abstract

The coding apparatus includes a plurality of external coding circuits that generate an external code for error correction using the input first information and output a first code word in which the external code is added to the first information. , A plurality of internal coding circuits that generate an internal code for error correction using the input second information and output a second codeword in which the internal code is added to the second information, and a plurality of external codes. A codeword and a first codeword group containing a plurality of first codewords or an information series to be coded, which is arranged in front of one of a coding circuit and a plurality of internal codewords, are divided. A replacement circuit that outputs the information series or the information obtained by dividing the first codeword group as the first information or the second information to one side, and the first codeword that is arranged after the other. It is provided with a reverse exchange circuit that returns the information of the information series constituting the group or the second codeword group including a plurality of second codewords to the positional relationship of the information series.

Description

The present invention relates to a coding device, a decoding device, and an error correcting device for correcting information errors.

In high-speed transmission systems such as optical transmission systems, error correction technology is generally applied as an effective method for realizing high transmission capacity and long-distance transmission. The error correction technology is a technology used in a wired / wireless transmission system, a storage device, etc., and makes the target information redundant. As a result, when error detection and correction technology is applied to the transmission system, by adding redundant bits as error correction codes to the digital information sent on the transmitting side, even if an error occurs in the received digital information, the added error The correction code can detect and correct an error.

As error correction codes used in error correction technology, various codes such as Hamming code, BCH (Bose-Chaudhuri-Hocquenghem) code, RS (Reed-Solomon) code, product code combining these, and concatenated code have been proposed. There is.

Even if an error correction code is added, there is a limit to the number of error bits, which is the number of bits for which an error can be corrected. Further, the number of error bits that can be corrected differs depending on the type of error correction code.

In a transmission system, transmission information including overhead and the like constituting a frame is called an information bit. A redundant bit added to the information bit as an error correction code is also called a parity bit. The parity bit is calculated from the information bit by using a different calculation method depending on the type of error correction code. A bit string in which information bits and parity bits are combined is also called a code word.

In the error correction code called a block code, the parity bit is calculated from the information bit in the unit of a preset number of bits. The number of information bits and the number of parity bits in one codeword are predetermined, and they are called the information bit length and the parity bit length, respectively. The number of bits of a code word is called the code length.

In the core metro optical transmission system used for submarine cables and intercity communication, there is a remarkable demand for expansion of transmission capacity and transmission distance. As a result, strong error correction codes are applied and proposed every day for high-speed transmissions of several hundred Gbps to 1 Tbps and the like.

In recent years, a low-density parity check (LDPC) code has been widely used as an error correction code. The LDPC code is a block code defined by a sparse parity check matrix with few non-zero elements.

The LDPC code can be corrected even in a transmission line with many errors by using soft judgment information such as LLR (Log-Likelihood-Ratio), and is implemented in a high-speed transmission system such as several hundred Gbps to 1 Tbps. It is possible. For this reason, LDPC codes have been widely used in core metro optical transmission systems.

On the other hand, the LDPC code causes a phenomenon called an error floor in which the correction effect is not as effective as the correction result in the transmission environment in which the error before correction is relatively large in the transmission environment where the error before correction is relatively small. Cheap.

As a countermeasure against this error floor, a frame configuration is adopted in which the LDPC code is used as the internal code and the above-mentioned Hamming code, BCH code, RS code, product code combining these, concatenated code combining these, etc. are combined as the external code. (See, for example, Non-Patent Documents 1 and 2).

Non-Patent Document 1 discloses a triple concatenated coding method in which three types of block codes including LDPC codes are combined as concatenated codes. Further, Non-Patent Document 2 discloses a coding method in which a block code is concatenated with an LDPC code having a long code length and a strong correction ability.

Conventionally, an interleave is inserted between the connected LDPC code and the block code to disperse the error remaining in the LDPC code into a plurality of block codes as a plurality of external codes. The error remaining in the LDPC code can be corrected by a plurality of block codes. Conventionally, there is a coding device in which external coding processing is performed in parallel, then interleaving processing is performed to change the order, and internal coding processing is performed in parallel (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2001-136079

Y. Miyata, K. Sugihara, W. Matsumoto, K. Onohara, T. Sugihara, K. Kazuo, H. Yoshida, and T. Mizuochi, “A triple-concatenated FEC using soft-decision decoding for 100 Gb / s optical transmission, ”in Proc. OFC / NFOEC 2010, OThL3 (2010). K. Sugihara, Y. Miyata, T. Sugihara, K. Kubo, H. Yoshida, W. Matsumoto, and T. Mizuochi, “A spatially-coupled type LDPC code with an NCG of 12 dB for optical transmission beyond 100 Gb / s , "Proc. OFC / NFOEC 2013, OM2B.4 (2013).

In recent years, optical transmission systems are required to have higher processing capacity as the transmission capacity is expanded. On the other hand, low power consumption is also required.

In the prior art described in Patent Document 1, the outer code and the inner code of the concatenated code are added by a plurality of coding circuits, and their decoding is performed by a plurality of decoding circuits, respectively. In addition, an interleaved circuit and a deinterleaved circuit are placed to replace symbols that do not require memory. However, it requires a counter and a selector because it is replaced every time.

The present invention has been made to solve such a problem, and provides a coding device, a decoding device, and an error correction device capable of further suppressing power consumption.

The coding apparatus according to the present invention uses the input first information to generate an external code for error correction, and outputs a plurality of codewords in which the external code is added to the first information. A coding circuit and a plurality of internal coding circuits that generate an internal code for error correction using the input second information and output a second code word in which the internal code is added to the second information. , A first codeword group that is placed in front of one of a plurality of external codewords and a plurality of internal codewords and includes an information sequence to be encoded, or a plurality of first codewords. Is divided, and the information obtained by dividing the information series or the first codeword group is arranged as the first information or the second information in a replacement circuit to be output to one side, and is arranged after the other side. It is provided with a reverse exchange circuit for returning the information of the information series constituting the codeword group of 1 or the second codeword group including a plurality of second codewords to the positional relationship of the information series.

The decoding device according to the present invention inputs a second code word to which an internal code is added to the second information, corrects an error in the second information using the internal code, and outputs the second information. A plurality of internal code decoding circuits and a first code word in which an external code is added to the first information are input, and an error correction of the first information is performed using the external code to obtain the first information. A second code word group that is arranged in front of one of a plurality of output code decoding circuits, a plurality of internal code decoding circuits, and a plurality of external code decoding circuits and includes a plurality of second code words. Alternatively, the second information group including a plurality of second information is divided, and the second code word group or the information obtained by dividing the second information group is the second code word or the first code word. As a code word, an information sequence to be encoded, which comprises a replacement circuit to be output to one side and a first information group arranged after the other and containing a second information group or a plurality of first information. It is provided with a reverse exchange circuit that returns the information of the above to the positional relationship of the information series.

The error correction device according to the present invention includes at least one of the coding device and the decoding device.

According to the present invention, the power consumption can be further suppressed.

It is a block diagram which shows the structural example of the error correction apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structural example of the coding apparatus which concerns on Embodiment 1 of this invention. It is a figure explaining the operation example of the coding apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structural example of the decoding apparatus which concerns on Embodiment 1 of this invention.

Hereinafter, preferred embodiments of the error correction device, the coding device, and the decoding device according to the present invention will be described with reference to the drawings. In the following description, the same reference numerals are given to the same, the same, or corresponding components.

Embodiment 1.
FIG. 1 is a block diagram showing a configuration example of an error correction device according to a first embodiment of the present invention.
As shown in FIG. 1, the error correction device 10 includes an input unit 1, a coding device 2, a transmitting unit 3, a receiving unit 5, a decoding device 6, and an output unit 7.

The error correction device 10 is, for example, a device applied to a terminal device constituting a high-speed transmission system. The error correction device 10 adds an error correction code to the information transmitted via the transmission line, that is, the data, and corrects the error generated in the received data. The input unit 1, the coding device 2, and the transmitting unit 3 are components particularly related to data transmission, and the receiving unit 5, the decoding device 6, and the output unit 7 are components particularly related to data reception. .. The error correction device 10 may be used for other purposes such as writing and reading data in the storage device.

The input unit 1 outputs the data to be transmitted to the coding device 2. The coding device 2 is the coding device according to the first embodiment, and generates a plurality of external codes and a plurality of internal codes as codes for error correction from the data input from the input unit 1, and each of the generated codes is generated. Add a code to the data. The transmission unit 3 transmits the data to which each code is added as a frame. The frame is modulated and transmitted by the transmission unit 3. The outer code is, for example, for hard determination decoding, and the inner code is, for example, for soft determination decoding.

The receiving unit 5 demodulates the frame received via the transmission line and outputs it to the decoding device 6. The decoding device 6 is the decoding device according to the first embodiment, extracts each code in the demodulated frame, and uses each of the extracted codes to detect an error generated in the data in the frame and detect an error. If this is the case, correct the error. As a result, error-free data is output from the decoding device 6 to the output unit 7. The output unit 7 provides an interface for outputting the data from the decoding device 6 to the outside.

As described above, the error correction device 10 includes a coding device 2 and a decoding device 6. Data can be sent and received in only one direction. For this reason, the error correction device 10 may be equipped with only one of the coding device 2 and the decoding device 6.

FIG. 2 is a block diagram showing a configuration example of a coding device according to the first embodiment of the present invention. Next, with reference to FIG. 2, the configuration and operation of the coding device 2 will be described in detail.

As shown in FIG. 2, the coding device 2 includes a rate conversion memory 21, a bit replacement circuit 22, M external coding circuits 23, a bit reverse switching circuit 24, N internal coding circuits 25, and a mapping circuit. 26 is included. They are connected in parallel with A × N × M bits, respectively. A, N and M are all integers of 1 or more. The error correction codes of the internal code and the external code are not particularly limited. However, here, for convenience of explanation, the inner code is the organization code type LDPC code in which the parity bit follows the information bit series, and the outer code is the organization code type BCH in which the parity bit follows the information bit series. It is assumed to be a sign. The BCH code is a block code.

The rate conversion memory 21 is provided to adjust the transmission rate of the information bit series input from the input unit 1 as the object of coding to the addition of the parity bit which is the outer code and the parity bit which is the inner code. Memory. In the information bit sequence, a dummy section is provided in which the rate conversion memory 21 is used and the insertion of each parity bit is assumed. When the information bit sequence provided with the dummy section is input from the input unit 1, the rate conversion memory 21 can be omitted. The A × N × M bit data are all significant data or data including significant data and dummy data.

The bit length of the external code sequence, that is, the bit length obtained by combining the information bit length and the parity bit length is a bit length divisible by A × N. Further, the bit length of the internal code sequence, that is, the bit length including the information bit length and the parity bit length is a bit length divisible by A × M. However, the parity bit length of the internal code does not necessarily have to be divisible by A × M. However, if it is not divisible by A × M, it is necessary to add a dummy bit after the parity bit length so that it is divisible by A × M. Adding such dummy bits has the disadvantage of increasing the apparent transmission rate. Further, when the information bit length, the parity bit length, or both of the internal code series is variable, it is preferable to add or subtract in A × M bit units. When the information bit length, the parity bit length, or both of the external code series is variable, it is preferable to add or subtract in A × N bit units.

The A × N × M bit information output from the rate conversion memory 21 passes through the bit exchange circuit 22, M external coding circuits 23, and the bit reverse exchange circuit 24 to N internal coding circuits 25. Entered. Therefore, the bit replacement circuit 22 is fixedly connected to the external coding circuit 23 so that the information of the A bit among the A × M bits input to each internal coding circuit 25 is input. There is. That is, the bit replacement circuit 22 is assigned A bit of the A × M bit information input to each of the N internal coding circuits 25 to one external coding circuit 23.

The M external coding circuits 23 input information in A × N bit units from the bit replacement circuit 22, and perform coding calculation processing using the input information. The parity bit generated as the external code by this coding operation processing is replaced with the dummy bit in the corresponding dummy section in the A × N bit. Therefore, each external coding circuit 23 outputs information of A × N bits including the generated external code to the bit reverse exchange circuit 24. The A × N bit information corresponds to the first codeword in the first embodiment. The portion obtained by removing the parity bit from the A × N bit information corresponds to the first information.

Here, the total bit length of the information bit length and the parity bit length of the external code sequence is set to be a bit length divisible by A × N, but this is not always the case. That is, the total bit lengths of the M external code sequences may be divisible by A × N, and the bit lengths assigned to the M external code coding circuits 23 may be different. When the bit lengths are different in this way, it is necessary to adjust the information output from the rate conversion memory 21 according to the bit lengths of each external coding circuit 23.

The bit reverse exchange circuit 24 is a fixedly connected circuit like the bit exchange circuit 22. The bit reverse exchange circuit 24 converts the A × N × M bit information obtained by inputting A × N bit information from each of the M external coding circuits 23 into N A × M bit information. It is divided and A × M bit information is output to N internal coding circuits 25.

The bit reverse exchange circuit 24 restores the positional relationship of the information bits in the A × N bit information input from each of the M external coding circuits 23, and divides the information into N A × M bit information. .. The information of each A × M bit includes the information of A bit input from M external coding circuits 23. Therefore, the parity bits generated by one external coding circuit 23 are divided and output by the bit reverse switching circuit 24 into N internal coding circuits 25 as in the case of the target information bit series.

The N internal coding circuits 25 perform coding processing using the information bits in the A × M bits to generate parity bits as internal codes. The generated parity bit is replaced with the corresponding dummy bit in the A × M bits. As a result, each internal coding circuit 25 adds the parity bit generated by itself while keeping the information bit in the A × M bit and the parity bit generated by each external coding circuit 23 as they are. The A × M bit information thus obtained is output from each internal coding circuit 25 to the mapping circuit 26. The A × M bit information corresponds to the second codeword in the first embodiment. The portion of the A × M bit information excluding the generated parity bit corresponds to the second information.

The mapping circuit 26 inputs A × M bit information from each internal coding circuit 25, and uses the input A × M bit information to generate information to be stored as a payload in a frame. The transmission unit 3 generates a frame in which the information input from the mapping circuit 26 is stored, modulates the generated frame, and transmits the frame.

For A × N × M bits, M and N are common divisors. Therefore, when N is an integer of 2 or more, the parity bits, which are the outer codes, are spatially and temporally dispersed when the inner code is generated. With such dispersion, it is possible to correct the generated error with a higher probability even in the case of information transmission via a transmission line in which an error is likely to occur. The bit replacement circuit 22 and the bit reverse replacement circuit 24 are fixedly connected circuits. Therefore, as compared with the prior art (see, for example, Patent Document 1), which requires a selector for each coding circuit and a counter for the operation of each selector in order to perform different replacement for each time, the coding apparatus The scale can be suppressed. By reducing the scale of the coding device, it is possible to reduce the power consumption and the manufacturing cost.

FIG. 3 is a diagram illustrating an operation example of the coding device according to the first embodiment of the present invention. Next, the operation of the coding device 2 will be described in more detail with reference to FIG.

FIG. 3 assumes that information for A × N × M bits is input from the input unit 1, and shows parity bits that are sequentially generated and added as codes using the input information. Reference numeral 201 denotes an information bit sequence to be transmitted, and 202 is dummy data for the parity bit added to the information bit sequence 201 as an external code or an internal code. The information bit sequence 201 and the dummy data 202 are information for A × N × M bits. The information bit sequence 201 corresponds to the information sequence in the first embodiment.

The information bit sequence 201 is burst-input from the input unit 1 with, for example, a K clock (Kclk). When the dummy data 202 is provided, the dummy data 202 is burst-input from the input unit 1 with, for example, a P clock (Pclk). When the dummy data 202 is not input, the information bit sequence 201 may be burst-input from the input unit 1 with the K + P clock. That is, in the case of only the information bit sequence 201, the transmission rate may be reduced to K / (K + P) times.

In the rate conversion memory 21, information for A × N × M bits is burst output when the L clock can be output at the transmission rate after encoding. This A × N × M bit × L clock information is equivalent to N pieces of A × M bit information. As shown in FIG. 3, the burst output is a set of the burst output of the L clock (Lclk) for the information bit series 201 and the burst output of the Q clock (Qclk) for the dummy data 202, for a total of N times. It is said. Reference numeral 211 is an information bit which is a burst output portion of the L clock in the information bit series 201, and reference numeral 212 is a dummy bit which is a burst output portion of the Q clock in the dummy data 202.

In the example shown in FIG. 3, the last set of information bits 213 is the burst output of the LR clock. As a result, the dummy bit 214 for the burst output of the R clock follows the information bit 213. The dummy bit 214 is for a parity bit generated as an external code. In the first embodiment, the information bit 211 corresponds to the second information. The information bit 213 and the parity bit 221 replaced by the dummy bit 214 following it also correspond to the second information.

The dummy bits 212 and 214 may be added by stopping the reading of data from the rate conversion memory 21. The information bits 211 and 213 and the dummy bits 212 and 214 are all bit strings composed of a plurality of bits.

The A × N × M bit information output from the rate conversion memory 21 as described above is divided into M A × N bit information through the bit exchange circuit 22, and input to each external coding circuit 23. Will be done. The information of M A × N bits includes the divided portion of the dummy bits 214. The information of M A × N bits corresponds to the first codeword group in the first embodiment.

As shown in FIG. 3, the bit reverse exchange circuit 24 returns the information of A × N bits input from each external coding circuit 23 to the arrangement at the time of input to the bit exchange circuit 22, and N A × M bits. It is divided into the information of the above and output to each internal coding circuit 25. The A × M bit information includes one information bit 211 and one dummy bit 212, except for the one not located at the end. The information of the A × M bit located at the end includes the information bit 213, the dummy bit 212, and the parity bit 221 replaced with the dummy bit 214. As a result, the A × M bit information output to each internal coding circuit 25 includes a dummy bit 212 that is replaced with the parity bit generated as the internal code.

Each internal coding circuit 25 generates a parity bit which is an internal code by a coding process using information other than the dummy bit 212, and replaces the parity bit with the dummy bit 212 as the parity bit 231. Each internal coding circuit 25 outputs the information of A × M bits after the replacement to the mapping circuit 26. The information of N A × M bits corresponds to the second codeword group in the first embodiment.

As described above, in the first embodiment, the rate conversion memory 21, the bit replacement circuit 22, the M external coding circuits 23, the bit reverse switching circuits 24, and the N internal coding circuits 25 are interleaved with each other. It is connected by A × N × M bits. A × N × M is divisible by the parallel number M of the outer coding circuit 23 and the parallel number N of the inner coding circuit 25, respectively. When different error correction codes are adopted as the external code and the internal code and N is 2 or more, a concatenated code having a strong correction ability can be added by the coding device 2 having a small circuit scale even in high-speed transmission of 1 Tbps class. it can.

Further, in the first embodiment, the fixed connection bit reverse exchange circuit 24 is inserted in front of the M outer coding circuits 23, and the M outer coding circuits 23 and the N inner coding circuits 25 are combined. A fixed-connection bit reverse exchange circuit 24 is inserted between the two. As a result, interleaving is performed between after the generation of the external code and before the generation of the internal code, and the error remaining in a part of the internal code is dispersed into M external codes, and the correction capability is relatively small. It is possible to realize a coding device 2 capable of strongly error-correcting even with a code. As for the information bit portion, the output of the rate conversion memory 21 and the information bit output of the N internal coding circuits 25 are arranged in the same order. Therefore, the output of the rate conversion memory 21 may be arranged in consideration of mapping, and the design can be facilitated. Further, since the inner code is dispersed in the outer code not only in the space but also in the time direction, the parity bit can be easily added to the outer code. As a result, the overhead for adding the parity bit to the external code can be made smaller.

The insertion positions of the bit replacement circuit 22 and the bit reverse replacement circuit 24 may be before and after the N internal coding circuits 25. That is, one of the M outer coding circuits 23 and the N inner coding circuits 25 may be N inner coding circuits 25. When such an insertion position is adopted, interleaving is performed between the same N A × M bit information before and after the N internal coding circuits 25.

In the example shown in FIG. 3, if L + Q is an even number, the input bit width to the internal coding circuit 25 may be doubled and the operating frequency may be halved. If K + R is an even number, the external coding circuit 23 may also double the input bit width and halve the operating frequency. In this way, the operating frequency can be lowered even in high-speed transmission.

Further, in the first embodiment, information having the same number of bits is output to each of the external coding circuits 23 and each of the internal coding circuits 25. However, the total number of bits may be A × N × M bits, and the number of bits of information output to each external coding circuit 23 or each internal coding circuit 25 may be different. For this reason, the information constituting the information bit sequence and the arrangement of each parity bit in the A × N × M bits are not particularly limited. For example, the parity bit 221 may be divided into N bits, and the divided portion may be combined with each information bit 211.

In the first embodiment, a fixed transmission rate is assumed. However, the transmission rate may vary. For example, when the transmission rate is halved, the number of bits to be connected in parallel is changed from A × N × M to 1/2 × A × N × M, and half of the M external coding circuits 23, Only half of the N internal coding circuits 25 may be used respectively. In this case, the bit replacement circuit 22 and the bit reverse replacement circuit 24 need to correspond to fluctuations in the number of information output destinations. If the state at this time is a normal transmission rate, the M external coding circuits 23 and the N internal coding circuits 25 are all operated to correspond to twice the normal transmission rate. Can be done.

FIG. 4 is a block diagram showing a configuration example of the decoding device according to the first embodiment of the present invention. Next, with reference to FIG. 4, the configuration and operation of the decoding device 6 will be described in detail.

As shown in FIG. 4, the decoding device 6 includes a demapper 61, N internal code decoding circuits 62, a bit exchange circuit 63, M external code decoding circuits 64, and a bit reverse exchange circuit 65. The decoding device 6 causes each of the N internal code decoding circuits 62 to perform soft determination decoding of the information in the frame input as the received signal from the receiving unit 5 by the demapper 61. As a result, M external code decoding circuits 64 are input by the bit exchange circuit 63 fixedly connected to the bit reverse exchange circuit 24, and each external code decoding circuit 64 is made to perform external decoding. The result is replaced with the arrangement output by the rate conversion memory 21 by the bit reverse replacement circuit 65, which is fixedly connected to the bit replacement circuit 63. The information after this replacement is the decoding result.

The receiving unit 5 demodulates the received frame, and outputs an S-bit soft determination bit indicating the reliability of the bit to the demapper 61 for each bit constituting the demodulated frame. The A × N × M bit information is stored in a frame as, for example, a payload. As a result, the demapper 61 outputs the S × A × M bit information to each internal code decoding circuit 62 as a result of dividing the A × N × M bit information into N A × M bit information.

Each of the N internal code decoding circuits 62 performs soft determination decoding. When soft-determination decoding is performed using an LDPC code or the like, it is often performed repeatedly. Therefore, it is desirable that the code length of the internal code, that is, the number of bits of the dummy bit 212 shown in FIG. 3, is such that an appropriate repetitive operation can be performed until the input of the next information is completed. The longer the code length, the larger the circuit scale and the processing delay.

Each of the N internal code decoding circuits 62 outputs the hard determination bits of A × M bits to the bit replacement circuit 63 as a result of performing the soft determination decoding. Each internal code decoding circuit 62 corrects an error by rewriting the value of the corresponding bit in the A × M bit, and rewrites the parity bit corresponding to the internal code with dummy data. The N hard determination bits of A × M bits correspond to the second information group in the first embodiment.

As described above, the bit replacement circuit 63 is fixedly connected to the bit reverse replacement circuit 24. As a result, the bit replacement circuit 63 divides the A × N × M bit information so that the A bits in the information output by each internal code decoding circuit 62 are evenly output to each external code decoding circuit 64. Then, A × N bit information is output to each external code decoding circuit 64. The information of each A × N bit includes a hard determination bit of the parity bit generated by any of the external coding circuits 23.

The M external code decoding circuits 64 use the rigidity bit of the parity bit to correct errors generated in other information as necessary. Error correction is performed by rewriting the value of the corresponding bit in the A × N bits. As a result, each external code decoding circuit 64 outputs A × N bit information to the bit reverse exchange circuit 65. Each external code decoding circuit 64 also rewrites the parity bit corresponding to the external code in the A × N bit information to dummy data. The information of M A × N bits corresponds to the first information group in the first embodiment.

As described above, the bit reverse replacement circuit 65 is a circuit that is fixedly connected to the bit reverse circuit 22. As a result, the bit reverse exchange circuit 65 returns the A × N bit information input from each external code decoding circuit 64 to the arrangement output by the rate conversion memory 21, and outputs the A × N × M bit information. The bit reverse exchange circuit 65 may output the information bit sequence 201 as the decoding result.

As described above, in the first embodiment, N internal code decoding circuits 62 and M external code decoding circuits 64 are connected by A × N × M bits. A × N × M is divisible by the parallel number N of the internal code decoding circuit 62 and the parallel number M of the external code decoding circuit 64, respectively. Different error correction codes are adopted as the external code and the internal code, and N is 2 or more. Therefore, even in 1 Tbps class high-speed transmission, a concatenated code having a strong correction ability can be decoded by the decoding device 6 having a small circuit scale.

Further, in the first embodiment, N internal code decoding circuits 62 and M external code decoding circuits 64 are connected by A × N × M bits, interleaving by exchanging bits between them, and subsequent decoding. I try to interleave. No memory is used for interleaving and deinterleaving. By adopting such a configuration, it is possible to realize a decoding device 6 that performs decoding by a concatenated code at high speed at a lower cost. Interleaving and deinterleaving may be performed before and after the N internal code decoding circuits 62 because it is necessary to match the processing at the time of coding.

Similarly to the coding device 2, the transmission rate of the decoding device 6 does not have to be fixed.
For example, the number of operations in the N inner code decoding circuits 62 and the M outer code decoding circuits 64 may be increased or decreased according to the transmission rate. More specifically, for example, when the transmission rate corresponds to a normal half, only half of the N internal code decoding circuits 62 and the M external code decoding circuits 64 are used, and the information from the demapper 61 is 1 The / 2 × N internal code decoding circuits 62 may be alternately input. In this case, for example, the bit replacement circuit 63 corresponds to the information output alternately by the 1/2 × N internal code decoding circuits 62, and outputs the information only to the 1/2 × M external code decoding circuits 64. All you have to do is replace the bits. In this case, the interval until the next information is input from the demapper 61 to the internal code decoding circuit 62 is doubled. Therefore, the code length of the internal code can be set so that more repetitive operations can be performed. The error correction performance can be improved by enabling more repetitive operations.

Here, a parameter example will be described assuming that the inner code is an LDPC code having a strong error correction capability by soft determination decoding and the outer code is a BCH code which is one of the block codes.

The parallel number M of the external coding circuit 23 that generates the BCH code as the external code is 16, and the parallel number N of the internal coding circuit 25 that generates the LDPC code as the internal code is 4. At this time, assuming that A is 16, 64-bit information is assigned to one external coding circuit 23, and 256-bit information is assigned to one internal coding circuit 25. A × N × M = 16 × 4 × 16 = 1024. As the bit replacement circuit 22 and the bit reverse replacement circuit 24, those having this number of terminals on the input side and the output side, respectively, and having a fixed connection between the terminals on the input side and the output side may be adopted.

Under such an assumption, one inner coding circuit 25 is assigned one bit among the parity bits generated by the 16 outer coding circuits 23. On the contrary, in the decoding device 6, 16 bits are assigned to one external code decoding circuit 64 as the external code output by each of the four internal code decoding circuits 62.

In coding, the inner code encodes the outer code dispersed in the time direction. Therefore, even if an external code having a strong correction ability is adopted, the overhead in concatenated coding can be reduced. For example, in FIG. 3, the dummy bit 214 in which 16 external codes are stored is set to 48 bits. Assuming that the parallel number N of the internal coding circuit 25 is 4 and the clock number L required for transmission of the information bit 211 is 21, the code length of one external code is 1024 × 21 × 48/16 = 64512 bits. .. This means that a BCH code having 16 bits per bit correction can be adopted. The 64512 is divisible by 64, which is the input / output bit width of one external coding circuit 23. Therefore, if it is a multiple of 4, the information bit to be input / output to the external coding circuit 23 and the parity bit can be separated. There is no need to add dummy bits.

Similarly, since the input / output bit width of the internal coding circuit 25 is 256 bits, if it is a multiple of 4, the information bit to be input / output and the parity bit can be separated. That is, all the parity bits can be distributed in the spatial and temporal directions. There is no need to add dummy bits. For this reason, in the QC (Qusi-Cycloc) -LDPC code often used as a kind of LDPC code, it is preferable that the QC size is a common divisor of 256.

Further, if the number of clocks Q required for the transmission of the parity bit 231 of the LDPC code is set to an odd number, L (= 21) + Q becomes an even number. Therefore, even with the same frame configuration, the input / output bit width can be doubled and the clock frequency can be halved. Such changes
For example, it can be supported by inserting a circuit that performs bus width conversion between the bit reverse exchange circuit 24 and each internal coding circuit 25. This method can also be applied to the decoding device 6.

As for the external code, if the sum of the information bit sequence input clock K and the external code parity clock R in FIG. 2 is an even number, the input / output bit width of the external coding circuit 23 is doubled in the same manner as described above. This makes it possible to halve the clock frequency. This method can also be applied to the decoding device 6.

If the number of clocks K + R and the number of clocks L + Q are both common multiples of an integer T of 2 or more, the connection bus width of the external coding circuit 23 and the internal coding circuit 25 should be T times and the clock frequency should be 1 / T. Can be done. At this time, when the number of clocks L is an odd number, it can be dealt with by providing a circuit for adjusting the insertion of the dummy bit 112 for the internal code between the bit reverse exchange circuit 24 and each internal coding circuit 25. This also applies to the internal code decoding circuit 62 and the external code decoding circuit 64.

1 input unit, 2 encoding device, 3 transmitting unit, 5 receiving unit, 6 decoding device, 7 output unit, 10 error correction device, 21 rate conversion memory, 22-bit replacement circuit, 23 external coding circuit, 24-bit reverse replacement Circuit, 25 internal coding circuit, 26 mapping circuit, 61 demapper, 62 internal code decoding circuit, 63 bit replacement circuit, 64 external code decoding circuit, 65 bit reverse replacement circuit, 201 information bit series, 202 dummy data, 211, 213 Information bits, 212, 214 dummy bits, 221 and 231 parity bits.

The coding apparatus according to the present invention uses the input first information to generate an external code for error correction, and outputs a plurality of codewords in which the external code is added to the first information. A coding circuit and a plurality of internal coding circuits that generate an internal code for error correction using the input second information and output a second code word in which the internal code is added to the second information. , A first codeword group that is placed in front of one of a plurality of external codewords and a plurality of internal codewords and includes an information sequence to be encoded, or a plurality of first codewords. Is divided, and the information obtained by dividing the information series or the first codeword group is arranged as the first information or the second information in a replacement circuit to be output to one side, and is arranged after the other side. A plurality of external codes are provided, including a reverse exchange circuit that returns the information of the information series constituting the codeword group of 1 or the second codeword group including the plurality of second codewords to the positional relationship of the information series. The number of bits of all external codes in the first codeword output by each of the conversion circuits is a value that can be divided by the total number of internal coding circuits, and is the total number of clocks required for internal transfer of the information series and all external codes. When the total number of clocks required for internal transmission of the second information, and the inner code together, Ru 2 or more integer multiples der.

The decoding device according to the present invention inputs a second code word to which an internal code is added to the second information, corrects an error in the second information using the internal code, and outputs the second information. A plurality of internal code decoding circuits and a first code word in which an external code is added to the first information are input, error correction of the first information is performed using the external code, and the first information is obtained. A second code word group that is arranged in front of one of a plurality of output code decoding circuits, a plurality of internal code decoding circuits, and a plurality of external code decoding circuits and includes a plurality of second code words. Alternatively, the second information group including a plurality of second information is divided, and the second code word group or the information obtained by dividing the second information group is the second code word or the first code word. As a code word, an information sequence to be encoded, which comprises a replacement circuit to be output to one side and a first information group arranged after the other and containing a second information group or a plurality of first information. The information sequence is provided with an inverse replacement circuit that returns the information of the information sequence to the positional relationship of the information sequence, and the number of bits of all the outer codes in the first code word is a value that can be divided by the total number of the internal coding circuits. and the total number of clocks required for the internal transfer of all of the outer code, the total number of clocks required for internal transmission of the second information, and the inner code together, Ru 2 or more integer multiples der.

Further, if the number of clocks Q required for the transmission of the parity bit 231 of the LDPC code is set to an odd number, L (= 21) + Q becomes an even number. Therefore, even with the same frame configuration, the input / output bit width can be doubled and the clock frequency can be halved. Such changes can be dealt with by inserting a circuit that performs bus width conversion between bit reverse switching circuit 24 and each of the coding circuit 25 if example embodiment. This method can also be applied to the decoding device 6.

Coding apparatus according to the present invention, by using the first information input, and generates an outer code for error correction, and outputs the first codeword obtained by adding the outer code to the first information A plurality of external coded circuits and a plurality of input second information are used to generate an internal code for error correction, and a plurality of second codewords in which the internal code is added to the second information are output. An information sequence arranged in front of one of the inner coding circuit, the plurality of outer coding circuits, and the plurality of inner coding circuits and to be coded, or a plurality of the first codes. The first codeword group including words is divided, and the information series or the information obtained by dividing the first codeword group is used as the first information or the second information. The information of the information series which is arranged after the one and constitutes the first codeword group or the second codeword group including the plurality of the second codewords. The total number of bits of the external code constituting the first codeword output by the plurality of external coded circuits is the total number of bits of the internal coded circuit. It is a value divisible by the total number, and the total number of clocks required for internal transfer of the information series and all external codes and the total number of clocks required for internal transmission of the second information and the internal code are both 2 or more. Is an integral multiple of.

The decoding device according to the present invention inputs a second code word to which an internal code is added to the second information, corrects an error in the second information using the internal code, and performs the error correction of the second information. enter a plurality of inner code decoding circuit for outputting information, respectively, the first codeword is the outer code added to the first information, by using the outer code, performs error correction of the first information a plurality of outer code decoding circuit for outputting the first information, respectively, said plurality of inner code decoding circuit, and is arranged in front of one of the plurality of outer code decoding circuit, a plurality of the second Obtained by dividing the second code word group including the code word or the second information group containing the plurality of the second information, and dividing the second code word group or the second information group. A replacement circuit that outputs the information to be output as the second code word or the first code word to the one, and the second information group or a plurality of the first information groups arranged after the one. All the above in the first code word are provided with a reverse replacement circuit that returns the information of the information series to be encoded to the positional relationship of the information series, which constitutes the first information group including the information. The number of bits of the external code is a value that can be divided by the total number of internal coding circuits, and is the total number of clocks required for internal transfer of the information series and all external codes, the second information, and the internal code. The total number of clocks required for internal transmission is an integral multiple of 2 or more.

In coding, the inner code encodes the outer code dispersed in the time direction. Therefore, even if an external code having a strong correction ability is adopted, the overhead in concatenated coding can be reduced. For example , the parallel number N of the internal coding circuit 25 is 4, the clock number L required for transmission of the information bit 211 is 21 , the bit width is 1024 (= A × N × M) bits, and the information bit 211 of the L clock. Let the number of be 48. However, the information bit of the last L clock is composed of the information bit 213 and the dummy bit 214 of the external code. The dummy bit 214 in which 16 external codes are stored is the R clock in the L clock, and has a relationship of L> R. In this assumption, the code length of one external code is 1024 × 21 × 48/16 = 64512 bits. This means that a BCH code having 16 bits per bit correction can be adopted. The 64512 is divisible by 64, which is the input / output bit width of one external coding circuit 23. Therefore, if it is a multiple of 4, the information bit to be input / output to the external coding circuit 23 and the parity bit can be separated. There is no need to add dummy bits.

Claims (5)

A plurality of external coding circuits that generate an external code for error correction using the input first information and output a first code word in which the external code is added to the first information.
A plurality of internal coding circuits that generate an internal code for error correction using the input second information and output a second code word in which the internal code is added to the second information.
A first code that is arranged in front of one of the plurality of external coding circuits and the plurality of internal coding circuits and includes an information sequence to be encoded, or a plurality of the first codewords. A replacement circuit that divides a word group and outputs the information series or the information obtained by dividing the first codeword group as the first information or the second information to the one.
The information of the information series arranged after the one and constituting the first codeword group or the second codeword group including the plurality of the second codewords is returned to the positional relationship of the information series. Reverse replacement circuit and
A coding device comprising. The internal code is a code for soft determination decoding, and the external code is a block code for hard determination decoding.
The coding device according to claim 1. The number of bits of all the external codes in the first codeword output by the plurality of external coding circuits is a value that can be divided by the total number of internal coding circuits.
The coding device according to claim 1. A plurality of internal codes for inputting a second codeword in which an internal code is added to the second information, correcting errors in the second information using the internal code, and outputting the second information. Decoding circuit and
A plurality of external codes for inputting a first codeword in which an external code is added to the first information, correcting errors in the first information using the external code, and outputting the first information. Decoding circuit and
A second codeword group, which is arranged in front of one of the plurality of internal code decoding circuits and the plurality of external code decoding circuits and includes the plurality of the second codewords, or a plurality of the second codewords. The second codeword or the first codeword is obtained by dividing the second information group containing information and dividing the second codeword group or the second information group. As a replacement circuit that outputs to one of the above,
The position of the information series is the information of the information series to be encoded, which is arranged after the one and constitutes the second information group or the first information group including the plurality of the first information. A reverse replacement circuit that returns to the relationship,
Decoding device. The coding device according to any one of claims 1 to 3 and at least one of the decoding devices according to claim 4 are provided.
Error correction device.

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