JP2010200247A - Digital transmission system and digital transmission method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital transmission system and method in which error correction performance is improved by enabling error protection of a payload, having the same length as that of an OTU frame according to a concatenated coding scheme. <P>SOLUTION: The present invention relates to a digital transmission system for performing concatenated coding by combining a plurality of error-correcting codes. The digital transmission system is provided with an error-correcting coding device which is provided on a transmission side of the system, and uses an RS code or any other block code as an outer code and uses an LDPC code as an inner code to perform concatenated coding for applying error-correcting coding after interleaving, thereby error-protecting a payload having the same length as that of an OTU frame. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a digital transmission system and a digital transmission method, and more particularly to an error correction code technique.

  A conventional error correction coding method for optical communication, for example, is shown in FIG. 709-compliant (ITU: International Telecommunication Union) frame format (OTUk frame 201: k is k = 1, 2, 3 depending on the transmission rate. Hereinafter, abbreviated as OTU frame 201) 16 bytes × As shown in FIG. 6B, four series (128 bits × 4 series) overhead (OH) 226 and 3808 bytes × 4 series (30464 bits × 4 series) of payload data 223 are serial / parallel converted. With respect to the payload data 203 of 128 × 239 × 4 bits, an RS (Reed Solomon) code having a code length of 255 bytes, an information length of 239 bytes, and an 8-bit per byte is shown in FIG. In a manner indicated by 211, a 16 × 4 codeword parallel operation is performed and transmitted. The RS parity sequence 213 generated by the RS encoding is shifted to the right side of the frame (see, for example, Non-Patent Document 1). In FIG. 6, reference numeral 212 denotes an RS codeword sequence order, 202 denotes an FEC frame, 204 denotes a payload data sequence order, and 205 denotes a dummy sequence.

"ITU-T G.709", INTERNATIONANL TELECOMMUNUCATION UNION, pp.24-25,94-95, Mar. 2003

  In the error correction coding in the conventional digital transmission system, the effect for protecting the payload data of the OTU frame is limited by the error correction capability of the RS (255, 239) code. For this reason, there is a problem that the system margin of the optical transmission system depends on the error correction characteristics of the RS code.

  The present invention has been made to solve the above-described problems. For payload data of an OTU frame, an RS code or other block code is used as an outer code, and an LDPC (Low-Density Parity- It is an object of the present invention to obtain a digital transmission system and a digital transmission method for performing error correction coding so as to improve error correction performance by a concatenated code method combining Check) codes.

  The present invention is a digital transmission system that performs concatenated coding combining a plurality of error correction codes, and is provided on the transmission side of the system, and uses an RS code or other block code as an outer code and an LDPC code as an inner code A digital transmission system and method comprising an error correction encoding device that performs concatenated encoding for performing error correction encoding after each interleaving and error-protects a payload having the same length as an OTU frame .

  In the present invention, a concatenated encoding method using an RS code or other block code as an outer code and an LDPC code as an inner code enables payload error protection with the same length as an OTU frame, and improves error correction performance. It was.

It is a block diagram which shows the structure of the digital transmission system provided with the error correction coding apparatus and error correction decoding apparatus by one Embodiment of this invention. It is a block diagram which shows the specific structural example of the error correction encoding apparatus of FIG. It is a block diagram which shows the specific structural example of the error correction decoding apparatus of FIG. It is a figure for demonstrating the operation | movement in the digital transmission system by this invention. It is a figure for demonstrating the operation | movement in the digital transmission system by this invention following FIG. It is a figure for demonstrating the conventional error correction encoding method. It is a figure for demonstrating the conventional error correction encoding method. It is a block diagram which shows another specific structural example of the error correction encoding apparatus of FIG. It is a block diagram which shows another specific structural example of the error correction decoding apparatus of FIG. It is a figure for demonstrating another operation | movement in the digital transmission system by this invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a digital transmission system (hereinafter simply referred to as “transmission system”) provided with an error correction coding apparatus and an error correction decoding apparatus according to an embodiment of the present invention.

  In FIG. 1, a transmission system 30 includes an error correction encoding device 31 connected to an information source, a modulator 32 connected to the error correction encoding device 31, a communication path 33 connected to the modulator 32, A demodulator 41 connected to the modulator 32 via the communication path 33, an A / D (analog / digital) converter 42 connected to the demodulator 41, and an error correction connected to the A / D converter 42. The error correction decoding device 43 is connected to the receiver side. The modulator 32, the communication channel 33, the demodulator 41, and the A / D converter 42 each have a device configuration generally used in a digital transmission system. Note that the codeword sequence output of the error correction encoding device 31 is a digital signal, and the transmission signal output of the modulator 32 that has been input and modulated is an analog signal.

  FIG. 2 is a block diagram showing a specific configuration example of the error correction coding apparatus 31 of FIG. In FIG. 2, an error correction coding device 31 includes a first demultiplexing circuit 11, a first frame generation circuit 12, a first interleaving circuit 13, a first FEC coding circuit 14 (outer code coding means). ), A second interleave circuit 15, a second FEC encoding circuit (inner code encoding means) 16, a third interleave circuit 17, and a first multiplexing circuit 18.

  In the error correction coding apparatus 31, the first demultiplexing circuit 11 on the uppermost stage generates a second information sequence (parallel) based on the first information sequence (serial). The first frame generation circuit 12 generates first information + OH (overhead) + dummy series (parallel) based on the second information series.

  The first interleave circuit 13 generates second information + OH + dummy series (in parallel after rearrangement) based on the first information + OH + dummy series. The first FEC encoding circuit 14 generates a first codeword sequence (parallel) based on the second information + OH + dummy sequence.

  The second interleave circuit 15 generates a second codeword sequence (in parallel after rearrangement) based on the first codeword sequence. The second FEC encoding circuit 16 generates a third codeword sequence (parallel) based on the second codeword sequence.

  The third interleave circuit 17 generates a fourth codeword sequence (parallel after reordering) based on the third codeword sequence. Then, in the error correction encoding device 31, the first multiplexing circuit 18 on the lowermost stage generates a fifth codeword sequence (serial) based on the fourth codeword sequence.

  Next, the operation of the error correction coding apparatus 31 will be described. In FIG. 2, first, the first information series input to the error correction encoding device 31 in a serial order is converted into a parallel order by the first demultiplexing circuit 11. The parallel number at this time is defined as “n”. The parallel number n can be defined by an arbitrary integer. However, when a frame conforming to the OTU frame 51, which is a feature of the present invention, is considered, n = 128 is preferable.

  Subsequently, the first frame generation circuit 12 adds an OH including a synchronization control signal in addition to the n-parallel second information series generated from the first demultiplexing circuit 11 and error correction. An area to which the parity sequence of the code is added is secured, and further, OH and a dummy series are added, and information in which the transmission rate is increased by the addition of these redundant areas is generated. That is, when the coding rate based on the information length Kc of the concatenated code and the code length Nc is Kc / Nc, the transmission rate is increased by Nc / Kc.

  The first information + OH + dummy sequence generated here is formed by the payload 103 of the OTUkV frame 51 shown in FIG. 4B, the RS dummy sequence 53, and the LDPC dummy sequence 54. The OTUkV frame 51 is an ITU-T GG. 709 recommendation, pp. It conforms to the frame shown in 101-103. Here, k = 1, 2, 3 depending on the transmission rate. Hereinafter, it is abbreviated as the OTU frame 51. Further, the lengths of the RS dummy series 53 and the LDPC dummy series 54 are shown as an example, and it is possible to set lengths other than those shown in the figure. Note that reference numeral 104 in FIG. 4B indicates the sequence of payload data. Note that OH is included in one column at the left end of the payload 103, but is omitted in the figure.

  The first interleave circuit 13 rearranges the n-parallel sequence composed of the input information sequence from the first frame generation circuit 12, the OH and the dummy sequence in a predetermined order, and outputs the result in n-parallel. To do. The rearrangement means of the first interleave circuit 13 rearranges the sequence order of the OTU frames 51 shown in (b) of FIG. 4 so as to become the RS codeword frame 61 shown in (a) of FIG. In FIG. 4, a payload 103, an RS dummy sequence 53, an LDPC dummy sequence 54, and a block obtained by dividing an OTU frame 51 defined as an FEC frame 52 into one unit with one column of n = 128 rows as one unit. Sort by. In FIG. 4A, 62 indicates the sequence order of RS codeword frames, 63 indicates an RS parity sequence, 64 indicates a valid area, and 65 indicates an invalid area. Note that the rearrangement shown in FIG. 4 shows an example, and the configuration of the present invention is possible even with other rearrangement methods.

Returning to FIG. 2, next, the first FEC encoding circuit 14 applies a predetermined code length N1, information length K1, Galois field GF (2), or the like to the sequence input from the first interleave circuit 13. Error correction coding of the block code on the Galois field GF (2 ^m ) is performed. As a result, the first code word sequence is generated in n parallel from the first FEC encoding circuit 14.

Here, the error correction code of the outer code is described as the block code, but it can also be configured by other codes. Also, for example, in the case of a BCH code on the Galois field GF (2), the encoding operation is performed with an arbitrary parallel number of n or less. In the case of an RS code on the Galois field GF (2 ^m ), it is performed with n / m parallel or an arbitrary parallel number of n / m or less. In addition, the type of outer code encoded in parallel operation is not necessarily one type as long as the frame format constraint condition is satisfied, and a plurality of types of codes may be used.

For example, in the case of n = 128 shown in FIG. 4, RS (992, 956) code on Galois field GF (2 ¹⁰ ) is 4 codewords, and RS (992, 956) code on Galois field GF (2 ¹¹ ) When 8 code words are used, the present invention can be applied to the OTU frame 51 well.

  Next, the second interleave circuit 15 performs an operation of rearranging the n parallel first codeword sequences generated from the first FEC encoding circuit 14. The rearrangement method first rearranges the RS codeword frame 61 shown in FIG. 4A to the OTU frame 51 shown in FIG. 4B. In general, rearrangement of a sequence is called “deinterleaving”, but in the description of the embodiment of the present invention, rearrangement and rearrangement are called “interleaving” in a broad sense.

  Next, the sequence rearranged in the OTU frame 51 is divided into a portion corresponding to the payload 103 and the RS dummy sequence 53 into an LDPC information sequence 71 as shown in FIG. Then, the divided LDPC dummy series 72 is divided. Although any method can be considered as the dividing method, FIG. 4 shows an example in which each FEC frame 52 is divided into four, and the entire OTU frame 51 is divided into 16. Then, the LDPC code sequence 81 shown in FIG. 5A is formed by connecting the LDPC information sequence 71 and the divided LDPC dummy sequence 72. This is output as a second codeword sequence. The second codeword sequence interleaved by the above method is input to the second FEC encoding circuit 16. In FIG. 5A, 82 indicates an LDPC information sequence, 83 indicates an LDPC parity sequence, and 84 indicates the sequence order of LDPC codewords.

Next, the second FEC encoding circuit 16 performs “two elements” on a sequence input from the second interleave circuit 15 with a predetermined code length N2, information length K2, and Galois field GF (2). Error correction coding of the LDPC code or the “multiple” LDPC code on the Galois field GF (2 ^{m ′} ). As a result, the second FEC encoding circuit 16 outputs the third codeword sequence in n parallel.

  Note that the encoding operation by the second FEC encoding circuit 16 is performed in an arbitrary parallel number of n or less in the case of a “binary” LDPC code, for example. In the case of a “multiple” LDPC code, n / m parallel or an arbitrary parallel number of n / m or less is used. Also, the inner code encoding operation may be realized by pipeline processing. Further, the type of inner code is not necessarily limited to one type as long as the constraints of the frame format are satisfied, and a plurality of types of codes may be used. Furthermore, although the error correction code used as the inner code has been described as a “binary” or “multiple” LDPC code here, other codes may be used.

  For example, when a binary LDPC (9216, 7936) code of n = 128, information length 128 × 62, parity length 128 × 10 (each a multiple of 128) shown in FIG. By performing the encoding process in FIG. 3, the present invention can be applied to the OTU frame 51 well.

  If the code length and the information length of the LDPC code are multiples of 128, the present invention can be applied to the OTU frame 51, but if such an LDPC code is difficult to construct, a predetermined number of bits are punctured. Therefore, it can be applied to such a configuration.

  Next, the third interleave circuit 17 rearranges the n-parallel third codeword sequence generated from the second FEC encoding circuit 16 and generates the result as a fourth codeword sequence. . As this rearrangement method, for example, a method of rearranging the plurality of LDPC codeword frames 81 shown in FIG. 5A to the OTU frame 51 shown in FIG. 5B can be considered. In FIG. 5B, 91 indicates a combined RS parity sequence, 92 indicates a combined LDPC parity sequence, and 93 indicates a transmission sequence sequence.

  The third interleave circuit 17 is not always necessary and can be omitted. However, by performing this rearrangement, the frame configuration on the transmission path is changed to ITU-T G.264. It has the characteristic that it becomes the same format as the OTUkV frame 51 compliant with 709.

  Finally, the first multiplexing circuit 18 converts the fourth codeword sequence into a fifth codeword sequence in series, generates a fifth codeword sequence in series, and inputs it to the modulator 32.

  The information (data) transmitted between the circuits 11 to 18 in the error correction coding device 31 is configured to be transferred in a pipeline manner via a bus connecting the circuits 11 to 18. Alternatively, a working storage area that can be referred to from adjacent front and rear circuits may be provided and transferred. In the following description, in order to facilitate understanding, it is assumed that a working storage area that can be referred to from adjacent front and rear circuits is provided.

  FIG. 3 is a block diagram showing a specific configuration example of the error correction decoding apparatus 43 of FIG. In FIG. 3, the error correction decoding device 43 includes a second demultiplexing circuit 21, a frame synchronization circuit 22, a fourth interleaving circuit 23, a first FEC decoding circuit (internal code decoding means) 24, and a fifth interleaving. A circuit 25, a second FEC decoding circuit (outer code decoding means) 26, a sixth interleave circuit 27, a first frame separation circuit 28, and a second multiplexing circuit 29 are provided.

  The error correction decoding device 43 has a circuit configuration corresponding to the error correction encoding device 31, and has a function of decoding the error correction code encoded by the error correction encoding device 31.

  In the error correction decoding device 43, the second demultiplexing circuit 21 on the uppermost side is configured to generate a second quantized reception sequence (parallel) based on the first quantized reception sequence (in series) from the A / D converter 42. ) Is generated. The frame synchronization circuit 22 generates a second quantization reception sequence (parallel) + frame synchronization signal based on the second quantization reception sequence.

  The fourth interleave circuit 23 generates a third quantized reception sequence (parallel after reordering) based on the second quantized reception sequence + the frame synchronization signal. The first FEC decoding circuit 24 generates a first FEC decoding result sequence (parallel) based on the third quantized reception sequence.

  The fifth interleave circuit 25 generates a second FEC decoding result sequence (in parallel after reordering) based on the first FEC decoding result sequence. The second FEC decoding circuit 26 generates a first estimated codeword sequence (parallel) based on the second FEC decoding result sequence.

  The sixth interleave circuit 27 generates a second estimated codeword sequence (parallel after reordering) based on the first estimated codeword sequence. The first frame separation circuit 28 generates a first estimated information sequence (parallel) based on the second estimated codeword sequence. Then, in the error correction decoding device 43, the second multiplexing circuit 29 on the lowermost stage generates a second estimated information sequence (serial) based on the first estimated information sequence.

  Note that in the error correction decoding device 43 (reception side), the demodulator 41 and the A / D converter 42 (see FIG. 1) demodulate the reception sequence in the serial order mixed with noise through the communication path. A / D conversion is performed to generate a quantized reception sequence. Here, assuming that quantization is performed to q bits per transmission symbol, a case where q = 1 is referred to as “hard decision”, and a case where q> 1 is referred to as “soft decision”.

  Next, the operation of the error correction decoding device 43 will be described. In FIG. 3, the first quantized reception sequence input to the error correction decoding apparatus 43 in the serial order is first converted into a parallel order by the second demultiplexing circuit 21, and the second quantized reception sequence is obtained. Is generated.

  At this time, the second demultiplexing circuit 21 converts the q-bit quantized reception sequence per transmission symbol into an n ′ (= n × q) parallel quantization reception sequence. Since a q-bit quantized reception sequence per transmission symbol can be handled with q bits as one unit, in the following description on the receiving side, an n ′ (= n × q) parallel one is referred to as “n” for convenience. This is referred to as “parallel”.

  Subsequently, the frame synchronization circuit 22 detects the OH information (overhead information) added to the n-parallel second quantized reception sequence and identifies the head position of the frame.

  Next, the fourth interleaving circuit 23 (corresponding to the third interleaving circuit 17 in the error correction coding apparatus 31), when interleaving is executed on the transmission side, reverses the interleaving before FEC decoding on the reception side. Are interleaved and rearranged to generate an n-parallel third quantized reception sequence. That is, for example, when the transmitting side rearranges the plurality of LDPC codeword frames 81 shown in FIG. 5A to the OTU frame 51 shown in FIG. 5B, the receiving side inputs the OTU frame 51. The operation of rearranging the images into a plurality of LDPC codeword frames 81 is performed.

  The fourth interleave circuit 23 is not necessarily required, as with the third interleave circuit 17 in the error correction coding apparatus 31, and can be omitted. That is, when the third interleave circuit 17 is omitted in the error correction coding apparatus 31 on the information source transmission side, the fourth interleave circuit 23 in the error correction decoding apparatus 43 is also unnecessary.

  Next, the first FEC decoding circuit 24 applies a third codeword sequence to the n-parallel third quantized reception sequence generated by adding the frame synchronization signal to the n-parallel quantized reception sequence. Decoding processing (decoding processing of the correction code encoded by the second FEC encoding circuit 16). As a result, the first FEC decoding result series is generated in n parallel.

  Note that the first FEC decoding circuit 24 performs hard decision decoding and soft decision decoding according to the quantization number of the input quantized reception sequence. In general, hard decision decoding is performed when q = 1, and soft decision decoding is performed when q> 1, but the present invention is not limited to this.

The number of quantization bits (per transmission symbol) of the first FEC decoding result sequence is generally a hard decision (q ″ = 1). Information (q ″> 1) may be output.
Since the first FEC decoding result sequence of q ″ bits per transmission symbol can be handled with q ″ bits as one unit, in the following description on the receiving side, n ″ (= n × q ′ ') For convenience, the parallel one is referred to as “n parallel”.

  When puncturing is performed to match the code length and information length of the LDPC code of the inner code to a multiple of 128, the punctured bit is processed as having been transmitted as 0 as processing of the first FEC decoding circuit 24. Alternatively, it may be ignored and processed as originally not included in the code word.

  Returning to FIG. 3, the fifth interleaving circuit 25 (corresponding to the second interleaving circuit 15 in the error correction coding apparatus 31) generates the n-parallel first generated from the first FEC decoding circuit 24. The FEC decoding result sequence is replaced with the order before being input to the second interleave circuit 15, and the result is generated as the second FEC decoding result sequence. That is, for example, when the transmitting side rearranges the plurality of RS codeword frames 61 shown in FIG. 4A to the LDPC codeword frame 81 shown in FIG. 5A, the receiving side arranges the reverse. Perform the change operation. The n-parallel second FEC decoding result sequence encoded and converted by the above method is input to the second FEC decoding circuit 26.

  The second FEC decoding circuit 26 decodes the first codeword sequence (decoding of the correction code encoded by the first FEC encoding circuit 14) with respect to the n parallel second FEC decoding result sequence. Process). As a result, the first estimated codeword sequence is generated in n parallel.

  Note that the first FEC decoding circuit 25 performs hard decision decoding and soft decision decoding according to the quantization number of the input quantized reception sequence. In general, hard decision decoding is performed when q ″ = 1, and soft decision decoding is performed when q ″> 1, but the present invention is not limited to this.

  The number of quantization bits (per transmission symbol) of the first estimated codeword sequence is generally a hard decision (q ′ ″ = 1), but the reliability of the decoding result is added, Soft information (q ′ ″> 1) may be generated.

  In this case, after appropriate interleaving / deinterleaving, the result may be input again to the first and second FEC decoding circuits 24 and 26 in order, and this processing may be repeated to repeatedly perform decoding.

  Since the first estimated codeword sequence of q ′ ″ bits per transmission symbol can be handled with q ′ ″ bits as one unit, in the following description on the receiving side, n ′ ″ (= n Xq ′ ″) The parallel one is called “n parallel” for convenience.

  Returning to FIG. 3, the sixth interleaving circuit 27 (corresponding to the first interleaving circuit 13 in the error correction coding apparatus 31) generates the n-parallel first generated from the first FEC decoding circuit 26. Are replaced with the order before being input to the first interleave circuit 13, and the result is generated as a second estimated codeword sequence. That is, for example, when rearranging the OTU frame 51 shown in (b) of FIG. 4 to the RS codeword frame 61 shown in (a) of FIG. 4 on the transmitting side, the receiving side performs an operation of reversing the reverse. . The n parallel second estimated codeword sequences encoded and converted by the above method are input to the first frame separation circuit 28.

  The first frame separation circuit 28 (corresponding to the first frame generation circuit 12 on the transmission side) removes bits corresponding to the OH signal (overhead signal) from the second estimated codeword sequence, and then transmits the transmission side. Corresponding to the speed conversion executed by the first frame generation circuit 12, the bit corresponding to the reserved parity sequence area is separated and removed, and the reverse speed conversion of the n parallel sequences is performed. That is, when the coding rate based on the information length Kc of the concatenated code and the code length Nc is Kc / Nc, the transmission rate is multiplied by Kc / Nc. As a result, the first estimated information series is generated in n parallel.

  Finally, the second multiplexing circuit 29 generates the n-parallel first estimated information sequence by converting it into a serial second estimated information sequence.

  Note that information (data) transmitted between the circuits 21 to 29 constituting the error correction decoding device 43 is transferred via a pipeline that connects the circuits, as in the error correction coding device 31. It may be configured to be delivered by a method, or may be configured to be delivered by providing a working storage area that can be referred to from adjacent front and rear circuits. In the following description, in order to facilitate understanding, it is assumed that a working storage area that can be referred to from adjacent front and rear circuits is provided.

  With the above configuration, a payload having the same length as that of an OTU frame can be error-protected by a concatenated encoding method using an RS code or other block code as an outer code and an LDPC code as an inner code.

  Further, as described above, by making the code length and information length of the LDPC code of the inner code a multiple of 128, the input / output and encoding / decoding of the codeword sequence can be performed in 128 parallel units.

  As described above, the RS code of the outer code can be assigned different codes with the same code length, and can be input / output, encoded and decoded in parallel.

  As described above, after the encoding process of the outer code and the inner code is completed, the parity of the LDPC code of the inner code is set to the rightmost (the rearmost side of the frame), and the parity of the RS code of the outer code is set to that By moving to the left side, it is possible to maintain the same positional relationship between the information series and the parity series as in the OTU frame.

  The above-described embodiment is not limited to the parameters shown in the above specific examples, and the error correction coding method, the length of the frame format, the number of input / output parallels, the transmission rate, etc. can be applied well. Needless to say, any combination is possible and can be realized.

  For example, the LDPC codeword frame 81 in FIG. 5 divides the number of rows n = 128 of the FEC frame 52 by 72 columns for each column. However, this LDPC codeword frame may be set for each row. For example, the number of rows n2 = 16, 32, 64, the number of columns is set to the number of columns in the FEC frame 51, the LDPC codeword frame number f2 = 8, 4, 2 is determined, and the LDPC parity sequence is moved to the rightmost side. It may be in such a form.

  In the above-described embodiment, the ITU-T G. 709 recommendation, pp. The frame conforming to the OTUkV frame 51 shown in 101-103 has been described. However, by adjusting the coding rate of the outer code and the inner code, the ITU-T G.D. 709 recommendation, pp. The frame conforming to the OTUk frame 201 shown in 94-95 can be similarly configured.

  Further, the present invention is not limited to the optical transmission system and can be applied to various types of transmission systems such as subscriber wired communication, mobile wireless communication, and satellite communication.

Embodiment 2. FIG.
FIG. 8 is a block diagram showing another embodiment of the error correction coding apparatus 31 of FIG. In FIG. 8, an error correction coding device 31 includes a first demultiplexing circuit 11, a second frame generation circuit 112, a third FEC coding circuit 114 (outer code coding means), a second FEC code. An encoding circuit (inner code encoding means) 16 and a first multiplexing circuit 18. 2 that are the same as or correspond to those in FIG.

  In the error correction coding apparatus 31 of the second embodiment, the first demultiplexing circuit 11 on the uppermost stage generates a second information sequence (parallel) based on the first information sequence (serial). The second frame generation circuit 112 generates the third information + OH (overhead) + dummy sequence (parallel) based on the second information sequence.

  The third FEC encoding circuit 114 generates a sixth codeword sequence (parallel) based on the third information + OH + dummy sequence.

  The second FEC encoding circuit 16 generates a seventh codeword sequence (parallel) based on the sixth codeword sequence.

  Then, in the error correction encoding device 31, the first multiplexing circuit 18 on the lowermost stage generates an eighth codeword sequence (serial) based on the seventh codeword sequence.

  Next, the operation of the error correction coding apparatus 31 according to the second embodiment will be described. The difference in operation from the first embodiment is a portion of the second frame generation circuit 112 and the third FEC encoding circuit 114 (outer code encoding means). Therefore, in the following, this part will be mainly described. The portion where the description is omitted is the same operation as in the first embodiment.

  In FIG. 8, the second frame generation circuit 112 adds an OH including a synchronization control signal and the like in addition to the n-parallel second information series generated from the first demultiplexing circuit 11; An area to which a parity sequence of an error correction code is added is secured, and further, OH and a dummy sequence are added, and information whose transmission rate is increased by the addition of these redundant areas is generated. That is, when the coding rate based on the information length Kc of the concatenated code and the code length Nc is Kc / Nc, the transmission rate is increased by Nc / Kc.

  The third information + OH + dummy sequence generated here includes the payload 153 of the OTUkV frame 151 shown in FIG. To replace). The major difference from the OTUkV frame 51 shown in FIG. 4B is that the payload 153 is divided into a plurality of sub-blocks, and an RS dummy sequence and an LDPC dummy sequence are interrupted between the divided sub-blocks. is there.

  Note that the OTUkV frame 151 has a transmission sequence order on the transmission line, strictly speaking, ITU-TG. 709 recommendation, pp. It is different from the frame shown in 94-95. However, the length of the payload 153 to be transmitted is the same. Therefore, the second embodiment is characterized in that the payload having the same length as the OTU frame is error-protected.

  Returning to FIG. 8, next, the third FEC encoding circuit 114 applies a predetermined code length N1, information length K1, Galois field GF (2) to the sequence input from the second frame generation circuit 112. Alternatively, error correction coding of the block code on the Galois field GF (2m) is performed. As a result, the sixth codeword sequence is generated in n parallel from the third FEC encoding circuit 114.

  The sixth codeword sequence generated here is output in the same order without interleaving the sequence input from the second frame generation circuit 112. At the time of output, the RS dummy sequence is replaced with the RS parity sequence 191. At the time of input of the LDPC dummy series, control is performed to handle the input / output of invalid data. Therefore, it is not necessary to perform interleaving before and after the third FEC encoding circuit 114. Note that the FEC encoding processing method itself of the third FEC encoding circuit 114 is the same as that of the first FEC encoding circuit 14, and the details are omitted.

  Next, the second FEC encoding circuit 16 applies a predetermined code length N2, information length K2, and “2” on the Galois field GF (2) to the sequence input from the third FEC encoding circuit 114. The error correction coding of the “original” LDPC code or the “multiple” LDPC code on the Galois field GF (2m ′) is performed. As a result, the seventh codeword sequence is output in n parallel from the second FEC encoding circuit 16.

  At the time of output of the second frame generation circuit 112, the LDPC codeword frame 181 has already been formed. The seventh codeword sequence generated here is output in the same order without interleaving the sequence input from the third FEC encoding circuit 114. At the time of output, the LDPC dummy sequence is replaced with the LDPC parity sequence 192. Therefore, it is not necessary to perform interleaving before and after the second FEC encoding circuit 16. Since the FEC encoding processing method itself of the second FEC encoding circuit 16 has already been described in the description of the first embodiment, the details are omitted.

  Finally, the first multiplexing circuit 18 converts the seventh codeword sequence into an eighth codeword sequence in series, generates an eighth codeword sequence in series, and inputs it to the modulator 32.

  Note that the information (data) transmitted between the circuits 11 to 18 in the error correction coding apparatus 31 is a pipeline system via a bus connecting the circuits 11 to 18 as in the first embodiment. It may be configured to be delivered by the system, or may be configured to be delivered by providing a working storage area that can be referred to from adjacent front and rear circuits. In the following description, in order to facilitate understanding, it is assumed that a working storage area that can be referred to from adjacent front and rear circuits is provided.

  FIG. 9 is a block diagram showing another specific configuration example of the error correction decoding apparatus 43 of FIG. In FIG. 9, the error correction decoding apparatus 43 includes a second demultiplexing circuit 21, a frame synchronization circuit 22, a first FEC decoding circuit (inner code decoding means) 24, and a third FEC decoding circuit (outer code decoding). Means) 126, a second frame separation circuit 128, and a second multiplexing circuit 29. 3 that are the same as or correspond to those in FIG.

  The error correction decoding apparatus 43 of the second embodiment has a circuit configuration corresponding to the error correction encoding apparatus 31 of the second embodiment, and is an error correction code encoded by the error correction encoding apparatus 31 of the second embodiment. Has a function of decrypting.

  In the error correction decoding apparatus 43 of the second embodiment, the second demultiplexing circuit 21 on the uppermost stage is configured based on the fifth quantized reception sequence (in series) from the A / D converter 42, Generate a quantized reception sequence (parallel). The frame synchronization circuit 22 generates a sixth quantization reception sequence (parallel) + frame synchronization signal based on the sixth quantization reception sequence.

  The first FEC decoding circuit 24 generates a third FEC decoding result sequence (parallel) based on the sixth quantized reception sequence (parallel) + frame synchronization signal.

  The third FEC decoding circuit 126 generates a third estimated codeword sequence (parallel) based on the third FEC decoding result sequence.

  The second frame separation circuit 128 generates a first estimated information sequence (parallel) based on the third estimated codeword sequence. Then, in the error correction decoding device 43, the second multiplexing circuit 29 on the lowermost stage generates a second estimated information sequence (serial) based on the first estimated information sequence.

  Next, the operation of the error correction decoding apparatus 43 according to the second embodiment will be described. Note that the difference in operation from the first embodiment is the portion of the third FEC decoding circuit 126 and the second frame separation circuit 128. Therefore, in the following, this part will be mainly described. The portion where the description is omitted is the same operation as in the first embodiment. Further, the description of the quantization bit number q and the parallel number n described in the first embodiment is handled in the same manner in the second embodiment.

  In FIG. 9, the fifth quantized received sequence input to the error correction decoding apparatus 43 in the serial order is first converted into a parallel order by the second demultiplexing circuit 21, and the sixth quantized received sequence is obtained. Is generated.

  At this time, the sixth demultiplexing circuit 21 converts the q-bit quantized reception sequence per transmission symbol into an n-parallel quantization reception sequence.

  Subsequently, the frame synchronization circuit 22 detects the OH information (overhead information) added to the n-parallel sixth quantized reception sequence and identifies the head position of the frame.

  Next, the first FEC decoding circuit 24 applies a seventh codeword sequence to the n-parallel sixth quantized reception sequence generated by adding the frame synchronization signal to the n-parallel quantized reception sequence. Decoding processing (decoding processing of the correction code encoded by the second FEC encoding circuit 16). As a result, a third FEC decoding result sequence is generated in n parallel.

  At the time of output of the frame synchronization circuit 22, the LDPC codeword frame 181 has already been formed. The third FEC decoding result sequence generated here is output in the same order without interleaving the sequence input from the frame synchronization circuit 22. At the time of output, the decoding result of the LDPC code is output as a third FEC decoding result sequence. Therefore, it is not necessary to perform interleaving before and after the first FEC decoding circuit 24. Note that the FEC decoding processing method itself of the first FEC decoding circuit 24 has already been described in the description of the first embodiment, and the details are omitted.

  Returning to FIG. 9, the third FEC decoding circuit 126 then decodes the sixth codeword sequence (by the third FEC encoding circuit 114) on the n parallel third FEC decoding result sequence. (Decoding process of the encoded correction code). As a result, a third estimated codeword sequence is generated in n parallel.

  The third estimated codeword sequence generated here is output in the same order without interleaving the sequence input from the first FEC decoding circuit 24. At the time of output, the decoding result of the RS code is output as a third estimated codeword sequence. Therefore, it is not necessary to perform interleaving before and after the third FEC decoding circuit 126. Note that the FEC decoding processing method itself of the third FEC decoding circuit 126 is the same as that of the second FEC decoding circuit 26, and thus the details are omitted.

  The second frame separation circuit 128 (corresponding to the second frame generation circuit 112 on the transmission side) removes bits corresponding to the OH signal (overhead signal) from the third estimated codeword sequence, and then transmits the transmission side. In response to the speed conversion executed by the second frame generation circuit 112, the payload 153 of the OTUkV frame 151 shown in FIG. 10 is divided into sub blocks, and an RS parity sequence 191 secured between the sub blocks and The bits corresponding to the LDPC parity sequence 192 are separated and removed, and the reverse speed conversion of n parallel sequences is performed. That is, when the coding rate based on the information length Kc of the concatenated code and the code length Nc is Kc / Nc, the transmission rate is multiplied by Kc / Nc. As a result, the first estimated information series is generated in n parallel.

  Finally, the second multiplexing circuit 29 generates the n-parallel first estimated information sequence by converting it into a serial second estimated information sequence.

  Note that information (data) transmitted between the circuits 21 to 29 constituting the error correction decoding device 43 is transferred via a pipeline that connects the circuits, as in the error correction coding device 31. It may be configured to be delivered by a method, or may be configured to be delivered by providing a working storage area that can be referred to from adjacent front and rear circuits. In the following description, in order to facilitate understanding, it is assumed that a working storage area that can be referred to from adjacent front and rear circuits is provided.

  With the above configuration, in a concatenated encoding method using an RS code or other block code as an outer code and an LDPC code as an inner code, the payload is divided into a plurality of sub-blocks, and between the divided sub-blocks. Error protection of a payload having the same length as the OTU frame without interleaving rearrangement before and after the processing of the outer code and the inner code by interrupting the parity sequence of the outer code and the parity sequence of the inner code Can do.

  The above-described embodiment is not limited to the parameters shown in the above specific examples, and the error correction coding method, the length of the frame format, the number of input / output parallels, the transmission rate, etc. can be applied well. Needless to say, any combination is possible and can be realized.

  For example, the LDPC codeword frame 181 in FIG. 10 divides the number of rows n = 128 of the FEC frame 152 by 72 columns for each column. However, this LDPC codeword frame may be set for each row. For example, the number of rows n2 = 16, 32, 64, the number of columns is set to the number of columns in the FEC frame 51, the LDPC codeword frame number f2 = 8, 4, 2 is determined, and the LDPC parity sequence is moved to the rightmost side. It may be in such a form.

  In the above-described embodiment, the ITU-T G. 709 recommendation, pp. The frame conforming to the OTUkV frame 51 shown in 101-103 has been described. However, by adjusting the coding rate of the outer code and the inner code, the ITU-T G.D. 709 recommendation, pp. The frame conforming to the OTUk frame 201 shown in 94-95 can be similarly configured.

  Further, the present invention is not limited to the optical transmission system and can be applied to various types of transmission systems such as subscriber wired communication, mobile wireless communication, and satellite communication.

  DESCRIPTION OF SYMBOLS 11 1st demultiplexing circuit, 12 1st flame | frame production | generation circuit, 13 1st interleave circuit, 14 1st FEC encoding circuit, 15 2nd interleave circuit, 16 2nd FEC encoding circuit, 17 1st 3 interleaving circuit, 18 first multiplexing circuit, 21 second demultiplexing circuit, 22 frame synchronization circuit, 23 fourth interleaving circuit, 24 first FEC decoding circuit, 25 fifth interleaving circuit, 26 th 2 FEC decoding circuits, 27 6th interleave circuit, 28 1st frame separation circuit, 29 2nd multiplexing circuit, 30 digital transmission system, 31 error correction coding device, 32 modulator, 33 communication channel, 41 Demodulator, 42 converter, 43 error correction decoding device, 112 second frame generation circuit, 114 third FEC encoding circuit, 126 Third FEC decoding circuit, 128 Second frame separation circuit.

Claims (7)

A digital transmission system that performs concatenated coding combining a plurality of error correction codes,
Provided on the transmission side of the system, RS code or other block code as outer code, LDPC code as inner code, concatenated coding to perform error correction coding after each interleaving, and the same length as OTU frame A digital transmission system comprising an error correction coding device for error-protecting a payload.   2. The error correction encoding apparatus performs input / output and encoding of a codeword sequence in units of 128 parallel by setting the code length and information length of the LDPC code of the inner code to a multiple of 128. The digital transmission system described in 1.   The digital transmission system according to claim 1 or 2, wherein the error correction coding apparatus assigns different codes with the same code length to the RS code of the outer code, and inputs / outputs and codes each of them in parallel.   After the error correction coding apparatus completes the coding process of the outer code and the inner code, the parity of the LDPC code of the inner code is the rearmost of the frame, and the parity of the RS code of the outer code is the parity of the LDPC code. 4. The digital transmission system according to claim 1, wherein the positional relationship between the same information sequence and parity sequence as that of the OTU frame is maintained by being positioned immediately before. 5.   An error correction decoding apparatus for receiving a transmission signal concatenated and encoded by the error correction encoding apparatus at the reception side and performing decoding after interleaving opposite to the interleaving on the transmission side for each error correction encoding; The digital transmission system according to claim 1, wherein the digital transmission system is a digital transmission system. A digital transmission method for performing concatenated coding combining a plurality of error correction codes,
In the error correction coding apparatus provided on the transmission side of the system, RS code or other block code is used as an outer code, LDPC code is used as an inner code, and concatenated coding is performed to perform error correction coding after each interleaving. A digital transmission method characterized by error-protecting a payload having the same length as an OTU frame.   7. The concatenated encoded transmission signal is received by an error correction decoding apparatus on the receiving side, and decoding is performed after interleaving opposite to the interleaving on the transmitting side for each error correction encoding. The digital transmission method described in 1.

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