JP5523120B2 - Error correction encoding method, error correction decoding method, error correction encoding device, and error correction decoding device - Google Patents

Description

  The present invention relates to an error correction encoding method, an error correction decoding method, and an apparatus therefor in, for example, a digital transmission system.

  The conventional error correction coding method for optical communication (see Patent Document 1, for example) is a function of interleaving between an outer code and an inner code as shown in FIGS. 2, 5, 6, and 7 in the document. Is performed by an operation of bit-shifting for each column. In this case, ITU-T Recommendation G. For OTUk (Optical channel Transport Unit-k (k is classified as 1, 2, 3, 4 depending on transmission speed)) frame conforming to 709 (see Non-Patent Document 1). This interleave operation can be performed by parallel processing. At this time, when looking at the allocation of the information sequence area and the parity sequence area divided into four internal frames (herein referred to as FEC (Forward Error Correction) frames), all 128 rows are found. Are evenly distributed.

Japanese Patent No. 4382124

ITU-T Recommendation G. 709

  Since the conventional error correction encoding method and apparatus are configured as described above, for example, 512 rows per column are processed in parallel, and ITU-T Recommendation G. When the OTUkV frame described in Appendix 709 (in which the parity sequence length is longer than the OTUk frame) is introduced, the parity sequence length of each internal frame needs to be divisible by 512. If the condition is not satisfied, the allocation of the information sequence region and the parity sequence region becomes non-uniform for each row, and accordingly, the distribution of codeword sequences arranged in the horizontal direction becomes non-uniform.

  As described above, the conventional error correction coding method and the apparatus thereof have a problem that restrictions on the parity sequence length occur. That is, there is a problem that a restriction is imposed on the frame configuration for increasing the processing parallel number to increase the processing throughput and increasing the error correction capability.

  The present invention has been made to solve such a problem. By classifying parallel input sequences into specific lanes and performing interleaving for performing a specific barrel shift for each internal frame, an information sequence region and a parity are obtained. An error correction encoding method, an error correction decoding method, an error correction encoding device, which can make the allocation of the sequence region uniform, increase the processing throughput, and increase the error correction capability, and An object is to obtain an error correction decoding apparatus.

The present invention provides an outer encoding step for performing an outer code encoding process on a parallel input sequence, and a predetermined width for the parallel input sequence on which the outer code encoding process has been performed by the outer encoding step. The plurality of internal frames of the parallel input sequence divided into the plurality of lanes are subjected to barrel shift based on an integral multiple of the width of the lane, and the integral multiple is 0 or more. in it, an error correction coding to the interleaving step, characterized by comprising an encoding step inner performing encoding of the inner code of the barrel shift performed with the parallel input sequence by the interleaving processing step Is the method.

The present invention provides an outer encoding step for performing an outer code encoding process on a parallel input sequence, and a predetermined width for the parallel input sequence on which the outer code encoding process has been performed by the outer encoding step. The plurality of internal frames of the parallel input sequence divided into the plurality of lanes are subjected to barrel shift based on an integral multiple of the width of the lane, and the integral multiple is 0 or more. in it, an error correction coding to the interleaving step, characterized by comprising an encoding step inner performing encoding of the inner code of the barrel shift performed with the parallel input sequence by the interleaving processing step Since this method classifies parallel input sequences into specific lanes and performs interleaving to perform a specific barrel shift for each internal frame, the information sequence region Allocation of parity sequence areas can be made uniform, and it is possible to achieve an error correction coding method that avoids frame configuration restrictions, increases processing throughput, and increases error correction capability. .

It is explanatory drawing which shows the circuit structure of the error correction coding method which concerns on Embodiment 1 of this invention, and its apparatus. It is explanatory drawing which shows the circuit structure of the error correction decoding method which concerns on Embodiment 1 of this invention, and its apparatus. It is explanatory drawing which shows the circuit structure of the error correction coding method which concerns on Embodiment 1 of this invention, and its apparatus. It is explanatory drawing which shows the circuit structure of the error correction decoding method which concerns on Embodiment 1 of this invention, and its apparatus. It is a block diagram which shows the structure of the digital transmission system which concerns on Embodiment 1 of this invention. It is explanatory drawing which shows the standard frame format in an error correction encoding method. It is explanatory drawing which shows the frame format of the error correction coding method which concerns on Embodiment 1 of this invention. It is explanatory drawing which shows the frame format of the error correction coding method which concerns on Embodiment 1 of this invention. It is explanatory drawing which shows the frame format of the error correction coding method which concerns on Embodiment 1 of this invention. It is explanatory drawing which shows the frame format of the error correction coding method which concerns on Embodiment 1 of this invention. It is explanatory drawing which shows the frame format of the error correction coding method which concerns on Embodiment 1 of this invention. It is explanatory drawing which shows the frame format of the error correction coding method which concerns on Embodiment 1 of this invention. It is explanatory drawing which shows the frame format of the error correction coding method which concerns on Embodiment 1 of this invention. It is explanatory drawing which shows the frame format of the error correction coding method which concerns on Embodiment 1 of this invention.

Embodiment 1 FIG.
FIG. 5 is a block diagram showing a configuration of a digital transmission system (hereinafter simply referred to as “transmission system”) provided with an error correction coding apparatus and an error correction decoding apparatus according to an embodiment of the present invention. In FIG. 5, the transmission system includes an error correction encoder 11 (error correction encoding device) connected to an information source, and a D / A (digital / analog) converter 12 connected to the error correction encoder 11. A modulator 13 connected to the D / A converter 12, a communication path 14 connected to the modulator 13, a demodulator 21 connected to the modulator 13 through the communication path 14, and a demodulator 21 The A / D (analog / digital) converter 22 connected to the A / D converter 22 and the error correction decoder 23 (error correction decoding device) connected to the A / D converter 22. Is connected to the recipient. Here, the D / A converter 12, the modulator 13, the communication path 14, the demodulator 21, and the A / D converter 22 each have a device configuration generally used in a digital transmission system. Note that the D / A converter 12 is necessary in the case of multilevel modulation with two or more values, but is not necessarily required in the case of binary modulation.

  FIG. 1 is a block diagram showing a specific configuration example of the error correction encoder 11 of FIG. In FIG. 1, an error correction encoder 11 includes a transmission side demultiplexing circuit 31, a frame generation circuit 32, an outer encoding input circuit 51, an outer encoding operation circuit 52, an outer encoding output circuit 53, and an inner encoding input circuit. 54, an inner coding operation circuit 55, an inner coding output circuit 56, and a transmission side multiplexing circuit 35. A combination of the outer coding input circuit 51, the outer coding arithmetic circuit 52, and the outer coding output circuit 53 is an outer coding circuit 33 (outer code coding means). A combination of the input circuit 54, the inner encoding operation circuit 55, and the inner encoding output circuit 56 is an inner encoding circuit 34 (inner code encoding means).

  FIG. 3 is a block diagram showing a specific configuration example of the inner encoding circuit 34 of FIG. In FIG. 3, an inner encoding circuit 34 includes an inner encoding input I / F (interface) circuit 71, a 1-1 interleave circuit 72, a 1-2 interleave circuit 73, an inner encoding operation circuit 55, A 1-2 deinterleave circuit 74, a 1-1 deinterleave circuit 75, and an inner-coded output I / F circuit 76 are provided. A combination of the inner coding input I / F circuit 71, the 1-1 interleave circuit 72, and the 1-2 interleaving circuit 73 is an inner coding input circuit 54. A combination of the two deinterleave circuits 74, the 1-1 deinterleave circuit 75, and the inner coded output I / F circuit 76 is an inner coded output circuit 56.

  FIG. 2 is a block diagram showing a specific configuration example of the error correction decoder 23 of FIG. In FIG. 2, the error correction decoder 23 includes a frame synchronization circuit 41, a receiving side demultiplexing circuit 42, an inner decoding input circuit 61, an inner decoding operation circuit 62, an inner decoding output circuit 63, an outer decoding input circuit 64, an outer decoding operation. A circuit 65, an outer decoding output circuit 66, a frame separation circuit 45, and a reception side multiplexing circuit 46 are provided. A combination of the inner decoding input circuit 61, the inner decoding operation circuit 62, and the inner decoding output circuit 63 is an inner decoding circuit 43 (decoding means for inner code), and an outer decoding input circuit 64, outer decoding. A combination of the arithmetic circuit 65 and the outer decoding output circuit 66 is an outer decoding circuit 44 (decoding means for outer code).

  FIG. 4 is a block diagram showing a specific configuration example of the inner decoding circuit 43 of FIG. In FIG. 4, the inner decoding circuit 43 includes an inner decoding input I / F circuit 81, a soft input value calculation circuit 82, a 2-1 interleave circuit 83, a 2-2 interleave circuit 84, an inner decoding calculation circuit 62, A 2-2 deinterleave circuit 85, a 2-1 deinterleave circuit 86, and an inner decoding output I / F circuit 87 are provided. The inner decoding input circuit 61 is a combination of the inner decoding input I / F circuit 81, the soft input value arithmetic circuit 82, the 2-1 interleave circuit 83, and the 2-2 interleaving circuit 84. The inner decoding output circuit 63 is a combination of the 2-2 deinterleaving circuit 85, the 2-1 deinterleaving circuit 86, and the inner decoding output I / F circuit 87.

  Although detailed views of the outer encoding circuit 33 and the outer decoding circuit 44 shown in FIGS. 1 and 2 are omitted here, the parallel input series that characterize the first embodiment of the present invention is specified. It is preferable to use an example in which this function is installed on the side of the inner encoding circuit 34 and the inner decoding circuit 43 in explaining the function of performing interleaving for performing a specific barrel shift for each inner frame. Therefore, detailed description of the outer encoding circuit 33 and the outer decoding circuit 44 is omitted. In the first embodiment of the present invention, the function can naturally be mounted on the side of the outer encoding circuit 33 and the outer decoding circuit 44 if the conditions of the frame format are matched.

  Next, the operation of the error correction encoder 11 will be described. In FIG. 1, first, an information sequence input to the error correction encoder 11 in a serial order or a predetermined interface standard such as SFI (Serdes Framer Interface) is converted into a parallel order by a transmission side demultiplexing circuit 31. Converted. The parallel number at this time is defined as “n”. The parallel number n can be defined as an arbitrary integer according to a predetermined frame format. However, in the first embodiment, assuming that a frame conforming to the OTUkV frame is considered, it is assumed that n = 512. To do. The information series converted into the parallel order by the transmission side demultiplexing circuit 31 is converted into a predetermined frame order by the frame generation circuit 32.

  For example, ITU-T recommendation G.A. When an OTUk frame conforming to 709 (see Non-Patent Document 1) is considered, the frame format is as shown in FIG. FIG. 6 illustrates an ITU frame image. In this example, OTU Row 1 to Row 4 are arranged, each having a control overhead (OH) signal (length of each row: 1 × 16 bytes), an information sequence. Is assigned to the area corresponding to the payload (length 238 × 16 bytes for each row) and the code parity sequence (length 16 × 16 bytes for each row). In addition, ITU-T Recommendation G. When the OTUkV frame described in Appendix 709 is considered, the frame format is as shown in FIG. In FIG. 7, the OH and payload have the same length as the OTUk frame, the parity sequence length is arbitrarily longer than that of the OTUk frame, and they are assigned to the parity sequence of the inner code. Further, as an outer code, ITU-T Recommendation G. When a concatenated code or a product code conforming to the OTUk frame as described in Appendix of 975.1 is used and the inner code is further concatenated, the frame format is as shown in FIG.

  Note that the frame generation circuit 32 is a necessary circuit when considering the frame format such as the OTUkV frame, but it is not necessary to be aware of the frame format, and digital transmission capable of continuous encoding is possible. It is not always necessary in the system.

  Returning to FIG. 1, the outer encoding circuit 33 then performs outer encoding processing (outer code encoding processing). The frame encoding input from the frame generation circuit 32 is subjected to input timing adjustment, input sequence order adjustment (including interleaving processing), etc. by the outer encoding input circuit 51, and outer encoding is performed by the outer encoding arithmetic circuit 52. The calculation is performed, and the outer encoding output circuit 53 performs output timing adjustment, output sequence order adjustment (including interleave processing), scramble processing, and the like, and outputs the result as an outer encoded output sequence (parallel).

  Note that hard-decision decoding is suitable as a method of outer coding calculation performed by the outer coding calculation circuit 52, and a block code that can reduce the circuit scale relatively, particularly a BCH (Bose-Chaudhuri-Hocquenghem) code or RS ( Reed-Solomon) code is suitable. It is also possible to use a concatenated code, a product code or the like having a higher error correction capability than the block code alone. In particular, as already described in FIG. A configuration example using a concatenated code, a product code, etc. conforming to the OTUk frame (a combination of a plurality of types such as a BCH code and an RS code of a block code) as described in Appendix of 975.1 is preferable. The configuration can also be made by combining a block code and a convolutional code.

  Further, timing adjustment, sequence order adjustment, and the like in the outer coding input circuit 51 and outer coding output circuit 53 vary depending on the type of outer code to be used, the presence / absence of interleaving and its configuration, the presence / absence of scrambling and its format, and the like. However, it is possible to constitute Embodiment 1 of the present invention regardless of the configuration. The output of the outer encoding output circuit 53 is configured in the form of an n-parallel normal bus signal, but it may be output after being converted to a predetermined interface standard such as SFI. In this case, the outer encoding circuit 33 and the inner encoding circuit 34 can be incorporated in different devices.

  Returning to FIG. 1, next, the inner encoding circuit 34 performs an inner encoding process (an inner code encoding process). Hereinafter, the inner encoding process will be described with reference to FIG. The inner coded input I / F circuit 71 performs input timing adjustment, descrambling processing, and the like on the outer coded output sequence (parallel) input from the outer coding circuit 33. When the output of the outer encoding output circuit 53 is output after being converted into a predetermined interface standard such as SFI, the inverse conversion is also performed. The inner coding input I / F circuit 71 outputs the processing result in the form of N parallel signals. The parallel number N can be defined as an arbitrary integer according to a predetermined frame format, but in the first embodiment, assuming that a frame conforming to the OTUkV frame is considered, N = 512 is described. To do. The above processing is performed, and N parallel signals are output to the 1-1 interleaving circuit 72.

  The 1-1 interleaving circuit 72 and the 1-2 interleaving circuit 73 perform sequence rearrangement processing on the basis of a predetermined frame format, and the resulting inner encoded input sequence is converted into an inner encoded arithmetic circuit 55. Output to. This specific rearrangement method will be described later.

  The inner coding operation circuit 55 performs an inner coding operation on the inner coded input sequence, and outputs the resulting inner coded output sequence to the inner coding output circuit 56. In addition, as a method of the inner coding operation, a block code such as a BCH code or an RS code, a convolutional code, a convolutional turbo code, a block turbo code, an LDPC (Low-Density Parity-Check) code, or the like can be applied. . However, as the inner code, a code having a high error correction capability and capable of soft decision decoding is suitable. In particular, the first embodiment will be described assuming that an LDPC code is used.

  In the inner coding output circuit 56, first, the 1-2 deinterleaving circuit 74 and the 1-1 deinterleaving circuit 75 perform rearrangement processing on the inner coding output sequence, and the result is inner coded. The data is transferred to the output I / F circuit 76. This specific rearrangement method will be described later. Although it is assumed here that the rearrangement process is performed, the rearrangement process is not necessarily performed depending on the conditions of a predetermined frame format. Further, not the rearrangement process but the rearrangement process may be performed in a different order from the input time of the inner encoding circuit 34.

  The inner coded output I / F circuit 76 performs output timing adjustment, scramble processing, and the like, and outputs the result as a codeword sequence (parallel). The output of the inner encoding output circuit 56 is configured in the form of N parallel normal bus signals, but may be output after being converted into a predetermined interface standard such as SFI. In this case, the inner encoding circuit 34 and the transmission side multiplexing circuit 35 can be incorporated in different devices.

  Finally, the transmission side multiplexing circuit 35 performs multiplexing conversion on the codeword sequence (parallel), generates a codeword sequence (serial), and outputs the codeword sequence to the D / A converter 12.

  Information (data) transmitted between the circuits 31 to 35 in the error correction encoder 11 and between the internal circuits 51 to 56, 71 to 73, and 74 to 76 is as follows. It may be configured to be delivered by a pipeline system via a bus connecting between circuits, or may be configured to be delivered by providing a working storage area that can be referred to from adjacent circuits. Also good. Further, a specific section, for example, between the outer encoding circuit 33 and the inner encoding circuit 34 may be connected with a predetermined interface standard such as SFI.

  Next, the operation of the error correction decoder 23 will be described. The error correction decoder 23 has a circuit configuration corresponding to the error correction encoder 11 and has a function of decoding the error correction code encoded by the error correction encoder 11.

  In FIG. 2, the quantized reception sequence (serial) input to the error correction decoder 23 is adjusted by a frame synchronization circuit 41 after adjusting the synchronization timing of a predetermined frame, and then the reception side demultiplexing circuit 42. Is input.

  The frame synchronization circuit 41 is necessary for detecting the OH added to the quantized reception sequence and specifying the head position of the frame when considering the frame format such as the OTUk frame and the OTUkV frame. However, this is not always necessary in a digital transmission system capable of continuous encoding without having to be aware of the frame format.

  The reception-side demultiplexing circuit 42 converts the quantized reception sequence (serial) into a parallel order. The converted quantized reception sequence (parallel) is output to the inner decoding circuit 43. The parallel number at this time is defined as “N”. The parallel number N can be defined as an arbitrary integer according to a predetermined frame format, but is preferably matched with the transmission side. In the first embodiment, it is assumed that N = 512 in order to match with the transmission side. .

  When the quantized reception sequence processed by the A / D converter 22 is quantized to q bits per transmission symbol, the case of q = 1 is “hard decision”, and the case of q> 1. Although referred to as “soft decision”, soft decision is assumed in the first embodiment. The parallel number N defined above is described as N symbol parallel for convenience because the q bits per transmission symbol are regarded as one symbol and the symbols are processed together.

  Next, the inner decoding circuit 43 performs inner decoding processing (decoding of the inner code). Hereinafter, the inner decoding process will be described with reference to FIG. An inner decoding input I / F circuit 81 performs input timing adjustment, descrambling processing, and the like on the quantized reception sequence (parallel) input from the receiving side demultiplexing circuit 42. When the output of the receiving side demultiplexing circuit 42 is output after being converted to a predetermined interface standard such as SFI, the inverse conversion is also performed. The processing result is output in the form of N parallel signals.

  The soft input value calculation circuit 82 converts a q-bit quantized reception sequence (parallel) per transmission symbol into a Q-bit soft input value (parallel) per transmission symbol. This conversion is a process required when a code suitable for soft decision decoding, for example, a convolutional code convolutional turbo code, a block turbo code, an LDPC code, or the like is selected. It is not necessary when performing hard decision decoding. In addition, when it is possible to process a q-bit quantized reception sequence (parallel) per transmission symbol as it is as a soft input value (parallel), the processing is similarly unnecessary. A specific processing method varies depending on a code to be used, a communication channel model, and the like. In the first embodiment of the present invention, any method can be applied.

  The 2-1 interleave circuit 83 and the 2-2 interleave circuit 84 perform sequence rearrangement processing based on a predetermined frame format, and output the resulting inner decoded input sequence to the inner decoding arithmetic circuit 62. To do. This specific rearrangement method will be described later. Note that this rearrangement order is performed in accordance with the rearrangement order processed by the transmitting-side 1-2 deinterleaving circuit 74 and the 1-1 deinterleaving circuit 75. Therefore, when the rearrangement process is not performed on the transmission side or when the rearrangement process is different, it is necessary to adjust the rearrangement order accordingly.

  The inner decoding operation circuit 62 performs an inner decoding operation, performs an inner decoding operation on the inner decoding input sequence, and outputs the resulting inner decoding output sequence to the inner decoding output circuit 63. This inner decoding process is performed according to the inner coding method. When a block code such as a BCH code or an RS code is selected, hard decision decoding is performed. When a convolutional code is selected, soft decision decoding is performed. When a convolutional turbo code, a block turbo code, an LDPC code, or the like is used. It is preferable to perform soft decision iterative decoding. In particular, the first embodiment will be described assuming that soft decision iterative decoding for an LDPC code is used.

  In the inner decoding output circuit 63, first, the 2-2 deinterleaving circuit 85 and the 2-1 deinterleaving circuit 86 perform rearrangement processing on the inner decoding output sequence, and the result is output as the inner decoding output I / Transfer to the F circuit 87. This specific rearrangement method will be described later. Although it is assumed here that the rearrangement process is performed, the rearrangement process is not necessarily performed depending on the conditions of a predetermined frame format. What is necessary is just to perform according to the rearrangement process by the transmission side, and it should just return to the order of the input time of the 1-1st interleave circuit 72 finally.

  The inner decoding output I / F circuit 87 performs output timing adjustment, scramble processing, and the like, and outputs the result as an inner decoding output sequence (parallel). The output of the inner decoding output circuit 63 is configured in the form of an n-parallel normal bus signal in accordance with the transmission side, but it may be output after being converted into a predetermined interface standard such as SFI. . In this case, the inner decoding circuit 43 and the outer decoding circuit 44 can be incorporated in different devices.

  Returning to FIG. 2, next, the outer decoding circuit 44 performs outer decoding processing (decoding of outer code). The outer decoding input circuit 64 performs input timing adjustment, input sequence order adjustment (including interleaving processing), descrambling processing, etc. on the inner decoding output sequence (parallel) input from the inner decoding circuit 43, and outer decoding is performed. The arithmetic circuit 65 performs an outer decoding operation, the outer decoding output circuit 66 performs output timing adjustment, output sequence order adjustment (including interleaving processing), and the like, and outputs the result as an estimated codeword sequence (parallel).

  When a block code suitable for hard decision decoding, particularly a BCH code or RS code, is selected as the outer coding method, in the outer decoding processing performed by the outer decoding arithmetic circuit 65, hard decision corresponding to outer coding is performed. Perform limit distance decoding. Further, when a concatenated code, a product code, or the like is used as an outer encoding method, it is preferable to perform hard decision iterative decoding in the outer decoding arithmetic circuit 65. It is also possible to output soft decision information (Q ′ bits per transmission symbol, Q ′> 1) as an inner decoding result and perform soft decision iterative decoding with an outer code. Further, as an inner decoding result, it is also possible to additionally output an erasure flag (a flag that sets 1 if a transmission symbol is lost and 0 otherwise) and performs decoding based on erasure correction with an outer code. . However, it is preferable to perform hard decision decoding based on hard decision information (Q ′ = 1) in the outer decoding process.

  Further, timing adjustment, sequence order adjustment, and the like in the outer decoding input circuit 64 and outer decoding output circuit 66 differ depending on the type of outer code to be used, the presence / absence of interleaving and its configuration, the presence / absence of scrambling and its format, etc. It is possible to constitute Embodiment 1 of the present invention in any format. The input of the outer decoding input circuit 64 is configured in the form of an n-parallel normal bus signal, but may be output after being converted into a predetermined interface standard such as SFI. In this case, the inner decoding circuit 43 and the outer decoding circuit 44 can be incorporated in different devices.

  The frame separation circuit 45 (corresponding to the frame generation circuit 32 on the transmission side) removes bits corresponding to the OH signal (overhead signal) and bits corresponding to the parity sequence from the estimated codeword sequence, and estimates information sequence (parallel) Is output. Finally, the receiving-side multiplexing circuit 46 performs multiplexing conversion on the estimated information sequence (parallel) to generate an estimated information sequence (serial) to generate a serial order or a predetermined interface standard such as SFI. Output in a format according to.

  Note that the frame separation circuit 45 is a necessary circuit when considering the frame format such as the OTUk frame, the OTUkV frame, etc., but can be continuously encoded without having to be aware of the frame format. Such a digital transmission system is not always necessary.

  Information (data) transmitted between the circuits 41 to 46 in the error correction decoder 23 and between the internal circuits 61 to 66, 81 to 84, and 85 to 87 is transmitted between the circuits. It may be configured to be delivered by a pipeline method via a bus to be connected, or may be configured to be delivered by providing a working storage area that can be referred to from adjacent front and rear circuits. Further, a specific section, for example, between the inner decoding circuit 43 and the outer decoding circuit 44 may be connected with a predetermined interface standard such as SFI.

  Here, the interleaving process and the deinterleaving process performed by the inner encoding circuit 34 and the inner decoding circuit 43 will be described.

  FIG. 9 shows the OTUkV frame shown in FIG. 7 or FIG. 8 with an N parallel, N = 512 internal data bus image. The most significant bit on the left side / column number 0 is the bit transmitted first. The data are arranged in order from the bottom to the bottom in the order of transmission, and the bits after 512 bits are sequentially arranged from the top of the next column number 1 to the bottom. Since the length of each row of the OTUk frame is 4080 bytes, in the 512 parallel, the 384th bit of the column number 63 is filled. Although the parity sequence length of the OTUkV frame can be arbitrarily set, in the description of the first embodiment, it is set to 256 bytes (OTUk frame parity sequence) +528 bytes. In that case, the lower 128 bits of the column number 63 and the column numbers 64 to 71 are filled in the parity sequence of the inner code. After Row 2, they are arranged after column number 72, and finally 512 parallels × 288 columns are arranged in one OTUkV frame.

  The problem here is the non-uniform inner code parity sequence region indicated by the black blocks at the 63rd, 135th, 207th, and 279th columns. This 128 bit × 4 column region is caused by the constraints of the frame length of the OTUk frame and the parallel number N = 512. When an LDPC code is used as an inner code, it is not practical to assign only one LDPC code code word to an OTUkV frame in consideration of the circuit scale, and it is necessary to assign to a plurality of code words. That is, each area of the overhead, payload, and outer code parity sequence is assigned to an information sequence of a plurality of LDPC code words, and an inner code parity sequence region shown in black and dark gray is assigned to a parity sequence of a plurality of LDPC code words. There is a need. For example, when the allocation method is divided into different codewords for each row, the information sequence region and the parity sequence region are not uniformly allocated in the upper 384 rows and the lower 128 rows.

  One solution to this problem is to assign LDPC codes having different information lengths and parity lengths on the upper side and the lower side. However, in this case, since it is necessary to implement two types of inner encoder and inner decoder, it is not very efficient.

  Therefore, in the first embodiment of the present invention, the parallel input sequence is classified into specific L lanes and subjected to interleaving for performing a specific barrel shift for each internal frame, so that the information sequence region and the parity sequence region are divided. Make the allocation uniform.

  First, the parallel input sequence of the parallel number N = 512 is classified into a specific lane. Here, one lane is set for every 128 bits, and the total L = 4 lanes. This 4-lane configuration is a multi-level modulation such as quadrature phase shift keying (QPSK), which is becoming mainstream in recent optical communications, and polarization multiplexing of polarization channels (X polarization, Y polarization). It has good affinity with the modulation method combining The number of lanes L can be defined as an arbitrary integer according to a predetermined frame format, and any number can constitute Embodiment 1 of the present invention.

Next, lane replacement processing is performed for each column. Various methods can be used for the replacement method for each column. For example, it is possible to perform rearrangement by barrel shift in units of lanes (128-bit units) for each column. It is also conceivable to change the shift amount of this barrel shift for every four FEC frames included in one OTUkV frame. FIG. 10 shows an example of this, and shows a state after rearrangement by barrel shift. Here, the barrel shift amount of each column of the first FEC frame included in the OTUkV frame is 0 bit, the barrel shift amount of each column of the second FEC frame is 128 bits lower, and the column shift amount of each column of the third FEC frame is barrel shift amount 256 bit lower, a barrel shift amount for each column of the last FEC frame 3 84-bit lower and so on. As is apparent from the figure, a black block appears once for each lane. Therefore, the allocation of the information sequence area and the parity sequence area for each row can be made uniform.

  FIG. 11 is a diagram showing an outer encoded output sequence (parallel) before the order is changed by the 1-1 interleaving circuit 72. In the figure, like 511-0 and 510-1, what is shown in the format of “RC” is a number indicating the position of each bit of the OTUk frame, and R is a row number (the upper side is 511). ) And C are column numbers (the left side is 0). The 1-1 interleaving circuit 72 does not change the order of the input time points (corresponding to each column) of the N = 512 parallel outer coded output series (parallel), and closes the input time points (for each column). Change the order. This column-by-column replacement method can be performed in various forms. In the first embodiment of the present invention, for example, it is described that the column shift is performed in units of lanes (128-bit units) for each column. . FIG. 12 is a diagram showing a sequence of OTUk frame sequences after the order has been changed in this way.

  Next, a method for assigning each codeword of the LDPC code is determined. This allocation method can be performed in various formats according to a predetermined frame format. Here, a format in which a codeword sequence of an LDPC code is allocated to a different codeword for each row is assumed.

  FIG. 13 is a diagram showing the order change in the 1-2 interleaving circuit 73. In the figure, like 000-4607 and 001-4591, what is shown in the format of “L # -B #” is a number indicating the code word number of the LDPC code and the bit position of each code word. , L # is a code word number (first code word is 0), and B # is a bit number (first bit is 4607). Here, it is assumed that 32 (8 per lane) LDPC codewords are assigned to each 1 OTUkV frame. Different code words L # = 000 to 007 are assigned to row numbers 511 to 504 of column number 0, and these are allocated to the first bit B # = 4607 of the code word. Also, row numbers 503 to 496 of column number 0 are allocated to bits B # = 4606 of codewords L # = 000 to 007, respectively. Also, a different code word is assigned to each lane. According to this procedure, the bits of the same code word included in each column are 16 bits. Since one OTUkV frame is composed of 288 columns, the code length of the LDPC code is 4608 bits. In this example, the information sequence length is 4080 bits and the parity sequence length is 528 bits.

  One advantage of the first embodiment of the present invention is that the number of interleaving stages can be easily expanded. In the previous paragraph, the number of interleaving stages is set as 1 OTUkV frame, but it may be set as 2 OTUkV frame or 4 OTUkV frame. FIG. 14 is a diagram showing the order change in the 1-2 interleave circuit 73 when the number of interleave stages is set to 4 OTUkV frames. If the parameters of the LDPC code are the same as those in the previous paragraph, it is necessary to allocate 128 codewords in the 4 OTUkV frame. As shown in FIG. 14, different code words are assigned to adjacent columns of column numbers 0, 1, 2, and 3 as shown in FIG. The procedure of assigning to a word and assigning the same row of column number 1 and column number 5 to the same code word is performed. That is, the number of interleaving stages can be increased without greatly changing the allocation rule of each codeword. FIG. 14 shows the first OTUkV frame among the four OTUkV frames, and the second and subsequent frames are similarly distributed.

  When the number of interleaving stages is 4 OTUkV frames, the reordering in the 1-1 interleaving circuit 72 uses a different barrel shift amount for each OTUkV frame in addition to a method for setting a different barrel shift amount for each FEC frame. You can also set it up.

  The 1-2 deinterleaving circuit 74 performs a process of returning the inner coded output sequence, that is, the LDPC codeword sequence, in the sequence of the input time points of the 1-2 interleaving circuit 73. Further, the 1-1 deinterleave circuit 75 performs a reverse operation of the barrel shift operation in the 1-1 interleave circuit 72 and performs a process of returning to the sequence of the input time points of the 1-1 interleave circuit 72. . Although it is assumed here that the rearrangement process is performed, the rearrangement process is not necessarily performed depending on the conditions of a predetermined frame format. Further, not the rearrangement process but the rearrangement process may be performed in a different order from the input time of the inner encoding circuit 34.

  The 2-1 interleave circuit 83 performs the same operation as the barrel shift operation in the 1-1 interleave circuit 72 on the quantized reception sequence (parallel). The 2-2 interleave circuit 84 The same operation as the LDPC codeword sequence assignment operation in the 1-2 interleave circuit 73 is performed to output an inner decoded input sequence, that is, a soft input sequence for each codeword of the LDPC code. Note that this rearrangement order is performed in accordance with the rearrangement order processed by the transmitting-side 1-2 deinterleaving circuit 74 and the 1-1 deinterleaving circuit 75. Therefore, when the rearrangement process is not performed on the transmission side or when the rearrangement process is different, it is necessary to adjust the rearrangement order accordingly.

  The 2-2 deinterleave circuit 85 performs processing for returning the inner decoded output sequence, that is, the LDPC estimated codeword sequence, in the sequence of the input time points of the 2-2 interleave circuit 84. Further, the 2-1 deinterleave circuit 86 performs the reverse operation of the barrel shift operation in the 2-1 interleave circuit 83 and performs the process of returning to the sequence of the input time points of the 2-1 interleave circuit 83. . Although it is assumed here that the rearrangement process is performed, the rearrangement process is not necessarily performed depending on the conditions of a predetermined frame format. What is necessary is just to perform according to the rearrangement process by the transmission side, and it should just return to the order of the input time of the 1-1st interleave circuit 72 finally.

  The above-described embodiment is not limited to the parameters shown in the above specific examples, and the error correction coding method, the length of the frame format, the number of input / output parallels, the transmission rate, etc. can be applied well. Needless to say, any combination is possible and can be realized.

  Further, the present invention is not limited to the optical transmission system and can be applied to various types of transmission systems such as subscriber wired communication, mobile wireless communication, and satellite communication.

  In the above-described embodiment, the example in which the inner code encoding process is performed after the outer code encoding process is performed in the error correction encoder 11 is described. After the code encoding process, the outer code encoding process may be performed. Similarly, in the above-described embodiment, the example in which the error correction decoder 23 performs the decoding process of the outer code after performing the decoding process of the inner code has been described. After the code decoding process, the inner code decoding process may be performed.

  As described above, according to the first embodiment of the present invention, the outer coding circuit 33, the inner coding circuit 34, the inner decoding circuit 43, the outer decoding circuit 44, and the interleave function for performing a specific barrel shift. Each input circuit and output circuit, and each input circuit and output circuit having a deinterleaving function for performing a specific barrel shift. By configuring in this way, an information sequence region and a parity sequence region Therefore, it is possible to avoid the restriction of the frame configuration, increase the processing throughput, and increase the error correction capability.

  DESCRIPTION OF SYMBOLS 11 Error correction encoder, 12 D / A converter, 13 Modulator, 14 Communication path, 21 Demodulator, 22 A / D converter, 23 Error correction decoder, 31 Transmission side demultiplexing circuit, 32 Frame generation circuit 33 Outer encoding circuit, 34 Inner encoding circuit, 35 Transmission side multiplexing circuit, 41 Frame synchronization circuit, 42 Reception side demultiplexing circuit, 43 Inner decoding circuit, 44 Outer decoding circuit, 45 Frame separation circuit, 46 Reception side Multiplexing circuit, 51 Outer encoding input circuit, 52 Outer encoding operation circuit, 53 Outer encoding output circuit, 54 Inner encoding input circuit, 55 Inner encoding operation circuit, 56 Inner encoding output circuit, 61 Inner decoding input Circuit, 62 inner decoding arithmetic circuit, 63 inner decoding output circuit, 64 outer decoding input circuit, 65 outer decoding arithmetic circuit, 66 outer decoding output circuit, 71 inner encoding input I / F (interface) ) Circuit, 72 1-1 interleave circuit, 73 1-2 interleave circuit, 74 1-2 deinterleave circuit, 75 1-1 deinterleave circuit, 76 intra-coded output I / F circuit, 81 decoding input I / F circuit, 82 soft input value arithmetic circuit, 83 2-1 interleave circuit, 84 2-2 interleave circuit, 85 2-2 deinterleave circuit, 86 second -1 deinterleave circuit, 87 inner decoding output I / F circuit.

Claims (8)

An outer encoding step for encoding an outer code of a parallel input sequence;
The parallel input sequence subjected to the encoding process of the outer code in the outer encoding step is divided into a plurality of lanes having a preset width, and a plurality of the parallel input sequences divided into the lanes are divided. For each of the internal frames, performing a barrel shift based on an integer multiple of the width of the lane, the integer multiple being 0 or more, an interleaving process step;
An inner encoding step for encoding an inner code of the parallel input sequence subjected to the barrel shift by the interleaving step ;
Error correction coding method characterized by comprising a. 2. The error correction code according to claim 1, wherein the interleaving processing step processes a plurality of frames in the parallel input sequence subjected to the encoding processing of the outer code in the outer encoding step as a unit. Method. The error correction coding method according to claim 2, wherein the interleaving processing step includes a method of switching the order of the barrel shift in units of frames and a method of switching for each internal frame. A decoding step among which performs decoding of the inner code of the parallel input sequence,
The parallel input sequence subjected to the decoding process of the inner code in the inner decoding step is divided into a plurality of lanes having a preset width, and a plurality of inner frames of the parallel input sequence divided into the lanes A de- interleaving process step for performing a barrel shift based on an integer multiple of the width of the lane, and the integer multiple is 0 or more ;
An error correction decoding method comprising: an outer decoding step of performing decoding processing of the outer code of the parallel input sequence subjected to the barrel shift by the deinterleave processing step . The de-interleaving processing step, an error correction decoding method according to claim 4, characterized in that for processing a plurality of frames in a unit decoding of the inner code in the parallel input sequence performed by the inner decoding step . The de-interleaving processing step, the order of the barrel shift, error correction decoding method according to claim 5, characterized in that it comprises a method of switching on a frame basis, and a method of switching every inner frame. An outer encoding circuit that performs encoding processing of an outer code of a parallel input sequence;
The parallel input sequence subjected to the encoding process of the outer code by the outer encoding circuit is divided into a plurality of lanes having a preset width, and a plurality of the parallel input sequences divided into the lanes are divided. For each of the internal frames, perform a barrel shift based on an integer multiple of the width of the lane, and the integer multiple is 0 or more, an interleave circuit;
An inner encoding circuit for performing an encoding process of the inner code of the parallel input sequence subjected to the barrel shift by the interleave circuit ;
Error correction coding apparatus characterized by comprising a. A decoding circuit among which performs decoding processing for inner code parallel input sequence,
The parallel input sequence subjected to the decoding process of the inner code by the inner decoding circuit is divided into a plurality of lanes having a preset width, and a plurality of inner frames of the parallel input sequence divided into the lanes against each performs barrel shift based on an integral multiple of the width of the lane, the integer multiple is 0 or more, and the de-interleave circuit,
An error correction decoding apparatus comprising: an outer decoding circuit that performs decoding processing of the outer code of the parallel input sequence subjected to the barrel shift by the deinterleave circuit .

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