KR101411720B1 - Method and apparatus for decoding system consisting of multiple decoders corresponding to variations of a single parity check matrix - Google Patents

Abstract

The present invention relates to a method of decoding an LDPC code for generating a plurality of different decoders using a parity check matrix of an LDPC code, and an LDPC code system including the LDPC code. The LDPC encoder includes an LDPC encoder for outputting an LDPC codeword through a channel, Decoding the LDPC codeword received through the first LDPC decoder and decoding the LDPC codeword received from the second LDPC decoder when the second LDPC decoder fails to decode the LDPC codeword, A first LDPC decoder for decoding an LDPC codeword according to a matrix, and a second LDPC decoder for receiving soft information of each bit from the first LDPC when decoding is failed in the first LDPC decoder, An LDPC codeword is decoded according to a new parity check matrix created from the parity check matrix of the LDPC codeword Includes a second LDPC decoder.
Therefore, it is possible to make several different decoders by using one LDPC parity check matrix, and it has an advantage that the code rate is not changed by using the existing code as it is without any additional encoding process. Also, the second LDPC decoder can be operated only when the first LDPC decoder fails to correct the error, so that the speed loss due to the additional operation can be minimized.

Description

[0001] The present invention relates to a decoding method of an LDPC code for generating a plurality of different decoders using a parity check matrix of an LDPC code, and an LDPC code system including the LDPC code, }

The present invention relates to a decoding method of an LDPC (Low Density Parity Check) code and an LDPC code system using the LDPC code. More particularly, the present invention relates to an LDPC Code decoding method and an LDPC code system including the same.

An LDPC code is a linear block code and includes k bits of information and p bits of parity. That is, the total length n is the sum of k and p. The code rate representing the length ratio of the information bits in the entire length can be expressed by k / n. The encoding of the LDPC code takes the input of k using the parity check matrix and outputs the output of n.

The decoding algorithm of the LDPC code is based on a message passing algorithm. The message passing algorithm is largely divided into two processes. First, a bit-to-check message passing is performed. In bit-check message passing, bit nodes bound to the same check node send and receive messages to inform other bit nodes of the same group. At this time, the structure in which the bit-check is bundled is fixed (to satisfy the even parity condition) so that the sum of the bit judgment values tied to the common check according to the parity check matrix becomes an even number. A check-bit message passing is performed after the bit-check message passing process. In check-bit message passing, messages are exchanged between check nodes tied to one bit node. The bit-check message passing and the check-bit message passing are iteratively repeated until it is decoded with a valid codeword or until the maximum number of iterations is reached. If the LDPC code is concatenated with another code, the error correction capability is improved. However, since the parity bit is increased by the additional encoding process, the code rate is lowered. It is also inevitable to increase the complexity due to the additional encoding process and the accompanying additional decoding process.

1, a conventional basic LDPC code system includes an LDPC encoder that encodes an LDPC code, which is input data, and transmits the LDPC code through a channel, and an LDPC encoder that receives an LDPC code received through the channel And an LDPC decoder (Decoder) for decoding the data.

The decoding process in the LDPC decoder operates iteratively until the determined value x_hat becomes a valid code word or until the maximum number of iterations is reached.

However, as described above, the conventional LDPC code system having the above configuration uses an LDPC code concatenated with another code for error correction capability, so that the parity bit is increased by an additional encoding process, . Further, there is a problem that the complexity increases due to the additional encoding process and the additional decoding process.

Korean Patent Publication No. 2008-0088030 (published on October 22, 2008). Korean Published Patent No. 2011-0000013 (Published date: 2011.03.03.)

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above problems, and an object of the present invention is to provide an LDPC code decoding method capable of generating a plurality of different decoders using one LDPC parity check matrix, I have to propose.

According to another aspect of the present invention, there is provided a decoding method of an LDPC code in which a code rate is not changed using an existing code without requiring an additional encoding process, and an LDPC code system including the decoding method.

According to another aspect of the present invention, there is provided a method of decoding an LDPC code capable of minimizing speed loss due to a second LDPC decoder operating only when a first LDPC decoder fails in error correction, And an LDPC code system including the same.

The solution to the problem of the present invention is not limited to those mentioned above, and other solutions not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of decoding an LDPC code, the method comprising: (a) outputting an LDPC codeword through a channel in an LDPC encoder; (b) (C) decoding soft-information of each bit from the first LDPC in a second LDPC decoder when decoding is failed in the first LDPC decoder; Decoding the LDPC codeword according to a new parity check matrix generated from a parity check matrix of the LDPC codeword received by the first LDPC decoder, and (d) when decoding is failed in the second LDPC decoder, 2 decoding the LDPC codeword according to the parity check matrix of the LDPC codeword after receiving the soft information newly generated after the decoding operation is finished from the LDPC codeword; Repeating the steps (c) and (d) until the LDPC code is decoded or until the maximum number of iterations is reached.

According to another aspect of the present invention, there is provided an LDPC code system including an LDPC encoder for outputting an LDPC codeword through a channel, an LDPC encoder for decoding the LDPC codeword received through the channel, A first LDPC decoder for decoding an LDPC codeword according to a parity check matrix of the LDPC codeword with newly generated soft-information after a decoding operation is completed in the second LDPC decoder when decoding in the LDPC decoder fails; Decoder for receiving soft information of each bit from the first LDPC when the first LDPC decoder fails to decode the soft information of each bit received from the first LDPC decoder, And a second LDPC decoder that decodes the LDPC codeword according to the check matrix.

Here, the new parity check matrix may have a new row formed by a linere operation of an even or odd number of rows in the parity check matrix of the LDPC codeword.

In addition, the new parity check matrix may be a parity check matrix of an LDPC codeword, or a parity check matrix of an even or odd number of columns, You can have a new column created.

In addition, the new parity check matrix is a linear operation of an even or odd number row (Row) and the column (Column) in the parity check matrix of the LDPC codeword (linera operation) a new row (Row) and the column (Column made of ).

When integrating the even or odd rows or columns into a binary sum, the bit nodes to which the two check nodes are bound can be tied to the combined check nodes, and the redundant bit nodes can be disconnected. The soft-information may be probability information of '1' or '0' of each bit.

According to the present invention, a plurality of different decoders can be created using one LDPC parity check matrix.

It also has the advantage of not changing the coding rate by using existing code without needing additional encoding process.

Also, the second LDPC decoder can be operated only when the first LDPC decoder fails to correct the error, so that the speed loss due to the additional operation can be minimized.

Also, as a result of implementing the LDPC code system according to the present invention, it is confirmed that the system exhibits strong error correction capability in a high SNR region as compared with the conventional LDPC code system.

The effects of the present invention are not limited to those mentioned above, and other effects not mentioned can be clearly understood by those skilled in the art from the following description.

1 is a block diagram of a conventional basic LDPC code system
2 is a block diagram of an LDPC code system according to a preferred embodiment of the present invention.
3 is a diagram showing an example of generating a row of a new parity check matrix by combining two rows of a parity check matrix with a binary sum
4 shows an example of combining two check nodes into one check node
5 is a graph showing the results of simulation of the error correction capability according to the SNR of the conventional LDPC code system and the LDPC system proposed by the present invention

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly explain the present invention in the drawings, parts not related to the description are omitted, and similar parts are denoted by similar reference numerals throughout the specification.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Example

4 is a block diagram of an LDPC code system according to a preferred embodiment of the present invention,

4, the LDPC code system of the present invention includes an LDPC encoder 110, a channel 120, a first LDPC decoder 130, and a second LDPC decoder 140 .

The LDPC encoder 110 encodes an input LDPC code and transmits the encoded data to a channel 120.

The LDPC encoder 110 performs an LDPC coding process to transmit data to be transmitted on the channel 120 without loss or distortion. When data transmitted through the channel coding process is transmitted through the wireless channel 120, several bits may be collected and transmitted as a single symbol. At this time, the procedure of mapping various bits to one symbol is called modulation.

The modulated data is converted into a signal for multiplex transmission through a multiplexing process or a multiple access method. As the multiplexing method, there are various methods such as CDM, TDM, and FDM. The signal passed through the multiplexing block is changed into a structure suitable for transmission to one or more multiple antennas and transmitted to a receiver through a wireless channel. In this process, the transmitted data may experience fading and thermal noise, which may cause distortion of the data. After receiving the distorted data, the receiving end performs a series of procedures of the transmitting end in reverse order. Demodulates the data mapped to the symbol into a bit stream, performs a channel decoding process, and restores the distorted data to original data.

The LDPC encoder 110 for performing the channel coding includes an H matrix which is a parity check matrix used for generating parity bits to be added to input data (information bits or systematic bits) And a Generation Matrix G matrix derived from the H matrix. That is, the LDPC encoder generates parity bits through the H or G matrix and the input data.

The first and second LDPC decoders 130 and 140 are devices for performing channel decoding on the received data (distorted Systematic Bits + Parity Bits) Confirm that the input data (systematic bits) are restored properly and re-execute the operation when the recovery fails.

More specifically, the first LDPC decoder 130 decodes the LDPC codeword received through the channel 120. At this time, if decoding is failed in the first LDPC decoder 130, the second LDPC decoder 140 receives soft-information of each bit from the first LDPC 130, And decodes the LDPC codeword according to a new parity check matrix created from a parity check matrix of the LDPC codeword with soft-information of each bit. Here, the soft-information indicates probability information of '1' or '0' of each bit. That is, the present invention uses a secondary LDPC decoder such as a second LDPC decoder that decodes the new LDPC decoder according to a new parity check matrix generated from the parity check matrix of the first LDPC decoder, and the number of such secondary LDPC decoders may be changed. In addition, the first LDPC decoder and the auxiliary LDPC decoder may be serial, parallel, or a combination of serial and parallel.

If the second LDPC decoder 140 fails to decode the data, soft-information newly generated after the decoding operation is completed in the second LDPC decoder 140 in the first LDPC decoder 130, And decodes the LDPC codeword according to the parity check matrix of the LDPC codeword.

As described above, in the embodiment of the present invention, extrinsic information is exchanged between the first and second LDPC decoders 130 and 140 until the LDPC code is decoded or the maximum number of iterations is reached And the LDPC codeword is decoded through the feedback process.

Here, the new parity check matrix may be a new even or odd number of rows or columns formed by a linere operation of an even or odd row or column in the parity check matrix of the LDPC codeword, A new even or odd number of rows or columns having a row or column or a linere operation of even or odd rows and columns in the parity check matrix of the LDPC codeword, And may have a row and a column. The new parity check matrix will be described later in detail with reference to FIG. 3 and FIG.

The second LDPC decoder 140 is based on a parity check matrix newly generated by the method proposed by the present invention. The LDPC code system of the present invention has an advantage that the complexity of the transmitter is maintained and the code rate is not changed since there is no additional encoding process. When decoding is performed on the receiving side, since the second LDPC decoder 140 is designed to operate only when the first LDPC decoder 130 fails to decode, the speed loss due to the additional operation can be minimized. That is, when the first LDPC decoder 130 fails to decode at the receiving end, the second LDPC decoder 140 operates. When the first LDPC decoder 130 receives soft-information of each bit, It comes. At this time, after the operation of the second LDPC decoder 140 is completed, the newly generated soft-information is passed to the first LDPC decoder 130. That is, the first and second LDPC decoders 130 and 140 have a feedback process for exchanging extrinsic information.

Next, a method of designing the second LDPC decoder 140 will be described. Since the decoder structure of the LDPC code is based on a parity check matrix, an additional parity check matrix is needed to design an additional decoder. The parity check matrix proposed in the present invention is a parity check matrix in which a new row (Low) or an odd number of rows (Low) or a combination of a column (Low) and a column ) Or a column or row (Low) and a column.

FIG. 3 is a diagram showing an example of generating a row of a new parity check matrix by combining two rows of the parity check matrix with a binary sum.

As shown in FIG. 3, a new parity check matrix is formed by adding two rows (Low) as a binary sum. The degree of check node degrade due to two binary sums (the number of bit nodes bounded by one check node) is still an even number, so even parity conditions are satisfied. That is, the existing code can be decoded using a new parity check matrix. At this time, if the condition that the number of rows to be combined is an even number is satisfied, decoding can be performed using a newly created matrix. Therefore, it is not necessary to have two (2) combinations.

In this way, a new parity check matrix can be created by adding even or odd columns to the binary sum, or even or odd numbered rows and columns can be combined into a binary sum In addition, a new parity check matrix can be created.

On the other hand, an arbitrary parity check matrix can be represented by a bipartite graph composed of a check node and a variable node. FIG. 4 shows an example of combining two check nodes into one check node using a bipartite graph.

Combining two rows in FIG. 4 means combining two check nodes when viewed with a bipartite graph. At this time, the bit nodes to which the two check nodes are bound are tied to the combined check nodes, and the redundant bit nodes are disconnected.

는 각각 제 1 LDPC 디코더(130), 제 2 LDPC 디코더(140)의 최대 반복 횟수를 나타낸다.

는 두 디코더의 피드백 횟수를 나타낸다. 즉, 도 5에서 기본적인 LDPC 부호 시스템(normal)은 제 1 LDPC 디코더(130)만 동작하고 최대 반복횟수가 250으로 고정된 시스템이다. 반면, 본 발명에서 제안하는 LDPC 부호 시스템은 제 1 LDPC 디코더(130)는 40, 제 2 LDPC 디코더(140)는 10 의 최대 반복횟수, 그리고 5번의 최대 피드백 횟수를 가진다. 결국 두 시스템 모두 250번의 최대 반복횟수로 고정되어 있는 것이다. 시뮬레이션 결과를 보면 높은 SNR 영역에서 제안된 시스템이 기존 시스템에 비해 좋은 오류 정정 능력을 보이는 것을 확인 할 수 있다.FIG. 5 is a simulation result of a basic LDPC code system (Normal) and an error correction capability according to the SNR (Signal to Noise Ratio) of the LDPC code system proposed in the present invention. The same AWGN data was generated at each SNR. here,

Represent the maximum number of repetitions of the first LDPC decoder 130 and the second LDPC decoder 140, respectively.

Represents the number of feedbacks of the two decoders. That is, in FIG. 5, the basic LDPC code system (normal) is a system in which only the first LDPC decoder 130 operates and the maximum number of repetitions is fixed at 250. On the other hand, in the LDPC coding system proposed in the present invention, the first LDPC decoder 130 has a maximum number of repetitions of 10, and the second LDPC decoder 140 has a maximum number of feedback times of 5 and 40, respectively. As a result, both systems are fixed at the maximum number of iterations of 250 times. Simulation results show that the proposed system shows better error correction performance than the existing system in the high SNR region.

The decoding method of the LDPC code according to the present invention and the LDPC code system including the LDPC code according to the present invention can solve the technical problem of the present invention by forming a plurality of different decoders using one LDPC parity check matrix .

It will be apparent to those skilled in the art that various modifications and changes can be made in the present invention without departing from the spirit or scope of the present invention as defined by the appended claims. It will be appreciated that such modifications and variations are intended to fall within the scope of the following claims.

110: LDPC Encoder
120: Channel
130: a first LDPC decoder;
140: a second LDPC decoder;

Claims (13)

(a) outputting an LDPC codeword through a channel in an LDPC encoder;
(b) decoding the LDPC codeword output through the channel in a first LDPC decoder;
(c) when decoding in the first LDPC decoder fails, at least one second LDPC decoder receives soft-information of each bit from the first LDPC, and outputs soft-information of each bit from the parity check matrix of the LDPC codeword Decoding the LDPC codeword according to the generated new parity check matrix;
(d) when decoding is failed in the at least one second LDPC decoder, receiving the newly generated soft information after decoding from the at least one second LDPC in the first LDPC decoder, Decoding an LDPC codeword according to a parity check matrix; And
(e) repeating the steps (c) and (d) until the LDPC code is decoded or until a maximum number of iterations is reached,
The first LDPC decoder and the at least one second LDPC decoder form a decoding system composed of serial, parallel, or a combination of serial and parallel,
The new parity check matrix may include at least one of a new row and a column formed by a linereal operation of an even or odd number of rows in the parity check matrix of the LDPC codeword, And a number of rows and columns different from the parity check matrix of the parity check matrix.
delete delete delete delete delete The method according to claim 1,
When the even or odd rows or columns are combined into a binary sum, the bit nodes bounded by the two check nodes are bound to the combined check node, and the redundant bit node is decoded by the decoding method of the LDPC code .
The method according to claim 1,
Wherein the soft-information is probability information of '1' or '0' of each bit.
An LDPC encoder for outputting an LDPC codeword through a channel;
Decoding the LDPC codeword received through the channel and generating soft-information newly generated after the decoding operation is completed in the at least one second LDPC decoder when decoding in the at least one second LDPC decoder fails, A first LDPC decoder for decoding an LDPC codeword according to a parity check matrix of the LDPC codeword; And
When decoding is failed in the first LDPC decoder, soft information of each bit is received from the first LDPC, and a new parity check matrix is generated from the parity check matrix of the LDPC codeword with soft information of each received bit And at least one second LDPC decoder for decoding an LDPC codeword,
The first LDPC decoder and the at least one second LDPC decoder form a decoding system composed of serial, parallel, or a combination of serial and parallel,
The new parity check matrix may include at least one of a new row and a column formed by a linereal operation of an even or odd number of rows in the parity check matrix of the LDPC codeword, Wherein the parity check matrix comprises a plurality of rows and columns different from the parity check matrix of the parity check matrix.
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