JP7408671B2 - シストリックアレイに対するブロックスパース演算のためのアーキテクチャ - Google Patents

シストリックアレイに対するブロックスパース演算のためのアーキテクチャ Download PDF

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JP7408671B2
JP7408671B2 JP2021547450A JP2021547450A JP7408671B2 JP 7408671 B2 JP7408671 B2 JP 7408671B2 JP 2021547450 A JP2021547450 A JP 2021547450A JP 2021547450 A JP2021547450 A JP 2021547450A JP 7408671 B2 JP7408671 B2 JP 7408671B2
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matrix
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JP2022523761A (ja
JPWO2020190809A5 (enExample
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アップー，アビシェク
マイユラン，スブラマニアム
マクファーソン，マイク
フゥ，ファーンウェン
チェン，ジアシュヨン
ジョージ，ヴァーギーズ
ランガナタン，ヴァサント
ガルグ，アシュトシュ
レイ，ジョイディープ
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インテル コーポレイション
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JP2021547450A 2019-03-15 2020-03-14 シストリックアレイに対するブロックスパース演算のためのアーキテクチャ Active JP7408671B2 (ja)

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Application Number Priority Date Filing Date Title
US201962819337P 2019-03-15 2019-03-15
US201962819361P 2019-03-15 2019-03-15
US201962819435P 2019-03-15 2019-03-15
US62/819,361 2019-03-15
US62/819,435 2019-03-15
US62/819,337 2019-03-15
US201962935670P 2019-11-15 2019-11-15
US62/935,670 2019-11-15
PCT/US2020/022847 WO2020190809A1 (en) 2019-03-15 2020-03-14 Architecture for block sparse operations on a systolic array

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JP2022523761A JP2022523761A (ja) 2022-04-26
JPWO2020190809A5 JPWO2020190809A5 (enExample) 2022-07-13
JP7408671B2 true JP7408671B2 (ja) 2024-01-05

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JP2021547288A Active JP7494197B2 (ja) 2019-03-15 2020-03-14 行列アクセラレータアーキテクチャ内のシストリック分解
JP2021547452A Active JP7423644B2 (ja) 2019-03-15 2020-03-14 行列アクセラレータアーキテクチャのためのスパース最適化
JP2024006026A Active JP7717863B2 (ja) 2019-03-15 2024-01-18 行列アクセラレータアーキテクチャのためのスパース最適化

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JP2021547452A Active JP7423644B2 (ja) 2019-03-15 2020-03-14 行列アクセラレータアーキテクチャのためのスパース最適化
JP2024006026A Active JP7717863B2 (ja) 2019-03-15 2024-01-18 行列アクセラレータアーキテクチャのためのスパース最適化

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US (8) US11113784B2 (enExample)
EP (4) EP3938888A1 (enExample)
JP (4) JP7408671B2 (enExample)
KR (3) KR20210135999A (enExample)
CN (5) CN113383310A (enExample)
AU (1) AU2020241262B2 (enExample)
BR (2) BR112021016106A2 (enExample)
DE (2) DE112020000846T5 (enExample)
DK (1) DK3938890T3 (enExample)
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