JP7406104B2 - Memory control circuit and memory device - Google Patents

Description

The present invention relates to a memory control circuit and a memory device.

A memory control circuit that controls a volatile memory (hereinafter simply referred to as memory) such as a DRAM (Dynamic Random Access Memory) periodically generates a refresh during a period in which a read or write request to the memory is accepted.

For memory that requires refresh, refresh must occur within a predetermined period due to specifications. Therefore, when a request and a refresh conflict, the memory control circuit sometimes puts the request on hold and performs control that gives priority to the refresh.

Conventionally, in order to suppress delays in read and write operations due to refresh processing that is forcibly executed by interrupts, there has been a technology that executes refresh processing during an idle period when burst read or burst write processing is not being performed (for example, patented (See Reference 1).

Japanese Patent Application Publication No. 2009-157549

Incidentally, the request issuance interval is not constant, and even if the issuance interval is short, if a refresh occurs during a period when no requests are issued, the waiting time for the request may become long.

In one aspect, the present invention aims to provide a memory control circuit and a memory device that can reduce request waiting time.

In one embodiment, a request generating unit generates a read or write request for a memory to be refreshed and outputs the request, and a first issuing interval of the request is set to a request continuity determination unit that determines that a continuous group of requests is issued when the second issuance interval of the refresh is less than a second threshold; a refresh issuance inhibiting unit that suppresses issuance of the refresh while it is determined that the refresh is in the state, and allows issuance of the refresh when the second issuance interval reaches the second threshold; A memory control circuit having a memory control circuit is provided.

Also, in one embodiment, a memory device is provided.

In one aspect, the invention can reduce request latency.

1 is a diagram showing an example of a memory device and a memory control circuit according to a first embodiment; FIG. FIG. 7 is a diagram illustrating an example of a memory device according to a second embodiment. FIG. 3 is a diagram illustrating an example of a refresh storage unit. FIG. 3 is a diagram illustrating an example of a request continuity determination unit. 3 is a flowchart showing an example of the operation of the memory control circuit. FIG. 3 is a state transition diagram of a memory control circuit. 5 is a timing chart showing an example of temporal changes in signals of each part of the memory control circuit. 5 is a timing chart showing an example of temporal changes in signals of various parts within the request continuity determination section. This is a memory device as a comparative example. 7 is a timing chart showing an example of temporal changes in signals of each part of a memory control circuit of a memory device of a comparative example.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram showing an example of a memory device and a memory control circuit according to the first embodiment.

The memory device 10 has a memory 11 and a memory control circuit 12.
The memory 11 is a memory such as DRAM or HBM (High Bandwidth Memory) that is refreshed to hold data.

The memory control circuit 12 includes a request generation section 12a, a request storage section 12b, a request continuity determination section 12c, a refresh generation section 12d, and a selection section 12e.
The request generation unit 12a generates a read or write request for the memory 11 based on a signal input from outside the memory device 10 (for example, a read command or a write command specifying a certain address), and sends the request. Output (issue). Further, the request generating unit 12a outputs a signal indicating whether or not a request is being issued (hereinafter referred to as a request issuing status signal).

The request storage unit 12b includes, for example, a register, and temporarily stores requests issued by the request generation unit 12a. This is because, depending on the specifications of the memory 11, there is a period during which the memory 11 cannot receive requests. Further, the request storage unit 12b performs clock switching when the request generation unit 12a and the selection unit 12e are circuits in different clock domains.

The request continuity determination unit 12c detects the request issuance interval based on the request issuance status signal during the request acceptance period in the memory 11, and if the request issuance interval is less than a first threshold value, the request continuity determination unit 12c detects a request issuance interval based on the request issuance status signal, and determines whether a group of consecutive requests is received. It is determined that the group is in the issuing state. When the data size of write data or read data is large, a somewhat continuous request group is often formed (although there may be some gaps in the middle). The request continuity determination unit 12c can determine whether such a request group is being issued by comparing the request issuance interval and the first threshold.

Furthermore, when the request continuity determination unit 12c has finished issuing requests, it outputs a signal indicating the end of issuing the request group after the first threshold period has elapsed. Furthermore, the request continuity determination unit 12c may perform clock switching when the request generation unit 12a and the refresh generation unit 12d are circuits in different clock domains. A circuit example of the request continuity determination unit 12c will be described later.

The first threshold value is appropriately set, for example, depending on how much priority is given to a request over a refresh. The larger the first threshold value is, the more likely it is that multiple requests will be determined as a group of consecutive requests even if the issuance interval is wide, and the more likely it will be that refresh issuance will be suppressed by the function of the refresh issue suppression unit 12d1, which will be described later. Therefore, the priority of the request increases.

The refresh generation unit 12d periodically issues a signal for generating refresh during a period in which refresh issuance is not suppressed by the function of the refresh issue suppression unit 12d1, which will be described later. The refresh issue interval (the issue interval of the signal that causes refresh) does not have to be constant and can be adjusted within a range that satisfies the specifications of the memory 11.

The selection unit 12e selects either the output of the request storage unit 12b or the output of the refresh generation unit 12d, and supplies the selected output to the memory 11. In the memory 11, when the refresh bus and the request bus are common, such a selection unit 12e is used.

In the example of FIG. 1, the refresh generation unit 12d includes a refresh issue suppression unit 12d1.
If the refresh issuance interval (period in which no refresh is issued) is less than a second threshold, the refresh issue suppression unit 12d1 prevents the refresh while it is determined that a continuous group of requests is being issued. Suppress publication. Further, the refresh issue suppression unit 12d1 allows the issue of refresh when the refresh issue interval reaches a second threshold.

The second threshold is, for example, the upper limit of the refresh issue interval that is set according to the specifications of the memory 11. Furthermore, in this specification, "suppression" means an operation in which a refresh is not issued for a certain period of time, and a refresh that was supposed to be issued during that period is delayed and issued after that period. This does not mean that the issuance itself will disappear. This is because the refresh process in the memory 11 is performed a predetermined number of times within a predetermined total refresh period according to specifications.

Note that the memory control circuit 12 may include a refresh storage section that temporarily stores refreshes issued by the refresh generation section 12d and adjusts the interval at which refreshes are issued to the memory 11. In that case, the refresh issue suppression unit 12d1 may be included in the refresh storage unit.

FIG. 1 shows an example of the operation of the memory control circuit 12.
When the request generating unit 12a issues a request, the logic level of the request issuing state signal rises from the L (Low) level to the H (High) level (timing t1). In response to this change, the request continuity determination unit 12c outputs a pulse signal with an H logic level (hereinafter referred to as a request group issuance start signal) indicating the start of issuance of a continuous group of requests. As a result, the refresh issue suppression unit 12d1 starts suppressing refresh issuance.

In the example of FIG. 1, the request generation unit 12a finishes issuing the request at timing t2, and then issues the request again at timing t3. As shown in FIG. 1, if T (=t3-t2), which is the interval between issuing two requests at this time, is less than Tth1, which is the above-mentioned first threshold, the request continuity determination unit 12c determines whether It is determined that a group of requests is being issued. In this case, the request continuity determination unit 12c does not output a pulse signal having an H logic level (hereinafter referred to as a request group issuance end signal) indicating the end of issuance of a continuous group of requests. Therefore, the refresh issue suppression unit 12d1 continues to suppress the issue of refresh.

In the example of FIG. 1, the request generation unit 12a finishes issuing requests at timing t4, and has not issued the next request even after a period of Tth1 has elapsed from timing t4. Therefore, the request continuity determination unit 12c outputs a refresh group issue end signal after the period Tth1 has elapsed (timing t5). As a result, the refresh issue suppression unit 12d1 allows the refresh issue.

In this way, the memory control circuit 12 of the memory device 10 of the first embodiment determines the continuity of requests during the request reception period in the memory 11, and if the request issuance interval is less than the first threshold, Suppresses issuing refreshes. As a result, even when the request issuance interval is short, refreshing is suppressed from being issued between requests, and the occurrence of request waiting is suppressed. Therefore, the waiting time for requests can be reduced. Furthermore, since the wait time for requests can be reduced, delays in read and write operations can be reduced, and the performance (request processing speed) of the memory device 10 can be improved.

(Second embodiment)
FIG. 2 is a diagram illustrating an example of a memory device according to the second embodiment. In FIG. 2, the same elements as those shown in FIG. 1 are given the same reference numerals.

The memory control circuit 21 in the memory device 20 of the second embodiment temporarily stores the signal that generates refresh that is periodically issued by the refresh generator 21b, and adjusts the interval at which refresh is issued to the memory 11. It has a refresh storage section 21c.

FIG. 3 is a diagram showing an example of a refresh storage section.
The refresh storage unit 21c includes a refresh issue interval counter 21c1, an upper limit setting register 21c2, a comparator 21c3, an OR circuit 21c4, a refresh issue suppression unit 21c5, and an issue interval adjustment circuit 21c6.

The refresh issue interval counter 21c1 is a counter that counts the refresh issue interval (period in which a refresh is not issued). The refresh issue interval counter 21c1 counts up the count value in synchronization with, for example, a clock signal (not shown) until the issue interval adjustment circuit 21c6 outputs a signal for generating refresh. When the issue interval adjustment circuit 21c6 outputs a signal for generating refresh, the refresh issue interval counter 21c1 resets the count value.

The upper limit setting register 21c2 is a register in which an upper limit value of the refresh issue interval is set. The upper limit value of the refresh issue interval is set according to the specifications of the memory 11 at the time of initial setting of the memory device 20, for example.

The comparator 21c3 outputs a comparison result between the count value counted by the refresh issue interval counter 21c1 and the upper limit value. In the example below, the comparator 21c3 outputs a signal whose logic level is L level until the count value reaches the upper limit value, and outputs a signal whose logic level is H level when the count value reaches the upper limit value. However, it is not limited to this.

The output signal of the comparator 21c3 is supplied to the OR circuit 21c4 and the request continuity determination section 21a. When the logic level of the output signal of the comparator 21c3 is H level, the request continuity determination unit 21a is instructed to forcibly terminate the issuance of a continuous group of requests.

The OR circuit 21c4 combines the output signal of the comparator 21c3 and a signal output by the request continuity determination unit 21a that instructs whether or not to issue a refresh (indicating whether or not the issuance of a continuous group of requests is completed. outputs the logical sum (OR) with the signal). When the logic level of the output signal of the OR circuit 21c4 is H level, it corresponds to the above-mentioned request group issuance end signal and instructs the issuance of refresh, but is not limited thereto.

The refresh issue suppression unit 21c5 combines the output signal of the OR circuit 21c4 and a signal output by the request continuity determination unit 21a that instructs whether or not to suppress the issuance of refresh (whether the issuance of a continuous group of requests has started or not). (signal indicating whether or not) is received. When the logic level of the output signal of the OR circuit 21c4 is at the L level, or when receiving a signal instructing to suppress the refresh issue, the refresh issue suppressing unit 21c5 suppresses the issue of the refresh. In the example below, when the logic level is H level, the signal instructing whether to suppress issuance of refresh corresponds to the above-mentioned request group issuance start signal, and instructs to suppress issuance of refresh. However, it is not limited to this.

The refresh issue suppression unit 21c5 is, for example, a reset-prioritized flip-flop that has a set terminal and a reset terminal, and holds a logical value “1” or a logical value “0”. In this case, a signal instructing whether to suppress issuance of refresh is input to the set terminal, and an output signal of the OR circuit 21c4 is input to the reset terminal. Then, when the logic level of the signal instructing whether or not to suppress the refresh issue becomes H level, "1" is set in the refresh issue inhibiting section 21c5, and the logic level of the signal to suppress the refresh issue is H level. is output. Hereinafter, the state in which "1" is set in the refresh issue inhibiting section 21c5 will be referred to as a refresh issue inhibited state.

Further, when the refresh issue interval reaches the upper limit value or a signal instructing refresh issue is supplied, the logic level of the output signal of the OR circuit 21c4 becomes H level. At this time, the refresh issue suppression unit 21c5 is reset to “0”, and the refresh issue suppression unit 21c5 outputs a signal whose logic level is L level.

The issue interval adjustment circuit 21c6 has, for example, a register, temporarily stores a signal for generating a refresh issued by the refresh generation unit 21b, and adjusts the interval at which the refresh is issued to the memory 11. Further, the issue interval adjustment circuit 21c6 does not output a signal for generating refresh while the refresh issue inhibiting unit 21c5 instructs to suppress the issue of refresh.

FIG. 4 is a diagram illustrating an example of a request continuity determination section.
The request continuity determination unit 21a includes a request no-period counter 21a1, an upper limit setting register 21a2, a comparator 21a3, OR circuits 21a4, 21a9, AND circuits 21a5, 21a6, 21a7, 21a8, and a request group issuance status determination unit 21a10.

The request no-period counter 21a1 is a reset-prioritized counter, and counts the period (request interval) in which no requests are issued when a continuous group of requests is issued. For example, when the logic level of the output signal of the OR circuit 21a9 is L level and the logic level of the output signal of the AND circuit 21a7 is H level, the request non-period counter 21a1 calculates the count value in synchronization with a clock signal (not shown). Count up. Further, the request non-period counter 21a1 resets the count value when the output signal of the OR circuit 21a9 is at the H level, and does not perform a counting operation while the output signal of the OR circuit 21a9 is at the H level.

The upper limit setting register 21a2 holds the upper limit value of the request interval for determining a continuous group of requests. The upper limit value of the request interval is set, for example, at the time of initial setting of the memory device 20.

The comparator 21a3 outputs a comparison result between the count value counted by the request no-period counter 21a1 and the upper limit value. In the example below, the request no-period counter 21a1 outputs a signal whose logic level is L level until the count value reaches the upper limit value, and when the count value reaches the upper limit value, a signal whose logic level becomes H level. However, the output is not limited to this.

The OR circuit 21a4 outputs the logical sum (OR) of the output signal of the comparator 21a3 and the output signal of the comparator 21c3 of the refresh storage section 21c shown in FIG.
The AND circuit 21a5 outputs the logical product (AND) of the request issuing state signal outputted by the request generating section 12a and a signal obtained by inverting the logic level of the output signal of the request group issuing state determining section 21a10. In the following example, when the logic level of the request issuing state signal is H level, it indicates that a request is being issued, but the request is not limited to this. Further, in the following example, when the logic level of the output signal of the request group issuance state determination unit 21a10 is H level, it indicates that a continuous request group is in the issuance state; however, the present invention is not limited to this. It's not something you can do. The output signal of the AND circuit 21a5 is a signal instructing whether or not to suppress the above-mentioned refresh issuance, and is supplied to the request group issuance status determination unit 21a10 and the refresh storage unit 21c.

The AND circuit 21a6 outputs the logical product of the output signal of the OR circuit 21a4 and the output signal of the request group issuance state determination unit 21a10. The output signal of the AND circuit 21a6 is a signal instructing whether or not to issue the above-mentioned refresh, and is supplied to the request group issuance status determination section 21a10 and the refresh storage section 21c.

The AND circuit 21a7 outputs the logical product of a signal obtained by inverting the logic level of the request issuing state signal output by the request generating section 12a and the output signal of the request group issuing state determining section 21a10.

The AND circuit 21a8 outputs the logical product of the request issuance status signal output by the request generation unit 12a and the output signal of the request group issuance status determination unit 21a10.
The OR circuit 21a9 outputs the logical sum of the output signal of the AND circuit 21a6 and the output signal of the AND circuit 21a8.

The request group issuance state determining unit 21a10 outputs a signal indicating whether or not a continuous request group is in the issuance state based on the output signals of the AND circuit 21a5 and the AND circuit 21a6.

The request group issuance state determining unit 21a10 is, for example, a flip-flop that has a set terminal and a reset terminal and holds a logical value of "1" or a logical value of "0". In this case, the output signal of the AND circuit 21a5 is input to the set terminal, and the output signal of the AND circuit 21a6 is input to the reset terminal. Then, when a request is issued when the logic level of the output signal of the request group issuance state determining unit 21a10 is at the L level, the logic level of the output signal of the AND circuit 21a5 becomes the H level. At this time, "1" is set in the request group issuance state determination unit 21a10, and a signal with a logic level of H level indicating that a continuous request group is in the issuance state is output. Hereinafter, the state in which "1" is set in the request group issuance state determination unit 21a10 will be referred to as the request group issuance state.

Further, in the request group issuing state, if the request interval reaches the upper limit value or the refresh issue interval reaches the upper limit value, the logic level of the output signal of the AND circuit 21a6 becomes H level. At this time, the request group issuance state determination section 21a10 is reset to "0", and the request group issuance state determination section 21a10 has a logic level of L indicating that it is not in the request group issuance state (hereinafter referred to as the request group non-issuance state). Outputs a level signal.

Note that the request continuity determination unit 12c of the memory control circuit 12 of the first embodiment shown in FIG. 1 can also be realized by a circuit as shown in FIG. In that case, the output signals of the AND circuits 21a5 and 21a6 in FIG. 4 are supplied to the refresh generation section 12d in FIG. 1. Further, the refresh generation unit 12d includes a refresh issue interval counter 21c1, an upper limit setting register 21c2, a comparator 21c3, and an OR circuit 21c4 as shown in FIG. The data will be supplied to the gender determining section 12c.

The following is a diagram showing an example of the operation of the memory control circuit 21 according to the second embodiment.
FIG. 5 is a flowchart showing an example of the operation of the memory control circuit.
When the request generating section 12a issues a request (step S1), the request continuity determining section 21a sets the request group issuing state, and the refresh storage section 21c sets the request group issuing state (step S2).

If the refresh issue interval has not reached the upper limit (step S3: NO) and the request interval has not reached the upper limit (step S4: NO), the request group issue state and the refresh issue prohibited state are maintained. Ru.

If the refresh issue interval reaches the upper limit value (step S3: YES) or if the request interval reaches the upper limit value (step S4: YES), the request group issue state and the refresh issue prohibition state are canceled (step S3: YES). S5). As a result, a refresh is issued (step S6). This completes the process from issuing a request to issuing the next refresh.

FIG. 6 is a state transition diagram of the memory control circuit.
FIG. 6 shows an example of state transitions among four states: a request group issuing state, a request group non-issuing state, a refresh issue prohibiting state, and a refresh issuing permitting state.

When a request is issued in the request group non-issuing state, a state transition occurs from the request group non-issuing state to the request group issuing state. Further, the request continuity determination unit 21a issues an instruction to suppress the issuance of refresh (refresh suppression instruction) to the refresh storage unit 21c, and a state transition occurs from the refresh issue permission state to the refresh issue prohibition state.

When the request interval reaches the upper limit value in the request group issuing state, a state transition occurs from the request group issuing state to the request group non-issuing state. Further, the request continuity determination unit 21a issues a refresh issue instruction (refresh issue instruction) to the refresh storage unit 21c, and a state transition occurs from the refresh issue prohibited state to the refresh issue allowed state.

Furthermore, in the refresh issue prohibition state, if the refresh issue interval reaches the upper limit value, a state transition occurs from the refresh issue prohibition state to the refresh issue permission state. Further, the refresh storage unit 21c issues a request group issue forced termination instruction to the request continuity determination unit 21a, and a state transition occurs from the request group issuing state to the request group non-issuing state.

Next, temporal changes in signals of each part of the memory control circuit 21 will be explained using a timing chart.
FIG. 7 is a timing chart showing an example of temporal changes in signals of each part of the memory control circuit.

FIG. 7 shows temporal changes in the request issuance status signal, request group issuance start signal, and request group issuance end signal output by the request generation unit 12a. Furthermore, FIG. 7 shows changes over time in the storage state of requests in the request storage section 12b and the output state of requests in the request storage section 12b. Regarding the request storage state, when the logic level is H level, it indicates that the request is stored, and when the logic level is L level, it indicates that no request is stored (empty state). Regarding the request output state, when the logic level is H level, it indicates that the request storage unit 12b is outputting a request, and when the logic level is L level, it indicates that the request storage unit 12b is not outputting a request. show. Even if the requests issued by the request generation unit 12a are continuous, if reading from the request storage unit 12b is fast, the request storage unit 12b becomes temporarily empty. An example is shown in FIG.

Further, FIG. 7 shows temporal changes in the output signal of the refresh issue suppression unit 21c5 and the output signal of the refresh storage unit 21c (signal supplied to the selection unit 12e (indicated as “refresh generation signal”)). has been done. Furthermore, although not shown in FIG. 3, FIG. 7 shows, for example, a temporal change in a signal further output by the refresh storage unit 21c, which indicates whether or not to suppress issuance of a request. The signal indicating whether or not to suppress the issuance of a request is a signal whose logic level remains at the H level for a predetermined period (the period during which refresh is executed) from the timing when the logic level of the refresh generation signal falls from the H level to the L level. It is. A signal indicating whether or not to suppress the issuance of a request is supplied to the request storage unit 12b.

In the example of FIG. 7, at timing t10, the logic level of the refresh generation signal rises from L level to H level, and then, at timing t11, the logic level of the refresh generation signal falls from H level to L level. At this time, the logic level of a signal indicating whether or not to suppress the issuance of a request rises from L level to H level.

At timing t12, when the request generator 12a issues a request, a request group issue start signal is output. As a result, the request continuity determination unit 21a issues the above-mentioned refresh suppression instruction to the refresh storage unit 21c, and at timing t14, the logic level of the output signal of the refresh issue suppression unit 21c5 rises from the L level to the H level.

At timing t13, the request storage unit 12b is in a state where the request is stored, but does not output the request until the logic level of the signal indicating whether to suppress the issuance of the request falls from the H level to the L level. At timing t14, the logic level of the signal indicating whether or not to suppress the issuance of a request has fallen from the H level to the L level. Thereby, the request storage section 12b outputs the request.

While the logic level of the output signal of the refresh issue inhibiting section 21c5 is at H level, the refresh issue is prohibited. Therefore, at timings t15 and t17, the refresh generation signal whose logic level was supposed to rise from L level to H level does not change, and no refresh is issued. Note that the refresh that has not been issued will be issued with a delay after the logic level of the output signal of the refresh issue inhibiting section 21c5 falls to the L level.

When the issuance of requests ends (timing t16) and the request interval reaches the upper limit value, a request group issuance end signal is output (timing t18). As a result, the request continuity determination unit 21a issues a refresh issue instruction to the refresh storage unit 21c, and at timing t19, the logic level of the output signal of the refresh issue suppression unit 21c5 falls from the H level to the L level.

Therefore, at timing t20, the logic level of the refresh generation signal rises from the L level to the H level, and, for example, the refresh that was supposed to be issued at timing t15 is issued.

FIG. 8 is a timing chart showing an example of temporal changes in signals of each part within the request continuity determination part.
FIG. 8 shows the request issuance status signal supplied from the request generation unit 12a to the request continuity determination unit 21a, and changes over time in the issuance status of the request group determined by the request group issuance status determination unit 21a10. Furthermore, changes over time in the count value of the request no-period counter 21a1, the value set in the upper limit setting register 21a2 (upper limit value of the request interval), and changes over time in the request group issuance start signal and the request group issuance end signal are shown. .

In the example shown in FIG. 8, the request no-period counter 21a1 is set during a period other than the period from when the request group issuance start signal is output until the request group issuance end signal is output (the period when the request group is not issued). is not counting up (counting operation). The request no-period counter 21a1 may count up even in the request group non-issuance state, but since the counted value in the request group non-issuance state is not used, the count is incremented as shown in FIG. 8 in order to reduce power consumption. It is desirable not to do so. In the example of FIG. 8, 3 is set as the upper limit value in the upper limit setting register 21a2.

When the request generation unit 12a issues a request in the request group non-issuance state (timing t30), the AND circuit 21a5 of the request continuity determination unit 21a outputs a refresh group issuance start signal. This causes the request group to be issued.

In the example of FIG. 8, the request generation unit 12a finishes issuing the request at timing t31, and then issues the request again at timing t32. As shown in FIG. 8, since the issuance interval between the two requests at this time (the count value of the request no-period counter 21a1) is less than 3, the request group issuance state is maintained.

Furthermore, in the example of FIG. 8, the request generation unit 12a finishes issuing the request at timing t33, and then issues the request again at timing t34. As shown in FIG. 8, since the issuance interval between the two requests at this time is also less than 3, the request group issuance state is maintained.

Thereafter, the request generation unit 12a finishes issuing requests at timing t35, and does not issue the next request even when the count value of the request no-period counter 21a1 from timing t35 reaches 3. Therefore, the AND circuit 21a6 outputs a refresh group issue end signal at timing t36 when the count value reaches 3. This changes the request group issuing state to the request group non-issuing state.

In this way, the memory control circuit 21 of the memory device 20 of the second embodiment determines the continuity of requests during the request reception period in the memory 11, and if the request issuance interval is less than the predetermined upper limit, Suppresses issuing refreshes. This provides the same effects as the memory device 10 and memory control circuit 12 of the first embodiment.

A comparative example of the memory device 20 as described above will be shown below.
(Comparative example)
FIG. 9 shows a memory device of a comparative example. In FIG. 9, the same elements as those in the memory device 20 shown in FIG. 2 are given the same reference numerals.

In the memory control circuit 31 of the memory device 30, the refresh storage section 31b suppresses or allows output of the refresh generation signal depending on the storage state of the request by the request storage section 31a.

FIG. 10 is a timing chart showing an example of temporal changes in signals of each part of the memory control circuit of the memory device of the comparative example.
FIG. 10 shows temporal changes in the request issuing state signal output by the request generation unit 12a, the request storage state in the request storage unit 31a, and the time change in the request output state of the request storage unit 31a. Further, FIG. 10 shows the time change of the request issuance prohibited state, the refresh occurrence signal which is the output signal of the refresh storage section 31b, and the signal further outputted by the refresh storage section 31b indicating whether or not to suppress the issuance of a request. It is shown.

In the example of FIG. 10, a request is issued by the request generation unit 12a at timing t40.
In the memory control circuit 31 of the comparative example, when the request storage section 31a stores a request (timing t41), a refresh suppression instruction is issued from the request storage section 31a to the refresh storage section 31b. Therefore, in the refresh storage section 31b, the refresh issue is prohibited (timing t42), and no refresh is issued.

Furthermore, when the request storage section 31a becomes empty (timing t43), a refresh issue instruction is issued from the request storage section 31a to the refresh storage section 31b. Therefore, in the refresh storage section 31b, the refresh issue prohibition state is canceled (timing t44), the logic level of the refresh generation signal rises from the L level to the H level (timing t45), and a refresh is issued.

In this case, the request storage unit 31a cannot output the request until the timing t46 when the logic level of the signal indicating whether or not to suppress the issuance of the request falls from the H level to the L level, even if requests are issued continuously. .

For this reason, the request interval becomes excessively long, causing a delay in read and write operations, which may deteriorate the performance of the memory device 30.
In contrast, in the memory control circuit 21 of the memory device 20 according to the second embodiment, the request continuity determination unit 21a notifies the refresh storage unit 21c of the start and end of a continuous group of requests. As a result, even if the request storage section 12b becomes empty, the request continuity determination section 21a determines that a continuous group of requests is being transferred, and causes the refresh storage section 21c to suppress issuing a refresh request. Priority can be given to the issuance of

Although one aspect of the memory control circuit and memory device of the present invention has been described above based on the embodiments, these are merely examples, and the present invention is not limited to the above description.

10 Memory device 11 Memory 12 Memory control circuit 12a Request generation unit 12b Request storage unit 12c Request continuity determination unit 12d Refresh generation unit 12d1 Refresh issue suppression unit 12e Selection unit

Claims (5)

a request generation unit that generates a read or write request for the memory to be refreshed and outputs the request;
a request continuity determination unit that determines that a continuous group of requests is being issued if a first issuance interval of the requests is less than a first threshold during a request acceptance period in the memory;
If the second issuance interval of the refresh is less than the second threshold, the issuance of the refresh is suppressed while it is determined that the request group is in the issuance state, and the second issuance interval is less than the second threshold. a refresh issuance inhibiting unit that allows the issuance of the refresh when the threshold of No. 2 is reached;
A memory control circuit having: The request continuity determination unit outputs a first signal indicating the end of issuance of the request group after the first threshold period has elapsed when the request generation unit has finished outputting the requests;
The refresh issue inhibiting unit allows the refresh to be issued when the first signal is output.
The memory control circuit according to claim 1. The request continuity determination unit outputs a second signal indicating the start of issuance of the request group when the request generation unit starts outputting the requests,
The refresh issue suppression unit starts suppressing the refresh issue when the second signal is output.
The memory control circuit according to claim 2. The request continuity determination unit includes a counter that counts the first issuance interval,
The counter stops counting operation during a period other than the period from when the second signal is output to when the first signal is output.
The memory control circuit according to claim 3. memory to be refreshed,
a request generation unit that generates a read or write request for the memory and outputs the request; and a request generating unit that generates a read or write request for the memory and outputs the request, and if a first issuance interval of the request is less than a first threshold value during a request reception period in the memory, the request is issued continuously. a request continuity determination unit that determines that the request group is in the issuance state; and when the second refresh interval is less than a second threshold, the request continuity determination unit determines that the request group is in the issuance state; a memory control circuit comprising: a refresh issue inhibiting unit that suppresses issuance of the refresh and allows issuance of the refresh when the second issue interval reaches the second threshold;
A memory device having:

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