JP2021185462A - Memory control circuit and memory device - Google Patents

Abstract

To reduce a waiting time of a request.SOLUTION: A memory control circuit determines that a continuous batch of request groups is in an issue state, when a first issue interval of a request is less than a first threshold value, during a request reception period in a memory; suppresses issue of refreshment, while determining that the request groups are in the issue state, when a second issue interval of the request is less than a second threshold value; and permits the issue of the refreshment, when the second issue interval reaches the second threshold value.SELECTED DRAWING: Figure 7

Description

The present invention relates to a memory control circuit and a memory device.

A memory control circuit that controls a volatile memory (hereinafter simply referred to as a memory) such as a DRAM (Dynamic Random Access Memory) periodically generates a refresh during a read or write request reception period for the memory.

For memory that needs to be refreshed, the refresh must occur within a specified period according to the specifications. Therefore, when the request and the refresh conflict with each other, the memory control circuit may control the request to wait and give priority to the refresh.

Conventionally, in order to suppress the delay of read and write operations due to the refresh process forcibly executed by an interrupt, there has been a technique of executing the refresh process during an idle period when the burst read or burst write process is not executed (for example, a patent). See Document 1).

Japanese Unexamined Patent Publication No. 2009-157549

By the way, the request issuance interval is not constant, and even if the issuance interval is short, if refresh is generated during the period when the request is not issued, the request waiting time may become long.

In one aspect, it is an object of the present invention to provide a memory control circuit and a memory device capable of reducing the waiting time of a request.

In one embodiment, a request generator that generates a read or write request for the memory to be refreshed and outputs the request, and a first issuance interval of the request during the request acceptance period in the memory are third. If it is less than the threshold value of 1, the request continuity determination unit that determines that the request group is in the issuing state of a continuous group, and if the second issuance interval of the refresh is less than the second threshold value, the request group is issued. While it is determined to be in the state, the refresh issuance suppressing unit suppresses the issuance of the refresh, and when the second issuance interval reaches the second threshold value, the refresh issuance suppressing unit allows the issuance of the refresh. A memory control circuit having is provided.

Also, in one embodiment, a memory device is provided.

In one aspect, the invention can reduce the waiting time for a request.

It is a figure which shows an example of the memory apparatus and the memory control circuit of 1st Embodiment. It is a figure which shows an example of the memory apparatus of 2nd Embodiment. It is a figure which shows an example of the refresh storage part. It is a figure which shows an example of the request continuity determination part. It is a flowchart which shows the flow of an example of the operation of a memory control circuit. It is a state transition diagram of a memory control circuit. It is a timing chart which shows an example of the time change of the signal of each part of a memory control circuit. It is a timing chart which shows an example of the time change of the signal of each part in a request continuity determination part. It is a memory device of a comparative example. It is a timing chart which shows an example of the time change of the signal of each part of the memory control circuit of the memory device of the comparative example.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First Embodiment)
FIG. 1 is a diagram showing an example of a memory device and a memory control circuit according to the first embodiment.

The memory device 10 includes a memory 11 and a memory control circuit 12.
The memory 11 is a memory such as a DRAM or HBM (High Bandwidth Memory) that is refreshed to hold data.

The memory control circuit 12 includes a request generation unit 12a, a request storage unit 12b, a request continuity determination unit 12c, a refresh generation unit 12d, and a selection unit 12e.
The request generation unit 12a generates a read or write request to the memory 11 based on a signal input from the outside of the memory device 10 (for example, a read instruction or a write instruction specifying a certain address), and makes a request. Output (issue). Further, the request generation unit 12a outputs a signal indicating whether or not the request is in the issuance state (hereinafter, referred to as a request issuance state signal).

The request storage unit 12b has, for example, a register and temporarily stores the request issued by the request generation unit 12a. This is because there is a period during which the memory 11 cannot receive a request due to the specifications of the memory 11. Further, the request storage unit 12b performs clock switching when the request generation unit 12a and the selection unit 12e are circuits having different clock domains.

The request continuity determination unit 12c detects the request issuance interval based on the request issuance status signal during the request acceptance period in the memory 11, and when the request issuance interval is less than the first threshold value, a continuous group of requests. It is determined that the group is in the issuing state. When the data size of write data or read data is large, a group of requests that are continuous to some extent is often formed (although there may be a slight gap in the middle). The request continuity determination unit 12c can determine whether or not such a request group is in the issuance state by comparing the request issuance interval with the first threshold value.

Further, when the issuance of the request is completed, the request continuity determination unit 12c outputs a signal indicating the end of the issuance of the request group after the elapse of the period of the first threshold value. Furthermore, the request continuity determination unit 12c may switch clocks when the request generation unit 12a and the refresh generation unit 12d are circuits of different clock domains. A circuit example of the request continuity determination unit 12c will be described later.

The first threshold is set as appropriate, for example, depending on how much priority the request has over refreshing. The larger the first threshold value, the easier it is that a plurality of requests are determined to be a continuous group of requests even if the issuance interval is wide, and the refresh issuance is more likely to be suppressed by the function of the refresh issuance suppression unit 12d1 described later. Therefore, the priority of the request is increased.

The refresh generation unit 12d periodically issues a signal for generating a refresh during a period in which the refresh issuance is not suppressed by the function of the refresh issuance suppression unit 12d1, which will be described later. The refresh issuance interval (issue interval of the signal that causes refreshment) does not have to be constant, and can be adjusted within a range that satisfies the specifications of the memory 11.

The selection unit 12e selects either the output of the request storage unit 12b or the output of the refresh generation unit 12d and supplies it to the memory 11. When the refresh bus and the request bus are common in the memory 11, such a selection unit 12e is used.

In the example of FIG. 1, the refresh generation unit 12d has a refresh issuance suppression unit 12d1.
When the refresh issuance interval (the period during which the refresh is not issued) is less than the second threshold value, the refresh issuance suppression unit 12d1 performs refresh while it is determined that a group of consecutive requests is being issued. Suppress issuance. Further, the refresh issuance suppressing unit 12d1 allows the issuance of refreshes when the refresh issuance interval reaches the second threshold value.

The second threshold value is, for example, an upper limit value of the refresh issuance interval set according to the specifications of the memory 11. Further, in the present specification, "suppression" means an operation in which a refresh is not issued for a certain period of time, and a refresh that should have been issued during that period is issued with a delay after that period. It does not mean that the issue itself of is extinguished. This is because the refresh process in the memory 11 is performed a predetermined number of times within a predetermined total refresh period according to the specifications.

The memory control circuit 12 may have a refresh storage unit that temporarily stores the refresh issued by the refresh generation unit 12d and adjusts the refresh issuance interval for the memory 11. In that case, the refresh issuance suppressing unit 12d1 may be included in the refresh storage unit.

FIG. 1 shows an operation example of an example of the memory control circuit 12.
When the request generation unit 12a issues a request, the logic level of the request issuance status signal rises from the L (Low) level to the H (High) level (timing t1). In response to this change, the request continuity determination unit 12c outputs a pulse signal having a logic level of H level (hereinafter, referred to as a request group issuance start signal) indicating the start of issuance of a continuous group of requests. As a result, the refresh issuance suppression unit 12d1 starts suppressing the issuance of refresh.

In the example of FIG. 1, the request generation unit 12a finishes issuing the request at the timing t2, and then issues the request again at the timing t3. As shown in FIG. 1, when T (= t3-t2), which is the issuance interval between the two requests at this time, is less than Tth1, which is the first threshold value described above, the request continuity determination unit 12c is continuous. It is determined that a group of requests is being issued. In this case, the request continuity determination unit 12c does not output a pulse signal having an H level logic level indicating the end of issuance of a continuous group of requests (hereinafter referred to as a request group issuance end signal). Therefore, the refresh issuance suppression unit 12d1 continues to suppress the issuance of refreshes.

In the example of FIG. 1, the request generation unit 12a finishes issuing a request at timing t4, and does not issue the next request even after the period from timing t4 to Tth1 has elapsed. Therefore, the request continuity determination unit 12c outputs a refresh group issuance end signal after the period of Tth1 has elapsed (timing t5). As a result, the refresh issuance suppression unit 12d1 allows the issuance of refreshes.

As described above, the memory control circuit 12 of the memory device 10 of the first embodiment determines the continuity of requests during the request acceptance period in the memory 11, and when the request issuance interval is less than the first threshold value, Suppress the issuance of refreshes. As a result, even when the request issuance interval is short, the refresh is suppressed from being issued between requests, so that the waiting for the request is suppressed. Therefore, the waiting time of the request can be reduced. Further, since the request waiting time can be reduced, the delay of read and write operations can be reduced, and the performance (request processing speed) of the memory device 10 can be improved.

(Second embodiment)
FIG. 2 is a diagram showing an example of a memory device according to a second embodiment. In FIG. 2, the same elements as those shown in FIG. 1 are designated by the same reference numerals.

The memory control circuit 21 in the memory device 20 of the second embodiment temporarily stores a signal for generating a refresh issued periodically by the refresh generation unit 21b, and adjusts the refresh issuance interval to the memory 11. It has a refresh storage unit 21c.

FIG. 3 is a diagram showing an example of a refresh storage unit.
The refresh storage unit 21c includes a refresh issuance interval counter 21c1, an upper limit setting register 21c2, a comparator 21c3, an OR circuit 21c4, a refresh issuance suppression unit 21c5, and an issuance interval adjustment circuit 21c6.

The refresh issuance interval counter 21c1 is a counter that counts the refresh issuance interval (the period during which no refresh is issued). The refresh issuance interval counter 21c1 counts up the count value in synchronization with, for example, a clock signal (not shown) until the issuance interval adjustment circuit 21c6 outputs a signal that causes a refresh. When the issue interval adjustment circuit 21c6 outputs a signal to generate a refresh, the refresh issue interval counter 21c1 resets the count value.

The upper limit setting register 21c2 is a register in which the upper limit value of the refresh issuance interval is set. The upper limit of the refresh issuance interval is set, for example, according to the specifications of the memory 11 at the time of initial setting of the memory device 20.

The comparator 21c3 outputs a comparison result between the count value counted by the refresh issuance interval counter 21c1 and the upper limit value. In the following example, the comparator 21c3 outputs a signal whose logic level is L level until the count value reaches the upper limit value, and outputs a signal whose logic level is H level when the count value reaches the upper limit value. However, it is not limited to this.

The output signal of the comparator 21c3 is supplied to the OR circuit 21c4 and the request continuity determination unit 21a. When the logic level of the output signal of the comparator 21c3 is H level, the request continuity determination unit 21a is instructed to forcibly terminate the issuance of a continuous group of requests.

The OR circuit 21c4 indicates whether or not the output signal of the comparator 21c3 and the signal indicating whether or not to issue the refresh output by the request continuity determination unit 21a (whether or not the issuance of a continuous group of requests has been completed). The logical sum (OR) with the signal) is output. When the logic level is H level, the output signal of the OR circuit 21c4 corresponds to the above-mentioned request group issuance end signal and indicates the issuance of refresh, but is not limited thereto.

The refresh issuance suppression unit 21c5 has an output signal of the OR circuit 21c4 and a signal instructing whether to suppress the issuance of the refresh output by the request continuity determination unit 21a (whether the issuance of a continuous group of requests has started? (Signal indicating whether or not) is received. Then, the refresh issuance suppressing unit 21c5 suppresses the issuance of refresh when the logic level of the output signal of the OR circuit 21c4 is L level or when a signal instructing to suppress the issuance of refresh is received. In the following example, the signal instructing whether or not to suppress the issuance of refresh corresponds to the above-mentioned request group issuance start signal when the logic level is H level, and indicates to suppress the issuance of refresh. However, it is not limited to this.

The refresh issuance suppressing unit 21c5 is, for example, a reset-priority flip-flop having a set terminal and a reset terminal and holding a logical value “1” or a logical value “0”. In this case, a signal instructing whether or not to suppress the issuance of refresh is input to the set terminal, and the output signal of the OR circuit 21c4 is input to the reset terminal. When the logical level of the signal instructing whether to suppress the issuance of refresh becomes H level, "1" is set in the refresh issuance suppressing unit 21c5, and the logical level for suppressing the issuance of refresh is the H level signal. Is output. Hereinafter, the state in which "1" is set in the refresh issuance suppression unit 21c5 is referred to as a refresh issuance prohibition state.

Further, when the refresh issuance interval reaches the upper limit value or a signal instructing the refresh issuance is supplied, the logic level of the output signal of the OR circuit 21c4 becomes H level. At this time, the refresh issuance suppression unit 21c5 is reset to "0", and the refresh issuance suppression unit 21c5 outputs a signal whose logic level is L level.

The issuance interval adjusting circuit 21c6 has, for example, a register, temporarily stores a signal for generating a refresh issued by the refresh generation unit 21b, and adjusts the issuance interval of the refresh to the memory 11. Further, the issuance interval adjusting circuit 21c6 does not output a signal for generating a refresh while the refresh issuance suppression unit 21c5 is instructed to suppress the issuance of refresh.

FIG. 4 is a diagram showing an example of a request continuity determination unit.
The request continuity determination unit 21a includes a request indefinite period counter 21a1, an upper limit setting register 21a2, a comparator 21a3, an OR circuit 21a4, 21a9, an AND circuit 21a5, 21a6, 21a7, 21a8, and a request group issuance state determination unit 21a10.

The request indefinite period counter 21a1 is a reset priority counter, and counts a period (request interval) in which a request is not issued when a continuous group of requests is issued. When the logic level of the output signal of the OR circuit 21a9 is L level and the logic level of the output signal of the AND circuit 21a7 is H level, the request indefinite period counter 21a1 calculates the count value in synchronization with a clock signal (not shown), for example. Count up. Further, the request indefinite period counter 21a1 resets the counting value when the output signal of the OR circuit 21a9 is at the H level, and does not perform the counting operation while the output signal of the OR circuit 21a9 is at the H level.

The upper limit setting register 21a2 holds an upper limit value of the request interval for determining a continuous group of requests. The upper limit of the request interval is set, for example, at the time of initial setting of the memory device 20.

The comparator 21a3 outputs a comparison result between the count value counted by the request indefinite period counter 21a1 and the upper limit value. In the following example, the request indefinite period counter 21a1 outputs a signal whose logic level is L level until the count value reaches the upper limit value, and when the count value reaches the upper limit value, a signal whose logic level is H level. Is output, but is not limited to this.

The OR circuit 21a4 outputs a logical sum (OR) of the output signal of the comparator 21a3 and the output signal of the comparator 21c3 of the refresh storage unit 21c shown in FIG.
The AND circuit 21a5 outputs a logical product (AND) of a request issuance state signal output by the request generation unit 12a and a signal obtained by inverting the logic level of the output signal of the request group issuance state determination unit 21a10. In the following example, the request issuance status signal indicates, but is not limited to, the request issuance status when the logic level is H level. Further, in the following example, the output signal of the request group issuance state determination unit 21a10 indicates that when the logic level is H level, it is the issuance state of a continuous group of requests, but the present invention is limited to this. It's not something. The output signal of the AND circuit 21a5 is a signal instructing whether or not to suppress the issuance of the above-mentioned refresh, and is supplied to the request group issuance state determination unit 21a10 and the refresh storage unit 21c.

The AND circuit 21a6 outputs the logical product of the output signal of the OR circuit 21a4 and the output signal of the request group issuance state determination unit 21a10. The output signal of the AND circuit 21a6 is a signal instructing whether or not to issue the above-mentioned refresh, and is supplied to the request group issuance state determination unit 21a10 and the refresh storage unit 21c.

The AND circuit 21a7 outputs the logical product of the signal obtained by inverting the logical level of the request issuance state signal output by the request generation unit 12a and the output signal of the request group issuance state determination unit 21a10.

The AND circuit 21a8 outputs the logical product of the request issuance status signal output by the request generation unit 12a and the output signal of the request group issuance status determination unit 21a10.
The OR circuit 21a9 outputs the logical sum of the output signal of the AND circuit 21a6 and the output signal of the AND circuit 21a8.

The request group issuance state determination unit 21a10 outputs a signal indicating whether or not a continuous group of request groups is in the issuance state, based on the output signals of the AND circuit 21a5 and the AND circuit 21a6.

The request group issuance state determination unit 21a10 is, for example, a flip-flop having a set terminal and a reset terminal and holding a logical value “1” or a logical value “0”. In this case, the output signal of the AND circuit 21a5 is input to the set terminal, and the output signal of the AND circuit 21a6 is input to the reset terminal. Then, when the logic level of the output signal of the request group issuance state determination unit 21a10 is L level, when the request is issued, the logic level of the output signal of the AND circuit 21a5 becomes H level. At this time, "1" is set in the request group issuance state determination unit 21a10, and a signal having a logic level of H level indicating that the request group is in the issuance state of a continuous group is output. Hereinafter, the state in which "1" is set in the request group issuance state determination unit 21a10 is referred to as a request group issuance state.

Further, in the request group issuance state, when the request interval reaches the upper limit value or the refresh issuance interval reaches the upper limit value, the logical level of the output signal of the AND circuit 21a6 becomes the H level. At this time, the request group issuance status determination unit 21a10 is reset to "0", and the request group issuance status determination unit 21a10 has a logic level L indicating that the request group is not in the request group issuance state (hereinafter referred to as the request group non-issued state). Output a level signal.

The request continuity determination unit 12c of the memory control circuit 12 of the first embodiment shown in FIG. 1 can also be realized by the circuit as shown in FIG. In that case, the output signals of the AND circuits 21a5 and 21a6 of FIG. 4 are supplied to the refresh generation unit 12d of FIG. Further, the refresh generation unit 12d has a refresh issuance interval counter 21c1, an upper limit setting register 21c2, a comparator 21c3, and an OR circuit 21c4 as shown in FIG. 3, and the output signal of the comparator 21c3 is a continuous request. It will be supplied to the sex determination unit 12c.

Hereinafter, it is a figure which shows the operation example of the memory control circuit 21 of the 2nd Embodiment.
FIG. 5 is a flowchart showing a flow of an example of the operation of the memory control circuit.
When the request generation unit 12a issues a request (step S1), the request continuity determination unit 21a sets the request group issuance state, and the refresh storage unit 21c sets the refresh issuance prohibition state (step S2).

When the refresh issuance interval has not reached the upper limit value (step S3: NO) and the request interval has not reached the upper limit value (step S4: NO), the request group issuance state and the refresh issuance prohibition state are maintained. To.

When the refresh issuance interval reaches the upper limit (step S3: YES) or the request interval reaches the upper limit (step S4: YES), the request group issuance state and the refresh issuance prohibition state are canceled (step). S5). As a result, a refresh is issued (step S6). This completes the process from the issuance of the request to the next issuance of the refresh.

FIG. 6 is a state transition diagram of the memory control circuit.
FIG. 6 shows an example of a state transition between four states: a request group issuance state, a request group non-issuance state, a refresh issuance prohibition state, and a refresh issuance allowance state.

When a request is issued in the request group non-issued state, a state transition occurs from the request group non-issued state to the request group issued state. Further, the request continuity determination unit 21a gives an instruction (refresh suppression instruction) to suppress the refresh issuance to the refresh storage unit 21c, and a state transition from the refresh issuance allowable state to the refresh issuance prohibition state occurs.

When the request interval reaches the upper limit in the request group issuance state, a state transition occurs from the request group issuance state to the request group non-issuance state. Further, the request continuity determination unit 21a gives an instruction to issue a refresh (a refresh issuance instruction) to the refresh storage unit 21c, and a state transition from the refresh issuance prohibition state to the refresh issuance allowable state occurs.

Further, in the refresh issuance prohibited state, when the refresh issuance interval reaches the upper limit value, a state transition occurs from the refresh issuance prohibited state to the refresh issuance permitted state. Further, the refresh storage unit 21c gives an instruction to forcibly terminate the request group issuance to the request continuity determination unit 21a, and a state transition from the request group issuance state to the request group non-issuance state occurs.

Next, the time change of the signal of each part of the memory control circuit 21 will be described using a timing chart.
FIG. 7 is a timing chart showing an example of the time change of the signal of each part of the memory control circuit.

FIG. 7 shows the time change of the request issuance status signal, the request group issuance start signal, and the request group issuance end signal output by the request generation unit 12a. Further, FIG. 7 shows the time change of the request storage state of the request storage unit 12b and the request output state of the request storage unit 12b. The storage state of the request indicates a state in which the request is stored when the logical level is H level, and indicates a state in which the request is not stored (empty state) when the logical level is L level. The request output state indicates a state in which the request storage unit 12b is outputting a request when the logic level is H level, and a state in which the request storage unit 12b is not outputting a request when the logic level is L level. show. Even if the requests issued by the request generation unit 12a are continuous, if the reading from the request storage unit 12b is fast, the request storage unit 12b is temporarily emptied. FIG. 7 shows an example.

Further, FIG. 7 shows time changes of the output signal of the refresh issuance suppressing unit 21c5 and the output signal of the refresh storage unit 21c (the signal supplied to the selection unit 12e (shown as “refresh generation signal”)). Has been done. Further, although not shown in FIG. 3, FIG. 7 shows, for example, a time change of a signal further output by the refresh storage unit 21c, which indicates whether or not to suppress the issuance of a request. The signal indicating whether to suppress the issuance of the request is a signal whose logic level becomes H level for a predetermined period (period during which refresh is executed) from the timing when the logic level of the refresh generation signal falls from H level to L level. Is. A signal indicating whether or not to suppress the issuance of the request is supplied to the request storage unit 12b.

In the example of FIG. 7, at the timing t10, the logic level of the refresh generation signal rises from the L level to the H level, and then at the timing t11, the logic level of the refresh generation signal falls from the H level to the L level. At this time, the logic level of the signal indicating whether or not to suppress the issuance of the request rises from the L level to the H level.

When a request is issued by the request generation unit 12a at the timing t12, a request group issuance start signal is output. As a result, the request continuity determination unit 21a issues the above-mentioned refresh suppression instruction to the refresh storage unit 21c, and at the timing t14, the logical level of the output signal of the refresh issuance suppression unit 21c5 rises from the L level to the H level.

At the timing t13, the request storage unit 12b is in a state of storing the request, but does not output the request until the logical level of the signal indicating whether to suppress the issuance of the request drops from the H level to the L level. At the timing t14, the logic level of the signal indicating whether or not to suppress the issuance of the request is lowered from the H level to the L level. As a result, the request storage unit 12b outputs the request.

While the logic level of the output signal of the refresh issuance suppression unit 21c5 is H level, the refresh issuance prohibition state is set. Therefore, at the timings t15 and t17, the refresh generation signal whose logic level should have risen from the L level to the H level does not change, and no refresh is issued. The refresh that was not issued will be issued with a delay after the logical level of the output signal of the refresh issuance suppression unit 21c5 drops to the L level.

When the issuance of the request is completed (timing t16) and the request interval reaches the upper limit, the request group issuance end signal is output (timing t18). As a result, the request continuity determination unit 21a issues a refresh issuance instruction to the refresh storage unit 21c, and at the timing t19, the logical level of the output signal of the refresh issuance suppression unit 21c5 drops from the H level to the L level.

Therefore, at the timing t20, the logic level of the refresh generation signal rises from the L level to the H level, and for example, the refresh that should have been issued at the timing t15 is issued.

FIG. 8 is a timing chart showing an example of the time change of the signal of each unit in the request continuity determination unit.
FIG. 8 shows a request issuance state signal supplied from the request generation unit 12a to the request continuity determination unit 21a, and a time change of the issuance state of the request group determined by the request group issuance state determination unit 21a10. Further, the time change of the count value of the request indefinite period counter 21a1, the value set in the upper limit setting register 21a2 (the upper limit value of the request interval), and the time change of the request group issuance start signal and the request group issuance end signal are shown. ..

In the example of FIG. 8, the request indefinite period counter 21a1 is used in a period other than the period from the output of the request group issuance start signal to the output of the request group issuance end signal (the period in which the request group is not issued). Is not counting up (counting operation). The request indefinite period counter 21a1 may count up even in the request group non-issued state, but since the count value in the request group non-issued state is not used, the count-up is performed as shown in FIG. 8 in order to reduce power consumption. It is desirable not to do. Further, in the example of FIG. 8, 3 is set as the upper limit value in the upper limit setting register 21a2.

When the request generation unit 12a issues a request (timing t30) in the request group non-issuance state, the AND circuit 21a5 of the request continuity determination unit 21a outputs a refresh group issuance start signal. As a result, the request group is issued.

In the example of FIG. 8, the request generation unit 12a finishes issuing the request at the timing t31, and then issues the request again at the timing t32. As shown in FIG. 8, since the issuance interval of the two requests at this time (count value of the request indefinite period counter 21a1) is less than 3, the request group issuance state is maintained.

Further, in the example of FIG. 8, the request generation unit 12a finishes issuing the request at the timing t33, and then issues the request again at the timing t34. As shown in FIG. 8, since the issuance interval between the two requests at this time is also less than 3, the request group issuance state is maintained.

After that, the request generation unit 12a finishes issuing the request at the timing t35, and does not issue the next request even if the count value of the request indefinite period counter 21a1 from the timing t35 reaches 3. Therefore, the AND circuit 21a6 outputs a refresh group issuance end signal at the timing t36 when the count value reaches 3. As a result, the request group issuance state changes to the request group non-issued state.

As described above, the memory control circuit 21 of the memory device 20 of the second embodiment determines the continuity of requests during the request acceptance period in the memory 11, and when the request issuance interval is less than a predetermined upper limit value, Suppress the issuance of refreshes. As a result, the same effect as that of the memory device 10 and the memory control circuit 12 of the first embodiment can be obtained.

Hereinafter, a comparative example with respect to the memory device 20 as described above will be shown.
(Comparative example)
FIG. 9 is a memory device of a comparative example. In FIG. 9, the same elements as those of the memory device 20 shown in FIG. 2 are designated by the same reference numerals.

In the memory control circuit 31 of the memory device 30, the refresh storage unit 31b suppresses or allows the output of the refresh generation signal according to the storage state of the request by the request storage unit 31a.

FIG. 10 is a timing chart showing an example of time change of a signal of each part of the memory control circuit of the memory device of the comparative example.
FIG. 10 shows the time change of the request issuance state signal output by the request generation unit 12a, the time change of the request storage state of the request storage unit 31a, and the time change of the request output state of the request storage unit 31a. Further, in FIG. 10, the request issuance prohibited state, the refresh generation signal which is the output signal of the refresh storage unit 31b, and the time change of the signal further output by the refresh storage unit 31b indicating whether or not to suppress the issuance of the request are shown. It is shown.

In the example of FIG. 10, a request is issued by the request generation unit 12a at the timing t40.
In the memory control circuit 31 of the comparative example, when the request storage unit 31a stores the request (timing t41), the request storage unit 31a issues a refresh suppression instruction to the refresh storage unit 31b. Therefore, in the refresh storage unit 31b, the refresh issuance is prohibited (timing t42), and no refresh is issued.

When the request storage unit 31a becomes empty (timing t43), the request storage unit 31a issues a refresh issuance instruction to the refresh storage unit 31b. Therefore, in the refresh storage unit 31b, the refresh issuance prohibition state is released (timing t44), the logical level of the refresh generation signal rises from the L level to the H level (timing t45), and the refresh is issued.

In this case, the request storage unit 31a cannot output the request until the timing t46 when the logical level of the signal indicating whether or not to suppress the issuance of the request drops from the H level to the L level even if the requests are continuously issued. ..

Therefore, the request interval becomes excessively long, delays in read and write operations occur, and the performance of the memory device 30 may deteriorate.
On the other hand, in the memory control circuit 21 of the memory device 20 of the second embodiment, the request continuity determination unit 21a conveys the start and end of a continuous group of requests to the refresh storage unit 21c. As a result, even if the request storage unit 12b becomes empty, the request continuity determination unit 21a determines that a continuous group of requests is being transferred, and causes the refresh storage unit 21c to suppress the issuance of a refresh request. Issuance can be prioritized.

Although one viewpoint of the memory control circuit and the memory device of the present invention has been described above based on the embodiment, these are merely examples and are not limited to the above description.

10 Memory device 11 Memory 12 Memory control circuit 12a Request generation unit 12b Request storage unit 12c Request continuity judgment unit 12d Refresh generation unit 12d1 Refresh issuance suppression unit 12e Selection unit

Claims (5)

A request generator that generates a read or write request for the memory to be refreshed and outputs the request,
When the first issuance interval of the request is less than the first threshold value during the request acceptance period in the memory, the request continuity determination unit for determining that the request is in the issuance state of a continuous group of requests, and the request continuity determination unit.
When the second issuance interval of the refresh is less than the second threshold value, the issuance of the refresh is suppressed while it is determined that the request group is in the issuance state, and the second issuance interval is the second issuance interval. When the threshold value of 2 is reached, the refresh issuance suppression unit that allows the issuance of the refresh is
Memory control circuit with. When the request generation unit ends the output of the request, the request continuity determination unit outputs a first signal indicating the end of issuance of the request group after the elapse of the period of the first threshold value.
The refresh issuance suppressing unit allows the issuance of the refresh when the first signal is output.
The memory control circuit according to claim 1. When the request generation unit starts outputting the request, the request continuity determination unit outputs a second signal indicating the start of issuance of the request group.
When the second signal is output, the refresh issuance suppressing unit starts suppressing the issuance of the refresh.
The memory control circuit according to claim 2. The request continuity determination unit has a counter for counting the first issuance interval.
The counter stops the counting operation for a period other than the period from the output of the second signal to the output of the first signal.
The memory control circuit according to claim 3. The memory to be refreshed and
A request generator that generates a read or write request for the memory and outputs the request, and a request generation unit that outputs the request are continuous when the first issuance interval of the request is less than the first threshold value during the request acceptance period in the memory. While the request continuity determination unit that determines that the request group is in the issuing state of a group and the request continuity determination unit that determines that the request group is in the issuing state when the second issuance interval of the refresh is less than the second threshold value. Is a memory control circuit including a refresh issuance suppressing unit that suppresses the issuance of the refresh and allows the issuance of the refresh when the second issuance interval reaches the second threshold value.
Memory device with.

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