CN117894353A - Virtual static random access memory - Google Patents
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- CN117894353A CN117894353A CN202211228985.4A CN202211228985A CN117894353A CN 117894353 A CN117894353 A CN 117894353A CN 202211228985 A CN202211228985 A CN 202211228985A CN 117894353 A CN117894353 A CN 117894353A
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- G—PHYSICS
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
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Abstract
A pseudo static random access memory includes a control unit 10 for controlling, when a refresh request is generated for the memory during operation 1, the number of refresh requests generated during operation 1 to be executed only during a period from the end of operation 1 to the start of operation 2.
Description
Technical Field
The present invention relates to a pseudo-static random access memory (pSRAM).
Background
pSRAM is a semiconductor memory device that includes an interface that is compatible with static random access memory (Static Random Access Memory, SRAM). Referring to fig. 1, an example of the update operation in the conventional pSRAM will be described. In the example of fig. 1, the read or write operation starts when the wafer select signal cs# transitions from a high level to a low level. Then, since the access signal RD/WR for performing data access to the memory cell array is changed from the low level to the high level, read or write access of data to the memory cell array is performed. After that, the read or write operation ends when the wafer select signal cs# transitions from a low level to a high level. Then, since the access signal RD/WR transitions from the high level to the low level, the read or write access to the data of the memory cell array ends.
In addition, in the interior of the pSRAM, an update request signal Ref request for requesting an update operation is generated at a predetermined interval tREFI. Here, when the refresh request signal Ref request is generated (set to high level) during the period in which the wafer selection signal cs# is set to high level, the pSRAM is configured to perform the refresh operation by immediately setting the refresh signal Ref for performing the refresh operation to high level. On the other hand, when the refresh request signal Ref request is generated (set to high level) during the period when the wafer select signal cs# is set to low level (during read or write access), the execution of the refresh operation is ready since the pSRAM is performing the read or write access. Then, when the wafer select signal CS# is set to a high level and the access signal RD/WR transitions from a high level to a low level, the pSRAM performs a refresh operation.
In the pSRAM, if the period tCSL during which the wafer select signal cs# is set to low is longer than the generation interval tREFI of the refresh request signal Ref request (i.e., tCSL > tREFI), the refresh request is ignored, and the refresh operation may not be performed. For example, in the example of fig. 1, although 2 update request signals Ref request are generated in the period tCSL in which the wafer selection signal cs# is set to the low level, the update operation is performed only 1 time and the update request of the 2 nd time is disregarded in the period in which the wafer selection signal cs# is set to the high level. Thus, there may be a case where it is difficult to hold data since 1 or more update requests generated in the operation are not responded to and the update operation is performed.
On the other hand, at tCSL < tREFI, although the update request may be suppressed from being disregarded. However, at this time, since the period tCSL during which the wafer select signal cs# is set to the low level becomes short, the amount of data that can be transferred and received in 1 operation decreases. Therefore, the data transmission rate may be lowered.
Disclosure of Invention
In order to solve the above problems, the present invention provides a pseudo static random access memory comprising: and a control unit configured to control, when an update request of the memory is generated during the 1 st operation, the number of update requests generated during the 1 st operation to be executed by the memory during a period from the end of the 1 st operation to the start of the 2 nd operation after the 1 st operation.
According to the present invention, the number of update requests generated during the 1 st operation is counted during the period from the end of the 1 st operation to the start of the 2 nd operation after the 1 st operation. Thus, even when, for example, the period during which the wafer selection signal is set to the low level is longer than the generation interval of the update request signal, it is possible to respond to 1 or more update requests generated in the 1 st operation period to surely perform the update operation. Further, the data retention characteristics can be maintained while suppressing a decrease in the data transmission rate.
Drawings
Fig. 1 is a waveform diagram showing signals in a conventional pSRAM.
FIG. 2 is a block diagram showing a constitution example of a pSRAM according to embodiment 1 of the present invention.
Fig. 3 is a waveform diagram showing signals in the pSRAM of embodiment 1.
FIG. 4 is a block diagram showing a constitution example of pSRAM according to embodiment 2 of the present invention.
Fig. 5 is a waveform diagram showing signals in pSRAM of embodiment 2.
Reference numerals and signs
10 pseudo static random access memory (pSRAM)
11 Oscillator
12 control part
12a counter
12b counter
12c comparator
12d reverser
12e AND gate
13 arbiter
14 instruction generating part
Cmp_ref signal
Cnt_req signal
Cnt_exe signal
CS#: signal
RD/WR access signal
REF update signal
Ref request update request signal
Detailed Description
Fig. 2 is a block diagram showing an exemplary configuration of a pSRAM (pseudo static random access memory) 10 according to embodiment 1 of the present invention. The pSRAM 10 is configured such that, when the refresh request signal ref_request of the memory is generated during the 1 st operation, the refresh operation of the memory is performed only by the number of refresh request signals ref_request generated during the 1 st operation in a period from the end of the 1 st operation to the start of the 2 nd operation. In addition, the pSRAM according to the present embodiment may be a clock synchronous type pseudo-static random access memory in which signals are input or output in synchronization with clock signals. Furthermore, the pSRAM according to the present embodiment may be an address data multiplexing interface type pseudo-static random access memory having address data terminals configured to input address signals and data signals, respectively.
Referring to fig. 2, the psram 10 includes an oscillator 11, a control section 12, an arbiter 13, and a command generation section 14.
The oscillator 11 generates an update request signal ref_request at each specific interval (for example, the generation interval tREFI shown in fig. 1), and outputs the generated update request signal ref_request to the control unit 12.
The control section 12 includes a counter 12a, a counter 12b, a comparator 12c, an inverter 12d, and an and gate 12e.
The counter 12a is configured to count the number of update request signals ref_requests. Specifically, the counter 12a counts the number of update request signals ref_requests that are input every time an update request signal ref_requests is input from the oscillator 11. Next, the counter 12a outputs a signal cnt_req indicating the number of update request signals ref_request to the comparator 12c.
The value of the signal cnt_req may be reset to an initial value (e.g., 0) at the start of each operation (transition of the wafer selection signal cs# from high to low), for example.
The counter 12b is configured to count the number of update actions performed during a period from the end of the 1 st operation to the start of the 2 nd operation. Specifically, the counter 12b counts the number of update signals REF to be input each time an update signal REF for performing an update operation is input from the instruction generation unit 14. Next, the counter 12b outputs a signal cnt_exe showing the number of the update signals REF to the comparator 12c.
In addition, the value of the signal cnt_exe may be reset to an initial value (e.g., 0) at the end of each operation (transition of the wafer selection signal cs# from low level to high level), for example.
The comparator 12c is configured to compare the number of update request signals ref_request counted by the counter 12a with the number of update signals Ref counted by the counter 12b. Specifically, the comparator 12c compares the value of the signal cnt_req input from the counter 12a with the value of the signal cnt_exe input from the counter 12b. Next, when cnt_req > cnt_exe, the comparator 12c outputs an output signal of high level to the and gate 12e. On the other hand, when cnt_req++cnt_exe, the comparator 12c outputs the output signal of low level to the and gate 12e.
The inverter 12d logically inverts the update signal REF input from the instruction generation unit 14, and outputs the logically inverted signal to the and gate 12e.
The output signal output from the comparator 12c is input to an input terminal of the and gate 12e. In addition, the signal output from the inverter 12d is input to the other input terminal of the and gate 12e. The and gate 12e performs a logical and operation based on the input signal, and outputs a signal cmp_ref indicating the operation result to the arbiter 13. Here, the signal cmp_ref is an example of the "update control signal" of the present invention.
The arbiter 13 arbitrates (mediates) between the chip select signal cs# and the signal cmp_ref, and adjusts the timing of outputting the signal cmp_ref to the command generation unit 14. In addition, in the present embodiment, the arbiter 13 is configured to output the update control signal (signal cmp_ref) to the command generation section 14 every time the update control signal (signal cmp_ref) is input from the control section 12 during a period from the end of the 1 st operation to the start of the 2 nd operation.
Specifically, when the wafer selection signal cs# is at a high level (that is, when the signal cmp_ref at a high level is input from the control unit 12 in a period from the end of the 1 st operation to the start of the 2 nd operation), the arbiter 13 outputs the signal cmp_ref at a high level to the command generation unit 14. In addition, the arbiter 13 does not output the high-level signal cmp_ref to the command generation unit 14 when the high-level signal cmp_ref is input from the control unit 12 during the period in which the wafer selection signal cs# is low (i.e., during operation).
The instruction generation unit 14 generates an update signal REF for performing an update operation based on the control unit 12. The instruction generator 14 outputs the update signal REF to the counter 12b each time the update signal REF is generated. Specifically, when the wafer selection signal cs# is at a high level and the access signal RD/WR for performing data access to the memory cell array is at a low level, and the high-level signal cmp_ref is input from the arbiter 13, the command generating unit 14 generates the high-level update signal REF and outputs the high-level update signal REF to the memory cell array (not shown), the counter 12b of the control unit 12, and the inverter 12d.
In addition, the command generating section 14 generates a high-level access signal RD/WR to output to the memory cell array when a read or write command is externally input during each operation (during a period in which the wafer selection signal cs# is low).
In addition, the refresh operation of the memory is performed when the high-level refresh signal REF is input to the memory cell array, and the data reading or writing process is performed for the memory cell array when the high-level access signal RD/WR is input to the memory cell array.
Next, an update operation in the pSRAM according to the present embodiment is described with reference to fig. 3. Here, a case where the period tCSL in which the wafer select signal cs# is low is longer than the generation interval tREFI of the refresh request signal ref_request will be described as an example.
First, the wafer select signal cs# transitions from a high level to a low level, and when reading or writing is performed from or to an external input after the start of the 1 st operation, the command generating section 14 generates the high-level access signal RD/WR and outputs the high-level access signal RD/WR to the memory cell array.
Here, at time t1, the high-level update request signal ref_request is generated by the oscillator 11, the counter 12a of the control section 12 increases the count value of the update request signal ref_request count from 0 to 1, and outputs a signal cnt_req showing the count value of 1 to the comparator 12c. In addition, the comparator 12c compares the value of the signal cnt_req with the value of the signal cnt_exe (here, assumed to be 0), and outputs a high-level output signal to the and gate 12e because the value of the signal cnt_req is larger than the value of the signal cnt_exe. The and gate 12e performs a logical and operation between the output signal from the comparator 12c and the signal output from the inverter 12d (the signal output from the inverter 12d is high since the update signal REF is initially low), and outputs the high-level signal cmp_ref to the arbiter 13.
Here, since the wafer select signal cs# is low at time t1, the arbiter 13 does not output the received high-level signal cmp_ref to the command generation unit 14. As described above, the command generating section 14 generates the high-level access signal RD/WR and outputs the high-level access signal RD/WR to the memory cell array.
Next, at time t2 after the specific interval tREFI from time t1, when the high-level update request signal ref_request is generated by the oscillator 11, the count value of the counter 12a of the control unit 12 increases from 1 to 2, and the signal cnt_req having the display count value of 2 is output to the comparator 12c. In addition, since the value of the signal cnt_req is larger than the value of the signal cnt_exe, the comparator 12c outputs an output signal of high level to the and gate 12e. Further, the and gate 12e outputs the high-level signal cmp_ref to the arbiter 13 as in the case of time t 1. In addition, at time t2, the operations of the arbiter 13 and the instruction generation unit 14 are the same as in the case of time t 1.
When the wafer select signal cs# transitions from the low level to the high level after time t2, the arbiter 13 outputs the high level signal cmp_ref to the command generation unit 14. On the other hand, when the access signal RD/WR is low at time t3, the command generating unit 14 generates a high-level update signal REF in response to the high-level signal cmp_ref input from the arbiter 13 at time t4, and outputs the high-level update signal REF to the memory cell array, the counter 12b of the control unit 12, and the inverter 12d.
When the high-level update signal REF is input, the counter 12b of the control unit 12 increases the count value from 0 to 1, and outputs a signal cnt_exe indicating a count value of 1 to the comparator 12c. In addition, at time t4, since the value of the signal cnt_req is still larger than the value of the signal cnt_exe, the comparator 12c outputs the output signal of high level to the and gate 12e. The signal cmp_ref output from the and gate 12e transitions to a low level when the high-level update signal REF is output from the command generating unit 14, and transitions to a high level again when the update operation end update signal REF transitions to a low level. At this time, the arbiter 13 outputs the high-level signal cmp_ref to the command generation unit 14.
Next, at a time t5 after the lapse of the period tRFC (refresh interval) from the time t4, the command generating unit 14 generates again the high-level refresh signal REF in response to the high-level signal cmp_ref input from the arbiter 13, and outputs the high-level refresh signal REF to the memory cell array, the counter 12b of the control unit 12, and the inverter 12d. When the high-level update signal REF is input, the counter 12b of the control unit 12 increases the count value from 1 to 2, and outputs a signal cnt_exe indicating the count value of 2 to the comparator 12c. At this time, since the value of the signal cnt_req is equal to the value of the signal cnt_exe, the comparator 12c outputs the output signal of low level to the and gate 12e. At this time, the signal cmp_ref goes low. After that, when the refresh operation end refresh signal REF goes low again, the signal cmp_ref output from the and gate 12e remains low. Up to this point, in response to 2 update request signals ref_request generated in the operation, 2 update actions are performed and then ended.
In the example of fig. 3, the wafer selection signal cs# transitions from the low level to the high level, and then transitions to the low level again after the period tCSH elapses, and the 2 nd operation starts. However, in this example, since the 2 nd operation is still in progress at the start of the 2 nd update operation. Therefore, the instruction generating section 14 can wait until the end of the 2 nd refresh operation (the 2 nd refresh signal REF transitions to the low level) and set the access signal RD/WR to the high level in response to the start of the 2 nd operation.
As described above, according to the pSRAM of the present embodiment, even in a case where, for example, the period tCSL in which the wafer selection signal cs# is low is longer than the generation interval tREFI of the refresh request signal ref_request, it is possible to surely perform the refresh operation in response to each of 1 or more refresh requests generated during the operation. In addition, the data transfer rate can be suppressed from decreasing while maintaining the data retention characteristics.
Embodiment 2 of the present invention is described below. The pSRAM of the present embodiment is different from that of embodiment 1 in that it includes a plurality of banks accessed in an interleaved manner. The following description is of a configuration different from that of embodiment 1.
In the present embodiment, the pSRAM 10 includes a plurality of (for example, n (n is an integer of 2 or more)) banks 20 that are accessed in an interleaved manner, as shown in fig. 4. Each memory bank 20 includes a control section 12, an arbiter 13, and an instruction generation section 14.
In the present embodiment, in the case where a selected one 20 of the plurality of memory banks 20 is accessed during operation 1, the control section 12 of each memory bank 20 controls the update operation in the selected memory bank 20 when the update request of the memory is generated during operation 1. Specifically, after the operation 1 is completed, the control section 12 of the selection bank 20 performs an update operation of the number of update request signals ref_requests generated during the operation 1; and the control part 12 of the other memory banks 20 except the selected memory bank 20 controls the refresh operation in the other memory banks 20 during the 1 st operation so as to be performed in response to the generated refresh request signal ref_request during the 1 st operation.
For example, in the case where the i (0+.i+.n-1) th bank 20 among the plurality of banks 20 is accessed during the 1 st operation, when an update request of the memory is generated during the 1 st operation, the update operation in the i th bank 20 performs the update operation of the number of update request signals ref_requests generated during the 1 st operation after the 1 st operation is ended. On the other hand, the refresh operation in the memory banks 20 other than the i-th memory bank 20 is performed during operation 1 in response to the refresh request signal ref_request generated.
It should be noted that, since the present embodiment accesses a plurality of banks in an interleaved manner, in an example, the update operation is performed on the ith bank 20 after the operation 1 is finished, and the access operation to other banks can be simultaneously started, so as to increase the processing performance of the pSRAM. However, in another example, the present invention may execute only the update operation of the i-th repository 20 during the period from the end of the 1 st operation to the start of the 2 nd operation, as in embodiment 1. And the 2 nd operation is restarted after the update operation to the i-th repository 20 is completed.
In the present embodiment, the arbiter 13 of each Bank 20 inputs a Bank address signal Bank in addition to the chip select signal cs# and the signal cmp_ref. In this case, the arbiter 13 may operate in the same manner as in embodiment 1 when the inputted Bank address signal Bank indicates the Bank to which it is set. The Bank address signal Bank address may be generated by an address decoding circuit (not shown) provided in the pSRAM 10, for example.
In the present embodiment, the command generating section 14 of each memory Bank 20 inputs a Bank address signal Bank in addition to the wafer selection signal cs# and the signal cmp_ref. In this case, the command generating unit 14 may operate in the same manner as in embodiment 1 when the input Bank address signal Bank indicates the Bank to which it is set.
The operation of the pSRAM according to the present embodiment is described with reference to fig. 5. Here, a case where the 0 th (i=0) th bank 20 is accessed during the 1 st operation and the 1 st (i=1) th bank 20 is accessed during the 2 nd operation will be described as an example.
Here, the operations of the control unit 12, the arbiter 13, and the instruction generation unit 14 in the 0 th bank 20 when the 0 th (i=0) th bank 20 is accessed during the 1 st operation are the same as the operations of the control unit 12, the arbiter 13, and the instruction generation unit 14 in the respective times t1, t2, t3, t4, and t5 shown in fig. 2 in the respective times t11, t12, t13, t14, and t 15. That is, each of the access signal RD/wr_0, the update signal ref_0, the signal cnt_req_0, the signal cnt_exe_0, and the signal cmp_ref_0 of the 0 th bank 20 shown in fig. 5 is the same as each of the access signal RD/WR, the update signal REF, the signal cnt_req, the signal cnt_exe, and the signal cmp_ref shown in fig. 2.
Therefore, when the update request of the memory is generated during the 1 st operation, the update operation in the 0 th bank 20 is performed only by the number of update request signals ref_requests (2 times in the example of the figure) generated during the 1 st operation in the period from the end of the 1 st operation to the start of the 2 nd operation.
Next, the update operation in the 1 st (i=1) th memory bank 20 during the 1 st operation will be described. First, when the wafer select signal cs# transitions from a high level to a low level, the 1 st operation starts because the 1 st bank 20 is not an access target, and the command generating section 14 of the 1 st bank 20 generates the low-level access signal RD/WR to be output to the memory array.
At time t11, when the high-level update request signal ref_request is generated by the oscillator 11, the counter 12a of the 1 st bank 20 increases the count value from 0 to 1, and outputs a signal cnt_req_1 showing the count value of 1 to the comparator 12c. In addition, the comparator 12c of the 1 st bank 20 compares the value of the signal cnt_req_1 with the value of the signal cnt_exe_1 (here, 0 is assumed), and outputs a high-level output signal to the and gate 12e of the 1 st bank 20 because the value of the signal cnt_req_1 is larger than the value of the signal cnt_exe_1. The and gate 12e of the 1 st bank 20 performs a logical and operation between the output signal from the comparator 12c and the signal outputted from the inverter 12d (high level because the update signal ref_1 is low), and outputs the high level signal cmp_ref_1 to the arbiter 13 of the 1 st bank 20.
At time t11, since the 1 st bank 20 is not the access target, the arbiter 13 outputs the signal cmp_ref_1 to the instruction generation unit 14. The command generating unit 14 of the 1 st bank 20 generates the high-level update signal ref_1 in response to the high-level signal cmp_ref_1 input from the arbiter 13, and outputs the high-level update signal ref_1 to the memory array, the counter 12b of the 1 st bank 20, and the inverter 12d. Thus, the 1 st update action in the 1 st repository 20 is performed during the 1 st operation.
When the update signal ref_1 of the high level is input, the counter 12b of the 1 st bank 20 increases the count value from 0 to 1, and outputs a signal cnt_exe_1 showing the count value of 1 to the comparator 12c. At this time, since the value of the signal cnt_req_1 is equal to the value of the signal cnt_exe_1, the comparator 12c of the 1 st memory bank 20 outputs the output signal of the low level to the and gate 12e. Therefore, the signal cmp_ref_1 output from the and gate 12e of the 1 st bank 20 becomes low level.
Next, at time t12, when the high-level update request signal ref_request is generated by the oscillator 11, the control unit 12, the arbiter 13, and the instruction generation unit 14 of the 1 st memory bank 20 operate in the same manner as the operation at time t 11. Thus, the 2 nd update action in the 1 st repository 20 during the 1 st operation.
In addition, all the libraries 20 other than the 0 th library 20 of the plurality of libraries 20 may perform the same update operation as the 1 st library 20.
Thus, when an update request is generated during operation 1, the update operations in the banks 20 other than 0 of the plurality of banks 20 are performed during operation 1 in response to the generated update request signal ref_request.
As described above, according to the pSRAM of the present embodiment, for the selection bank 20 (0 th bank 20) accessed during the 1 st operation, only the number of update operations of the update requests generated during the 1 st operation can be performed during the period from the end of the 1 st operation to the start of the 2 nd operation. On the other hand, for the non-selected store 20 (1 st store 20) during the 1 st operation, the update action may be performed immediately when the update request is generated during the 1 st operation. Thus, the update action in each of the plurality of memory banks 20 may be performed appropriately depending on whether it is a selected memory bank. In this case, since tCSH can be shortened between the end of the 1 st operation (for the 0 th bank 20) and the start of the 2 nd operation (for the 1 st bank 20), the processing performance of the pSRAM can be improved.
The examples described above are presented for the purpose of facilitating understanding of the present invention, and are not intended to limit the present invention. Accordingly, the elements disclosed in the above embodiments are intended to include all design modifications and equivalents falling within the technical scope of the present invention.
For example, in the above embodiments, as shown in fig. 2 and 4, the control unit 12 has been described as an example in which the control unit 12 includes the counter 12a, the counter 12b, the comparator 12c, the inverter 12d, and the and gate 12e, but the configuration of the control unit 12 may be changed as appropriate, or other various configurations may be adopted.
In the above-described embodiment 2, the control unit 12 is provided in each of the plurality of storage libraries 20 as an example, but the present invention is not limited to this. For example, a single control unit 12 may be provided in the pSRAM 10 to control the update operation in each memory bank 20.
In the above-described embodiment 2, the control unit 12, the arbiter 13, and the instruction generation unit 14 are provided in each of the plurality of banks 20 as an example, but the present invention is not limited thereto. For example, a single control unit 12, arbiter 13, and command generation unit 14 may be provided in the pSRAM 10, and the update operation in each memory bank 20 may be controlled by the control unit 12, arbiter 13, and command generation unit 14.
Claims (10)
1. A virtual static random access memory, comprising:
and a control unit configured to control, when an update request of the memory is generated during the 1 st operation, the number of update requests generated during the 1 st operation to be executed by the memory during a period from the end of the 1 st operation to the start of the 2 nd operation after the 1 st operation.
2. The pseudo-static random access memory according to claim 1, wherein said control section comprises:
a 1 st counter for counting the number of update requests generated during the 1 st operation; and
a 2 nd counter for counting the number of update operations performed between the end of the 1 st operation and the start of the 2 nd operation;
the control unit controls the update operation until the number of update operations counted by the 2 nd counter reaches the number of update requests counted by the 1 st counter.
3. The pseudo-static random access memory according to claim 2, wherein said control section further comprises:
and a comparator for comparing the number of update requests counted by the 1 st counter with the number of update operations counted by the 2 nd counter.
4. The virtual static random access memory of claim 2, further comprising:
a command generating unit for generating an update signal for executing an update operation based on the control of the control unit;
wherein the instruction generating unit outputs the update signal to the 2 nd counter every time the update signal is generated.
5. The pseudo-static random access memory according to claim 4, wherein said instruction generating section generates an access signal for data access to the memory cell array during said 1 st operation.
6. The virtual static random access memory of claim 4, further comprising:
an arbiter that outputs the update control signal to the command generating unit each time the update control signal is input from the control unit in a period from the end of the 1 st operation to the start of the 2 nd operation;
wherein the instruction generating unit generates the update signal each time the update control signal is input.
7. The virtual static random access memory of claim 1, further comprising:
a plurality of memory banks accessed in an interleaved manner;
wherein the control unit performs the following operations:
during operation 1, when a selected one of the plurality of memory banks is accessed, and when a refresh request for the memory is generated during operation 1,
controlling the update operation in the selection memory bank to execute only the number of update requests generated during the 1 st operation, during the period from the end of the 1 st operation to the start of the 2 nd operation; and
control the update operation in the other memory banks other than the selected memory bank among the plurality of memory banks, and execute the update request in response to the generated update request during the 1 st operation.
8. The pseudo-static random access memory according to claim 7, wherein each of said plurality of memory banks includes said control portion.
9. The pseudo-sram according to any one of claims 1 to 8, wherein the pseudo-sram is a clocked pseudo-sram having signals input or output in synchronization with clock signals.
10. The pseudo-sram according to any one of claims 1 to 8, wherein said pseudo-sram is an address data multiplexing interface type pseudo-sram.
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