JP7373034B1 - pseudo-static random access memory - Google Patents

Abstract

A pseudo-static random access memory is provided that can reliably perform a refresh operation in response to each of one or more refresh requests generated during a transaction. In the pseudo-static random access memory, when a memory refresh request is generated during a first transaction, a memory refresh operation is performed in a second transaction after the first transaction after the first transaction is completed. The controller 10 includes a control unit 10 that controls the number of refresh requests generated during the first transaction to be executed until the first transaction starts. [Selection diagram] Figure 2

Description

The present invention relates to pseudo-static random access memory (pSRAM).

pSRAM is a semiconductor memory device equipped with an interface compatible with SRAM (Static Random Access Memory) (for example, Patent Document 1).

An example of a refresh operation in a conventional pSRAM will be described with reference to FIG. In the example shown in FIG. 1, a read or write transaction is started when the chip select signal CS# transitions from negated (high level) to asserted (low level). When the access signal RD/WR for accessing data to the memory cell array shifts from negated (low level) to asserted (high level), data read or write access to the memory cell array is performed. Thereafter, when the chip select signal CS# transitions from asserted (low level) to negated (high level), the read or write transaction ends. Then, when the access signal RD/WR transitions from asserted (high level) to negated (low level), the data read or write access to the memory cell array ends.

Furthermore, inside the pSRAM, a refresh request signal Ref request for requesting a refresh operation is generated at predetermined generation intervals tREFI. Here, in the pSRAM, when the refresh request signal Ref request is generated (becomes high level) while the chip select signal CS# is negated (high level), the refresh signal REF for performing the refresh operation is immediately generated. It is configured to perform a refresh operation by being asserted (high level). On the other hand, if the refresh request signal Ref request is generated (becomes high level) while the chip select signal CS# is asserted (low level) (during read or write access), the pSRAM performs no read or write operation. Wait for the refresh operation to be performed because the access is in progress. Then, the pSRAM performs a refresh operation when the chip select signal CS# is negated (high level) and the access signal RD/WR transitions from asserted (high level) to negated (low level).

Japanese Patent Application Publication No. 2020-135914

In such a pSRAM, if the period tCSL during which the chip select signal CS# is asserted (low level) is longer than the generation interval tREFI of the refresh request signal Ref request (i.e., tCSL>tREFI), the refresh request is ignored. There is a possibility that the refresh operation may not be performed due to this. For example, in the example shown in FIG. 1, two refresh request signals Ref request are generated during the period tCSL in which the chip select signal CS# is asserted (low level), but the chip select signal CS# is negated (high level). ), a refresh operation can only be performed once, and the second refresh request will be ignored. This may make it difficult to retain data because a refresh operation is not performed in response to each one or more refresh requests generated during a transaction.

On the other hand, if tCSL<tREFI, it is possible to prevent the refresh request from being ignored. However, in this case, the period tCSL during which the chip select signal CS# is asserted (low level) becomes shorter, so the amount of data that can be transmitted and received in one transaction is reduced. This may reduce the data transfer rate.

In order to solve the above problems, the present invention provides that when a memory refresh request is generated during a first transaction, the memory refresh operation is performed after the first transaction ends and after the first transaction. A pseudo-static random access memory is provided, the pseudo-static random access memory comprising a control unit configured to execute refresh requests as many times as the number of refresh requests generated during the first transaction until the second transaction starts.

According to this invention, between the end of the first transaction and the start of the second transaction, refresh operations are performed as many times as there are refresh requests generated during the first transaction. As a result, even if, for example, the period during which the chip select signal is asserted (low level) is longer than the refresh request signal generation interval, each of the one or more refresh requests generated during the first transaction The refresh operation can be reliably performed according to the Therefore, data retention characteristics can be maintained.

The pseudo-static random access memory of the present invention ensures that refresh operations are performed in response to each of one or more refresh requests generated during a transaction.

3 is a time chart showing an example of a time transition of a signal in a conventional pSRAM. 1 is a block diagram showing a configuration example of a pSRAM according to a first embodiment of the present invention. FIG. 5 is a time chart showing an example of a time transition of a signal in the pSRAM according to the first embodiment. FIG. 2 is a block diagram showing a configuration example of a pSRAM according to a second embodiment of the present invention. 7 is a time chart showing an example of a time transition of a signal in a pSRAM according to a second embodiment.

(First embodiment)
FIG. 2 is a block diagram showing a configuration example of a pSRAM (pseudo static random access memory) 10 according to the first embodiment of the present invention. When the memory refresh request signal Ref_request is generated during the first transaction, the pSRAM 10 performs the memory refresh operation from the end of the first transaction until the start of the second transaction after the first transaction. The refresh request signal Ref_request is executed as many times as the refresh request signals Ref_request generated during the first transaction.

Furthermore, the pSRAM according to this embodiment may be a clock-synchronous pseudo-static random access memory in which a signal is input or output in synchronization with a clock signal. Further, the pSRAM according to this embodiment may be an address data multiplex interface type pSRAM having an address data terminal configured to receive each of an address signal and a data signal.

As shown in FIG. 2, the pSRAM 10 includes an oscillator 11, a control section 12, an arbiter 13, and a command generation section 14.

The oscillator 11 generates a refresh request signal Ref_request at predetermined intervals (for example, the generation interval tREFI shown in FIG. 1) and outputs it to the control unit 12.

The control unit 12 includes a counter 12a, a counter 12b, a comparator 12c, an inverter 12d, and an AND circuit 12e.

The counter 12a is configured to count the number of refresh request signals Ref_request. Specifically, the counter 12a counts the number of input refresh request signals Ref_request every time the refresh request signal Ref_request is input from the oscillator 11. Then, the counter 12a outputs a signal Cnt_req indicating the number of refresh request signals Ref_request to the comparator 12c.

Note that the value of the signal Cnt_req is reset to the initial value (for example, 0) each time a transaction starts (the chip select signal CS# transitions from negation (high level) to assertion (low level)). Good too.

The counter 12b is configured to count the number of refresh operations performed between the end of the first transaction and the start of the second transaction. Specifically, the counter 12b counts the number of input refresh signals REF each time a refresh signal REF for executing a refresh operation is input from the command generation section 14. Then, the counter 12b outputs a signal Cnt_exe indicating the number of refresh signals REF to the comparator 12c.

Note that the value of the signal Cnt_exe is reset to the initial value (for example, 0) each time a transaction ends (chip select signal CS# transitions from assertion (low level) to negation (high level)). Good too.

The comparator 12c is configured to compare the number of refresh request signals Ref_request counted by the counter 12a and the number of refresh signals REF counted by the counter 12b. Specifically, the comparator 12c compares the value of the signal Cnt_req input from the counter 12a and the value of the signal Cnt_exe input from the counter 12b. Then, when Cnt_req>Cnt_exe, the comparator 12c outputs a high-level output signal to the AND circuit 12e. On the other hand, the comparator 12c outputs a low-level output signal to the AND circuit 12e when Cnt_req≦Cnt_exe.

The inverter 12d logically inverts the refresh signal REF input from the command generating section 14, and outputs the logically inverted signal to the AND circuit 12e.

The output signal output from the comparator 12c is input to one input terminal of the AND circuit 12e. Furthermore, the signal output from the inverter 12d is input to the other input terminal of the AND circuit 12e. The AND circuit 12e performs an AND operation based on the input signal and outputs a signal Cmp_ref as the operation result to the arbiter 13. Here, the signal Cmp_ref is an example of the "refresh control signal" of the present invention.

The arbiter 13 performs arbitration between the chip select signal CS# and the signal Cmp_ref, and adjusts the timing of outputting the signal Cmp_ref to the command generation unit 14. Further, in the present embodiment, the arbiter 13 performs refresh control every time a refresh control signal (signal Cmp_ref) is input from the control unit 12 between the end of the first transaction and the start of the second transaction. It is configured to output a signal (signal Cmp_ref) to the command generation unit 14.

Specifically, when the chip select signal CS# is negated (high level) (that is, between the end of the first transaction and the start of the second transaction), the arbiter 13 outputs a high level signal. When the signal Cmp_ref is input from the control unit 12, a high-level signal Cmp_ref may be output to the command generation unit 14. Furthermore, if a high level signal Cmp_ref is input from the control unit 12 while the chip select signal CS# is asserted (low level) (that is, during a transaction), the arbiter 13 outputs the high level signal Cmp_ref. does not have to be output to the command generation unit 14.

The command generation unit 14 generates a refresh signal REF for performing a refresh operation based on the control by the control unit 12. Further, the command generation unit 14 outputs the refresh signal REF to the counter 12b every time it generates the refresh signal REF. Specifically, the command generation unit 14 operates when the chip select signal CS# is negated (high level) and the access signal RD/WR for accessing data to the memory cell array is low. In the case of a high level signal Cmp_ref is input from the arbiter 13, a high level refresh signal REF is generated and sent to the memory cell array (not shown), the counter 12b and the inverter 12d of the control unit 12. Output.

Additionally, when a read or write command is input from the outside during each transaction (while the chip select signal CS# is asserted (low level)), the command generation unit 14 generates a high level access signal RD/WR. generated and output to the memory cell array.

Note that when a high-level refresh signal REF is input to the memory cell array, a memory refresh operation is executed, and when a high-level access signal RD/WR is input to the memory cell array, data read or write processing to the memory cell array is executed. It will be done.

Next, a refresh operation in the pSRAM according to this embodiment will be explained with reference to FIG. 3. Here, an example will be described in which the period tCSL during which the chip select signal CS# is asserted (low level) is longer than the generation interval tREFI of the refresh request signal Ref_request.

First, when a read or write command is input from the outside after the chip select signal CS# transitions from negated (high level) to asserted (low level) and the first transaction is started, the command generation unit 14 outputs a high level signal. The access signal RD/WR is generated and output to the memory cell array.

Here, at time t1, when the high-level refresh request signal Ref_request is generated by the oscillator 11, the counter 12a of the control unit 12 increases the count value for counting the refresh request signal Ref_request from 0 to 1, and the count value A signal Cnt_req indicating that is 1 is output to the comparator 12c. Further, the comparator 12c compares the value of the signal Cnt_req and the value of the signal Cnt_exe (here, it is assumed that the value is 0), and since the value of the signal Cnt_req is larger than the value of the signal Cnt_exe, the value of the signal Cnt_req is higher than that of the signal Cnt_exe. The level output signal is output to the AND circuit 12e. Further, the AND circuit 12e performs an AND operation between the output signal from the comparator 12c and the signal output from the inverter 12d (since the first refresh signal REF is at a low level, the signal output from the inverter 12d is at a high level). It performs calculations and outputs a high-level signal Cmp_ref to the arbiter 13.

Here, since the chip select signal CS# is asserted (low level) at time t1, the arbiter 13 does not output the received high level signal Cmp_ref to the command generation unit 14. Further, as described above, the command generation unit 14 generates the high-level access signal RD/WR and outputs it to the memory cell array.

Next, at time t2 after a predetermined interval tREFI from time t1, when a high-level refresh request signal Ref_request is generated by the oscillator 11, the counter 12a of the control unit 12 increases the count value from 1 to 2, A signal Cnt_req indicating that the count value is 2 is output to the comparator 12c. Further, since the value of the signal Cnt_req is larger than the value of the signal Cnt_exe, the comparator 12c outputs a high-level output signal to the AND circuit 12e. Furthermore, the AND circuit 12e outputs a high-level signal Cmp_ref to the arbiter 13 as in the case of time t1. The operations of the arbiter 13 and command generation unit 14 at time t2 are the same as those at time t1.

When chip select signal CS# transitions from assertion (low level) to negation (high level) after time t2, arbiter 13 outputs high level signal Cmp_ref to command generation unit 14. On the other hand, when the access signal RD/WR becomes low level at time t3, the command generation unit 14 generates a high level refresh signal REF at time t4 in response to the high level signal Cmp_ref input from the arbiter 13. , the memory cell array, and the counter 12b and inverter 12d of the control unit 12.

When the high-level refresh signal REF is input, the counter 12b of the control unit 12 increases the count value from 0 to 1, and outputs a signal Cnt_exe indicating that the count value is 1 to the comparator 12c. Note that at time t4, the value of the signal Cnt_req is still larger than the value of the signal Cnt_exe, so the comparator 12c outputs a high-level output signal to the AND circuit 12e. Note that the signal Cmp_ref output from the AND circuit 12e becomes a low level when a high-level refresh signal REF is output from the command generation section 14, but when the refresh operation is completed and the refresh signal REF becomes a low level. Then it becomes high level again. At this time, the arbiter 13 outputs a high-level signal Cmp_ref to the command generation unit 14.

Then, at time t5 after a period tRFC (refresh interval) has elapsed from time t4, the command generation unit 14 generates a high-level refresh signal REF again in response to the high-level signal Cmp_ref input from the arbiter 13. The output signal is output to the memory cell array, the counter 12b and the inverter 12d of the control section 12. Here, when the high-level refresh signal REF is input, the counter 12b of the control unit 12 increases the count value from 1 to 2, and outputs a signal Cnt_exe indicating that the count value is 2 to the comparator 12c. . Further, since the value of the signal Cnt_req and the value of the signal Cnt_exe are equal, the comparator 12c outputs a low level output signal to the AND circuit 12e. In this case, when the signal Cmp_ref becomes low level and then the refresh signal REF shifts to low level again, the signal Cmp_ref output from the AND circuit 12e maintains the low level. Then, the process ends after performing two refresh operations in response to the two refresh request signals Ref_request generated during the transaction.

In the example shown in FIG. 3, after a period tCSH has elapsed since the chip select signal CS# transitioned from low level to high level, it becomes low level again, and the second transaction is started. However, in this example, when the second transaction is started, the second refresh operation is in progress. Therefore, the command generation unit 14 stops asserting (high level) the access signal RD/WR in response to the start of the second transaction until the second refresh operation ends (the second refresh signal REF goes low). You may wait until the next level.

As described above, according to the pSRAM of this embodiment, for example, even if the period tCSL during which the chip select signal CS# is asserted (low level) is longer than the generation interval tREFI of the refresh request signal Ref_request, Refresh operations can be reliably performed in response to each of one or more refresh requests generated during a transaction. Furthermore, in this case, it is possible to suppress a decrease in the data transfer rate and maintain data retention characteristics.

(Second embodiment)
A second embodiment of the present invention will be described below. The pSRAM of this embodiment differs from the first embodiment in that it includes a plurality of memory banks that are accessed in an interleaved manner. Hereinafter, configurations different from the first embodiment will be explained.

In this embodiment, the pSRAM 10 includes a plurality of (for example, n (n is an integer of 2 or more)) memory banks 20 that are accessed in an interleaved manner, as shown in FIG. Each memory bank 20 includes a control section 12, an arbiter 13, and a command generation section 14.

In this embodiment, the control unit 12 of each memory bank 20 refreshes the memory during the first transaction when the memory bank 20 selected from among the plurality of memory banks 20 is accessed in the first transaction. When a request is generated, the refresh operation in the selected memory bank 20 is controlled. Specifically, after the first transaction is completed, the control unit 12 of the memory bank 20 controls to execute refresh operations as many as the number of refresh request signals Ref_request generated during the first transaction, and performs the selected refresh operations. In the first transaction, the control unit 12 of the other memory bank 20 other than the memory bank 20 controls the control unit 12 of the other memory bank 20 to perform a refresh operation in response to the generated refresh request signal Ref_request. do.

For example, in the first transaction, the i-th (0≦i≦n-1) memory bank 20 among the plurality of memory banks 20 is accessed, and a memory refresh request is generated during the first transaction. If so, in the i-th memory bank 20, after the first transaction ends, refresh operations are performed as many times as the number of refresh request signals Ref_request generated during the first transaction. On the other hand, refresh operations in memory banks 20 other than the i-th memory bank 20 among the plurality of memory banks 20 are performed during the first transaction in response to the generated refresh request signal Ref_request.

Note that this embodiment accesses multiple memory banks 20 in an interleaved pattern. Therefore, in one example, when performing a refresh operation on the i-th memory bank 20 after the first transaction is completed, accesses to other memory banks 20 can be performed simultaneously, thereby allowing Processing performance can be improved. However, in another example, the present invention performs only the refresh operation for the i-th memory bank 20 between the end of the first transaction and the start of the second transaction, as shown in the first embodiment. , it is possible to start the second transaction after the refresh operation for the i-th memory bank 20 is completed.

In this embodiment, the arbiter 13 of each memory bank 20 receives a bank address signal Bank address in addition to the chip select signal CS# and the signal Cmp_ref. In this case, the arbiter 13 may operate in the same manner as in the first embodiment when the input bank address signal Bank address indicates the memory bank in which the arbiter 13 is provided. Note that the bank address signal Bank address may be generated by, for example, an address decoder circuit (not shown) provided in the pSRAM 10.

Further, in this embodiment, the command generation unit 14 of each memory bank 20 receives a bank address signal Bank address in addition to the chip select signal CS# and the signal Cmp_ref. In this case, the command generation unit 14 may operate in the same manner as in the first embodiment when the input bank address signal Bank address indicates the memory bank in which the command generation unit 14 is provided.

The operation of the pSRAM according to this embodiment will be explained with reference to FIG. Here, a case will be described as an example in which the 0th (i=0) memory bank 20 is accessed in the first transaction and the first (i=1) memory bank 20 is accessed in the second transaction.

Here, times t11, t12, t13 of the control unit 12, arbiter 13, and command generation unit 14 of the 0th memory bank 20 when the 0th (i=0) memory bank 20 is accessed in the first transaction. , t14, and t15 are similar to the operations of the control unit 12, arbiter 13, and command generation unit 14 at times t1, t2, t3, t4, and t5 shown in FIG. That is, each of the access signal RD/WR_0, refresh signal REF_0, signal Cnt_req_0, signal Cnt_exe_0, and signal Cmp_ref_0 of the 0th memory bank 20 shown in FIG. 5 corresponds to the access signal RD/WR, refresh signal REF, and signal shown in FIG. This is similar to Cnt_req, signal Cnt_exe, and signal Cmp_ref.

As a result, if a memory refresh request is generated during the first transaction, the refresh operation in the 0th memory bank 20 will be performed between the end of the first transaction and the start of the second transaction. The refresh request signal Ref_request generated during the first transaction is executed the same number of times (in the illustrated example, twice).

Next, a refresh operation in the first (i=1) memory bank 20 during the first transaction will be described. First, when the chip select signal CS# shifts from negated (high level) to asserted (low level) and a first transaction starts, the command generation unit 14 of the first memory bank 20 Since it is not an access target, a low-level access signal RD/WR is generated and output to the memory cell array.

At time t11, when the high-level refresh request signal Ref_request is generated by the oscillator 11, the counter 12a of the first memory bank 20 increases the count value from 0 to 1, indicating that the count value is 1. The signal Cnt_req_1 is output to the comparator 12c. Further, the comparator 12c of the first memory bank 20 compares the value of the signal Cnt_req_1 and the value of the signal Cnt_exe_1 (here, it is assumed that the value is 0), and the value of the signal Cnt_req_1 is determined to be the value of the signal Cnt_exe_1. , a high-level output signal is output to the AND circuit 12e of the first memory bank 20. Furthermore, the AND circuit 12e of the first memory bank 20 performs an AND operation between the output signal from the comparator 12c and the signal output from the inverter 12d (which becomes high level because the refresh signal REF_1 is low level). , outputs a high level signal Cmp_ref_1 to the arbiter 13 of the first memory bank 20.

At time t11, the first memory bank 20 is not the access target, so the arbiter 13 outputs a high-level signal Cmp_ref_1 to the command generation unit 14. Further, the command generation unit 14 of the first memory bank 20 generates a high-level refresh signal REF_1 in response to the high-level signal Cmp_ref_1 input from the arbiter 13, and generates a high-level refresh signal REF_1 to connect the memory cell array and the first memory bank 20. The output signal is output to the counter 12b and the inverter 12d. As a result, the first refresh operation is performed in the first memory bank 20 during the first transaction.

When the high-level refresh signal REF_1 is input, the counter 12b of the first memory bank 20 increases the count value from 0 to 1, and outputs a signal Cnt_exe_1 indicating that the count value is 1 to the comparator 12c. . In this case, since the value of the signal Cnt_req_1 is equal to the value of the signal Cnt_exe_1, the comparator 12c of the first memory bank 20 outputs a low-level output signal to the AND circuit 12e. As a result, the signal Cmp_ref_1 output from the AND circuit 12e of the first memory bank 20 becomes low level.

Next, at time t12, when the high-level refresh request signal Ref_request is generated by the oscillator 11, the control section 12, arbiter 13, and command generation section 14 of the first memory bank 20 operate in the same manner as at time t11. Operate. As a result, a second refresh operation is performed in the first memory bank 20 during the first transaction.

Note that all the memory banks 20 other than the 0th memory bank 20 among the plurality of memory banks 20 can perform a refresh operation in the same way as the 1st memory bank 20.

In this way, when a memory refresh request is generated during the first transaction, refresh operations in memory banks 20 other than the 0th among the plurality of memory banks 20 are performed in accordance with the generated refresh request signal Ref_request. is executed during the first transaction.

As described above, according to the pSRAM of this embodiment, the selected memory bank 20 (0th memory bank 20) to be accessed in the first transaction is accessed in the second transaction after the first transaction is completed. , it is possible to perform refresh operations equal to the number of refresh requests generated during the first transaction. On the other hand, for the memory bank 20 that was not selected in the first transaction (first memory bank 20), it becomes possible to perform a refresh operation immediately when a refresh request is generated during the first transaction. Thereby, the refresh operation in each of the plurality of memory banks 20 can be appropriately executed depending on whether or not the memory bank 20 is selected in a transaction. In addition, in this case, it is possible to shorten the period tCSH from the end of the first transaction (to the 0th memory bank 20) until the start of the second transaction (to the 1st memory bank 20). Therefore, it becomes possible to improve the processing performance of pSRAM.

The embodiments described above are described to facilitate understanding of the present invention, and are not described to limit the present invention. Therefore, each element disclosed in each of the above embodiments is intended to include all design changes and equivalents that fall within the technical scope of the present invention.

For example, in each of the embodiments described above, as shown in FIGS. 2 and 4, an example is given in which the control unit 12 includes a counter 12a, a counter 12b, a comparator 12c, an inverter 12d, and an AND circuit 12e. However, the configuration of the control unit 12 may be changed as appropriate, and various other configurations may be adopted.

Further, in the second embodiment described above, the case where the control unit 12 is provided in each of the plurality of memory banks 20 has been described as an example, but the present invention is not limited to this case. For example, one control unit 12 provided in the pSRAM 10 may control the refresh operation in each memory bank 20.

Further, in the second embodiment described above, the case where the control unit 12, the arbiter 13, and the command generation unit 14 are provided in each of the plurality of memory banks 20 has been described as an example, but the present invention is not limited to this case. . For example, one control unit 12, one arbiter 13, and one command generation unit 14 may be provided, and the refresh operation in each memory bank 20 may be controlled using the control unit 12, arbiter 13, and command generation unit 14. .

10...Pseudo static random access memory (pSRAM)
11...Oscillator 12...Control unit 12a...Counter 12b...Counter 12c...Comparator 13...Arbiter 14...Command generation unit 20...Memory bank

Claims (10)

When a memory refresh request is generated during a first transaction, the memory refresh operation is performed between the end of the first transaction and the start of a second transaction after the first transaction; comprising a control unit configured to execute refresh requests equal to the number of refresh requests generated during the first transaction;
Pseudo-static random access memory. The control unit includes:
a first counter that counts the number of refresh requests generated during the first transaction;
a second counter that counts the number of refresh operations executed between the end of the first transaction and the start of the second transaction;
controlling to perform refresh operations until the number of refresh operations counted by the second counter reaches the number of refresh requests counted by the first counter;
A pseudo-static random access memory according to claim 1. The control unit includes:
comprising a comparator that compares the number of refresh requests counted by the first counter and the number of refresh operations counted by the second counter;
The pseudo-static random access memory according to claim 2. a command generation unit that generates a refresh command for executing a refresh operation based on control by the control unit,
The command generation unit outputs the refresh command to the second counter every time the refresh command is generated.
The pseudo-static random access memory according to claim 2. The command generation unit generates an access command for accessing data to the memory cell array during the first transaction.
The pseudo-static random access memory according to claim 4. an arbiter that outputs the refresh control signal to the command generation unit each time the refresh control signal is input from the control unit between the end of the first transaction and the start of the second transaction. ,
The command generation unit generates the refresh command every time the refresh control signal is input.
The pseudo-static random access memory according to claim 4. With multiple memory banks accessed in an interleaved manner,
The control unit includes:
When a memory bank selected from among the plurality of memory banks is accessed in the first transaction, and a memory refresh request is generated during the first transaction,
A refresh operation in the selected memory bank is performed for the number of refresh requests generated during the first transaction between the end of the first transaction and the start of the second transaction. control,
controlling a refresh operation in a memory bank other than the selected memory bank among the plurality of memory banks to be executed during the first transaction in response to the generated refresh request;
A pseudo-static random access memory according to claim 1. Each of the plurality of memory banks includes the control section,
The pseudo-static random access memory according to claim 7. The pseudo-static random access memory is a clock-synchronous pseudo-static random access memory in which a signal is input or output in synchronization with a clock signal.
A pseudo-static random access memory according to any one of claims 1 to 8. The pseudo-static random access memory is an address data multiplex interface type pseudo-static random access memory.
A pseudo-static random access memory according to any one of claims 1 to 8.

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