JP7394655B2 - Imaging devices and radiation imaging devices - Google Patents

Description

The present invention relates to an imaging device and a radiation imaging device, and more particularly to an imaging device including an amplification transistor in a pixel and a radiation imaging device using the imaging device.

Conventionally, in so-called APS (active pixel sensor) imaging devices in which each pixel is provided with an amplification transistor, there are examples in which polycrystalline Si TFTs are used as amplification transistors for amplifying signals (Patent Document 1), and examples in which a-Si TFTs are used. (Patent Document 2) and an example using an amorphous oxide semiconductor TFT (Patent Document 3) are known.

Japanese Unexamined Patent Publication No. 58-068968 Japanese Unexamined Patent Publication No. 60-091666 Japanese Patent Application Publication No. 2016-25572

APS image sensors that have amplification transistors in their pixels are greatly affected by variations in threshold voltage caused by manufacturing variations in thin film transistors (TFTs), which leads to malfunction of the source follower circuit and reduces device yield. There was a problem with the decline.

The present invention provides an imaging device including an amplification transistor in a pixel, which can prevent a decrease in device yield due to variations in threshold voltage caused by manufacturing variations in TFTs, and the use of the imaging device. The purpose of the present invention is to provide a radiographic imaging device that has the following characteristics.

(1) A first aspect of the present invention includes a pixel array in which a plurality of pixels forming a plurality of rows and a plurality of columns are arranged, a plurality of signal lines provided corresponding to the plurality of columns, An imaging device comprising:
Each pixel includes a photoelectric conversion element, an amplification transistor that amplifies the electrical signal output from the photoelectric conversion element, and a selection transistor that outputs the amplified electrical signal to the signal line,
The amplification transistor is a thin film transistor, the thin film transistor has a first control electrode and a second control electrode,
The imaging device includes an adjustment voltage generation unit that generates and applies an adjustment voltage for each pixel to adjust the threshold value of the thin film transistor to one of the first control electrode and the second control electrode.

(2) In the imaging device of (1) above, each of the plurality of signal lines may include a load transistor formed of a thin film transistor.

(3) In the imaging device according to (2) above, the load transistor has a third control electrode and a fourth control electrode,
When the adjustment voltage is a first adjustment voltage, a second adjustment voltage for adjusting the threshold value of the load transistor is applied to one of the third control electrode and the fourth control electrode for each signal line. It may be provided with an adjustment voltage application section that applies the adjustment voltage.

(4) In the imaging device according to any one of (1) to (3) above, a scanning circuit unit that sequentially selects a plurality of pixel rows of the pixel array and outputs signals from the pixel array to the plurality of signal lines. Prepare,
The adjustment voltage generation section may apply the adjustment voltage to each amplification transistor of the one pixel row at the same timing as a row selection period in which the scanning circuit section selects one pixel row of the pixel array.

(5) The imaging device according to (3) above, including a scanning circuit section that sequentially selects a plurality of pixel rows of the pixel array and outputs signals from the pixel array to the plurality of signal lines;
The adjustment voltage applying section may apply the second adjustment voltage to the load transistor of the signal line at the same timing as a row selection period in which the scanning circuit section selects one pixel row of the pixel array. .

(6) A second aspect of the present invention is a radiation radiation source comprising the imaging device according to any one of (1) to (5) above, and a scintillator that converts radiation into light, which is provided on at least the photoelectric conversion element. It is an imaging device.

According to the present invention, it is possible to adjust the threshold voltage caused by manufacturing variations of TFTs in a pixel array of an imaging device on a pixel-by-pixel basis, thereby improving the yield of elements due to variations in threshold voltage. I can do it.

FIG. 1 is a block diagram showing the configuration of an imaging device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a circuit configuration of one pixel in an image sensor section. FIG. 2 is a cross-sectional view showing the structure of an amplification transistor. 5 is a timing chart showing operations of input signals and output signals to each transistor of pixels in one pixel row of the image sensor section. 5 is a timing chart showing the operation of input signals and output signals to each transistor of pixels in a plurality of pixel rows of the image sensor section. FIG. 7 is a circuit diagram showing a circuit configuration of one pixel in an image sensor section of an image pickup device according to a second embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of an imaging device according to a second embodiment of the present invention. FIG. 1 is a diagram showing a radiation imaging system including a radiation imaging device.

Hereinafter, embodiments of the present invention will be described in detail using the drawings.
(First embodiment)
FIG. 1 is a block diagram showing the configuration of an imaging device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing the circuit configuration of one pixel of the image sensor section.

As shown in FIG. 1, the imaging device 10 includes an imaging device section 100, a scanning circuit section 110 that scans pixels of the imaging device section 100, a readout circuit section 120 that reads out signals from the imaging device section 100, and a scanning circuit section 120 that reads out signals from the imaging device section 100. A control unit 130 that controls the circuit unit 110, the readout circuit unit 120, and the regulated voltage generation unit 140 and outputs the regulated voltage value; and a control unit 130 that receives the regulated voltage value from the control unit 130 and generates the regulated voltage based on the regulated voltage value. and an adjustment voltage generation section 140 that outputs the adjusted voltage to the image sensor section 100.

The image sensor unit 100 includes a pixel array in which a plurality of pixels forming j rows and k columns (j and k are natural numbers of 2 or more) are arranged, and j row selection lines Rs provided corresponding to the j rows. and j row reset lines Rr, k column signal lines Cs (which serve as signal lines) provided corresponding to k columns, and k column wiring Cv. As shown in FIG. 2, one pixel of the image sensor section 100 includes a photoelectric conversion element PD, a selection transistor Tr1, a reset transistor Tr2, and an amplification transistor Tr3. The selection transistor Tr1, the reset transistor Tr2, and the amplification transistor Tr3 are composed of thin film transistors (TFTs) using polycrystalline Si, amorphous Si, an amorphous oxide semiconductor, or the like.

The photoelectric conversion element PD has a photoelectric conversion film, and the photoelectric conversion film is formed on the transistor circuit by a film forming method such as vapor deposition, CVD (Chemical Vapor Deposition), or sputtering. Examples of the photoelectric conversion material of the photoelectric conversion film include an organic photoconductive film and an inorganic material such as Si. By forming an electrode on the photoelectric conversion film and applying a bias voltage Vf to this electrode, charges generated by light are read out to the gate electrode of the amplification transistor Tr3 on the transistor circuit side.

The selection transistor Tr1 has a gate electrode connected to the row selection line Rs, and generates an electric signal (hereinafter referred to as a signal) amplified by the amplification transistor Tr3 based on a gate potential (electrical signal) that fluctuates due to the charge generated in the photoelectric conversion element PD. ) is transferred to the column signal line Cs.
The reset transistor Tr2 has a gate electrode connected to the row reset line Rr, resets the charges remaining in the gate electrodes of the photoelectric conversion element PD and the amplification transistor TR3, and sets the gate potential of the gate electrodes of the photoelectric conversion element PD and the amplification transistor TR3. is set to the reset voltage Vrst.
The amplification transistor Tr3 amplifies the gate potential (which becomes an electrical signal) that fluctuates due to the charge generated by the photoelectric conversion element PD, and outputs the amplified signal.

In the pixels arranged in the row direction of the image sensor section 100, the gate electrode of the selection transistor Tr1 of each pixel is connected to a common row selection line Rs, and the gate electrode of the reset transistor Tr2 of each pixel is connected to the common row reset line Rr. connected to. Signals transferred from each pixel arranged in the column direction of the image sensor section 100 are output row by row from a shared column signal line Cs. A load transistor Tr4 is provided for each column in the column signal line Cs, and the amplification transistor Tr3 and load transistor Tr4 function as a source follower circuit, and the amplified signal is read out outside the pixel to read out the signal with a high S/N ratio. I can do it.

The scanning circuit section 110 applies a row selection signal to the row selection line Rs for each pixel row of the pixel array of the image sensor section 100, and turns on the selection transistor Tr1 whose gate electrode is connected to the row selection line Rs. By turning on the selection transistor Tr1, as described above, the signal amplified by the amplification transistor Tr3 is transferred to the column signal line Cs.
In addition, the scanning circuit section 110 turns on the selection transistor Tr1 to read out the signal amplified by the amplification transistor Tr3, and then adds a row reset signal to the row reset line Rr for each row of the image sensor section 100. The reset transistor Tr2 whose gate electrode is connected to the reset line Rr is turned on. By turning on the reset transistor Tr2, the charges remaining in the photoelectric conversion element PD and the amplification transistor TR3 are reset, as described above.
Through the above operations, the scanning circuit section 110 sequentially selects a plurality of pixel rows in the pixel array and outputs signals from the pixel array to the k column signal lines Cs.

The readout circuit unit 120 performs predetermined signal processing, such as amplification processing and A/D conversion processing, on the signals appearing on each column signal line Cs, and reads the processed signals column by column. Output sequentially. By turning on the reset transistor Tr2 during the row selection period, the readout circuit section 120 can reset the accumulated voltage due to the charge generated in the photoelectric conversion element PD, and can detect the signal output from the voltage difference before and after the reset.

The control unit 130 sends a control signal to the scanning circuit unit 110 and the readout circuit unit 120 to control the timing so that the scanning circuit unit 110 and the readout circuit unit 120 perform the above-described operations. The control unit 130 also sends a control signal to the adjustment voltage generation unit 140 so that the adjustment voltage generation unit 140 can output the adjustment voltage to the image sensor unit 100 at the same timing as the row selection signal is applied to the row selection line Rs. send. Furthermore, the control section 130 outputs an adjustment voltage value for generating an adjustment voltage to the adjustment voltage generation section 140. The control unit 130 includes a correction table 131 that associates the adjustment voltage value of each pixel with each pixel.
In the correction table 131, an adjustment voltage value is calculated and recorded in advance so that the signal output from the image sensor section 100 becomes uniform when an image is captured under uniform light.

The adjustment voltage generation section 140 receives the adjustment voltage value from the control section 130, generates an adjustment voltage, and adjusts the threshold of the amplification transistor Tr3 of the image sensor section 100 at the same timing as the selection signal is applied to the row selection line Rs. An adjustment voltage is applied to the electrode for value adjustment via the column wiring Cv. The electrodes for threshold adjustment of the amplification transistors Tr3 in the plurality of pixels arranged in columns are connected to a common column wiring Cv, and the adjustment voltage is applied to each column wiring Cv. The adjustment voltage applied to the column wiring Cv is set for each pixel so as to adjust the threshold value of the amplification transistor Tr3 of the pixel selected by the row selection signal.
The adjustment voltage generation section 140 can set the adjustment voltage of each pixel by using a known voltage generation section as described in, for example, Japanese Patent Application Publication No. 2011-102876. The regulated voltage generation unit 140 may be a power source that generates a regulated voltage based on the regulated voltage value, or may be a circuit that converts a voltage supplied from another power source into an regulated voltage based on the regulated voltage value. Good too.

The amplification transistor Tr3 having an electrode for threshold adjustment will be described below.
FIG. 3 is a cross-sectional view showing the structure of the amplification transistor Tr3. In FIG. 3, a first gate electrode 202 serving as a first control electrode is provided on a substrate 201, a first insulating film 203 is provided on the first gate electrode 202, and a semiconductor layer is provided on the first insulating film 203. 204, a source electrode 205 serving as one main electrode, and a drain electrode 206 serving as the other main electrode are provided. A second insulating film 207 is provided on the semiconductor layer 204, the source electrode 205, and the drain electrode 206, and a second gate electrode 208 serving as a second control electrode is provided so as to face the semiconductor layer 204. A third insulating film 209 is provided on the second gate electrode 208 and the second insulating film 207. In the third insulating film 209, a wiring layer 210 is connected to the source electrode 205 through a via hole 211, a wiring layer 212 is connected to the second gate electrode 208 through a via hole 213, and a wiring layer 212 is connected to the drain electrode 206 through a via hole 215. A wiring layer 214 is provided which is connected via the wiring layer 214. A fourth insulating film 216 is provided on the third insulating film 209.

If the threshold voltage of the amplification transistor Tr3 varies from pixel to pixel, the amplification characteristics for the input of each pixel will vary, which will lead to malfunction of the source follower circuit and reduce the yield of the device.
As a means of correcting such variations in threshold voltage, as shown in FIG. 3, a second gate electrode 208 and a first gate electrode 202 are provided on both upper and lower sides of the semiconductor layer 204 of the amplification transistor Tr3 with an insulating layer interposed therebetween. establish. In this embodiment, one of the first gate electrode 202 and the second gate electrode 208 is used as a threshold adjustment electrode for threshold adjustment.
The other selection transistors Tr1, reset transistor Tr2, and load transistor Tr4 do not need to have threshold adjustment electrodes. However, as will be explained later in the second embodiment, in order to improve the accuracy of correction, it is desirable that the load transistor Tr4 has the same structure as the amplification transistor Tr3.

Next, a method for manufacturing a TFT of the amplification transistor Tr3 having a threshold adjustment electrode will be described using FIG. 3.

First, a first gate electrode 202 made of a metal such as Cu, Al, Mo, Cr, Au, Ni, Ti, W, or a conductive material such as ITO or an organic material is formed on a substrate 201 made of glass or Si. . The first gate electrode 202 is formed by a thin film forming method such as sputtering or vapor deposition, and patterning using photolithography, etching, or the like. The thickness of the first gate electrode 202 is preferably about 10 to 1000 nm.

Next, a first insulating film 203 made of an oxide such as SiO ₂ , SiN, Al ₂ O _{2 ,} nitride, or an organic material is formed on the substrate on which the first gate electrode 202 is formed. This first insulating film 203 is formed by a thin film forming method such as sputtering or CVD, and patterning using photolithography, etching, or the like. After forming the first insulating film 203, the surface is preferably polished for planarization, and the thickness after polishing is preferably 500 nm or less.

Next, an oxide semiconductor made of an oxide semiconductor such as IGZO (a substance made of indium, gallium, zinc, and oxygen), Si, an organic material, etc. is formed on the first insulating film 203. A semiconductor layer 204 is formed. This semiconductor layer 204 is formed by a thin film forming method such as sputtering or CVD, and patterning using photolithography, etching, or the like. The thickness of the semiconductor layer 204 is preferably about 5 nm to 100 nm. After forming the semiconductor layer 204, an annealing treatment may be performed by heating the substrate or irradiating light for activation.

Next, a source electrode 205 and a drain electrode made of a metal such as Cu, Al, Mo, Cr, Au, Ni, Ti, W, or a conductive material such as ITO (Indium Tin Oxide) or an organic material are formed on the semiconductor layer 204. 206 is formed. These source electrode 205 and drain electrode 206 are formed by a thin film forming method such as sputtering or vapor deposition, and patterning using photolithography, etching, or the like. The thickness of the source electrode 205 and the drain electrode 206 is preferably about 10 nm to 500 nm. The source electrode 205 and the drain electrode 206 may be formed not only on the semiconductor layer 204 but also on the first insulating film 203 in order to contact wiring layers 210 and 214, which will be described later.

Next, a second insulating film 207 made of an oxide such as SiO ₂ , SiN, Al ₂ O _{2 ,} nitride, or an organic material is formed on the substrate on which the source electrode 205 and the drain electrode 206 are formed. This second insulating film 207 is formed by a thin film forming method such as sputtering or CVD, and patterning using photolithography, etching, or the like. After forming the second insulating film 207, the surface is preferably polished for planarization, and the thickness after polishing is preferably 500 nm or less.

Next, a second gate electrode 208 made of a metal such as Cu, Al, Mo, Cr, Au, Ni, Ti, W, or a conductive material such as ITO or an organic material is placed on the substrate on which the second insulating film 207 is formed. form. This second gate electrode 208 is formed by a thin film forming method such as sputtering or vapor deposition, and patterning using photolithography, etching, or the like. The thickness of the second gate electrode 208 is preferably about 10 to 1000 nm.

Next, a third insulating film 209 made of an oxide such as SiO ₂ , SiN, Al ₂ O _{2 ,} nitride, or an organic material is formed on the substrate on which the second gate electrode 208 is formed. This third insulating film 209 is formed by a thin film forming method such as sputtering or CVD, and patterning using photolithography, etching, or the like. After forming the third insulating film 209, the surface is preferably polished for planarization, and the thickness after polishing is preferably 500 nm or less.

Next, after forming via holes 211, 213, 215 in the third insulating film 209 and the second insulating film 207 by photolithography, etching, etc., metal such as Cu, Al, Mo, Cr, Au, Ni, Ti, W, etc. Alternatively, wiring layers 210, 212, and 214 made of a conductive material such as ITO or an organic material are formed. The via holes 211, 213, and 215 and the wiring layers 210, 212, and 214 are preferably formed by a damascene method suitable for planarization. The wiring layer 210 is connected to the source electrode 205 through the via hole 211, the wiring layer 212 is connected to the second gate electrode through the via hole 213, and the wiring layer 214 is connected to the drain electrode 206 through the via hole 215. Subsequently, if necessary, a fourth insulating film 216 may be formed for surface protection.

The first gate electrode 202 and the second gate electrode 208 of the amplification transistor Tr3 are, for example, a normal gate electrode for selection and a threshold value adjustment electrode, respectively. When the thickness of the first insulating film 203 > the thickness of the second insulating film 207, the sensitivity to the threshold voltage adjustment becomes high, and the threshold voltage can be adjusted at a relatively low voltage with respect to the first gate electrode 202. become. On the other hand, when the thickness of the first insulating film 203<thickness of the second insulating film 207, the threshold voltage adjustment increases, but the margin against fluctuations in the adjustment voltage becomes larger, making the device resistant to noise. Note that the roles of the first gate electrode 202 and the second gate electrode 208 may be reversed, and in that case, the effect on the thickness will also be reversed.

Next, the timing chart of FIG. 4 shows the operation of input signals and output signals to each transistor of pixels in one pixel row of the image sensor section 100. Further, the timing chart of FIG. 5 shows the operation of input signals and output signals to each transistor of pixels in a plurality of pixel rows of the image sensor section 100.
Light is irradiated onto the photoelectric conversion element PD of each pixel of the image sensor section 100, and charges generated in the photoelectric conversion element PD are accumulated in the gate electrode of the amplification transistor Tr3 as a photoelectric conversion signal Vin.

Next, the scanning circuit section 110 sequentially sends a row selection signal to the rows of the pixel array of the image sensor section 100. For example, as shown in FIG. 4, a case will be described in which a row selection signal is sent to the row selection line Rs of a certain pixel row. When the row selection signal reaches the on level Von during the row selection period of a certain pixel row, the selection transistor Tr1 of the pixel in that pixel row is turned on. Based on the gate potential (photoelectric conversion signal Vin) that fluctuates due to the charge accumulated in the gate electrode of the amplification transistor Tr3, the signal amplified by the amplification transistor Tr3 is read out as Vsig to the column signal line Cs via the selection transistor Tr1. . At the same timing as this row selection period, the threshold adjustment voltage Vad1 is applied to the second gate electrode 208 of the amplification transistor Tr3 of each pixel in the pixel row via the column wiring Cv. The value of this adjustment voltage Vad1 is set according to the variation in the threshold value of the amplification transistor Tr3 for each pixel in the pixel row.

When signal output ends during the row selection period for a certain row, the scanning circuit section 110 sends a row reset signal to the corresponding row of the pixel array of the image sensor section 100. For example, as shown in FIG. 4, when the row reset signal reaches the on level Von during the selection period of a certain row, the reset transistor Tr2 of the pixel in the row is turned on. When the reset transistor Tr2 is turned on, the charges remaining in the photoelectric conversion element PD and the amplification transistor TR3 are reset. By turning on the reset transistor Tr2 during the row selection period, the accumulated voltage due to the charge generated in the photoelectric conversion element PD can be reset, and the signal output can be detected from the voltage difference before and after the reset.
When the row selection period ends, the scanning circuit unit 110 sets the row selection signal and the row reset signal to the off level Voff.
When the row selection period of a certain row ends, the row selection period of the next row starts, and the same operation as the row selection period of the certain row is performed for the pixels of the next row.

FIG. 5 shows the operation of pixel rows during the row selection period of the nth row (n is a natural number of 1≦n<j) and the row selection period of the (n+1)th row.
As shown in FIG. 5, when the row selection signal reaches the on level Von during the row selection period of the nth row, the k selection transistors Tr1Xn of the nth pixel row are turned on, and the operation is similar to that shown in FIG. In this operation, the signals of the k pixels are transferred to the k column signal lines Cs, respectively. The photoelectric conversion signal VinXnYm shown in FIG. 5 indicates the gate potential that fluctuates due to the charge accumulated in the gate electrode of the amplification transistor Tr3 of the pixel in the m column of the n pixel row (m is a natural number of 1≦m<k). , the signal VsigXnYm indicates a signal in which the photoelectric conversion signal VinXnYm is amplified by the amplification transistor Tr3 and read out to the column signal line Cs via the selection transistor Tr1.
At the same timing as this row selection period, the threshold adjustment voltage Vad1 is applied to the second gate electrode 208 of the amplification transistor Tr3Xn (not shown) in the pixel row. The adjustment voltage Vad1 (n, m) shown in FIG. 5 is a voltage applied to the second gate electrode 208 of the amplification transistor of the pixel in the m column of the n pixel row.

In the row selection period for the nth row, when the signal output ends, the scanning circuit unit 110 sends a row reset signal, and when the row reset signal reaches the on level Von, the k reset transistors Tr2Xn of the pixels in the row are turned on. , the charges remaining in the photoelectric conversion element PD and amplification transistor Tr3Xn of each pixel are reset.

When the nth row selection period ends, the (n+1)th row selection period starts, and the same operation as the nth row selection period is performed for the (n+1)th row pixels. The adjustment voltage Vad1 (n+1, m) shown in FIG. 5 is a voltage applied to the second gate electrode 208 of the amplification transistor Tr3Xn+1 of the pixel in the m column of the (n+1) pixel row.

When the row selection period for the last pixel column ends, the readout circuit section 120 sequentially outputs the signal processed for each column. In this way, the imaging operation is performed.

According to the present embodiment, by adjusting the threshold of the amplification transistor with the threshold adjustment voltage, the variation of the signal from pixel to pixel is reduced, so that the subsequent stage for correcting image distortion is The signal processing load can be reduced. Furthermore, since variations in manufacturing can be corrected, it contributes to improving manufacturing yield.

(Second embodiment)
In the first embodiment, an example has been described in which the load transistor Tr4 is not provided with a threshold adjustment electrode, but in order to improve the accuracy of correction, the load transistor Tr4 is also provided with a threshold adjustment electrode in the same way as the amplification transistor Tr3, and the threshold value is It is desirable to make adjustments. In the second embodiment, an example will be described in which the load transistor Tr4 is replaced with a load transistor Tr5 having a threshold value adjustment electrode, and the threshold value adjustment electrode is provided similarly to the amplification transistor Tr3.

FIG. 6 is a circuit diagram showing the circuit configuration of one pixel in the image sensor portion of the image sensor according to the second embodiment of the present invention. The circuit diagram of FIG. 6 is different from the circuit diagram of FIG. 2 in that the load transistor Tr5 shown in FIG. Vad2 is applied.

FIG. 7 is a block diagram showing the configuration of an imaging device according to a second embodiment of the present invention. The block diagram of FIG. 7 differs from the block diagram of FIG. 1 in that the imaging device 11 shown in FIG. 7 has an adjustment voltage application section 150 added to the imaging device 10 of FIG. The adjustment voltage applying section 150 applies an adjustment voltage Vad2 set for each load transistor Tr5 to the threshold adjustment electrodes of the k load transistors Tr5 connected to the k column signal lines Cs.

The structure and manufacturing method of the load transistor Tr5 having a threshold value adjustment electrode are the same as the structure and manufacturing method of the amplification transistor Tr3 described using FIG.
Similar to the amplification transistor Tr3 shown in FIG. 3, the load transistor Tr5 has a second gate electrode 208, which serves as a fourth control electrode, and a third control electrode on both upper and lower sides of the semiconductor layer 204 of the load transistor Tr5, with an insulating layer interposed therebetween. Each of them is provided with a first gate electrode 202 serving as an electrode. One of the first gate electrode 202 and the second gate electrode 208 is used as a threshold adjustment electrode for threshold adjustment.
Further, the functions of the first gate electrode 202 and the second gate electrode 208 in the amplification transistor Tr3 and the relationship between the thicknesses of the first insulating film 203 and the second insulating film 207 are the same for the load transistor Tr5.

The load transistor Tr5 is provided for each of the k column signal lines Cs, and one load transistor Tr5 is connected to one column signal line Cs. The threshold voltage adjustment voltage Vad2 of the load transistor Tr5 is determined for each column regardless of the row scanning of the pixel array.
The adjustment voltage Vad2 is determined in advance by finding a combination of the adjustment voltage of the amplification transistor Tr3 and the adjustment voltage of the load transistor Tr5 so that the pixel data when imaged under uniform light becomes uniform.
Since the adjustment voltage Vad2 can be determined for each column regardless of the row scanning of the pixel array, it can be fixed. The threshold adjustment voltage Vad2 is fixed.

The adjustment voltage application section 150 inputs the adjustment voltage Vad2 to the load transistor Tr5 at the same timing as the row selection period of each pixel row based on the control signal output from the control section 130. The voltage level of the adjustment voltage Vad2 applied to the load transistor Tr5 connected to one column signal line Cs is the same in each row selection period from the first pixel row to the j-th pixel row.

Although the use of the imaging device described above is not particularly limited, a radiation imaging device that detects radiation can be configured by arranging a scintillator above the imaging element section of the imaging device described above. The radiation imaging device can be used as a medical image diagnostic device, a non-destructive testing device, an analysis device, etc. that use radiation. Radiation includes X-rays, alpha rays, beta rays, gamma rays, etc., which are beams produced by particles (including photons) emitted by radiation decay, as well as beams with energy of the same level or higher, such as particle beams, Also includes cosmic rays, etc.

FIG. 8 is a diagram showing a radiation imaging system including a radiation imaging device. In FIG. 8, an example in which X-rays are used as radiation will be explained. The radiation imaging system includes a radiation imaging device 20 and an X-ray source 30. As shown in FIG. 8, the radiation imaging device 20 is configured by disposing a scintillator 101 above the imaging element section 100 of the imaging device 10. In FIG. 8, the scanning circuit section 110, readout circuit section 120, control section 130, and adjustment voltage generation section 140 of the imaging device 10 are omitted.

X-rays emitted from the X-ray source 30 enter the radiation imaging device 20 through the subject. X-rays are converted into light by the scintillator 101, and the light is converted into charges by the photoelectric conversion element PD of the image sensor unit 100, and imaging is performed by the operation described above.
The scintillator 101 absorbs radiation such as X-rays and generates visible light, and is provided at least on the photoelectric conversion element PD. The material of the scintillator 101 is appropriately determined depending on the type of radiation, its purpose, etc., but when detecting X-rays, for example, cesium iodide (CsI) can be used.
In the above description, the radiation imaging device 20 uses the imaging device 10, but the imaging device 11 may also be used.

Although the embodiments described above are preferred embodiments of the present invention, the scope of the present invention is not limited to only the above embodiments, and various modifications may be made without departing from the gist of the present invention. It is possible to implement
For example, the pixel configuration of the image sensor section 100 is not particularly limited to the configuration shown in FIG. 2, and may be other configurations. Specifically, the selection transistor Tr1 may be connected to the drain electrode of the amplification transistor Tr3 on the voltage Vdd application side instead of between the amplification transistor Tr3 and the column signal line Cs.

10, 11 Imaging device 20 Radiation imaging device 30 X-ray source 100 Imaging element section 101 Scintillator 110 Scanning circuit section 120 Readout circuit section 130 Control section 131 Correction table 140 Adjustment voltage generation section 150 Adjustment voltage application section Tr1 Selection transistor Tr2 Reset transistor Tr3 Amplification transistor Tr4, Tr5 Load transistor

Claims (6)

An imaging device comprising a pixel array in which a plurality of pixels constituting a plurality of rows and a plurality of columns are arranged, and a plurality of signal lines provided corresponding to the plurality of columns, the imaging device comprising:
Each pixel includes a photoelectric conversion element, an amplification transistor that amplifies the electrical signal output from the photoelectric conversion element, and a selection transistor that outputs the amplified electrical signal to the signal line,
The amplification transistor is a thin film transistor, the thin film transistor has a first control electrode and a second control electrode,
An imaging device including an adjustment voltage generation unit that generates and applies an adjustment voltage for each pixel to adjust a threshold value of the thin film transistor to one of the first control electrode and the second control electrode. The imaging device according to claim 1, wherein each of the plurality of signal lines includes a load transistor formed of a thin film transistor. The load transistor has a third control electrode and a fourth control electrode,
When the adjustment voltage is a first adjustment voltage, a second adjustment voltage for adjusting the threshold value of the load transistor is applied to one of the third control electrode and the fourth control electrode for each signal line. The imaging device according to claim 2, further comprising an adjustment voltage application unit that applies an adjustment voltage. comprising a scanning circuit section that sequentially selects a plurality of pixel rows of the pixel array and outputs signals from the pixel array to the plurality of signal lines,
2. The adjusting voltage generating section applies the adjusting voltage to each amplification transistor of the one pixel row at the same timing as a row selection period in which the scanning circuit section selects one pixel row of the pixel array. 3. The imaging device according to any one of 3. comprising a scanning circuit section that sequentially selects a plurality of pixel rows of the pixel array and outputs signals from the pixel array to the plurality of signal lines,
3. The adjustment voltage applying section applies the second adjustment voltage to the load transistor of the signal line at the same timing as a row selection period in which the scanning circuit section selects one pixel row of the pixel array. The imaging device described in . A radiation imaging device comprising the imaging device according to any one of claims 1 to 5 and a scintillator provided on at least the photoelectric conversion element and converting radiation into light.

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