JP7391574B2 - 半導体装置の製造方法および半導体装置 - Google Patents

半導体装置の製造方法および半導体装置 Download PDF

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JP7391574B2
JP7391574B2 JP2019157290A JP2019157290A JP7391574B2 JP 7391574 B2 JP7391574 B2 JP 7391574B2 JP 2019157290 A JP2019157290 A JP 2019157290A JP 2019157290 A JP2019157290 A JP 2019157290A JP 7391574 B2 JP7391574 B2 JP 7391574B2
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chip
substrate
semiconductor device
semiconductor
manufacturing
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JP2021034702A5 (https=
JP2021034702A (ja
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信一郎 渡辺
庸一 深谷
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Canon Inc
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Canon Inc
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Priority to JP2019157290A priority Critical patent/JP7391574B2/ja
Priority to US17/002,189 priority patent/US11444055B2/en
Publication of JP2021034702A publication Critical patent/JP2021034702A/ja
Priority to US17/885,445 priority patent/US11948910B2/en
Publication of JP2021034702A5 publication Critical patent/JP2021034702A5/ja
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    • HELECTRICITY
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    • H10W20/01Manufacture or treatment
    • H10W20/021Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
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    • H10W20/021Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • HELECTRICITY
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    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211Through-semiconductor vias, e.g. TSVs
    • H10W20/213Cross-sectional shapes or dispositions
    • H10W20/2134TSVs extending from the semiconductor wafer into back-end-of-line layers
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    • H10W70/093Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
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    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • H10W70/652Cross-sectional shapes
    • H10W70/6523Cross-sectional shapes for connecting to pads at different heights at the same side of the package substrate, interposer or RDL
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    • H10W72/07304Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
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    • H10W72/07337Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H10W72/07338Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy hardening the adhesive by curing, e.g. thermosetting
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JP2019157290A 2019-08-29 2019-08-29 半導体装置の製造方法および半導体装置 Active JP7391574B2 (ja)

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Application Number Priority Date Filing Date Title
JP2019157290A JP7391574B2 (ja) 2019-08-29 2019-08-29 半導体装置の製造方法および半導体装置
US17/002,189 US11444055B2 (en) 2019-08-29 2020-08-25 Manufacturing method of semiconductor apparatus and semiconductor apparatus
US17/885,445 US11948910B2 (en) 2019-08-29 2022-08-10 Manufacturing method of semiconductor apparatus and semiconductor apparatus

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JP2019157290A JP7391574B2 (ja) 2019-08-29 2019-08-29 半導体装置の製造方法および半導体装置

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JP2021034702A5 JP2021034702A5 (https=) 2022-08-30
JP7391574B2 true JP7391574B2 (ja) 2023-12-05

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US12388039B2 (en) * 2022-04-11 2025-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC comprising semiconductor substrates with different bandgaps

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Publication number Priority date Publication date Assignee Title
JP2006517344A (ja) 2003-02-07 2006-07-20 ジプトロニクス・インコーポレイテッド 室温金属直接ボンディング
JP2009164314A (ja) 2007-12-30 2009-07-23 Fujikura Ltd 貼り合わせ基板および貼り合せ基板を用いた半導体装置の製造方法
JP2013065761A (ja) 2011-09-20 2013-04-11 Toshiba Corp 半導体装置の製造方法および半導体装置の製造装置
WO2015040798A1 (ja) 2013-09-20 2015-03-26 パナソニックIpマネジメント株式会社 半導体装置及びその製造方法
WO2018194030A1 (ja) 2017-04-19 2018-10-25 ソニーセミコンダクタソリューションズ株式会社 半導体素子およびその製造方法、並びに電子機器

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Publication number Priority date Publication date Assignee Title
JPH0536966A (ja) 1991-07-19 1993-02-12 Fujitsu Ltd 半導体装置
CN102290425B (zh) 2004-08-20 2014-04-02 Kamiyacho知识产权控股公司 具有三维层叠结构的半导体器件的制造方法
JP6904017B2 (ja) 2017-04-06 2021-07-14 富士通株式会社 撮像素子及び撮像装置
KR102467845B1 (ko) * 2017-10-24 2022-11-16 삼성전자주식회사 적층형 씨모스 이미지 센서
KR102823598B1 (ko) * 2019-06-26 2025-06-23 소니 세미컨덕터 솔루션즈 가부시키가이샤 고체 촬상 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006517344A (ja) 2003-02-07 2006-07-20 ジプトロニクス・インコーポレイテッド 室温金属直接ボンディング
JP2009164314A (ja) 2007-12-30 2009-07-23 Fujikura Ltd 貼り合わせ基板および貼り合せ基板を用いた半導体装置の製造方法
JP2013065761A (ja) 2011-09-20 2013-04-11 Toshiba Corp 半導体装置の製造方法および半導体装置の製造装置
WO2015040798A1 (ja) 2013-09-20 2015-03-26 パナソニックIpマネジメント株式会社 半導体装置及びその製造方法
WO2018194030A1 (ja) 2017-04-19 2018-10-25 ソニーセミコンダクタソリューションズ株式会社 半導体素子およびその製造方法、並びに電子機器

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US11948910B2 (en) 2024-04-02
US11444055B2 (en) 2022-09-13
US20210066241A1 (en) 2021-03-04
JP2021034702A (ja) 2021-03-01
US20220384387A1 (en) 2022-12-01

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