JP7356887B2 - 誤り訂正符号加速装置及びシステム - Google Patents

誤り訂正符号加速装置及びシステム Download PDF

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Publication number
JP7356887B2
JP7356887B2 JP2019222969A JP2019222969A JP7356887B2 JP 7356887 B2 JP7356887 B2 JP 7356887B2 JP 2019222969 A JP2019222969 A JP 2019222969A JP 2019222969 A JP2019222969 A JP 2019222969A JP 7356887 B2 JP7356887 B2 JP 7356887B2
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Prior art keywords
processing device
error correction
data elements
data
correction code
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JP2019222969A
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Japanese (ja)
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JP2020095722A5 (enExample
JP2020095722A (ja
Inventor
冕 秦
周 桓 李
ピチュマニ レカー
亮 ソク 奇
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/1096—Parity calculation or recalculation after configuration or reconfiguration of the system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/079—Root cause analysis, i.e. error or fault diagnosis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1032—Simple parity
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009—Thread control instructions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6575—Implementations based on combinatorial logic, e.g. Boolean circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Probability & Statistics with Applications (AREA)
  • Human Computer Interaction (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP2019222969A 2018-12-14 2019-12-10 誤り訂正符号加速装置及びシステム Active JP7356887B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862780185P 2018-12-14 2018-12-14
US62/780,185 2018-12-14
US16/271,777 2019-02-08
US16/271,777 US11061772B2 (en) 2018-12-14 2019-02-08 FPGA acceleration system for MSR codes

Publications (3)

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JP2020095722A JP2020095722A (ja) 2020-06-18
JP2020095722A5 JP2020095722A5 (enExample) 2022-12-13
JP7356887B2 true JP7356887B2 (ja) 2023-10-05

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JP2019222969A Active JP7356887B2 (ja) 2018-12-14 2019-12-10 誤り訂正符号加速装置及びシステム

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US (3) US11061772B2 (enExample)
JP (1) JP7356887B2 (enExample)
KR (1) KR102491112B1 (enExample)
CN (1) CN111324479B (enExample)
TW (1) TWI791891B (enExample)

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US10949301B2 (en) * 2011-06-06 2021-03-16 Pure Storage, Inc. Pre-positioning pre-stored content in a content distribution system
WO2018176238A1 (en) * 2017-03-28 2018-10-04 Intel Corporation Technologies for hybrid field-programmable gate array-application-specific integrated circuit code acceleration
US11061772B2 (en) * 2018-12-14 2021-07-13 Samsung Electronics Co., Ltd. FPGA acceleration system for MSR codes
US11934330B2 (en) 2020-05-08 2024-03-19 Intel Corporation Memory allocation for distributed processing devices
US11568089B2 (en) * 2020-08-31 2023-01-31 Frontiir Pte Ltd. Offloading operations from a primary processing device to a secondary processing device
US11868777B2 (en) 2020-12-16 2024-01-09 Advanced Micro Devices, Inc. Processor-guided execution of offloaded instructions using fixed function operations
US12073251B2 (en) * 2020-12-29 2024-08-27 Advanced Micro Devices, Inc. Offloading computations from a processor to remote execution logic
US11625249B2 (en) 2020-12-29 2023-04-11 Advanced Micro Devices, Inc. Preserving memory ordering between offloaded instructions and non-offloaded instructions
US12468474B2 (en) * 2021-11-15 2025-11-11 Samsung Electronics Co., Ltd. Storage device and method performing processing operation requested by host
US12197378B2 (en) 2022-06-01 2025-01-14 Advanced Micro Devices, Inc. Method and apparatus to expedite system services using processing-in-memory (PIM)
US12050531B2 (en) 2022-09-26 2024-07-30 Advanced Micro Devices, Inc. Data compression and decompression for processing in memory
US12147338B2 (en) 2022-12-27 2024-11-19 Advanced Micro Devices, Inc. Leveraging processing in memory registers as victim buffers
US12265470B1 (en) 2023-09-29 2025-04-01 Advanced Micro Devices, Inc. Bypassing cache directory lookups for processing-in-memory instructions
US12455826B2 (en) 2024-03-29 2025-10-28 Advanced Micro Devices, Inc. Dynamic caching policies for processing-in-memory

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US20110239064A1 (en) 2010-03-24 2011-09-29 Apple Inc. Management of a non-volatile memory based on test quality
US20140317222A1 (en) 2012-01-13 2014-10-23 Hui Li Data Storage Method, Device and Distributed Network Storage System
US20170102899A1 (en) 2010-02-26 2017-04-13 Apple Inc. Data partitioning scheme for non-volatile memories
US20180300201A1 (en) 2017-04-17 2018-10-18 Intel Corporation Bypassing error correction code (ecc) processing based on software hint

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US7673222B2 (en) 2005-07-15 2010-03-02 Mediatek Incorporation Error-correcting apparatus including multiple error-correcting modules functioning in parallel and related method
CN102272730B (zh) * 2008-10-09 2017-05-24 美光科技公司 经虚拟化错误校正码nand
JP5422974B2 (ja) 2008-11-18 2014-02-19 富士通株式会社 誤り判定回路及び共有メモリシステム
US9647698B2 (en) 2013-02-26 2017-05-09 Peking University Shenzhen Graduate School Method for encoding MSR (minimum-storage regenerating) codes and repairing storage nodes
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US20170102899A1 (en) 2010-02-26 2017-04-13 Apple Inc. Data partitioning scheme for non-volatile memories
US20110239064A1 (en) 2010-03-24 2011-09-29 Apple Inc. Management of a non-volatile memory based on test quality
US20140317222A1 (en) 2012-01-13 2014-10-23 Hui Li Data Storage Method, Device and Distributed Network Storage System
US20180300201A1 (en) 2017-04-17 2018-10-18 Intel Corporation Bypassing error correction code (ecc) processing based on software hint

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Publication number Publication date
US12117903B2 (en) 2024-10-15
CN111324479B (zh) 2022-08-09
US11061772B2 (en) 2021-07-13
KR102491112B1 (ko) 2023-01-20
TWI791891B (zh) 2023-02-11
US20200192757A1 (en) 2020-06-18
CN111324479A (zh) 2020-06-23
TW202026871A (zh) 2020-07-16
KR20200073978A (ko) 2020-06-24
US20230367675A1 (en) 2023-11-16
US11726876B2 (en) 2023-08-15
JP2020095722A (ja) 2020-06-18
US20210334162A1 (en) 2021-10-28

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