JP2020095722A5 - - Google Patents

Download PDF

Info

Publication number
JP2020095722A5
JP2020095722A5 JP2019222969A JP2019222969A JP2020095722A5 JP 2020095722 A5 JP2020095722 A5 JP 2020095722A5 JP 2019222969 A JP2019222969 A JP 2019222969A JP 2019222969 A JP2019222969 A JP 2019222969A JP 2020095722 A5 JP2020095722 A5 JP 2020095722A5
Authority
JP
Japan
Prior art keywords
data elements
error correction
error
processing unit
correction code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2019222969A
Other languages
English (en)
Japanese (ja)
Other versions
JP7356887B2 (ja
JP2020095722A (ja
Filing date
Publication date
Priority claimed from US16/271,777 external-priority patent/US11061772B2/en
Application filed filed Critical
Publication of JP2020095722A publication Critical patent/JP2020095722A/ja
Publication of JP2020095722A5 publication Critical patent/JP2020095722A5/ja
Application granted granted Critical
Publication of JP7356887B2 publication Critical patent/JP7356887B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2019222969A 2018-12-14 2019-12-10 誤り訂正符号加速装置及びシステム Active JP7356887B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862780185P 2018-12-14 2018-12-14
US62/780,185 2018-12-14
US16/271,777 2019-02-08
US16/271,777 US11061772B2 (en) 2018-12-14 2019-02-08 FPGA acceleration system for MSR codes

Publications (3)

Publication Number Publication Date
JP2020095722A JP2020095722A (ja) 2020-06-18
JP2020095722A5 true JP2020095722A5 (enExample) 2022-12-13
JP7356887B2 JP7356887B2 (ja) 2023-10-05

Family

ID=71072501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019222969A Active JP7356887B2 (ja) 2018-12-14 2019-12-10 誤り訂正符号加速装置及びシステム

Country Status (5)

Country Link
US (3) US11061772B2 (enExample)
JP (1) JP7356887B2 (enExample)
KR (1) KR102491112B1 (enExample)
CN (1) CN111324479B (enExample)
TW (1) TWI791891B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10949301B2 (en) * 2011-06-06 2021-03-16 Pure Storage, Inc. Pre-positioning pre-stored content in a content distribution system
WO2018176238A1 (en) * 2017-03-28 2018-10-04 Intel Corporation Technologies for hybrid field-programmable gate array-application-specific integrated circuit code acceleration
US11061772B2 (en) * 2018-12-14 2021-07-13 Samsung Electronics Co., Ltd. FPGA acceleration system for MSR codes
US11934330B2 (en) 2020-05-08 2024-03-19 Intel Corporation Memory allocation for distributed processing devices
US11568089B2 (en) * 2020-08-31 2023-01-31 Frontiir Pte Ltd. Offloading operations from a primary processing device to a secondary processing device
US11868777B2 (en) 2020-12-16 2024-01-09 Advanced Micro Devices, Inc. Processor-guided execution of offloaded instructions using fixed function operations
US12073251B2 (en) * 2020-12-29 2024-08-27 Advanced Micro Devices, Inc. Offloading computations from a processor to remote execution logic
US11625249B2 (en) 2020-12-29 2023-04-11 Advanced Micro Devices, Inc. Preserving memory ordering between offloaded instructions and non-offloaded instructions
US12468474B2 (en) * 2021-11-15 2025-11-11 Samsung Electronics Co., Ltd. Storage device and method performing processing operation requested by host
US12197378B2 (en) 2022-06-01 2025-01-14 Advanced Micro Devices, Inc. Method and apparatus to expedite system services using processing-in-memory (PIM)
US12050531B2 (en) 2022-09-26 2024-07-30 Advanced Micro Devices, Inc. Data compression and decompression for processing in memory
US12147338B2 (en) 2022-12-27 2024-11-19 Advanced Micro Devices, Inc. Leveraging processing in memory registers as victim buffers
US12265470B1 (en) 2023-09-29 2025-04-01 Advanced Micro Devices, Inc. Bypassing cache directory lookups for processing-in-memory instructions
US12455826B2 (en) 2024-03-29 2025-10-28 Advanced Micro Devices, Inc. Dynamic caching policies for processing-in-memory

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2695195B2 (ja) 1988-09-02 1997-12-24 三菱電機株式会社 誤り訂正回路
US7673222B2 (en) 2005-07-15 2010-03-02 Mediatek Incorporation Error-correcting apparatus including multiple error-correcting modules functioning in parallel and related method
CN102272730B (zh) * 2008-10-09 2017-05-24 美光科技公司 经虚拟化错误校正码nand
JP5422974B2 (ja) 2008-11-18 2014-02-19 富士通株式会社 誤り判定回路及び共有メモリシステム
US8356137B2 (en) * 2010-02-26 2013-01-15 Apple Inc. Data storage scheme for non-volatile memories based on data priority
US8650446B2 (en) * 2010-03-24 2014-02-11 Apple Inc. Management of a non-volatile memory based on test quality
CN102624866B (zh) * 2012-01-13 2014-08-20 北京大学深圳研究生院 一种存储数据的方法、装置及分布式网络存储系统
US9647698B2 (en) 2013-02-26 2017-05-09 Peking University Shenzhen Graduate School Method for encoding MSR (minimum-storage regenerating) codes and repairing storage nodes
US9021188B1 (en) 2013-03-15 2015-04-28 Virident Systems Inc. Small block write operations in non-volatile memory systems
US9710330B2 (en) 2014-10-15 2017-07-18 Empire Technology Development Llc Partial cloud data storage
US9547458B2 (en) 2014-12-24 2017-01-17 International Business Machines Corporation Intra-rack and inter-rack erasure code distribution
US10007587B2 (en) 2015-09-18 2018-06-26 Qualcomm Incorporated Systems and methods for pre-generation and pre-storage of repair fragments in storage systems
US20170179979A1 (en) 2015-12-18 2017-06-22 Netapp, Inc. Systems and Methods for Minimum Storage Regeneration Erasure Code Construction Using r-Ary Trees
US10452477B2 (en) 2016-08-26 2019-10-22 Netapp, Inc. Multiple node repair using high rate minimum storage regeneration erasure code
US10261859B2 (en) * 2017-04-17 2019-04-16 Intel Corporation Bypassing error correction code (ECC) processing based on software hint
US11061772B2 (en) * 2018-12-14 2021-07-13 Samsung Electronics Co., Ltd. FPGA acceleration system for MSR codes

Similar Documents

Publication Publication Date Title
JP2020095722A5 (enExample)
KR102242872B1 (ko) 비휘발성 메모리 내의 복구 알고리즘
US8301986B2 (en) Memory system and method for providing error correction
US11263081B2 (en) Checkpointing
CN111324479B (zh) 用于错误修正代码的加速的装置及系统
US8904260B2 (en) Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme
CN105659332B (zh) 存储器中的错误校正
KR101522509B1 (ko) 갈루아 필드 산술을 사용하는 효율적이고 스케일링가능한 순환 중복 검사 회로
US7562283B2 (en) Systems and methods for error correction using binary coded hexidecimal or hamming decoding
KR101374958B1 (ko) 프로그램 가능한 ｃｒｃ 계산을 위한 명령어 집합 구조
US9075739B2 (en) Storage device
CN104658609B (zh) 用于存储器系统的纠错码分布的方法和系统
CN111427717B (zh) 用于在存储器系统中编码和解码数据的方法和装置
US8769390B2 (en) Apparatus and method for processing operations in parallel using a single instruction multiple data processor
US7797612B2 (en) Storage accelerator
CN116670652A (zh) 在远程执行设备中提供基于主机的错误检测能力
KR20120110450A (ko) 에러 정정 디코더 및 그것의 에러 정정 방법
EP3835960A2 (en) Storage controller for correcting error, storage device including the same, and operating method thereof
CN108140016B (zh) 确定矩阵-向量相乘的运算最优序列的优化器
CN108665940B (zh) Ecc编码电路、解码电路以及存储器控制器
Marov et al. Optimization of RAID erasure coding algorithms for Intel Xeon Phi
US11768735B2 (en) Checkpointing
Haiyang Designing high-performance erasure coding schemes for next-generation storage systems
Braun et al. Algorithm-based fault tolerance for many-core architectures
CN105812448A (zh) 一种云存储系统的纠删编码方法