JP7354838B2 - Semiconductor device, wireless communication device, sensor control device, and method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, a wireless communication device, a sensor control device, and a method for manufacturing a semiconductor device.

In recent years, development of wireless communication systems (ie, RFID systems) using RFID (Radio Frequency IDentification) technology has been progressing as non-contact tags. In an RFID system, wireless communication is performed between a wireless transceiver called a reader/writer and an RFID tag.

RFID tags are expected to be used for various purposes such as logistics management, product management, and shoplifting prevention, and are beginning to be introduced in some applications such as IC cards such as transportation cards and product tags. The RFID tag has an IC chip and an antenna for wireless communication with a reader/writer. An antenna installed within the RFID tag receives a radio signal transmitted from the reader/writer, and a drive circuit within the IC chip operates.

RFID tags are expected to be used in all kinds of products. To achieve this, it is necessary to reduce the manufacturing cost of RFID tags, and we are considering moving away from manufacturing processes that use vacuum and high temperatures, and instead using coating and printing technologies to create flexible and inexpensive RFID tag manufacturing processes. has been done.

For example, a field effect transistor (hereinafter referred to as FET) using an organic semiconductor with excellent moldability as a semiconductor layer has been proposed for a drive circuit in an IC chip. By using organic semiconductors as inks, it becomes possible to form circuit patterns such as FETs directly on flexible substrates using inkjet technology, screening technology, etc. Therefore, instead of conventional inorganic semiconductors, FETs using carbon nanotubes (CNTs) and organic semiconductors are being actively studied, and circuits using them are also being studied (see, for example, Patent Document 1).

A drive circuit in an RFID tag is generally configured with a complementary circuit consisting of a p-type FET and an n-type FET in order to suppress its power consumption. However, it is known that FETs using CNTs normally exhibit characteristics of p-type semiconductor devices in the atmosphere. Furthermore, FETs using organic semiconductors are single channel. Therefore, a complementary circuit cannot be constructed using the same material, and materials must be selected separately for the p-type FET and the n-type FET. Due to this, the manufacturing process of the complementary circuit becomes complicated, resulting in problems of decreased production efficiency and increased manufacturing cost of RFID tags.

Therefore, for example, in a FET using CNT, after forming a p-type FET, a layer of an n-type modified polymer is formed on the semiconductor layer to modify the p-type characteristics to the n-type characteristics. , an n-type FET is formed, and a complementary circuit is realized in a relatively easy process (for example, see Patent Document 2).

International Publication No. 2009/139339 International Publication No. 2005/57665

However, as mentioned above, complementary circuits require FETs with different conductivity types, p-type FET and n-type FET, and compared to an IC chip formed of only FETs of the same conductivity type, There was a problem in that the chip area increased, leading to an increase in cost.

For example, in the conventional technique described in Patent Document 2, when an n-type FET is formed on a base material, a layer of an n-type modified polymer having a relatively thicker film thickness than a source electrode or a drain electrode is required. Therefore, compared to the minimum area of the base material region required to form a p-type FET including a source electrode, a drain electrode, a semiconductor layer, a gate electrode, etc., the formation of an n-type FET using an n-type modified polymer requires more A large amount of substrate area was required.

Further, in Patent Document 2, a layer of an n-type modified polymer is formed by an inkjet method. For this reason, it is necessary to selectively apply the n-type modified polymer to the FET whose characteristics are to be modified, which not only increases the time required for the coating process, but also requires measures to prevent misalignment and variations in the coating position. In addition, it was necessary to secure a sufficient space between the FET to which the polymer is applied and other FETs. In particular, in Patent Document 2, a layer of an n-type modified polymer is formed on the FET, and then CNTs are dropped onto the layer of the n-type modified polymer to make the FET an n-type FET. In this case, since the n-type modified polymer on the FET has conductivity or semiconductivity, the space between adjacent FETs must be spaced to prevent short circuits between each FET, regardless of the conductivity type of the FET. It was necessary to secure sufficient capacity.

That is, in a complementary circuit in which an n-type FET 20 and a p-type FET 30 are arranged on a base material 10, such as the conventional semiconductor device 11 illustrated in FIG. By covering the FET with 50, it exhibits n-type characteristics. The n-type modified polymer 50 is dropped onto the FET on the base material 10 by an inkjet method, so that the n-type modified polymer 50 has a circular planar shape when viewed from a plane perpendicular to the surface of the base material 10 . In order to prevent the layer of n-type modified polymer 50 from touching FETs to which n-type modified polymer 50 should not be applied, the distance between n-type FET 20 and p-type FET 30, and the distance between each adjacent It was necessary to maintain a sufficient distance between the n-type FETs 20.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and is aimed at increasing chip area and manufacturing costs in circuits that require multiple types of semiconductor elements with different electrical characteristics, such as complementary circuits. A first object of the present invention is to provide a semiconductor device capable of suppressing the above. A second object of the present invention is to provide a wireless communication device and a sensor control device using the semiconductor device, and a method for manufacturing the semiconductor device.

In order to solve the above-mentioned problems and achieve the objects, a semiconductor device according to the present invention includes, on a base material, at least a first region in which two or more semiconductor elements are arranged, and a first region in which at least one semiconductor element is arranged. a second region disposed, wherein the semiconductor element in the first region includes a source electrode in the first region, a drain electrode in the first region, and a semiconductor device in the first region. a gate electrode in the first region, a semiconductor layer in the first region in contact with a source electrode in the first region and a drain electrode in the first region, and a semiconductor layer in the first region and a gate in the first region. The base material includes a gate insulating layer in the first region that insulates the gate insulating layer from the electrode, and a second insulating layer in contact with the semiconductor layer in the first region at a position different from that of the gate insulating layer in the first region. The semiconductor element in the second region includes a source electrode in the second region, a drain electrode in the second region, a gate electrode in the second region, and a source electrode in the second region. a semiconductor layer in the second region that is in contact with a drain electrode in the second region; and a gate insulation in the second region that insulates the semiconductor layer in the second region and the gate electrode in the second region. a layer on the substrate, the electrical conductivity of the semiconductor element in the first region is different from the electrical conductivity of the semiconductor element in the second region due to the second insulating layer; The insulating layer is characterized in that the insulating layer is continuously arranged over two or more semiconductor elements in the first region.

Further, in the above invention, the semiconductor device according to the present invention further includes a third region in which two or more semiconductor elements are arranged on the base material, and the semiconductor elements in the third region are arranged in the third region. a source electrode in the third region, a drain electrode in the third region, a gate electrode in the third region, and a third region in contact with the source electrode in the third region and the drain electrode in the third region. a semiconductor layer in the third region, and a gate insulating layer in the third region that insulates the semiconductor layer in the third region and the gate electrode in the third region, and a gate insulating layer in the third region at a different position. and a third insulating layer in contact with the semiconductor layer in the third region, wherein the composition forming the second insulating layer and the composition forming the third insulating layer are different from each other. shall be.

Further, in the semiconductor device according to the present invention, in the above-described invention, a plurality of the second insulating layers are arranged in a shape having long and short lengths in the first region, and a plurality of the second insulating layers have long and short lengths. The ulnar directions are each in the same direction.

Further, in the semiconductor device according to the present invention, in the above invention, the second insulating layer and the third insulating layer are each arranged to have a long and short shape, and the second insulating layer is arranged in a longitudinal direction of the second insulating layer. and the longitudinal direction of the third insulating layer are the same direction.

Further, in the semiconductor device according to the present invention, in the above invention, the semiconductor layer on the base material is made of one or more semiconductor materials selected from carbon nanotubes, carbon nanocoils, fullerenes, graphene, and nanodiamonds. It is characterized by containing.

Moreover, the semiconductor device according to the present invention is characterized in that, in the above invention, the semiconductor layer on the base material contains carbon nanotubes.

Further, the semiconductor device according to the present invention is characterized in that, in the above invention, the second insulating layer contains an electron-donating compound having at least one selected from nitrogen atoms and phosphorus atoms. shall be.

Further, in the semiconductor device according to the present invention, in the above invention, the difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is the difference in threshold voltage of the transistor. It is characterized by:

Further, in the semiconductor device according to the present invention, in the above invention, the difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is a difference in conductivity type of the transistor. , is characterized by.

Further, in the semiconductor device according to the present invention, in the above invention, the difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is the difference in electrical conductivity with respect to ambient temperature. It is characterized by:

Further, in the semiconductor device according to the present invention, in the above invention, the difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is the difference in electrical conductivity with respect to ambient humidity. It is characterized by:

Further, in the semiconductor device according to the present invention, in the above invention, the difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is a difference in electrical conductivity with respect to the wavelength of incident light. It is characterized by being different.

Further, in the semiconductor device according to the present invention, in the above invention, the difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is the difference in electrical conductivity with respect to the amount of incident light. It is characterized by:

Further, in the semiconductor device according to the present invention, in the above invention, the difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is the difference in electrical conductivity with respect to the amount of oxygen. It is characterized by:

Further, in the semiconductor device according to the present invention, in the above invention, the electrical conductivity of the semiconductor element in the third region is compatible with the electrical conductivity of the semiconductor element in the second region due to the third insulating layer. However, the difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is the difference in conductivity type of the transistor, and the difference in electrical conductivity between the semiconductor element in the third region and the semiconductor element in the second region The difference in electrical conductivity between the second region and the semiconductor element is the difference in threshold voltage of the transistor.

Further, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device for manufacturing the semiconductor device according to any one of the above inventions, comprising: a composition for forming the second insulating layer; The method is characterized in that it includes a coating step of continuously coating two or more semiconductor elements in the first region.

Further, in the method for manufacturing a semiconductor device according to the present invention, in the above invention, the coating step is performed by any one of an inkjet method, a nozzle coating method, a screen printing method, an offset printing method, or a drop cast coating method. The second insulating layer is formed by applying a composition.

Further, a wireless communication device according to the present invention is characterized in that it includes the semiconductor device according to any one of the above inventions.

Further, a sensor control device according to the present invention is characterized in that it includes the semiconductor device according to any one of the above inventions.

According to the present invention, since the chip area of the complementary circuit is small and the time required for the manufacturing process can be shortened, it is possible to suppress an increase in manufacturing costs and provide an inexpensive and compact semiconductor device. Become. Further, according to the present invention, it is possible to provide a wireless communication device and a sensor control device using such a semiconductor device.

FIG. 1 is a schematic plan view schematically showing a configuration example of a semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a schematic cross-sectional view showing a configuration example of the semiconductor device shown in FIG. 1 taken along the line AB. FIG. 3 is a schematic plan view schematically showing a configuration example of a semiconductor device according to Embodiment 2 of the present invention. FIG. 4 is a schematic circuit diagram showing a configuration example of a charge pump circuit to which a semiconductor device according to Embodiment 2 of the present invention is applied. FIG. 5 is a schematic plan view schematically showing a configuration example of a semiconductor device according to Embodiment 3 of the present invention. FIG. 6 is a schematic plan view schematically showing a configuration example of a semiconductor device according to Embodiment 4 of the present invention. FIG. 7 is a schematic plan view schematically showing a configuration example of a semiconductor device according to Embodiment 5 of the present invention. FIG. 8 is a schematic plan view schematically showing a configuration example of a semiconductor device according to Embodiment 6 of the present invention. FIG. 9 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the present invention. FIG. 10 is a schematic block diagram showing a configuration example of a wireless communication device including a semiconductor device according to the present invention. FIG. 11 is a schematic plan view showing a configuration example of a ring oscillator including a semiconductor device according to Embodiment 1 of the present invention. FIG. 12 is a schematic plan view showing a configuration example of a frequency dividing circuit including a semiconductor device according to Embodiment 1 of the present invention. FIG. 13A is a schematic plan view showing a configuration example of a semiconductor device according to a comparative example with respect to the present invention. FIG. 13B is a schematic plan view showing a configuration example of a semiconductor device according to Example 3 of the present invention. FIG. 14 is a schematic plan view illustrating a conventional semiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments (hereinafter referred to as "embodiments") for implementing a semiconductor device, a wireless communication device, a sensor control device, and a method for manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings. Note that the drawings are schematic. Further, the present invention is not limited to the embodiments described below.

<Semiconductor device>
(Embodiment 1)
FIG. 1 is a schematic plan view schematically showing a configuration example of a semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a schematic cross-sectional view showing a configuration example of the semiconductor device shown in FIG. 1 taken along the line AB. The semiconductor device 101 according to Embodiment 1 of the present invention includes, on a base material, at least a first region in which two or more semiconductor elements are arranged, and a second region in which one or more semiconductor elements are arranged. , is an example of a semiconductor device including the following. In the first embodiment, for example, as shown in FIG. 1, a semiconductor device 101 includes a base material 100 including a first region 110 and a second region 120 as a plurality of regions on the surface of the base material. Further, the semiconductor device 101 includes a plurality of FETs 200 (eight in FIG. 1) provided with the second insulating layer 500 in the first region 110 on the base material 100, and in the second region 120, One or more FETs 300 (eight in FIG. 1) are provided without the second insulating layer 500.

Specifically, in the semiconductor device 101 shown in FIG. 1, the base material 100 is a film base material made of polyethylene terephthalate (PET) or the like. On this base material 100, a first region 110 in which eight FETs 200 covered with a second insulating layer 500 are arranged, and eight FETs 300 without a second insulating layer 500 are arranged. There is a second region 120 where the The first region 110 and the second region 120 are mutually different regions on the base material surface of the base material 100, and are adjacent to each other, as shown in FIG. 1, for example. As shown in FIG. 1, in a portion of the first region 110 where at least a plurality of FETs 200 are formed, a second insulating layer 500 is provided to cover the plurality of FETs 200.

FET 200 is an example of a semiconductor element in first region 110, and in the first embodiment is an FET having n-type characteristics (n-type FET). In detail, as shown in FIGS. 1 and 2, each of the eight FETs 200 has a source electrode 210 in the first region 110, a drain electrode 220 in the first region 110, and a gate electrode in the first region 110. An electrode 230, a gate insulating layer 250 in the first region 110, a semiconductor layer 270 in the first region 110, and a second insulating layer 500 are provided on the base material 100. Gate insulating layer 250 covers at least a portion of gate electrode 230, thereby electrically insulating semiconductor layer 270 and gate electrode 230. The semiconductor layer 270 is in contact with the source electrode 210 and the drain electrode 220. In the first embodiment, the semiconductor layer 270 contacts both the source electrode 210 and the drain electrode 220 at least partially. The second insulating layer 500 contacts the semiconductor layer 270 at a different position from the gate insulating layer 250 in each of the eight FETs 200.

In particular, in the first embodiment, the second insulating layer 500 is arranged continuously over two or more (eight in FIG. 1) of the FETs 200 in the first region 110, as shown in FIGS. There is. The second insulating layer 500 disposed in the first region 110 is in contact with the semiconductor layer 270 at a position different from the gate insulating layer 250 for all eight FETs 200, so that the FET 200 The original p-type characteristics are modified to n-type characteristics. That is, the FET 200 having the second insulating layer 500 has n-type characteristics.

FET 300 is an example of a semiconductor element in second region 120, and in the first embodiment is a FET having p-type characteristics (p-type FET). In detail, as shown in FIGS. 1 and 2, each of the eight FETs 300 has a source electrode 310 in the second region 120, a drain electrode 320 in the second region 120, and a gate electrode in the second region 120. An electrode 330, a gate insulating layer 350 in the second region 120, and a semiconductor layer 370 in the second region 120 are provided on the base material 100. Gate insulating layer 350 covers at least a portion of gate electrode 330, thereby electrically insulating semiconductor layer 370 and gate electrode 330. The semiconductor layer 370 is in contact with the source electrode 310 and the drain electrode 320. In the first embodiment, the semiconductor layer 370 is in contact with both the source electrode 310 and the drain electrode 320 at least in part.

Furthermore, focusing on the electrical conductivity of each FET 200 and 300 in the first embodiment, the electrical conductivity of FET 200 in the first region 110 is lowered by the electrical conductivity of FET 300 in the second region 120 due to the second insulating layer 500. different from gender. Specifically, FET 200 in first region 110 has n-type characteristics, and FET 300 in second region 120 has p-type characteristics. That is, the difference in electrical conductivity between the FET 200 in the first region 110 and the FET 300 in the second region 120 is the difference in conductivity type of the transistors.

In the present invention, the number of n-type FETs 200 and p-type FETs 300 included in the semiconductor device 101 is not limited to eight as described above. The number of n-type FETs 200 formed in the first region 110 may be two or more, and the number of p-type FETs 300 formed in the second region 120 may be one or more. . Further, the arrangement of the plurality of FETs 200 in the first region 110 is not limited to the arrangement of two rows and four columns illustrated in FIG. 1, but may be arranged in one or more rows and one or more columns. A multi-row arrangement is preferred. When these multiple FETs 200 are arranged in multiple rows and multiple columns, the number of FETs included in one row may be one or more, and the number of FETs included in one column is one. It may be more than that. Preferably, the number of FETs included in one row is plural, and the number of FETs included in one column is preferably plural. Similarly, the arrangement of the plurality of FETs 300 in the second region 120 is not limited to the 2 rows and 4 columns illustrated in FIG. 1, but may be arranged in one or more rows and one or more columns. A multi-row and multi-column arrangement is preferred.

Furthermore, the number of source electrodes 210, drain electrodes 220, and gate electrodes 230 included in one n-type FET 200 may be one or more. Similarly, each of the source electrode 310, drain electrode 320, and gate electrode 330 included in one p-type FET 300 may be one or more.

It is preferable that the source electrode 210 of the n-type FET 200 and the source electrode 310 of the p-type FET 300 be formed using the same material and the same process. Similarly, the drain electrode 220 of the n-type FET 200 and the drain electrode 320 of the p-type FET 300, the gate electrode 230 of the n-type FET 200 and the gate electrode 330 of the p-type FET 300, and the gate insulating layer 250 of the n-type FET 200 It is preferable that the gate insulating layer 350 of the p-type FET 300, the semiconductor layer 270 of the n-type FET 200, and the semiconductor layer 370 of the p-type FET 300 be formed using the same material and the same process. However, the materials and processes for forming each of these electrodes and each layer do not necessarily need to be the same as described above. These materials and processes are not particularly limited as long as desired characteristics can be obtained.

In the first embodiment, as described above, the n-type FET 200 is exemplified as the semiconductor element in the first region 110, and the p-type FET 300 is exemplified as the semiconductor element in the second region 120. That is, although the case has been exemplified in which the difference in electrical conductivity between the semiconductor element in the first region 110 and the semiconductor element in the second region 120 is a difference in conductivity type of the transistor, the present invention is not limited to this. It's not something you can do. The semiconductor element in the first region 110 may have electrical conductivity different from that of the semiconductor element in the second region 120. For example, even if the semiconductor element in the first region 110 and the semiconductor element in the second region 120 are both n-type FETs, there may be a difference in electrical conductivity between these semiconductor elements (for example, a threshold voltage of a transistor). If there is a difference in conductivity, the conductivity type does not matter.

In the first embodiment, physical connections using wiring are omitted for drain electrodes, source electrodes, and gate electrodes of a plurality of semiconductor elements formed on the base material 100. However, each drain electrode 220, 320, each source electrode 210, 310, and each gate electrode 230, 330 is electrically connected to a desired connection destination via wiring. As a result, a circuit using a plurality of semiconductor elements on the base material 100 is formed.

In the first embodiment, since the second insulating layer 500 is continuously arranged over two or more FETs 200 in the first region 110, semiconductor elements having the same electrical conductivity (for example, n-type FETs 200) are connected to each other. It becomes possible to arrange them all in the first area 110. Thereby, the size of the semiconductor element occupying the first region 110 and the size of the semiconductor element occupying the second region 120 are set to the minimum dimensions of the processing process of the source electrode, drain electrode, gate electrode, gate insulating layer, and semiconductor layer. , or can be reduced to a similar extent. As a result, without increasing the chip area of a circuit (for example, a complementary circuit) including the semiconductor element in the first region 110 and the semiconductor element in the second region 120, these semiconductor elements can be made to have different electrical conductivity. It becomes possible to efficiently form a semiconductor element having the following characteristics.

The electrode material used for the gate electrodes 230, 330, the source electrodes 210, 310, and the drain electrodes 220, 320 may be any conductive material that can be generally used as an electrode. Examples of electrode materials include indium tin oxide (ITO), gold, silver, copper, aluminum, polysilicon, conductive polymers, and carbon materials. These electrode materials may be used alone, or a plurality of electrode materials may be stacked or mixed.

Further, in the first embodiment, a film base material made of PET is illustrated as the base material 100, but the base material 100 is not limited to the above film base material, and at least the surface on which the electrode system is arranged is insulated. Any base material may be used as long as it is compatible with the base material. For example, examples of the material of the base material 100 include silicon wafer, glass, polyimide, and ceramics. Further, the base material 100 may be made of a plurality of laminated materials.

The material of the gate insulating layers 250 and 350 is not particularly limited as long as the desired insulation properties can be obtained. For example, materials for the gate insulating layers 250 and 350 include silicon oxide, alumina, hafnium oxide, polyimide, and the like. Further, although the gate insulating layers 250 and 350 are integrally formed over the first region 110 and the second region 120 on the base material 100, the gate electrode and the semiconductor layer are electrically connected to each other. It may be formed for each semiconductor element in an insulating manner.

Regarding the semiconductor layers 270 and 370, the material and formation method thereof are not particularly limited as long as desired electrical conductivity can be obtained. For example, materials for the semiconductor layers 270 and 370 include silicon nanowires, oxide semiconductor materials such as IGZO, amorphous semiconductor materials such as Cu-Sn-I, organic semiconductors, carbon materials, and the like. These materials are preferably used because they have high carrier mobility. Further, these materials are preferable from the viewpoint that a simple coating process can be applied at low cost.

Examples of organic semiconductors include polythiophenes, compounds containing a thiophene unit in the main chain, polypyrroles, polyanilines, polyacetylenes, polydiacetylenes, polycarbazoles, polyfurans, and nitrogen-containing aromatic rings as constitutional units. Polyheteroaryls, fused polycyclic aromatic compounds, heteroaromatic compounds, aromatic amine derivatives, biscarbazole derivatives, pyrazoline derivatives, stilbene compounds, hydrazone compounds, metal phthalocyanines, metal porphyrins, distyrylbenzene Examples include derivatives, aminostyryl derivatives, aromatic acetylene derivatives, fused ring tetracarboxylic acid diimides, and organic dyes. These organic semiconductors may be used alone or in combination of two or more types.

Among the organic semiconductors exemplified above, examples of polythiophenes include poly-3-hexylthiophene and polybenzothiophene. Examples of compounds containing a thiophene unit in the main chain include poly(2,5-bis(2-thienyl)-3,6-dipentadecylthieno[3,2-b]thiophene), poly(4,8 -dihexyl-2,6-bis(3-hexylthiophen-2-yl)benzo[1,2-b:4,5-b']dithiophene), poly(4-octyl-2-(3-octylthiophene-) 2-yl)thiazole), poly(5,5'-bis(4-octylthiazol-2-yl)-2,2'-bithiophene), and the like. Examples of poly(p-phenylene vinylene) include poly(p-phenylene vinylene). Examples of polyfurans include polyfuran and polybenzofuran. Examples of polyheteroaryls having a nitrogen-containing aromatic ring as a constituent unit include pyridine, quinoline, phenanthroline, oxazole, and oxadiazole. Examples of the fused polycyclic aromatic compound include anthracene, pyrene, naphthacene, pentacene, hexacene, and rubrene. Examples of the heteroaromatic compound include furan, thiophene, benzothiophene, dibenzofuran, pyridine, quinoline, phenanthroline, oxazole, oxadiazole, and the like. Examples of aromatic amine derivatives include 4,4'-bis(N-(3-methylphenyl)-N-phenylamino)biphenyl. Examples of biscarbazole derivatives include bis(N-allylcarbazole) and bis(N-alkylcarbazole). Examples of metal phthalocyanines include copper phthalocyanine. Examples of metal porphyrins include copper porphyrin. Examples of the fused ring tetracarboxylic diimides include naphthalene-1,4,5,8-tetracarboxylic diimide and perylene-3,4,9,10-tetracarboxylic diimide. Examples of organic dyes include merocyanine, phenoxazine, and rhodamine.

Further, carbon materials include carbon nanotubes, carbon nanocoils, fullerenes, graphene, nanodiamonds, and the like. In the semiconductor device 101 according to the first embodiment, the semiconductor layers 270 and 370 on the base material 100 are made of one or more semiconductor materials selected from carbon nanotubes, carbon nanocoils, fullerenes, graphene, and nanodiamonds. It is preferable to contain. These semiconductor materials (carbon materials) may be used in combination of two or more types. It is more preferable to use a carbon material as the material for the semiconductor layers 270 and 370, since this achieves high electrical characteristics due to high carrier mobility and facilitates formation by coating. In particular, it is preferable that the semiconductor layers 270 and 370 on the base material 100 contain carbon nanotubes (CNT) as the carbon material. As the CNTs included in the semiconductor layers 270 and 370, CNTs having a conjugated polymer attached to at least a portion of their surfaces are more preferable.

CNTs include single-walled CNTs in which one carbon film (graphene sheet) is wound into a cylindrical shape, two-walled CNTs in which two graphene sheets are wound in a concentric circle, and multiple graphene sheets in a concentric circle. Any of the multilayered CNTs wound around the wafer may be used. Two or more types of these single-walled CNTs, double-walled CNTs, and multi-walled CNTs may be used. Among these, from the viewpoint of exhibiting semiconductor characteristics, it is preferable to use single-layer CNTs as the CNTs. In particular, it is more preferable that the single-walled CNTs contain 90% by weight or more of semiconductor-type single-walled CNTs. More preferably, the single-walled CNTs contain 95% by weight or more of semiconductor-type single-walled CNTs.

The content ratio of semiconducting single-walled CNTs can be calculated from the absorption area ratio of visible-near infrared absorption spectra. CNTs can be obtained by methods such as an arc discharge method, a chemical vapor deposition method (CVD method), and a laser ablation method.

On the other hand, the material of the second insulating layer 500 is not particularly limited as long as it is an insulating material. Examples of the resin contained in the second insulating layer 500 include acrylic resin, methacrylic resin, olefin polymer, cycloolefin polymer, polystyrene, polysiloxane, polyimide, polycarbonate, vinyl alcohol resin, and phenol resin.

Further, the shape, size, and formation method of the second insulating layer 500 are not particularly limited as long as the second insulating layer 500 is continuously arranged over a plurality of semiconductor elements (for example, the FET 200 shown in FIG. 1) in the first region 110. For example, the shape of the second insulating layer 500 may be circular, oval, hexagonal, square, rectangular, rounded rectangle, diamond, trapezoid, convex, semiconductor, etc. Examples include a linear shape having a width equivalent to that of the element, a composite shape thereof, and the like. These shapes may be the shape of an insulating layer in which a plurality of dot-shaped resins are in contact with each other and integrated. It is more preferable that the second insulating layer 500 has a linear shape extending over a plurality of semiconductor elements from the first to third viewpoints described below. The first viewpoint is that the film thickness and line width of the second insulating layer 500 are stabilized. The second viewpoint is that variations in characteristics can be suppressed by forming a compositionally homogeneous film of the second insulating layer 500. The third viewpoint is that compared to the case where a plurality of insulating layers covering each individual semiconductor element are arranged with a desired space between them, This is from the viewpoint that the amount of overlap required for the second insulating layer 500 and its margin can be reduced in order to completely cover a plurality of semiconductor elements. Furthermore, since the second insulating layer 500 has a planar shape that covers the semiconductor elements arranged (arrayed) in multiple columns and multiple rows, the thickness of the second insulating layer 500 in both vertical and horizontal directions can be easily smoothed. It is particularly preferable from this viewpoint and from the above-mentioned first to third viewpoints. When the second insulating layer 500 has the above-described planar shape, a plurality of semiconductor elements covered by the second insulating layer 500 having the planar shape are arranged in multiple rows and columns, as illustrated for the FET 200 described above. It is preferable that In the arrangement of these plurality of semiconductor elements (arrangement of multiple rows and multiple columns), the number of semiconductor elements included in one row or one column may be one or more, but in particular, the third aspect above Therefore, it is preferable that the number of semiconductor elements included in one row and the number of semiconductor elements included in one column are both plural.

The second insulating layer 500 contains an organic compound containing a bond between carbon atoms and nitrogen atoms in order to supply carriers such as electrons and holes that are responsible for electrical conductivity to the semiconductor layer 270. It is preferable. Such an organic compound may be any organic compound, and examples thereof include amide compounds, imide compounds, urea compounds, amine compounds, imine compounds, aniline compounds, and nitrile compounds. However, the organic compounds contained in the second insulating layer 500 are not limited to these.

In particular, the second insulating layer 500 preferably contains an electron-donating compound having at least one selected from nitrogen atoms and phosphorus atoms. Since the second insulating layer 500 contains an electron-donating compound, the function of the second insulating layer 500 as an electron-donating material necessary for changing the original conductivity type (p-type) of the FET 200 to an n-type becomes greater. Become. As the electron donating compound, any organic compound may be used, but for example, amide compounds, imide compounds, urea compounds, amine compounds, imine compounds, aniline compounds, nitrile compounds, etc. are preferable.

Further, the second insulating layer 500 can also play a role in adjusting the degree of change in characteristics with respect to the environment around the semiconductor element. Therefore, when the semiconductor device 101 according to the first embodiment of the present invention is used as a sensor for detecting changes in the external environment, it is preferable that the second insulating layer 500 has the above properties. preferable.

For example, if the plurality of semiconductor elements of the semiconductor device 101 are made to have different electrical conductivity depending on the ambient temperature due to the presence or absence of the second insulating layer 500, the There will be two or more types of semiconductor elements (for example, two types of FET 200 in the first region 110 and FET 300 in the second region 120) having different electrical conductivity. In this case, the difference in electrical conductivity between the semiconductor element in the first region 110 and the semiconductor element in the second region 120 is a difference in electrical conductivity with respect to ambient temperature. With this configuration, the semiconductor device 101 can contribute to realizing a circuit with more excellent functionality, such as detecting ambient temperature and forming a circuit that operates only in a specific temperature range.

Further, when the plurality of semiconductor elements of the semiconductor device 101 are made to have different electrical conductivity depending on the ambient humidity due to the presence or absence of the second insulating layer 500, there is a There will be two or more types of semiconductor elements with different electrical conductivity. In this case, the difference in electrical conductivity between the semiconductor element in the first region 110 and the semiconductor element in the second region 120 is a difference in electrical conductivity with respect to ambient humidity. With this configuration, the semiconductor device 101 can contribute to detecting ambient humidity and realizing a circuit that operates only at a specific humidity.

Further, when the plurality of semiconductor elements of the semiconductor device 101 are made to have different electrical conductivity depending on the wavelength of externally incident light due to the presence or absence of the second insulating layer 500, There will be two or more types of semiconductor elements having different electrical conductivity with respect to the wavelength of light. In this case, the difference in electrical conductivity between the semiconductor element in the first region 110 and the semiconductor element in the second region 120 is a difference in electrical conductivity with respect to the wavelength of incident light. Further, when the plurality of semiconductor elements of the semiconductor device 101 are made to have different electrical conductivity depending on the amount of incident light from the outside due to the presence or absence of the second insulating layer 500, the amount of incident light on the base material 100 of the semiconductor device 101 is There will be two or more types of semiconductor elements having different electrical conductivities relative to each other. In this case, the difference in electrical conductivity between the semiconductor element in the first region 110 and the semiconductor element in the second region 120 is the difference in electrical conductivity with respect to the amount of incident light. A semiconductor device 101 including two or more types of semiconductor elements having different electrical conductivities with respect to the wavelength of incident light as described above, and two or more types of semiconductor elements having different electrical conductivities with respect to the amount of incident light as described above. By combining the above semiconductor device 101, it is possible to realize a circuit whose operation and function change depending on the type and intensity of light incident from the outside. As a result, it is possible to provide a circuit that can be applied to a wide variety of applications, such as imaging devices such as image sensors and ultraviolet detection devices.

Furthermore, when the plurality of semiconductor elements of the semiconductor device 101 are made to have different electrical conductivity depending on the amount of oxygen applied from the outside by the presence or absence of the second insulating layer 500, the amount of oxygen on the base material 100 of the semiconductor device 101 is There will be two or more types of semiconductor elements having different electrical conductivities relative to each other. In this case, the difference in electrical conductivity between the semiconductor element in the first region 110 and the semiconductor element in the second region 120 is the difference in electrical conductivity with respect to the amount of oxygen. With this configuration, the semiconductor device 101 can realize a wide variety of functions, such as being able to be used as a sensor for detecting oxygen.

Further, the structure of the FETs 200 and 300 in the first embodiment is a so-called bottom gate structure in which the gate electrode is arranged below the semiconductor layer (on the base material side), as shown in FIG. However, the structure of the FETs 200 and 300 in the first embodiment is not limited to this, and may be, for example, a so-called top gate structure in which the gate electrode is placed above the semiconductor layer (on the opposite side to the base material). There may be.

Further, in the first embodiment, the vertical structure of the channel portion of the n-type FET 200 includes, from the bottom to the top, the base material 100, the gate electrode 230, the gate insulating layer 250, the semiconductor layer 270, and the second insulating layer. 500 are arranged in this order. However, the vertical structure of the channel portion of the n-type FET 200 is not limited to this, and from the bottom to the top, the gate electrode 230, the gate insulating layer 250, the semiconductor layer 270, the second insulating layer 500, and the base material 100. may be arranged in this order. Similarly, the vertical structure of the channel portion of the p-type FET 300 is such that the base material 100, gate electrode 330, gate insulating layer 350, and semiconductor layer 370 are arranged in this order from the bottom to the top. However, the structure is not limited to this, and the gate electrode 330, gate insulating layer 350, semiconductor layer 370, and base material 100 may be arranged in this order from the bottom to the top.

Further, the lateral structure of the channel portion of these FETs 200 and 300 is such that a source electrode, a semiconductor layer, and a drain electrode are arranged in this order from the right side to the left side, as shown in FIG. However, since these source and drain electrodes have symmetry, the lateral structure of the channel portion may have the right and left sides reversed.

(Embodiment 2)
FIG. 3 is a schematic plan view schematically showing a configuration example of a semiconductor device according to Embodiment 2 of the present invention. As shown in FIG. 3, a semiconductor device 102 according to the second embodiment includes a first region 111 on a base material 100 in place of the first region 110 in the first embodiment described above. In addition to the first region 111 and the second region 120, the third region 130 is further included. The first region 111 is a region continuous with the second region 120 and the third region 130 on the surface of the base material 100 (in FIG. 3, a region adjacent to both of them). This is the same as the first region 110 in No. 1. In the second embodiment, four FETs 201 are arranged in the first region 111 as an example of two or more semiconductor elements. These FETs 201 each include a second insulating layer 510 similar to the second insulating layer 500 in the first embodiment. Each of these FETs 201 has the same transistor structure as the FET 200 in the first region 110 in the first embodiment, and has the same electrical conductivity (for example, n-type characteristics) as the above-described FET 200 due to the second insulating layer 510. has. The second insulating layer 510 is continuously arranged over two or more semiconductor elements (four FETs 201 in FIG. 3) in the first region 111. The other configurations are the same as those in Embodiment 1, and the same components are given the same reference numerals.

As shown in FIG. 3, the third region 130 is a region other than the first region 111 and the second region 120 among the plurality of regions on the base material 100, in which two or more semiconductor elements are arranged. This is an example of an area where In the second embodiment, four FETs 202 are arranged in the third region 130 as an example of two or more semiconductor elements. Each of these FETs 202 is an example of a semiconductor element in the third region 130. Although not particularly illustrated, each of these FETs 202 includes a source electrode in the third region 130, a drain electrode in the third region 130, a gate electrode in the third region 130, and a semiconductor layer in the third region 130. , a gate insulating layer in the third region 130 , and a third insulating layer 520 . The semiconductor layer of the third region 130 is a semiconductor layer that is in contact with the source electrode of the third region 130 and the drain electrode of the third region 130. The gate insulating layer of the third region 130 is a layer that insulates the semiconductor layer of the third region 130 and the gate electrode of the third region 130. These source electrodes, drain electrodes, gate electrodes, semiconductor layers, and gate insulating layers in the third region are the source electrodes, drain electrodes, gate electrodes, and gate electrodes in the first region 111 and the second region 120, respectively. This is similar to the semiconductor layer and the gate insulating layer. The transistor structure of the FET 202 in the third region 130 is similar to the FET 201 in the first region 111 except that it includes the third insulating layer 520.

The third insulating layer 520 is an insulating layer that contacts the semiconductor layer of the third region 130 at a position different from the gate insulating layer of the third region 130, and is continuous over two or more of the semiconductor elements of the third region 130. will be placed. In the second embodiment, as shown in FIG. 3, the third insulating layer 520 is disposed continuously over the four FETs 202 so as to cover them. The composition forming the second insulating layer 510 described above and the composition forming the third insulating layer 520 are different from each other.

In the present invention, "the composition constituting the second insulating layer and the composition constituting the third insulating layer are different from each other" means that the compounds constituting each layer of the second insulating layer and the third insulating layer are different from each other. That means. For example, as an example of the case where the "compounds constituting each layer are different", for example, the resin constituting the insulating layer in each layer is different from each other, or the resin constituting the insulating layer is the same in each layer. However, additives such as organic compounds and electron-donating compounds that are separately included may be different.

As with the preferred example of the second insulating layer described in Embodiment 1 (for example, the second insulating layer 500 shown in FIG. 1), the second insulating layer 510 is electrically connected to the semiconductor layer of the FET 201 in the first region 111. There are no particular limitations on the material or formation method as long as it can fulfill the role of supplying carriers such as electrons and holes that play a role in conductivity.

Similarly to the preferred example of the second insulating layer described in Embodiment 1, the third insulating layer 520 also contains carriers such as electrons and holes that are responsible for electrical conductivity with respect to the semiconductor layer of the FET 202 in the third region 130. It is preferable to be able to fulfill the role of supplying. That is, the FET 202 in the third region 130 preferably has desired electrical conductivity due to the third insulating layer 520. For example, the electrical conductivity of FET 202 in third region 130 is different from both the electrical conductivity of FET 201 in first region 111 and the electrical conductivity of FET 300 in second region 120 due to third insulating layer 520. It is possible. To give a specific example in this case, the difference in electrical conductivity between the FET 201 in the first region 111 and the FET 300 in the second region 120 is due to the difference in the electric type of the transistor, and The difference in electrical conductivity between the FET 202 in the second region 120 and the FET 300 in the second region 120 is a difference in threshold voltage of the transistors.

However, the third insulating layer 520 makes the electrical conductivity of the FET 202 in the third region 130 different from that of the FET 201 arranged in the first region 111 and the FET 300 arranged in the second region 120. It is not limited to things that change. For example, the third insulating layer 520 plays a role of increasing the insulation between wirings arranged so as to sandwich the third region 130, and a role of improving processability, mechanical strength, etc. in the manufacturing process. You can also do that. At this time, for example, both the FET 201 in the first region 111 and the FET 202 in the third region 130 may be FETs having n-type characteristics (n-type FETs).

With the above configuration, in the semiconductor device 102 according to the second embodiment, at least the FET 201 disposed in the first region 111 and the FET 202 disposed in the third region 130 have different electric currents. It becomes possible to provide conductivity. For example, the FET 201 in the first region 111, the FET 300 in the second region 120, and the FET 202 in the third region 130 can have different electrical conductivities. As a result, a more complex circuit can be formed on the base material 100 without excessively increasing the area of the semiconductor device 102. Specifically, the second insulating layer 510 and the third insulating layer 520 have different compositions from each other, and have different compositions than the semiconductor layer of the FET 201 in the first region 111 and the semiconductor layer of the FET 202 in the third region 130. , each providing a different electrical conductivity. This makes it possible, for example, to bring about a change in threshold voltage between these FETs 201 and 202. That is, the difference in electrical conductivity between the FET 201 in the first region 111 and the FET 202 in the third region 130 is due to the difference in threshold voltage of the transistors, regardless of whether their conductivity types are different from each other. can do. As a result, it is possible to realize a more complicated circuit of the semiconductor device 102 without significantly increasing the area of the base material 100.

FIG. 4 is a schematic circuit diagram showing a configuration example of a charge pump circuit to which a semiconductor device according to Embodiment 2 of the present invention is applied. In the second embodiment, for example, by using the semiconductor device 102 and the like, a charge pump circuit as shown in FIG. 4 can be configured. As shown in FIG. 4, this charge pump circuit includes a plurality (for example, two) of inverters 600, a clock generation circuit 601, a plurality of (for example, two) FETs 602, and a capacitor 603. Each of these inverters 600 is configured by wiring-connecting and combining FET 201 (n-type FET) in first region 111 and FET 300 (p-type FET) in second region 120 in semiconductor device 102 . The clock generation circuit 601 is configured by combining a plurality of these FETs 201 and 300 by wiring them. Further, the plurality of FETs 602 are configured by connecting a plurality of FETs 202 in the third region 130 of the semiconductor device 102 by wiring and combining them. The charge pump circuit shown in FIG. 4 is configured by wiring-connecting a capacitor 603 to a plurality of inverters 600, a clock generation circuit 601, and a plurality of FETs 602 that are configured using the semiconductor device 102 as described above.

Generally, in a voltage boosting circuit called a charge pump circuit using a capacitor 603, the FET 602 is required to have the lowest possible threshold voltage. On the other hand, in circuits for controlling this charge pump circuit, such as the internal circuit of the clock generation circuit 601 (oscillation circuit) and the inverter 600, the transistors (specifically, the n-type FET 201 and From the viewpoint of current consumption of the semiconductor device 102, it is preferable to set the threshold voltage of the p-type FET 300 to a threshold voltage (approximately 0.7 V to 1.2 V) used in a normal logic circuit. Therefore, such a charge pump circuit requires n-type FETs having at least two types of threshold voltages. In such a case, by using the semiconductor device 102 including the FET 201 in the first region 111, the FET 300 in the second region 120, and the FET 202 in the third region 130 in the second embodiment, the circuit area can be reduced. A small IC chip can be formed.

In addition, when forming this charge pump circuit, in the semiconductor device 102, the second insulating layer 510 is applied to the semiconductor layer of the FET 201 in the first region 111 and the semiconductor layer of the FET 202 in the third region 130, respectively. The third insulating layer 520 provides different electrical conductivity. Specifically, although these FET 201 and FET 202 are both n-type FETs, the threshold voltage of FET 202 that constitutes FET 602 of the charge pump circuit is the same as that of FET 201 used in inverter 600 and clock generation circuit 601. It will be lower than the value voltage.

Furthermore, when forming this charge pump circuit, the FET 602 does not necessarily have to be an n-type FET, and may be, for example, a p-type FET whose threshold voltage is as low as possible. In this case, the third insulating layer 520 gives the semiconductor layer of the FET 202 in the third region 130, which is a p-type FET, different electrical characteristics from the semiconductor layer of the FET 300 in the second region 120, which is a p-type FET. It will be provided. Specifically, the FET 201 in the first region 111 is an n-type FET, and the FET 300 in the second region 120 and the FET 202 in the third region 130 are p-type FETs different from the FET 201 described above. Although FET 300 and FET 202 are both p-type FETs, the threshold voltage of FET 202 that constitutes FET 602 of the charge pump circuit is higher than that of FET 300 used in inverter 600 and clock generation circuit 601. It will be low.

Note that although the second embodiment described above shows a semiconductor device having the first to third regions on the base material, the present invention is not limited to this. The semiconductor device according to the present invention includes an insulating layer having a composition different from the second insulating layer and the third insulating layer described above (a fourth insulating layer or a fifth insulating layer that collectively covers two or more semiconductor elements) on the base material. It may have a plurality of regions including further regions such as a fourth region, a fifth region, etc., in which an insulating layer, etc.) are arranged. Further, the arrangement of the plurality of semiconductor elements (for example, FETs 202) in the third region 130 is not limited to the two rows and two columns illustrated in FIG. 3, but may be arranged in one or more rows and one or more columns. A multi-row and multi-column arrangement is often preferred. When these multiple semiconductor devices are arranged in multiple rows and multiple columns, the number of semiconductor devices included in one row may be one or more, and the number of semiconductor devices included in one column may be may be one or more. Preferably, the number of semiconductor elements included in one row is plural, and the number of semiconductor elements included in one column is preferably plural. The reason why it is preferable to arrange the plurality of semiconductor elements in the third region 130 in a plurality of rows and columns is the same as the arrangement of the semiconductor elements in the first region 110 described in the first embodiment. be. In addition, matters that were not explained in detail in the second embodiment described above and have the same configuration as the first embodiment are the same as those in the first embodiment.

(Embodiment 3)
FIG. 5 is a schematic plan view schematically showing a configuration example of a semiconductor device according to Embodiment 3 of the present invention. As shown in FIG. 5, the semiconductor device 103 according to the third embodiment also includes a second insulating layer 550 on the FET 300 disposed in the second region 120 of the base material 100. The other configurations are the same as in the second embodiment, and the same components are given the same reference numerals.

In the first and second embodiments described above, the necessity for the second insulating layer 550 to exist in the second region 120 was not particularly explained. However, as described in Embodiment 1 by exemplifying the second insulating layer 500 shown in FIG. As a protective film, it has the function of protecting semiconductor elements from surrounding contamination, noise, and environmental changes. Therefore, as long as the FET 201 in the first region 111 and the FET 300 in the second region 120 have different electrical conductivities, the second insulating layer is present in both the first region 111 and the second region 120. It's okay.

For example, as shown in FIG. 5, a second insulating layer 550 is provided in the second region 120 of the base material 100 so as to cover one or more (for example, eight) FETs 300 arranged in the second region 120. It is provided. In particular, when two or more FETs 300 are arranged in the second region 120, the second insulating layer 550 is continuously arranged over two or more of these FETs 300. Like the second insulating layer 510 in the first region 111, the second insulating layer 550 contacts the semiconductor layer of the FET 300 in the second region 120 at a different position from the gate insulating layer of the FET 300. The material of the second insulating layer 550 is not particularly limited as long as it is an insulating material that makes the electrical conductivity of the FET 300 in the second region 120 different from the electrical conductivity of the FET 201 in the first region 111.

In the third embodiment, the base material 100 on which the second insulating layer 510 in the first region 111 and the second insulating layer 550 in the second region 120 are provided has a base material surface divided into three regions. However, the present invention is not limited thereto. The base material 100 in which the second insulating layer 550 is provided in the second region 120 may have a base material surface divided into two regions as shown in the first embodiment described above, or The surface may be divided into four or more regions. Further, the arrangement of the semiconductor elements (for example, FET 300) in the second region 120 is not limited to the arrangement of two rows and four columns illustrated in FIG. 5, but may be arranged in one or more rows and one or more columns. A multi-row and multi-column arrangement is preferred. When the semiconductor elements in the second region 120 are arranged in multiple rows and columns, the number of semiconductor elements included in one row may be one or more, and the number of semiconductor elements included in one column may be The number of elements may be one or more. Preferably, the number of semiconductor elements included in one row is plural, and the number of semiconductor elements included in one column is preferably plural. The reason why it is preferable to arrange the semiconductor elements in the second region 120 in a plurality of rows and columns is the same as the arrangement of the semiconductor elements in the first region 110 described in the first embodiment described above.

(Embodiment 4)
FIG. 6 is a schematic plan view schematically showing a configuration example of a semiconductor device according to Embodiment 4 of the present invention. As shown in FIG. 6, the semiconductor device 104 according to the sixth embodiment further includes an overcoat layer 560 on the base material 100. Overcoat layer 560 is provided on base material 100 so as to cover second insulating layers 510, 550 and third insulating layer 520. The other configurations are the same as those in Embodiment 3, and the same components are given the same reference numerals.

As shown in FIG. 6, the overcoat layer 560 is disposed on the base material 100 of the semiconductor device 104, and is arranged on the semiconductor element (first The FET 201 in the region 111, the FET 300 in the second region 120, and the FET 202 in the third region 130 are covered. Thereby, overcoat layer 560 can protect these second insulating layers 510, 550 and third insulating layer 520, and the semiconductor element on base material 100 from the outside. It is preferable to arrange the overcoat layer 560 on the base material 100 of the semiconductor device 104 in this way from the viewpoint of suppressing deterioration of the electrical characteristics of the semiconductor element, protecting it from contamination, and the like.

Note that the semiconductor device 104 further includes, for example, not only the overcoat layer 560 but also an insulating layer having a composition different from that of the overcoat layer 560, and uses the insulating layer to improve electrical conduction of each semiconductor element on the base material 100. Gender may be adjusted. As long as each semiconductor element on the base material 100 has desired electrical conductivity, the number of the insulating layers is not particularly limited.

Furthermore, in the fourth embodiment, the overcoat layer 560 is exemplified to cover the second insulating layers 510, 550 and the third insulating layer 520 provided in three regions on the base material 100, but the present invention is not limited to this. In the present invention, the overcoat layer 560 may cover the second insulating layer 500 and the FET 200 of the semiconductor device 101 according to the first embodiment and the FET 300 of the second region 120, or may cover the FET 300 of the second region 120. The second insulating layer 510 and FET 201 of the semiconductor device 102, the FET 300 of the second region 120, the third insulating layer 520, and the FET 202 may be covered. Alternatively, the overcoat layer 560 may suitably cover the semiconductor element in each region divided into four or more regions on the base material 100 and the insulating layer thereon.

(Embodiment 5)
FIG. 7 is a schematic plan view schematically showing a configuration example of a semiconductor device according to Embodiment 5 of the present invention. As shown in FIG. 7, a semiconductor device 105 according to the fifth embodiment includes a first region 112 on a base material 100 instead of the first region 110 in the first embodiment described above, and a second region 112 in place of the first region 110 in the first embodiment described above. A second region 121 is included in place of the region 120 of FIG. Further, the semiconductor device 105 includes two or more FETs 203 and 204 in the first region 112 instead of the two or more FETs 200 in the first embodiment described above, and two or more FETs 203 and 204 instead of the second insulating layer 500. The second insulating layer 511 covers the FET 203 and the second insulating layer 512 covers the two or more FETs 204. Furthermore, the semiconductor device 105 includes one or more FETs 301 in the second region 121 instead of the one or more FETs 300 in the first embodiment described above. The other configurations are the same as those in Embodiment 1, and the same components are given the same reference numerals.

Each of the two or more FETs 203 and 204 in the first region 112 has the same transistor structure as the FET 200 in the first region 110 in the first embodiment. The FET 203 includes a second insulating layer 511, and has the same electrical conductivity (for example, n-type characteristics) as the above-described FET 200 due to the second insulating layer 511. Further, the FET 204 includes a second insulating layer 512, and has the same electrical conductivity as the above-described FET 203 due to the second insulating layer 512. In the fifth embodiment, as shown in FIG. 7, two or more FETs 203 (for example, 10) are formed in the first region 112 so that the FETs 203 are arranged in a lengthwise manner (for example, an arrangement of 2 rows and 5 columns). ing. Further, two or more (for example, six) FETs 204 are formed in the first region 112 so that the FETs 204 are arranged in a lengthwise manner (for example, an arrangement of 1 row and 6 columns). In the present invention, an arrangement having long and short lengths refers to an arrangement in which one of a plurality of rows or columns of semiconductor elements arranged on a base material is longer than the other (the number of semiconductor elements arranged is larger). It is.

The second insulating layers 511 and 512 are each made of the same composition as the second insulating layer 500 in the first embodiment. That is, the composition forming the second insulating layer 511 and the composition forming the second insulating layer 512 are the same. On the other hand, the second insulating layer 511 and the second insulating layer 512 are provided in independent regions within the first region 112 without contacting each other.

In addition, the second insulating layer 511 covers two or more FETs 203 (FIG. 7 (10 pieces) are arranged consecutively. On the other hand, the second insulating layer 512 is continuously arranged over two or more FETs 204 (six in FIG. 7) so as to collectively cover the FETs 204 among these FETs 203 and 204. In the fifth embodiment, these second insulating layers 511 and 512 have a rectangular shape with rounded corners when viewed in plan from a direction perpendicular to the surface of the base material 100. Similar to the second insulating layer in .about.4, the shape of the second insulating layer 511, 512 is not particularly limited to a rectangular shape with rounded corners. For example, as in the case of the second insulating layer 500 in the first embodiment, the shape of the second insulating layers 511 and 512 may be an ellipse, a rectangle, a rectangle with rounded corners, or a width and length depending on the arrangement of semiconductor elements. For example, a shape having a shape (for example, a linear shape) can be mentioned.

Further, in the fifth embodiment, as shown in FIG. 7, a plurality (for example, two) of second insulating layers 511 and 512 are arranged in the first region 112 so as to have a shape with long and short lengths. . That is, the second insulating layers 511 and 512 each have a shape having a long direction and a short direction depending on the arrangement of the FETs 203 and 204, respectively. When the plurality of second insulating layers 511 and 512 each have a shape having a long direction and a short direction, the long directions of the plurality of second insulating layers 511 and 512 may be the same direction. preferable. In particular, when the second insulating layers 511 and 512 are formed by coating using a nozzle coating method or the like, the longitudinal direction of the second insulating layers 511 and 512 is parallel to the transport direction of the base material 100 during manufacturing of the semiconductor device 105. It is more preferable from the viewpoint of manufacturing tact and the like. In addition, when forming the second insulating layers 511 and 512 by coating using a screen printing method or the like, the longitudinal direction of the second insulating layers 511 and 512 is aligned with the transport direction of the base material 100 from the viewpoint of ease of designing the manufacturing apparatus. It is preferable that the direction is perpendicular to the direction.

Items that were not explained in detail in the above-described fifth embodiment and have common configurations with the first embodiment are the same as those in the first embodiment. Further, in the fifth embodiment described above, a plurality of second insulating layers are provided in the first region of the base material 100 including two regions, but the present invention is not limited to this. isn't it. In the present invention, the plurality of second insulating layers are provided in a first region of the base material 100 including three regions as shown in Embodiments 2 to 4. You can. Further, the number of second insulating layers provided in the first region is not limited to two as described above, and may be three or more. Further, the arrangement of the plurality of semiconductor elements (for example, FETs 203 and 204) in the first region 112 is not limited to the arrangement of 2 rows and 5 columns or 1 row and 6 columns illustrated in FIG. The above arrangement may be possible, and an arrangement of multiple rows and multiple columns is preferred. When these multiple semiconductor devices are arranged in multiple rows and multiple columns, the number of semiconductor devices included in one row may be one or more, and the number of semiconductor devices included in one column may be may be one or more. Preferably, the number of semiconductor elements included in one row is plural, and the number of semiconductor elements included in one column is preferably plural. The reason why it is preferable to arrange the plurality of semiconductor elements in the first region 112 in a plurality of rows and columns is the same as the arrangement of the semiconductor elements in the first region 110 described in the first embodiment. be.

(Embodiment 6)
FIG. 8 is a schematic plan view schematically showing a configuration example of a semiconductor device according to Embodiment 6 of the present invention. As shown in FIG. 8, the semiconductor device 106 according to the sixth embodiment has a third region on the base material 100, in addition to the first region 112 and the second region 121 in the fifth embodiment described above. area 131. The third region 131 is a region continuous with the first region 112 and the second region 121 on the surface of the base material 100 (in FIG. 8, it is a region sandwiched between the first region 112 and the second region 121 (adjacent areas). In the sixth embodiment, six FETs 205 are arranged in the third region 131 as an example of two or more semiconductor elements. These FETs 205 each include a third insulating layer 521. The other configurations are the same as in the fifth embodiment, and the same components are given the same reference numerals.

As shown in FIG. 8, the third region 131 is a region other than the first region 112 and the second region 121 among the plurality of regions on the base material 100, in which two or more semiconductor elements are arranged. This is an example of an area where In the sixth embodiment, six FETs 205 are arranged in the third region 131 as an example of two or more semiconductor elements. These FETs 205 are formed in the third region 131 in an arrangement having lengths (for example, an arrangement of 1 row and 6 columns). Each of these FETs 205 is an example of a semiconductor element in the third region 131, and has the same transistor structure as the FET 202 in the third region 130 in the second embodiment described above, except that it includes the third insulating layer 521. have

The third insulating layer 521 is an insulating layer in contact with the semiconductor layer of the FET 205 at a position different from the gate insulating layer of the FET 205 in the third region 131, and is continuous over two or more semiconductor elements in the third region 131. will be placed. In the sixth embodiment, as shown in FIG. 8, the third insulating layer 521 is continuously arranged over six FETs 205 that are arranged in a long and short arrangement so as to cover the six FETs 205. In this case, the third insulating layer 521 has a shape having long and short lengths (for example, a linear shape having a width and length depending on the arrangement of the FETs 205), as shown in FIG. Further, the composition forming the second insulating layer 511 of the first region 112 and the composition forming the third insulating layer 521 are different from each other.

Moreover, it is preferable that the third insulating layer 521 can realize the role of supplying carriers such as electrons and holes that are responsible for electrical conductivity to the semiconductor layer of the FET 205 in the third region 131. That is, it is preferable that the FET 205 in the third region 131 has desired electrical conductivity due to the third insulating layer 521. For example, the FET 205 in the third region 131 has the same n-type characteristics as the FET 203 in the first region 112 due to the third insulating layer 521, and has a different threshold voltage than the FET 203 in the first region 112. It is a type FET. The material and formation method of the third insulating layer 521 are not limited as long as the functions described above can be realized.

Further, in the sixth embodiment, the second insulating layer 511 of the first region 112 and the third insulating layer 521 of the third region 131 each have a shape with long and short lengths, as shown in FIG. 8, for example. It is arranged like this. In this case, the longitudinal direction of the second insulating layer 511 and the longitudinal direction of the third insulating layer are preferably the same direction. In particular, when the second insulating layer 511 and the third insulating layer 521 are formed by coating using a nozzle coating method or the like, the longitudinal direction of the second insulating layer 511 and the third insulating layer 521 is aligned with the base material 100 when the semiconductor device 106 is manufactured. It is more preferable from the viewpoint of manufacturing tact etc. to be parallel to the conveyance direction. In addition, when forming the second insulating layer 511 and the third insulating layer 521 by coating using a screen printing method or the like, the longitudinal direction of the second insulating layer 511 and the third insulating layer 521 is The direction is preferably perpendicular to the conveying direction of the base material 100.

In the sixth embodiment described above, one second insulating layer 511 is provided in the first region 112, but the number of second insulating layers 511 in the first region 112 is limited to one. Instead, a plurality of second insulating layers 511 may be provided in the first region 112. Similarly, the number of third insulating layers 521 in the third region 131 is not limited to one, and a plurality of third insulating layers 521 may be provided in the third region 131. In addition, similar to the second embodiment described above, the semiconductor device according to the present invention includes an insulating layer having a composition different from the second insulating layer and the third insulating layer (two or more semiconductor elements) on the base material. It may have a plurality of regions, including further regions such as a fourth region and a fifth region, in which a fourth insulating layer, a fifth insulating layer, etc. that collectively cover the substrate are disposed. Regarding the fourth region and the fifth region, the configuration items common to the third region are the same as the third region.

Furthermore, the shapes of the second insulating layer 511 and the third insulating layer 521 are not particularly limited, similar to the shape of the second insulating layer shown in the fifth embodiment described above. For example, one or more second insulating layers 511 and one or more third insulating layers 521 are provided on the base material 100 of the semiconductor device 106, and the shapes of the second insulating layers 511 and the third insulating layers 521 are different from each other in the longitudinal direction. In the case of a shape having a short direction, the long directions of all the second insulating layers 511 and third insulating layers 521 in the semiconductor device 106 are preferably the same direction.

Further, the arrangement of the plurality of semiconductor elements (for example, FET 205) in the third region 131 is not limited to the arrangement of one row and six columns illustrated in FIG. 8, but may be arranged in one or more rows and one or more columns. A multi-row and multi-column arrangement is often preferred. When these multiple semiconductor devices are arranged in multiple rows and multiple columns, the number of semiconductor devices included in one row may be one or more, and the number of semiconductor devices included in one column may be may be one or more. Preferably, the number of semiconductor elements included in one row is plural, and the number of semiconductor elements included in one column is preferably plural. The reason why it is preferable to arrange the plurality of semiconductor elements in the third region 131 in a plurality of rows and columns is the same as the arrangement of the semiconductor elements in the first region 110 described in the first embodiment. be. In addition, matters not explained in detail in the above-mentioned sixth embodiment, which have the same configuration as the second embodiment and the fifth embodiment, are the same as the second embodiment and the fifth embodiment. .

<Method for manufacturing semiconductor devices>
Next, a method for manufacturing a semiconductor device according to the present invention will be explained. FIG. 9 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the present invention. Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be explained in detail with reference to FIG. 9, taking as an example a method for manufacturing semiconductor device 101 according to the first embodiment shown in FIGS.

In the method for manufacturing a semiconductor device according to the present invention, as shown in FIG. 9, first, a gate electrode forming step of forming gate electrodes 230 and 330 on the base material 100 is performed (step ST1). In this step ST1, first, an electrode layer (for example, a metal layer) that will become the source of the gate electrode 230 and the gate electrode 330 is formed on the substrate surface of the base material 100 made of a PET film or the like. Next, the formed electrode layer is processed into a desired shape using a process including resist coating, exposure, development, etching, and the like, a so-called photolithography process. Thereby, as shown in FIG. 9, the gate electrode 230 is formed in the first region 110 of the base material 100, and the gate electrode 330 is formed in the second region 120 of the base material 100. Note that the detailed conditions of the materials for forming the gate electrodes 230 and the gate electrodes 330, the method of forming the electrode layers, and the photolithography process are as long as the desired shapes of the gate electrodes 230 and the gate electrodes 330 can be obtained. , not particularly limited.

Next, as shown in FIG. 9, a gate insulating layer forming step of forming gate insulating layers 250 and 350 on the base material 100 is performed (step ST2). In this step ST2, an insulating film for forming the gate insulating layer 250 and the gate insulating layer 350 is formed on the substrate surface of the base material 100. As a result, the portion of this insulating film that covers the gate electrode 230 in the first region 110 is formed as the gate insulating layer 250, and the portion that covers the gate electrode 330 in the second region 120 is formed as the gate insulating layer 350. It is formed. The method of forming the gate insulating layer 250 and the gate insulating layer 350 is not particularly limited, but for example, forming the gate insulating layer 250 and the gate insulating layer 350 by coating has the advantage that the gate insulating layer 250 and the gate insulating layer 350 can be formed at low cost. be. Note that the gate insulating layer 250 and the gate insulating layer 350 may be processed using, for example, a photolithography process so that only the portions constituting the semiconductor element remain, or may be processed without being processed. The entire surface of the insulating film including 350 may remain. However, although omitted in this example of the semiconductor device manufacturing method, wiring for electrical connection to the gate electrode 230 and the gate electrode 330 is formed in any process included in this semiconductor device manufacturing method. The process is necessary.

Subsequently, as shown in FIG. 9, an electrode forming step is performed to form source electrodes 210, 310 and drain electrodes 220, 320 on the base material 100 (step ST3). In this step ST3, the source electrode 210 and the drain electrode 220 are formed in desired shapes on the gate insulating layer 250 in the first region 110 on the base material 100, and the gate insulating layer 350 in the second region 120 is formed on the gate insulating layer 350 in the second region 120. A source electrode 310 and a drain electrode 320 are formed in desired shapes thereon. At this time, for example, on the insulating film (the insulating film including the gate insulating layers 250, 350) formed in the above-mentioned step ST2, an electrode such as a metal layer that is the source of the source electrodes 210, 310 and the drain electrodes 220, 320 is placed. Deposit a layer. Next, this formed electrode layer is processed into a desired shape using the photolithography process described above. As a result, as shown in FIG. 9, the source electrode 210 and drain electrode 220 in the first region 110 and the source electrode 310 and drain electrode 320 in the second region 120 are formed.

Also in this step ST3, for example, there is an advantage that the source electrodes 210, 310 and the drain electrodes 220, 320 can be formed at a lower cost by using a material that can be coated as the electrode material. However, the materials, film formation methods, and processing methods for forming the source electrodes 210, 310 and the drain electrodes 220, 320 are limited as long as the desired shapes and characteristics of the source electrodes 210, 310 and the drain electrodes 220, 320 can be obtained. , not particularly limited. Further, although omitted in the example of this semiconductor device manufacturing method, in any process included in this semiconductor device manufacturing method, a process for electrically connecting to the source electrodes 210, 310 and the drain electrodes 220, 320 A process of forming wiring is necessary.

Next, as shown in FIG. 9, a semiconductor layer forming step of forming semiconductor layers 270 and 370 on the base material 100 is performed (step ST4). In this step ST4, a semiconductor layer 270 is formed on the base material 100 in a region between the source electrode 210 and the drain electrode 220 in the first region 110, and A semiconductor layer 370 is formed in the region between the electrodes 320. Note that these semiconductor layers 270 and 370 may be formed by, for example, dropping using an inkjet method, using the region to be formed as a target. However, the method for forming the semiconductor layers 270, 370 is not particularly limited as long as the semiconductor layers 270, 370 can be formed at desired locations. Furthermore, in this example of the method for manufacturing a semiconductor device, a semiconductor is formed after forming a source electrode and a drain electrode, but a semiconductor layer may be formed before forming a source electrode and a drain electrode. The order of the forming steps is not particularly limited.

Next, as shown in FIG. 9, a step of forming the second insulating layer 500 in the first region 110 of the base material 100 is performed (step ST5). The second insulating layer formed in this step ST5 is preferably an organic insulating layer. Further, the method for forming the second insulating layer 500 in this step ST5 is not particularly limited, but a method of applying a composition for forming the second insulating layer 500 is preferable. That is, in the method for manufacturing a semiconductor device according to the present invention, a composition for forming a second insulating layer (hereinafter referred to as a "second insulating layer composition"), exemplified by the second insulating layer 500, is used as a base. It is preferable to include a coating step of continuously coating two or more semiconductor elements in the first region of the material. This coating step is performed, for example, as step ST5 of forming the second insulating layer 500 on the first region 110 of the base material 100. In addition, in this coating step, the second insulating layer composition is applied to two or more FETs 200 in the first region 110, rather than applying the second insulating layer composition to each of the plurality of FETs 200 in the first region 110. From the viewpoint of manufacturing costs, it is preferable to apply the coating continuously over a plurality of semiconductor elements.

Examples of the coating method include an inkjet method, a nozzle coating method, a screen printing method, an offset printing method, and a drop cast coating method. In step ST5 (coating step), the second insulating layer composition is applied to the first region 110 by any one of these methods, thereby collectively covering the plurality of FETs 200 in the first region 110. A second insulating layer 500 according to the embodiment is formed. As for the coating method performed in step ST5, it is preferable to select an optimal method depending on the size of each FET 200 and the material of the second insulating layer 500. From the viewpoint of manufacturing cost and uniformity of the film thickness of the second insulating layer 500, compared to an inkjet method or other coating method in which the second insulating layer composition is repeatedly applied to a relatively narrow area, a relatively narrow coating method such as screen printing is preferred. A coating method that allows the second insulating layer composition to be applied all at once over a wide area is more preferred. By improving the uniformity of the film thickness of the second insulating layer 500, variations in electrical characteristics between FETs 200 that are close to each other can be minimized as much as possible, and electrical characteristics can be improved, especially in circuits that utilize relative precision. High-performance circuits can be realized.

By performing the above steps ST1 to ST5, it is possible to manufacture a chip using a semiconductor device having the configuration shown in Embodiment 1 of the present invention, and it is possible to realize a highly functional or high-performance circuit at a low manufacturing cost. . Furthermore, these steps ST1 to ST5 can be applied not only to the manufacture of the semiconductor device according to the first embodiment but also to the manufacture of the semiconductor devices according to the second to sixth embodiments. For example, when forming a plurality of second insulating layers in the first region of the base material 100, the above-mentioned step ST5 is appropriately performed at a plurality of locations in the first region. Further, when forming a semiconductor element in the third region of the base material 100, each of the above-described steps ST1 to ST5 is also performed appropriately for the third region.

<Wireless communication device>
A wireless communication device including a semiconductor device according to the present invention will be described. This wireless communication device is a device, such as an RFID tag, which performs electrical communication by receiving a wireless signal transmitted from an antenna mounted on a reader/writer.

The specific operation of the RFID tag as an example of the wireless communication device is as follows, for example. That is, the antenna of the RFID tag receives a wireless signal transmitted from an antenna mounted on the reader/writer. The received radio signal is converted into direct current by the rectifier circuit of the RFID tag. The RFID tag generates electricity based on this direct current. Next, the energized RFID tag acquires a command based on the wireless signal from the reader/writer, and performs an operation according to this command. For example, an RFID tag carries data stored in its own memory circuit on a wireless signal, and transmits this wireless signal from its own antenna to the reader/writer's antenna.

A wireless communication device according to the present invention includes one or more types of semiconductor devices among the semiconductor devices according to the first to sixth embodiments described above. For example, in the present invention, a wireless communication device can be configured using an n-type FET, a p-type FET, etc. included in the semiconductor device. By using a wireless communication device having such a configuration, it is possible to realize an inexpensive RFID tag.

FIG. 10 is a schematic block diagram showing a configuration example of a wireless communication device including a semiconductor device according to the present invention. This wireless communication device 700 is configured by combining an antenna 701 with a circuit formed using any one or more of the semiconductor devices according to the first to sixth embodiments described above. The circuit includes, for example, a rectifier circuit 702, a power generation section 703, a logic circuit 704, a memory circuit 705, and an output section 706 shown in FIG. That is, as shown in FIG. 10, the wireless communication device 700 includes an antenna 701, a rectifier circuit 702, a power generation section 703, a logic circuit 704, a memory circuit 705, and an output section 706.

Rectifier circuit 702, power generation section 703, logic circuit 704, memory circuit 705, and output section 706 are each formed using the semiconductor devices according to the first to sixth embodiments described above, as appropriate. For example, the power generation unit 703 can be formed by using a charge pump circuit (see FIG. 4) configured by the semiconductor device or the like according to the second embodiment. Further, the logic circuit 704 can be formed using a ring oscillator, a frequency dividing circuit, etc. to which one or more of the semiconductor devices of the first to sixth embodiments described above is applied. These ring oscillators and frequency dividing circuits can be formed by combining a plurality of n-type FETs and p-type FETs included in the semiconductor device through wiring connections.

In the wireless communication device 700 having the above configuration, the antenna 701 receives a wireless signal transmitted from an external device such as a reader/writer. The rectifier circuit 702 rectifies the radio signal received by the antenna 701 into a DC signal. The power generation unit 703 generates power based on this DC signal, and supplies the generated power to each component of the wireless communication device 700. The logic circuit 704 performs processing such as demodulation on the received radio signal and thereby obtains a command. Next, the logic circuit 704 reads data from the memory circuit 705 based on this command, and generates an electrical signal containing the read data. The output unit 706 acquires an electrical signal from the logic circuit 704 and outputs the acquired electrical signal to the antenna 701 each time. Antenna 701 transmits the electrical signal from output section 706 to an external device as a wireless signal containing the above data.

<Sensor control device>
A sensor control device including a semiconductor device according to the present invention will be described. Although not particularly illustrated, this sensor control device includes one or more types of semiconductor devices among the semiconductor devices according to the first to sixth embodiments described above. Specifically, as illustrated in Embodiment 1, in the semiconductor device according to the present invention, semiconductor elements having arbitrary electrical characteristics (such as electrical conductivity) can be manufactured. In particular, by separately manufacturing a semiconductor element with a second insulating layer (for example, FET 200 shown in FIGS. 1 and 2) and a semiconductor element without a second insulating layer (for example, FET 300 shown in FIGS. 1 and 2), the external environment It is possible to simultaneously form a semiconductor element having a characteristic of being sensitive to external environment and a semiconductor element having a characteristic of being insensitive to an external environment on the same substrate. A semiconductor device including a plurality of semiconductor elements having such mutually different characteristics can be used as a sensor control device.

Specifically, in the present invention, when two or more types of semiconductor elements having different electrical conductivity with respect to ambient temperature are made depending on whether or not a second insulating layer is provided, by using the above semiconductor device, it is possible to It is possible to configure a sensor control device that detects temperature or operates in a specific temperature range. In addition, when two or more types of semiconductor elements having different electrical conductivity with respect to ambient humidity are made depending on the presence or absence of a second insulating layer, by using the above semiconductor device, it is possible to detect ambient humidity or in a specific humidity range. It is possible to configure a sensor control device that performs the following operations. In addition, when two or more types of semiconductor elements having different electrical conductivity with respect to the wavelength of externally incident light are manufactured depending on the presence or absence of the second insulating layer, by using the above semiconductor device, the externally incident light can be It is possible to configure a sensor control device whose operation and functions change depending on the wavelength (type of light). Furthermore, when two or more types of semiconductor elements having different electrical conductivity with respect to the amount of incident light from the outside are manufactured depending on the presence or absence of the second insulating layer, by using the above semiconductor device, it is possible to reduce the amount of incident light from the outside. It is possible to configure a sensor control device whose operation and function change depending on the strength.

Hereinafter, the present invention will be explained in more detail based on Examples. Note that the present invention is not limited to the following examples.

<Example 1>
(First item: Preparation of semiconductor solution)
To prepare a semiconductor solution, first, CNTs (1.5 mg) with a purity of 95% and sodium dodecyl sulfate (1.5 mg) were added to water (30 mL) and cooled on ice using an ultrasonic homogenizer. Then, the mixture was ultrasonically stirred for 3 hours at an output of 250W. At this time, single-walled CNT manufactured by CNI was used as the CNT. The sodium dodecyl sulfate used was manufactured by Wako Pure Chemical Industries, Ltd. Through this ultrasonic stirring, a CNT composite dispersion liquid having a CNT composite concentration relative to the solvent of 0.05 g/L was obtained. Next, the obtained CNT composite dispersion was centrifuged at 21,000 G for 30 minutes using a centrifuge (manufactured by Hitachi Koki, CT15E). Thereafter, 80% by volume of the supernatant of this CNT composite dispersion was taken out to obtain semiconductor solution A1.

(Second item: Preparation of gate insulating layer material)
In preparing the gate insulating layer material, first, methyltrimethoxysilane (61.29g (0.45mol)) and β-(3,4-epoxycyclohexyl)ethyltrimethoxysilane (12.31g (0.05mol)) and phenyltrimethoxysilane (99.15 g (0.5 mol)) were dissolved in propylene glycol monobutyl ether having a volume of 203.36 g and a boiling point of 170°C. Subsequently, water (54.90 g) and phosphoric acid (0.864 g) were added to this with stirring. The solution thus obtained was heated at a bath temperature of 105° C. for 2 hours, the internal temperature was raised to 90° C., and a component mainly consisting of by-produced methanol was distilled out. Next, the bath temperature was set to 130°C, and the mixture was heated for 2.0 hours to raise the internal temperature to 118°C to distill out components mainly consisting of water and propylene glycol monobutyl ether, and then cooled to room temperature. Thereby, gate insulating layer material A2 having a solid content concentration of 26.0% by mass was obtained.

(Third item: Fabrication of semiconductor device)
In manufacturing the semiconductor device of Example 1, as illustrated in Embodiment 1 described above, a semiconductor device 101 including an n-type FET 200 and a p-type FET 300 is formed, and this semiconductor device 101 is used to We created a ring oscillator, which is an oscillation circuit. FIG. 11 is a schematic plan view showing a configuration example of a ring oscillator including a semiconductor device according to Embodiment 1 of the present invention. As shown in FIG. 11, this ring oscillator 632 includes 21 inverters 611 to 631. The ring oscillator 632 was constructed by connecting 21 stages of these inverters 611 to 631 in series. In FIG. 11, in order to simply illustrate the configuration of the ring oscillator 632, among the 21 inverters 611 to 631, inverters 614 to 630, which have a repetitive configuration, are omitted.

Each of the inverters 611 to 631 is a combination of FET 200 (n-type FET) in the first region 110 and FET 300 (p-type FET) in the second region 120 in the semiconductor device 101 illustrated in FIG. It consists of Further, the plurality of sets of FETs 200 and 300 constituting each of these inverters 611 to 631 are connected by wiring (not shown) formed on the base material surface of the base material 100. By using the semiconductor device 101 having such a circuit configuration of a plurality of sets of FETs 200 and 300, a ring oscillator 632 as shown in FIG. 11 can be manufactured. Note that although the semiconductor device 101 that includes eight n-type FETs 200 and eight p-type FETs 300 is illustrated in FIG. Not limited. That is, the semiconductor device 101 applied to the ring oscillator 632 includes the number of n-type FETs 200 and p-type FETs 300 necessary for forming the ring oscillator 632.

The semiconductor device 101 that can constitute the circuit of the ring oscillator 632 in Example 1 is manufactured by sequentially performing the steps shown below. Specifically, in the gate electrode forming step, a glass substrate with a thickness of 1 mm was used as the base material 100, and aluminum with a thickness of 100 nm was vacuum-deposited onto the base material 100 by a resistance heating method. On this aluminum film, a photoresist (trade name "LC100-10cP", manufactured by Rohm and Haas) was spin-coated (1000 rpm x 20 seconds) and dried by heating at 100° C. for 10 minutes. The photoresist film thus produced was pattern-exposed through a mask using a parallel light mask aligner (manufactured by Canon Inc., PLA-501F). Thereafter, this photoresist film was developed with a 2.38% by weight aqueous tetramethylammonium hydroxide solution (trade name "ELM-D", manufactured by Mitsubishi Gas Chemical Co., Ltd.) for 30 seconds with stirring, and then with water for 30 seconds. Washed. Next, through this patterned photoresist film, the aluminum film on the base material 100 is etched for 6 minutes with mixed acid (trade name "SEA-5", manufactured by Kanto Kagaku Co., Ltd.), and then with water. Washed for 30 seconds. Next, this base material 100 was immersed in AZ Remover 100 (trade name, manufactured by AZ Electronic Materials) for 2 minutes to peel off the photoresist film, washed with water for 30 seconds, and then heated and dried at 120° C. for 20 minutes. . As a result, a gate electrode was formed on the base material 100.

After the gate electrode forming step, in the gate insulating layer forming step, the above-mentioned gate insulating layer material A2 (see the second item of Example 1) is dropped onto the base material 100, and this base material 100 is coated with a spin coater. , 5 seconds at a rotation speed of 200 rpm, and then 15 seconds at a rotation speed of 700 rpm. Thereby, the gate insulating layer material A2 was uniformly applied onto the base material 100. Next, the coating film of the gate insulating layer material A2 on the base material 100 was subjected to an annealing treatment in which a certain heat treatment was applied, thereby hardening the gate insulating layer material A2 to form an insulating layer. As a result, a gate insulating layer with a thickness of 350 nm was obtained on the base material 100. Furthermore, this gate insulating layer was pattern-exposed through a mask using a parallel light mask aligner, and then the gate insulating layer at a predetermined position was dip-developed with ELM-D for 40 seconds, and washed with water for 30 seconds. did. This exposed the electrode in the contact hole portion from this gate insulating layer.

After the gate insulating layer forming step, in the electrode forming step, a metal film is formed on the gate insulating layer of the base material 100, and a photoresist is applied by spin coating (1000 rpm x 20 seconds) on this metal film. ) and then heated and dried at 100°C for 10 minutes. The photoresist film thus produced was pattern-exposed through a mask using a parallel light mask aligner. Thereafter, this photoresist film was developed with ELM-D for 30 seconds while stirring using an automatic developing device (manufactured by Takizawa Sangyo Co., Ltd., AD-2000), and then washed with water for 30 seconds. Next, the metal film on the base material 100 was etched for 6 minutes using AURUM-302 (trade name, manufactured by Kanto Kagaku Co., Ltd.) through this patterned photoresist film, and then washed with water for 30 seconds. . Next, this base material 100 was immersed in AZ remover 100 for 2 minutes to peel off the photoresist film, washed with water for 30 seconds, and then heated and dried at 120° C. for 20 minutes. As a result, a source electrode and a drain electrode were formed on the base material 100.

After the electrode forming step, in the semiconductor layer forming step, a semiconductor solution A1 (1 μL) containing CNTs shown in the first item of Example 1 is applied to the source electrode and drain electrode on the base material 100 by an inkjet method. The solution was added dropwise during the time and air-dried at 30°C for 10 minutes. Next, this air-dried semiconductor solution A1 was heat-treated on a hot plate at 150° C. for 30 minutes under a nitrogen stream. As a result, semiconductor layers of a plurality of FETs in the first region 110 and the second region 120 on the base material 100 were formed. At this point, these multiple FETs are p-type FETs with p-type characteristics.

After the semiconductor layer forming step, in the coating step, an electron-donating polymer (byck-chemy Japan Co., Ltd. BYK6919) was applied continuously under the conditions of 0.2 μL/piece by drop casting method. Thereby, the polymer was applied to the first region 110 so as to continuously cover all of the plurality of FETs. Subsequently, the coated polymer was heat treated at 150° C. for 30 minutes, thereby forming the second insulating layer 500 in the first region 110. All the FETs in the first region 110 had their original p-type characteristics modified to n-type characteristics by the second insulating layer 500 for the semiconductor layer, and as a result, they became n-type FETs. In Example 1, the semiconductor device 101 including the circuit of the ring oscillator 632 was obtained through the above steps.

In the first embodiment, 5.0 V is applied as a power supply voltage to the circuit of the semiconductor device 101 that constitutes the ring oscillator 632, and the waveform is observed with an oscilloscope (DSOX6002A manufactured by Keysight Technology) to determine the oscillation of the ring oscillator 632. I confirmed the operation. As a result, due to the second insulating layer 500 continuously formed over a plurality of FETs in the first region 110, the FET 200 in the first region 110 becomes an n-type FET, and the second insulating layer 500 on which the second insulating layer 500 is not formed becomes an n-type FET. It was confirmed that the FET 300 in the region 120 was a p-type FET.

<Example 2>
In this second embodiment, as illustrated in the first embodiment described above, a semiconductor device 101 including an n-type FET 200 and a p-type FET 300 is formed, and this semiconductor device 101 is used to construct a frequency dividing circuit. Created. FIG. 12 is a schematic plan view showing a configuration example of a frequency dividing circuit including a semiconductor device according to Embodiment 1 of the present invention. As shown in FIG. 12, this frequency dividing circuit 642 includes a D flip-flop 640. The D flip-flop 640 has a clock input terminal (CLK input terminal), a data input terminal (D terminal), an inverted output terminal (QB terminal), and an output terminal (Q terminal). The QB terminal and D terminal of the D flip-flop 640 are electrically connected by a wiring 641. When a clock signal is applied to the CLK input terminal, the D flip-flop 640 outputs a clock signal whose frequency is divided by two from the Q terminal.

The D flip-flop 640 uses a plurality of FETs 200 (n-type FET) in the first region 110 and a plurality of FETs 300 (p-type FET) in the second region 120 in the semiconductor device 101 illustrated in FIG. It is constructed by wiring and combining two FETs 200 and 300. By using the semiconductor device 101 having such a circuit configuration of a plurality of FETs 200 and 300, a frequency dividing circuit 642 as shown in FIG. 12 can be manufactured. Note that although the semiconductor device 101 that includes eight n-type FETs 200 and eight p-type FETs 300 is illustrated in FIG. Not limited. That is, the semiconductor device 101 applied to the frequency divider circuit 642 includes the necessary number of n-type FETs 200 and p-type FETs 300 to form the frequency divider circuit 642.

The method for manufacturing the semiconductor device in Example 2 was the same as the process shown in Example 1 described above. Further, in the second embodiment, as in the first embodiment, 5.0 V is applied as a power supply voltage to the circuit of the semiconductor device 101 constituting the frequency dividing circuit 642, and a predetermined frequency is applied to the CLK input terminal of the D flip-flop 640. It was confirmed that when a signal with an amplitude of 5.0V was inputted at the CLK input terminal, a signal was output from the Q terminal of the D flip-flop 640 at half the frequency of the signal inputted to the CLK input terminal. That is, normal frequency dividing operation of the frequency dividing circuit 642 could be confirmed.

<Example 3 and comparative example>
Example 3 and a comparative example with respect to Example 3 will be described. FIG. 13A is a schematic plan view showing a configuration example of a semiconductor device according to a comparative example with respect to the present invention. FIG. 13B is a schematic plan view showing a configuration example of a semiconductor device according to Example 3 of the present invention.

As shown in FIG. 13A, a semiconductor device 107 according to a comparative example includes a base material 100A and a plurality of FETs 206 and 302. The base material 100A is a base material formed of the same material as the base material 100 in the first embodiment described above, and includes a predetermined region 113 and a second region 122 on the base material surface. A plurality of FETs 206 are arranged in a predetermined area 113 of the base material 100A. Each of the plurality of FETs 206 includes a second insulating layer 513, and the second insulating layer 513 serves as an n-type FET. Furthermore, in the semiconductor device 107 according to the comparative example, the second insulating layer 513 is provided in the predetermined region 113 so as to cover each of the plurality of FETs 206 individually. On the other hand, a plurality of FETs 302 are arranged in the second region 122 of the base material 100A. Each of the plurality of FETs 302 is a FET without the second insulating layer 513, that is, a p-type FET. A semiconductor device 107 according to a comparative example was manufactured under the same conditions and method as in Example 1, except that the second insulating layer 513 was formed for each FET 206.

Further, as shown in FIG. 13B, the semiconductor device 108 according to the third embodiment includes a base material 100B and a plurality of FETs 206 and 302. Base material 100B is a base material formed of the same material as base material 100 in the first embodiment described above, and includes a first region 114 and a second region 122 on the base material surface. A plurality of FETs 206 are arranged in the first region 114 of the base material 100B, as in the above comparative example. In the third embodiment, each of the plurality of FETs 206 includes a second insulating layer 514, and the second insulating layer 514 makes the plurality of FETs 206 n-type FETs. Further, in the semiconductor device 108 according to the third embodiment, the second insulating layer 514 is disposed continuously over a plurality (for example, all the FETs 206) of the FETs 206 in the first region 114, and the second insulating layer 514 is arranged continuously over a plurality of (for example, all) the FETs 206 in the first region 114. covered. On the other hand, in the second region 122 of the base material 100B, a plurality of FETs 302 (p-type FETs) are arranged, similar to the above comparative example. A semiconductor device 108 according to Example 3 was manufactured under the same conditions and method as in Example 1.

In particular, in forming the second insulating layer 513 of the comparative example and the second insulating layer 514 of Example 3, a dispenser device (SHOTmini, ML-808-FX, manufactured by Musashi Engineering Co., Ltd.) was used to form the second insulating layer composition. A polymer having electron-donating properties (BYK6919, manufactured by BYK-Chemie Japan) was applied by discharging it onto each semiconductor element for 1.0 seconds. In this way, second insulating layers 513 and 514 were formed, respectively. When the second insulating layer composition (resin that becomes the second insulating layer) is applied under these conditions, the applied shape of the resin becomes circular or elliptical in plan view when viewed from the direction perpendicular to the surface of the base material. The diameter of the coated body obtained by discharging the resin once was about 1200 μm. Further, the accuracy of the center position of the second insulating layer, taking into account variations in the coating position of the resin, wetting and spreading of the resin, etc., was about ±400 μm.

In a comparative example, the semiconductor device 107 was manufactured with the inter-element distance L1 of the n-type FET 206 set to 2000 μm based on the knowledge of the size of the resin coating body mentioned above, the accuracy of the center position of the second insulating layer, and the like. Further, in Example 3, based on the above findings, the semiconductor device 108 was manufactured with the inter-element distance L2 of the n-type FET 206 set to 800 μm. These semiconductor devices 107 and 108 each have a circuit (ring oscillator circuit) including the ring oscillator 632 shown in FIG. 11. The conditions for discharging the polymer in forming the second insulating layers 513 and 514 were the same: 1.0 seconds per semiconductor element, and the polymer was discharged in a dotted manner directly above all the FETs 206 .

Among the semiconductor devices 107 and 108 manufactured in this manner, the second insulating layer 513 of the semiconductor device 107 according to the comparative example had an independent circular shape, as shown in FIG. 13A. In the base material 100A of this semiconductor device 107, the area of the predetermined region 113 occupied by the n-type FET 206 and the second insulating layer 513 was approximately 67.8 mm ² . On the other hand, as shown in FIG. 13B, the second insulating layer 514 of the semiconductor device 108 according to Example 3 had a shape integrated into a rounded rectangle across the plurality of FETs 206. In the base material 100B of this semiconductor device 108, the area of the first region 114 was approximately 18.4 mm ² . As can be seen by comparing the comparative example and the present example 3 as described above, in the semiconductor device 108 according to the present example 3, the second insulating layer 514 is continuous over a plurality of FETs 206 in the first region 114. Because of this arrangement, the area of the first region 114 occupied by these FETs 206 and the second insulating layer 514 could be significantly reduced compared to the predetermined region 113 of the semiconductor device 107 according to the comparative example. As a result, the size (base material area, IC chip area, etc.) of the semiconductor device 108 according to Example 3 was able to be reduced compared to the semiconductor device 107 according to the comparative example.

In addition, 5.0 V was applied as a power supply voltage to the ring oscillator circuits of these semiconductor devices 107 and 108, and the waveforms were observed using an oscilloscope (DSOX6002A manufactured by Keysight Technology) to confirm the oscillation operation of each ring oscillator circuit. did. As a result, it was confirmed that both ring oscillator circuits have equivalent circuit characteristics.

As described above, the present invention provides a semiconductor device, a wireless communication device, a sensor control device, and a method for manufacturing a semiconductor device. It is suitable for realizing a wireless communication device and a sensor control device using the device.

10, 100, 100A, 100B Base material 11, 101-108 Semiconductor device 20 n-type FET
30 p-type FET
50 N-type modified polymer 110-112, 114 First region 113 Predetermined region 120-122 Second region 130, 131 Third region 200-206, 300-302 FET
210, 310 source electrode 220, 320 drain electrode 230, 330 gate electrode 250, 350 gate insulating layer 270, 370 semiconductor layer 500, 510 to 514, 550 second insulating layer 520, 521 third insulating layer 560 overcoat layer 600 inverter 601 Clock generation circuit 602 FET
603 Capacitor 611, 612, 613, 631 Inverter 632 Ring oscillator 640 D flip-flop 641 Wiring 642 Frequency divider circuit 700 Wireless communication device 701 Antenna 702 Rectifier circuit 703 Power generation section 704 Logic circuit 705 Memory circuit 706 Output section L1, L2 between elements distance

Claims (19)

A semiconductor device comprising, on a base material, at least a first region in which two or more semiconductor elements are arranged, and a second region in which one or more semiconductor elements are arranged,
The semiconductor element in the first region is
a source electrode in the first region, a drain electrode in the first region, a gate electrode in the first region, and the first electrode in contact with the source electrode in the first region and the drain electrode in the first region. a semiconductor layer in the region, and a gate insulating layer in the first region that insulates the semiconductor layer in the first region and the gate electrode in the first region;
a second insulating layer in contact with the semiconductor layer in the first region at a position different from the gate insulating layer in the first region;
on the base material,
The semiconductor element in the second region is
a source electrode in the second region, a drain electrode in the second region, a gate electrode in the second region, and a second electrode in contact with the source electrode in the second region and the drain electrode in the second region. and a gate insulating layer in the second region that insulates the semiconductor layer in the second region and the gate electrode in the second region, on the base material,
The electrical conductivity of the semiconductor element in the first region is different from the electrical conductivity of the semiconductor element in the second region due to the second insulating layer,
the second insulating layer is continuously arranged over two or more semiconductor elements in the first region;
A semiconductor device characterized by: further comprising a third region where two or more semiconductor elements are arranged on the base material,
The semiconductor element in the third region is
a source electrode in the third region, a drain electrode in the third region, a gate electrode in the third region, and a third region in contact with the source electrode in the third region and the drain electrode in the third region. a semiconductor layer in the region, and a gate insulating layer in the third region that insulates the semiconductor layer in the third region and the gate electrode in the third region;
a third insulating layer in contact with the semiconductor layer in the third region at a position different from the gate insulating layer in the third region;
Equipped with
The composition constituting the second insulating layer and the composition constituting the third insulating layer are different from each other,
The semiconductor device according to claim 1, characterized in that: A plurality of the second insulating layers are arranged in the first region so as to have a long and short shape,
The longitudinal directions of the plurality of second insulating layers are each in the same direction,
The semiconductor device according to claim 1, characterized in that: The second insulating layer and the third insulating layer are each arranged to have a shape having a length and a length,
The longitudinal direction of the second insulating layer and the longitudinal direction of the third insulating layer are the same direction,
The semiconductor device according to claim 2, characterized in that: The semiconductor layer on the base material contains any one or more semiconductor materials selected from carbon nanotubes, carbon nanocoils, fullerenes, graphene, and nanodiamonds.
The semiconductor device according to any one of claims 1 to 4, characterized in that: The semiconductor layer on the base material contains carbon nanotubes.
The semiconductor device according to claim 5, characterized in that: The second insulating layer contains an electron-donating compound having one or more selected from nitrogen atoms and phosphorus atoms.
The semiconductor device according to any one of claims 1 to 6, characterized in that: The difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is a difference in threshold voltage of the transistor,
The semiconductor device according to any one of claims 1 to 7, characterized in that: The difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is a difference in conductivity type of the transistor,
The semiconductor device according to any one of claims 1 to 7, characterized in that: The difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is a difference in electrical conductivity with respect to ambient temperature.
The semiconductor device according to any one of claims 1 to 7, characterized in that: The difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is a difference in electrical conductivity with respect to ambient humidity.
The semiconductor device according to any one of claims 1 to 7, characterized in that: The difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is a difference in electrical conductivity with respect to the wavelength of incident light.
The semiconductor device according to any one of claims 1 to 7, characterized in that: The difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is a difference in electrical conductivity with respect to the amount of incident light.
The semiconductor device according to any one of claims 1 to 7, characterized in that: The difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is a difference in electrical conductivity with respect to the amount of oxygen.
The semiconductor device according to any one of claims 1 to 7, characterized in that: The electrical conductivity of the semiconductor element in the third region is different from the electrical conductivity of the semiconductor element in the second region due to the third insulating layer,
The difference in electrical conductivity between the semiconductor element in the first region and the semiconductor element in the second region is a difference in conductivity type of the transistor,
The difference in electrical conductivity between the semiconductor element in the third region and the semiconductor element in the second region is a difference in threshold voltage of the transistor,
The semiconductor device according to claim 2 or 4, characterized in that: A semiconductor device manufacturing method for manufacturing the semiconductor device according to any one of claims 1 to 15, comprising:
a coating step of continuously coating a composition for forming the second insulating layer over two or more semiconductor elements in the first region;
A method for manufacturing a semiconductor device, characterized in that: In the coating step, the composition is coated by any one of an inkjet method, a nozzle coating method, a screen printing method, an offset printing method, or a drop cast coating method to form the second insulating layer.
17. The method of manufacturing a semiconductor device according to claim 16. comprising the semiconductor device according to any one of claims 1 to 15,
A wireless communication device characterized by: comprising the semiconductor device according to any one of claims 1 to 15,
A sensor control device characterized by:

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