CN101136408A - CMOS circuit based on semi-conductor nano material and preparation therefor - Google Patents
CMOS circuit based on semi-conductor nano material and preparation therefor Download PDFInfo
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Abstract
This invention puts forward a simple preparing and integrating method for realizing high performance CMOS circuit not doped on one-dimensional semiconductor nm material, in which, the p-type field effect transistor in the CMOS circuit is realized by controlling a metal electrode of high power function to exchange electrons with the valence band of carbon nm tube or other one-dimensional nm materials, the n-type field effect transistor is realized by controlling a metal electrode of low power function to exchange electrons with the conduction band of a carbon nm tube or other one-dimensional semiconductor nm materials directly, besides, this invention applies a back grid and a top grid to realize a basic logic circuit or even more complicated logic circuit of inverters, AND-NOT gates, NOR gates and full-adders.
Description
Technical field
The invention belongs to the nano-electron field, particularly a kind of with monodimension nanometer material particularly carbon nano-tube be nanometer complementary field-effect transist (CMOS) circuit and the technology of preparing thereof of base.
Background technology
Current is that the progress of the microelectric technique of main flow has benefited from by a certain percentage device being dwindled to a great extent with the silicon base CMOS.Device is more little, and performance and integrated level are all high more, the also corresponding reduction of price, and it is constantly progressive forward that these advantages are promoting microelectronics industry.But along with device dimension enters sub-micron, the difficulty that the raising of depending merely on the P/C ratio that the reduction of device yardstick obtained no longer can balance brings thus.One of wherein the most serious problem is exactly the homogeneity question of small size device.Though have the report of the silicon-based field-effect transistors of 10 nanoscales successfully at present, because the error resulting devices size of process technology can not be the size of single strictness.For example the channel length of 10 nano field-effect transistors of Pi Liangshengchaning can not strictness be 10 nanometers, and the error of 10-20% is probably inevitable.In addition, the electric property of semiconductor device is controlled by mixing substantially at present.But, along with reducing of device size, can reduce to tens to hundreds of at the impurity number of several active areas to tens nanometers, statistic fluctuation may also can reach tens percent to the inhomogeneities that device performance brings on this size.How to overcome the inhomogeneities of nano-device, become the nanoelectronic integrated circuit and further develop the subject matter that is faced.
Can controllably prepare monodimension nanometer materials such as yardstick homogeneous semiconductor nano wire, pipe, band under certain conditions by chemical method, and these nano materials can be linked to each other with metal electrode and prepare the field-effect transistor of similar extensive use in integrated circuit at present.Wherein carbon nano tube structure is the most perfect for this, because the surface does not have dangling bonds, the mobility of electronics is much better than all known semiconductor materials.H.J.Dai seminar of U.S. Standford university adopts Metal Palladium (Pd), and material preparation has gone out high performance carbon nano-tube p type field-effect transistor [A.Javey, J.Guo, Q.Wang as contact electrode, M.Lundstrom, H.Dai, Nature, 424,654 (2003)].Prepare n type field-effect transistor method at present commonly used and mainly contain (1) carbon nano-tube mix [A.Javey, R.Tu, D.B.Farmer, J.Guo, R.G. Gordon, and H.Dai, Nano Lett, 5,345 (2005)].But because carbon nano tube surface is difficult and foreign atom forms very strong valence link combination and do not influence its carrier mobility, the performance or the stability of the n type field-effect transistor that doping method commonly used at present prepares are not fine, device must be in certain chemical environment could operate as normal, be unfavorable for the integrated and general application of device.(2) adopt low work function (less than 4.7 electron-volts) metal (as Al, Mg, Ca) [Y. Nosho, Y. Ohno, S.Kishimoto, T.Mizutani, Nanotechnology, 17,3412 (2006), Ali Javey, Qian Wang, Woong Kim, and Hongjie Dai, IEEE IEDM2003] realize that as electrode material metal contacts with the n type of carbon nano-tube conduction band.But poor-performing, particularly switch current ratio and the ON state current value of the n type device that obtains by this method are all smaller.The people such as Liang Xuelei (Chinese invention patent application, application number 200710090362.4) of Peking University adopt metal scandium (Sc) to prepare the carbon nano-tube n type field-effect transistor of performance near theoretical limit as electrode material recently.
Adopt the integrated circuit of complementary field-effect transist (CMOS) structure to have integrated level height, advantage such as low in energy consumption, it will be the first-selected structure of nanometer integrated circuit, how preparing the cmos circuit based on nano material simply, is that the nanometer integrated circuit really moves towards to use the problem that at first must solve.The Avouris of IBM Corporation group adopts the vacuum annealing technology to prepare n type field-effect transistor [V.Derycke, R.Martel, J.Appenzeller, and Ph.Avouris, NanoLetters, 1,453 (2001)], obtained cmos circuit on this basis, still wherein the performance of n type and p type field-effect transistor is all very low, and n type device instability.H.J.Dai seminar of U.S. Standford university adopts big electric current calcining that part p type field-effect transistor is converted to the n type, thereby obtain cmos circuit [A.Javey, Qian Wang, Ant Ural, Yiming Li, H.Dai, NanoLetters, 2,929 (2002)], but p type that obtains and n type device performance be coupling very, and this method to be not suitable for scale fully integrated.Complementary field-effect transist (CMOS) circuit lays the foundation the result in these early stages in order to prepare efficiently.
Summary of the invention
The object of the present invention is to provide a kind of cmos circuit and technology of preparing thereof of based semiconductor nano material, wherein, conductive channel is the semiconductor nano material of one dimension, and by adopting different metal electrodes to contact the polarity of controlling filed effect transistor.
Below, characteristics of the present invention and principle will mainly be set forth by the cmos circuit based on carbon nano-tube, but its range of application is not limited to carbon nano-tube, and basic operation principle is suitable equally for other cmos circuits based on monodimension nanometer material.
P type field-effect transistor in the cmos circuit of the present invention is that the valence band exchange electronics of and carbon nano-tube or other one dimension semiconductor nano material direct by the electrode (for example Pd electrode) of control high work function is realized, n type field-effect transistor then is that the conduction band exchange electronics of and carbon nano-tube or other one dimension semiconductor nano material direct by the electrode (for example Sc electrode) of control low work function is realized.Said high-work-function metal is meant that work function is higher than the metal of the semiconductor nano material Fermi level of its contact among the present invention, and same, low workfunction metal is meant that work function is lower than the metal of the semiconductor nano material Fermi level of its contact.
The conductive channel of field-effect transistor involved in the present invention is semiconductor carbon nanometer tube or other one dimension semiconductor nano material of Intrinsical, no matter p type or the realization of n type field-effect transistor does not need this conductive channel is mixed.When transistor is worked, be not to be that carbon nano-tube or semiconductor nano material are provided by transistorized charge carrier by conductive channel, but depend on the electrode pair conductive channel injection efficiency determined.For example by adopting metal scandium (Sc) as the source, the drain electrode that are connected with carbon nano-tube, the conduction band of electrode and carbon nano-tube can be realized without hindrance ohmic contact.Even under the condition of low bias voltage and low temperature, the source electrode also can inject electronics to carbon nano-tube effectively, and it is the n type that transistorized field effect is revealed as electron type.Similarly, by adopting metal Pd as the source, the drain electrode that are connected with carbon nano-tube, the valence band of electrode and carbon nano-tube can realize without hindrance ohmic contact, and the source electrode also can be effectively to the carbon nano-tube injected hole, and it is the p type that transistorized field effect is revealed as cavity type.No matter the electron type or the transistor of cavity type, the doping content of its device current fundamental sum carbon nano-tube in working order the time is irrelevant, mainly the work function by the electrode material that is adopted is determined, the metal electrode that is high work function can be realized the field effect of p type, and the metal of low work function can be realized the field effect of n type.
The present invention proposes directly to adopt suitable metal material can realize the cmos circuit function as electrode on the one dimension semiconductor nano material of intrinsic: the metal of employing high work function and one dimension semiconductor nano material are set up electrode and are got in touch formation p type field-effect transistor, and the metal that adopts low work function and one dimension semiconductor nano material are set up electrode and are got in touch and form n type field-effect transistor, according in advance circuit design source, drain electrode and gate electrode are coupled together the certain circuit of formation then.Required circuit can be achieved on one or more one dimension semiconductor nano material.Fig. 1 a is the schematic diagram that an employing bottom gate the simplest is realized the CMOS inverter circuit.N type FET (field-effect transistor) in this circuit realizes that by setting up with getting in touch of Sc electrode at the two ends of one section carbon nano-tube the Sc electrode of rightmost ground connection is the source electrode among the figure, and the Sc electrode on the left side is a drain electrode; P type FET is that the two ends by the one section carbon nano-tube on hand that keeps left are in the drawings set up with getting in touch of Pd electrode and realized, Far Left meets high-order voltage (V for example among the figure
DD=5V) Pd electrode is the source electrode, and the Pd electrode on the right is a drain electrode.The input-output curve that Fig. 1 b obtains for the CMOS inverter experiment measuring that adopts prepared of the present invention to come out from.
Above-mentioned set up the method that electrode gets in touch can be between metal and one dimension semiconductor nano material: at first form the shape of electrode around the one dimension semiconductor nano material by photoetching, the evaporation layer of metal be peeled off then and is removed unwanted metal level again.With top grid cmos circuit is example, and concrete preparation process is as follows:
1. by located growth, perhaps scattered one dimension semiconductor nano material solution is dripped to and obtain one or more parallel one dimension semiconductor nano material on the markd substrate;
2. note the particular location of nano material by ESEM or atomic force microscope observation;
3. photoetching forms the shape of grid;
4. sample is put into the high k top gate medium layer of growth in the atomic layer deposition system;
5. sample is put in the acetone and peeled off, perhaps use corroding method, remove unwanted dielectric layer;
6. photoetching forms source, the leakage of p type FET or n type FET, the shape of gate electrode;
7. evaporation metal Pd or Sc;
8. sample is put in the acetone and peeled off, remove p type FET or n type FET that unwanted metal level promptly obtains top gate structure;
9. repeating step 6～8 prepares all required p type FET and n type FET;
10. adopt interconnection technique that source, drain electrode and gate electrode are coupled together and to obtain cmos circuit based on the one dimension semiconductor nano material.
Method of the present invention is simple, practical.For example the preparation of CMOS inverter has as shown in Figure 1 only related to according to certain figure to carbon nano-tube evaporation metal Sc and Pd film, and traditional CMOS microelectronic technique comprises complicated technology of tens steps, and particularly difference is repeatedly injected the doping process of degree.Simultaneously greatly to have reduced conductive channel be the scattering of the charge carrier in the carbon nano-tube owing to removed the doping step, improved corresponding carrier mobility, improved the performance of device.
The operation principle that the present invention relies on is come the carrier type of trim for selecting to regulate electrode material.Simply, the metal of high work function is used to prepare the p transistor npn npn, and low workfunction metal is used to prepare the n transistor npn npn.But in the preparation of traditional flat field effect electronic device,, use the different metal electrode less for the field effect behavioral implications of traditional FET owing to the strong pinning effect of surface state for the metal Fermi surface.Adopt monodimension nanometer material very different with the conventional planar device as the situation of conductive channel.The special geometry of one-dimensional material has guaranteed that the conductive channel material reduces greatly for the pinning effect of the Fermi level of metal electrode, makes the metal electrode might to control the polarity of FET fully.The uniformity that adopts the cmos device of the inventive method preparation mainly is by the uniformity decision of nano material.The present invention emphasizes the integrated integrated circuit that goes out certain complexity on the uniform monodimension nanometer material of single size.With the carbon nano-tube is example, at present existing about centimetre in addition the report of the controlledly synthesis of the carbon nano-tube of decimeter length.The width of supposing electrode is 30 nanometers, and conductive channel length is the 20-30 nanometer, and the size of single transistor can be controlled at 0.1 micron scope.Can be integrated on the carbon nano-tube of a centimeter length go out 100,000 transistors, can reach the scale of ultra-large integrated circuit.Because the mean free path of monodimension nanometer material is generally greater than tens nanometers (being the yardstick of the conductive channel of device), the transport property of device is that the length of trajectory and concrete conductive channel is irrelevant substantially.These factors have guaranteed to adopt the uniformity of the prepared cmos device of the technology of the present invention.
Owing to need not to mix, the performance that adopts the carbon nano-tube cmos device that the inventive method prepares is the high performance device near theoretical limit, and it mainly is by the number decision of the quantum subband that participates in conduction that its ON state electricity is led.Under little bias condition the number of sub-bands of Single Walled Carbon Nanotube be 2 and caliber irrelevant.The quantized restriction of this device performance has further guaranteed the uniformity of device.For the concrete preparation of device, this quantum condition has guaranteed based on the uniformity between the carbon nano tube device of different tube diameters.It is best that the n type of the formation cmos circuit among the present invention and p type field-effect transistor performance can both reach, and mutual ON state electricity leads very coupling, and this makes the overall performance of circuit reach best.
Description of drawings
Fig. 1 a is with SiO
2Structural representation for the carbon nano-tube CMOS inverter of bottom grating structure;
Fig. 1 b is the input-output voltage curve of carbon nano-tube CMOS inverter shown in Fig. 1 a of experiment measuring.
Fig. 2 is to be the transfer characteristic figure of p type Single Walled Carbon Nanotube (diameter is about 2nm) field-effect transistor of the bottom grating structure of source-drain electrode with Pd.
Fig. 3 is to be the transfer characteristic figure of n type Single Walled Carbon Nanotube (diameter is about 2nm) field-effect transistor of the bottom grating structure of source-drain electrode with Sc.
Fig. 4 a is based on the structural representation of the top grid CMOS inverter of two carbon nano-tube; Fig. 4 b is the corresponding circuit diagram of Fig. 4 a.
Fig. 5 is based on the structural representation of the top grid CMOS inverter of single-root carbon nano-tube.
Fig. 6 a is based on the structural representation of the top grid cmos nand gate of two carbon nano-tube; Fig. 6 b is the corresponding circuit diagram of Fig. 6 a.
Fig. 7 is based on the structural representation of the top grid cmos nand gate of single-root carbon nano-tube.
Fig. 8 a is based on the structural representation of the top grid CMOS NOR gate of two carbon nano-tube; Fig. 8 b is the corresponding circuit diagram of Fig. 8 a.
Fig. 9 is based on the structural representation of the top grid CMOS NOR gate of single-root carbon nano-tube.
Figure 10 is based on the structural representation of the top grid CMOS full adder of double joint carbon nano-tube.
Embodiment
Below in conjunction with accompanying drawing, further describe the present invention by embodiment, but do not limit the present invention in any way.
Embodiment 1: be the Single Walled Carbon Nanotube CMOS inverter and the preparation thereof of the bottom grating structure of source-drain electrode with Pd and Sc
As shown in Figure 1a with SiO
2For gate medium, with Si is the Single Walled Carbon Nanotube CMOS inverter of back of the body grid.The left side is source (left side) with Pd and leaks (right side) electrode material, adds two carbon nano-tube between the electrode, has constituted a p type FET.The right is source (right side) with Sc and leaks (left side) electrode material, adds two carbon nano-tube between the electrode, has constituted a n type FET.As shown in the figure, the drain electrode of p type FET and the drain electrode of n type FET are linked to each other, its current potential is the output voltage of inverter.The common bottom gate voltage of p type FET and n type FET as input voltage vin, has so just been constituted a CMOS inverter circuit.Concrete preparation process is as follows:
1. by located growth, perhaps scattered carbon pipe solution is dripped on the markd substrate, thereby obtaining to be positioned at is dispersed in Si/SiO
2Carbon nano-tube on the substrate;
2. by ESEM or atomic force microscope observation, note the particular location of carbon nano-tube;
3. resist coating also passes through the shape that optical exposure or electron beam lithography form p type FET electrode on substrate;
4. the sample that photoetching is good is put in electron beam or the thermal evaporation system, is evacuated to 3 * 10
-8About Torr, with the thick metal Pd film of speed evaporation one deck 30nm of 1A/s;
5. sample is put in the acetone and peeled off, remove unwanted metal level and promptly obtain with SiO
2For gate medium, with Si is the carbon nano-tube p type FET of back grid structure.
6. repeat the 3-5 step, the shape of definition n type FET electrode in step 3, the thick metal Sc of evaporation one deck 30nm in step 4.
7. the drain electrode that connects n type FET and p type FET is to output, and bottom gate thin film is finished the preparation of inverter to input.
The input-output voltage curve of the inverter circuit of preparing with said method is shown in Fig. 1 b.When input voltage is positioned at logical zero (less than-2.5 volts), output voltage is positioned at logical one (greater than 4 volts).When input voltage is positioned at logical one (greater than-1.5 volts), output voltage is positioned at logical zero (less than 1 volt).The voltage amplification factor of inverter is 11 near inverter threshold shift voltage (～-2.2 volts).These results show and need not to mix, and adopt method of the present invention can prepare the cmos circuit of excellent performance.
Embodiment 2: the carbon nano-tube CMOS inverter of top gate structure
As Fig. 4 a and shown in Figure 5, can adopt step similar to Example 1 to prepare the CMOS inverter of top gate structure.Concrete preparation comprises the following steps:
1. by located growth, perhaps scattered carbon pipe solution is dripped to and obtain to be positioned at Si/SiO on the markd substrate
2The carbon nano-tube that on the substrate one or more is parallel;
2. note the particular location of carbon nano-tube by ESEM or atomic force microscope observation;
3. resist coating also passes through the shape that optical exposure or electron beam lithography form grid on substrate;
4. sample is put into growth one deck gate dielectric layer (ZrO in the atomic layer deposition system
2, Al
2O
3Or HfO
2), growth temperature is not higher than 170 degrees centigrade;
5. sample is put in the acetone and peeled off, perhaps use corroding method, remove unwanted dielectric layer;
6. resist coating and form source, the leakage of n type FET or p type FET, the shape of gate electrode by optical exposure or electron beam lithography;
7. the sample that photoetching is good is put in the electron beam evaporation system, is evacuated to 3 * 10
-8About Torr, prepare n type FET or metal Pd is used to prepare p type FET with the thick metal Sc of speed evaporation one deck 30nm of 1A/s;
8. sample is put in the acetone and peeled off, remove carbon nano-tube n type FET or p type FET that unwanted metal level promptly obtains top gate structure;
9. repeating step 6～8 prepares all required n type FET and p type FET;
10. source, drain electrode and gate electrode can be obtained CMOS inverter based on 2 and 1 carbon nano-tube as Fig. 4 a and shown in Figure 5 coupling together respectively.
Embodiment 3: the carbon nano-tube cmos nand gate circuit of top gate structure
As Fig. 6 a and shown in Figure 7, can adopt step similar to Example 2 to prepare the carbon nano-tube n type FET and the p type FET of top gate structure respectively, can obtain cmos nand gate circuit as Fig. 6 a and shown in Figure 7 source, drain electrode and gate electrode are coupled together as shown in the figure respectively based on 2 and 1 carbon nano-tube.
Embodiment 4: the carbon nano-tube CMOS OR-NOT circuit of top gate structure
As Fig. 8 a and shown in Figure 9, can adopt step similar to Example 2 to prepare the carbon nano-tube n type FET and the p type FET of top gate structure respectively, can obtain CMOS OR-NOT circuit as Fig. 8 a and shown in Figure 9 source, drain electrode and gate electrode are coupled together as shown in the figure respectively based on 2 and 1 carbon nano-tube.
Embodiment 5: the carbon nano-tube CMOS full adder of top gate structure
As shown in figure 10, can adopt step similar to Example 2 to prepare the carbon nano-tube n type FET and the p type FET of top gate structure respectively, source, drain electrode and gate electrode be coupled together as shown in the figure can obtain CMOS full adder as shown in figure 10 based on 4 carbon nano-tube.
The foregoing description all is by being that the device architecture of conductive channel is set forth with the carbon nano-tube, but the inventive method is not limited in the carbon nano-tube cmos device, can be used to prepare the cmos circuit based on other semiconductor nanowires, pipe, band.The present invention also is not limited only to certain several device architecture, and any CMOS technology based on marrow correct of the present invention all belongs to category of the present invention.
Claims (10)
1. nanometer complementary field-effect transist circuit, its conductive channel is the one dimension semiconductor nano material of Intrinsical, wherein: p type field-effect transistor is made up of with the metal electrode of the high work function that directly contacts with it one section one dimension semiconductor nano material; N type field-effect transistor is made up of with the metal electrode of the low work function that directly contacts with it one section one dimension semiconductor nano material.
2. nanometer complementary field-effect transist circuit according to claim 1 is characterized in that: described one dimension semiconductor nano material is a carbon nano-tube.
3. nanometer complementary field-effect transist circuit according to claim 2 is characterized in that: the metal electrode of described high work function is the Pd electrode.
4. nanometer complementary field-effect transist circuit according to claim 2 is characterized in that: the metal electrode of described low work function is the Sc electrode.
5. the preparation method of a nanometer complementary field-effect transist circuit, with the one dimension semiconductor nano material is conductive channel, adopt the metal of high work function to set up electrode and get in touch formation p type field-effect transistor as contact electrode material and one dimension semiconductor nano material, and the metal that adopts low work function is set up electrode as contact electrode material and one dimension semiconductor nano material and is got in touch formation n type field-effect transistor, according to circuit design each transistorized source, drain electrode is connected with gate electrode then.
6. the preparation method of nanometer complementary field-effect transist circuit according to claim 5 is characterized in that: described one dimension semiconductor nano material is a carbon nano-tube.
7. the preparation method of nanometer complementary field-effect transist circuit according to claim 6 is characterized in that: the metal of described high work function is Pd.
8. the preparation method of nanometer complementary field-effect transist circuit according to claim 7 is characterized in that: the metal of described low work function is Sc.
9. according to the preparation method of the described nanometer complementary field-effect transist of arbitrary claim circuit in the claim 5～8, it is characterized in that, setting up the method that electrode gets in touch between metal and one dimension semiconductor nano material is: the shape that at first forms electrode by photoetching around the one dimension semiconductor nano material, the evaporation layer of metal is peeled off then and is removed unwanted metal level again.
10. the preparation method of nanometer complementary field-effect transist circuit according to claim 9 is characterized in that, specifically comprises the steps:
1), perhaps scattered one dimension semiconductor nano material solution is dripped to and obtain one or more parallel one dimension semiconductor nano material on the markd substrate by located growth;
2) note the particular location of nano material by ESEM or atomic force microscope observation;
3) photoetching forms the shape of grid;
4) sample is put into the high k top gate medium layer of growth in the atomic layer deposition system;
5) sample is put into peel off in the acetone or with the corrosion way remove unwanted dielectric layer;
6) shape of the source of photoetching formation p type field-effect transistor or n type field-effect transistor, leakage, gate electrode;
7) evaporation metal Pd or Sc;
8) sample is put in the acetone peeled off, remove p type or n type field-effect transistor that unwanted metal level promptly obtains top gate structure;
9) repeating step 6)～8) prepare all required p types and n type field-effect transistor;
10) adopt interconnection technique that source, drain electrode and gate electrode are coupled together and to obtain complementary field-effect transist circuit based on the one dimension semiconductor nano material.
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| WO2021056785A1 (en) * | 2019-09-23 | 2021-04-01 | 深圳市华星光电半导体显示技术有限公司 | Inverter manufacturing method and inverter |
| CN111584484B (en) * | 2019-12-24 | 2023-09-29 | 苏州大学 | Low-voltage, low-power complementary circuit, inverter and NAND device |
| CN111584484A (en) * | 2019-12-24 | 2020-08-25 | 苏州大学 | Low-voltage and low-power complementary circuit, phase inverter and NAND device |
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