JP7314917B2 - Multilayer ceramic capacitor - Google Patents

Description

The present invention relates to a multilayer ceramic capacitor.

In recent years, efforts have been made to reduce the size and increase the capacity of laminated ceramic electronic components such as laminated ceramic capacitors. In order to reduce the size and increase the capacity of a multilayer ceramic capacitor, it is effective to increase the area of the internal electrode layers facing each other by thinning the side margins for each side surface of the laminate in which a plurality of dielectric ceramic layers and a plurality of internal electrode layers are laminated.

Patent Document 1 discloses a method of manufacturing an electronic component, comprising the steps of: preparing a chip including a plurality of laminated dielectric ceramic layers and a plurality of internal electrode layers, with the plurality of internal electrode layers exposed on the side; forming a dielectric laminated sheet by bonding a plurality of coating dielectric sheets together; and bonding the dielectric laminated sheet to the side surface of the chip.

In addition, Patent Document 2 discloses that when a multilayer ceramic capacitor is manufactured by laminating, pressing, and firing a plurality of ceramic green sheets on which internal electrodes are printed, it is possible to prevent the occurrence of a step between a portion where the internal electrodes overlap and a portion where the internal electrodes do not overlap by applying a ceramic slurry for eliminating the step to a region where the internal electrodes are not printed.

JP 2017-147358 A JP-A-2003-209025

However, Document 1 does not particularly mention the composition of the ceramic dielectric sheet to be attached to the side surface of the laminate. Moreover, the composition of the step-removing ceramic paste used in Cited Document 2 is not particularly mentioned. Therefore, in Patent Documents 1 and 2, there is room for improving the reliability of the multilayer ceramic capacitor by optimizing the composition of the dielectric multilayer sheet and the step-removing ceramic paste.
In addition, since an electric field concentrates on the end portion of the internal electrode adjacent to the step-resolving ceramic paste described in Patent Document 2, there is a possibility that the reliability is lowered.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer ceramic capacitor capable of improving reliability by suppressing electric field concentration at least at the ends of internal electrodes.

A laminated ceramic capacitor of the present invention is a laminated ceramic capacitor comprising a laminated body including a dielectric ceramic layer and an internal electrode layer, which are laminated in the lamination direction, and an external electrode connected to the internal electrode layer, wherein the laminated body has first and second principal surfaces facing each other in the lamination direction, first and second side faces facing each other in the width direction perpendicular to the lamination direction, first and second end faces facing each other in the length direction perpendicular to the lamination direction and the width direction, wherein the internal electrode layers include a first internal electrode layer drawn out to the first end face and a second internal electrode layer drawn out to the second end face so as to face the first internal electrode layer through the dielectric ceramic layer, the external electrode being arranged on the first end face and connected to the first internal electrode layer; and a second external electrode connected to the dielectric ceramic layer, wherein the dielectric ceramic layer comprises a first dielectric ceramic layer and a second dielectric ceramic layer, wherein the first dielectric ceramic layer is arranged between the first internal electrode layer and the second internal electrode layer, and the second dielectric ceramic layer includes a region where the internal electrode layer is not arranged between the first dielectric ceramic layers facing each other via the internal electrode layer, and a part of the first dielectric ceramic layer. The laminate has an inner layer portion in which the first internal electrode layers and the second internal electrode layers are alternately laminated with the dielectric ceramic layers interposed therebetween; an outer layer portion arranged to sandwich the inner layer portion in the lamination direction and made of a ceramic material; and a third dielectric ceramic layer arranged to sandwich the inner layer portion and the outer layer portion in the width direction and made of a dielectric ceramic material, In a plane including the length direction and the width direction, the second dielectric ceramic layer, the first internal electrode layer or the second internal electrode layer, and the third dielectric ceramic layer form an interface intersection, the second dielectric ceramic layer and the third dielectric ceramic layer each include an intersection vicinity region near the intersection, and the average particle diameter of the dielectric particles contained in the intersection vicinity region is the average of the dielectric particles contained in the first dielectric ceramic layer. It is smaller than the average particle size of any of the particle size, the average particle size of the dielectric particles contained in the second dielectric ceramic layer, and the average particle size of the dielectric particles contained in the third dielectric ceramic layer.

ADVANTAGE OF THE INVENTION According to this invention, the multilayer ceramic capacitor which can suppress the electric field concentration to the edge part of an internal electrode at least, and can improve reliability can be provided.

1 is a perspective view schematically showing an example of a laminated ceramic capacitor of the present invention; FIG. FIG. 2 is a perspective view schematically showing an example of a laminate constituting the laminated ceramic capacitor shown in FIG. 1; FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along the line AA; 2 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along the line CC. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along the line BB. FIG. 1 is a plan view schematically showing an example of a ceramic green sheet; FIG. 1 is a plan view schematically showing an example of a ceramic green sheet; FIG. 1 is a plan view schematically showing an example of a ceramic green sheet; FIG. 1 is an exploded perspective view schematically showing an example of a mother block; FIG. 1 is a perspective view schematically showing an example of a green chip; FIG. FIG. 2 is a part of the LT cross section of the multilayer ceramic capacitor of the present invention and schematically shows a first alloy portion and a second alloy portion; FIG. 12 is a partially enlarged view of FIG. 11; FIG. 2 is a part of the LT cross section of the multilayer ceramic capacitor of the present invention and schematically shows first interspersed internal electrodes, second interspersed internal electrodes and fourth alloy parts. FIG. 2 is a part of the WT cross section of the multilayer ceramic capacitor of the present invention and schematically shows a first alloy portion and a third alloy portion; FIG. 15 is a partially enlarged view of FIG. 14 and schematically showing a fifth alloy portion; FIG. 4 is a cross-sectional view schematically showing a mode in which the end portions of the second dielectric ceramic layers are superimposed on the end portions of the internal electrode layers in the multilayer ceramic capacitor of the present invention; FIG. 4 is a cross-sectional view schematically showing a mode in which the end portions of the second dielectric ceramic layers are superimposed on the end portions of the internal electrode layers in the multilayer ceramic capacitor of the present invention; FIG. 4 is a diagram for explaining a TEM analysis method for analyzing the amount of metal elements contained in the internal electrode layers of the multilayer ceramic capacitor of the present invention; FIG. 6 is a part of FIG. 5 showing the intersection neighborhood region of the present invention; FIG. 3 is a diagram for explaining a method of measuring the average particle size of dielectric particles contained in a first dielectric ceramic layer and a third dielectric ceramic layer; FIG. 4 is a diagram for explaining a method of measuring the average particle size of dielectric particles contained in a third dielectric ceramic layer; FIG. 4 is a diagram for explaining the first step of the method of measuring the average particle size of dielectric particles contained in the second dielectric ceramic layer and the region near the intersection; FIG. 4 is a diagram for explaining the second step of the method for measuring the average particle size of dielectric particles contained in the second dielectric ceramic layer and the region near the intersection; FIG. 4 is a diagram for explaining a method of measuring the average particle size of dielectric particles contained in an intersection vicinity region; FIG. 4 is a diagram schematically showing a step of removing side surfaces of an unfired laminate in the method of manufacturing a multilayer ceramic capacitor of the present invention; FIG. 4 is a view showing an end surface of an unfired laminate with side surfaces removed in the manufacturing method of the multilayer ceramic capacitor of the present invention; FIG. 4 is a cross-sectional view schematically showing a mode in which the end portions of the second dielectric ceramic layers are superimposed on the end portions of the internal electrode layers in the manufacturing method of the laminated ceramic capacitor of the present invention; FIG. 4 is a view schematically showing a missing portion of the second dielectric ceramic layer, which is a part of the WT cross section of the multilayer ceramic capacitor of the present invention. FIG. 29 is a sectional view taken along line KK of FIG. 28; 1 is a diagram schematically showing a first segregation, which is a part of the LT cross section of the multilayer ceramic capacitor of the present invention; FIG. 31 is a partially enlarged view of FIG. 30; FIG. FIG. 4 is a view schematically showing a second segregation, which is a part of the WT cross section of the multilayer ceramic capacitor of the present invention. FIG. 4 is a part of the LW cross section of the multilayer ceramic capacitor of the present invention, showing third segregation segregating in the first corner region and the second corner region; FIG. 4 is a cross-sectional view schematically showing a mode in which the end portion of the second dielectric ceramic layer overlaps the third segregation in the multilayer ceramic capacitor of the present invention; FIG. 4 is a diagram showing the thickness of the first dielectric ceramic layer at the central portion in the length (L) direction of the multilayer ceramic capacitor of the present invention; FIG. 4 is a diagram showing the thickness of the second dielectric ceramic layer of the laminated ceramic capacitor of the present invention;

The laminated ceramic capacitor of the present invention will be described below.
However, the present invention is not limited to the following configurations, and can be appropriately modified and applied without changing the gist of the present invention. Combinations of two or more of the individual desirable configurations described below are also part of the present invention.

[Multilayer ceramic capacitor]
FIG. 1 is a perspective view schematically showing an example of the laminated ceramic capacitor of the present invention. FIG. 2 is a perspective view schematically showing an example of a laminate constituting the laminated ceramic capacitor shown in FIG. 1. FIG. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1, taken along the line AA. 4 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along the line CC.

In this specification, the lamination direction, width direction, and length direction of the multilayer ceramic capacitor and the multilayer body are defined by arrows T, W, and L in the multilayer ceramic capacitor 1 shown in FIG. 1 and the multilayer body 10 shown in FIG. 2, respectively. Here, the lamination (T) direction, the width (W) direction, and the length (L) direction are orthogonal to each other. The lamination (T) direction is the direction in which the plurality of dielectric ceramic layers 20 and the plurality of pairs of the first internal electrode layers 21 and the second internal electrode layers 22 are stacked.

The multilayer ceramic capacitor 1 shown in FIG. 1 includes a laminate 10 and first external electrodes 51 and second external electrodes 52 provided on both end surfaces of the laminate 10, respectively.

As shown in FIG. 2, the laminate 10 has a rectangular parallelepiped shape or a substantially rectangular parallelepiped shape, and has a first main surface 11 and a second main surface 12 facing each other in the lamination (T) direction, a first side face 13 and a second side face 14 facing each other in the width (W) direction perpendicular to the lamination (T) direction, and a first end face 15 and a second end face 16 facing each other in the length (L) direction perpendicular to the lamination (T) direction and the width (W) direction. and

In this specification, the cross section of the multilayer ceramic capacitor 1 or the multilayer body 10 perpendicular to the first end face 15 and the second end face 16 and parallel to the lamination (T) direction is referred to as the LT cross section, which is a cross section in the length (L) direction and the lamination (T) direction. A cross section of the multilayer ceramic capacitor 1 or the multilayer body 10 perpendicular to the first side surface 13 and the second side surface 14 and parallel to the lamination (T) direction is referred to as a WT cross section, which is a cross section in the width (W) direction and the lamination (T) direction. Further, the cross section of the multilayer ceramic capacitor 1 or the multilayer body 10 which is orthogonal to the first side surface 13, the second side surface 14, the first end surface 15 and the second end surface 16 and is orthogonal to the lamination (T) direction is referred to as the LW cross section which is a cross section in the length (L) direction and the width (W) direction. Therefore, FIG. 3 is the LT cross section of the multilayer ceramic capacitor 1, and FIG. 4 is the WT cross section of the multilayer ceramic capacitor 1. As shown in FIG.

The laminate 10 preferably has rounded corners and ridges. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect.

As shown in FIGS. 2, 3 and 4, the laminate 10 has a laminated structure including a plurality of dielectric ceramic layers 20 laminated in the lamination (T) direction and a plurality of pairs of first internal electrode layers 21 and second internal electrode layers 22 formed along the interfaces between the dielectric ceramic layers 20. The dielectric ceramic layers 20 extend along the width (W) direction and the length (L) direction, and each of the first internal electrode layers 21 and the second internal electrode layers 22 extends flatly along the dielectric ceramic layers 20.

The first internal electrode layer 21 is drawn out to the first end surface 15 of the laminate 10 . On the other hand, the second internal electrode layers 22 are drawn out to the second end surface 16 of the laminate 10 .

The first internal electrode layer 21 and the second internal electrode layer 22 face each other with the dielectric ceramic layer 20 interposed therebetween in the stacking (T) direction. Capacitance is generated by the portion where the first internal electrode layer 21 and the second internal electrode layer 22 face each other with the dielectric ceramic layer 20 interposed therebetween.

Each of the first internal electrode layers 21 and the second internal electrode layers 22 preferably contains a metal such as Ni, Cu, Ag, Pd, Ag—Pd alloy, and Au. Each of the first internal electrode layers 21 and the second internal electrode layers 22 may contain the same dielectric ceramic material as the dielectric ceramic layers 20 in addition to the above metals.

The dielectric ceramic layer 20 has a first dielectric ceramic layer 20a and a second dielectric ceramic layer 20b.
The first dielectric ceramic layer 20 a is a dielectric ceramic layer arranged between the first internal electrode layer 21 and the second internal electrode layer 22 .
The second dielectric ceramic layer 20b is a dielectric ceramic layer arranged in a region where the internal electrode layers (21, 22) are not arranged, between the first dielectric ceramic layers 20a facing each other with the internal electrode layers (21, 22) interposed therebetween.

The first external electrode 51 is provided on the first end face 15 of the laminate 10, and in FIG. The first external electrode 51 is connected to the first internal electrode layer 21 at the first end surface 15 .

The second external electrode 52 is provided on the second end surface 16 of the laminate 10, and in FIG. The second external electrode 52 is connected to the second internal electrode layer 22 at the second end surface 16 .

Preferably, the first external electrode 51 and the second external electrode 52 each include a Ni layer containing Ni and a ceramic material. The Ni layer is a base electrode layer. Such a Ni layer can be formed by a so-called cofiring method in which the first internal electrode layers 21 and the second internal electrode layers 22 are fired simultaneously. The Ni layer is preferably arranged directly on the laminate 10 .

The first external electrode 51 preferably includes a Ni layer, a first plated layer, and a second plated layer in order from the first end surface 15 side of the laminate 10 . Similarly, the second external electrode 52 preferably includes, in order from the second end surface 16 side of the laminate 10, a Ni layer, a first plated layer, and a second plated layer. The first plating layer is preferably formed by Ni plating, and the second plating layer is preferably formed by Sn plating. Each of the first external electrode 51 and the second external electrode 52 may include a conductive resin layer containing conductive particles and resin between the Ni layer and the first plating layer. Examples of conductive particles in the conductive resin layer include metal particles such as Cu, Ag, and Ni.

The Ni layer may be formed by a so-called post-fire method, in which a conductive paste is applied to the end face of the laminated body after firing and baked. In this case, the Ni layer may not contain ceramic material.

Alternatively, the first external electrode 51 and the second external electrode 52 may each include a base electrode layer containing metal such as Cu. The underlying electrode layer may be formed by a co-fire method or by a post-fire method. Also, the underlying electrode layer may be a plurality of layers.

For example, the first external electrode 51 may have a four-layer structure including, in order from the first end surface 15 side of the laminate 10, a Cu layer as a base electrode layer, a conductive resin layer containing conductive particles and resin, a first plating layer, and a second plating layer. Similarly, the second external electrode 52 may have a four-layer structure including, in order from the second end face 16 side of the laminate 10, a Cu layer as a base electrode layer, a conductive resin layer containing conductive particles and resin, a first plated layer, and a second plated layer.

As shown in FIGS. 3 and 4, the dielectric ceramic layer 20 has a first dielectric ceramic layer 20a and a second dielectric ceramic layer 20b.
The first dielectric ceramic layer 20 a is arranged between the first internal electrode layer 21 and the second internal electrode layer 22 .
The second dielectric ceramic layer 20b is arranged in a region where the internal electrode layers are not arranged, between the first dielectric ceramic layers 20a facing each other with the internal electrode layers interposed therebetween.

As shown in FIGS. 2, 3, and 4, the laminate 10 includes an inner layer 30 in which a first internal electrode layer 21 and a second internal electrode layer 22 face each other across the dielectric ceramic layer 20, outer layers 31 and 32 arranged to sandwich the inner layer 30 in the lamination (T) direction, and a third dielectric ceramic arranged to sandwich the inner layer 30, the outer layer 31, and the outer layer 32 in the width (W) direction. Layers 41 and 42 are provided. The third dielectric ceramic layers 41 and 42 are also called side margin portions.
3 and 4, the inner layer portion 30 is a region sandwiched between the first internal electrode layer 21 closest to the first main surface 11 and the first internal electrode layer 21 closest to the second main surface 12 along the lamination (T) direction. Although not shown, each of the outer layer portion 31 and the outer layer portion 32 is preferably composed of a plurality of dielectric ceramic layers 20 laminated in the lamination (T) direction, and more preferably composed of the first dielectric ceramic layer 20a.

The thickness of each of the outer layer portions 31 and 32 is preferably 15 μm or more and 40 μm or less. Note that each of the outer layer portions 31 and 32 may have a single-layer structure instead of a multilayer structure.

As shown in FIG. 4, each of the third dielectric ceramic layer 41 and the third dielectric ceramic layer 42 may be composed of a plurality of dielectric ceramic layers laminated in the width (W) direction.
Among the dielectric ceramic layers constituting the third dielectric ceramic layer, the innermost layer in the width direction is called an inner layer, and the outermost layer is called an outer layer. An interface exists between the inner layer and the outer layer.
In FIG. 4, the third dielectric ceramic layer 41 has a two-layer structure including an inner layer 41a arranged on the innermost side of the laminate 10 and an outer layer 41b arranged on the outermost side of the laminated body 10 as the dielectric ceramic layers. Similarly, the third dielectric ceramic layer 42 has a two-layer structure including an inner layer 42a arranged on the innermost side of the laminate 10 and an outer layer 42b arranged on the outermost side of the laminated body 10 as the dielectric ceramic layers.
Note that the third dielectric ceramic layer is not limited to a two-layer structure, and may have a structure of three or more layers. When the third dielectric ceramic layer includes three or more dielectric ceramic layers, the innermost dielectric ceramic layer in the width direction is the inner layer, and the outermost dielectric ceramic layer in the width direction is the outer layer.
Further, the number of dielectric ceramic layers may differ between the third dielectric ceramic layers on the first side surface of the laminate and the third dielectric ceramic layers on the second side surface of the laminate.

When the third dielectric ceramic layer has a two-layer structure including an inner layer and an outer layer, it is possible to confirm the two-layer structure and the interface between the layers by observing with an optical microscope in a dark field because of the difference in sinterability between the inner layer and the outer layer. The same applies when the third dielectric ceramic layer has a structure of three or more layers.

The first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42 are made of a dielectric ceramic material containing BaTiO ₃ as a main component, for example. The dielectric ceramic layer 20 forming the inner layer portion 30 may further contain a sintering aid element.

The dielectric ceramic layers constituting the first dielectric ceramic layer, the second dielectric ceramic layer and the third dielectric ceramic layer may contain ceramic grains. The details of the diameter of the ceramic grains will be described later.

In the multilayer ceramic capacitor of the present invention, at least one of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer has a composition different from that of the other dielectric ceramic layers.
Since the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer are all different in the purpose of arrangement and the characteristics required in terms of the manufacturing method, by making the composition of at least one dielectric ceramic layer different from the composition of the other dielectric ceramic layers among the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, it is possible to realize an optimum composition according to the location where the dielectric ceramic layer is arranged, and reliability can be improved.

In the laminated ceramic capacitor of the present invention, the composition of the first dielectric ceramic layer may differ from the composition of the second dielectric ceramic layer and the composition of the third dielectric ceramic layer, the composition of the second dielectric ceramic layer may differ from the composition of the first dielectric ceramic layer and the third dielectric ceramic layer, the composition of the third dielectric ceramic layer may differ from the composition of the first dielectric ceramic layer and the second dielectric ceramic layer, or the composition of the first dielectric ceramic layer may differ from that of the first dielectric ceramic layer, The compositions of the second dielectric ceramic layer and the third dielectric ceramic layer may differ from each other.

In the laminated ceramic capacitor of the present invention, the composition of the second dielectric ceramic layer and the composition of the third dielectric ceramic layer are preferably different, and it is more preferable that the compositions of the first dielectric ceramic layer, the second dielectric ceramic layer and the third dielectric ceramic layer are all different.

When the third dielectric ceramic layer is composed of a plurality of dielectric ceramic layers, the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer may have the same composition or may have different compositions.
When the composition of any one of the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer is different from that of the first dielectric ceramic layer, it can be said that the composition of the third dielectric ceramic layer is different from the composition of the first dielectric ceramic layer.
Further, when the composition of any one of the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer is different from that of the second dielectric ceramic layer, it can be said that the composition of the third dielectric ceramic layer and the composition of the second dielectric ceramic layer are different.

Among the first dielectric ceramic layer, the second dielectric ceramic layer and the third dielectric ceramic layer, the dielectric ceramic layers having different compositions preferably have the same main component and different additives.
Main components include BaTiO ₃ , CaTiO ₃ , SrTiO ₃ and the like.
The additive preferably contains elements such as Si, Mg, Mn, Sn, Cu, rare earths, Ni and Al.
The first dielectric ceramic layer, the second dielectric ceramic layer and the third dielectric ceramic layer may contain two or more of the above elements.

Note that "having the same composition" means that the types of elements contained in the dielectric ceramics constituting each dielectric ceramic layer are the same, and that the contents (molar ratios) of other elements based on Ti are all within ±0.5%.
Differences in the diameter of ceramic grains constituting each dielectric ceramic layer and differences in porosity are not included in the difference in composition of the dielectric ceramic layers.

The composition of each dielectric ceramic layer can be obtained by performing elemental analysis on a cut surface obtained by cutting the laminated ceramic capacitor to expose the dielectric ceramic layer by wavelength dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis (TEM-EDX). At this time, the composition of each dielectric ceramic layer is measured at five points and an average value is obtained.
For the second dielectric ceramic layer, the average value obtained by measuring five points from the second dielectric ceramic layer exposed on the first end surface of the laminate and five points from the second dielectric ceramic layer exposed on the second end surface of the laminate.
When the third dielectric ceramic layer has a multilayer structure, the composition obtained by measuring the composition of each layer at five locations is multiplied by the ratio of the thickness of each layer in the third dielectric ceramic layer.
If segregation of elements is observed in the vicinity of the interface with other dielectric ceramic layers or internal electrode layers, the location where segregation of elements is observed shall not be measured by WDX.

Mg is preferable as the element added to the first dielectric ceramic layer.
The content of Mg in the first dielectric ceramic layer is preferably 0.05 mol % or more and 3.0 mol % or less with respect to 100 mol of Ti.
More preferably, the Mg content in the first dielectric ceramic layer is lower than the Mg content in the second dielectric ceramic layer and the third dielectric ceramic layer.
When the content of Mg in the first dielectric ceramic layer is low, the dielectric constant of the first dielectric ceramic layer increases, so that the capacitance of the multilayer ceramic capacitor can be improved. In some cases, it is preferable that the content of Mg in the first dielectric ceramic layer is as low as possible.

Sn is preferable as the element added to the second dielectric ceramic layer.
The Sn content in the second dielectric ceramic layer is preferably 0.05 mol % or more and 3.0 mol % or less with respect to 100 mol of Ti.
The Sn content in the second dielectric ceramic layer is preferably higher than the Sn content in the first dielectric ceramic layer and the third dielectric ceramic layer.

Si is preferable as the element added to the third dielectric ceramic layer.
The content of Si in the third dielectric ceramic layer is preferably 0.05 mol % or more and 5.0 mol % or less with respect to 100 mol of Ti.
The Si content in the third dielectric ceramic layer is preferably higher than the Si content in the first dielectric ceramic layer and the second dielectric ceramic layer.
When the Si content in the third dielectric ceramic layer is high, the sinterability of the dielectric ceramic layer is enhanced, so it is possible to suppress the deterioration of the internal electrode layers due to the intrusion of moisture or the like from the first and second side surfaces of the laminate.

Mg is preferable as an element added to the third dielectric ceramic layer.
The content of Mg in the third dielectric ceramic layer is preferably 0.05 mol % or more and 5.0 mol % or less with respect to 100 mol of Ti.
The Mg content in the third dielectric ceramic layer is preferably higher than the Mg content in the first dielectric ceramic layer and the second dielectric ceramic layer.
When the Mg content in the third dielectric ceramic layer is high, grain growth of ceramic grains contained in the third dielectric ceramic layer can be suppressed, and short circuits between internal electrode layers can be prevented.

Mn is preferable as the element added to the third dielectric ceramic layer.
The content of Mn in the third dielectric ceramic layer is preferably 0.01 mol % or more and 3.0 mol % or less with respect to 100 mol of Ti.
The Mn content in the third dielectric ceramic layer is preferably higher than the Mn content in the first dielectric ceramic layer and the second dielectric ceramic layer.
When the Mn content in the third dielectric ceramic layer is high, grain growth of ceramic grains contained in the third dielectric ceramic layer can be suppressed, and short circuits between internal electrode layers can be prevented.

In the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, elements other than the main component contained in each dielectric ceramic layer are preferably diffused into the other dielectric ceramic layers.
Further, it is preferable that part of the elements contained as additives in the first dielectric ceramic layer, the second dielectric ceramic layer and the third dielectric ceramic layer diffuse into other adjacent dielectric ceramic layers and internal electrode layers.

FIG. 5 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1, taken along the line BB.
In addition, FIG. 5 is an LW cross section of the laminated ceramic capacitor 1 .
As shown in FIG. 5, the second internal electrode layer 22 is exposed on the second end surface 16 of the laminate 10, and the second dielectric ceramic layer 20b is exposed on the first end surface 15 of the laminate 10. A third dielectric ceramic layer 41 and a third dielectric ceramic layer 42 are arranged on the first side surface 13 side and the second side surface 14 side of the laminate 10, respectively.

As shown in FIG. 5, an interface 2220b exists between the second internal electrode layer 22 and the second dielectric ceramic layer 20b. Interfaces 2241 and 2242 are present between the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42 . Further, interfaces 20b41 and 20b42 are present between the second dielectric ceramic layer 20b and the third dielectric ceramic layers 41 and 42, respectively.

Although not shown in FIG. 5, the first dielectric ceramic layers 20a are arranged on both sides in the thickness direction of the second internal electrode layers 22 and the second dielectric ceramic layers 20b. Therefore, it can be said that the first dielectric ceramic layer 20a has interfaces in direct contact with the second dielectric ceramic layer 20b, the third dielectric ceramic layers 41 and 42, and the internal electrode layers 21 and 22. FIG.

Furthermore, the first internal electrode layer 21 also has interfaces with the first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42, similarly to the second internal electrode layer 22 shown in FIG.

Elements derived from the second dielectric ceramic layer 20b may be segregated in the vicinity of the interface with the second dielectric ceramic layer 20b in the first dielectric ceramic layer 20a. Further, elements derived from the third dielectric ceramic layer 41 or 42 may be segregated in the vicinity of the interface with the third dielectric ceramic layer 41 or 42 in the first dielectric ceramic layer 20a.

Elements derived from the first dielectric ceramic layer 20a may be segregated in the vicinity of the interface with the first dielectric ceramic layer 20a in the second dielectric ceramic layer 20b. In the second dielectric ceramic layer 20b, elements derived from the third dielectric ceramic layer 41 or 42 may be segregated near the interfaces 20b41 and 20b42 with the third dielectric ceramic layer 41 or 42.

Elements derived from the first dielectric ceramic layer 20a may be segregated in the vicinity of the interface with the first dielectric ceramic layer 20a in the third dielectric ceramic layers 41 and 42. FIG. Moreover, elements derived from the second dielectric ceramic layer 20b may be segregated in the vicinity of the interfaces 20b41 and 20b42 with the second dielectric ceramic layer 20b in the third dielectric ceramic layers 41 and 42.

An element derived from the first dielectric ceramic layer 20a may be segregated in the vicinity of the interface with the first dielectric ceramic layer 20a in the first internal electrode layer 21 and the second internal electrode layer 22. Further, elements derived from the second dielectric ceramic layer 20b may be segregated in the vicinity of the interface 2220b with the second dielectric ceramic layer 20b in the first internal electrode layer 21 and the second internal electrode layer 22. Furthermore, elements derived from the third dielectric ceramic layers 41 and 42 may be segregated in the vicinity of the interfaces 2241 and 2242 with the third dielectric ceramic layers 41 and 42 in the first internal electrode layer 21 and the second internal electrode layer 22.
Further, in the vicinity of the portion where the interface 2220b between the second internal electrode layer 22 and the second dielectric ceramic layer 20b and the interface 2241 or 2242 between the second internal electrode layer 22 and the third dielectric ceramic layer 41 or 42 are in contact (the corner of the second internal electrode layer 22 on the side of the first end surface 15), elements derived from the second dielectric ceramic layer 20b and the third dielectric ceramic layer 4 Both elements derived from 1 or 42 may be segregated.

The porosity of the first dielectric ceramic layer, the second dielectric ceramic layer and the third dielectric ceramic layer may be the same, or may be different.
A cut surface obtained by cutting the laminated ceramic capacitor and exposing each dielectric ceramic layer is observed with a scanning electron microscope (SEM) at a magnification of 20,000. A region with a visual field size of 6.3 μm × 4.4 μm is photographed at five locations so that the regions do not overlap each other, and from each obtained SEM image, the ratio of the area occupied by the voids to the entire visual field is calculated as the porosity, and the average value in the five visual fields is obtained. However, when the third dielectric ceramic layer is composed of a plurality of layers, after obtaining the porosity of each layer individually, the value obtained by dividing the thickness of the layer by the thickness of the third dielectric ceramic layer and the sum of the products of the porosity of each layer is taken as the porosity of the third dielectric ceramic layer.

Preferably, the first dielectric ceramic layer, the second dielectric ceramic layer and the third dielectric ceramic layer contain ceramic grains.
When the dielectric ceramic layer contains ceramic grains, interfacial resistance is generated at the interfaces between the ceramic grains, which increases the insulation resistance between the internal electrode layers and prevents the occurrence of short circuits.

A rare earth element is preferably present at the interfaces of the ceramic grains.
The presence of rare earth elements at the interfaces of the ceramic grains can be confirmed by elemental analysis using TEM-EDX. Rare earths include La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y and the like.
The presence of the rare earth element at the interfaces of the ceramic grains further increases the interfacial resistance of the dielectric ceramic layers, thereby further improving the reliability of the multilayer ceramic capacitor. Mg, Mn, Si, etc. may be present.

The rare earth element is preferably present in an amount of 0.2 mol % or more and 5 mol % or less with respect to 100 mol of Ti.
Here, 100 mol of Ti is defined as the abundance of rare earth elements with respect to 100 mol of Ti, on the premise that the dielectric ceramic material constituting the dielectric ceramic layer is mainly composed of a compound having a perovskite structure (structure represented by _ABO3 , B=Ti).
The abundance of rare earth elements can be confirmed by TEM-EDX.

In the multilayer ceramic capacitor, the thickness of each of the first internal electrode layers and the second internal electrode layers is preferably 0.4 μm or less.
Moreover, the thickness of each of the first internal electrode layers and the thickness of the second internal electrode layers is preferably 0.38 μm or less.
Moreover, the thickness of each of the first internal electrode layers and the thickness of the second internal electrode layers is preferably 0.25 μm or more.

The thickness of the first dielectric ceramic layer is preferably 0.55 μm or less.
Also, the thickness of each of the first dielectric ceramic layers is preferably 0.4 μm or more.

The thickness of the second dielectric ceramic layer is preferably the same as the thickness of the internal electrode layers.

The thickness of each of the third dielectric ceramic layers 41 and 42 is preferably 5 μm or more and 40 μm or less, more preferably 5 μm or more and 20 μm or less. The thicknesses of the third dielectric ceramic layers 41 and 42 are preferably the same. However, it is preferable that the outer layer 41b is thicker than the inner layer 41a while the inner layer 41a and the outer layer 41b satisfy the above ranges. Similarly, it is preferable that the outer layer 42b is thicker than the inner layer 42a while the inner layer 42a and the outer layer 42b satisfy the above ranges.

From the viewpoint of maintaining the shape and performance of the multilayer ceramic capacitor 1, the inner layer 41a is preferably thinner than the outer layer 41b. Similarly, the inner layer 42a is preferably thinner than the outer layer 42b.

Each thickness of the inner layers 41a and 42a is preferably 0.1 μm or more and 20 μm or less. The inner layers 41a and 42a preferably have the same thickness.

The thickness of each of the outer layers 41b and 42b is preferably 5 μm or more and 20 μm or less. The outer layers 41b and 42b preferably have the same thickness.

The thickness of each ceramic layer in the side margin means the average value of the thickness of the third dielectric ceramic layer measured at a plurality of points along the lamination (T) direction.

[Manufacturing method of multilayer ceramic capacitor]
The method for manufacturing a laminated ceramic capacitor of the present invention preferably comprises a step of preparing a green chip having a laminated structure composed of a plurality of first dielectric ceramic layers and a plurality of second dielectric ceramic layers in an unfired state and a plurality of pairs of first internal electrode layers and second internal electrode layers, wherein the first internal electrode layer and the second internal electrode layer are exposed on first side surfaces and second side surfaces facing each other in a width direction perpendicular to the stacking direction; forming an unfired third dielectric ceramic layer on the side surface and the second side surface to form an unfired laminate; and firing the unfired laminate. In the step of preparing the green chip, the unfired first internal electrode layer or the second internal electrode layer is formed on the surface of the unfired first dielectric ceramic layer, and the unfired second dielectric ceramic layer is formed in a region where the first internal electrode layer and the second internal electrode layer are not provided. in the step of laminating the ceramic green sheets obtained by forming to form the unfired laminate, forming unfired inner layers on the first side surface and the second side surface, and forming an unfired outer layer on the outermost side, thereby forming the unfired side margin portions, and of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, at least one dielectric ceramic layer has a different composition.

An example of a method for manufacturing the multilayer ceramic capacitor 1 shown in FIG. 1 will be described below.

First, ceramic green sheets to be the first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42 are prepared. The ceramic green sheet contains a binder, a solvent, and the like, in addition to the ceramic raw material including the dielectric ceramic material described above. Additives containing rare earth elements may also be added to the ceramic raw material. By changing the elements contained in the additive, the compositions of the first dielectric ceramic layer, the second dielectric ceramic layer and the third dielectric ceramic layer can be changed. It is preferable that the ceramic raw materials, which are the main components, be the same.
A ceramic green sheet is formed, for example, on a carrier film using a die coater, gravure coater, micro gravure coater, or the like.

6, 7 and 8 are plan views schematically showing examples of ceramic green sheets. 6, 7 and 8 respectively show a first ceramic green sheet 101 for forming the inner layer 30, a second ceramic green sheet 102 for forming the inner layer 30, and a third ceramic green sheet 103 for forming the outer layer 31 or 32.

6, 7 and 8, the first ceramic green sheet 101, the second ceramic green sheet 102 and the third ceramic green sheet 103 are not cut for each laminated ceramic capacitor 1. In FIGS. 6, 7 and 8 show cutting lines X and Y for cutting into each multilayer ceramic capacitor 1. FIG. The cutting line X is parallel to the length (L) direction, and the cutting line Y is parallel to the width (W) direction.

As shown in FIG. 6, in the first ceramic green sheet 101, unfired first internal electrode layers 121 corresponding to the first internal electrode layers 21 are formed on the unfired first dielectric ceramic layers 120a corresponding to the first dielectric ceramic layers 20a. In addition, unfired second dielectric ceramic layers 120b corresponding to the second dielectric ceramic layers 20b are formed in regions where the unfired first internal electrode layers 121 are not formed.
The unfired first dielectric ceramic layer 120 a and the unfired second dielectric ceramic layer 120 b are also the unfired dielectric ceramic layers 120 corresponding to the dielectric ceramic layers 20 .

As shown in FIG. 7, in the second ceramic green sheet 102, unfired second internal electrode layers 122 corresponding to the second internal electrode layers 22 are formed on the unfired first dielectric ceramic layers 120a corresponding to the first dielectric ceramic layers 20a. In addition, unfired second dielectric ceramic layers 120b corresponding to the second dielectric ceramic layers 20b are formed in regions where the unfired second internal electrode layers 122 are not formed.
The unfired first dielectric ceramic layer 120 a and the unfired second dielectric ceramic layer 120 b are also the unfired dielectric ceramic layers 120 corresponding to the dielectric ceramic layers 20 .

The method for producing the first ceramic green sheet 101 shown in FIG. 6 and the second ceramic green sheet shown in FIG. 7 is not particularly limited. Examples include a method of applying a dielectric paste, which is a mixture of a dielectric ceramic and a solvent, to form the second dielectric ceramic layer 20b by firing, and a conductive paste to form the internal electrode layers 21 or 22 by firing, to predetermined regions on the surface of the unfired first dielectric ceramic layer 120a.
The order of applying the dielectric paste and the conductive paste is not particularly limited, and the dielectric paste may be applied first and then the conductive paste, or the conductive paste may be applied first and then the dielectric paste may be applied.
Alternatively, the dielectric paste and the conductive paste may be applied so that part of the surface of the previously applied paste is covered by part of the later applied paste.

As shown in FIG. 8, the third ceramic green sheet 103 corresponding to the outer layer portion 31 or 32 is composed of the unfired first dielectric ceramic layer 120a corresponding to the first dielectric ceramic layer, and the unfired internal electrode layer 121 or 122 and the unfired second dielectric ceramic layer 120b are not formed.

The first internal electrode layers 121 and the second internal electrode layers 122 can be formed using any conductive paste. For forming the first internal electrode layers 121 and the second internal electrode layers 122 with the conductive paste, for example, a screen printing method, a gravure printing method, or the like can be used.

The first internal electrode layer 121 and the second internal electrode layer 122 are arranged over two regions separated by the cutting line Y and adjacent in the length (L) direction, and extend in a strip shape in the width (W) direction. In the first internal electrode layer 121 and the second internal electrode layer 122, the regions partitioned by the cutting line Y are shifted by one line in the length (L) direction. That is, the cutting line Y passing through the center of the first internal electrode layer 121 passes through the region between the second internal electrode layers 122 (that is, the center of the second dielectric ceramic layer 120b), and the cutting line Y that passes through the center of the second internal electrode layer 122 passes through the region between the first internal electrode layers 121 (that is, the center of the second dielectric ceramic layer 120b).

After that, a mother block is produced by laminating the first ceramic green sheet 101, the second ceramic green sheet 102 and the third ceramic green sheet 103. FIG.

FIG. 9 is an exploded perspective view schematically showing an example of the mother block.
In FIG. 9, for convenience of explanation, the first ceramic green sheet 101, the second ceramic green sheet 102 and the third ceramic green sheet 103 are shown disassembled. In the actual mother block 104, the first ceramic green sheet 101, the second ceramic green sheet 102 and the third ceramic green sheet 103 are pressure-bonded and integrated by a means such as hydrostatic pressing.

In the mother block 104 shown in FIG. 9, the first ceramic green sheets 101 and the second ceramic green sheets 102 corresponding to the inner layer portion 30 are alternately laminated in the lamination (T) direction. Further, third ceramic green sheets 103 corresponding to the outer layer portions 31 and 32 are laminated on the upper and lower surfaces in the lamination (T) direction of the alternately laminated first ceramic green sheets 101 and second ceramic green sheets 102. Although three third ceramic green sheets 103 are laminated in FIG. 9, the number of third ceramic green sheets 103 can be changed as appropriate.

A plurality of green chips are fabricated by cutting the resulting mother block 104 along cutting lines X and Y (see FIGS. 6, 7 and 8). For this cutting, for example, a method such as dicing, press cutting, or laser cutting is applied.

FIG. 10 is a perspective view schematically showing an example of a green chip.
The green chip 110 shown in FIG. 10 has a laminated structure composed of a plurality of unfired first dielectric ceramic layers 120a and second dielectric ceramic layers 120b and a plurality of pairs of first internal electrode layers 121 and second internal electrode layers 122. A first side surface 113 and a second side surface 114 of the green chip 110 are surfaces that appear by cutting along the cutting line X, and a first end surface 115 and a second end surface 116 are surfaces that appear by cutting along the cutting line Y. The first internal electrode layers 121 and the second internal electrode layers 122 are exposed on the first side surface 113 and the second side surface 114 . Further, only the first internal electrode layer 121 and the second dielectric ceramic layer 120b are exposed on the first end surface 115, and only the second internal electrode layer 122 and the second dielectric ceramic layer 120b are exposed on the second end surface 116.
The first dielectric ceramic layer 120a is exposed on the first side surface 113, the second side surface 114, the first end surface 115, and the second end surface 116, but the second dielectric ceramic layer is exposed in different places in the area where it is arranged.
That is, the second dielectric ceramic layer 120b arranged on the first end face 115 side is not exposed on the second end face 116, and the second dielectric ceramic layer 120b arranged on the second end face 116 side is not exposed on the first end face 115.

By forming an unfired third dielectric ceramic layer on the first side surface 113 and the second side surface 114 of the obtained green chip 110, an unfired laminate is produced. The unfired third dielectric ceramic layer is formed, for example, by attaching ceramic green sheets made of dielectric ceramic to the first and second side surfaces of the green chip.

For example, when the third dielectric ceramic layer is composed of two layers, an inner layer and an outer layer, first, in order to fabricate a ceramic green sheet for the inner layer, a ceramic raw material containing a dielectric ceramic material containing BaTiO ₃ or the like as a main component, as well as a ceramic slurry containing a binder, a solvent, and the like is prepared. Si, which is a sintering aid, may be added to the ceramic slurry for the inner layer. The inner layer has a role of bonding with the green chip 110 .
Further, the inner layer ceramic slurry may contain a liquid-phase metal, and the inner layer ceramic slurry may contain more rare earth elements, Mg, and Mn than the ceramic green sheets for forming the inner layer. By doing so, it is possible to suppress the grain growth of the ceramic grains contained in the dielectric ceramic layers sandwiched between the widthwise ends of the internal electrode layers.

Next, in order to produce the outer layer ceramic green sheets, a ceramic slurry containing a binder, a solvent, etc., as well as a ceramic raw material containing a dielectric ceramic material whose main component is BaTiO ₃ or the like is produced. Si, which is a sintering aid, may be added to the ceramic slurry for the outer layer. In addition, it is preferable that the amount of Si contained in the inner layer ceramic green sheets is larger than the amount of Si contained in the outer layer ceramic green sheets. The amount of content is judged by the size of the area where Si is detected by taking an image of the cross section with WDX.

The outer layer ceramic green sheet is formed by applying the outer layer ceramic slurry to the surface of the resin film and drying it. The inner layer ceramic green sheet is formed by applying the inner layer ceramic slurry to the surface of the outer layer ceramic green sheet on the resin film and drying it. As described above, a ceramic green sheet having a two-layer structure is obtained.

A ceramic green sheet having a two-layer structure can also be obtained, for example, by forming an outer layer ceramic green sheet and an inner layer ceramic green sheet in advance and then bonding them together. Moreover, the ceramic green sheet is not limited to two layers, and may be three or more layers.

After that, the ceramic green sheet is peeled off from the resin film.

Subsequently, the ceramic green sheet for the inner layer of the ceramic green sheet and the first side surface 113 of the green chip 110 are opposed to each other, pressed against each other, and punched to form the unfired side margin portions 41 . Further, on the second side surface 114 of the green chip 110 as well, the unfired side margin portions 42 are formed by facing the inner layer ceramic green sheets of the ceramic green sheets and pressing and punching them. At this time, it is preferable to previously apply an organic solvent as an adhesive to the side surface of the green chip. As described above, an unfired laminate is obtained.

It is preferable to subject the unfired laminate obtained by the above method to barrel polishing or the like. By polishing the unfired laminate, the corners and ridges of the fired laminate 10 are rounded.

After that, in the unfired laminate, an external electrode conductive paste containing Ni and a ceramic material is applied to each of the first end face 115 and the second end face 116 of the green chip 110 .

The external electrode conductive paste preferably contains the same dielectric ceramic material as the first dielectric ceramic layer, the second dielectric ceramic layer, or the outer layer as the ceramic material. The content of the ceramic material in the external electrode conductive paste is preferably 15% by weight or more. Also, the content of the ceramic material in the conductive paste for external electrodes is preferably 25% by weight or less.

Next, the unfired laminate coated with the conductive paste for external electrodes is degreased under predetermined conditions in, for example, a nitrogen atmosphere, and then fired at a predetermined temperature in a nitrogen-hydrogen-water vapor mixed atmosphere. As a result, the unfired laminate and the conductive paste for the external electrode are fired at the same time, and the laminate 10, the Ni layer connected to the first internal electrode layer 21, and the Ni layer connected to the second internal electrode layer 22 are simultaneously formed by the so-called co-firing method. After that, a first Ni-plated layer and a second Sn-plated layer are sequentially laminated on the surface of each Ni layer. Thereby, the first external electrode 51 and the second external electrode 52 are formed.

Note that the laminate 10 and the first external electrode 51 and the second external electrode 52 may be formed at different timings by a so-called post-fire method. Specifically, first, an unfired laminate is degreased under predetermined conditions, for example, in a nitrogen atmosphere, and then fired at a predetermined temperature in a mixed nitrogen-hydrogen-water vapor atmosphere to form the laminate 10. Then, a conductive paste containing Cu powder is applied to each of the first end face 15 and the second end face 16 of the laminate 10 and baked. As a result, base electrode layers connected to the first internal electrode layers 21 and base electrode layers connected to the second internal electrode layers 22 are formed. Then, on the surface of each base electrode layer, a conductive resin layer containing conductive particles (for example, metal particles such as Cu, Ag, Ni, etc.) and a resin, a first Ni-plated layer, and a second Sn-plated layer are sequentially laminated. Thereby, the first external electrode 51 and the second external electrode 52 are formed.

As described above, the multilayer ceramic capacitor 1 is manufactured.

In the above-described embodiment, the mother block 104 is cut along the cutting lines X and Y to obtain a plurality of green chips, and then the unfired third dielectric ceramic layers are formed on both sides of the green chips.

That is, the mother block may be cut only along the cutting line X to obtain a plurality of bar-shaped green blocks in which the first internal electrode layers and the second internal electrode layers are exposed on the side surfaces exposed by cutting along the cutting line X, and after forming the unfired third dielectric ceramic layers on both side surfaces of the green block, cutting along the cutting line Y to obtain a plurality of unfired laminates, and then firing the unfired laminates. After sintering, a multilayer ceramic capacitor can be manufactured by performing the same steps as in the above-described embodiments.

The present invention further comprises the following configurations [1] to [7].

[1] Alloy Portions Between Dielectric Ceramic Layers, Internal Electrode Layers, and External Electrodes In the multilayer ceramic capacitor 1 of the present invention, as shown in FIG. In addition, in the multilayer ceramic capacitor 1 of the present invention, the first alloy portions 310 are formed between the first dielectric ceramic layers 20a and the first internal electrode layers 21 and between the first dielectric ceramic layers 20a and the second internal electrode layers 22, respectively.

As shown in FIG. 12, the metal element 321a is segregated at the interface 2220b between the second internal electrode layer 22 and the second dielectric ceramic layer 20b. The second alloy portion 320 is formed of a segregation layer 321 that is layered segregation of a metal element 321a. Similarly, the segregation layer 321 is formed by the segregation of the metal element 321a at the interface 2220b between the first internal electrode layer 21 and the second dielectric ceramic layer 20b, and the second alloy portion 320 is formed by the segregation layer 321. A second alloy portion 320 is formed on each of the surfaces of the first internal electrode layer 21 and the second internal electrode layer 22 on the side of the second dielectric ceramic layer 20b. The second alloy portion 320 is formed between the first internal electrode layer 21 and the second dielectric ceramic layer 20b and between the second internal electrode layer 22 and the second dielectric ceramic layer 20b.

Further, as shown in FIG. 12, the metal element 311a is segregated at the interface 2220a between the second internal electrode layer 22 and the first dielectric ceramic layer 20a. The first alloy portion 310 is formed of a segregation layer 311 that is layered segregation of a metal element 311a. Similarly, the segregation layer 311 is formed by the segregation of the metal element 311a at the interface 2220a between the first internal electrode layer 21 and the first dielectric ceramic layer 20a, and the segregation layer 311 forms the first alloy portion 310. The first alloy portions 310 are formed on the surfaces of the first internal electrode layers 21 and the second internal electrode layers 22 on the side of the first dielectric ceramic layer 20a. The first alloy portion 310 is formed between the first internal electrode layer 21 and the first dielectric ceramic layer 20a and between the second internal electrode layer 22 and the first dielectric ceramic layer 20a.

There are a plurality of types of segregated metal elements 321a that form the second alloy portion 320 . The plurality of types of metal elements 321a forming the segregation layer 321 include the metal element contained most among the metal elements forming the first internal electrode layer 21 and the second internal electrode layer 22, and the element derived from the second dielectric ceramic layer 20b. Also, the segregated metal element 311a forming the first alloy portion 310 is the same. That is, the metal element 311a includes the metal element contained most among the metal elements forming the first internal electrode layer 21 and the second internal electrode layer 22 and the element derived from the first dielectric ceramic layer 20a.

Among the metal elements forming the first internal electrode layers 21 and the second internal electrode layers 22, the metal element contained most frequently is, for example, one of Ni, Cu, Ag, Pd, Au, and Pt. On the other hand, the elements derived from the second dielectric ceramic layer 20b and the first dielectric ceramic layer 20a include, for example, metal elements as additives. Specifically, any one or more metal elements selected from the metal group of Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, Y, and Ge can be mentioned, and among these, Sn, Ga, and Ge are particularly preferred. Hereinafter, the metal group may be referred to as metal group M.

The segregation of the metal element 321a occurs when the metal element contained in the second dielectric ceramic layer 20b moves to the first internal electrode layer 21 and the second internal electrode layer 22 during firing of the second dielectric ceramic layer 20b. The segregation of the metal element 311a occurs when the metal element contained in the first dielectric ceramic layer 20a moves to the first internal electrode layer 21 and the second internal electrode layer 22 during firing of the first dielectric ceramic layer 20a.

When the first dielectric ceramic layer 20a contains BaTiO ₃ as the main component, the second alloy portion 320 has a higher molar ratio of the metal element contained in the second dielectric ceramic layer 20b than the first alloy portion 310, i.e., any one or more of the metal group M, to 100 moles of Ti.

FIG. 13 shows a surface of the laminate 10 including the central portion in the width (W) direction, the length (L) direction, and the lamination (T) direction. In the multilayer ceramic capacitor 1 of the present invention, on the surface shown in FIG. 13, the first internal electrode layer 21 includes a plurality of first interspersed internal electrodes 210 interspersed discontinuously in the length (L) direction at the ends in the length (L) direction that are not connected to the second external electrodes 52. In addition, the second internal electrode layer 22 includes a plurality of second interspersed internal electrodes 220 discontinuously scattered in the length (L) direction at the ends in the length (L) direction that are not connected to the first external electrodes 51. Each of the first interspersed internal electrodes 210 and the second interspersed internal electrodes 220 is formed inside the second dielectric ceramic layer 20b. The plurality of first interspersed internal electrodes 210 may be connected to the first internal electrode layer 21 while extending in the width (W) direction. In some cases, the plurality of second interspersed internal electrodes 220 are also connected to the second internal electrode layers 22 while extending in the width (W) direction.

A fourth alloy portion 340 is formed around each of the first interspersed internal electrodes 210 and the second interspersed internal electrodes 220 . The fourth alloy portion 340 is formed of a segregation layer 341 that is layered segregation of a metal element 341a. The metal element 341a includes the metal element contained most among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22, and one or more metal elements from the metal group M derived from the second dielectric ceramic layer 20b.

The segregation of the metal element 341a occurs when the metal element contained in the second dielectric ceramic layer 20b moves to the first interspersed internal electrodes 210 and the second interspersed internal electrodes 220 during firing of the second dielectric ceramic layer 20b. The segregation of the metal element 341 a occurs around one or more first interspersed internal electrodes 210 and multiple second interspersed internal electrodes 220 . Alternatively, it may occur all around the first interspersed internal electrodes 210 and all around the second interspersed internal electrodes 220 .

As shown in FIG. 14, in the multilayer ceramic capacitor 1 of the present invention, third alloy portions 330 are formed between the third dielectric ceramic layers 41 and 42 and the first internal electrode layer 21 and between the third dielectric ceramic layers 41 and 42 and the second internal electrode layer 22.

As shown in FIG. 14, metal elements 331a are segregated at interfaces 2220c between the first internal electrode layers 21 and the third dielectric ceramic layers 41 and 42. As shown in FIG. The metal element 331a is also segregated at the interface 2220c between the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42. As shown in FIG. The third alloy portion 330 is formed of a layered segregation of a metal element 331a, that is, a segregation layer 331 . Third alloy portions 330 are formed on the surfaces of the first internal electrode layers 21 and the second internal electrode layers 22 on the sides of the third dielectric ceramic layers 41 and 42, respectively. The third alloy portion 330 is formed between the first internal electrode layer 21 and the third dielectric ceramic layers 41 and 42, and between the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42.

The metal element 331a includes the metal element contained most among the metal elements constituting the first internal electrode layers 21 and the second internal electrode layers 22, and one or more metal elements from the metal group M derived from the third dielectric ceramic layers 41 and 42. Elements derived from the third dielectric ceramic layers 41 and 42 include, for example, metal elements as additives. Specifically, any one or more metal elements in the above metal group M can be used.

The segregation of the metal element 331a occurs when the metal element contained in the third dielectric ceramic layers 41 and 42 moves to the first internal electrode layer 21 and the second internal electrode layer 22 during firing of the third dielectric ceramic layers 41 and 42.

In the multilayer ceramic capacitor 1 of the present invention, when the first external electrode 51 and the second external electrode 52 each include a Ni layer as a base electrode layer and are formed by the co-firing method, as shown in FIG. 15, a fifth alloy portion 350 is formed in the Ni layer.

FIG. 15 shows a state where the fifth alloy portion 350 is formed at the interface 51b of the first external electrode 51 with the second dielectric ceramic layer 20b. The fifth alloy portion 350 is formed of a segregation layer 351 that is layered segregation of a metal element 351a. Similarly, the interface 51b of the second external electrode 52 with the second dielectric ceramic layer 20b also forms a fifth alloy portion 350 by segregation of the metal element 351a. The segregation of the metal element 351a occurs when the metal element contained in the second dielectric ceramic layer 20b moves to the first external electrode 51 and the second external electrode 52 during firing of the second dielectric ceramic layer 20b.

In the laminated body 10 of the laminated ceramic capacitor 1 of the present invention, the mutually adjacent ends of the first internal electrode layer 21 and the second internal electrode layer 22 and the second dielectric ceramic layer 20b may overlap each other. For example, as shown in FIG. 16, the ends of the second dielectric ceramic layers 20b may overlap the ends of the second internal electrode layers 22. As shown in FIG. Further, as shown in FIG. 17, the end portions of the second dielectric ceramic layers 20b may overlap the end portions of the first internal electrode layers 21. As shown in FIG. In such a mode in which the ends overlap each other, the first internal electrode layer 21 and the second internal electrode layer 22 may each overlap on the second dielectric ceramic layer 20b.

In the multilayer ceramic capacitor 1 of the present invention, between the second dielectric ceramic layer 20b and the first internal electrode layer 21 and between the second dielectric ceramic layer 20b and the second internal electrode layer 22, respectively, one of the metal elements constituting the internal electrode layers that is contained in the largest amount, Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, and V , Y and one or more metal elements selected from the metal group M of Y are formed.

An electric field tends to concentrate at the respective ends of the first internal electrode layer 21 and the second internal electrode layer 22 that are in contact with the second dielectric ceramic layer 20b, which may reduce the reliability of the multilayer ceramic capacitor. However, in the multilayer ceramic capacitor 1 of the present invention, the second alloy portion 320 is formed between the second dielectric ceramic layer 20b and the first internal electrode layer 21 and the second internal electrode layer 22, thereby suppressing electric field concentration and improving reliability.

In the laminated ceramic capacitor 1 of the present invention, when the first dielectric ceramic layers 20a contain Ba and Ti, the first alloy portions 31 each containing the most abundant metal element among the metal elements constituting the internal electrode layers and one or more metal elements from the metal group M are provided between the first dielectric ceramic layers 20a and the first internal electrode layers 21 and between the first dielectric ceramic layers 20a and the second internal electrode layers 22, respectively. 0 is formed. The second alloy portion 320 has a higher molar ratio to 100 moles of Ti in the content of the metal group M than the first alloy portion 310 .

As a result, electric field concentration is suppressed by the second alloy portion 320 in the vicinity of the interface with the second dielectric ceramic layer 20b in the first internal electrode layer 21 and the second internal electrode layer 22, and reliability can be improved. In addition, the second alloy portions 320 formed at the ends of the first internal electrode layers 21 and 22, which are in contact with the second dielectric ceramic layer 20b where electric field concentration is likely to occur, are made higher than the first alloy portions 310 formed on the first dielectric ceramic layer 20a side in terms of the molar ratio of the metal group M to Ti100 mol, thereby effectively suppressing the electric field concentration on the second dielectric ceramic layer 20b side and improving the reliability. can be improved.

By controlling the metal amount of the metal group M added to each of the first dielectric ceramic layer 20a and the second dielectric ceramic layer 20b, the thickness of the first alloy portion 310 and the second alloy portion 320 and the concentration of the contained metal group M can be controlled. For example, when the concentration of the metal group M added to the second dielectric ceramic layer 20b is higher than that of the first dielectric ceramic layer 20a, as shown in FIG.

In the laminated ceramic capacitor 1 of the present invention, the first internal electrode layers 21 include the first interspersed internal electrodes 210 interspersed discontinuously in the length (L) direction at the ends in the length (L) direction not connected to the second external electrodes 52 in the plane including the width (W) direction central portion, the length (L) direction, and the stacking (T) direction of the laminate 10 , and the second internal electrode layers 22 are connected to the first external electrodes 51 . A fourth alloy portion 340 is formed around each of the first interspersed internal electrodes 210 and the second interspersed internal electrodes 220, which contains the most abundant metal element among the metal elements constituting the internal electrode layers and at least one metal element from the metal group M.

When the first interspersed internal electrodes 210 and the second interspersed internal electrodes 220 extend in the width (W) direction and are connected to the first internal electrode layer 21 and the second internal electrode layer 22, respectively, if an electric field concentrates on the connecting portion, dielectric breakdown may occur and reliability may be lowered. However, in the multilayer ceramic capacitor 1 of the present invention, dielectric breakdown due to electric field concentration is suppressed by the fourth alloy portions 340 formed around the first interspersed internal electrodes 210 and the second interspersed internal electrodes 220, and reliability can be improved.

In the laminated ceramic capacitor 1 of the present invention, third alloy portions 330 containing the most abundant metal element among the metal elements constituting the internal electrode layers and one or more metal elements from the metal group M are formed between the third dielectric ceramic layers 41 and 42 and the first internal electrode layers 21 and between the third dielectric ceramic layers 41 and 42 and the second internal electrode layers 22, respectively.

As a result, electric field concentration is suppressed by the third alloy portion 330 in the vicinity of the interface with the third dielectric ceramic layers 41 and 42 in the first internal electrode layer 21 and the second internal electrode layer 22, and reliability can be improved.

In the laminated ceramic capacitor 1 of the present invention, the first external electrode 51 and the second external electrode 52 contain Ni, and the fifth alloy portion 350 is formed between the second dielectric ceramic layer 20b and the first external electrode 51 and the second external electrode 52, in which one or more metal elements of the metal group M are segregated in Ni.

As a result, even when the distance between the first internal electrode layer 21 and the second external electrode 52 and between the second internal electrode layer 22 and the first external electrode 51, that is, the distance in the length (L) direction of the second dielectric ceramic layer 20b is narrow, for example, less than 15 μm, the presence of the fifth alloy portion 350 makes it difficult for dielectric breakdown due to electric field concentration to occur between the internal electrode layer and the external electrode, thereby improving reliability.

[Test Example 1]
Next, Test Example 1 for verifying the effects of the first alloy portion 310, the second alloy portion 320 and the third alloy portion 330 in the multilayer ceramic capacitor 1 of the present invention will be described.

About TEM analysis In the above-described method for manufacturing a multilayer ceramic capacitor of the present invention, the first external electrode 51 and the second external electrode 52 are not co-fired, and the green chip 110 is fired without co-firing the laminate 10. The laminate 10 is polished from the first side surface 13 side and the second side surface 14 side to obtain a polished body as a test piece, leaving the central portion in the width (W) direction as shown in FIG.
The types and metal amounts (metal concentrations) of metal elements contained in the first alloy portion 310 were analyzed as follows.
As shown in FIG. 18, an imaginary line OL1 perpendicular to the length (L) direction is assumed at the center of the length (L) direction. Then, along the imaginary line OL1, the region in which the first dielectric ceramic layer 20a related to obtaining the capacitance of the polishing body, and the first internal electrode layer 21 and the second internal electrode layer 22 are stacked is divided into three equal regions in the stacking direction into three regions: an upper region E1, a central region E2 and a lower region E3.
An upper region E1, a central region E2 and a lower region E3 are cut out from the polishing body, and each of the upper region E1, the central region E2 and the lower region E3 is thinned by Ar ion milling or the like to obtain three thin film samples from each region.

The three thin film samples of the upper region E1, the central region E2, and the lower region E3 of the specimen thus obtained were subjected to TEM observation and elemental mapping by EDX attached to the TEM.
As a result, no significant difference was observed between the upper and lower regions E1 and E3 and the central region E2, so the results obtained from the central region E2 are regarded as the microstructures of the dielectric ceramic layers and the internal electrode layers. As a result, the type and amount of metal (metal concentration) of the metal element contained in the first alloy portion 310 can be found.
In addition, the type and metal amount (metal concentration) of the metal element contained in the second alloy portion 320 can be analyzed by obtaining a thin film sample in the same manner as described above in the region of one end portion in the length (L) direction where the second alloy portion 320 exists. That is, in the polishing body shown in FIG. 18, assuming an imaginary line OL2 perpendicular to the length (L) direction at one end in the length (L) direction, a thin film sample is obtained in three areas, an upper area E4, a central area E5 and a lower area E6, which are equally divided in the stacking direction along the imaginary line OL2. Then, the three thin film samples of the upper region E4, the central region E5, and the lower region E6 were subjected to TEM observation and elemental mapping by EDX attached to the TEM, and the types and metal amounts (metal concentrations) of the metal elements contained in the second alloy portion 320 were investigated.

As for the second alloy part and the first alloy part, the concentration of Sn was examined by analysis using an EDX mapping image based on a TEM observation image. TEM measurement points were measured at intervals of about 5 nm to 10 nm. At the interface between the internal electrode layer and the dielectric ceramic layer, the alloy portion is defined as the region where the observed value is three times or more higher than that of the other measurement points, and the average value thereof is defined as the metal concentration of the alloy portion.

Eighteen multilayer ceramic capacitors of Test Examples 1-1 to 1-5 shown in Table 1 were prepared. In Test Example 1-2, in the multilayer ceramic capacitor of the present invention, the first internal electrode layer 21 and the second internal electrode layer 22 are made of Ni, and the same amount of Sn as an additive is added to the first dielectric ceramic layer 20a and the second dielectric ceramic layer 20b. In Test Examples 1-3 to 1-5, the amount of Sn added to the second dielectric ceramic layer 20b is gradually increased from Test Example 1-2. In Test Example 1-1, a laminated ceramic capacitor was manufactured under the same conditions as in Test Examples 1-2 to 1-5, except that Sn was not added to the second dielectric ceramic layer 20b.

For the multilayer ceramic capacitors of Test Examples 1-1 to 1-5, the resistance value (kΩ) was measured with a voltage of 6.3 V applied at a room temperature of 150° C., and the MTTF (mean time to failure) was examined and judged. The MTTF was defined as the time when the resistance value became 10 kΩ or less, and the evaluation when the MTTF was 15.3 hours (hr) or less was evaluated as x. The results are also shown in Table 1. When the coverage of the internal electrode layer was less than 80%, it was considered impossible to measure the capacitance because it was difficult to obtain the capacitance.

According to Table 1, by forming the second alloy portion, the MTTF exceeds the specified time of 15.3 hours and is good, and it can be seen that the higher the Sn concentration, the better. On the other hand, in Test Example 1-1 in which the second alloy portion of Sn was not formed, the MTTF could not exceed the specified time. This confirms that the second alloy portion enhances the reliability of the multilayer ceramic capacitor.

Next, in addition to Test Example 1-1, 18 multilayer ceramic capacitors of Test Examples 1-6 to 1-9 shown in Table 2 were prepared. In Test Example 1-6, Sn as an additive was added to the third dielectric ceramic layer in the same amount as the first dielectric ceramic layer and the second dielectric ceramic layer in Test Example 1-2. In Test Examples 1-7 to 1-9, the amount of Sn added to the third dielectric ceramic layer is gradually increased from Test Example 1-6. In Test Example 1-1, Sn was not added to the third dielectric ceramic layer.

For Test Examples 1-1 and 1-6 to 1-9, MTTF determination was performed in the same manner as in Test Examples 1-1 to 1-5. The results are shown in Table 2.

According to Table 2, by forming the third alloy portion together with the second alloy portion, the MTTF is good exceeding the specified time of 15.3 hours, and the higher the Sn concentration, the better. On the other hand, in Test Example 1-1 in which both the second alloy portion and the third alloy portion of Sn were not formed, the MTTF could not exceed the specified time. This confirms that the second alloy portion and the third alloy portion enhance the reliability of the multilayer ceramic capacitor.

[2] Average particle diameter of dielectric particles contained in near-intersection region FIG. 19 shows a surface including the length (L) direction and the width (W) direction of the multilayer ceramic capacitor 1 of the present invention, which includes the second dielectric ceramic layer 20b and the second internal electrode layer 22. As shown in FIG. 19, both sides in the width (W) direction of the end portion on the first end surface 15 side of the multilayer ceramic capacitor 1 have the second dielectric ceramic layer 20b, the second internal electrode layer 22, and the third dielectric ceramic layers 41 and 42, and have an interface intersection 400 surrounded by them. This intersection point 400 is the intersection point between the interface 2220b between the second dielectric ceramic layer 20b and the second internal electrode layer 22 and the width (W) direction inner surface 401 of the third dielectric ceramic layers 41 and . Similarly, both sides in the width (W) direction of the end on the second end face 16 side also have interface intersection points 400 surrounded by the second dielectric ceramic layer 20b, the first internal electrode layer 21, and the third dielectric ceramic layers 41 and 42.

A region inside a circle 400 r with a radius of 5 μm centered at the intersection point 400 is defined as a second intersection neighborhood region 420 . A region inside a circle 400 r with a radius of 5 μm centered at the intersection 400 is defined as a third intersection neighborhood region 430 . The area inside the circle 400r also includes the line of the circle 400r. In the following description, the second near-intersection region 420 on the side of the second dielectric ceramic layer 20b and the third near-intersection region 430 on the side of the third dielectric ceramic layers 41 and 42 may be collectively referred to as the near-intersection region 440.
A region inside the second intersection vicinity region 420 includes a portion of the second dielectric ceramic layer 20b. A region inside the third intersection neighborhood region 430 includes portions of the third dielectric ceramic layers 41 and 42 .

In the multilayer ceramic capacitor 1 of the present invention,
(A) The average particle diameter of the dielectric particles contained in each intersection neighboring region 440 is smaller than the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a, the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b, and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

(B) Moreover, it is preferable that the ratio of the smallness is 5% or more.

In this case, the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b refers to the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b in the portion other than the second intersection vicinity region 420, and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 refers to the dielectric particles contained in the third dielectric ceramic layers 41 and 42 in the portion other than the third intersection vicinity region 430. refers to the average particle size of

Preferably, the multilayer ceramic capacitor 1 of the present invention having the above configuration (A) or (B) further has any one of the following configurations (C) to (I).

(C) The difference between the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is within 5%, and the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a is equal to the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42. and the average particle diameter of the dielectric particles contained in the intersection neighboring region 440 is smaller than the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

(D) The difference between the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b is within 5%, and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is either the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a or the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b. , and the average particle size of the dielectric particles contained in the intersection vicinity region 440 is smaller than the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 .

(E) The difference between the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is within 5%, and the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b is equal to the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42. The average particle size of the dielectric particles included in the intersection vicinity region 440 is smaller than the average particle size of any of the particle sizes, and the average particle size of the dielectric particles included in the second dielectric ceramic layer 20b is smaller.

(F) the difference between the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b; the difference between the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42; and the average particle diameter of the dielectric particles contained in the dielectric ceramic layers 41 and 42 of No. 3 is within 5%, and the average particle diameter of the dielectric particles contained in the intersection neighboring region 440 is any one of the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a, the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b, and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42. Smaller than the average particle size.

(G) The average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a is smaller than the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b, the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a, and the average particle size of the dielectric particles contained in the intersection neighboring region 440 is smaller than that of the third dielectric ceramic. It is smaller than the average particle size of the dielectric particles contained in layers 41 and 42 .

(H) The average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a is smaller than the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42, the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a, and the average particle size of the dielectric particles contained in the intersection vicinity region 440 is smaller than that of the second dielectric ceramic. It is smaller than the average particle size of the dielectric particles contained in layer 20b.

(I) The average particle diameter of the dielectric particles contained in the intersection vicinity region 440 is smaller than the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a, and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 or the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b is smaller than the average particle diameter of the dielectric particles contained in the intersection vicinity region 440.

The average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42 can be controlled by adjusting the amount of sintering aids such as Si and Mn contained in the dielectric ceramic slurry forming each dielectric ceramic layer, and by adjusting the firing temperature.

As described above, in the multilayer ceramic capacitor 1 of the present invention, the average particle diameter of the dielectric particles contained in the intersection vicinity region 440 is smaller than the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a around the intersection vicinity region 440, the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b, and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

An electric field is likely to concentrate in the region 440 near the intersection, and the electric field concentration may reduce the reliability of the multilayer ceramic capacitor. However, in the multilayer ceramic capacitor 1 of the present invention, the average particle size of the dielectric particles contained in the region 440 near the intersection is smaller than the average particle size of the dielectric particles contained in the surrounding first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42, respectively. Due to such a small average particle size, there are many grain boundaries and electric field concentration is suppressed. As a result, reliability as a multilayer ceramic capacitor can be improved.

[Test Example 2]
Next, in the multilayer ceramic capacitor 1 of the present invention, Test Example 2 for verifying that it is advantageous that the average particle size of the dielectric particles contained in the region 440 near the intersection point is smaller than the average particle size of the dielectric particles contained in each of the first dielectric ceramic layer 20a and the third dielectric ceramic layers 41 and 42 therearound will be described.

The average particle size of dielectric particles contained in each of the first dielectric ceramic layer, the second dielectric ceramic layer and the third dielectric ceramic layer is measured as follows.

(Average particle diameter of dielectric particles contained in the first dielectric ceramic layer)
In the above-described method for manufacturing a laminated ceramic capacitor of the present invention, the first external electrode 51 and the second external electrode 52 are not co-fired, and the green chip 110 is fired without the first external electrode 51 and the second external electrode 52 being fired, and the laminated body 10 is polished from the first end face 15 side or the second end face 16 side, and as shown in FIG.
As shown in FIG. 20, an imaginary line OS1 perpendicular to the width (W) direction is assumed at the central portion in the width (W) direction. Then, along the virtual line OS1, the region in which the first dielectric ceramic layer 20a related to obtaining the capacitance of the polishing body, and the first internal electrode layer 21 and the second internal electrode layer 22 are laminated was divided into three equal parts in the lamination direction into three regions: an upper region F1, a central region F2 and a lower region F3. The first dielectric ceramic layer 20a was imaged with a visual field size of 4.3 μm×3.2 μm for each of the regions F1, F2, and F3, and the area of 20 dielectric particles was measured by image processing for each of the regions F1, F2, and F3. Then, the equivalent circle diameter was calculated from the measured area and the average was taken to obtain the average particle diameter. The average particle size was measured in each of the upper region F1, the central region F2, and the lower region F3, and since no significant difference was found in the measured values, the average particle size of the central region F2 was regarded as the average particle size of the first dielectric ceramic layer.

(Average particle size of dielectric particles contained in the third dielectric ceramic layer)
In the specimen shown in FIG. 20, a virtual line connecting the ends of the plurality of first internal electrode layers 21 and the plurality of second internal electrode layers 22 on the side of the first side surface 13 or the side of the second side surface 14 in the lamination (T) direction is assumed. FIG. 20 shows a virtual line OS3 connecting the ends of the plurality of first internal electrode layers 21 and the plurality of second internal electrode layers 22 on the side of the second side surface 14 in the lamination (T) direction. As shown in FIG. 21, the third dielectric ceramic layer 42 was imaged with a visual field size of 4.3 μm×3.2 μm in a range of 5 μm from the virtual line OS3 toward the third dielectric ceramic layer 42 side, and the area of 20 dielectric particles was measured by image processing for each of the regions F1, F2, and F3. Reference numeral 42F in FIG. 21 indicates an imaging area. Then, the equivalent circle diameter was calculated from the measured area and the average was taken to obtain the average particle diameter. The average particle size was measured in each of the upper region F1, the central region F2, and the lower region F3, and since no significant difference was found in the measured values, the average particle size of the central region F2 was regarded as the average particle size of the third dielectric ceramic layer.

(Average particle diameter of dielectric particles contained in the second dielectric ceramic layer)
The laminated body 10 is polished from the first end surface 15 side or the second end surface 16 side until at least one of the internal electrode layers appears. For example, as shown in FIG. 22, polishing is performed from the second end surface 16 side to the surface J just before the second internal electrode layer 22 appears. As shown in FIG. 23, an imaginary line OS2 perpendicular to the width (W) direction is assumed at the center in the width (W) direction. Then, the second dielectric ceramic layer 20b was divided into three equal parts in the stacking direction along the imaginary line OS2 into three regions, an upper region G1, a central region G2 and a lower region G3. The second dielectric ceramic layer was imaged with a field size of 4.3 μm×3.2 μm for each region G1, G2 and G3, and the area of 20 dielectric particles was measured by image processing for each region G1, G2 and G3. Then, the equivalent circle diameter was calculated from the measured area and the average was taken to obtain the average particle diameter. The average particle size was measured in each of the upper region G1, the central region G2, and the lower region G3, and since no significant difference was found in the measured values, the average particle size of the central region G2 was regarded as the average particle size of the second dielectric ceramic layer.

(Average particle size of dielectric particles contained in the region near the intersection)
In the specimen shown in FIG. 23, a virtual line OS4 connecting the ends of the plurality of first internal electrode layers 21 and the plurality of second internal electrode layers 22 on the side of the second side surface 14 in the lamination (T) direction is assumed. Then, along the virtual line OS4, the regions on both sides of the virtual line OS4 in the width (W) direction, including the region near the intersection 440, were divided into three equal parts in the stacking direction into three regions: an upper region H1, a central region H2, and a lower region H3. As shown in FIG. 24, the second dielectric ceramic layer 20b and the third dielectric ceramic layer 42 were imaged with a visual field size of 4.3 μm×3.2 μm within a range of 5 μm on both sides of the virtual line OS4 in the width (W) direction, and the areas of 20 dielectric particles were measured by image processing for each of the regions F1, F2, and F3. Reference numeral 42H in FIG. 24 indicates an imaging region. Then, the equivalent circle diameter was calculated from the measured area and the average was taken to obtain the average particle diameter. The average particle size was measured in each of the upper region H1, the central region H2, and the lower region H3, and no significant difference was found in the measured values.

Test Examples 2-1 to 2-24 shown in Table 3 were prepared as multilayer ceramic capacitors corresponding to (C) to (I) described above. Further, in Test Examples 2-25 to 2-27, the average particle diameter of the dielectric particles contained in the intersection neighboring region 440 was larger than the average particle diameter of any of the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a, the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b, and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42. For these test examples 2-1 to 2-27, the average particle size was examined by the measurement method described above.

In Table 3, "first" in the average particle size comparison item is the average particle size of the dielectric particles contained in the first dielectric ceramic layer, "second" is the average particle size of the dielectric particles contained in the second dielectric ceramic layer, "third" is the average particle size of the dielectric particles contained in the third dielectric ceramic layer, and "intersection" is the average particle size of the dielectric particles contained in the region near the intersection.

On the other hand, for the multilayer ceramic capacitors of Test Examples 2-25 to 2-27, the resistance value (kΩ) was measured with a voltage of 6.3 V applied in an environment of room temperature 150°, and the MTTF (mean time to failure) was examined and judged. The MTTF was defined as the time when the resistance value became 10 kΩ or less, and the evaluation when the MTTF was 15.3 hours (hr) or less was evaluated as x. The results are also shown in Table 3. When the coverage of the internal electrode layer was less than 80%, it was considered impossible to measure the capacitance because it was difficult to obtain the capacitance.

According to Table 3, it was confirmed that when the average particle size of the dielectric particles contained in the region near the intersection is smaller than the average particle size of the dielectric particles contained in each of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, the MTTF increases and the reliability of the multilayer ceramic capacitor increases.

[3] Manufacturing Method Adding a Step of Removing Sides of the Laminate In the manufacturing method of the laminated ceramic capacitor 1 of the present invention described above, in obtaining the green chip 110 which is the unfired laminate 10, the steps of printing the unfired first internal electrode layers 121 and the second internal electrode layers 122 on the unfired first dielectric ceramic layers 120a, and the steps of printing the unfired first internal electrode layers 121 and the second internal electrode layers 122 on the first dielectric ceramic layers 120a, and the first internal electrode layers 121 and the second internal electrode layers in the first dielectric ceramic layers 120a. forming a green chip 110 by laminating a plurality of first dielectric ceramic layers 120a; cutting the mother block 104; 0a and the second dielectric ceramic layer 120b, and bonding and forming unfired third dielectric ceramic layers (side margin portions 41 and 42) to the first side surface 113 and the second side surface 114 of each green chip 110.
Here, the green chip 110 is an example of a laminate. The first dielectric ceramic layer 120a is an example of a dielectric layer. The first internal electrode layers 121 and the second internal electrode layers 122 are examples of internal electrode patterns. The second dielectric ceramic layer 120b is an example of a dielectric pattern. The first side surface 113 and the second side surface 114 are examples of side surfaces. The side margin portions 41 and 42, which are unfired third dielectric ceramic layers, are an example of dielectric gap layers.

In this manufacturing method, after the step of exposing the first internal electrode layer 121 and the second internal electrode layer 122, the first dielectric ceramic layer 120a, and the second dielectric ceramic layer 120b from the first side surface 113 and the second side surface 114 of the green chip 110 by cutting the mother block 104, the third dielectric ceramic layer is applied to the first side surface 113 and the second side surface 114 of the green chip 110. A removal step for removing a certain amount of thickness from the first side surface 113 and the second side surface 114 can be added before the step of laminating and forming the layers. As a result, the side surfaces of the first dielectric ceramic layer 120a, the second dielectric ceramic layer 120b, the first internal electrode layer 121 and the second internal electrode layer 122 exposed on the first side surface 113 and the second side surface 114 are removed.

FIG. 25 shows a state where the first side surface 113 and the second side surface 114 of the green chip 110 are removed by a certain thickness (for example, 1 μm or less) and flattened. In FIG. 25, the left side shows the state before the removal process, and the right side shows the state after the removal process. When the mother block 104 is cut to obtain a plurality of green chips 110, the first side surface 113 and the second side surface 114 of the green chip 110 may be plastically deformed by the side surface flowing slightly downward as shown in FIG. In addition, the cut surface may not be sufficiently smooth, or foreign matter may be present on the cut surface. Therefore, the thickness is removed to the extent that the deformed portion disappears. Although the means for removing the first side surface 113 and the second side surface 114 in this way is not limited, for example, polishing with an appropriate polishing means is preferable.

As shown in FIG. 26, the first side surface 113 and the second side surface 114 after the removal step are formed as smooth surfaces, and become surfaces from which foreign matter has been removed. A third dielectric ceramic layer (side margin portions 41 and 42) is adhered to the first side surface 113 and the second side surface 114 after this removing step.

In the present invention, each of the second dielectric ceramic layers 20b, the first internal electrode layers 21 and the second internal electrode layers 22 may contain resin. The resin can be included by adding it to the material during manufacture. That is, the dielectric paste of the second dielectric ceramic layer 20b contains a resin, and the conductive paste of the first internal electrode layer 21 and the second internal electrode layer 22 contains a resin.

The resin contained in the dielectric paste and the conductive paste is added for the purpose of functioning as a binder and improving the viscosity of the material. Such resins include, for example, polyvinyl acetal resins such as polyvinyl butyral and polyvinyl acetoacetal; polyvinyl alcohol resins such as polyvinyl alcohol; cellulose resins such as methyl cellulose, ethyl cellulose and cellulose acetate phthalate; (meth) acrylic resins such as (meth) acrylic acid esters; Resins, polyethylene, polypropylene, vinyl resins such as vinyl acetate, rubber resins such as styrene-butadiene rubber, and the like are included, but are not limited to these.

As for the resin content, it is preferable that the content in the second dielectric ceramic layer 20b and the content in the first dielectric ceramic layer 20a are different. The resin content of the first dielectric ceramic layer 20a and the second dielectric ceramic layer 20b is preferably, for example, 30 wt % or more and 50 wt % or less. It is preferable that the resin contents of the first dielectric ceramic layer and the second dielectric ceramic layer 20b are different from each other within this range.

In addition, in the method of manufacturing a laminated ceramic capacitor of the present invention, the thickness of first dielectric ceramic layer 120a is preferably 0.4 μm or more and 0.8 μm or less. Moreover, in the method of manufacturing a laminated ceramic capacitor of the present invention, the thickness of the first internal electrode layers 121 and the second internal electrode layers 122 is preferably 0.4 μm or more and 0.8 μm or less.

Moreover, in forming the green chip 110 , a portion of the second internal electrode layer 122 may overlap a portion of the first internal electrode layer 121 and the second internal electrode layer 122 . Specifically, the ends of the second dielectric ceramic layer 120b and the first internal electrode layer 121 and the second internal electrode layer 122 adjacent to each other in the length (L) direction may overlap each other. For example, as shown in FIG. 27, the ends of the second dielectric ceramic layers 120b may overlap the ends of the first internal electrode layers 121 in the length (L) direction. Similarly, the ends of the second dielectric ceramic layers 120 b may overlap the ends of the second internal electrode layers 122 . In such a mode in which the ends in the length (L) direction overlap, the ends of the first internal electrode layers 121 and the ends of the second dielectric ceramic layers 120b may overlap on the ends of the second dielectric ceramic layers 120b.

In the manufacturing method of the multilayer ceramic capacitor of the present invention, the first side surface 113 and the second side surface 114 of the green chip 110, which is the unfired multilayer body 10, are removed by a certain thickness, and then the unfired third dielectric ceramic layer is attached to the first side surface 113 and the second side surface 114. Thereby, the unfired third dielectric ceramic layer can be formed in a smooth and clean state on the first side surface 113 and the second side surface 114 .

In the manufacturing method of the multilayer ceramic capacitor of the present invention, by removing the first side surface 113 and the second side surface 114 by polishing, the first side surface 113 and the second side surface 114 can be easily and accurately removed with a predetermined thickness.

In the method of manufacturing a laminated ceramic capacitor of the present invention, the second dielectric ceramic layers 120b contain resin, and the amount of resin is preferably greater than the amount of resin contained in the first internal electrode layers 121 and the second internal electrode layers 122. As a result, the viscosity of the second dielectric ceramic layer 120b is relatively increased, and problems such as cracking and chipping of the cut surface of the second dielectric ceramic layer 20b when the mother block 104 is cut can be suppressed.

In addition, in the method of manufacturing a laminated ceramic capacitor of the present invention, the thickness of first dielectric ceramic layer 120a is preferably 0.4 μm or more and 0.8 μm or less. Moreover, in the method of manufacturing a laminated ceramic capacitor of the present invention, the thickness of the first internal electrode layers 121 and the second internal electrode layers 122 is preferably 0.4 μm or more and 0.8 μm or less. Since the unfired dielectric layers and internal electrode layers have such thicknesses, the first dielectric ceramic layer 20a, the first internal electrode layer 21, and the second internal electrode layer 22 after firing can be formed to have appropriate thicknesses.

Further, in the method of manufacturing a laminated ceramic capacitor of the present invention, part of the second internal electrode layers 122 may overlap the first internal electrode layers 121 and the second internal electrode layers 122 . As a result, after firing, the second dielectric ceramic layer 20b can be arranged with a sufficient thickness without gaps.

[4] Missing portion of second dielectric ceramic layer As shown in Figs. 28 and 29, the multilayer ceramic capacitor 1 of the present invention has a missing portion 520 in which a part of the second dielectric ceramic layer 20b is missing between at least one second dielectric ceramic layer 20b and one third dielectric ceramic layer 42. Similarly, between at least one second dielectric ceramic layer 20b and the other third dielectric ceramic layer 41, there is a missing portion 520 in which a part of the second dielectric ceramic layer 20b is missing.

The region where the second dielectric ceramic layer 20b is arranged, that is, between the end portion of the first internal electrode layer 21 not connected to the second external electrode 52 and the second external electrode 52 in the length (L) direction of the laminate 10, and between the end portion of the second internal electrode layer 22 not connected to the first external electrode 51 and the first external electrode 51, at least one of the regions in the stacking (T) direction and width. In the plane including the (W) direction, the position in the lamination (T) direction is between the first dielectric ceramic layers 20a, and the position in the width (W) direction is between the second dielectric ceramic layer 20b and the third dielectric ceramic layer 41 or 42.

When the green chip 110, which is the unfired laminate 10, is produced, the side surface of the unfired second dielectric ceramic layer 120b is processed and then fired to obtain the laminate 10 having the defect portion 520 on the side surface of the second dielectric ceramic layer 20b. Any processing method can be used to obtain the cutout portion 520, and for example, the cutout portion 520 can be formed by boring with an appropriate tool.

In addition, in the above-described "manufacturing method in which a step of removing the side surface of the laminate" is added, when the first side surface 113 or the second side surface 114 of the unfired green chip 110 is removed by means such as polishing, a part of the side surface of the second dielectric ceramic layer 20b may be missing and a minute hole may be formed. If such a hole occurs, it is also possible to use the hole as the missing portion 520 . The cutout portion 520 may not be formed on all the side surfaces of the second internal electrode layer 22, and one or more cutout portions 520 may be formed on each of the first side surface 13 side and the second side surface 14 side at both ends in the length (L) direction.

In addition, as shown in FIGS. 28 and 29 , Si segregation 530 may be arranged in the defect portion 520 . Si segregation 530 is segregation of Si added as an additive to the second dielectric ceramic layer 20b.

The size of the Si segregation 530 is preferably larger than 1/3 of the thickness of the second dielectric ceramic layer 20b in terms of equivalent circle diameter. Moreover, it may be 100 nm or more and 600 nm or less.

It is preferable that the cutout portion 520 is arranged close to the first internal electrode layer 21 or the second internal electrode layer 22 . In FIG. 29, the missing portion 520 is arranged close to the end portion of the second internal electrode layer 22 in the length (L) direction. Similarly, it is preferable that the cutout portion 520 is arranged close to the end portion of the first internal electrode layer 21 in the length (L) direction.

The dimension of the Si segregation 530 is preferably 0.1% or more and 5% or less of the dimension of the third dielectric ceramic layers 41 and 42 in the width (W) direction.

In the laminated ceramic capacitor 1 of the present invention, the region where the second dielectric ceramic layer 20b is arranged, that is, in the length (L) direction of the laminated body 10, between the second external electrode 52 and the end of the first internal electrode layer 21 and the second external electrode 52, and between the end of the second internal electrode layer 22 not connected to the first external electrode 51 and the first external electrode 51. In at least one of the regions, the stacking (T) direction and width (W) In the plane including the direction, the position in the lamination (T) direction is between the first dielectric ceramic layers 20a, and the position in the width (W) direction is between the second dielectric ceramic layer 20b and the third dielectric ceramic layers 41 and 42. There is a missing portion 520.

Thereby, the stress generated in the second dielectric ceramic layer 20b during firing can be relieved by the defect portion 520. FIG. As a result, it is possible to prevent the second dielectric ceramic layer 20b from being cracked or chipped.

In the multilayer ceramic capacitor 1 of the present invention, Si segregation 530 may be arranged in the defect portion 520 . When the segregation 530 exists in the defect portion 520, the segregation 530 suppresses the intrusion of moisture. The presence of the segregation 530 in the cutout portion 520 improves the moisture resistance of the multilayer ceramic capacitor 1 . The segregation 530 may exist in the entire defect portion 520 or may exist in a part of the defect portion 520 . It is possible to suppress cracking or chipping of the second dielectric ceramic layer 20b due to the defect portion 520 where the segregation 530 exists, and the moisture resistance of the multilayer ceramic capacitor 1 can be improved.

In the multilayer ceramic capacitor 1 of the present invention, the Si segregation 530 is ⅓ or more (or less than) the thickness of the second dielectric ceramic layer 20b.

In the multilayer ceramic capacitor 1 of the present invention, the missing portion 520 is arranged close to the first internal electrode layer 21 and the second internal electrode layer 22 . A region adjacent to the first internal electrode layer 21 and the second internal electrode layer 22 has a relatively large stress generated during firing, but the stress is relieved by the defect portion 520, so cracking and chipping can be effectively suppressed.

In the laminated ceramic capacitor 1 of the present invention, the dimension of the Si segregation 530 in the width direction is preferably 0.1% or more and 5% or less of the dimension of the third dielectric ceramic layers 41 and 42 . When the segregation 530 of Si exists in the chipped portion 520, cracking and chipping can be effectively suppressed, and the moisture resistance of the multilayer ceramic capacitor 1 can be improved.

[5] Segregation Formed at the End of the Second Dielectric Ceramic Layer on the Internal Electrode Layer Side As shown in FIG. 30, in the multilayer ceramic capacitor 1 of the present invention, the first segregation 610 may exist at the end of the first internal electrode layer 21 in the length (L) direction that is not connected to the second external electrode 52. In addition, the first segregation 610 may be present at the ends of the second internal electrode layers 22 in the length (L) direction that are not connected to the first external electrodes 51 .

As shown in FIG. 31, the first segregation 610 is produced by layered segregation of the metal element 610a derived from the second dielectric ceramic layer 20b. At least one of Mg, Mn, and Si can be used as the metal element 610a, for example. The segregation 610 due to the metal element 610a is caused by the metal element contained in the second dielectric ceramic layer 20b moving to the first internal electrode layer 21 and the second internal electrode layer 22 during firing of the second dielectric ceramic layer 20b.

On the other hand, as shown in FIG. 32, second segregation 620 may exist at the end of the first internal electrode layer 21 in the width (W) direction. Also, the second segregation 620 may exist at the end of the second internal electrode layer 22 in the width (W) direction.

The second segregation 620 is produced by segregation of metal elements 620a derived from the third dielectric ceramic layers 41 and 42 in contact with the first internal electrode layer 21 and the second internal electrode layer 22 into layers. The metal element 620a is, for example, the same as the first segregation 610 and includes at least one of Mg, Mn, and Si. The segregation 620 due to the metal element 620a is caused by the metal element contained in the third dielectric ceramic layers 41 and 42 moving to the first internal electrode layer 21 and the second internal electrode layer 22 during firing of the third dielectric ceramic layers 41 and 42.

In the laminated ceramic capacitor 1 of the present invention, the first segregation 610 segregated in the first internal electrode layer 21, the first segregation 610 segregated in the second internal electrode layer 22, the second segregation 620 segregated in the first internal electrode layer 21, and the second segregation 620 segregated in the second internal electrode layer 22, the metal element contained in at least one set of these segregations is the metal contained in the other segregation. It is preferably different from the elements.

When the first dielectric ceramic layer 20a contains BaTiO ₃ as the main component, the content of the metal element contained in the first segregation 610 in the first internal electrode layers 21 and the second internal electrode layers 22 is 0.3 mol% or more with respect to 100 mol of Ti. Similarly, the content of the metal element contained in the second segregation 620 in the first internal electrode layer 21 and the second internal electrode layer 22 is 0.3 mol % or more with respect to 100 mol of Ti.

In the present invention, the region where the first segregation 610 exists in the first internal electrode layer 21 preferably has a length of 0.1 μm or more along the length (L) direction. Moreover, the region in which the first segregation 610 exists in the second internal electrode layer 22 preferably has a length of 0.1 μm or more along the length (L) direction. Moreover, the region where the second segregation 620 exists in the first internal electrode layer 21 preferably has a length of 0.1 μm or more along the width (W) direction. Moreover, the region in which the second segregation 620 exists in the second internal electrode layer 22 preferably has a length of 0.1 μm or more along the width (W) direction. By having these lengths, it is possible to reliably obtain the effect of suppressing electric field concentration by segregation and improving reliability.

Regarding the length of the first segregation 610 and the second segregation 620, if the length is less than the above length, it becomes difficult to suppress the electric field concentration. In addition, when the first segregation 610 exceeds 0.5% in the length (L) direction, and the second segregation 620 exceeds 1.0% in the width (W) direction, the segregating metal element (at least one of Mg, Mn, and Si) becomes excessive, and the function of storing electric charges in the internal electrode layers deteriorates.

The length in the length (L) direction of the first segregation 610 is contained in the second dielectric ceramic layer 20b, and can be controlled by adjusting the content of the metal element 610a that migrates to the first internal electrode layer 21 and the second internal electrode layer 22 and segregates. In addition, the length of the second segregation 620 in the width (W) direction can be controlled by adjusting the content of the metal element 620a that is included in the third dielectric ceramic layers 41 and 42 and migrates to the first internal electrode layer 21 and the second internal electrode layer 22 to segregate.

In the laminated ceramic capacitor 1 of the present invention, first segregation 610 of at least one metal element selected from among Mg, Mn, and Si is present at each of the length (L)-direction ends of the first internal electrode layers 21 that are not connected to the second external electrodes 52 and the length (L)-direction ends of the second internal electrode layers 22 that are not connected to the first external electrodes 51.

An electric field tends to concentrate at the ends in the length (L) direction of each of the first internal electrode layers 21 and the second internal electrode layers 22 that are in contact with the second dielectric ceramic layer 20b, and the electric field concentration may reduce the reliability of the multilayer ceramic capacitor. However, in the multilayer ceramic capacitor 1 of the present invention, the electric field concentration is suppressed by the first segregation 610, and reliability can be improved.

In the multilayer ceramic capacitor 1 of the present invention, second segregation 620 of at least one metal element selected from among Mg, Mn, and Si exists at each of the width (W) direction end portions of the first internal electrode layers 21 and the width (W) direction end portions of the second internal electrode layers 22.

An electric field tends to concentrate at the ends in the width (W) direction of the first internal electrode layer 21 and the second internal electrode layer 22, which are in contact with the third dielectric ceramic layers 41 and 42, and the electric field concentration may reduce the reliability of the multilayer ceramic capacitor. However, in the multilayer ceramic capacitor 1 of the present invention, the electric field concentration is suppressed by the second segregation 620, so reliability can be improved.

In the laminated ceramic capacitor 1 of the present invention, the first segregation 610 segregated in the first internal electrode layer 21, the first segregation 610 segregated in the second internal electrode layer 22, the second segregation 620 segregated in the first internal electrode layer 21, and the second segregation 620 segregated in the second internal electrode layer 22, the metal element contained in at least one set of these segregations is the metal contained in the other segregation. Different from the elements.

As a result, the optimum metal element can be arranged according to the locations where the first segregation 610 and the second segregation 620 are arranged, and the reliability can be improved.

In the multilayer ceramic capacitor 1 of the present invention, the first dielectric ceramic layer 20a contains Ba and Ti, and the content of the metal element 610a contained in the first segregation 610 and the metal element 620a contained in the second segregation 620 is 0.3 mol% or more with respect to 100 mol of Ti.

Thereby, the electric field concentration described above can be effectively suppressed, and the reliability can be further improved.

In the laminated ceramic capacitor 1 of the present invention, the region where the first segregation 610 exists in the first internal electrode layer 21 is 0.3 μm or more in the length (L) direction, the region where the first segregation 610 exists in the second internal electrode layer 22 is 0.3 μm or more in the length (L) direction, and the region where the second segregation 620 exists in the first segregation 610 is 0.3 μm or more in the width (W) direction. Preferably, the region where the second segregation 620 exists in the second segregation 620 is 0.3 μm or more in the width (W) direction.

As a result, the effect of suppressing electric field concentration by segregation and improving reliability can be reliably obtained.

[Test Example 3]
Next, Test Example 3 for verifying the effects of the first segregation 610 and the second segregation 620 in the multilayer ceramic capacitor 1 of the present invention will be described.

As shown in Table 4, test examples 3-1 to 3-18 of multilayer ceramic capacitors provided with a second dielectric ceramic layer 20b containing one of the elements Mg, Mn, and Si, and third dielectric ceramic layers 41 and 42 were prepared. Then, for each test example, the concentration of the first segregation element generated at the ends in the length (L) direction of the first internal electrode layer 21 and the second internal electrode layer 22, the length in the length (L) direction, and the length in the width (W) direction were examined. The concentrations of the metal elements in the first segregation and the second segregation were investigated using the same method as the concentration of the second alloy portion and the concentration of the third alloy portion in "Test Example 1" described above. Also, the length of each of the first segregation and the second segregation was measured by EDX analysis.

The multilayer ceramic capacitors of Test Examples 3-1 to 3-18 were heated in an environment at a temperature of 150° C. for 1 hour, cooled to room temperature, and then measured with a voltage of 6.3 V to measure the resistance value (kΩ), and the MTTF (mean time to failure) was examined. In addition, the presence or absence of a decrease in capacitance was examined using an LCR meter (manufactured by Keysight: E4980).
If the decrease in capacitance is 3% or more or the MTTF is 15.3 hr or less, it is x, and the case where the decrease in capacitance is less than 3% and the MTTF exceeds 15.3 hr and is 30 hours or less is determined as ◯ (good). The results are also shown in Table 4.

By incorporating Mg, Mn, and Si into the second dielectric layer to create segregation portions at the ends in the length direction and width direction of the internal electrodes, it is possible to eliminate factors that reduce reliability that tend to occur at the ends. However, if the content is too high, the area of the internal electrode that functions as a metal is narrowed, resulting in a decrease in capacitance.

[6] Segregation formed in the corner region of the second dielectric ceramic layer on the internal electrode layer side When the above-described first segregation 610 and second segregation 620 are present, as shown in FIG. A third segregation 630 is present in each of the first corner region 710 and the second corner region 720 .

The first corner region 710 is a region where the length (L) direction of the first segregation 610 and the width (W) direction of the second segregation 620 overlap in the first internal electrode layer 21 . The second corner region 720 is a region where the length (L) direction in which the first segregation 610 exists and the width (W) direction of the second segregation 620 in the second internal electrode layer 22 overlap. The third segregation 630 results from the segregation of the metal element 610a of the first segregation 610 and the metal element 620a of the second segregation 620 .

In the present invention, the metal element 610a contained in the first segregation 610 and the metal element 620a contained in the second segregation 620 are different from each other, and the metal element 630a in the third segregation 630 preferably contains both the metal element 610a contained in the first segregation 610 and the metal element 620a contained in the second segregation 620.

In the present invention, it is preferable that the region where the first segregation 610 exists is 0.1 μm or more in the length (L) direction, and the region where the second segregation 620 exists is 0.1 μm or more in the width (W) direction.

FIG. 33 shows planes including the length (L) direction and the width (W) direction in the multilayer ceramic capacitor 1 of the present invention. The third segregation 630 is preferably segregated in a substantially right-angled triangular shape so that the existing area increases toward the ends in the length (L) direction in the plane including the length (L) direction and the width (W) direction. Part or all of the third segregation 630 is included in the intersection neighborhood region 440 in FIG.

Further, in the laminated ceramic capacitor 1 of the present invention, the second dielectric ceramic layer 20b is preferably arranged such that a part of the second dielectric ceramic layer 20b overlaps the existing region of the third segregation 630 in the stacking (T) direction with respect to the first internal electrode layer 21 and the second internal electrode layer 22. Specifically, as shown in FIG. 34, in the length (L) direction, the end of the second dielectric ceramic layer 120b overlaps the end of the second internal electrode layer 22 in the region containing the third segregation 630. Similarly, the ends of the second dielectric ceramic layers 20 b may overlap the ends of the first internal electrode layers 21 . In such a mode in which the ends in the length (L) direction overlap, the ends of the first internal electrode layers 121 or the ends of the second dielectric ceramic layers 120b may overlap the ends of the second dielectric ceramic layers 20b.

In the laminated ceramic capacitor 1 of the present invention, the first segregation 610 of at least one metal element selected from among Mg, Mn, and Si is present at each of the ends of the first internal electrode layers 21 in the length (L) direction that are not connected to the second external electrodes 52 and the ends of the second internal electrode layers 22 in the length (L) direction that are not connected to the first external electrodes 51 . A second segregation 620 of at least one metal element selected from among Mg, Mn, and Si exists at each of the end portion and the end portion in the width (W) direction of the second internal electrode layer 22. In the first internal electrode layer 21, the end portion in the length (L) direction where the first segregation 610 exists and the width (W) direction where the second segregation 620 exists overlap the first corner region 710 and the second corner region 710. In each of the second corner regions 720 where the end portion in the length (L) direction where the first segregation 610 exists overlaps with the width (W) direction where the second segregation 620 exists in the internal electrode layer 22, the third segregation 630 by the respective metal elements of the first segregation 610 and the second segregation 620 exists.

An electric field tends to concentrate in the first corner region 710 and the second corner region 720, and the electric field concentration may reduce the reliability of the multilayer ceramic capacitor. However, in the multilayer ceramic capacitor 1 of the present invention, the third segregation 630 suppresses the electric field concentration on the first corner region 710 and the second corner region 720, so reliability can be improved.

In the multilayer ceramic capacitor 1 of the present invention, the metal element 610a contained in the first segregation 610 and the metal element 620a contained in the second segregation 620 are different from each other, and the metal element contained in the third segregation 630 contains both the metal element 610a contained in the first segregation 610 and the metal element 620a contained in the second segregation 620.

As a result, the third segregation 630 suppresses electric field concentration on the first corner region 710 and the second corner region 720, thereby improving reliability.

In addition, in the third segregation 630, Mg is preferable as the metal element arranged on the side close to the third dielectric ceramic layers 41 and . On the other hand, in the third segregation 630, Si is preferable as the metal element arranged on the side close to the second dielectric ceramic layer 20b from the viewpoint of improving the moisture resistance. Therefore, both Mg and Si are preferably segregated in the first corner region 710 and the second corner region 720 . In addition, short recovery may occur due to the first segregation 610 at the ends in the width (W) direction of the first internal electrode layers 21 and the second internal electrode layers 22 . Moreover, it is more preferable that Sn is dissolved in the first internal electrode layers 21 and the second internal electrode layers 22 .

In the multilayer ceramic capacitor 1 of the present invention, the region where the first segregation 610 exists is 0.1 μm or more in the length (L) direction, and the region where the second segregation 620 exists is 0.1 μm or more in the width (W) direction. As a result, the effect of suppressing electric field concentration by segregation and improving reliability can be reliably obtained.

In the multilayer ceramic capacitor 1 of the present invention, the third segregation 630 exists in a larger area toward the ends in the length (L) direction in the plane including the length (L) direction and the width (W) direction.

As a result, the area of the third segregation 630 increases at the end portion in the length (L) direction of the second dielectric ceramic layer 20b where electric field concentration tends to occur, and the electric field concentration by the third segregation 630 is more effectively suppressed, and reliability can be further improved.

In the laminated ceramic capacitor 1 of the present invention, the second dielectric ceramic layer 20b is partly arranged in the lamination (T) direction with respect to the first internal electrode layer 21 and the second internal electrode layer 22 so as to overlap the existing region of the segregation 630.

As a result, the third segregation 630 is formed in a plane including the length (L) direction and the width (W) direction such that the existence area thereof increases toward the ends in the length (L) direction.

[Test Example 4]
Next, Test Example 4 for verifying the effect of the third segregation 630 in the multilayer ceramic capacitor 1 of the present invention will be described.

As shown in Table 5, Test Examples 4-1 to 4-18 were prepared for multilayer ceramic capacitors having a second dielectric ceramic layer containing one of the metallic elements Mg, Mn, and Si, and a third dielectric ceramic layer containing one of Mg, Mn, and Si. Then, the concentration of the metal element contained in the third segregation generated in the first corner region and the second corner region of each multilayer ceramic capacitor, the length in the length (L) direction, and the length in the width (W) direction were examined. The concentration of the metal element in the third segregation was investigated using the same method as the concentration of the second alloy portion and the concentration of the third alloy portion in "Test Example 1" described above. Also, the length of each of the third segregations was measured by EDX analysis.

For the multilayer ceramic capacitors of Test Examples 4-1 to 4-14, the resistance value (kΩ) was measured with a voltage of 6.3 V applied at room temperature of 150° C., and the MTTF (mean time to failure) was investigated and judged. The MTTF was defined as the time when the resistance value became 10 kΩ or less, and the evaluation when the MTTF was 15.3 hours (hr) or less was evaluated as x. The results are also shown in Table 5. In addition, the presence or absence of a decrease in capacitance was examined with an LCR meter (manufactured by Keysight: E4980), and those showing a decrease in capacitance of 3% or more were evaluated as x. When the coverage of the internal electrode layer was less than 80%, it was difficult to obtain the capacitance, so the measurement was not possible.

By including Si, Mg, and Mn in the second ceramic dielectric layer and the third ceramic dielectric layer, many segregation regions can be created at the corners. In particular, electric field concentration occurs at the corners, which tends to lower the reliability. However, if the content is too high, the area of the internal electrode that functions as a metal is narrowed, resulting in a decrease in capacitance.

[7] Thickness of Second Dielectric Ceramic Layer FIG. 35 schematically shows a WT cross section at the central portion in the length (L) direction of the laminated body 10 in the laminated ceramic capacitor 1 of the present invention.

Also, FIG. 36 shows a part of the LT cross section of the multilayer ceramic capacitor 1 of the present invention, where T3 is the thickness of the second dielectric ceramic layer 20b. Although FIG. 36 shows the second dielectric ceramic layer 20b in contact with the second internal electrode layer 22, the thickness of the second dielectric ceramic layer 20b in contact with the first internal electrode layer 21 is also assumed to be T3. In other words, the thickness T3 of the second dielectric ceramic layer 20b is the thickness between the end of the first internal electrode layer 21 in the length (L) direction that is not connected to the second external electrode 52 and the second external electrode 52, and the thickness between the end of the second internal electrode layer 22 in the length (L) direction that is not connected to the first external electrode 51 and the second external electrode 52.

In the present invention, the difference in thickness between T1 and T2 is relatively small, within 10% of T1. On the other hand, the thickness of T3 is preferably greater than T1 and T2, and the difference therebetween is 10% or more of T1 and T2.

The means for making the thickness T3 of the second dielectric ceramic layer 20b larger than the thicknesses T1 and T2 of the first dielectric ceramic layer 20a is not limited as described above. This can be achieved by setting the green chip 110 in a state where it is placed in a state where the green chip 110 is formed, and then firing the green chip 110 .

Of T1, T2 and T3, the thickness T1 of the central portion of the first dielectric ceramic layer 20a is preferably 0.7 μm or less. Also, the thickness T3 of the second dielectric ceramic layer 20b is preferably 0.4 μm or more.

In the multilayer ceramic capacitor 1 of the present invention, T1 is the thickness of the first dielectric ceramic layer 20a at the central portion in the lamination (T) direction in a plane including the central portion in the length (L) direction, the lamination (T) direction, and the width (W) direction, T2 is the thickness of the end portion in the width (W) direction of the first dielectric ceramic layer 20a, the length (L) direction end portion of the first internal electrode layer 21 not connected to the second external electrode 52, and the second and between the first external electrode 51 and the end portion of the second internal electrode layer 22 in the length (L) direction that is not connected to the first external electrode 51 and the first external electrode 51, the difference in thickness between T1 and T2 is within 10% of T1, the thickness of T3 is greater than T1 and T2, and the difference is 10% or more of T1 and T2.

As a result, the second dielectric ceramic layer 20b arranged for eliminating the step between the first dielectric ceramic layers 20a sandwiching the first internal electrode layer 21 and the second internal electrode layer 22 has a sufficient element thickness, and as a result, the reliability can be improved.

1 Multilayer Ceramic Capacitor 10 Laminate 11 First Main Surface of Laminate 12 Second Main Surface of Laminate 13 First Side of Laminate 14 Second Side of Laminate 15 First End Face of Laminate 16 Second End Face of Laminate 20 Dielectric Ceramic Layer 20a First Dielectric Ceramic Layer 20b Second Dielectric Ceramic Layer 21 First Internal Electrode Layer 22 Second Inside Electrode layer 30 inner layer portions 31, 32 outer layer portions 41, 42 third dielectric ceramic layer 51 first external electrode 52 second external electrode 400 intersection 440 intersection vicinity region

Claims (9)

a laminate including dielectric ceramic layers and internal electrode layers laminated in a lamination direction;
A multilayer ceramic capacitor comprising: an external electrode connected to the internal electrode layer,
The laminate has a first main surface and a second main surface facing each other in the lamination direction, a first side surface and a second side surface facing each other in a width direction perpendicular to the lamination direction, and a first end face and a second end face facing each other in a length direction perpendicular to the lamination direction and the width direction,
The internal electrode layers include a first internal electrode layer drawn out to the first end face and a second internal electrode layer drawn out to the second end face so as to face the first internal electrode layer via the dielectric ceramic layer,
the external electrodes are arranged on the first end face and connected to the first internal electrode layer; and arranged on the second end face and connected to the second internal electrode layer;
the dielectric ceramic layer comprises a first dielectric ceramic layer and a second dielectric ceramic layer,
The first dielectric ceramic layer is arranged between the first internal electrode layer and the second internal electrode layer,
The second dielectric ceramic layer includes a region where the internal electrode layer is not arranged between the first dielectric ceramic layers facing each other with the internal electrode layer interposed therebetween, and a part of the region overlaps the first dielectric ceramic layer in the stacking direction,
The laminate includes: an inner layer portion in which the first internal electrode layers and the second internal electrode layers are alternately laminated with the dielectric ceramic layers interposed therebetween; an outer layer portion disposed so as to sandwich the inner layer portion in the stacking direction and made of a ceramic material; and a third dielectric ceramic layer disposed so as to sandwich the inner layer portion and the outer layer portion in the width direction and made of a dielectric ceramic material;
In a plane including the length direction and the width direction, an interface intersection is formed by the second dielectric ceramic layer, the first internal electrode layer or the second internal electrode layer, and the third dielectric ceramic layer,
the second dielectric ceramic layer and the third dielectric ceramic layer each include an intersection vicinity region near the intersection;
The average particle diameter of the dielectric particles contained in the near-intersection region is smaller than the average particle diameter of any one of the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer, the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer, and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layer. 2. The multilayer ceramic capacitor according to claim 1, wherein the average particle diameter of the dielectric particles contained in the near-intersection region is 5% or more smaller than the average particle diameter of any one of the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer, the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer, and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layer. The difference between the average particle size of the dielectric particles contained in the second dielectric ceramic layer and the average particle size of the dielectric particles contained in the third dielectric ceramic layer is within 5%,
The average particle size of the dielectric particles contained in the first dielectric ceramic layer is larger than the average particle size of either the average particle size of the dielectric particles contained in the second dielectric ceramic layer or the average particle size of the dielectric particles contained in the third dielectric ceramic layer,
3. The multilayer ceramic capacitor according to claim 1, wherein the average particle size of the dielectric particles contained in the near-intersection region is smaller than the average particle size of both the average particle size of the dielectric particles contained in the second dielectric ceramic layer and the average particle size of the dielectric particles contained in the third dielectric ceramic layer. The difference between the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer and the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer is within 5%,
The average particle size of the dielectric particles contained in the third dielectric ceramic layer is smaller than either the average particle size of the dielectric particles contained in the first dielectric ceramic layer or the average particle size of the dielectric particles contained in the second dielectric ceramic layer,
3. The multilayer ceramic capacitor according to claim 1, wherein an average particle size of dielectric particles contained in said intersection vicinity region is smaller than an average particle size of dielectric particles contained in said third dielectric ceramic layer. The difference between the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layer is within 5%,
The average particle diameter of the dielectric particles contained in the second dielectric ceramic layer is smaller than the average particle diameter of either the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer or the average particle diameter of the dielectric particles contained in the third dielectric ceramic layer,
3. The multilayer ceramic capacitor according to claim 1, wherein an average particle size of dielectric particles contained in said intersection vicinity region is smaller than an average particle size of dielectric particles contained in said second dielectric ceramic layer. The difference between the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer and the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer, the difference between the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layer, the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer, and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layer. Both the difference from the diameter is within 5%,
3. The multilayer ceramic capacitor according to claim 1, wherein the average particle diameter of the dielectric particles contained in the near-intersection region is smaller than any one of the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer, the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer, and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layer. The average particle size of the dielectric particles contained in the first dielectric ceramic layer is smaller than the average particle size of the dielectric particles contained in the second dielectric ceramic layer,
The average particle size of the dielectric particles contained in the third dielectric ceramic layer is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer,
3. The multilayer ceramic capacitor according to claim 1, wherein an average particle size of dielectric particles contained in said intersection vicinity region is smaller than an average particle size of dielectric particles contained in said third dielectric ceramic layer. The average particle size of the dielectric particles contained in the first dielectric ceramic layer is smaller than the average particle size of the dielectric particles contained in the third dielectric ceramic layer,
The average particle size of the dielectric particles contained in the second dielectric ceramic layer is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer,
3. The multilayer ceramic capacitor according to claim 1, wherein an average particle size of dielectric particles contained in said intersection vicinity region is smaller than an average particle size of dielectric particles contained in said second dielectric ceramic layer. The average particle size of the dielectric particles contained in the near-intersection region is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer,
3. The multilayer ceramic capacitor according to claim 1, wherein the average particle diameter of the dielectric particles contained in the third dielectric ceramic layer or the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer is smaller than the average particle diameter of the dielectric particles contained in the near-intersection region.

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